Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Cryptographic API.
4 *
5 * Support for OMAP AES HW ACCELERATOR defines
6 *
7 * Copyright (c) 2015 Texas Instruments Incorporated
8 */
9#ifndef __OMAP_AES_H__
10#define __OMAP_AES_H__
11
12#include <crypto/aes.h>
13
14#define DST_MAXBURST 4
15#define DMA_MIN (DST_MAXBURST * sizeof(u32))
16
17#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
18
19/*
20 * OMAP TRM gives bitfields as start:end, where start is the higher bit
21 * number. For example 7:0
22 */
23#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
24#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
25
26#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
27 (((x) ^ 0x01) * 0x04))
28#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
29
30#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
31#define AES_REG_CTRL_CONTEXT_READY BIT(31)
32#define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7)
33#define AES_REG_CTRL_CTR_WIDTH_32 0
34#define AES_REG_CTRL_CTR_WIDTH_64 BIT(7)
35#define AES_REG_CTRL_CTR_WIDTH_96 BIT(8)
36#define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7)
37#define AES_REG_CTRL_GCM GENMASK(17, 16)
38#define AES_REG_CTRL_CTR BIT(6)
39#define AES_REG_CTRL_CBC BIT(5)
40#define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3)
41#define AES_REG_CTRL_DIRECTION BIT(2)
42#define AES_REG_CTRL_INPUT_READY BIT(1)
43#define AES_REG_CTRL_OUTPUT_READY BIT(0)
44#define AES_REG_CTRL_MASK GENMASK(24, 2)
45
46#define AES_REG_C_LEN_0 0x54
47#define AES_REG_C_LEN_1 0x58
48#define AES_REG_A_LEN 0x5C
49
50#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
51#define AES_REG_TAG_N(dd, x) (0x70 + ((x) * 0x04))
52
53#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
54
55#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
56#define AES_REG_MASK_SIDLE BIT(6)
57#define AES_REG_MASK_START BIT(5)
58#define AES_REG_MASK_DMA_OUT_EN BIT(3)
59#define AES_REG_MASK_DMA_IN_EN BIT(2)
60#define AES_REG_MASK_SOFTRESET BIT(1)
61#define AES_REG_AUTOIDLE BIT(0)
62
63#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
64
65#define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
66#define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
67#define AES_REG_IRQ_DATA_IN BIT(1)
68#define AES_REG_IRQ_DATA_OUT BIT(2)
69#define DEFAULT_TIMEOUT (5 * HZ)
70
71#define DEFAULT_AUTOSUSPEND_DELAY 1000
72
73#define FLAGS_MODE_MASK 0x001f
74#define FLAGS_ENCRYPT BIT(0)
75#define FLAGS_CBC BIT(1)
76#define FLAGS_CTR BIT(2)
77#define FLAGS_GCM BIT(3)
78#define FLAGS_RFC4106_GCM BIT(4)
79
80#define FLAGS_INIT BIT(5)
81#define FLAGS_FAST BIT(6)
82
83#define FLAGS_IN_DATA_ST_SHIFT 8
84#define FLAGS_OUT_DATA_ST_SHIFT 10
85#define FLAGS_ASSOC_DATA_ST_SHIFT 12
86
87#define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2)
88
89struct omap_aes_gcm_result {
90 struct completion completion;
91 int err;
92};
93
94struct omap_aes_ctx {
95 int keylen;
96 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
97 u8 nonce[4];
98 struct crypto_skcipher *fallback;
99};
100
101struct omap_aes_gcm_ctx {
102 struct omap_aes_ctx octx;
103 struct crypto_aes_ctx actx;
104};
105
106struct omap_aes_reqctx {
107 struct omap_aes_dev *dd;
108 unsigned long mode;
109 u8 iv[AES_BLOCK_SIZE];
110 u32 auth_tag[AES_BLOCK_SIZE / sizeof(u32)];
111 struct skcipher_request fallback_req; // keep at the end
112};
113
114#define OMAP_AES_QUEUE_LENGTH 1
115#define OMAP_AES_CACHE_SIZE 0
116
117struct omap_aes_algs_info {
118 struct skcipher_engine_alg *algs_list;
119 unsigned int size;
120 unsigned int registered;
121};
122
123struct omap_aes_aead_algs {
124 struct aead_engine_alg *algs_list;
125 unsigned int size;
126 unsigned int registered;
127};
128
129struct omap_aes_pdata {
130 struct omap_aes_algs_info *algs_info;
131 unsigned int algs_info_size;
132 struct omap_aes_aead_algs *aead_algs_info;
133
134 void (*trigger)(struct omap_aes_dev *dd, int length);
135
136 u32 key_ofs;
137 u32 iv_ofs;
138 u32 ctrl_ofs;
139 u32 data_ofs;
140 u32 rev_ofs;
141 u32 mask_ofs;
142 u32 irq_enable_ofs;
143 u32 irq_status_ofs;
144
145 u32 dma_enable_in;
146 u32 dma_enable_out;
147 u32 dma_start;
148
149 u32 major_mask;
150 u32 major_shift;
151 u32 minor_mask;
152 u32 minor_shift;
153};
154
155struct omap_aes_dev {
156 struct list_head list;
157 unsigned long phys_base;
158 void __iomem *io_base;
159 struct omap_aes_ctx *ctx;
160 struct device *dev;
161 unsigned long flags;
162 int err;
163
164 struct tasklet_struct done_task;
165 struct aead_queue aead_queue;
166 spinlock_t lock;
167
168 struct skcipher_request *req;
169 struct aead_request *aead_req;
170 struct crypto_engine *engine;
171
172 /*
173 * total is used by PIO mode for book keeping so introduce
174 * variable total_save as need it to calc page_order
175 */
176 size_t total;
177 size_t total_save;
178 size_t assoc_len;
179 size_t authsize;
180
181 struct scatterlist *in_sg;
182 struct scatterlist *out_sg;
183
184 /* Buffers for copying for unaligned cases */
185 struct scatterlist in_sgl[2];
186 struct scatterlist out_sgl;
187 struct scatterlist *orig_out;
188
189 struct scatter_walk in_walk;
190 struct scatter_walk out_walk;
191 struct dma_chan *dma_lch_in;
192 struct dma_chan *dma_lch_out;
193 int in_sg_len;
194 int out_sg_len;
195 int pio_only;
196 const struct omap_aes_pdata *pdata;
197};
198
199u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset);
200void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value);
201struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx);
202int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
203 unsigned int keylen);
204int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key,
205 unsigned int keylen);
206int omap_aes_gcm_encrypt(struct aead_request *req);
207int omap_aes_gcm_decrypt(struct aead_request *req);
208int omap_aes_gcm_setauthsize(struct crypto_aead *tfm, unsigned int authsize);
209int omap_aes_4106gcm_encrypt(struct aead_request *req);
210int omap_aes_4106gcm_decrypt(struct aead_request *req);
211int omap_aes_4106gcm_setauthsize(struct crypto_aead *parent,
212 unsigned int authsize);
213int omap_aes_gcm_cra_init(struct crypto_aead *tfm);
214int omap_aes_write_ctrl(struct omap_aes_dev *dd);
215int omap_aes_crypt_dma_start(struct omap_aes_dev *dd);
216int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd);
217void omap_aes_gcm_dma_out_callback(void *data);
218void omap_aes_clear_copy_flags(struct omap_aes_dev *dd);
219int omap_aes_gcm_crypt_req(struct crypto_engine *engine, void *areq);
220
221#endif
1/*
2 * Cryptographic API.
3 *
4 * Support for OMAP AES HW ACCELERATOR defines
5 *
6 * Copyright (c) 2015 Texas Instruments Incorporated
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as published
10 * by the Free Software Foundation.
11 *
12 */
13#ifndef __OMAP_AES_H__
14#define __OMAP_AES_H__
15
16#include <crypto/engine.h>
17
18#define DST_MAXBURST 4
19#define DMA_MIN (DST_MAXBURST * sizeof(u32))
20
21#define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
22
23/*
24 * OMAP TRM gives bitfields as start:end, where start is the higher bit
25 * number. For example 7:0
26 */
27#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
28#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
29
30#define AES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
31 (((x) ^ 0x01) * 0x04))
32#define AES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
33
34#define AES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
35#define AES_REG_CTRL_CONTEXT_READY BIT(31)
36#define AES_REG_CTRL_CTR_WIDTH_MASK GENMASK(8, 7)
37#define AES_REG_CTRL_CTR_WIDTH_32 0
38#define AES_REG_CTRL_CTR_WIDTH_64 BIT(7)
39#define AES_REG_CTRL_CTR_WIDTH_96 BIT(8)
40#define AES_REG_CTRL_CTR_WIDTH_128 GENMASK(8, 7)
41#define AES_REG_CTRL_GCM GENMASK(17, 16)
42#define AES_REG_CTRL_CTR BIT(6)
43#define AES_REG_CTRL_CBC BIT(5)
44#define AES_REG_CTRL_KEY_SIZE GENMASK(4, 3)
45#define AES_REG_CTRL_DIRECTION BIT(2)
46#define AES_REG_CTRL_INPUT_READY BIT(1)
47#define AES_REG_CTRL_OUTPUT_READY BIT(0)
48#define AES_REG_CTRL_MASK GENMASK(24, 2)
49
50#define AES_REG_C_LEN_0 0x54
51#define AES_REG_C_LEN_1 0x58
52#define AES_REG_A_LEN 0x5C
53
54#define AES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
55#define AES_REG_TAG_N(dd, x) (0x70 + ((x) * 0x04))
56
57#define AES_REG_REV(dd) ((dd)->pdata->rev_ofs)
58
59#define AES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
60#define AES_REG_MASK_SIDLE BIT(6)
61#define AES_REG_MASK_START BIT(5)
62#define AES_REG_MASK_DMA_OUT_EN BIT(3)
63#define AES_REG_MASK_DMA_IN_EN BIT(2)
64#define AES_REG_MASK_SOFTRESET BIT(1)
65#define AES_REG_AUTOIDLE BIT(0)
66
67#define AES_REG_LENGTH_N(x) (0x54 + ((x) * 0x04))
68
69#define AES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
70#define AES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
71#define AES_REG_IRQ_DATA_IN BIT(1)
72#define AES_REG_IRQ_DATA_OUT BIT(2)
73#define DEFAULT_TIMEOUT (5 * HZ)
74
75#define DEFAULT_AUTOSUSPEND_DELAY 1000
76
77#define FLAGS_MODE_MASK 0x001f
78#define FLAGS_ENCRYPT BIT(0)
79#define FLAGS_CBC BIT(1)
80#define FLAGS_CTR BIT(2)
81#define FLAGS_GCM BIT(3)
82#define FLAGS_RFC4106_GCM BIT(4)
83
84#define FLAGS_INIT BIT(5)
85#define FLAGS_FAST BIT(6)
86#define FLAGS_BUSY BIT(7)
87
88#define FLAGS_IN_DATA_ST_SHIFT 8
89#define FLAGS_OUT_DATA_ST_SHIFT 10
90#define FLAGS_ASSOC_DATA_ST_SHIFT 12
91
92#define AES_BLOCK_WORDS (AES_BLOCK_SIZE >> 2)
93
94struct omap_aes_gcm_result {
95 struct completion completion;
96 int err;
97};
98
99struct omap_aes_ctx {
100 struct crypto_engine_ctx enginectx;
101 int keylen;
102 u32 key[AES_KEYSIZE_256 / sizeof(u32)];
103 u8 nonce[4];
104 struct crypto_skcipher *fallback;
105 struct crypto_skcipher *ctr;
106};
107
108struct omap_aes_reqctx {
109 struct omap_aes_dev *dd;
110 unsigned long mode;
111 u8 iv[AES_BLOCK_SIZE];
112 u32 auth_tag[AES_BLOCK_SIZE / sizeof(u32)];
113};
114
115#define OMAP_AES_QUEUE_LENGTH 1
116#define OMAP_AES_CACHE_SIZE 0
117
118struct omap_aes_algs_info {
119 struct crypto_alg *algs_list;
120 unsigned int size;
121 unsigned int registered;
122};
123
124struct omap_aes_aead_algs {
125 struct aead_alg *algs_list;
126 unsigned int size;
127 unsigned int registered;
128};
129
130struct omap_aes_pdata {
131 struct omap_aes_algs_info *algs_info;
132 unsigned int algs_info_size;
133 struct omap_aes_aead_algs *aead_algs_info;
134
135 void (*trigger)(struct omap_aes_dev *dd, int length);
136
137 u32 key_ofs;
138 u32 iv_ofs;
139 u32 ctrl_ofs;
140 u32 data_ofs;
141 u32 rev_ofs;
142 u32 mask_ofs;
143 u32 irq_enable_ofs;
144 u32 irq_status_ofs;
145
146 u32 dma_enable_in;
147 u32 dma_enable_out;
148 u32 dma_start;
149
150 u32 major_mask;
151 u32 major_shift;
152 u32 minor_mask;
153 u32 minor_shift;
154};
155
156struct omap_aes_dev {
157 struct list_head list;
158 unsigned long phys_base;
159 void __iomem *io_base;
160 struct omap_aes_ctx *ctx;
161 struct device *dev;
162 unsigned long flags;
163 int err;
164
165 struct tasklet_struct done_task;
166 struct aead_queue aead_queue;
167 spinlock_t lock;
168
169 struct ablkcipher_request *req;
170 struct aead_request *aead_req;
171 struct crypto_engine *engine;
172
173 /*
174 * total is used by PIO mode for book keeping so introduce
175 * variable total_save as need it to calc page_order
176 */
177 size_t total;
178 size_t total_save;
179 size_t assoc_len;
180 size_t authsize;
181
182 struct scatterlist *in_sg;
183 struct scatterlist *out_sg;
184
185 /* Buffers for copying for unaligned cases */
186 struct scatterlist in_sgl[2];
187 struct scatterlist out_sgl;
188 struct scatterlist *orig_out;
189
190 struct scatter_walk in_walk;
191 struct scatter_walk out_walk;
192 struct dma_chan *dma_lch_in;
193 struct dma_chan *dma_lch_out;
194 int in_sg_len;
195 int out_sg_len;
196 int pio_only;
197 const struct omap_aes_pdata *pdata;
198};
199
200u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset);
201void omap_aes_write(struct omap_aes_dev *dd, u32 offset, u32 value);
202struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx);
203int omap_aes_gcm_setkey(struct crypto_aead *tfm, const u8 *key,
204 unsigned int keylen);
205int omap_aes_4106gcm_setkey(struct crypto_aead *tfm, const u8 *key,
206 unsigned int keylen);
207int omap_aes_gcm_encrypt(struct aead_request *req);
208int omap_aes_gcm_decrypt(struct aead_request *req);
209int omap_aes_4106gcm_encrypt(struct aead_request *req);
210int omap_aes_4106gcm_decrypt(struct aead_request *req);
211int omap_aes_write_ctrl(struct omap_aes_dev *dd);
212int omap_aes_crypt_dma_start(struct omap_aes_dev *dd);
213int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd);
214void omap_aes_gcm_dma_out_callback(void *data);
215void omap_aes_clear_copy_flags(struct omap_aes_dev *dd);
216
217#endif