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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
4 * M (part of the Centrino chipset).
5 *
6 * Since the original Pentium M, most new Intel CPUs support Enhanced
7 * SpeedStep.
8 *
9 * Despite the "SpeedStep" in the name, this is almost entirely unlike
10 * traditional SpeedStep.
11 *
12 * Modelled on speedstep.c
13 *
14 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
15 */
16
17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
18
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/init.h>
22#include <linux/cpufreq.h>
23#include <linux/sched.h> /* current */
24#include <linux/delay.h>
25#include <linux/compiler.h>
26#include <linux/gfp.h>
27
28#include <asm/msr.h>
29#include <asm/processor.h>
30#include <asm/cpufeature.h>
31#include <asm/cpu_device_id.h>
32
33#define MAINTAINER "linux-pm@vger.kernel.org"
34
35#define INTEL_MSR_RANGE (0xffff)
36
37struct cpu_id
38{
39 __u8 x86; /* CPU family */
40 __u8 x86_model; /* model */
41 __u8 x86_stepping; /* stepping */
42};
43
44enum {
45 CPU_BANIAS,
46 CPU_DOTHAN_A1,
47 CPU_DOTHAN_A2,
48 CPU_DOTHAN_B0,
49 CPU_MP4HT_D0,
50 CPU_MP4HT_E0,
51};
52
53static const struct cpu_id cpu_ids[] = {
54 [CPU_BANIAS] = { 6, 9, 5 },
55 [CPU_DOTHAN_A1] = { 6, 13, 1 },
56 [CPU_DOTHAN_A2] = { 6, 13, 2 },
57 [CPU_DOTHAN_B0] = { 6, 13, 6 },
58 [CPU_MP4HT_D0] = {15, 3, 4 },
59 [CPU_MP4HT_E0] = {15, 4, 1 },
60};
61#define N_IDS ARRAY_SIZE(cpu_ids)
62
63struct cpu_model
64{
65 const struct cpu_id *cpu_id;
66 const char *model_name;
67 unsigned max_freq; /* max clock in kHz */
68
69 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
70};
71static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
72 const struct cpu_id *x);
73
74/* Operating points for current CPU */
75static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
76static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
77
78static struct cpufreq_driver centrino_driver;
79
80#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
81
82/* Computes the correct form for IA32_PERF_CTL MSR for a particular
83 frequency/voltage operating point; frequency in MHz, volts in mV.
84 This is stored as "driver_data" in the structure. */
85#define OP(mhz, mv) \
86 { \
87 .frequency = (mhz) * 1000, \
88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
89 }
90
91/*
92 * These voltage tables were derived from the Intel Pentium M
93 * datasheet, document 25261202.pdf, Table 5. I have verified they
94 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
95 * M.
96 */
97
98/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
99static struct cpufreq_frequency_table banias_900[] =
100{
101 OP(600, 844),
102 OP(800, 988),
103 OP(900, 1004),
104 { .frequency = CPUFREQ_TABLE_END }
105};
106
107/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
108static struct cpufreq_frequency_table banias_1000[] =
109{
110 OP(600, 844),
111 OP(800, 972),
112 OP(900, 988),
113 OP(1000, 1004),
114 { .frequency = CPUFREQ_TABLE_END }
115};
116
117/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
118static struct cpufreq_frequency_table banias_1100[] =
119{
120 OP( 600, 956),
121 OP( 800, 1020),
122 OP( 900, 1100),
123 OP(1000, 1164),
124 OP(1100, 1180),
125 { .frequency = CPUFREQ_TABLE_END }
126};
127
128
129/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
130static struct cpufreq_frequency_table banias_1200[] =
131{
132 OP( 600, 956),
133 OP( 800, 1004),
134 OP( 900, 1020),
135 OP(1000, 1100),
136 OP(1100, 1164),
137 OP(1200, 1180),
138 { .frequency = CPUFREQ_TABLE_END }
139};
140
141/* Intel Pentium M processor 1.30GHz (Banias) */
142static struct cpufreq_frequency_table banias_1300[] =
143{
144 OP( 600, 956),
145 OP( 800, 1260),
146 OP(1000, 1292),
147 OP(1200, 1356),
148 OP(1300, 1388),
149 { .frequency = CPUFREQ_TABLE_END }
150};
151
152/* Intel Pentium M processor 1.40GHz (Banias) */
153static struct cpufreq_frequency_table banias_1400[] =
154{
155 OP( 600, 956),
156 OP( 800, 1180),
157 OP(1000, 1308),
158 OP(1200, 1436),
159 OP(1400, 1484),
160 { .frequency = CPUFREQ_TABLE_END }
161};
162
163/* Intel Pentium M processor 1.50GHz (Banias) */
164static struct cpufreq_frequency_table banias_1500[] =
165{
166 OP( 600, 956),
167 OP( 800, 1116),
168 OP(1000, 1228),
169 OP(1200, 1356),
170 OP(1400, 1452),
171 OP(1500, 1484),
172 { .frequency = CPUFREQ_TABLE_END }
173};
174
175/* Intel Pentium M processor 1.60GHz (Banias) */
176static struct cpufreq_frequency_table banias_1600[] =
177{
178 OP( 600, 956),
179 OP( 800, 1036),
180 OP(1000, 1164),
181 OP(1200, 1276),
182 OP(1400, 1420),
183 OP(1600, 1484),
184 { .frequency = CPUFREQ_TABLE_END }
185};
186
187/* Intel Pentium M processor 1.70GHz (Banias) */
188static struct cpufreq_frequency_table banias_1700[] =
189{
190 OP( 600, 956),
191 OP( 800, 1004),
192 OP(1000, 1116),
193 OP(1200, 1228),
194 OP(1400, 1308),
195 OP(1700, 1484),
196 { .frequency = CPUFREQ_TABLE_END }
197};
198#undef OP
199
200#define _BANIAS(cpuid, max, name) \
201{ .cpu_id = cpuid, \
202 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
203 .max_freq = (max)*1000, \
204 .op_points = banias_##max, \
205}
206#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
207
208/* CPU models, their operating frequency range, and freq/voltage
209 operating points */
210static struct cpu_model models[] =
211{
212 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
213 BANIAS(1000),
214 BANIAS(1100),
215 BANIAS(1200),
216 BANIAS(1300),
217 BANIAS(1400),
218 BANIAS(1500),
219 BANIAS(1600),
220 BANIAS(1700),
221
222 /* NULL model_name is a wildcard */
223 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
224 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
225 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
226 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
227 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
228
229 { NULL, }
230};
231#undef _BANIAS
232#undef BANIAS
233
234static int centrino_cpu_init_table(struct cpufreq_policy *policy)
235{
236 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
237 struct cpu_model *model;
238
239 for(model = models; model->cpu_id != NULL; model++)
240 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
241 (model->model_name == NULL ||
242 strcmp(cpu->x86_model_id, model->model_name) == 0))
243 break;
244
245 if (model->cpu_id == NULL) {
246 /* No match at all */
247 pr_debug("no support for CPU model \"%s\": "
248 "send /proc/cpuinfo to " MAINTAINER "\n",
249 cpu->x86_model_id);
250 return -ENOENT;
251 }
252
253 if (model->op_points == NULL) {
254 /* Matched a non-match */
255 pr_debug("no table support for CPU model \"%s\"\n",
256 cpu->x86_model_id);
257 pr_debug("try using the acpi-cpufreq driver\n");
258 return -ENOENT;
259 }
260
261 per_cpu(centrino_model, policy->cpu) = model;
262
263 pr_debug("found \"%s\": max frequency: %dkHz\n",
264 model->model_name, model->max_freq);
265
266 return 0;
267}
268
269#else
270static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
271{
272 return -ENODEV;
273}
274#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
275
276static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
277 const struct cpu_id *x)
278{
279 if ((c->x86 == x->x86) &&
280 (c->x86_model == x->x86_model) &&
281 (c->x86_stepping == x->x86_stepping))
282 return 1;
283 return 0;
284}
285
286/* To be called only after centrino_model is initialized */
287static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
288{
289 int i;
290
291 /*
292 * Extract clock in kHz from PERF_CTL value
293 * for centrino, as some DSDTs are buggy.
294 * Ideally, this can be done using the acpi_data structure.
295 */
296 if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
297 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
298 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
299 msr = (msr >> 8) & 0xff;
300 return msr * 100000;
301 }
302
303 if ((!per_cpu(centrino_model, cpu)) ||
304 (!per_cpu(centrino_model, cpu)->op_points))
305 return 0;
306
307 msr &= 0xffff;
308 for (i = 0;
309 per_cpu(centrino_model, cpu)->op_points[i].frequency
310 != CPUFREQ_TABLE_END;
311 i++) {
312 if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
313 return per_cpu(centrino_model, cpu)->
314 op_points[i].frequency;
315 }
316 if (failsafe)
317 return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
318 else
319 return 0;
320}
321
322/* Return the current CPU frequency in kHz */
323static unsigned int get_cur_freq(unsigned int cpu)
324{
325 unsigned l, h;
326 unsigned clock_freq;
327
328 rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
329 clock_freq = extract_clock(l, cpu, 0);
330
331 if (unlikely(clock_freq == 0)) {
332 /*
333 * On some CPUs, we can see transient MSR values (which are
334 * not present in _PSS), while CPU is doing some automatic
335 * P-state transition (like TM2). Get the last freq set
336 * in PERF_CTL.
337 */
338 rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
339 clock_freq = extract_clock(l, cpu, 1);
340 }
341 return clock_freq;
342}
343
344
345static int centrino_cpu_init(struct cpufreq_policy *policy)
346{
347 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
348 unsigned l, h;
349 int i;
350
351 /* Only Intel makes Enhanced Speedstep-capable CPUs */
352 if (cpu->x86_vendor != X86_VENDOR_INTEL ||
353 !cpu_has(cpu, X86_FEATURE_EST))
354 return -ENODEV;
355
356 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
357 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
358
359 if (policy->cpu != 0)
360 return -ENODEV;
361
362 for (i = 0; i < N_IDS; i++)
363 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
364 break;
365
366 if (i != N_IDS)
367 per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
368
369 if (!per_cpu(centrino_cpu, policy->cpu)) {
370 pr_debug("found unsupported CPU with "
371 "Enhanced SpeedStep: send /proc/cpuinfo to "
372 MAINTAINER "\n");
373 return -ENODEV;
374 }
375
376 if (centrino_cpu_init_table(policy))
377 return -ENODEV;
378
379 /* Check to see if Enhanced SpeedStep is enabled, and try to
380 enable it if not. */
381 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
382
383 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
384 l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
385 pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
386 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
387
388 /* check to see if it stuck */
389 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
390 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
391 pr_info("couldn't enable Enhanced SpeedStep\n");
392 return -ENODEV;
393 }
394 }
395
396 policy->cpuinfo.transition_latency = 10000;
397 /* 10uS transition latency */
398 policy->freq_table = per_cpu(centrino_model, policy->cpu)->op_points;
399
400 return 0;
401}
402
403static void centrino_cpu_exit(struct cpufreq_policy *policy)
404{
405 unsigned int cpu = policy->cpu;
406
407 if (per_cpu(centrino_model, cpu))
408 per_cpu(centrino_model, cpu) = NULL;
409}
410
411/**
412 * centrino_target - set a new CPUFreq policy
413 * @policy: new policy
414 * @index: index of target frequency
415 *
416 * Sets a new CPUFreq policy.
417 */
418static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
419{
420 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
421 int retval = 0;
422 unsigned int j, first_cpu;
423 struct cpufreq_frequency_table *op_points;
424 cpumask_var_t covered_cpus;
425
426 if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
427 return -ENOMEM;
428
429 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
430 retval = -ENODEV;
431 goto out;
432 }
433
434 first_cpu = 1;
435 op_points = &per_cpu(centrino_model, cpu)->op_points[index];
436 for_each_cpu(j, policy->cpus) {
437 int good_cpu;
438
439 /*
440 * Support for SMP systems.
441 * Make sure we are running on CPU that wants to change freq
442 */
443 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
444 good_cpu = cpumask_any_and(policy->cpus,
445 cpu_online_mask);
446 else
447 good_cpu = j;
448
449 if (good_cpu >= nr_cpu_ids) {
450 pr_debug("couldn't limit to CPUs in this domain\n");
451 retval = -EAGAIN;
452 if (first_cpu) {
453 /* We haven't started the transition yet. */
454 goto out;
455 }
456 break;
457 }
458
459 msr = op_points->driver_data;
460
461 if (first_cpu) {
462 rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
463 if (msr == (oldmsr & 0xffff)) {
464 pr_debug("no change needed - msr was and needs "
465 "to be %x\n", oldmsr);
466 retval = 0;
467 goto out;
468 }
469
470 first_cpu = 0;
471 /* all but 16 LSB are reserved, treat them with care */
472 oldmsr &= ~0xffff;
473 msr &= 0xffff;
474 oldmsr |= msr;
475 }
476
477 wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
478 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
479 break;
480
481 cpumask_set_cpu(j, covered_cpus);
482 }
483
484 if (unlikely(retval)) {
485 /*
486 * We have failed halfway through the frequency change.
487 * We have sent callbacks to policy->cpus and
488 * MSRs have already been written on coverd_cpus.
489 * Best effort undo..
490 */
491
492 for_each_cpu(j, covered_cpus)
493 wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
494 }
495 retval = 0;
496
497out:
498 free_cpumask_var(covered_cpus);
499 return retval;
500}
501
502static struct cpufreq_driver centrino_driver = {
503 .name = "centrino", /* should be speedstep-centrino,
504 but there's a 16 char limit */
505 .init = centrino_cpu_init,
506 .exit = centrino_cpu_exit,
507 .verify = cpufreq_generic_frequency_table_verify,
508 .target_index = centrino_target,
509 .get = get_cur_freq,
510 .attr = cpufreq_generic_attr,
511};
512
513/*
514 * This doesn't replace the detailed checks above because
515 * the generic CPU IDs don't have a way to match for steppings
516 * or ASCII model IDs.
517 */
518static const struct x86_cpu_id centrino_ids[] = {
519 X86_MATCH_VFM_FEATURE(IFM( 6, 9), X86_FEATURE_EST, NULL),
520 X86_MATCH_VFM_FEATURE(IFM( 6, 13), X86_FEATURE_EST, NULL),
521 X86_MATCH_VFM_FEATURE(IFM(15, 3), X86_FEATURE_EST, NULL),
522 X86_MATCH_VFM_FEATURE(IFM(15, 4), X86_FEATURE_EST, NULL),
523 {}
524};
525
526/**
527 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
528 *
529 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
530 * unsupported devices, -ENOENT if there's no voltage table for this
531 * particular CPU model, -EINVAL on problems during initiatization,
532 * and zero on success.
533 *
534 * This is quite picky. Not only does the CPU have to advertise the
535 * "est" flag in the cpuid capability flags, we look for a specific
536 * CPU model and stepping, and we need to have the exact model name in
537 * our voltage tables. That is, be paranoid about not releasing
538 * someone's valuable magic smoke.
539 */
540static int __init centrino_init(void)
541{
542 if (!x86_match_cpu(centrino_ids))
543 return -ENODEV;
544 return cpufreq_register_driver(¢rino_driver);
545}
546
547static void __exit centrino_exit(void)
548{
549 cpufreq_unregister_driver(¢rino_driver);
550}
551
552MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
553MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
554MODULE_LICENSE ("GPL");
555
556late_initcall(centrino_init);
557module_exit(centrino_exit);
1/*
2 * cpufreq driver for Enhanced SpeedStep, as found in Intel's Pentium
3 * M (part of the Centrino chipset).
4 *
5 * Since the original Pentium M, most new Intel CPUs support Enhanced
6 * SpeedStep.
7 *
8 * Despite the "SpeedStep" in the name, this is almost entirely unlike
9 * traditional SpeedStep.
10 *
11 * Modelled on speedstep.c
12 *
13 * Copyright (C) 2003 Jeremy Fitzhardinge <jeremy@goop.org>
14 */
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/init.h>
21#include <linux/cpufreq.h>
22#include <linux/sched.h> /* current */
23#include <linux/delay.h>
24#include <linux/compiler.h>
25#include <linux/gfp.h>
26
27#include <asm/msr.h>
28#include <asm/processor.h>
29#include <asm/cpufeature.h>
30#include <asm/cpu_device_id.h>
31
32#define MAINTAINER "linux-pm@vger.kernel.org"
33
34#define INTEL_MSR_RANGE (0xffff)
35
36struct cpu_id
37{
38 __u8 x86; /* CPU family */
39 __u8 x86_model; /* model */
40 __u8 x86_stepping; /* stepping */
41};
42
43enum {
44 CPU_BANIAS,
45 CPU_DOTHAN_A1,
46 CPU_DOTHAN_A2,
47 CPU_DOTHAN_B0,
48 CPU_MP4HT_D0,
49 CPU_MP4HT_E0,
50};
51
52static const struct cpu_id cpu_ids[] = {
53 [CPU_BANIAS] = { 6, 9, 5 },
54 [CPU_DOTHAN_A1] = { 6, 13, 1 },
55 [CPU_DOTHAN_A2] = { 6, 13, 2 },
56 [CPU_DOTHAN_B0] = { 6, 13, 6 },
57 [CPU_MP4HT_D0] = {15, 3, 4 },
58 [CPU_MP4HT_E0] = {15, 4, 1 },
59};
60#define N_IDS ARRAY_SIZE(cpu_ids)
61
62struct cpu_model
63{
64 const struct cpu_id *cpu_id;
65 const char *model_name;
66 unsigned max_freq; /* max clock in kHz */
67
68 struct cpufreq_frequency_table *op_points; /* clock/voltage pairs */
69};
70static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
71 const struct cpu_id *x);
72
73/* Operating points for current CPU */
74static DEFINE_PER_CPU(struct cpu_model *, centrino_model);
75static DEFINE_PER_CPU(const struct cpu_id *, centrino_cpu);
76
77static struct cpufreq_driver centrino_driver;
78
79#ifdef CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE
80
81/* Computes the correct form for IA32_PERF_CTL MSR for a particular
82 frequency/voltage operating point; frequency in MHz, volts in mV.
83 This is stored as "driver_data" in the structure. */
84#define OP(mhz, mv) \
85 { \
86 .frequency = (mhz) * 1000, \
87 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
88 }
89
90/*
91 * These voltage tables were derived from the Intel Pentium M
92 * datasheet, document 25261202.pdf, Table 5. I have verified they
93 * are consistent with my IBM ThinkPad X31, which has a 1.3GHz Pentium
94 * M.
95 */
96
97/* Ultra Low Voltage Intel Pentium M processor 900MHz (Banias) */
98static struct cpufreq_frequency_table banias_900[] =
99{
100 OP(600, 844),
101 OP(800, 988),
102 OP(900, 1004),
103 { .frequency = CPUFREQ_TABLE_END }
104};
105
106/* Ultra Low Voltage Intel Pentium M processor 1000MHz (Banias) */
107static struct cpufreq_frequency_table banias_1000[] =
108{
109 OP(600, 844),
110 OP(800, 972),
111 OP(900, 988),
112 OP(1000, 1004),
113 { .frequency = CPUFREQ_TABLE_END }
114};
115
116/* Low Voltage Intel Pentium M processor 1.10GHz (Banias) */
117static struct cpufreq_frequency_table banias_1100[] =
118{
119 OP( 600, 956),
120 OP( 800, 1020),
121 OP( 900, 1100),
122 OP(1000, 1164),
123 OP(1100, 1180),
124 { .frequency = CPUFREQ_TABLE_END }
125};
126
127
128/* Low Voltage Intel Pentium M processor 1.20GHz (Banias) */
129static struct cpufreq_frequency_table banias_1200[] =
130{
131 OP( 600, 956),
132 OP( 800, 1004),
133 OP( 900, 1020),
134 OP(1000, 1100),
135 OP(1100, 1164),
136 OP(1200, 1180),
137 { .frequency = CPUFREQ_TABLE_END }
138};
139
140/* Intel Pentium M processor 1.30GHz (Banias) */
141static struct cpufreq_frequency_table banias_1300[] =
142{
143 OP( 600, 956),
144 OP( 800, 1260),
145 OP(1000, 1292),
146 OP(1200, 1356),
147 OP(1300, 1388),
148 { .frequency = CPUFREQ_TABLE_END }
149};
150
151/* Intel Pentium M processor 1.40GHz (Banias) */
152static struct cpufreq_frequency_table banias_1400[] =
153{
154 OP( 600, 956),
155 OP( 800, 1180),
156 OP(1000, 1308),
157 OP(1200, 1436),
158 OP(1400, 1484),
159 { .frequency = CPUFREQ_TABLE_END }
160};
161
162/* Intel Pentium M processor 1.50GHz (Banias) */
163static struct cpufreq_frequency_table banias_1500[] =
164{
165 OP( 600, 956),
166 OP( 800, 1116),
167 OP(1000, 1228),
168 OP(1200, 1356),
169 OP(1400, 1452),
170 OP(1500, 1484),
171 { .frequency = CPUFREQ_TABLE_END }
172};
173
174/* Intel Pentium M processor 1.60GHz (Banias) */
175static struct cpufreq_frequency_table banias_1600[] =
176{
177 OP( 600, 956),
178 OP( 800, 1036),
179 OP(1000, 1164),
180 OP(1200, 1276),
181 OP(1400, 1420),
182 OP(1600, 1484),
183 { .frequency = CPUFREQ_TABLE_END }
184};
185
186/* Intel Pentium M processor 1.70GHz (Banias) */
187static struct cpufreq_frequency_table banias_1700[] =
188{
189 OP( 600, 956),
190 OP( 800, 1004),
191 OP(1000, 1116),
192 OP(1200, 1228),
193 OP(1400, 1308),
194 OP(1700, 1484),
195 { .frequency = CPUFREQ_TABLE_END }
196};
197#undef OP
198
199#define _BANIAS(cpuid, max, name) \
200{ .cpu_id = cpuid, \
201 .model_name = "Intel(R) Pentium(R) M processor " name "MHz", \
202 .max_freq = (max)*1000, \
203 .op_points = banias_##max, \
204}
205#define BANIAS(max) _BANIAS(&cpu_ids[CPU_BANIAS], max, #max)
206
207/* CPU models, their operating frequency range, and freq/voltage
208 operating points */
209static struct cpu_model models[] =
210{
211 _BANIAS(&cpu_ids[CPU_BANIAS], 900, " 900"),
212 BANIAS(1000),
213 BANIAS(1100),
214 BANIAS(1200),
215 BANIAS(1300),
216 BANIAS(1400),
217 BANIAS(1500),
218 BANIAS(1600),
219 BANIAS(1700),
220
221 /* NULL model_name is a wildcard */
222 { &cpu_ids[CPU_DOTHAN_A1], NULL, 0, NULL },
223 { &cpu_ids[CPU_DOTHAN_A2], NULL, 0, NULL },
224 { &cpu_ids[CPU_DOTHAN_B0], NULL, 0, NULL },
225 { &cpu_ids[CPU_MP4HT_D0], NULL, 0, NULL },
226 { &cpu_ids[CPU_MP4HT_E0], NULL, 0, NULL },
227
228 { NULL, }
229};
230#undef _BANIAS
231#undef BANIAS
232
233static int centrino_cpu_init_table(struct cpufreq_policy *policy)
234{
235 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
236 struct cpu_model *model;
237
238 for(model = models; model->cpu_id != NULL; model++)
239 if (centrino_verify_cpu_id(cpu, model->cpu_id) &&
240 (model->model_name == NULL ||
241 strcmp(cpu->x86_model_id, model->model_name) == 0))
242 break;
243
244 if (model->cpu_id == NULL) {
245 /* No match at all */
246 pr_debug("no support for CPU model \"%s\": "
247 "send /proc/cpuinfo to " MAINTAINER "\n",
248 cpu->x86_model_id);
249 return -ENOENT;
250 }
251
252 if (model->op_points == NULL) {
253 /* Matched a non-match */
254 pr_debug("no table support for CPU model \"%s\"\n",
255 cpu->x86_model_id);
256 pr_debug("try using the acpi-cpufreq driver\n");
257 return -ENOENT;
258 }
259
260 per_cpu(centrino_model, policy->cpu) = model;
261
262 pr_debug("found \"%s\": max frequency: %dkHz\n",
263 model->model_name, model->max_freq);
264
265 return 0;
266}
267
268#else
269static inline int centrino_cpu_init_table(struct cpufreq_policy *policy)
270{
271 return -ENODEV;
272}
273#endif /* CONFIG_X86_SPEEDSTEP_CENTRINO_TABLE */
274
275static int centrino_verify_cpu_id(const struct cpuinfo_x86 *c,
276 const struct cpu_id *x)
277{
278 if ((c->x86 == x->x86) &&
279 (c->x86_model == x->x86_model) &&
280 (c->x86_stepping == x->x86_stepping))
281 return 1;
282 return 0;
283}
284
285/* To be called only after centrino_model is initialized */
286static unsigned extract_clock(unsigned msr, unsigned int cpu, int failsafe)
287{
288 int i;
289
290 /*
291 * Extract clock in kHz from PERF_CTL value
292 * for centrino, as some DSDTs are buggy.
293 * Ideally, this can be done using the acpi_data structure.
294 */
295 if ((per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_BANIAS]) ||
296 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_A1]) ||
297 (per_cpu(centrino_cpu, cpu) == &cpu_ids[CPU_DOTHAN_B0])) {
298 msr = (msr >> 8) & 0xff;
299 return msr * 100000;
300 }
301
302 if ((!per_cpu(centrino_model, cpu)) ||
303 (!per_cpu(centrino_model, cpu)->op_points))
304 return 0;
305
306 msr &= 0xffff;
307 for (i = 0;
308 per_cpu(centrino_model, cpu)->op_points[i].frequency
309 != CPUFREQ_TABLE_END;
310 i++) {
311 if (msr == per_cpu(centrino_model, cpu)->op_points[i].driver_data)
312 return per_cpu(centrino_model, cpu)->
313 op_points[i].frequency;
314 }
315 if (failsafe)
316 return per_cpu(centrino_model, cpu)->op_points[i-1].frequency;
317 else
318 return 0;
319}
320
321/* Return the current CPU frequency in kHz */
322static unsigned int get_cur_freq(unsigned int cpu)
323{
324 unsigned l, h;
325 unsigned clock_freq;
326
327 rdmsr_on_cpu(cpu, MSR_IA32_PERF_STATUS, &l, &h);
328 clock_freq = extract_clock(l, cpu, 0);
329
330 if (unlikely(clock_freq == 0)) {
331 /*
332 * On some CPUs, we can see transient MSR values (which are
333 * not present in _PSS), while CPU is doing some automatic
334 * P-state transition (like TM2). Get the last freq set
335 * in PERF_CTL.
336 */
337 rdmsr_on_cpu(cpu, MSR_IA32_PERF_CTL, &l, &h);
338 clock_freq = extract_clock(l, cpu, 1);
339 }
340 return clock_freq;
341}
342
343
344static int centrino_cpu_init(struct cpufreq_policy *policy)
345{
346 struct cpuinfo_x86 *cpu = &cpu_data(policy->cpu);
347 unsigned l, h;
348 int i;
349
350 /* Only Intel makes Enhanced Speedstep-capable CPUs */
351 if (cpu->x86_vendor != X86_VENDOR_INTEL ||
352 !cpu_has(cpu, X86_FEATURE_EST))
353 return -ENODEV;
354
355 if (cpu_has(cpu, X86_FEATURE_CONSTANT_TSC))
356 centrino_driver.flags |= CPUFREQ_CONST_LOOPS;
357
358 if (policy->cpu != 0)
359 return -ENODEV;
360
361 for (i = 0; i < N_IDS; i++)
362 if (centrino_verify_cpu_id(cpu, &cpu_ids[i]))
363 break;
364
365 if (i != N_IDS)
366 per_cpu(centrino_cpu, policy->cpu) = &cpu_ids[i];
367
368 if (!per_cpu(centrino_cpu, policy->cpu)) {
369 pr_debug("found unsupported CPU with "
370 "Enhanced SpeedStep: send /proc/cpuinfo to "
371 MAINTAINER "\n");
372 return -ENODEV;
373 }
374
375 if (centrino_cpu_init_table(policy))
376 return -ENODEV;
377
378 /* Check to see if Enhanced SpeedStep is enabled, and try to
379 enable it if not. */
380 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
381
382 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
383 l |= MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP;
384 pr_debug("trying to enable Enhanced SpeedStep (%x)\n", l);
385 wrmsr(MSR_IA32_MISC_ENABLE, l, h);
386
387 /* check to see if it stuck */
388 rdmsr(MSR_IA32_MISC_ENABLE, l, h);
389 if (!(l & MSR_IA32_MISC_ENABLE_ENHANCED_SPEEDSTEP)) {
390 pr_info("couldn't enable Enhanced SpeedStep\n");
391 return -ENODEV;
392 }
393 }
394
395 policy->cpuinfo.transition_latency = 10000;
396 /* 10uS transition latency */
397 policy->freq_table = per_cpu(centrino_model, policy->cpu)->op_points;
398
399 return 0;
400}
401
402static int centrino_cpu_exit(struct cpufreq_policy *policy)
403{
404 unsigned int cpu = policy->cpu;
405
406 if (!per_cpu(centrino_model, cpu))
407 return -ENODEV;
408
409 per_cpu(centrino_model, cpu) = NULL;
410
411 return 0;
412}
413
414/**
415 * centrino_setpolicy - set a new CPUFreq policy
416 * @policy: new policy
417 * @index: index of target frequency
418 *
419 * Sets a new CPUFreq policy.
420 */
421static int centrino_target(struct cpufreq_policy *policy, unsigned int index)
422{
423 unsigned int msr, oldmsr = 0, h = 0, cpu = policy->cpu;
424 int retval = 0;
425 unsigned int j, first_cpu;
426 struct cpufreq_frequency_table *op_points;
427 cpumask_var_t covered_cpus;
428
429 if (unlikely(!zalloc_cpumask_var(&covered_cpus, GFP_KERNEL)))
430 return -ENOMEM;
431
432 if (unlikely(per_cpu(centrino_model, cpu) == NULL)) {
433 retval = -ENODEV;
434 goto out;
435 }
436
437 first_cpu = 1;
438 op_points = &per_cpu(centrino_model, cpu)->op_points[index];
439 for_each_cpu(j, policy->cpus) {
440 int good_cpu;
441
442 /*
443 * Support for SMP systems.
444 * Make sure we are running on CPU that wants to change freq
445 */
446 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
447 good_cpu = cpumask_any_and(policy->cpus,
448 cpu_online_mask);
449 else
450 good_cpu = j;
451
452 if (good_cpu >= nr_cpu_ids) {
453 pr_debug("couldn't limit to CPUs in this domain\n");
454 retval = -EAGAIN;
455 if (first_cpu) {
456 /* We haven't started the transition yet. */
457 goto out;
458 }
459 break;
460 }
461
462 msr = op_points->driver_data;
463
464 if (first_cpu) {
465 rdmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, &oldmsr, &h);
466 if (msr == (oldmsr & 0xffff)) {
467 pr_debug("no change needed - msr was and needs "
468 "to be %x\n", oldmsr);
469 retval = 0;
470 goto out;
471 }
472
473 first_cpu = 0;
474 /* all but 16 LSB are reserved, treat them with care */
475 oldmsr &= ~0xffff;
476 msr &= 0xffff;
477 oldmsr |= msr;
478 }
479
480 wrmsr_on_cpu(good_cpu, MSR_IA32_PERF_CTL, oldmsr, h);
481 if (policy->shared_type == CPUFREQ_SHARED_TYPE_ANY)
482 break;
483
484 cpumask_set_cpu(j, covered_cpus);
485 }
486
487 if (unlikely(retval)) {
488 /*
489 * We have failed halfway through the frequency change.
490 * We have sent callbacks to policy->cpus and
491 * MSRs have already been written on coverd_cpus.
492 * Best effort undo..
493 */
494
495 for_each_cpu(j, covered_cpus)
496 wrmsr_on_cpu(j, MSR_IA32_PERF_CTL, oldmsr, h);
497 }
498 retval = 0;
499
500out:
501 free_cpumask_var(covered_cpus);
502 return retval;
503}
504
505static struct cpufreq_driver centrino_driver = {
506 .name = "centrino", /* should be speedstep-centrino,
507 but there's a 16 char limit */
508 .init = centrino_cpu_init,
509 .exit = centrino_cpu_exit,
510 .verify = cpufreq_generic_frequency_table_verify,
511 .target_index = centrino_target,
512 .get = get_cur_freq,
513 .attr = cpufreq_generic_attr,
514};
515
516/*
517 * This doesn't replace the detailed checks above because
518 * the generic CPU IDs don't have a way to match for steppings
519 * or ASCII model IDs.
520 */
521static const struct x86_cpu_id centrino_ids[] = {
522 { X86_VENDOR_INTEL, 6, 9, X86_FEATURE_EST },
523 { X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST },
524 { X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST },
525 { X86_VENDOR_INTEL, 6, 13, X86_FEATURE_EST },
526 { X86_VENDOR_INTEL, 15, 3, X86_FEATURE_EST },
527 { X86_VENDOR_INTEL, 15, 4, X86_FEATURE_EST },
528 {}
529};
530#if 0
531/* Autoload or not? Do not for now. */
532MODULE_DEVICE_TABLE(x86cpu, centrino_ids);
533#endif
534
535/**
536 * centrino_init - initializes the Enhanced SpeedStep CPUFreq driver
537 *
538 * Initializes the Enhanced SpeedStep support. Returns -ENODEV on
539 * unsupported devices, -ENOENT if there's no voltage table for this
540 * particular CPU model, -EINVAL on problems during initiatization,
541 * and zero on success.
542 *
543 * This is quite picky. Not only does the CPU have to advertise the
544 * "est" flag in the cpuid capability flags, we look for a specific
545 * CPU model and stepping, and we need to have the exact model name in
546 * our voltage tables. That is, be paranoid about not releasing
547 * someone's valuable magic smoke.
548 */
549static int __init centrino_init(void)
550{
551 if (!x86_match_cpu(centrino_ids))
552 return -ENODEV;
553 return cpufreq_register_driver(¢rino_driver);
554}
555
556static void __exit centrino_exit(void)
557{
558 cpufreq_unregister_driver(¢rino_driver);
559}
560
561MODULE_AUTHOR ("Jeremy Fitzhardinge <jeremy@goop.org>");
562MODULE_DESCRIPTION ("Enhanced SpeedStep driver for Intel Pentium M processors.");
563MODULE_LICENSE ("GPL");
564
565late_initcall(centrino_init);
566module_exit(centrino_exit);