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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
4 * 370/XP, Dove, Orion5x and MV78xx0)
5 *
6 * The Marvell EBU SoCs have a configurable physical address space:
7 * the physical address at which certain devices (PCIe, NOR, NAND,
8 * etc.) sit can be configured. The configuration takes place through
9 * two sets of registers:
10 *
11 * - One to configure the access of the CPU to the devices. Depending
12 * on the families, there are between 8 and 20 configurable windows,
13 * each can be use to create a physical memory window that maps to a
14 * specific device. Devices are identified by a tuple (target,
15 * attribute).
16 *
17 * - One to configure the access to the CPU to the SDRAM. There are
18 * either 2 (for Dove) or 4 (for other families) windows to map the
19 * SDRAM into the physical address space.
20 *
21 * This driver:
22 *
23 * - Reads out the SDRAM address decoding windows at initialization
24 * time, and fills the mvebu_mbus_dram_info structure with these
25 * information. The exported function mv_mbus_dram_info() allow
26 * device drivers to get those information related to the SDRAM
27 * address decoding windows. This is because devices also have their
28 * own windows (configured through registers that are part of each
29 * device register space), and therefore the drivers for Marvell
30 * devices have to configure those device -> SDRAM windows to ensure
31 * that DMA works properly.
32 *
33 * - Provides an API for platform code or device drivers to
34 * dynamically add or remove address decoding windows for the CPU ->
35 * device accesses. This API is mvebu_mbus_add_window_by_id(),
36 * mvebu_mbus_add_window_remap_by_id() and
37 * mvebu_mbus_del_window().
38 *
39 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
40 * see the list of CPU -> SDRAM windows and their configuration
41 * (file 'sdram') and the list of CPU -> devices windows and their
42 * configuration (file 'devices').
43 */
44
45#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
46
47#include <linux/kernel.h>
48#include <linux/module.h>
49#include <linux/init.h>
50#include <linux/mbus.h>
51#include <linux/io.h>
52#include <linux/ioport.h>
53#include <linux/of.h>
54#include <linux/of_address.h>
55#include <linux/debugfs.h>
56#include <linux/log2.h>
57#include <linux/memblock.h>
58#include <linux/syscore_ops.h>
59
60/*
61 * DDR target is the same on all platforms.
62 */
63#define TARGET_DDR 0
64
65/*
66 * CPU Address Decode Windows registers
67 */
68#define WIN_CTRL_OFF 0x0000
69#define WIN_CTRL_ENABLE BIT(0)
70/* Only on HW I/O coherency capable platforms */
71#define WIN_CTRL_SYNCBARRIER BIT(1)
72#define WIN_CTRL_TGT_MASK 0xf0
73#define WIN_CTRL_TGT_SHIFT 4
74#define WIN_CTRL_ATTR_MASK 0xff00
75#define WIN_CTRL_ATTR_SHIFT 8
76#define WIN_CTRL_SIZE_MASK 0xffff0000
77#define WIN_CTRL_SIZE_SHIFT 16
78#define WIN_BASE_OFF 0x0004
79#define WIN_BASE_LOW 0xffff0000
80#define WIN_BASE_HIGH 0xf
81#define WIN_REMAP_LO_OFF 0x0008
82#define WIN_REMAP_LOW 0xffff0000
83#define WIN_REMAP_HI_OFF 0x000c
84
85#define UNIT_SYNC_BARRIER_OFF 0x84
86#define UNIT_SYNC_BARRIER_ALL 0xFFFF
87
88#define ATTR_HW_COHERENCY (0x1 << 4)
89
90#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
91#define DDR_BASE_CS_HIGH_MASK 0xf
92#define DDR_BASE_CS_LOW_MASK 0xff000000
93#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
94#define DDR_SIZE_ENABLED BIT(0)
95#define DDR_SIZE_CS_MASK 0x1c
96#define DDR_SIZE_CS_SHIFT 2
97#define DDR_SIZE_MASK 0xff000000
98
99#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
100
101/* Relative to mbusbridge_base */
102#define MBUS_BRIDGE_CTRL_OFF 0x0
103#define MBUS_BRIDGE_BASE_OFF 0x4
104
105/* Maximum number of windows, for all known platforms */
106#define MBUS_WINS_MAX 20
107
108struct mvebu_mbus_state;
109
110struct mvebu_mbus_soc_data {
111 unsigned int num_wins;
112 bool has_mbus_bridge;
113 unsigned int (*win_cfg_offset)(const int win);
114 unsigned int (*win_remap_offset)(const int win);
115 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
116 int (*save_cpu_target)(struct mvebu_mbus_state *s,
117 u32 __iomem *store_addr);
118 int (*show_cpu_target)(struct mvebu_mbus_state *s,
119 struct seq_file *seq, void *v);
120};
121
122/*
123 * Used to store the state of one MBus window across suspend/resume.
124 */
125struct mvebu_mbus_win_data {
126 u32 ctrl;
127 u32 base;
128 u32 remap_lo;
129 u32 remap_hi;
130};
131
132struct mvebu_mbus_state {
133 void __iomem *mbuswins_base;
134 void __iomem *sdramwins_base;
135 void __iomem *mbusbridge_base;
136 phys_addr_t sdramwins_phys_base;
137 struct dentry *debugfs_root;
138 struct dentry *debugfs_sdram;
139 struct dentry *debugfs_devs;
140 struct resource pcie_mem_aperture;
141 struct resource pcie_io_aperture;
142 const struct mvebu_mbus_soc_data *soc;
143 int hw_io_coherency;
144
145 /* Used during suspend/resume */
146 u32 mbus_bridge_ctrl;
147 u32 mbus_bridge_base;
148 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
149};
150
151static struct mvebu_mbus_state mbus_state;
152
153/*
154 * We provide two variants of the mv_mbus_dram_info() function:
155 *
156 * - The normal one, where the described DRAM ranges may overlap with
157 * the I/O windows, but for which the DRAM ranges are guaranteed to
158 * have a power of two size. Such ranges are suitable for the DMA
159 * masters that only DMA between the RAM and the device, which is
160 * actually all devices except the crypto engines.
161 *
162 * - The 'nooverlap' one, where the described DRAM ranges are
163 * guaranteed to not overlap with the I/O windows, but for which the
164 * DRAM ranges will not have power of two sizes. They will only be
165 * aligned on a 64 KB boundary, and have a size multiple of 64
166 * KB. Such ranges are suitable for the DMA masters that DMA between
167 * the crypto SRAM (which is mapped through an I/O window) and a
168 * device. This is the case for the crypto engines.
169 */
170
171static struct mbus_dram_target_info mvebu_mbus_dram_info;
172static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
173
174const struct mbus_dram_target_info *mv_mbus_dram_info(void)
175{
176 return &mvebu_mbus_dram_info;
177}
178EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
179
180const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
181{
182 return &mvebu_mbus_dram_info_nooverlap;
183}
184EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
185
186/* Checks whether the given window has remap capability */
187static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
188 const int win)
189{
190 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
191}
192
193/*
194 * Functions to manipulate the address decoding windows
195 */
196
197static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
198 int win, int *enabled, u64 *base,
199 u32 *size, u8 *target, u8 *attr,
200 u64 *remap)
201{
202 void __iomem *addr = mbus->mbuswins_base +
203 mbus->soc->win_cfg_offset(win);
204 u32 basereg = readl(addr + WIN_BASE_OFF);
205 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
206
207 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
208 *enabled = 0;
209 return;
210 }
211
212 *enabled = 1;
213 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
214 *base |= (basereg & WIN_BASE_LOW);
215 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
216
217 if (target)
218 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
219
220 if (attr)
221 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
222
223 if (remap) {
224 if (mvebu_mbus_window_is_remappable(mbus, win)) {
225 u32 remap_low, remap_hi;
226 void __iomem *addr_rmp = mbus->mbuswins_base +
227 mbus->soc->win_remap_offset(win);
228 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
229 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
230 *remap = ((u64)remap_hi << 32) | remap_low;
231 } else
232 *remap = 0;
233 }
234}
235
236static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
237 int win)
238{
239 void __iomem *addr;
240
241 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
242 writel(0, addr + WIN_BASE_OFF);
243 writel(0, addr + WIN_CTRL_OFF);
244
245 if (mvebu_mbus_window_is_remappable(mbus, win)) {
246 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
247 writel(0, addr + WIN_REMAP_LO_OFF);
248 writel(0, addr + WIN_REMAP_HI_OFF);
249 }
250}
251
252/* Checks whether the given window number is available */
253
254static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
255 const int win)
256{
257 void __iomem *addr = mbus->mbuswins_base +
258 mbus->soc->win_cfg_offset(win);
259 u32 ctrl = readl(addr + WIN_CTRL_OFF);
260
261 return !(ctrl & WIN_CTRL_ENABLE);
262}
263
264/*
265 * Checks whether the given (base, base+size) area doesn't overlap an
266 * existing region
267 */
268static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
269 phys_addr_t base, size_t size,
270 u8 target, u8 attr)
271{
272 u64 end = (u64)base + size;
273 int win;
274
275 for (win = 0; win < mbus->soc->num_wins; win++) {
276 u64 wbase, wend;
277 u32 wsize;
278 u8 wtarget, wattr;
279 int enabled;
280
281 mvebu_mbus_read_window(mbus, win,
282 &enabled, &wbase, &wsize,
283 &wtarget, &wattr, NULL);
284
285 if (!enabled)
286 continue;
287
288 wend = wbase + wsize;
289
290 /*
291 * Check if the current window overlaps with the
292 * proposed physical range
293 */
294 if ((u64)base < wend && end > wbase)
295 return 0;
296 }
297
298 return 1;
299}
300
301static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
302 phys_addr_t base, size_t size)
303{
304 int win;
305
306 for (win = 0; win < mbus->soc->num_wins; win++) {
307 u64 wbase;
308 u32 wsize;
309 int enabled;
310
311 mvebu_mbus_read_window(mbus, win,
312 &enabled, &wbase, &wsize,
313 NULL, NULL, NULL);
314
315 if (!enabled)
316 continue;
317
318 if (base == wbase && size == wsize)
319 return win;
320 }
321
322 return -ENODEV;
323}
324
325static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
326 int win, phys_addr_t base, size_t size,
327 phys_addr_t remap, u8 target,
328 u8 attr)
329{
330 void __iomem *addr = mbus->mbuswins_base +
331 mbus->soc->win_cfg_offset(win);
332 u32 ctrl, remap_addr;
333
334 if (!is_power_of_2(size)) {
335 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
336 return -EINVAL;
337 }
338
339 if ((base & (phys_addr_t)(size - 1)) != 0) {
340 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
341 size);
342 return -EINVAL;
343 }
344
345 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
346 (attr << WIN_CTRL_ATTR_SHIFT) |
347 (target << WIN_CTRL_TGT_SHIFT) |
348 WIN_CTRL_ENABLE;
349 if (mbus->hw_io_coherency)
350 ctrl |= WIN_CTRL_SYNCBARRIER;
351
352 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
353 writel(ctrl, addr + WIN_CTRL_OFF);
354
355 if (mvebu_mbus_window_is_remappable(mbus, win)) {
356 void __iomem *addr_rmp = mbus->mbuswins_base +
357 mbus->soc->win_remap_offset(win);
358
359 if (remap == MVEBU_MBUS_NO_REMAP)
360 remap_addr = base;
361 else
362 remap_addr = remap;
363 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
364 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
365 }
366
367 return 0;
368}
369
370static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
371 phys_addr_t base, size_t size,
372 phys_addr_t remap, u8 target,
373 u8 attr)
374{
375 int win;
376
377 if (remap == MVEBU_MBUS_NO_REMAP) {
378 for (win = 0; win < mbus->soc->num_wins; win++) {
379 if (mvebu_mbus_window_is_remappable(mbus, win))
380 continue;
381
382 if (mvebu_mbus_window_is_free(mbus, win))
383 return mvebu_mbus_setup_window(mbus, win, base,
384 size, remap,
385 target, attr);
386 }
387 }
388
389 for (win = 0; win < mbus->soc->num_wins; win++) {
390 /* Skip window if need remap but is not supported */
391 if ((remap != MVEBU_MBUS_NO_REMAP) &&
392 !mvebu_mbus_window_is_remappable(mbus, win))
393 continue;
394
395 if (mvebu_mbus_window_is_free(mbus, win))
396 return mvebu_mbus_setup_window(mbus, win, base, size,
397 remap, target, attr);
398 }
399
400 return -ENOMEM;
401}
402
403/*
404 * Debugfs debugging
405 */
406
407/* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
408static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
409 struct seq_file *seq, void *v)
410{
411 int i;
412
413 for (i = 0; i < 4; i++) {
414 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
415 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
416 u64 base;
417 u32 size;
418
419 if (!(sizereg & DDR_SIZE_ENABLED)) {
420 seq_printf(seq, "[%d] disabled\n", i);
421 continue;
422 }
423
424 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
425 base |= basereg & DDR_BASE_CS_LOW_MASK;
426 size = (sizereg | ~DDR_SIZE_MASK);
427
428 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
429 i, (unsigned long long)base,
430 (unsigned long long)base + size + 1,
431 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
432 }
433
434 return 0;
435}
436
437/* Special function for Dove */
438static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
439 struct seq_file *seq, void *v)
440{
441 int i;
442
443 for (i = 0; i < 2; i++) {
444 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
445 u64 base;
446 u32 size;
447
448 if (!(map & 1)) {
449 seq_printf(seq, "[%d] disabled\n", i);
450 continue;
451 }
452
453 base = map & 0xff800000;
454 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
455
456 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
457 i, (unsigned long long)base,
458 (unsigned long long)base + size, i);
459 }
460
461 return 0;
462}
463
464static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
465{
466 struct mvebu_mbus_state *mbus = &mbus_state;
467 return mbus->soc->show_cpu_target(mbus, seq, v);
468}
469DEFINE_SHOW_ATTRIBUTE(mvebu_sdram_debug);
470
471static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
472{
473 struct mvebu_mbus_state *mbus = &mbus_state;
474 int win;
475
476 for (win = 0; win < mbus->soc->num_wins; win++) {
477 u64 wbase, wremap;
478 u32 wsize;
479 u8 wtarget, wattr;
480 int enabled;
481
482 mvebu_mbus_read_window(mbus, win,
483 &enabled, &wbase, &wsize,
484 &wtarget, &wattr, &wremap);
485
486 if (!enabled) {
487 seq_printf(seq, "[%02d] disabled\n", win);
488 continue;
489 }
490
491 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
492 win, (unsigned long long)wbase,
493 (unsigned long long)(wbase + wsize), wtarget, wattr);
494
495 if (!is_power_of_2(wsize) ||
496 ((wbase & (u64)(wsize - 1)) != 0))
497 seq_puts(seq, " (Invalid base/size!!)");
498
499 if (mvebu_mbus_window_is_remappable(mbus, win)) {
500 seq_printf(seq, " (remap %016llx)\n",
501 (unsigned long long)wremap);
502 } else
503 seq_printf(seq, "\n");
504 }
505
506 return 0;
507}
508DEFINE_SHOW_ATTRIBUTE(mvebu_devs_debug);
509
510/*
511 * SoC-specific functions and definitions
512 */
513
514static unsigned int generic_mbus_win_cfg_offset(int win)
515{
516 return win << 4;
517}
518
519static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
520{
521 /* The register layout is a bit annoying and the below code
522 * tries to cope with it.
523 * - At offset 0x0, there are the registers for the first 8
524 * windows, with 4 registers of 32 bits per window (ctrl,
525 * base, remap low, remap high)
526 * - Then at offset 0x80, there is a hole of 0x10 bytes for
527 * the internal registers base address and internal units
528 * sync barrier register.
529 * - Then at offset 0x90, there the registers for 12
530 * windows, with only 2 registers of 32 bits per window
531 * (ctrl, base).
532 */
533 if (win < 8)
534 return win << 4;
535 else
536 return 0x90 + ((win - 8) << 3);
537}
538
539static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
540{
541 if (win < 8)
542 return win << 4;
543 else
544 return 0x900 + ((win - 8) << 4);
545}
546
547static unsigned int generic_mbus_win_remap_2_offset(int win)
548{
549 if (win < 2)
550 return generic_mbus_win_cfg_offset(win);
551 else
552 return MVEBU_MBUS_NO_REMAP;
553}
554
555static unsigned int generic_mbus_win_remap_4_offset(int win)
556{
557 if (win < 4)
558 return generic_mbus_win_cfg_offset(win);
559 else
560 return MVEBU_MBUS_NO_REMAP;
561}
562
563static unsigned int generic_mbus_win_remap_8_offset(int win)
564{
565 if (win < 8)
566 return generic_mbus_win_cfg_offset(win);
567 else
568 return MVEBU_MBUS_NO_REMAP;
569}
570
571static unsigned int armada_xp_mbus_win_remap_offset(int win)
572{
573 if (win < 8)
574 return generic_mbus_win_cfg_offset(win);
575 else if (win == 13)
576 return 0xF0 - WIN_REMAP_LO_OFF;
577 else
578 return MVEBU_MBUS_NO_REMAP;
579}
580
581/*
582 * Use the memblock information to find the MBus bridge hole in the
583 * physical address space.
584 */
585static void __init
586mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
587{
588 phys_addr_t reg_start, reg_end;
589 uint64_t i, s = 0;
590
591 for_each_mem_range(i, ®_start, ®_end) {
592 /*
593 * This part of the memory is above 4 GB, so we don't
594 * care for the MBus bridge hole.
595 */
596 if ((u64)reg_start >= 0x100000000ULL)
597 continue;
598
599 /*
600 * The MBus bridge hole is at the end of the RAM under
601 * the 4 GB limit.
602 */
603 if (reg_end > s)
604 s = reg_end;
605 }
606
607 *start = s;
608 *end = 0x100000000ULL;
609}
610
611/*
612 * This function fills in the mvebu_mbus_dram_info_nooverlap data
613 * structure, by looking at the mvebu_mbus_dram_info data, and
614 * removing the parts of it that overlap with I/O windows.
615 */
616static void __init
617mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
618{
619 uint64_t mbus_bridge_base, mbus_bridge_end;
620 int cs_nooverlap = 0;
621 int i;
622
623 mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
624
625 for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
626 struct mbus_dram_window *w;
627 u64 base, size, end;
628
629 w = &mvebu_mbus_dram_info.cs[i];
630 base = w->base;
631 size = w->size;
632 end = base + size;
633
634 /*
635 * The CS is fully enclosed inside the MBus bridge
636 * area, so ignore it.
637 */
638 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
639 continue;
640
641 /*
642 * Beginning of CS overlaps with end of MBus, raise CS
643 * base address, and shrink its size.
644 */
645 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
646 size -= mbus_bridge_end - base;
647 base = mbus_bridge_end;
648 }
649
650 /*
651 * End of CS overlaps with beginning of MBus, shrink
652 * CS size.
653 */
654 if (base < mbus_bridge_base && end > mbus_bridge_base)
655 size -= end - mbus_bridge_base;
656
657 w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
658 w->cs_index = i;
659 w->mbus_attr = 0xf & ~(1 << i);
660 if (mbus->hw_io_coherency)
661 w->mbus_attr |= ATTR_HW_COHERENCY;
662 w->base = base;
663 w->size = size;
664 }
665
666 mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
667 mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
668}
669
670static void __init
671mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
672{
673 int i;
674 int cs;
675
676 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
677
678 for (i = 0, cs = 0; i < 4; i++) {
679 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
680 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
681
682 /*
683 * We only take care of entries for which the chip
684 * select is enabled, and that don't have high base
685 * address bits set (devices can only access the first
686 * 32 bits of the memory).
687 */
688 if ((size & DDR_SIZE_ENABLED) &&
689 !(base & DDR_BASE_CS_HIGH_MASK)) {
690 struct mbus_dram_window *w;
691
692 w = &mvebu_mbus_dram_info.cs[cs++];
693 w->cs_index = i;
694 w->mbus_attr = 0xf & ~(1 << i);
695 if (mbus->hw_io_coherency)
696 w->mbus_attr |= ATTR_HW_COHERENCY;
697 w->base = base & DDR_BASE_CS_LOW_MASK;
698 w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
699 }
700 }
701 mvebu_mbus_dram_info.num_cs = cs;
702}
703
704static int
705mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
706 u32 __iomem *store_addr)
707{
708 int i;
709
710 for (i = 0; i < 4; i++) {
711 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
712 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
713
714 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
715 store_addr++);
716 writel(base, store_addr++);
717 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
718 store_addr++);
719 writel(size, store_addr++);
720 }
721
722 /* We've written 16 words to the store address */
723 return 16;
724}
725
726static void __init
727mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
728{
729 int i;
730 int cs;
731
732 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
733
734 for (i = 0, cs = 0; i < 2; i++) {
735 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
736
737 /*
738 * Chip select enabled?
739 */
740 if (map & 1) {
741 struct mbus_dram_window *w;
742
743 w = &mvebu_mbus_dram_info.cs[cs++];
744 w->cs_index = i;
745 w->mbus_attr = 0; /* CS address decoding done inside */
746 /* the DDR controller, no need to */
747 /* provide attributes */
748 w->base = map & 0xff800000;
749 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
750 }
751 }
752
753 mvebu_mbus_dram_info.num_cs = cs;
754}
755
756static int
757mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
758 u32 __iomem *store_addr)
759{
760 int i;
761
762 for (i = 0; i < 2; i++) {
763 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
764
765 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
766 store_addr++);
767 writel(map, store_addr++);
768 }
769
770 /* We've written 4 words to the store address */
771 return 4;
772}
773
774int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
775{
776 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
777}
778
779static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
780 .num_wins = 20,
781 .has_mbus_bridge = true,
782 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
783 .win_remap_offset = generic_mbus_win_remap_8_offset,
784 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
785 .show_cpu_target = mvebu_sdram_debug_show_orion,
786 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
787};
788
789static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
790 .num_wins = 20,
791 .has_mbus_bridge = true,
792 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
793 .win_remap_offset = armada_xp_mbus_win_remap_offset,
794 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
795 .show_cpu_target = mvebu_sdram_debug_show_orion,
796 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
797};
798
799static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
800 .num_wins = 8,
801 .win_cfg_offset = generic_mbus_win_cfg_offset,
802 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
803 .win_remap_offset = generic_mbus_win_remap_4_offset,
804 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
805 .show_cpu_target = mvebu_sdram_debug_show_orion,
806};
807
808static const struct mvebu_mbus_soc_data dove_mbus_data = {
809 .num_wins = 8,
810 .win_cfg_offset = generic_mbus_win_cfg_offset,
811 .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
812 .win_remap_offset = generic_mbus_win_remap_4_offset,
813 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
814 .show_cpu_target = mvebu_sdram_debug_show_dove,
815};
816
817/*
818 * Some variants of Orion5x have 4 remappable windows, some other have
819 * only two of them.
820 */
821static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
822 .num_wins = 8,
823 .win_cfg_offset = generic_mbus_win_cfg_offset,
824 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
825 .win_remap_offset = generic_mbus_win_remap_4_offset,
826 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
827 .show_cpu_target = mvebu_sdram_debug_show_orion,
828};
829
830static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
831 .num_wins = 8,
832 .win_cfg_offset = generic_mbus_win_cfg_offset,
833 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
834 .win_remap_offset = generic_mbus_win_remap_2_offset,
835 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
836 .show_cpu_target = mvebu_sdram_debug_show_orion,
837};
838
839static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
840 .num_wins = 14,
841 .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
842 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
843 .win_remap_offset = generic_mbus_win_remap_8_offset,
844 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
845 .show_cpu_target = mvebu_sdram_debug_show_orion,
846};
847
848static const struct of_device_id of_mvebu_mbus_ids[] = {
849 { .compatible = "marvell,armada370-mbus",
850 .data = &armada_370_mbus_data, },
851 { .compatible = "marvell,armada375-mbus",
852 .data = &armada_xp_mbus_data, },
853 { .compatible = "marvell,armada380-mbus",
854 .data = &armada_xp_mbus_data, },
855 { .compatible = "marvell,armadaxp-mbus",
856 .data = &armada_xp_mbus_data, },
857 { .compatible = "marvell,kirkwood-mbus",
858 .data = &kirkwood_mbus_data, },
859 { .compatible = "marvell,dove-mbus",
860 .data = &dove_mbus_data, },
861 { .compatible = "marvell,orion5x-88f5281-mbus",
862 .data = &orion5x_4win_mbus_data, },
863 { .compatible = "marvell,orion5x-88f5182-mbus",
864 .data = &orion5x_2win_mbus_data, },
865 { .compatible = "marvell,orion5x-88f5181-mbus",
866 .data = &orion5x_2win_mbus_data, },
867 { .compatible = "marvell,orion5x-88f6183-mbus",
868 .data = &orion5x_4win_mbus_data, },
869 { .compatible = "marvell,mv78xx0-mbus",
870 .data = &mv78xx0_mbus_data, },
871 { },
872};
873
874/*
875 * Public API of the driver
876 */
877int mvebu_mbus_add_window_remap_by_id(unsigned int target,
878 unsigned int attribute,
879 phys_addr_t base, size_t size,
880 phys_addr_t remap)
881{
882 struct mvebu_mbus_state *s = &mbus_state;
883
884 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
885 pr_err("cannot add window '%x:%x', conflicts with another window\n",
886 target, attribute);
887 return -EINVAL;
888 }
889
890 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
891}
892EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_remap_by_id);
893
894int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
895 phys_addr_t base, size_t size)
896{
897 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
898 size, MVEBU_MBUS_NO_REMAP);
899}
900EXPORT_SYMBOL_GPL(mvebu_mbus_add_window_by_id);
901
902int mvebu_mbus_del_window(phys_addr_t base, size_t size)
903{
904 int win;
905
906 win = mvebu_mbus_find_window(&mbus_state, base, size);
907 if (win < 0)
908 return win;
909
910 mvebu_mbus_disable_window(&mbus_state, win);
911 return 0;
912}
913EXPORT_SYMBOL_GPL(mvebu_mbus_del_window);
914
915void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
916{
917 if (!res)
918 return;
919 *res = mbus_state.pcie_mem_aperture;
920}
921EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_mem_aperture);
922
923void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
924{
925 if (!res)
926 return;
927 *res = mbus_state.pcie_io_aperture;
928}
929EXPORT_SYMBOL_GPL(mvebu_mbus_get_pcie_io_aperture);
930
931int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
932{
933 const struct mbus_dram_target_info *dram;
934 int i;
935
936 /* Get dram info */
937 dram = mv_mbus_dram_info();
938 if (!dram) {
939 pr_err("missing DRAM information\n");
940 return -ENODEV;
941 }
942
943 /* Try to find matching DRAM window for phyaddr */
944 for (i = 0; i < dram->num_cs; i++) {
945 const struct mbus_dram_window *cs = dram->cs + i;
946
947 if (cs->base <= phyaddr &&
948 phyaddr <= (cs->base + cs->size - 1)) {
949 *target = dram->mbus_dram_target_id;
950 *attr = cs->mbus_attr;
951 return 0;
952 }
953 }
954
955 pr_err("invalid dram address %pa\n", &phyaddr);
956 return -EINVAL;
957}
958EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
959
960int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
961 u8 *attr)
962{
963 int win;
964
965 for (win = 0; win < mbus_state.soc->num_wins; win++) {
966 u64 wbase;
967 int enabled;
968
969 mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
970 size, target, attr, NULL);
971
972 if (!enabled)
973 continue;
974
975 if (wbase <= phyaddr && phyaddr <= wbase + *size)
976 return win;
977 }
978
979 return -EINVAL;
980}
981EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
982
983static __init int mvebu_mbus_debugfs_init(void)
984{
985 struct mvebu_mbus_state *s = &mbus_state;
986
987 /*
988 * If no base has been initialized, doesn't make sense to
989 * register the debugfs entries. We may be on a multiplatform
990 * kernel that isn't running a Marvell EBU SoC.
991 */
992 if (!s->mbuswins_base)
993 return 0;
994
995 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
996 if (s->debugfs_root) {
997 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
998 s->debugfs_root, NULL,
999 &mvebu_sdram_debug_fops);
1000 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
1001 s->debugfs_root, NULL,
1002 &mvebu_devs_debug_fops);
1003 }
1004
1005 return 0;
1006}
1007fs_initcall(mvebu_mbus_debugfs_init);
1008
1009static int mvebu_mbus_suspend(void)
1010{
1011 struct mvebu_mbus_state *s = &mbus_state;
1012 int win;
1013
1014 if (!s->mbusbridge_base)
1015 return -ENODEV;
1016
1017 for (win = 0; win < s->soc->num_wins; win++) {
1018 void __iomem *addr = s->mbuswins_base +
1019 s->soc->win_cfg_offset(win);
1020 void __iomem *addr_rmp;
1021
1022 s->wins[win].base = readl(addr + WIN_BASE_OFF);
1023 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
1024
1025 if (!mvebu_mbus_window_is_remappable(s, win))
1026 continue;
1027
1028 addr_rmp = s->mbuswins_base +
1029 s->soc->win_remap_offset(win);
1030
1031 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
1032 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
1033 }
1034
1035 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
1036 MBUS_BRIDGE_CTRL_OFF);
1037 s->mbus_bridge_base = readl(s->mbusbridge_base +
1038 MBUS_BRIDGE_BASE_OFF);
1039
1040 return 0;
1041}
1042
1043static void mvebu_mbus_resume(void)
1044{
1045 struct mvebu_mbus_state *s = &mbus_state;
1046 int win;
1047
1048 writel(s->mbus_bridge_ctrl,
1049 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
1050 writel(s->mbus_bridge_base,
1051 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
1052
1053 for (win = 0; win < s->soc->num_wins; win++) {
1054 void __iomem *addr = s->mbuswins_base +
1055 s->soc->win_cfg_offset(win);
1056 void __iomem *addr_rmp;
1057
1058 writel(s->wins[win].base, addr + WIN_BASE_OFF);
1059 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
1060
1061 if (!mvebu_mbus_window_is_remappable(s, win))
1062 continue;
1063
1064 addr_rmp = s->mbuswins_base +
1065 s->soc->win_remap_offset(win);
1066
1067 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
1068 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
1069 }
1070}
1071
1072static struct syscore_ops mvebu_mbus_syscore_ops = {
1073 .suspend = mvebu_mbus_suspend,
1074 .resume = mvebu_mbus_resume,
1075};
1076
1077static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
1078 phys_addr_t mbuswins_phys_base,
1079 size_t mbuswins_size,
1080 phys_addr_t sdramwins_phys_base,
1081 size_t sdramwins_size,
1082 phys_addr_t mbusbridge_phys_base,
1083 size_t mbusbridge_size,
1084 bool is_coherent)
1085{
1086 int win;
1087
1088 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
1089 if (!mbus->mbuswins_base)
1090 return -ENOMEM;
1091
1092 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
1093 if (!mbus->sdramwins_base) {
1094 iounmap(mbus->mbuswins_base);
1095 return -ENOMEM;
1096 }
1097
1098 mbus->sdramwins_phys_base = sdramwins_phys_base;
1099
1100 if (mbusbridge_phys_base) {
1101 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
1102 mbusbridge_size);
1103 if (!mbus->mbusbridge_base) {
1104 iounmap(mbus->sdramwins_base);
1105 iounmap(mbus->mbuswins_base);
1106 return -ENOMEM;
1107 }
1108 } else
1109 mbus->mbusbridge_base = NULL;
1110
1111 for (win = 0; win < mbus->soc->num_wins; win++)
1112 mvebu_mbus_disable_window(mbus, win);
1113
1114 mbus->soc->setup_cpu_target(mbus);
1115 mvebu_mbus_setup_cpu_target_nooverlap(mbus);
1116
1117 if (is_coherent)
1118 writel(UNIT_SYNC_BARRIER_ALL,
1119 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
1120
1121 register_syscore_ops(&mvebu_mbus_syscore_ops);
1122
1123 return 0;
1124}
1125
1126int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
1127 size_t mbuswins_size,
1128 phys_addr_t sdramwins_phys_base,
1129 size_t sdramwins_size)
1130{
1131 const struct of_device_id *of_id;
1132
1133 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
1134 if (!strcmp(of_id->compatible, soc))
1135 break;
1136
1137 if (!of_id->compatible[0]) {
1138 pr_err("could not find a matching SoC family\n");
1139 return -ENODEV;
1140 }
1141
1142 mbus_state.soc = of_id->data;
1143
1144 return mvebu_mbus_common_init(&mbus_state,
1145 mbuswins_phys_base,
1146 mbuswins_size,
1147 sdramwins_phys_base,
1148 sdramwins_size, 0, 0, false);
1149}
1150
1151#ifdef CONFIG_OF
1152/*
1153 * The window IDs in the ranges DT property have the following format:
1154 * - bits 28 to 31: MBus custom field
1155 * - bits 24 to 27: window target ID
1156 * - bits 16 to 23: window attribute ID
1157 * - bits 0 to 15: unused
1158 */
1159#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1160#define TARGET(id) (((id) & 0x0F000000) >> 24)
1161#define ATTR(id) (((id) & 0x00FF0000) >> 16)
1162
1163static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1164 u32 base, u32 size,
1165 u8 target, u8 attr)
1166{
1167 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1168 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1169 target, attr);
1170 return -EBUSY;
1171 }
1172
1173 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1174 target, attr)) {
1175 pr_err("cannot add window '%04x:%04x', too many windows\n",
1176 target, attr);
1177 return -ENOMEM;
1178 }
1179 return 0;
1180}
1181
1182static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1183 struct device_node *np)
1184{
1185 int ret;
1186 struct of_range_parser parser;
1187 struct of_range range;
1188
1189 ret = of_range_parser_init(&parser, np);
1190 if (ret < 0)
1191 return 0;
1192
1193 for_each_of_range(&parser, &range) {
1194 u32 windowid = upper_32_bits(range.bus_addr);
1195 u8 target, attr;
1196
1197 /*
1198 * An entry with a non-zero custom field do not
1199 * correspond to a static window, so skip it.
1200 */
1201 if (CUSTOM(windowid))
1202 continue;
1203
1204 target = TARGET(windowid);
1205 attr = ATTR(windowid);
1206
1207 ret = mbus_dt_setup_win(mbus, range.cpu_addr, range.size, target, attr);
1208 if (ret < 0)
1209 return ret;
1210 }
1211 return 0;
1212}
1213
1214static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1215 struct resource *mem,
1216 struct resource *io)
1217{
1218 u32 reg[2];
1219 int ret;
1220
1221 /*
1222 * These are optional, so we make sure that resource_size(x) will
1223 * return 0.
1224 */
1225 memset(mem, 0, sizeof(struct resource));
1226 mem->end = -1;
1227 memset(io, 0, sizeof(struct resource));
1228 io->end = -1;
1229
1230 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1231 if (!ret) {
1232 mem->start = reg[0];
1233 mem->end = mem->start + reg[1] - 1;
1234 mem->flags = IORESOURCE_MEM;
1235 }
1236
1237 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1238 if (!ret) {
1239 io->start = reg[0];
1240 io->end = io->start + reg[1] - 1;
1241 io->flags = IORESOURCE_IO;
1242 }
1243}
1244
1245int __init mvebu_mbus_dt_init(bool is_coherent)
1246{
1247 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1248 struct device_node *np, *controller;
1249 const struct of_device_id *of_id;
1250 const __be32 *prop;
1251 int ret;
1252
1253 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1254 if (!np) {
1255 pr_err("could not find a matching SoC family\n");
1256 return -ENODEV;
1257 }
1258
1259 mbus_state.soc = of_id->data;
1260
1261 prop = of_get_property(np, "controller", NULL);
1262 if (!prop) {
1263 pr_err("required 'controller' property missing\n");
1264 return -EINVAL;
1265 }
1266
1267 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1268 if (!controller) {
1269 pr_err("could not find an 'mbus-controller' node\n");
1270 return -ENODEV;
1271 }
1272
1273 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1274 pr_err("cannot get MBUS register address\n");
1275 return -EINVAL;
1276 }
1277
1278 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1279 pr_err("cannot get SDRAM register address\n");
1280 return -EINVAL;
1281 }
1282
1283 /*
1284 * Set the resource to 0 so that it can be left unmapped by
1285 * mvebu_mbus_common_init() if the DT doesn't carry the
1286 * necessary information. This is needed to preserve backward
1287 * compatibility.
1288 */
1289 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1290
1291 if (mbus_state.soc->has_mbus_bridge) {
1292 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1293 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1294 }
1295
1296 mbus_state.hw_io_coherency = is_coherent;
1297
1298 /* Get optional pcie-{mem,io}-aperture properties */
1299 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1300 &mbus_state.pcie_io_aperture);
1301
1302 ret = mvebu_mbus_common_init(&mbus_state,
1303 mbuswins_res.start,
1304 resource_size(&mbuswins_res),
1305 sdramwins_res.start,
1306 resource_size(&sdramwins_res),
1307 mbusbridge_res.start,
1308 resource_size(&mbusbridge_res),
1309 is_coherent);
1310 if (ret)
1311 return ret;
1312
1313 /* Setup statically declared windows in the DT */
1314 return mbus_dt_setup(&mbus_state, np);
1315}
1316#endif
1/*
2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2. This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 *
9 * The Marvell EBU SoCs have a configurable physical address space:
10 * the physical address at which certain devices (PCIe, NOR, NAND,
11 * etc.) sit can be configured. The configuration takes place through
12 * two sets of registers:
13 *
14 * - One to configure the access of the CPU to the devices. Depending
15 * on the families, there are between 8 and 20 configurable windows,
16 * each can be use to create a physical memory window that maps to a
17 * specific device. Devices are identified by a tuple (target,
18 * attribute).
19 *
20 * - One to configure the access to the CPU to the SDRAM. There are
21 * either 2 (for Dove) or 4 (for other families) windows to map the
22 * SDRAM into the physical address space.
23 *
24 * This driver:
25 *
26 * - Reads out the SDRAM address decoding windows at initialization
27 * time, and fills the mvebu_mbus_dram_info structure with these
28 * informations. The exported function mv_mbus_dram_info() allow
29 * device drivers to get those informations related to the SDRAM
30 * address decoding windows. This is because devices also have their
31 * own windows (configured through registers that are part of each
32 * device register space), and therefore the drivers for Marvell
33 * devices have to configure those device -> SDRAM windows to ensure
34 * that DMA works properly.
35 *
36 * - Provides an API for platform code or device drivers to
37 * dynamically add or remove address decoding windows for the CPU ->
38 * device accesses. This API is mvebu_mbus_add_window_by_id(),
39 * mvebu_mbus_add_window_remap_by_id() and
40 * mvebu_mbus_del_window().
41 *
42 * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
43 * see the list of CPU -> SDRAM windows and their configuration
44 * (file 'sdram') and the list of CPU -> devices windows and their
45 * configuration (file 'devices').
46 */
47
48#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
49
50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/init.h>
53#include <linux/mbus.h>
54#include <linux/io.h>
55#include <linux/ioport.h>
56#include <linux/of.h>
57#include <linux/of_address.h>
58#include <linux/debugfs.h>
59#include <linux/log2.h>
60#include <linux/memblock.h>
61#include <linux/syscore_ops.h>
62
63/*
64 * DDR target is the same on all platforms.
65 */
66#define TARGET_DDR 0
67
68/*
69 * CPU Address Decode Windows registers
70 */
71#define WIN_CTRL_OFF 0x0000
72#define WIN_CTRL_ENABLE BIT(0)
73/* Only on HW I/O coherency capable platforms */
74#define WIN_CTRL_SYNCBARRIER BIT(1)
75#define WIN_CTRL_TGT_MASK 0xf0
76#define WIN_CTRL_TGT_SHIFT 4
77#define WIN_CTRL_ATTR_MASK 0xff00
78#define WIN_CTRL_ATTR_SHIFT 8
79#define WIN_CTRL_SIZE_MASK 0xffff0000
80#define WIN_CTRL_SIZE_SHIFT 16
81#define WIN_BASE_OFF 0x0004
82#define WIN_BASE_LOW 0xffff0000
83#define WIN_BASE_HIGH 0xf
84#define WIN_REMAP_LO_OFF 0x0008
85#define WIN_REMAP_LOW 0xffff0000
86#define WIN_REMAP_HI_OFF 0x000c
87
88#define UNIT_SYNC_BARRIER_OFF 0x84
89#define UNIT_SYNC_BARRIER_ALL 0xFFFF
90
91#define ATTR_HW_COHERENCY (0x1 << 4)
92
93#define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
94#define DDR_BASE_CS_HIGH_MASK 0xf
95#define DDR_BASE_CS_LOW_MASK 0xff000000
96#define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
97#define DDR_SIZE_ENABLED BIT(0)
98#define DDR_SIZE_CS_MASK 0x1c
99#define DDR_SIZE_CS_SHIFT 2
100#define DDR_SIZE_MASK 0xff000000
101
102#define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
103
104/* Relative to mbusbridge_base */
105#define MBUS_BRIDGE_CTRL_OFF 0x0
106#define MBUS_BRIDGE_BASE_OFF 0x4
107
108/* Maximum number of windows, for all known platforms */
109#define MBUS_WINS_MAX 20
110
111struct mvebu_mbus_state;
112
113struct mvebu_mbus_soc_data {
114 unsigned int num_wins;
115 bool has_mbus_bridge;
116 unsigned int (*win_cfg_offset)(const int win);
117 unsigned int (*win_remap_offset)(const int win);
118 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
119 int (*save_cpu_target)(struct mvebu_mbus_state *s,
120 u32 __iomem *store_addr);
121 int (*show_cpu_target)(struct mvebu_mbus_state *s,
122 struct seq_file *seq, void *v);
123};
124
125/*
126 * Used to store the state of one MBus window accross suspend/resume.
127 */
128struct mvebu_mbus_win_data {
129 u32 ctrl;
130 u32 base;
131 u32 remap_lo;
132 u32 remap_hi;
133};
134
135struct mvebu_mbus_state {
136 void __iomem *mbuswins_base;
137 void __iomem *sdramwins_base;
138 void __iomem *mbusbridge_base;
139 phys_addr_t sdramwins_phys_base;
140 struct dentry *debugfs_root;
141 struct dentry *debugfs_sdram;
142 struct dentry *debugfs_devs;
143 struct resource pcie_mem_aperture;
144 struct resource pcie_io_aperture;
145 const struct mvebu_mbus_soc_data *soc;
146 int hw_io_coherency;
147
148 /* Used during suspend/resume */
149 u32 mbus_bridge_ctrl;
150 u32 mbus_bridge_base;
151 struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
152};
153
154static struct mvebu_mbus_state mbus_state;
155
156/*
157 * We provide two variants of the mv_mbus_dram_info() function:
158 *
159 * - The normal one, where the described DRAM ranges may overlap with
160 * the I/O windows, but for which the DRAM ranges are guaranteed to
161 * have a power of two size. Such ranges are suitable for the DMA
162 * masters that only DMA between the RAM and the device, which is
163 * actually all devices except the crypto engines.
164 *
165 * - The 'nooverlap' one, where the described DRAM ranges are
166 * guaranteed to not overlap with the I/O windows, but for which the
167 * DRAM ranges will not have power of two sizes. They will only be
168 * aligned on a 64 KB boundary, and have a size multiple of 64
169 * KB. Such ranges are suitable for the DMA masters that DMA between
170 * the crypto SRAM (which is mapped through an I/O window) and a
171 * device. This is the case for the crypto engines.
172 */
173
174static struct mbus_dram_target_info mvebu_mbus_dram_info;
175static struct mbus_dram_target_info mvebu_mbus_dram_info_nooverlap;
176
177const struct mbus_dram_target_info *mv_mbus_dram_info(void)
178{
179 return &mvebu_mbus_dram_info;
180}
181EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
182
183const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
184{
185 return &mvebu_mbus_dram_info_nooverlap;
186}
187EXPORT_SYMBOL_GPL(mv_mbus_dram_info_nooverlap);
188
189/* Checks whether the given window has remap capability */
190static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
191 const int win)
192{
193 return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
194}
195
196/*
197 * Functions to manipulate the address decoding windows
198 */
199
200static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
201 int win, int *enabled, u64 *base,
202 u32 *size, u8 *target, u8 *attr,
203 u64 *remap)
204{
205 void __iomem *addr = mbus->mbuswins_base +
206 mbus->soc->win_cfg_offset(win);
207 u32 basereg = readl(addr + WIN_BASE_OFF);
208 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
209
210 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
211 *enabled = 0;
212 return;
213 }
214
215 *enabled = 1;
216 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
217 *base |= (basereg & WIN_BASE_LOW);
218 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
219
220 if (target)
221 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
222
223 if (attr)
224 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
225
226 if (remap) {
227 if (mvebu_mbus_window_is_remappable(mbus, win)) {
228 u32 remap_low, remap_hi;
229 void __iomem *addr_rmp = mbus->mbuswins_base +
230 mbus->soc->win_remap_offset(win);
231 remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
232 remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
233 *remap = ((u64)remap_hi << 32) | remap_low;
234 } else
235 *remap = 0;
236 }
237}
238
239static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
240 int win)
241{
242 void __iomem *addr;
243
244 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
245 writel(0, addr + WIN_BASE_OFF);
246 writel(0, addr + WIN_CTRL_OFF);
247
248 if (mvebu_mbus_window_is_remappable(mbus, win)) {
249 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
250 writel(0, addr + WIN_REMAP_LO_OFF);
251 writel(0, addr + WIN_REMAP_HI_OFF);
252 }
253}
254
255/* Checks whether the given window number is available */
256
257static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
258 const int win)
259{
260 void __iomem *addr = mbus->mbuswins_base +
261 mbus->soc->win_cfg_offset(win);
262 u32 ctrl = readl(addr + WIN_CTRL_OFF);
263
264 return !(ctrl & WIN_CTRL_ENABLE);
265}
266
267/*
268 * Checks whether the given (base, base+size) area doesn't overlap an
269 * existing region
270 */
271static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
272 phys_addr_t base, size_t size,
273 u8 target, u8 attr)
274{
275 u64 end = (u64)base + size;
276 int win;
277
278 for (win = 0; win < mbus->soc->num_wins; win++) {
279 u64 wbase, wend;
280 u32 wsize;
281 u8 wtarget, wattr;
282 int enabled;
283
284 mvebu_mbus_read_window(mbus, win,
285 &enabled, &wbase, &wsize,
286 &wtarget, &wattr, NULL);
287
288 if (!enabled)
289 continue;
290
291 wend = wbase + wsize;
292
293 /*
294 * Check if the current window overlaps with the
295 * proposed physical range
296 */
297 if ((u64)base < wend && end > wbase)
298 return 0;
299 }
300
301 return 1;
302}
303
304static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
305 phys_addr_t base, size_t size)
306{
307 int win;
308
309 for (win = 0; win < mbus->soc->num_wins; win++) {
310 u64 wbase;
311 u32 wsize;
312 int enabled;
313
314 mvebu_mbus_read_window(mbus, win,
315 &enabled, &wbase, &wsize,
316 NULL, NULL, NULL);
317
318 if (!enabled)
319 continue;
320
321 if (base == wbase && size == wsize)
322 return win;
323 }
324
325 return -ENODEV;
326}
327
328static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
329 int win, phys_addr_t base, size_t size,
330 phys_addr_t remap, u8 target,
331 u8 attr)
332{
333 void __iomem *addr = mbus->mbuswins_base +
334 mbus->soc->win_cfg_offset(win);
335 u32 ctrl, remap_addr;
336
337 if (!is_power_of_2(size)) {
338 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
339 return -EINVAL;
340 }
341
342 if ((base & (phys_addr_t)(size - 1)) != 0) {
343 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
344 size);
345 return -EINVAL;
346 }
347
348 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
349 (attr << WIN_CTRL_ATTR_SHIFT) |
350 (target << WIN_CTRL_TGT_SHIFT) |
351 WIN_CTRL_ENABLE;
352 if (mbus->hw_io_coherency)
353 ctrl |= WIN_CTRL_SYNCBARRIER;
354
355 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
356 writel(ctrl, addr + WIN_CTRL_OFF);
357
358 if (mvebu_mbus_window_is_remappable(mbus, win)) {
359 void __iomem *addr_rmp = mbus->mbuswins_base +
360 mbus->soc->win_remap_offset(win);
361
362 if (remap == MVEBU_MBUS_NO_REMAP)
363 remap_addr = base;
364 else
365 remap_addr = remap;
366 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
367 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
368 }
369
370 return 0;
371}
372
373static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
374 phys_addr_t base, size_t size,
375 phys_addr_t remap, u8 target,
376 u8 attr)
377{
378 int win;
379
380 if (remap == MVEBU_MBUS_NO_REMAP) {
381 for (win = 0; win < mbus->soc->num_wins; win++) {
382 if (mvebu_mbus_window_is_remappable(mbus, win))
383 continue;
384
385 if (mvebu_mbus_window_is_free(mbus, win))
386 return mvebu_mbus_setup_window(mbus, win, base,
387 size, remap,
388 target, attr);
389 }
390 }
391
392 for (win = 0; win < mbus->soc->num_wins; win++) {
393 /* Skip window if need remap but is not supported */
394 if ((remap != MVEBU_MBUS_NO_REMAP) &&
395 !mvebu_mbus_window_is_remappable(mbus, win))
396 continue;
397
398 if (mvebu_mbus_window_is_free(mbus, win))
399 return mvebu_mbus_setup_window(mbus, win, base, size,
400 remap, target, attr);
401 }
402
403 return -ENOMEM;
404}
405
406/*
407 * Debugfs debugging
408 */
409
410/* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
411static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
412 struct seq_file *seq, void *v)
413{
414 int i;
415
416 for (i = 0; i < 4; i++) {
417 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
418 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
419 u64 base;
420 u32 size;
421
422 if (!(sizereg & DDR_SIZE_ENABLED)) {
423 seq_printf(seq, "[%d] disabled\n", i);
424 continue;
425 }
426
427 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
428 base |= basereg & DDR_BASE_CS_LOW_MASK;
429 size = (sizereg | ~DDR_SIZE_MASK);
430
431 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
432 i, (unsigned long long)base,
433 (unsigned long long)base + size + 1,
434 (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
435 }
436
437 return 0;
438}
439
440/* Special function for Dove */
441static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
442 struct seq_file *seq, void *v)
443{
444 int i;
445
446 for (i = 0; i < 2; i++) {
447 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
448 u64 base;
449 u32 size;
450
451 if (!(map & 1)) {
452 seq_printf(seq, "[%d] disabled\n", i);
453 continue;
454 }
455
456 base = map & 0xff800000;
457 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
458
459 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
460 i, (unsigned long long)base,
461 (unsigned long long)base + size, i);
462 }
463
464 return 0;
465}
466
467static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
468{
469 struct mvebu_mbus_state *mbus = &mbus_state;
470 return mbus->soc->show_cpu_target(mbus, seq, v);
471}
472
473static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
474{
475 return single_open(file, mvebu_sdram_debug_show, inode->i_private);
476}
477
478static const struct file_operations mvebu_sdram_debug_fops = {
479 .open = mvebu_sdram_debug_open,
480 .read = seq_read,
481 .llseek = seq_lseek,
482 .release = single_release,
483};
484
485static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
486{
487 struct mvebu_mbus_state *mbus = &mbus_state;
488 int win;
489
490 for (win = 0; win < mbus->soc->num_wins; win++) {
491 u64 wbase, wremap;
492 u32 wsize;
493 u8 wtarget, wattr;
494 int enabled;
495
496 mvebu_mbus_read_window(mbus, win,
497 &enabled, &wbase, &wsize,
498 &wtarget, &wattr, &wremap);
499
500 if (!enabled) {
501 seq_printf(seq, "[%02d] disabled\n", win);
502 continue;
503 }
504
505 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
506 win, (unsigned long long)wbase,
507 (unsigned long long)(wbase + wsize), wtarget, wattr);
508
509 if (!is_power_of_2(wsize) ||
510 ((wbase & (u64)(wsize - 1)) != 0))
511 seq_puts(seq, " (Invalid base/size!!)");
512
513 if (mvebu_mbus_window_is_remappable(mbus, win)) {
514 seq_printf(seq, " (remap %016llx)\n",
515 (unsigned long long)wremap);
516 } else
517 seq_printf(seq, "\n");
518 }
519
520 return 0;
521}
522
523static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
524{
525 return single_open(file, mvebu_devs_debug_show, inode->i_private);
526}
527
528static const struct file_operations mvebu_devs_debug_fops = {
529 .open = mvebu_devs_debug_open,
530 .read = seq_read,
531 .llseek = seq_lseek,
532 .release = single_release,
533};
534
535/*
536 * SoC-specific functions and definitions
537 */
538
539static unsigned int generic_mbus_win_cfg_offset(int win)
540{
541 return win << 4;
542}
543
544static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
545{
546 /* The register layout is a bit annoying and the below code
547 * tries to cope with it.
548 * - At offset 0x0, there are the registers for the first 8
549 * windows, with 4 registers of 32 bits per window (ctrl,
550 * base, remap low, remap high)
551 * - Then at offset 0x80, there is a hole of 0x10 bytes for
552 * the internal registers base address and internal units
553 * sync barrier register.
554 * - Then at offset 0x90, there the registers for 12
555 * windows, with only 2 registers of 32 bits per window
556 * (ctrl, base).
557 */
558 if (win < 8)
559 return win << 4;
560 else
561 return 0x90 + ((win - 8) << 3);
562}
563
564static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
565{
566 if (win < 8)
567 return win << 4;
568 else
569 return 0x900 + ((win - 8) << 4);
570}
571
572static unsigned int generic_mbus_win_remap_2_offset(int win)
573{
574 if (win < 2)
575 return generic_mbus_win_cfg_offset(win);
576 else
577 return MVEBU_MBUS_NO_REMAP;
578}
579
580static unsigned int generic_mbus_win_remap_4_offset(int win)
581{
582 if (win < 4)
583 return generic_mbus_win_cfg_offset(win);
584 else
585 return MVEBU_MBUS_NO_REMAP;
586}
587
588static unsigned int generic_mbus_win_remap_8_offset(int win)
589{
590 if (win < 8)
591 return generic_mbus_win_cfg_offset(win);
592 else
593 return MVEBU_MBUS_NO_REMAP;
594}
595
596static unsigned int armada_xp_mbus_win_remap_offset(int win)
597{
598 if (win < 8)
599 return generic_mbus_win_cfg_offset(win);
600 else if (win == 13)
601 return 0xF0 - WIN_REMAP_LO_OFF;
602 else
603 return MVEBU_MBUS_NO_REMAP;
604}
605
606/*
607 * Use the memblock information to find the MBus bridge hole in the
608 * physical address space.
609 */
610static void __init
611mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
612{
613 struct memblock_region *r;
614 uint64_t s = 0;
615
616 for_each_memblock(memory, r) {
617 /*
618 * This part of the memory is above 4 GB, so we don't
619 * care for the MBus bridge hole.
620 */
621 if (r->base >= 0x100000000ULL)
622 continue;
623
624 /*
625 * The MBus bridge hole is at the end of the RAM under
626 * the 4 GB limit.
627 */
628 if (r->base + r->size > s)
629 s = r->base + r->size;
630 }
631
632 *start = s;
633 *end = 0x100000000ULL;
634}
635
636/*
637 * This function fills in the mvebu_mbus_dram_info_nooverlap data
638 * structure, by looking at the mvebu_mbus_dram_info data, and
639 * removing the parts of it that overlap with I/O windows.
640 */
641static void __init
642mvebu_mbus_setup_cpu_target_nooverlap(struct mvebu_mbus_state *mbus)
643{
644 uint64_t mbus_bridge_base, mbus_bridge_end;
645 int cs_nooverlap = 0;
646 int i;
647
648 mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
649
650 for (i = 0; i < mvebu_mbus_dram_info.num_cs; i++) {
651 struct mbus_dram_window *w;
652 u64 base, size, end;
653
654 w = &mvebu_mbus_dram_info.cs[i];
655 base = w->base;
656 size = w->size;
657 end = base + size;
658
659 /*
660 * The CS is fully enclosed inside the MBus bridge
661 * area, so ignore it.
662 */
663 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
664 continue;
665
666 /*
667 * Beginning of CS overlaps with end of MBus, raise CS
668 * base address, and shrink its size.
669 */
670 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
671 size -= mbus_bridge_end - base;
672 base = mbus_bridge_end;
673 }
674
675 /*
676 * End of CS overlaps with beginning of MBus, shrink
677 * CS size.
678 */
679 if (base < mbus_bridge_base && end > mbus_bridge_base)
680 size -= end - mbus_bridge_base;
681
682 w = &mvebu_mbus_dram_info_nooverlap.cs[cs_nooverlap++];
683 w->cs_index = i;
684 w->mbus_attr = 0xf & ~(1 << i);
685 if (mbus->hw_io_coherency)
686 w->mbus_attr |= ATTR_HW_COHERENCY;
687 w->base = base;
688 w->size = size;
689 }
690
691 mvebu_mbus_dram_info_nooverlap.mbus_dram_target_id = TARGET_DDR;
692 mvebu_mbus_dram_info_nooverlap.num_cs = cs_nooverlap;
693}
694
695static void __init
696mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
697{
698 int i;
699 int cs;
700
701 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
702
703 for (i = 0, cs = 0; i < 4; i++) {
704 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
705 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
706
707 /*
708 * We only take care of entries for which the chip
709 * select is enabled, and that don't have high base
710 * address bits set (devices can only access the first
711 * 32 bits of the memory).
712 */
713 if ((size & DDR_SIZE_ENABLED) &&
714 !(base & DDR_BASE_CS_HIGH_MASK)) {
715 struct mbus_dram_window *w;
716
717 w = &mvebu_mbus_dram_info.cs[cs++];
718 w->cs_index = i;
719 w->mbus_attr = 0xf & ~(1 << i);
720 if (mbus->hw_io_coherency)
721 w->mbus_attr |= ATTR_HW_COHERENCY;
722 w->base = base & DDR_BASE_CS_LOW_MASK;
723 w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;
724 }
725 }
726 mvebu_mbus_dram_info.num_cs = cs;
727}
728
729static int
730mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
731 u32 __iomem *store_addr)
732{
733 int i;
734
735 for (i = 0; i < 4; i++) {
736 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
737 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
738
739 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
740 store_addr++);
741 writel(base, store_addr++);
742 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
743 store_addr++);
744 writel(size, store_addr++);
745 }
746
747 /* We've written 16 words to the store address */
748 return 16;
749}
750
751static void __init
752mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
753{
754 int i;
755 int cs;
756
757 mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
758
759 for (i = 0, cs = 0; i < 2; i++) {
760 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
761
762 /*
763 * Chip select enabled?
764 */
765 if (map & 1) {
766 struct mbus_dram_window *w;
767
768 w = &mvebu_mbus_dram_info.cs[cs++];
769 w->cs_index = i;
770 w->mbus_attr = 0; /* CS address decoding done inside */
771 /* the DDR controller, no need to */
772 /* provide attributes */
773 w->base = map & 0xff800000;
774 w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
775 }
776 }
777
778 mvebu_mbus_dram_info.num_cs = cs;
779}
780
781static int
782mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
783 u32 __iomem *store_addr)
784{
785 int i;
786
787 for (i = 0; i < 2; i++) {
788 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
789
790 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
791 store_addr++);
792 writel(map, store_addr++);
793 }
794
795 /* We've written 4 words to the store address */
796 return 4;
797}
798
799int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr)
800{
801 return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
802}
803
804static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
805 .num_wins = 20,
806 .has_mbus_bridge = true,
807 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
808 .win_remap_offset = generic_mbus_win_remap_8_offset,
809 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
810 .show_cpu_target = mvebu_sdram_debug_show_orion,
811 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
812};
813
814static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
815 .num_wins = 20,
816 .has_mbus_bridge = true,
817 .win_cfg_offset = armada_370_xp_mbus_win_cfg_offset,
818 .win_remap_offset = armada_xp_mbus_win_remap_offset,
819 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
820 .show_cpu_target = mvebu_sdram_debug_show_orion,
821 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
822};
823
824static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
825 .num_wins = 8,
826 .win_cfg_offset = generic_mbus_win_cfg_offset,
827 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
828 .win_remap_offset = generic_mbus_win_remap_4_offset,
829 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
830 .show_cpu_target = mvebu_sdram_debug_show_orion,
831};
832
833static const struct mvebu_mbus_soc_data dove_mbus_data = {
834 .num_wins = 8,
835 .win_cfg_offset = generic_mbus_win_cfg_offset,
836 .save_cpu_target = mvebu_mbus_dove_save_cpu_target,
837 .win_remap_offset = generic_mbus_win_remap_4_offset,
838 .setup_cpu_target = mvebu_mbus_dove_setup_cpu_target,
839 .show_cpu_target = mvebu_sdram_debug_show_dove,
840};
841
842/*
843 * Some variants of Orion5x have 4 remappable windows, some other have
844 * only two of them.
845 */
846static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
847 .num_wins = 8,
848 .win_cfg_offset = generic_mbus_win_cfg_offset,
849 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
850 .win_remap_offset = generic_mbus_win_remap_4_offset,
851 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
852 .show_cpu_target = mvebu_sdram_debug_show_orion,
853};
854
855static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
856 .num_wins = 8,
857 .win_cfg_offset = generic_mbus_win_cfg_offset,
858 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
859 .win_remap_offset = generic_mbus_win_remap_2_offset,
860 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
861 .show_cpu_target = mvebu_sdram_debug_show_orion,
862};
863
864static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
865 .num_wins = 14,
866 .win_cfg_offset = mv78xx0_mbus_win_cfg_offset,
867 .save_cpu_target = mvebu_mbus_default_save_cpu_target,
868 .win_remap_offset = generic_mbus_win_remap_8_offset,
869 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
870 .show_cpu_target = mvebu_sdram_debug_show_orion,
871};
872
873static const struct of_device_id of_mvebu_mbus_ids[] = {
874 { .compatible = "marvell,armada370-mbus",
875 .data = &armada_370_mbus_data, },
876 { .compatible = "marvell,armada375-mbus",
877 .data = &armada_xp_mbus_data, },
878 { .compatible = "marvell,armada380-mbus",
879 .data = &armada_xp_mbus_data, },
880 { .compatible = "marvell,armadaxp-mbus",
881 .data = &armada_xp_mbus_data, },
882 { .compatible = "marvell,kirkwood-mbus",
883 .data = &kirkwood_mbus_data, },
884 { .compatible = "marvell,dove-mbus",
885 .data = &dove_mbus_data, },
886 { .compatible = "marvell,orion5x-88f5281-mbus",
887 .data = &orion5x_4win_mbus_data, },
888 { .compatible = "marvell,orion5x-88f5182-mbus",
889 .data = &orion5x_2win_mbus_data, },
890 { .compatible = "marvell,orion5x-88f5181-mbus",
891 .data = &orion5x_2win_mbus_data, },
892 { .compatible = "marvell,orion5x-88f6183-mbus",
893 .data = &orion5x_4win_mbus_data, },
894 { .compatible = "marvell,mv78xx0-mbus",
895 .data = &mv78xx0_mbus_data, },
896 { },
897};
898
899/*
900 * Public API of the driver
901 */
902int mvebu_mbus_add_window_remap_by_id(unsigned int target,
903 unsigned int attribute,
904 phys_addr_t base, size_t size,
905 phys_addr_t remap)
906{
907 struct mvebu_mbus_state *s = &mbus_state;
908
909 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
910 pr_err("cannot add window '%x:%x', conflicts with another window\n",
911 target, attribute);
912 return -EINVAL;
913 }
914
915 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
916}
917
918int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
919 phys_addr_t base, size_t size)
920{
921 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
922 size, MVEBU_MBUS_NO_REMAP);
923}
924
925int mvebu_mbus_del_window(phys_addr_t base, size_t size)
926{
927 int win;
928
929 win = mvebu_mbus_find_window(&mbus_state, base, size);
930 if (win < 0)
931 return win;
932
933 mvebu_mbus_disable_window(&mbus_state, win);
934 return 0;
935}
936
937void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
938{
939 if (!res)
940 return;
941 *res = mbus_state.pcie_mem_aperture;
942}
943
944void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
945{
946 if (!res)
947 return;
948 *res = mbus_state.pcie_io_aperture;
949}
950
951int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
952{
953 const struct mbus_dram_target_info *dram;
954 int i;
955
956 /* Get dram info */
957 dram = mv_mbus_dram_info();
958 if (!dram) {
959 pr_err("missing DRAM information\n");
960 return -ENODEV;
961 }
962
963 /* Try to find matching DRAM window for phyaddr */
964 for (i = 0; i < dram->num_cs; i++) {
965 const struct mbus_dram_window *cs = dram->cs + i;
966
967 if (cs->base <= phyaddr &&
968 phyaddr <= (cs->base + cs->size - 1)) {
969 *target = dram->mbus_dram_target_id;
970 *attr = cs->mbus_attr;
971 return 0;
972 }
973 }
974
975 pr_err("invalid dram address %pa\n", &phyaddr);
976 return -EINVAL;
977}
978EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
979
980int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
981 u8 *attr)
982{
983 int win;
984
985 for (win = 0; win < mbus_state.soc->num_wins; win++) {
986 u64 wbase;
987 int enabled;
988
989 mvebu_mbus_read_window(&mbus_state, win, &enabled, &wbase,
990 size, target, attr, NULL);
991
992 if (!enabled)
993 continue;
994
995 if (wbase <= phyaddr && phyaddr <= wbase + *size)
996 return win;
997 }
998
999 return -EINVAL;
1000}
1001EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
1002
1003static __init int mvebu_mbus_debugfs_init(void)
1004{
1005 struct mvebu_mbus_state *s = &mbus_state;
1006
1007 /*
1008 * If no base has been initialized, doesn't make sense to
1009 * register the debugfs entries. We may be on a multiplatform
1010 * kernel that isn't running a Marvell EBU SoC.
1011 */
1012 if (!s->mbuswins_base)
1013 return 0;
1014
1015 s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
1016 if (s->debugfs_root) {
1017 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
1018 s->debugfs_root, NULL,
1019 &mvebu_sdram_debug_fops);
1020 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
1021 s->debugfs_root, NULL,
1022 &mvebu_devs_debug_fops);
1023 }
1024
1025 return 0;
1026}
1027fs_initcall(mvebu_mbus_debugfs_init);
1028
1029static int mvebu_mbus_suspend(void)
1030{
1031 struct mvebu_mbus_state *s = &mbus_state;
1032 int win;
1033
1034 if (!s->mbusbridge_base)
1035 return -ENODEV;
1036
1037 for (win = 0; win < s->soc->num_wins; win++) {
1038 void __iomem *addr = s->mbuswins_base +
1039 s->soc->win_cfg_offset(win);
1040 void __iomem *addr_rmp;
1041
1042 s->wins[win].base = readl(addr + WIN_BASE_OFF);
1043 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
1044
1045 if (!mvebu_mbus_window_is_remappable(s, win))
1046 continue;
1047
1048 addr_rmp = s->mbuswins_base +
1049 s->soc->win_remap_offset(win);
1050
1051 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
1052 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
1053 }
1054
1055 s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
1056 MBUS_BRIDGE_CTRL_OFF);
1057 s->mbus_bridge_base = readl(s->mbusbridge_base +
1058 MBUS_BRIDGE_BASE_OFF);
1059
1060 return 0;
1061}
1062
1063static void mvebu_mbus_resume(void)
1064{
1065 struct mvebu_mbus_state *s = &mbus_state;
1066 int win;
1067
1068 writel(s->mbus_bridge_ctrl,
1069 s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
1070 writel(s->mbus_bridge_base,
1071 s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
1072
1073 for (win = 0; win < s->soc->num_wins; win++) {
1074 void __iomem *addr = s->mbuswins_base +
1075 s->soc->win_cfg_offset(win);
1076 void __iomem *addr_rmp;
1077
1078 writel(s->wins[win].base, addr + WIN_BASE_OFF);
1079 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
1080
1081 if (!mvebu_mbus_window_is_remappable(s, win))
1082 continue;
1083
1084 addr_rmp = s->mbuswins_base +
1085 s->soc->win_remap_offset(win);
1086
1087 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
1088 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
1089 }
1090}
1091
1092static struct syscore_ops mvebu_mbus_syscore_ops = {
1093 .suspend = mvebu_mbus_suspend,
1094 .resume = mvebu_mbus_resume,
1095};
1096
1097static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
1098 phys_addr_t mbuswins_phys_base,
1099 size_t mbuswins_size,
1100 phys_addr_t sdramwins_phys_base,
1101 size_t sdramwins_size,
1102 phys_addr_t mbusbridge_phys_base,
1103 size_t mbusbridge_size,
1104 bool is_coherent)
1105{
1106 int win;
1107
1108 mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
1109 if (!mbus->mbuswins_base)
1110 return -ENOMEM;
1111
1112 mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
1113 if (!mbus->sdramwins_base) {
1114 iounmap(mbus_state.mbuswins_base);
1115 return -ENOMEM;
1116 }
1117
1118 mbus->sdramwins_phys_base = sdramwins_phys_base;
1119
1120 if (mbusbridge_phys_base) {
1121 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
1122 mbusbridge_size);
1123 if (!mbus->mbusbridge_base) {
1124 iounmap(mbus->sdramwins_base);
1125 iounmap(mbus->mbuswins_base);
1126 return -ENOMEM;
1127 }
1128 } else
1129 mbus->mbusbridge_base = NULL;
1130
1131 for (win = 0; win < mbus->soc->num_wins; win++)
1132 mvebu_mbus_disable_window(mbus, win);
1133
1134 mbus->soc->setup_cpu_target(mbus);
1135 mvebu_mbus_setup_cpu_target_nooverlap(mbus);
1136
1137 if (is_coherent)
1138 writel(UNIT_SYNC_BARRIER_ALL,
1139 mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
1140
1141 register_syscore_ops(&mvebu_mbus_syscore_ops);
1142
1143 return 0;
1144}
1145
1146int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
1147 size_t mbuswins_size,
1148 phys_addr_t sdramwins_phys_base,
1149 size_t sdramwins_size)
1150{
1151 const struct of_device_id *of_id;
1152
1153 for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
1154 if (!strcmp(of_id->compatible, soc))
1155 break;
1156
1157 if (!of_id->compatible[0]) {
1158 pr_err("could not find a matching SoC family\n");
1159 return -ENODEV;
1160 }
1161
1162 mbus_state.soc = of_id->data;
1163
1164 return mvebu_mbus_common_init(&mbus_state,
1165 mbuswins_phys_base,
1166 mbuswins_size,
1167 sdramwins_phys_base,
1168 sdramwins_size, 0, 0, false);
1169}
1170
1171#ifdef CONFIG_OF
1172/*
1173 * The window IDs in the ranges DT property have the following format:
1174 * - bits 28 to 31: MBus custom field
1175 * - bits 24 to 27: window target ID
1176 * - bits 16 to 23: window attribute ID
1177 * - bits 0 to 15: unused
1178 */
1179#define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1180#define TARGET(id) (((id) & 0x0F000000) >> 24)
1181#define ATTR(id) (((id) & 0x00FF0000) >> 16)
1182
1183static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1184 u32 base, u32 size,
1185 u8 target, u8 attr)
1186{
1187 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1188 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1189 target, attr);
1190 return -EBUSY;
1191 }
1192
1193 if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1194 target, attr)) {
1195 pr_err("cannot add window '%04x:%04x', too many windows\n",
1196 target, attr);
1197 return -ENOMEM;
1198 }
1199 return 0;
1200}
1201
1202static int __init
1203mbus_parse_ranges(struct device_node *node,
1204 int *addr_cells, int *c_addr_cells, int *c_size_cells,
1205 int *cell_count, const __be32 **ranges_start,
1206 const __be32 **ranges_end)
1207{
1208 const __be32 *prop;
1209 int ranges_len, tuple_len;
1210
1211 /* Allow a node with no 'ranges' property */
1212 *ranges_start = of_get_property(node, "ranges", &ranges_len);
1213 if (*ranges_start == NULL) {
1214 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
1215 *ranges_start = *ranges_end = NULL;
1216 return 0;
1217 }
1218 *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
1219
1220 *addr_cells = of_n_addr_cells(node);
1221
1222 prop = of_get_property(node, "#address-cells", NULL);
1223 *c_addr_cells = be32_to_cpup(prop);
1224
1225 prop = of_get_property(node, "#size-cells", NULL);
1226 *c_size_cells = be32_to_cpup(prop);
1227
1228 *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
1229 tuple_len = (*cell_count) * sizeof(__be32);
1230
1231 if (ranges_len % tuple_len) {
1232 pr_warn("malformed ranges entry '%s'\n", node->name);
1233 return -EINVAL;
1234 }
1235 return 0;
1236}
1237
1238static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1239 struct device_node *np)
1240{
1241 int addr_cells, c_addr_cells, c_size_cells;
1242 int i, ret, cell_count;
1243 const __be32 *r, *ranges_start, *ranges_end;
1244
1245 ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1246 &c_size_cells, &cell_count,
1247 &ranges_start, &ranges_end);
1248 if (ret < 0)
1249 return ret;
1250
1251 for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1252 u32 windowid, base, size;
1253 u8 target, attr;
1254
1255 /*
1256 * An entry with a non-zero custom field do not
1257 * correspond to a static window, so skip it.
1258 */
1259 windowid = of_read_number(r, 1);
1260 if (CUSTOM(windowid))
1261 continue;
1262
1263 target = TARGET(windowid);
1264 attr = ATTR(windowid);
1265
1266 base = of_read_number(r + c_addr_cells, addr_cells);
1267 size = of_read_number(r + c_addr_cells + addr_cells,
1268 c_size_cells);
1269 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1270 if (ret < 0)
1271 return ret;
1272 }
1273 return 0;
1274}
1275
1276static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1277 struct resource *mem,
1278 struct resource *io)
1279{
1280 u32 reg[2];
1281 int ret;
1282
1283 /*
1284 * These are optional, so we make sure that resource_size(x) will
1285 * return 0.
1286 */
1287 memset(mem, 0, sizeof(struct resource));
1288 mem->end = -1;
1289 memset(io, 0, sizeof(struct resource));
1290 io->end = -1;
1291
1292 ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1293 if (!ret) {
1294 mem->start = reg[0];
1295 mem->end = mem->start + reg[1] - 1;
1296 mem->flags = IORESOURCE_MEM;
1297 }
1298
1299 ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1300 if (!ret) {
1301 io->start = reg[0];
1302 io->end = io->start + reg[1] - 1;
1303 io->flags = IORESOURCE_IO;
1304 }
1305}
1306
1307int __init mvebu_mbus_dt_init(bool is_coherent)
1308{
1309 struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1310 struct device_node *np, *controller;
1311 const struct of_device_id *of_id;
1312 const __be32 *prop;
1313 int ret;
1314
1315 np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1316 if (!np) {
1317 pr_err("could not find a matching SoC family\n");
1318 return -ENODEV;
1319 }
1320
1321 mbus_state.soc = of_id->data;
1322
1323 prop = of_get_property(np, "controller", NULL);
1324 if (!prop) {
1325 pr_err("required 'controller' property missing\n");
1326 return -EINVAL;
1327 }
1328
1329 controller = of_find_node_by_phandle(be32_to_cpup(prop));
1330 if (!controller) {
1331 pr_err("could not find an 'mbus-controller' node\n");
1332 return -ENODEV;
1333 }
1334
1335 if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1336 pr_err("cannot get MBUS register address\n");
1337 return -EINVAL;
1338 }
1339
1340 if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1341 pr_err("cannot get SDRAM register address\n");
1342 return -EINVAL;
1343 }
1344
1345 /*
1346 * Set the resource to 0 so that it can be left unmapped by
1347 * mvebu_mbus_common_init() if the DT doesn't carry the
1348 * necessary information. This is needed to preserve backward
1349 * compatibility.
1350 */
1351 memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1352
1353 if (mbus_state.soc->has_mbus_bridge) {
1354 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1355 pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1356 }
1357
1358 mbus_state.hw_io_coherency = is_coherent;
1359
1360 /* Get optional pcie-{mem,io}-aperture properties */
1361 mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1362 &mbus_state.pcie_io_aperture);
1363
1364 ret = mvebu_mbus_common_init(&mbus_state,
1365 mbuswins_res.start,
1366 resource_size(&mbuswins_res),
1367 sdramwins_res.start,
1368 resource_size(&sdramwins_res),
1369 mbusbridge_res.start,
1370 resource_size(&mbusbridge_res),
1371 is_coherent);
1372 if (ret)
1373 return ret;
1374
1375 /* Setup statically declared windows in the DT */
1376 return mbus_dt_setup(&mbus_state, np);
1377}
1378#endif