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1// SPDX-License-Identifier: GPL-2.0-only
2
3/*
4 * Local APIC virtualization
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2007 Novell
8 * Copyright (C) 2007 Intel
9 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
10 *
11 * Authors:
12 * Dor Laor <dor.laor@qumranet.com>
13 * Gregory Haskins <ghaskins@novell.com>
14 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
15 *
16 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
17 */
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/kvm_host.h>
21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/export.h>
28#include <linux/math64.h>
29#include <linux/slab.h>
30#include <asm/processor.h>
31#include <asm/mce.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
36#include <asm/delay.h>
37#include <linux/atomic.h>
38#include <linux/jump_label.h>
39#include "kvm_cache_regs.h"
40#include "irq.h"
41#include "ioapic.h"
42#include "trace.h"
43#include "x86.h"
44#include "xen.h"
45#include "cpuid.h"
46#include "hyperv.h"
47#include "smm.h"
48
49#ifndef CONFIG_X86_64
50#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
51#else
52#define mod_64(x, y) ((x) % (y))
53#endif
54
55/* 14 is the version for Xeon and Pentium 8.4.8*/
56#define APIC_VERSION 0x14UL
57#define LAPIC_MMIO_LENGTH (1 << 12)
58/* followed define is not in apicdef.h */
59#define MAX_APIC_VECTOR 256
60#define APIC_VECTORS_PER_REG 32
61
62/*
63 * Enable local APIC timer advancement (tscdeadline mode only) with adaptive
64 * tuning. When enabled, KVM programs the host timer event to fire early, i.e.
65 * before the deadline expires, to account for the delay between taking the
66 * VM-Exit (to inject the guest event) and the subsequent VM-Enter to resume
67 * the guest, i.e. so that the interrupt arrives in the guest with minimal
68 * latency relative to the deadline programmed by the guest.
69 */
70static bool lapic_timer_advance __read_mostly = true;
71module_param(lapic_timer_advance, bool, 0444);
72
73#define LAPIC_TIMER_ADVANCE_ADJUST_MIN 100 /* clock cycles */
74#define LAPIC_TIMER_ADVANCE_ADJUST_MAX 10000 /* clock cycles */
75#define LAPIC_TIMER_ADVANCE_NS_INIT 1000
76#define LAPIC_TIMER_ADVANCE_NS_MAX 5000
77/* step-by-step approximation to mitigate fluctuation */
78#define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
79static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
80static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
81
82static inline void __kvm_lapic_set_reg(char *regs, int reg_off, u32 val)
83{
84 *((u32 *) (regs + reg_off)) = val;
85}
86
87static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
88{
89 __kvm_lapic_set_reg(apic->regs, reg_off, val);
90}
91
92static __always_inline u64 __kvm_lapic_get_reg64(char *regs, int reg)
93{
94 BUILD_BUG_ON(reg != APIC_ICR);
95 return *((u64 *) (regs + reg));
96}
97
98static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg)
99{
100 return __kvm_lapic_get_reg64(apic->regs, reg);
101}
102
103static __always_inline void __kvm_lapic_set_reg64(char *regs, int reg, u64 val)
104{
105 BUILD_BUG_ON(reg != APIC_ICR);
106 *((u64 *) (regs + reg)) = val;
107}
108
109static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic,
110 int reg, u64 val)
111{
112 __kvm_lapic_set_reg64(apic->regs, reg, val);
113}
114
115static inline int apic_test_vector(int vec, void *bitmap)
116{
117 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
118}
119
120bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
121{
122 struct kvm_lapic *apic = vcpu->arch.apic;
123
124 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
125 apic_test_vector(vector, apic->regs + APIC_IRR);
126}
127
128static inline int __apic_test_and_set_vector(int vec, void *bitmap)
129{
130 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
131}
132
133static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
134{
135 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
136}
137
138__read_mostly DEFINE_STATIC_KEY_FALSE(kvm_has_noapic_vcpu);
139EXPORT_SYMBOL_GPL(kvm_has_noapic_vcpu);
140
141__read_mostly DEFINE_STATIC_KEY_DEFERRED_FALSE(apic_hw_disabled, HZ);
142__read_mostly DEFINE_STATIC_KEY_DEFERRED_FALSE(apic_sw_disabled, HZ);
143
144static inline int apic_enabled(struct kvm_lapic *apic)
145{
146 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
147}
148
149#define LVT_MASK \
150 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
151
152#define LINT_MASK \
153 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
154 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
155
156static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
157{
158 return apic->vcpu->vcpu_id;
159}
160
161static bool kvm_can_post_timer_interrupt(struct kvm_vcpu *vcpu)
162{
163 return pi_inject_timer && kvm_vcpu_apicv_active(vcpu) &&
164 (kvm_mwait_in_guest(vcpu->kvm) || kvm_hlt_in_guest(vcpu->kvm));
165}
166
167bool kvm_can_use_hv_timer(struct kvm_vcpu *vcpu)
168{
169 return kvm_x86_ops.set_hv_timer
170 && !(kvm_mwait_in_guest(vcpu->kvm) ||
171 kvm_can_post_timer_interrupt(vcpu));
172}
173
174static bool kvm_use_posted_timer_interrupt(struct kvm_vcpu *vcpu)
175{
176 return kvm_can_post_timer_interrupt(vcpu) && vcpu->mode == IN_GUEST_MODE;
177}
178
179static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
180{
181 return ((id >> 4) << 16) | (1 << (id & 0xf));
182}
183
184static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
185 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
186 switch (map->logical_mode) {
187 case KVM_APIC_MODE_SW_DISABLED:
188 /* Arbitrarily use the flat map so that @cluster isn't NULL. */
189 *cluster = map->xapic_flat_map;
190 *mask = 0;
191 return true;
192 case KVM_APIC_MODE_X2APIC: {
193 u32 offset = (dest_id >> 16) * 16;
194 u32 max_apic_id = map->max_apic_id;
195
196 if (offset <= max_apic_id) {
197 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
198
199 offset = array_index_nospec(offset, map->max_apic_id + 1);
200 *cluster = &map->phys_map[offset];
201 *mask = dest_id & (0xffff >> (16 - cluster_size));
202 } else {
203 *mask = 0;
204 }
205
206 return true;
207 }
208 case KVM_APIC_MODE_XAPIC_FLAT:
209 *cluster = map->xapic_flat_map;
210 *mask = dest_id & 0xff;
211 return true;
212 case KVM_APIC_MODE_XAPIC_CLUSTER:
213 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
214 *mask = dest_id & 0xf;
215 return true;
216 case KVM_APIC_MODE_MAP_DISABLED:
217 return false;
218 default:
219 WARN_ON_ONCE(1);
220 return false;
221 }
222}
223
224static void kvm_apic_map_free(struct rcu_head *rcu)
225{
226 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
227
228 kvfree(map);
229}
230
231static int kvm_recalculate_phys_map(struct kvm_apic_map *new,
232 struct kvm_vcpu *vcpu,
233 bool *xapic_id_mismatch)
234{
235 struct kvm_lapic *apic = vcpu->arch.apic;
236 u32 x2apic_id = kvm_x2apic_id(apic);
237 u32 xapic_id = kvm_xapic_id(apic);
238 u32 physical_id;
239
240 /*
241 * For simplicity, KVM always allocates enough space for all possible
242 * xAPIC IDs. Yell, but don't kill the VM, as KVM can continue on
243 * without the optimized map.
244 */
245 if (WARN_ON_ONCE(xapic_id > new->max_apic_id))
246 return -EINVAL;
247
248 /*
249 * Bail if a vCPU was added and/or enabled its APIC between allocating
250 * the map and doing the actual calculations for the map. Note, KVM
251 * hardcodes the x2APIC ID to vcpu_id, i.e. there's no TOCTOU bug if
252 * the compiler decides to reload x2apic_id after this check.
253 */
254 if (x2apic_id > new->max_apic_id)
255 return -E2BIG;
256
257 /*
258 * Deliberately truncate the vCPU ID when detecting a mismatched APIC
259 * ID to avoid false positives if the vCPU ID, i.e. x2APIC ID, is a
260 * 32-bit value. Any unwanted aliasing due to truncation results will
261 * be detected below.
262 */
263 if (!apic_x2apic_mode(apic) && xapic_id != (u8)vcpu->vcpu_id)
264 *xapic_id_mismatch = true;
265
266 /*
267 * Apply KVM's hotplug hack if userspace has enable 32-bit APIC IDs.
268 * Allow sending events to vCPUs by their x2APIC ID even if the target
269 * vCPU is in legacy xAPIC mode, and silently ignore aliased xAPIC IDs
270 * (the x2APIC ID is truncated to 8 bits, causing IDs > 0xff to wrap
271 * and collide).
272 *
273 * Honor the architectural (and KVM's non-optimized) behavior if
274 * userspace has not enabled 32-bit x2APIC IDs. Each APIC is supposed
275 * to process messages independently. If multiple vCPUs have the same
276 * effective APIC ID, e.g. due to the x2APIC wrap or because the guest
277 * manually modified its xAPIC IDs, events targeting that ID are
278 * supposed to be recognized by all vCPUs with said ID.
279 */
280 if (vcpu->kvm->arch.x2apic_format) {
281 /* See also kvm_apic_match_physical_addr(). */
282 if (apic_x2apic_mode(apic) || x2apic_id > 0xff)
283 new->phys_map[x2apic_id] = apic;
284
285 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
286 new->phys_map[xapic_id] = apic;
287 } else {
288 /*
289 * Disable the optimized map if the physical APIC ID is already
290 * mapped, i.e. is aliased to multiple vCPUs. The optimized
291 * map requires a strict 1:1 mapping between IDs and vCPUs.
292 */
293 if (apic_x2apic_mode(apic))
294 physical_id = x2apic_id;
295 else
296 physical_id = xapic_id;
297
298 if (new->phys_map[physical_id])
299 return -EINVAL;
300
301 new->phys_map[physical_id] = apic;
302 }
303
304 return 0;
305}
306
307static void kvm_recalculate_logical_map(struct kvm_apic_map *new,
308 struct kvm_vcpu *vcpu)
309{
310 struct kvm_lapic *apic = vcpu->arch.apic;
311 enum kvm_apic_logical_mode logical_mode;
312 struct kvm_lapic **cluster;
313 u16 mask;
314 u32 ldr;
315
316 if (new->logical_mode == KVM_APIC_MODE_MAP_DISABLED)
317 return;
318
319 if (!kvm_apic_sw_enabled(apic))
320 return;
321
322 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
323 if (!ldr)
324 return;
325
326 if (apic_x2apic_mode(apic)) {
327 logical_mode = KVM_APIC_MODE_X2APIC;
328 } else {
329 ldr = GET_APIC_LOGICAL_ID(ldr);
330 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
331 logical_mode = KVM_APIC_MODE_XAPIC_FLAT;
332 else
333 logical_mode = KVM_APIC_MODE_XAPIC_CLUSTER;
334 }
335
336 /*
337 * To optimize logical mode delivery, all software-enabled APICs must
338 * be configured for the same mode.
339 */
340 if (new->logical_mode == KVM_APIC_MODE_SW_DISABLED) {
341 new->logical_mode = logical_mode;
342 } else if (new->logical_mode != logical_mode) {
343 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED;
344 return;
345 }
346
347 /*
348 * In x2APIC mode, the LDR is read-only and derived directly from the
349 * x2APIC ID, thus is guaranteed to be addressable. KVM reuses
350 * kvm_apic_map.phys_map to optimize logical mode x2APIC interrupts by
351 * reversing the LDR calculation to get cluster of APICs, i.e. no
352 * additional work is required.
353 */
354 if (apic_x2apic_mode(apic))
355 return;
356
357 if (WARN_ON_ONCE(!kvm_apic_map_get_logical_dest(new, ldr,
358 &cluster, &mask))) {
359 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED;
360 return;
361 }
362
363 if (!mask)
364 return;
365
366 ldr = ffs(mask) - 1;
367 if (!is_power_of_2(mask) || cluster[ldr])
368 new->logical_mode = KVM_APIC_MODE_MAP_DISABLED;
369 else
370 cluster[ldr] = apic;
371}
372
373/*
374 * CLEAN -> DIRTY and UPDATE_IN_PROGRESS -> DIRTY changes happen without a lock.
375 *
376 * DIRTY -> UPDATE_IN_PROGRESS and UPDATE_IN_PROGRESS -> CLEAN happen with
377 * apic_map_lock_held.
378 */
379enum {
380 CLEAN,
381 UPDATE_IN_PROGRESS,
382 DIRTY
383};
384
385static void kvm_recalculate_apic_map(struct kvm *kvm)
386{
387 struct kvm_apic_map *new, *old = NULL;
388 struct kvm_vcpu *vcpu;
389 unsigned long i;
390 u32 max_id = 255; /* enough space for any xAPIC ID */
391 bool xapic_id_mismatch;
392 int r;
393
394 /* Read kvm->arch.apic_map_dirty before kvm->arch.apic_map. */
395 if (atomic_read_acquire(&kvm->arch.apic_map_dirty) == CLEAN)
396 return;
397
398 WARN_ONCE(!irqchip_in_kernel(kvm),
399 "Dirty APIC map without an in-kernel local APIC");
400
401 mutex_lock(&kvm->arch.apic_map_lock);
402
403retry:
404 /*
405 * Read kvm->arch.apic_map_dirty before kvm->arch.apic_map (if clean)
406 * or the APIC registers (if dirty). Note, on retry the map may have
407 * not yet been marked dirty by whatever task changed a vCPU's x2APIC
408 * ID, i.e. the map may still show up as in-progress. In that case
409 * this task still needs to retry and complete its calculation.
410 */
411 if (atomic_cmpxchg_acquire(&kvm->arch.apic_map_dirty,
412 DIRTY, UPDATE_IN_PROGRESS) == CLEAN) {
413 /* Someone else has updated the map. */
414 mutex_unlock(&kvm->arch.apic_map_lock);
415 return;
416 }
417
418 /*
419 * Reset the mismatch flag between attempts so that KVM does the right
420 * thing if a vCPU changes its xAPIC ID, but do NOT reset max_id, i.e.
421 * keep max_id strictly increasing. Disallowing max_id from shrinking
422 * ensures KVM won't get stuck in an infinite loop, e.g. if the vCPU
423 * with the highest x2APIC ID is toggling its APIC on and off.
424 */
425 xapic_id_mismatch = false;
426
427 kvm_for_each_vcpu(i, vcpu, kvm)
428 if (kvm_apic_present(vcpu))
429 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
430
431 new = kvzalloc(sizeof(struct kvm_apic_map) +
432 sizeof(struct kvm_lapic *) * ((u64)max_id + 1),
433 GFP_KERNEL_ACCOUNT);
434
435 if (!new)
436 goto out;
437
438 new->max_apic_id = max_id;
439 new->logical_mode = KVM_APIC_MODE_SW_DISABLED;
440
441 kvm_for_each_vcpu(i, vcpu, kvm) {
442 if (!kvm_apic_present(vcpu))
443 continue;
444
445 r = kvm_recalculate_phys_map(new, vcpu, &xapic_id_mismatch);
446 if (r) {
447 kvfree(new);
448 new = NULL;
449 if (r == -E2BIG) {
450 cond_resched();
451 goto retry;
452 }
453
454 goto out;
455 }
456
457 kvm_recalculate_logical_map(new, vcpu);
458 }
459out:
460 /*
461 * The optimized map is effectively KVM's internal version of APICv,
462 * and all unwanted aliasing that results in disabling the optimized
463 * map also applies to APICv.
464 */
465 if (!new)
466 kvm_set_apicv_inhibit(kvm, APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED);
467 else
468 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED);
469
470 if (!new || new->logical_mode == KVM_APIC_MODE_MAP_DISABLED)
471 kvm_set_apicv_inhibit(kvm, APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED);
472 else
473 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED);
474
475 if (xapic_id_mismatch)
476 kvm_set_apicv_inhibit(kvm, APICV_INHIBIT_REASON_APIC_ID_MODIFIED);
477 else
478 kvm_clear_apicv_inhibit(kvm, APICV_INHIBIT_REASON_APIC_ID_MODIFIED);
479
480 old = rcu_dereference_protected(kvm->arch.apic_map,
481 lockdep_is_held(&kvm->arch.apic_map_lock));
482 rcu_assign_pointer(kvm->arch.apic_map, new);
483 /*
484 * Write kvm->arch.apic_map before clearing apic->apic_map_dirty.
485 * If another update has come in, leave it DIRTY.
486 */
487 atomic_cmpxchg_release(&kvm->arch.apic_map_dirty,
488 UPDATE_IN_PROGRESS, CLEAN);
489 mutex_unlock(&kvm->arch.apic_map_lock);
490
491 if (old)
492 call_rcu(&old->rcu, kvm_apic_map_free);
493
494 kvm_make_scan_ioapic_request(kvm);
495}
496
497static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
498{
499 bool enabled = val & APIC_SPIV_APIC_ENABLED;
500
501 kvm_lapic_set_reg(apic, APIC_SPIV, val);
502
503 if (enabled != apic->sw_enabled) {
504 apic->sw_enabled = enabled;
505 if (enabled)
506 static_branch_slow_dec_deferred(&apic_sw_disabled);
507 else
508 static_branch_inc(&apic_sw_disabled.key);
509
510 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
511 }
512
513 /* Check if there are APF page ready requests pending */
514 if (enabled) {
515 kvm_make_request(KVM_REQ_APF_READY, apic->vcpu);
516 kvm_xen_sw_enable_lapic(apic->vcpu);
517 }
518}
519
520static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
521{
522 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
523 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
524}
525
526static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
527{
528 kvm_lapic_set_reg(apic, APIC_LDR, id);
529 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
530}
531
532static inline void kvm_apic_set_dfr(struct kvm_lapic *apic, u32 val)
533{
534 kvm_lapic_set_reg(apic, APIC_DFR, val);
535 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
536}
537
538static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
539{
540 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
541
542 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
543
544 kvm_lapic_set_reg(apic, APIC_ID, id);
545 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
546 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
547}
548
549static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
550{
551 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
552}
553
554static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
555{
556 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
557}
558
559static inline int apic_lvtt_period(struct kvm_lapic *apic)
560{
561 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
562}
563
564static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
565{
566 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
567}
568
569static inline int apic_lvt_nmi_mode(u32 lvt_val)
570{
571 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
572}
573
574static inline bool kvm_lapic_lvt_supported(struct kvm_lapic *apic, int lvt_index)
575{
576 return apic->nr_lvt_entries > lvt_index;
577}
578
579static inline int kvm_apic_calc_nr_lvt_entries(struct kvm_vcpu *vcpu)
580{
581 return KVM_APIC_MAX_NR_LVT_ENTRIES - !(vcpu->arch.mcg_cap & MCG_CMCI_P);
582}
583
584void kvm_apic_set_version(struct kvm_vcpu *vcpu)
585{
586 struct kvm_lapic *apic = vcpu->arch.apic;
587 u32 v = 0;
588
589 if (!lapic_in_kernel(vcpu))
590 return;
591
592 v = APIC_VERSION | ((apic->nr_lvt_entries - 1) << 16);
593
594 /*
595 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
596 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
597 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
598 * version first and level-triggered interrupts never get EOIed in
599 * IOAPIC.
600 */
601 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) &&
602 !ioapic_in_kernel(vcpu->kvm))
603 v |= APIC_LVR_DIRECTED_EOI;
604 kvm_lapic_set_reg(apic, APIC_LVR, v);
605}
606
607void kvm_apic_after_set_mcg_cap(struct kvm_vcpu *vcpu)
608{
609 int nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu);
610 struct kvm_lapic *apic = vcpu->arch.apic;
611 int i;
612
613 if (!lapic_in_kernel(vcpu) || nr_lvt_entries == apic->nr_lvt_entries)
614 return;
615
616 /* Initialize/mask any "new" LVT entries. */
617 for (i = apic->nr_lvt_entries; i < nr_lvt_entries; i++)
618 kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED);
619
620 apic->nr_lvt_entries = nr_lvt_entries;
621
622 /* The number of LVT entries is reflected in the version register. */
623 kvm_apic_set_version(vcpu);
624}
625
626static const unsigned int apic_lvt_mask[KVM_APIC_MAX_NR_LVT_ENTRIES] = {
627 [LVT_TIMER] = LVT_MASK, /* timer mode mask added at runtime */
628 [LVT_THERMAL_MONITOR] = LVT_MASK | APIC_MODE_MASK,
629 [LVT_PERFORMANCE_COUNTER] = LVT_MASK | APIC_MODE_MASK,
630 [LVT_LINT0] = LINT_MASK,
631 [LVT_LINT1] = LINT_MASK,
632 [LVT_ERROR] = LVT_MASK,
633 [LVT_CMCI] = LVT_MASK | APIC_MODE_MASK
634};
635
636static int find_highest_vector(void *bitmap)
637{
638 int vec;
639 u32 *reg;
640
641 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
642 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
643 reg = bitmap + REG_POS(vec);
644 if (*reg)
645 return __fls(*reg) + vec;
646 }
647
648 return -1;
649}
650
651static u8 count_vectors(void *bitmap)
652{
653 int vec;
654 u32 *reg;
655 u8 count = 0;
656
657 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
658 reg = bitmap + REG_POS(vec);
659 count += hweight32(*reg);
660 }
661
662 return count;
663}
664
665bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
666{
667 u32 i, vec;
668 u32 pir_val, irr_val, prev_irr_val;
669 int max_updated_irr;
670
671 max_updated_irr = -1;
672 *max_irr = -1;
673
674 for (i = vec = 0; i <= 7; i++, vec += 32) {
675 u32 *p_irr = (u32 *)(regs + APIC_IRR + i * 0x10);
676
677 irr_val = *p_irr;
678 pir_val = READ_ONCE(pir[i]);
679
680 if (pir_val) {
681 pir_val = xchg(&pir[i], 0);
682
683 prev_irr_val = irr_val;
684 do {
685 irr_val = prev_irr_val | pir_val;
686 } while (prev_irr_val != irr_val &&
687 !try_cmpxchg(p_irr, &prev_irr_val, irr_val));
688
689 if (prev_irr_val != irr_val)
690 max_updated_irr = __fls(irr_val ^ prev_irr_val) + vec;
691 }
692 if (irr_val)
693 *max_irr = __fls(irr_val) + vec;
694 }
695
696 return ((max_updated_irr != -1) &&
697 (max_updated_irr == *max_irr));
698}
699EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
700
701bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
702{
703 struct kvm_lapic *apic = vcpu->arch.apic;
704 bool irr_updated = __kvm_apic_update_irr(pir, apic->regs, max_irr);
705
706 if (unlikely(!apic->apicv_active && irr_updated))
707 apic->irr_pending = true;
708 return irr_updated;
709}
710EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
711
712static inline int apic_search_irr(struct kvm_lapic *apic)
713{
714 return find_highest_vector(apic->regs + APIC_IRR);
715}
716
717static inline int apic_find_highest_irr(struct kvm_lapic *apic)
718{
719 int result;
720
721 /*
722 * Note that irr_pending is just a hint. It will be always
723 * true with virtual interrupt delivery enabled.
724 */
725 if (!apic->irr_pending)
726 return -1;
727
728 result = apic_search_irr(apic);
729 ASSERT(result == -1 || result >= 16);
730
731 return result;
732}
733
734static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
735{
736 if (unlikely(apic->apicv_active)) {
737 /* need to update RVI */
738 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
739 kvm_x86_call(hwapic_irr_update)(apic->vcpu,
740 apic_find_highest_irr(apic));
741 } else {
742 apic->irr_pending = false;
743 kvm_lapic_clear_vector(vec, apic->regs + APIC_IRR);
744 if (apic_search_irr(apic) != -1)
745 apic->irr_pending = true;
746 }
747}
748
749void kvm_apic_clear_irr(struct kvm_vcpu *vcpu, int vec)
750{
751 apic_clear_irr(vec, vcpu->arch.apic);
752}
753EXPORT_SYMBOL_GPL(kvm_apic_clear_irr);
754
755static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
756{
757 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
758 return;
759
760 /*
761 * With APIC virtualization enabled, all caching is disabled
762 * because the processor can modify ISR under the hood. Instead
763 * just set SVI.
764 */
765 if (unlikely(apic->apicv_active))
766 kvm_x86_call(hwapic_isr_update)(apic->vcpu, vec);
767 else {
768 ++apic->isr_count;
769 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
770 /*
771 * ISR (in service register) bit is set when injecting an interrupt.
772 * The highest vector is injected. Thus the latest bit set matches
773 * the highest bit in ISR.
774 */
775 apic->highest_isr_cache = vec;
776 }
777}
778
779static inline int apic_find_highest_isr(struct kvm_lapic *apic)
780{
781 int result;
782
783 /*
784 * Note that isr_count is always 1, and highest_isr_cache
785 * is always -1, with APIC virtualization enabled.
786 */
787 if (!apic->isr_count)
788 return -1;
789 if (likely(apic->highest_isr_cache != -1))
790 return apic->highest_isr_cache;
791
792 result = find_highest_vector(apic->regs + APIC_ISR);
793 ASSERT(result == -1 || result >= 16);
794
795 return result;
796}
797
798static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
799{
800 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
801 return;
802
803 /*
804 * We do get here for APIC virtualization enabled if the guest
805 * uses the Hyper-V APIC enlightenment. In this case we may need
806 * to trigger a new interrupt delivery by writing the SVI field;
807 * on the other hand isr_count and highest_isr_cache are unused
808 * and must be left alone.
809 */
810 if (unlikely(apic->apicv_active))
811 kvm_x86_call(hwapic_isr_update)(apic->vcpu, apic_find_highest_isr(apic));
812 else {
813 --apic->isr_count;
814 BUG_ON(apic->isr_count < 0);
815 apic->highest_isr_cache = -1;
816 }
817}
818
819void kvm_apic_update_hwapic_isr(struct kvm_vcpu *vcpu)
820{
821 struct kvm_lapic *apic = vcpu->arch.apic;
822
823 if (WARN_ON_ONCE(!lapic_in_kernel(vcpu)) || !apic->apicv_active)
824 return;
825
826 kvm_x86_call(hwapic_isr_update)(vcpu, apic_find_highest_isr(apic));
827}
828EXPORT_SYMBOL_GPL(kvm_apic_update_hwapic_isr);
829
830int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
831{
832 /* This may race with setting of irr in __apic_accept_irq() and
833 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
834 * will cause vmexit immediately and the value will be recalculated
835 * on the next vmentry.
836 */
837 return apic_find_highest_irr(vcpu->arch.apic);
838}
839EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
840
841static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
842 int vector, int level, int trig_mode,
843 struct dest_map *dest_map);
844
845int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
846 struct dest_map *dest_map)
847{
848 struct kvm_lapic *apic = vcpu->arch.apic;
849
850 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
851 irq->level, irq->trig_mode, dest_map);
852}
853
854static int __pv_send_ipi(unsigned long *ipi_bitmap, struct kvm_apic_map *map,
855 struct kvm_lapic_irq *irq, u32 min)
856{
857 int i, count = 0;
858 struct kvm_vcpu *vcpu;
859
860 if (min > map->max_apic_id)
861 return 0;
862
863 for_each_set_bit(i, ipi_bitmap,
864 min((u32)BITS_PER_LONG, (map->max_apic_id - min + 1))) {
865 if (map->phys_map[min + i]) {
866 vcpu = map->phys_map[min + i]->vcpu;
867 count += kvm_apic_set_irq(vcpu, irq, NULL);
868 }
869 }
870
871 return count;
872}
873
874int kvm_pv_send_ipi(struct kvm *kvm, unsigned long ipi_bitmap_low,
875 unsigned long ipi_bitmap_high, u32 min,
876 unsigned long icr, int op_64_bit)
877{
878 struct kvm_apic_map *map;
879 struct kvm_lapic_irq irq = {0};
880 int cluster_size = op_64_bit ? 64 : 32;
881 int count;
882
883 if (icr & (APIC_DEST_MASK | APIC_SHORT_MASK))
884 return -KVM_EINVAL;
885
886 irq.vector = icr & APIC_VECTOR_MASK;
887 irq.delivery_mode = icr & APIC_MODE_MASK;
888 irq.level = (icr & APIC_INT_ASSERT) != 0;
889 irq.trig_mode = icr & APIC_INT_LEVELTRIG;
890
891 rcu_read_lock();
892 map = rcu_dereference(kvm->arch.apic_map);
893
894 count = -EOPNOTSUPP;
895 if (likely(map)) {
896 count = __pv_send_ipi(&ipi_bitmap_low, map, &irq, min);
897 min += cluster_size;
898 count += __pv_send_ipi(&ipi_bitmap_high, map, &irq, min);
899 }
900
901 rcu_read_unlock();
902 return count;
903}
904
905static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
906{
907
908 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
909 sizeof(val));
910}
911
912static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
913{
914
915 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
916 sizeof(*val));
917}
918
919static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
920{
921 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
922}
923
924static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
925{
926 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0)
927 return;
928
929 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
930}
931
932static bool pv_eoi_test_and_clr_pending(struct kvm_vcpu *vcpu)
933{
934 u8 val;
935
936 if (pv_eoi_get_user(vcpu, &val) < 0)
937 return false;
938
939 val &= KVM_PV_EOI_ENABLED;
940
941 if (val && pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0)
942 return false;
943
944 /*
945 * Clear pending bit in any case: it will be set again on vmentry.
946 * While this might not be ideal from performance point of view,
947 * this makes sure pv eoi is only enabled when we know it's safe.
948 */
949 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
950
951 return val;
952}
953
954static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
955{
956 int highest_irr;
957 if (kvm_x86_ops.sync_pir_to_irr)
958 highest_irr = kvm_x86_call(sync_pir_to_irr)(apic->vcpu);
959 else
960 highest_irr = apic_find_highest_irr(apic);
961 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
962 return -1;
963 return highest_irr;
964}
965
966static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
967{
968 u32 tpr, isrv, ppr, old_ppr;
969 int isr;
970
971 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
972 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
973 isr = apic_find_highest_isr(apic);
974 isrv = (isr != -1) ? isr : 0;
975
976 if ((tpr & 0xf0) >= (isrv & 0xf0))
977 ppr = tpr & 0xff;
978 else
979 ppr = isrv & 0xf0;
980
981 *new_ppr = ppr;
982 if (old_ppr != ppr)
983 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
984
985 return ppr < old_ppr;
986}
987
988static void apic_update_ppr(struct kvm_lapic *apic)
989{
990 u32 ppr;
991
992 if (__apic_update_ppr(apic, &ppr) &&
993 apic_has_interrupt_for_ppr(apic, ppr) != -1)
994 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
995}
996
997void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
998{
999 apic_update_ppr(vcpu->arch.apic);
1000}
1001EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
1002
1003static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
1004{
1005 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
1006 apic_update_ppr(apic);
1007}
1008
1009static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
1010{
1011 return mda == (apic_x2apic_mode(apic) ?
1012 X2APIC_BROADCAST : APIC_BROADCAST);
1013}
1014
1015static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
1016{
1017 if (kvm_apic_broadcast(apic, mda))
1018 return true;
1019
1020 /*
1021 * Hotplug hack: Accept interrupts for vCPUs in xAPIC mode as if they
1022 * were in x2APIC mode if the target APIC ID can't be encoded as an
1023 * xAPIC ID. This allows unique addressing of hotplugged vCPUs (which
1024 * start in xAPIC mode) with an APIC ID that is unaddressable in xAPIC
1025 * mode. Match the x2APIC ID if and only if the target APIC ID can't
1026 * be encoded in xAPIC to avoid spurious matches against a vCPU that
1027 * changed its (addressable) xAPIC ID (which is writable).
1028 */
1029 if (apic_x2apic_mode(apic) || mda > 0xff)
1030 return mda == kvm_x2apic_id(apic);
1031
1032 return mda == kvm_xapic_id(apic);
1033}
1034
1035static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
1036{
1037 u32 logical_id;
1038
1039 if (kvm_apic_broadcast(apic, mda))
1040 return true;
1041
1042 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
1043
1044 if (apic_x2apic_mode(apic))
1045 return ((logical_id >> 16) == (mda >> 16))
1046 && (logical_id & mda & 0xffff) != 0;
1047
1048 logical_id = GET_APIC_LOGICAL_ID(logical_id);
1049
1050 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
1051 case APIC_DFR_FLAT:
1052 return (logical_id & mda) != 0;
1053 case APIC_DFR_CLUSTER:
1054 return ((logical_id >> 4) == (mda >> 4))
1055 && (logical_id & mda & 0xf) != 0;
1056 default:
1057 return false;
1058 }
1059}
1060
1061/* The KVM local APIC implementation has two quirks:
1062 *
1063 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
1064 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
1065 * KVM doesn't do that aliasing.
1066 *
1067 * - in-kernel IOAPIC messages have to be delivered directly to
1068 * x2APIC, because the kernel does not support interrupt remapping.
1069 * In order to support broadcast without interrupt remapping, x2APIC
1070 * rewrites the destination of non-IPI messages from APIC_BROADCAST
1071 * to X2APIC_BROADCAST.
1072 *
1073 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
1074 * important when userspace wants to use x2APIC-format MSIs, because
1075 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
1076 */
1077static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
1078 struct kvm_lapic *source, struct kvm_lapic *target)
1079{
1080 bool ipi = source != NULL;
1081
1082 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
1083 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
1084 return X2APIC_BROADCAST;
1085
1086 return dest_id;
1087}
1088
1089bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
1090 int shorthand, unsigned int dest, int dest_mode)
1091{
1092 struct kvm_lapic *target = vcpu->arch.apic;
1093 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
1094
1095 ASSERT(target);
1096 switch (shorthand) {
1097 case APIC_DEST_NOSHORT:
1098 if (dest_mode == APIC_DEST_PHYSICAL)
1099 return kvm_apic_match_physical_addr(target, mda);
1100 else
1101 return kvm_apic_match_logical_addr(target, mda);
1102 case APIC_DEST_SELF:
1103 return target == source;
1104 case APIC_DEST_ALLINC:
1105 return true;
1106 case APIC_DEST_ALLBUT:
1107 return target != source;
1108 default:
1109 return false;
1110 }
1111}
1112EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
1113
1114int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
1115 const unsigned long *bitmap, u32 bitmap_size)
1116{
1117 u32 mod;
1118 int i, idx = -1;
1119
1120 mod = vector % dest_vcpus;
1121
1122 for (i = 0; i <= mod; i++) {
1123 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
1124 BUG_ON(idx == bitmap_size);
1125 }
1126
1127 return idx;
1128}
1129
1130static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
1131{
1132 if (!kvm->arch.disabled_lapic_found) {
1133 kvm->arch.disabled_lapic_found = true;
1134 pr_info("Disabled LAPIC found during irq injection\n");
1135 }
1136}
1137
1138static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
1139 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
1140{
1141 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
1142 if ((irq->dest_id == APIC_BROADCAST &&
1143 map->logical_mode != KVM_APIC_MODE_X2APIC))
1144 return true;
1145 if (irq->dest_id == X2APIC_BROADCAST)
1146 return true;
1147 } else {
1148 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
1149 if (irq->dest_id == (x2apic_ipi ?
1150 X2APIC_BROADCAST : APIC_BROADCAST))
1151 return true;
1152 }
1153
1154 return false;
1155}
1156
1157/* Return true if the interrupt can be handled by using *bitmap as index mask
1158 * for valid destinations in *dst array.
1159 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
1160 * Note: we may have zero kvm_lapic destinations when we return true, which
1161 * means that the interrupt should be dropped. In this case, *bitmap would be
1162 * zero and *dst undefined.
1163 */
1164static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
1165 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
1166 struct kvm_apic_map *map, struct kvm_lapic ***dst,
1167 unsigned long *bitmap)
1168{
1169 int i, lowest;
1170
1171 if (irq->shorthand == APIC_DEST_SELF && src) {
1172 *dst = src;
1173 *bitmap = 1;
1174 return true;
1175 } else if (irq->shorthand)
1176 return false;
1177
1178 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
1179 return false;
1180
1181 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
1182 if (irq->dest_id > map->max_apic_id) {
1183 *bitmap = 0;
1184 } else {
1185 u32 dest_id = array_index_nospec(irq->dest_id, map->max_apic_id + 1);
1186 *dst = &map->phys_map[dest_id];
1187 *bitmap = 1;
1188 }
1189 return true;
1190 }
1191
1192 *bitmap = 0;
1193 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
1194 (u16 *)bitmap))
1195 return false;
1196
1197 if (!kvm_lowest_prio_delivery(irq))
1198 return true;
1199
1200 if (!kvm_vector_hashing_enabled()) {
1201 lowest = -1;
1202 for_each_set_bit(i, bitmap, 16) {
1203 if (!(*dst)[i])
1204 continue;
1205 if (lowest < 0)
1206 lowest = i;
1207 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
1208 (*dst)[lowest]->vcpu) < 0)
1209 lowest = i;
1210 }
1211 } else {
1212 if (!*bitmap)
1213 return true;
1214
1215 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
1216 bitmap, 16);
1217
1218 if (!(*dst)[lowest]) {
1219 kvm_apic_disabled_lapic_found(kvm);
1220 *bitmap = 0;
1221 return true;
1222 }
1223 }
1224
1225 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
1226
1227 return true;
1228}
1229
1230bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
1231 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
1232{
1233 struct kvm_apic_map *map;
1234 unsigned long bitmap;
1235 struct kvm_lapic **dst = NULL;
1236 int i;
1237 bool ret;
1238
1239 *r = -1;
1240
1241 if (irq->shorthand == APIC_DEST_SELF) {
1242 if (KVM_BUG_ON(!src, kvm)) {
1243 *r = 0;
1244 return true;
1245 }
1246 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
1247 return true;
1248 }
1249
1250 rcu_read_lock();
1251 map = rcu_dereference(kvm->arch.apic_map);
1252
1253 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
1254 if (ret) {
1255 *r = 0;
1256 for_each_set_bit(i, &bitmap, 16) {
1257 if (!dst[i])
1258 continue;
1259 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1260 }
1261 }
1262
1263 rcu_read_unlock();
1264 return ret;
1265}
1266
1267/*
1268 * This routine tries to handle interrupts in posted mode, here is how
1269 * it deals with different cases:
1270 * - For single-destination interrupts, handle it in posted mode
1271 * - Else if vector hashing is enabled and it is a lowest-priority
1272 * interrupt, handle it in posted mode and use the following mechanism
1273 * to find the destination vCPU.
1274 * 1. For lowest-priority interrupts, store all the possible
1275 * destination vCPUs in an array.
1276 * 2. Use "guest vector % max number of destination vCPUs" to find
1277 * the right destination vCPU in the array for the lowest-priority
1278 * interrupt.
1279 * - Otherwise, use remapped mode to inject the interrupt.
1280 */
1281bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
1282 struct kvm_vcpu **dest_vcpu)
1283{
1284 struct kvm_apic_map *map;
1285 unsigned long bitmap;
1286 struct kvm_lapic **dst = NULL;
1287 bool ret = false;
1288
1289 if (irq->shorthand)
1290 return false;
1291
1292 rcu_read_lock();
1293 map = rcu_dereference(kvm->arch.apic_map);
1294
1295 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
1296 hweight16(bitmap) == 1) {
1297 unsigned long i = find_first_bit(&bitmap, 16);
1298
1299 if (dst[i]) {
1300 *dest_vcpu = dst[i]->vcpu;
1301 ret = true;
1302 }
1303 }
1304
1305 rcu_read_unlock();
1306 return ret;
1307}
1308
1309/*
1310 * Add a pending IRQ into lapic.
1311 * Return 1 if successfully added and 0 if discarded.
1312 */
1313static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
1314 int vector, int level, int trig_mode,
1315 struct dest_map *dest_map)
1316{
1317 int result = 0;
1318 struct kvm_vcpu *vcpu = apic->vcpu;
1319
1320 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
1321 trig_mode, vector);
1322 switch (delivery_mode) {
1323 case APIC_DM_LOWEST:
1324 vcpu->arch.apic_arb_prio++;
1325 fallthrough;
1326 case APIC_DM_FIXED:
1327 if (unlikely(trig_mode && !level))
1328 break;
1329
1330 /* FIXME add logic for vcpu on reset */
1331 if (unlikely(!apic_enabled(apic)))
1332 break;
1333
1334 result = 1;
1335
1336 if (dest_map) {
1337 __set_bit(vcpu->vcpu_id, dest_map->map);
1338 dest_map->vectors[vcpu->vcpu_id] = vector;
1339 }
1340
1341 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
1342 if (trig_mode)
1343 kvm_lapic_set_vector(vector,
1344 apic->regs + APIC_TMR);
1345 else
1346 kvm_lapic_clear_vector(vector,
1347 apic->regs + APIC_TMR);
1348 }
1349
1350 kvm_x86_call(deliver_interrupt)(apic, delivery_mode,
1351 trig_mode, vector);
1352 break;
1353
1354 case APIC_DM_REMRD:
1355 result = 1;
1356 vcpu->arch.pv.pv_unhalted = 1;
1357 kvm_make_request(KVM_REQ_EVENT, vcpu);
1358 kvm_vcpu_kick(vcpu);
1359 break;
1360
1361 case APIC_DM_SMI:
1362 if (!kvm_inject_smi(vcpu)) {
1363 kvm_vcpu_kick(vcpu);
1364 result = 1;
1365 }
1366 break;
1367
1368 case APIC_DM_NMI:
1369 result = 1;
1370 kvm_inject_nmi(vcpu);
1371 kvm_vcpu_kick(vcpu);
1372 break;
1373
1374 case APIC_DM_INIT:
1375 if (!trig_mode || level) {
1376 result = 1;
1377 /* assumes that there are only KVM_APIC_INIT/SIPI */
1378 apic->pending_events = (1UL << KVM_APIC_INIT);
1379 kvm_make_request(KVM_REQ_EVENT, vcpu);
1380 kvm_vcpu_kick(vcpu);
1381 }
1382 break;
1383
1384 case APIC_DM_STARTUP:
1385 result = 1;
1386 apic->sipi_vector = vector;
1387 /* make sure sipi_vector is visible for the receiver */
1388 smp_wmb();
1389 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1390 kvm_make_request(KVM_REQ_EVENT, vcpu);
1391 kvm_vcpu_kick(vcpu);
1392 break;
1393
1394 case APIC_DM_EXTINT:
1395 /*
1396 * Should only be called by kvm_apic_local_deliver() with LVT0,
1397 * before NMI watchdog was enabled. Already handled by
1398 * kvm_apic_accept_pic_intr().
1399 */
1400 break;
1401
1402 default:
1403 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1404 delivery_mode);
1405 break;
1406 }
1407 return result;
1408}
1409
1410/*
1411 * This routine identifies the destination vcpus mask meant to receive the
1412 * IOAPIC interrupts. It either uses kvm_apic_map_get_dest_lapic() to find
1413 * out the destination vcpus array and set the bitmap or it traverses to
1414 * each available vcpu to identify the same.
1415 */
1416void kvm_bitmap_or_dest_vcpus(struct kvm *kvm, struct kvm_lapic_irq *irq,
1417 unsigned long *vcpu_bitmap)
1418{
1419 struct kvm_lapic **dest_vcpu = NULL;
1420 struct kvm_lapic *src = NULL;
1421 struct kvm_apic_map *map;
1422 struct kvm_vcpu *vcpu;
1423 unsigned long bitmap, i;
1424 int vcpu_idx;
1425 bool ret;
1426
1427 rcu_read_lock();
1428 map = rcu_dereference(kvm->arch.apic_map);
1429
1430 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dest_vcpu,
1431 &bitmap);
1432 if (ret) {
1433 for_each_set_bit(i, &bitmap, 16) {
1434 if (!dest_vcpu[i])
1435 continue;
1436 vcpu_idx = dest_vcpu[i]->vcpu->vcpu_idx;
1437 __set_bit(vcpu_idx, vcpu_bitmap);
1438 }
1439 } else {
1440 kvm_for_each_vcpu(i, vcpu, kvm) {
1441 if (!kvm_apic_present(vcpu))
1442 continue;
1443 if (!kvm_apic_match_dest(vcpu, NULL,
1444 irq->shorthand,
1445 irq->dest_id,
1446 irq->dest_mode))
1447 continue;
1448 __set_bit(i, vcpu_bitmap);
1449 }
1450 }
1451 rcu_read_unlock();
1452}
1453
1454int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1455{
1456 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1457}
1458
1459static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1460{
1461 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1462}
1463
1464static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1465{
1466 int trigger_mode;
1467
1468 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1469 if (!kvm_ioapic_handles_vector(apic, vector))
1470 return;
1471
1472 /* Request a KVM exit to inform the userspace IOAPIC. */
1473 if (irqchip_split(apic->vcpu->kvm)) {
1474 apic->vcpu->arch.pending_ioapic_eoi = vector;
1475 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1476 return;
1477 }
1478
1479 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1480 trigger_mode = IOAPIC_LEVEL_TRIG;
1481 else
1482 trigger_mode = IOAPIC_EDGE_TRIG;
1483
1484 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1485}
1486
1487static int apic_set_eoi(struct kvm_lapic *apic)
1488{
1489 int vector = apic_find_highest_isr(apic);
1490
1491 trace_kvm_eoi(apic, vector);
1492
1493 /*
1494 * Not every write EOI will has corresponding ISR,
1495 * one example is when Kernel check timer on setup_IO_APIC
1496 */
1497 if (vector == -1)
1498 return vector;
1499
1500 apic_clear_isr(vector, apic);
1501 apic_update_ppr(apic);
1502
1503 if (kvm_hv_synic_has_vector(apic->vcpu, vector))
1504 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1505
1506 kvm_ioapic_send_eoi(apic, vector);
1507 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1508 return vector;
1509}
1510
1511/*
1512 * this interface assumes a trap-like exit, which has already finished
1513 * desired side effect including vISR and vPPR update.
1514 */
1515void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1516{
1517 struct kvm_lapic *apic = vcpu->arch.apic;
1518
1519 trace_kvm_eoi(apic, vector);
1520
1521 kvm_ioapic_send_eoi(apic, vector);
1522 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1523}
1524EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1525
1526void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high)
1527{
1528 struct kvm_lapic_irq irq;
1529
1530 /* KVM has no delay and should always clear the BUSY/PENDING flag. */
1531 WARN_ON_ONCE(icr_low & APIC_ICR_BUSY);
1532
1533 irq.vector = icr_low & APIC_VECTOR_MASK;
1534 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1535 irq.dest_mode = icr_low & APIC_DEST_MASK;
1536 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1537 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1538 irq.shorthand = icr_low & APIC_SHORT_MASK;
1539 irq.msi_redir_hint = false;
1540 if (apic_x2apic_mode(apic))
1541 irq.dest_id = icr_high;
1542 else
1543 irq.dest_id = GET_XAPIC_DEST_FIELD(icr_high);
1544
1545 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1546
1547 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1548}
1549EXPORT_SYMBOL_GPL(kvm_apic_send_ipi);
1550
1551static u32 apic_get_tmcct(struct kvm_lapic *apic)
1552{
1553 ktime_t remaining, now;
1554 s64 ns;
1555
1556 ASSERT(apic != NULL);
1557
1558 /* if initial count is 0, current count should also be 0 */
1559 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1560 apic->lapic_timer.period == 0)
1561 return 0;
1562
1563 now = ktime_get();
1564 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1565 if (ktime_to_ns(remaining) < 0)
1566 remaining = 0;
1567
1568 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1569 return div64_u64(ns, (apic->vcpu->kvm->arch.apic_bus_cycle_ns *
1570 apic->divide_count));
1571}
1572
1573static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1574{
1575 struct kvm_vcpu *vcpu = apic->vcpu;
1576 struct kvm_run *run = vcpu->run;
1577
1578 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1579 run->tpr_access.rip = kvm_rip_read(vcpu);
1580 run->tpr_access.is_write = write;
1581}
1582
1583static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1584{
1585 if (apic->vcpu->arch.tpr_access_reporting)
1586 __report_tpr_access(apic, write);
1587}
1588
1589static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1590{
1591 u32 val = 0;
1592
1593 if (offset >= LAPIC_MMIO_LENGTH)
1594 return 0;
1595
1596 switch (offset) {
1597 case APIC_ARBPRI:
1598 break;
1599
1600 case APIC_TMCCT: /* Timer CCR */
1601 if (apic_lvtt_tscdeadline(apic))
1602 return 0;
1603
1604 val = apic_get_tmcct(apic);
1605 break;
1606 case APIC_PROCPRI:
1607 apic_update_ppr(apic);
1608 val = kvm_lapic_get_reg(apic, offset);
1609 break;
1610 case APIC_TASKPRI:
1611 report_tpr_access(apic, false);
1612 fallthrough;
1613 default:
1614 val = kvm_lapic_get_reg(apic, offset);
1615 break;
1616 }
1617
1618 return val;
1619}
1620
1621static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1622{
1623 return container_of(dev, struct kvm_lapic, dev);
1624}
1625
1626#define APIC_REG_MASK(reg) (1ull << ((reg) >> 4))
1627#define APIC_REGS_MASK(first, count) \
1628 (APIC_REG_MASK(first) * ((1ull << (count)) - 1))
1629
1630u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic)
1631{
1632 /* Leave bits '0' for reserved and write-only registers. */
1633 u64 valid_reg_mask =
1634 APIC_REG_MASK(APIC_ID) |
1635 APIC_REG_MASK(APIC_LVR) |
1636 APIC_REG_MASK(APIC_TASKPRI) |
1637 APIC_REG_MASK(APIC_PROCPRI) |
1638 APIC_REG_MASK(APIC_LDR) |
1639 APIC_REG_MASK(APIC_SPIV) |
1640 APIC_REGS_MASK(APIC_ISR, APIC_ISR_NR) |
1641 APIC_REGS_MASK(APIC_TMR, APIC_ISR_NR) |
1642 APIC_REGS_MASK(APIC_IRR, APIC_ISR_NR) |
1643 APIC_REG_MASK(APIC_ESR) |
1644 APIC_REG_MASK(APIC_ICR) |
1645 APIC_REG_MASK(APIC_LVTT) |
1646 APIC_REG_MASK(APIC_LVTTHMR) |
1647 APIC_REG_MASK(APIC_LVTPC) |
1648 APIC_REG_MASK(APIC_LVT0) |
1649 APIC_REG_MASK(APIC_LVT1) |
1650 APIC_REG_MASK(APIC_LVTERR) |
1651 APIC_REG_MASK(APIC_TMICT) |
1652 APIC_REG_MASK(APIC_TMCCT) |
1653 APIC_REG_MASK(APIC_TDCR);
1654
1655 if (kvm_lapic_lvt_supported(apic, LVT_CMCI))
1656 valid_reg_mask |= APIC_REG_MASK(APIC_LVTCMCI);
1657
1658 /* ARBPRI, DFR, and ICR2 are not valid in x2APIC mode. */
1659 if (!apic_x2apic_mode(apic))
1660 valid_reg_mask |= APIC_REG_MASK(APIC_ARBPRI) |
1661 APIC_REG_MASK(APIC_DFR) |
1662 APIC_REG_MASK(APIC_ICR2);
1663
1664 return valid_reg_mask;
1665}
1666EXPORT_SYMBOL_GPL(kvm_lapic_readable_reg_mask);
1667
1668static int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1669 void *data)
1670{
1671 unsigned char alignment = offset & 0xf;
1672 u32 result;
1673
1674 /*
1675 * WARN if KVM reads ICR in x2APIC mode, as it's an 8-byte register in
1676 * x2APIC and needs to be manually handled by the caller.
1677 */
1678 WARN_ON_ONCE(apic_x2apic_mode(apic) && offset == APIC_ICR);
1679
1680 if (alignment + len > 4)
1681 return 1;
1682
1683 if (offset > 0x3f0 ||
1684 !(kvm_lapic_readable_reg_mask(apic) & APIC_REG_MASK(offset)))
1685 return 1;
1686
1687 result = __apic_read(apic, offset & ~0xf);
1688
1689 trace_kvm_apic_read(offset, result);
1690
1691 switch (len) {
1692 case 1:
1693 case 2:
1694 case 4:
1695 memcpy(data, (char *)&result + alignment, len);
1696 break;
1697 default:
1698 printk(KERN_ERR "Local APIC read with len = %x, "
1699 "should be 1,2, or 4 instead\n", len);
1700 break;
1701 }
1702 return 0;
1703}
1704
1705static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1706{
1707 return addr >= apic->base_address &&
1708 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1709}
1710
1711static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1712 gpa_t address, int len, void *data)
1713{
1714 struct kvm_lapic *apic = to_lapic(this);
1715 u32 offset = address - apic->base_address;
1716
1717 if (!apic_mmio_in_range(apic, address))
1718 return -EOPNOTSUPP;
1719
1720 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
1721 if (!kvm_check_has_quirk(vcpu->kvm,
1722 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
1723 return -EOPNOTSUPP;
1724
1725 memset(data, 0xff, len);
1726 return 0;
1727 }
1728
1729 kvm_lapic_reg_read(apic, offset, len, data);
1730
1731 return 0;
1732}
1733
1734static void update_divide_count(struct kvm_lapic *apic)
1735{
1736 u32 tmp1, tmp2, tdcr;
1737
1738 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1739 tmp1 = tdcr & 0xf;
1740 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1741 apic->divide_count = 0x1 << (tmp2 & 0x7);
1742}
1743
1744static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1745{
1746 /*
1747 * Do not allow the guest to program periodic timers with small
1748 * interval, since the hrtimers are not throttled by the host
1749 * scheduler.
1750 */
1751 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1752 s64 min_period = min_timer_period_us * 1000LL;
1753
1754 if (apic->lapic_timer.period < min_period) {
1755 pr_info_once(
1756 "vcpu %i: requested %lld ns "
1757 "lapic timer period limited to %lld ns\n",
1758 apic->vcpu->vcpu_id,
1759 apic->lapic_timer.period, min_period);
1760 apic->lapic_timer.period = min_period;
1761 }
1762 }
1763}
1764
1765static void cancel_hv_timer(struct kvm_lapic *apic);
1766
1767static void cancel_apic_timer(struct kvm_lapic *apic)
1768{
1769 hrtimer_cancel(&apic->lapic_timer.timer);
1770 preempt_disable();
1771 if (apic->lapic_timer.hv_timer_in_use)
1772 cancel_hv_timer(apic);
1773 preempt_enable();
1774 atomic_set(&apic->lapic_timer.pending, 0);
1775}
1776
1777static void apic_update_lvtt(struct kvm_lapic *apic)
1778{
1779 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1780 apic->lapic_timer.timer_mode_mask;
1781
1782 if (apic->lapic_timer.timer_mode != timer_mode) {
1783 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1784 APIC_LVT_TIMER_TSCDEADLINE)) {
1785 cancel_apic_timer(apic);
1786 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1787 apic->lapic_timer.period = 0;
1788 apic->lapic_timer.tscdeadline = 0;
1789 }
1790 apic->lapic_timer.timer_mode = timer_mode;
1791 limit_periodic_timer_frequency(apic);
1792 }
1793}
1794
1795/*
1796 * On APICv, this test will cause a busy wait
1797 * during a higher-priority task.
1798 */
1799
1800static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1801{
1802 struct kvm_lapic *apic = vcpu->arch.apic;
1803 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1804
1805 if (kvm_apic_hw_enabled(apic)) {
1806 int vec = reg & APIC_VECTOR_MASK;
1807 void *bitmap = apic->regs + APIC_ISR;
1808
1809 if (apic->apicv_active)
1810 bitmap = apic->regs + APIC_IRR;
1811
1812 if (apic_test_vector(vec, bitmap))
1813 return true;
1814 }
1815 return false;
1816}
1817
1818static inline void __wait_lapic_expire(struct kvm_vcpu *vcpu, u64 guest_cycles)
1819{
1820 u64 timer_advance_ns = vcpu->arch.apic->lapic_timer.timer_advance_ns;
1821
1822 /*
1823 * If the guest TSC is running at a different ratio than the host, then
1824 * convert the delay to nanoseconds to achieve an accurate delay. Note
1825 * that __delay() uses delay_tsc whenever the hardware has TSC, thus
1826 * always for VMX enabled hardware.
1827 */
1828 if (vcpu->arch.tsc_scaling_ratio == kvm_caps.default_tsc_scaling_ratio) {
1829 __delay(min(guest_cycles,
1830 nsec_to_cycles(vcpu, timer_advance_ns)));
1831 } else {
1832 u64 delay_ns = guest_cycles * 1000000ULL;
1833 do_div(delay_ns, vcpu->arch.virtual_tsc_khz);
1834 ndelay(min_t(u32, delay_ns, timer_advance_ns));
1835 }
1836}
1837
1838static inline void adjust_lapic_timer_advance(struct kvm_vcpu *vcpu,
1839 s64 advance_expire_delta)
1840{
1841 struct kvm_lapic *apic = vcpu->arch.apic;
1842 u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
1843 u64 ns;
1844
1845 /* Do not adjust for tiny fluctuations or large random spikes. */
1846 if (abs(advance_expire_delta) > LAPIC_TIMER_ADVANCE_ADJUST_MAX ||
1847 abs(advance_expire_delta) < LAPIC_TIMER_ADVANCE_ADJUST_MIN)
1848 return;
1849
1850 /* too early */
1851 if (advance_expire_delta < 0) {
1852 ns = -advance_expire_delta * 1000000ULL;
1853 do_div(ns, vcpu->arch.virtual_tsc_khz);
1854 timer_advance_ns -= ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1855 } else {
1856 /* too late */
1857 ns = advance_expire_delta * 1000000ULL;
1858 do_div(ns, vcpu->arch.virtual_tsc_khz);
1859 timer_advance_ns += ns/LAPIC_TIMER_ADVANCE_ADJUST_STEP;
1860 }
1861
1862 if (unlikely(timer_advance_ns > LAPIC_TIMER_ADVANCE_NS_MAX))
1863 timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
1864 apic->lapic_timer.timer_advance_ns = timer_advance_ns;
1865}
1866
1867static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1868{
1869 struct kvm_lapic *apic = vcpu->arch.apic;
1870 u64 guest_tsc, tsc_deadline;
1871
1872 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1873 apic->lapic_timer.expired_tscdeadline = 0;
1874 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1875 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1876
1877 adjust_lapic_timer_advance(vcpu, guest_tsc - tsc_deadline);
1878
1879 /*
1880 * If the timer fired early, reread the TSC to account for the overhead
1881 * of the above adjustment to avoid waiting longer than is necessary.
1882 */
1883 if (guest_tsc < tsc_deadline)
1884 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1885
1886 if (guest_tsc < tsc_deadline)
1887 __wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
1888}
1889
1890void kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
1891{
1892 if (lapic_in_kernel(vcpu) &&
1893 vcpu->arch.apic->lapic_timer.expired_tscdeadline &&
1894 vcpu->arch.apic->lapic_timer.timer_advance_ns &&
1895 lapic_timer_int_injected(vcpu))
1896 __kvm_wait_lapic_expire(vcpu);
1897}
1898EXPORT_SYMBOL_GPL(kvm_wait_lapic_expire);
1899
1900static void kvm_apic_inject_pending_timer_irqs(struct kvm_lapic *apic)
1901{
1902 struct kvm_timer *ktimer = &apic->lapic_timer;
1903
1904 kvm_apic_local_deliver(apic, APIC_LVTT);
1905 if (apic_lvtt_tscdeadline(apic)) {
1906 ktimer->tscdeadline = 0;
1907 } else if (apic_lvtt_oneshot(apic)) {
1908 ktimer->tscdeadline = 0;
1909 ktimer->target_expiration = 0;
1910 }
1911}
1912
1913static void apic_timer_expired(struct kvm_lapic *apic, bool from_timer_fn)
1914{
1915 struct kvm_vcpu *vcpu = apic->vcpu;
1916 struct kvm_timer *ktimer = &apic->lapic_timer;
1917
1918 if (atomic_read(&apic->lapic_timer.pending))
1919 return;
1920
1921 if (apic_lvtt_tscdeadline(apic) || ktimer->hv_timer_in_use)
1922 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1923
1924 if (!from_timer_fn && apic->apicv_active) {
1925 WARN_ON(kvm_get_running_vcpu() != vcpu);
1926 kvm_apic_inject_pending_timer_irqs(apic);
1927 return;
1928 }
1929
1930 if (kvm_use_posted_timer_interrupt(apic->vcpu)) {
1931 /*
1932 * Ensure the guest's timer has truly expired before posting an
1933 * interrupt. Open code the relevant checks to avoid querying
1934 * lapic_timer_int_injected(), which will be false since the
1935 * interrupt isn't yet injected. Waiting until after injecting
1936 * is not an option since that won't help a posted interrupt.
1937 */
1938 if (vcpu->arch.apic->lapic_timer.expired_tscdeadline &&
1939 vcpu->arch.apic->lapic_timer.timer_advance_ns)
1940 __kvm_wait_lapic_expire(vcpu);
1941 kvm_apic_inject_pending_timer_irqs(apic);
1942 return;
1943 }
1944
1945 atomic_inc(&apic->lapic_timer.pending);
1946 kvm_make_request(KVM_REQ_UNBLOCK, vcpu);
1947 if (from_timer_fn)
1948 kvm_vcpu_kick(vcpu);
1949}
1950
1951static void start_sw_tscdeadline(struct kvm_lapic *apic)
1952{
1953 struct kvm_timer *ktimer = &apic->lapic_timer;
1954 u64 guest_tsc, tscdeadline = ktimer->tscdeadline;
1955 u64 ns = 0;
1956 ktime_t expire;
1957 struct kvm_vcpu *vcpu = apic->vcpu;
1958 u32 this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1959 unsigned long flags;
1960 ktime_t now;
1961
1962 if (unlikely(!tscdeadline || !this_tsc_khz))
1963 return;
1964
1965 local_irq_save(flags);
1966
1967 now = ktime_get();
1968 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1969
1970 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1971 do_div(ns, this_tsc_khz);
1972
1973 if (likely(tscdeadline > guest_tsc) &&
1974 likely(ns > apic->lapic_timer.timer_advance_ns)) {
1975 expire = ktime_add_ns(now, ns);
1976 expire = ktime_sub_ns(expire, ktimer->timer_advance_ns);
1977 hrtimer_start(&ktimer->timer, expire, HRTIMER_MODE_ABS_HARD);
1978 } else
1979 apic_timer_expired(apic, false);
1980
1981 local_irq_restore(flags);
1982}
1983
1984static inline u64 tmict_to_ns(struct kvm_lapic *apic, u32 tmict)
1985{
1986 return (u64)tmict * apic->vcpu->kvm->arch.apic_bus_cycle_ns *
1987 (u64)apic->divide_count;
1988}
1989
1990static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1991{
1992 ktime_t now, remaining;
1993 u64 ns_remaining_old, ns_remaining_new;
1994
1995 apic->lapic_timer.period =
1996 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
1997 limit_periodic_timer_frequency(apic);
1998
1999 now = ktime_get();
2000 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
2001 if (ktime_to_ns(remaining) < 0)
2002 remaining = 0;
2003
2004 ns_remaining_old = ktime_to_ns(remaining);
2005 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
2006 apic->divide_count, old_divisor);
2007
2008 apic->lapic_timer.tscdeadline +=
2009 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
2010 nsec_to_cycles(apic->vcpu, ns_remaining_old);
2011 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
2012}
2013
2014static bool set_target_expiration(struct kvm_lapic *apic, u32 count_reg)
2015{
2016 ktime_t now;
2017 u64 tscl = rdtsc();
2018 s64 deadline;
2019
2020 now = ktime_get();
2021 apic->lapic_timer.period =
2022 tmict_to_ns(apic, kvm_lapic_get_reg(apic, APIC_TMICT));
2023
2024 if (!apic->lapic_timer.period) {
2025 apic->lapic_timer.tscdeadline = 0;
2026 return false;
2027 }
2028
2029 limit_periodic_timer_frequency(apic);
2030 deadline = apic->lapic_timer.period;
2031
2032 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
2033 if (unlikely(count_reg != APIC_TMICT)) {
2034 deadline = tmict_to_ns(apic,
2035 kvm_lapic_get_reg(apic, count_reg));
2036 if (unlikely(deadline <= 0)) {
2037 if (apic_lvtt_period(apic))
2038 deadline = apic->lapic_timer.period;
2039 else
2040 deadline = 0;
2041 }
2042 else if (unlikely(deadline > apic->lapic_timer.period)) {
2043 pr_info_ratelimited(
2044 "vcpu %i: requested lapic timer restore with "
2045 "starting count register %#x=%u (%lld ns) > initial count (%lld ns). "
2046 "Using initial count to start timer.\n",
2047 apic->vcpu->vcpu_id,
2048 count_reg,
2049 kvm_lapic_get_reg(apic, count_reg),
2050 deadline, apic->lapic_timer.period);
2051 kvm_lapic_set_reg(apic, count_reg, 0);
2052 deadline = apic->lapic_timer.period;
2053 }
2054 }
2055 }
2056
2057 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
2058 nsec_to_cycles(apic->vcpu, deadline);
2059 apic->lapic_timer.target_expiration = ktime_add_ns(now, deadline);
2060
2061 return true;
2062}
2063
2064static void advance_periodic_target_expiration(struct kvm_lapic *apic)
2065{
2066 ktime_t now = ktime_get();
2067 u64 tscl = rdtsc();
2068 ktime_t delta;
2069
2070 /*
2071 * Synchronize both deadlines to the same time source or
2072 * differences in the periods (caused by differences in the
2073 * underlying clocks or numerical approximation errors) will
2074 * cause the two to drift apart over time as the errors
2075 * accumulate.
2076 */
2077 apic->lapic_timer.target_expiration =
2078 ktime_add_ns(apic->lapic_timer.target_expiration,
2079 apic->lapic_timer.period);
2080 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
2081 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
2082 nsec_to_cycles(apic->vcpu, delta);
2083}
2084
2085static void start_sw_period(struct kvm_lapic *apic)
2086{
2087 if (!apic->lapic_timer.period)
2088 return;
2089
2090 if (ktime_after(ktime_get(),
2091 apic->lapic_timer.target_expiration)) {
2092 apic_timer_expired(apic, false);
2093
2094 if (apic_lvtt_oneshot(apic))
2095 return;
2096
2097 advance_periodic_target_expiration(apic);
2098 }
2099
2100 hrtimer_start(&apic->lapic_timer.timer,
2101 apic->lapic_timer.target_expiration,
2102 HRTIMER_MODE_ABS_HARD);
2103}
2104
2105bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
2106{
2107 if (!lapic_in_kernel(vcpu))
2108 return false;
2109
2110 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
2111}
2112
2113static void cancel_hv_timer(struct kvm_lapic *apic)
2114{
2115 WARN_ON(preemptible());
2116 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
2117 kvm_x86_call(cancel_hv_timer)(apic->vcpu);
2118 apic->lapic_timer.hv_timer_in_use = false;
2119}
2120
2121static bool start_hv_timer(struct kvm_lapic *apic)
2122{
2123 struct kvm_timer *ktimer = &apic->lapic_timer;
2124 struct kvm_vcpu *vcpu = apic->vcpu;
2125 bool expired;
2126
2127 WARN_ON(preemptible());
2128 if (!kvm_can_use_hv_timer(vcpu))
2129 return false;
2130
2131 if (!ktimer->tscdeadline)
2132 return false;
2133
2134 if (kvm_x86_call(set_hv_timer)(vcpu, ktimer->tscdeadline, &expired))
2135 return false;
2136
2137 ktimer->hv_timer_in_use = true;
2138 hrtimer_cancel(&ktimer->timer);
2139
2140 /*
2141 * To simplify handling the periodic timer, leave the hv timer running
2142 * even if the deadline timer has expired, i.e. rely on the resulting
2143 * VM-Exit to recompute the periodic timer's target expiration.
2144 */
2145 if (!apic_lvtt_period(apic)) {
2146 /*
2147 * Cancel the hv timer if the sw timer fired while the hv timer
2148 * was being programmed, or if the hv timer itself expired.
2149 */
2150 if (atomic_read(&ktimer->pending)) {
2151 cancel_hv_timer(apic);
2152 } else if (expired) {
2153 apic_timer_expired(apic, false);
2154 cancel_hv_timer(apic);
2155 }
2156 }
2157
2158 trace_kvm_hv_timer_state(vcpu->vcpu_id, ktimer->hv_timer_in_use);
2159
2160 return true;
2161}
2162
2163static void start_sw_timer(struct kvm_lapic *apic)
2164{
2165 struct kvm_timer *ktimer = &apic->lapic_timer;
2166
2167 WARN_ON(preemptible());
2168 if (apic->lapic_timer.hv_timer_in_use)
2169 cancel_hv_timer(apic);
2170 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
2171 return;
2172
2173 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
2174 start_sw_period(apic);
2175 else if (apic_lvtt_tscdeadline(apic))
2176 start_sw_tscdeadline(apic);
2177 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
2178}
2179
2180static void restart_apic_timer(struct kvm_lapic *apic)
2181{
2182 preempt_disable();
2183
2184 if (!apic_lvtt_period(apic) && atomic_read(&apic->lapic_timer.pending))
2185 goto out;
2186
2187 if (!start_hv_timer(apic))
2188 start_sw_timer(apic);
2189out:
2190 preempt_enable();
2191}
2192
2193void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
2194{
2195 struct kvm_lapic *apic = vcpu->arch.apic;
2196
2197 preempt_disable();
2198 /* If the preempt notifier has already run, it also called apic_timer_expired */
2199 if (!apic->lapic_timer.hv_timer_in_use)
2200 goto out;
2201 WARN_ON(kvm_vcpu_is_blocking(vcpu));
2202 apic_timer_expired(apic, false);
2203 cancel_hv_timer(apic);
2204
2205 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
2206 advance_periodic_target_expiration(apic);
2207 restart_apic_timer(apic);
2208 }
2209out:
2210 preempt_enable();
2211}
2212EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
2213
2214void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
2215{
2216 restart_apic_timer(vcpu->arch.apic);
2217}
2218
2219void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
2220{
2221 struct kvm_lapic *apic = vcpu->arch.apic;
2222
2223 preempt_disable();
2224 /* Possibly the TSC deadline timer is not enabled yet */
2225 if (apic->lapic_timer.hv_timer_in_use)
2226 start_sw_timer(apic);
2227 preempt_enable();
2228}
2229
2230void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
2231{
2232 struct kvm_lapic *apic = vcpu->arch.apic;
2233
2234 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
2235 restart_apic_timer(apic);
2236}
2237
2238static void __start_apic_timer(struct kvm_lapic *apic, u32 count_reg)
2239{
2240 atomic_set(&apic->lapic_timer.pending, 0);
2241
2242 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
2243 && !set_target_expiration(apic, count_reg))
2244 return;
2245
2246 restart_apic_timer(apic);
2247}
2248
2249static void start_apic_timer(struct kvm_lapic *apic)
2250{
2251 __start_apic_timer(apic, APIC_TMICT);
2252}
2253
2254static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
2255{
2256 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
2257
2258 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
2259 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
2260 if (lvt0_in_nmi_mode) {
2261 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
2262 } else
2263 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
2264 }
2265}
2266
2267static int get_lvt_index(u32 reg)
2268{
2269 if (reg == APIC_LVTCMCI)
2270 return LVT_CMCI;
2271 if (reg < APIC_LVTT || reg > APIC_LVTERR)
2272 return -1;
2273 return array_index_nospec(
2274 (reg - APIC_LVTT) >> 4, KVM_APIC_MAX_NR_LVT_ENTRIES);
2275}
2276
2277static int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
2278{
2279 int ret = 0;
2280
2281 trace_kvm_apic_write(reg, val);
2282
2283 switch (reg) {
2284 case APIC_ID: /* Local APIC ID */
2285 if (!apic_x2apic_mode(apic)) {
2286 kvm_apic_set_xapic_id(apic, val >> 24);
2287 } else {
2288 ret = 1;
2289 }
2290 break;
2291
2292 case APIC_TASKPRI:
2293 report_tpr_access(apic, true);
2294 apic_set_tpr(apic, val & 0xff);
2295 break;
2296
2297 case APIC_EOI:
2298 apic_set_eoi(apic);
2299 break;
2300
2301 case APIC_LDR:
2302 if (!apic_x2apic_mode(apic))
2303 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
2304 else
2305 ret = 1;
2306 break;
2307
2308 case APIC_DFR:
2309 if (!apic_x2apic_mode(apic))
2310 kvm_apic_set_dfr(apic, val | 0x0FFFFFFF);
2311 else
2312 ret = 1;
2313 break;
2314
2315 case APIC_SPIV: {
2316 u32 mask = 0x3ff;
2317 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
2318 mask |= APIC_SPIV_DIRECTED_EOI;
2319 apic_set_spiv(apic, val & mask);
2320 if (!(val & APIC_SPIV_APIC_ENABLED)) {
2321 int i;
2322
2323 for (i = 0; i < apic->nr_lvt_entries; i++) {
2324 kvm_lapic_set_reg(apic, APIC_LVTx(i),
2325 kvm_lapic_get_reg(apic, APIC_LVTx(i)) | APIC_LVT_MASKED);
2326 }
2327 apic_update_lvtt(apic);
2328 atomic_set(&apic->lapic_timer.pending, 0);
2329
2330 }
2331 break;
2332 }
2333 case APIC_ICR:
2334 WARN_ON_ONCE(apic_x2apic_mode(apic));
2335
2336 /* No delay here, so we always clear the pending bit */
2337 val &= ~APIC_ICR_BUSY;
2338 kvm_apic_send_ipi(apic, val, kvm_lapic_get_reg(apic, APIC_ICR2));
2339 kvm_lapic_set_reg(apic, APIC_ICR, val);
2340 break;
2341 case APIC_ICR2:
2342 if (apic_x2apic_mode(apic))
2343 ret = 1;
2344 else
2345 kvm_lapic_set_reg(apic, APIC_ICR2, val & 0xff000000);
2346 break;
2347
2348 case APIC_LVT0:
2349 apic_manage_nmi_watchdog(apic, val);
2350 fallthrough;
2351 case APIC_LVTTHMR:
2352 case APIC_LVTPC:
2353 case APIC_LVT1:
2354 case APIC_LVTERR:
2355 case APIC_LVTCMCI: {
2356 u32 index = get_lvt_index(reg);
2357 if (!kvm_lapic_lvt_supported(apic, index)) {
2358 ret = 1;
2359 break;
2360 }
2361 if (!kvm_apic_sw_enabled(apic))
2362 val |= APIC_LVT_MASKED;
2363 val &= apic_lvt_mask[index];
2364 kvm_lapic_set_reg(apic, reg, val);
2365 break;
2366 }
2367
2368 case APIC_LVTT:
2369 if (!kvm_apic_sw_enabled(apic))
2370 val |= APIC_LVT_MASKED;
2371 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
2372 kvm_lapic_set_reg(apic, APIC_LVTT, val);
2373 apic_update_lvtt(apic);
2374 break;
2375
2376 case APIC_TMICT:
2377 if (apic_lvtt_tscdeadline(apic))
2378 break;
2379
2380 cancel_apic_timer(apic);
2381 kvm_lapic_set_reg(apic, APIC_TMICT, val);
2382 start_apic_timer(apic);
2383 break;
2384
2385 case APIC_TDCR: {
2386 uint32_t old_divisor = apic->divide_count;
2387
2388 kvm_lapic_set_reg(apic, APIC_TDCR, val & 0xb);
2389 update_divide_count(apic);
2390 if (apic->divide_count != old_divisor &&
2391 apic->lapic_timer.period) {
2392 hrtimer_cancel(&apic->lapic_timer.timer);
2393 update_target_expiration(apic, old_divisor);
2394 restart_apic_timer(apic);
2395 }
2396 break;
2397 }
2398 case APIC_ESR:
2399 if (apic_x2apic_mode(apic) && val != 0)
2400 ret = 1;
2401 break;
2402
2403 case APIC_SELF_IPI:
2404 /*
2405 * Self-IPI exists only when x2APIC is enabled. Bits 7:0 hold
2406 * the vector, everything else is reserved.
2407 */
2408 if (!apic_x2apic_mode(apic) || (val & ~APIC_VECTOR_MASK))
2409 ret = 1;
2410 else
2411 kvm_apic_send_ipi(apic, APIC_DEST_SELF | val, 0);
2412 break;
2413 default:
2414 ret = 1;
2415 break;
2416 }
2417
2418 /*
2419 * Recalculate APIC maps if necessary, e.g. if the software enable bit
2420 * was toggled, the APIC ID changed, etc... The maps are marked dirty
2421 * on relevant changes, i.e. this is a nop for most writes.
2422 */
2423 kvm_recalculate_apic_map(apic->vcpu->kvm);
2424
2425 return ret;
2426}
2427
2428static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
2429 gpa_t address, int len, const void *data)
2430{
2431 struct kvm_lapic *apic = to_lapic(this);
2432 unsigned int offset = address - apic->base_address;
2433 u32 val;
2434
2435 if (!apic_mmio_in_range(apic, address))
2436 return -EOPNOTSUPP;
2437
2438 if (!kvm_apic_hw_enabled(apic) || apic_x2apic_mode(apic)) {
2439 if (!kvm_check_has_quirk(vcpu->kvm,
2440 KVM_X86_QUIRK_LAPIC_MMIO_HOLE))
2441 return -EOPNOTSUPP;
2442
2443 return 0;
2444 }
2445
2446 /*
2447 * APIC register must be aligned on 128-bits boundary.
2448 * 32/64/128 bits registers must be accessed thru 32 bits.
2449 * Refer SDM 8.4.1
2450 */
2451 if (len != 4 || (offset & 0xf))
2452 return 0;
2453
2454 val = *(u32*)data;
2455
2456 kvm_lapic_reg_write(apic, offset & 0xff0, val);
2457
2458 return 0;
2459}
2460
2461void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
2462{
2463 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
2464}
2465EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
2466
2467#define X2APIC_ICR_RESERVED_BITS (GENMASK_ULL(31, 20) | GENMASK_ULL(17, 16) | BIT(13))
2468
2469int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data)
2470{
2471 if (data & X2APIC_ICR_RESERVED_BITS)
2472 return 1;
2473
2474 /*
2475 * The BUSY bit is reserved on both Intel and AMD in x2APIC mode, but
2476 * only AMD requires it to be zero, Intel essentially just ignores the
2477 * bit. And if IPI virtualization (Intel) or x2AVIC (AMD) is enabled,
2478 * the CPU performs the reserved bits checks, i.e. the underlying CPU
2479 * behavior will "win". Arbitrarily clear the BUSY bit, as there is no
2480 * sane way to provide consistent behavior with respect to hardware.
2481 */
2482 data &= ~APIC_ICR_BUSY;
2483
2484 kvm_apic_send_ipi(apic, (u32)data, (u32)(data >> 32));
2485 if (kvm_x86_ops.x2apic_icr_is_split) {
2486 kvm_lapic_set_reg(apic, APIC_ICR, data);
2487 kvm_lapic_set_reg(apic, APIC_ICR2, data >> 32);
2488 } else {
2489 kvm_lapic_set_reg64(apic, APIC_ICR, data);
2490 }
2491 trace_kvm_apic_write(APIC_ICR, data);
2492 return 0;
2493}
2494
2495static u64 kvm_x2apic_icr_read(struct kvm_lapic *apic)
2496{
2497 if (kvm_x86_ops.x2apic_icr_is_split)
2498 return (u64)kvm_lapic_get_reg(apic, APIC_ICR) |
2499 (u64)kvm_lapic_get_reg(apic, APIC_ICR2) << 32;
2500
2501 return kvm_lapic_get_reg64(apic, APIC_ICR);
2502}
2503
2504/* emulate APIC access in a trap manner */
2505void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
2506{
2507 struct kvm_lapic *apic = vcpu->arch.apic;
2508
2509 /*
2510 * ICR is a single 64-bit register when x2APIC is enabled, all others
2511 * registers hold 32-bit values. For legacy xAPIC, ICR writes need to
2512 * go down the common path to get the upper half from ICR2.
2513 *
2514 * Note, using the write helpers may incur an unnecessary write to the
2515 * virtual APIC state, but KVM needs to conditionally modify the value
2516 * in certain cases, e.g. to clear the ICR busy bit. The cost of extra
2517 * conditional branches is likely a wash relative to the cost of the
2518 * maybe-unecessary write, and both are in the noise anyways.
2519 */
2520 if (apic_x2apic_mode(apic) && offset == APIC_ICR)
2521 WARN_ON_ONCE(kvm_x2apic_icr_write(apic, kvm_x2apic_icr_read(apic)));
2522 else
2523 kvm_lapic_reg_write(apic, offset, kvm_lapic_get_reg(apic, offset));
2524}
2525EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
2526
2527void kvm_free_lapic(struct kvm_vcpu *vcpu)
2528{
2529 struct kvm_lapic *apic = vcpu->arch.apic;
2530
2531 if (!vcpu->arch.apic) {
2532 static_branch_dec(&kvm_has_noapic_vcpu);
2533 return;
2534 }
2535
2536 hrtimer_cancel(&apic->lapic_timer.timer);
2537
2538 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
2539 static_branch_slow_dec_deferred(&apic_hw_disabled);
2540
2541 if (!apic->sw_enabled)
2542 static_branch_slow_dec_deferred(&apic_sw_disabled);
2543
2544 if (apic->regs)
2545 free_page((unsigned long)apic->regs);
2546
2547 kfree(apic);
2548}
2549
2550/*
2551 *----------------------------------------------------------------------
2552 * LAPIC interface
2553 *----------------------------------------------------------------------
2554 */
2555u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
2556{
2557 struct kvm_lapic *apic = vcpu->arch.apic;
2558
2559 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
2560 return 0;
2561
2562 return apic->lapic_timer.tscdeadline;
2563}
2564
2565void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
2566{
2567 struct kvm_lapic *apic = vcpu->arch.apic;
2568
2569 if (!kvm_apic_present(vcpu) || !apic_lvtt_tscdeadline(apic))
2570 return;
2571
2572 hrtimer_cancel(&apic->lapic_timer.timer);
2573 apic->lapic_timer.tscdeadline = data;
2574 start_apic_timer(apic);
2575}
2576
2577void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
2578{
2579 apic_set_tpr(vcpu->arch.apic, (cr8 & 0x0f) << 4);
2580}
2581
2582u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
2583{
2584 u64 tpr;
2585
2586 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
2587
2588 return (tpr & 0xf0) >> 4;
2589}
2590
2591static void __kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value)
2592{
2593 u64 old_value = vcpu->arch.apic_base;
2594 struct kvm_lapic *apic = vcpu->arch.apic;
2595
2596 vcpu->arch.apic_base = value;
2597
2598 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
2599 kvm_update_cpuid_runtime(vcpu);
2600
2601 if (!apic)
2602 return;
2603
2604 /* update jump label if enable bit changes */
2605 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
2606 if (value & MSR_IA32_APICBASE_ENABLE) {
2607 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2608 static_branch_slow_dec_deferred(&apic_hw_disabled);
2609 /* Check if there are APF page ready requests pending */
2610 kvm_make_request(KVM_REQ_APF_READY, vcpu);
2611 } else {
2612 static_branch_inc(&apic_hw_disabled.key);
2613 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
2614 }
2615 }
2616
2617 if ((old_value ^ value) & X2APIC_ENABLE) {
2618 if (value & X2APIC_ENABLE)
2619 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2620 else if (value & MSR_IA32_APICBASE_ENABLE)
2621 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2622 }
2623
2624 if ((old_value ^ value) & (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) {
2625 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
2626 kvm_x86_call(set_virtual_apic_mode)(vcpu);
2627 }
2628
2629 apic->base_address = apic->vcpu->arch.apic_base &
2630 MSR_IA32_APICBASE_BASE;
2631
2632 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2633 apic->base_address != APIC_DEFAULT_PHYS_BASE) {
2634 kvm_set_apicv_inhibit(apic->vcpu->kvm,
2635 APICV_INHIBIT_REASON_APIC_BASE_MODIFIED);
2636 }
2637}
2638
2639int kvm_apic_set_base(struct kvm_vcpu *vcpu, u64 value, bool host_initiated)
2640{
2641 enum lapic_mode old_mode = kvm_get_apic_mode(vcpu);
2642 enum lapic_mode new_mode = kvm_apic_mode(value);
2643
2644 if (vcpu->arch.apic_base == value)
2645 return 0;
2646
2647 u64 reserved_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu) | 0x2ff |
2648 (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC) ? 0 : X2APIC_ENABLE);
2649
2650 if ((value & reserved_bits) != 0 || new_mode == LAPIC_MODE_INVALID)
2651 return 1;
2652 if (!host_initiated) {
2653 if (old_mode == LAPIC_MODE_X2APIC && new_mode == LAPIC_MODE_XAPIC)
2654 return 1;
2655 if (old_mode == LAPIC_MODE_DISABLED && new_mode == LAPIC_MODE_X2APIC)
2656 return 1;
2657 }
2658
2659 __kvm_apic_set_base(vcpu, value);
2660 kvm_recalculate_apic_map(vcpu->kvm);
2661 return 0;
2662}
2663
2664void kvm_apic_update_apicv(struct kvm_vcpu *vcpu)
2665{
2666 struct kvm_lapic *apic = vcpu->arch.apic;
2667
2668 /*
2669 * When APICv is enabled, KVM must always search the IRR for a pending
2670 * IRQ, as other vCPUs and devices can set IRR bits even if the vCPU
2671 * isn't running. If APICv is disabled, KVM _should_ search the IRR
2672 * for a pending IRQ. But KVM currently doesn't ensure *all* hardware,
2673 * e.g. CPUs and IOMMUs, has seen the change in state, i.e. searching
2674 * the IRR at this time could race with IRQ delivery from hardware that
2675 * still sees APICv as being enabled.
2676 *
2677 * FIXME: Ensure other vCPUs and devices observe the change in APICv
2678 * state prior to updating KVM's metadata caches, so that KVM
2679 * can safely search the IRR and set irr_pending accordingly.
2680 */
2681 apic->irr_pending = true;
2682
2683 if (apic->apicv_active)
2684 apic->isr_count = 1;
2685 else
2686 apic->isr_count = count_vectors(apic->regs + APIC_ISR);
2687
2688 apic->highest_isr_cache = -1;
2689}
2690
2691int kvm_alloc_apic_access_page(struct kvm *kvm)
2692{
2693 void __user *hva;
2694 int ret = 0;
2695
2696 mutex_lock(&kvm->slots_lock);
2697 if (kvm->arch.apic_access_memslot_enabled ||
2698 kvm->arch.apic_access_memslot_inhibited)
2699 goto out;
2700
2701 hva = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
2702 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
2703 if (IS_ERR(hva)) {
2704 ret = PTR_ERR(hva);
2705 goto out;
2706 }
2707
2708 kvm->arch.apic_access_memslot_enabled = true;
2709out:
2710 mutex_unlock(&kvm->slots_lock);
2711 return ret;
2712}
2713EXPORT_SYMBOL_GPL(kvm_alloc_apic_access_page);
2714
2715void kvm_inhibit_apic_access_page(struct kvm_vcpu *vcpu)
2716{
2717 struct kvm *kvm = vcpu->kvm;
2718
2719 if (!kvm->arch.apic_access_memslot_enabled)
2720 return;
2721
2722 kvm_vcpu_srcu_read_unlock(vcpu);
2723
2724 mutex_lock(&kvm->slots_lock);
2725
2726 if (kvm->arch.apic_access_memslot_enabled) {
2727 __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT, 0, 0);
2728 /*
2729 * Clear "enabled" after the memslot is deleted so that a
2730 * different vCPU doesn't get a false negative when checking
2731 * the flag out of slots_lock. No additional memory barrier is
2732 * needed as modifying memslots requires waiting other vCPUs to
2733 * drop SRCU (see above), and false positives are ok as the
2734 * flag is rechecked after acquiring slots_lock.
2735 */
2736 kvm->arch.apic_access_memslot_enabled = false;
2737
2738 /*
2739 * Mark the memslot as inhibited to prevent reallocating the
2740 * memslot during vCPU creation, e.g. if a vCPU is hotplugged.
2741 */
2742 kvm->arch.apic_access_memslot_inhibited = true;
2743 }
2744
2745 mutex_unlock(&kvm->slots_lock);
2746
2747 kvm_vcpu_srcu_read_lock(vcpu);
2748}
2749
2750void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2751{
2752 struct kvm_lapic *apic = vcpu->arch.apic;
2753 u64 msr_val;
2754 int i;
2755
2756 kvm_x86_call(apicv_pre_state_restore)(vcpu);
2757
2758 if (!init_event) {
2759 msr_val = APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE;
2760 if (kvm_vcpu_is_reset_bsp(vcpu))
2761 msr_val |= MSR_IA32_APICBASE_BSP;
2762
2763 /*
2764 * Use the inner helper to avoid an extra recalcuation of the
2765 * optimized APIC map if some other task has dirtied the map.
2766 * The recalculation needed for this vCPU will be done after
2767 * all APIC state has been initialized (see below).
2768 */
2769 __kvm_apic_set_base(vcpu, msr_val);
2770 }
2771
2772 if (!apic)
2773 return;
2774
2775 /* Stop the timer in case it's a reset to an active apic */
2776 hrtimer_cancel(&apic->lapic_timer.timer);
2777
2778 /* The xAPIC ID is set at RESET even if the APIC was already enabled. */
2779 if (!init_event)
2780 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2781 kvm_apic_set_version(apic->vcpu);
2782
2783 for (i = 0; i < apic->nr_lvt_entries; i++)
2784 kvm_lapic_set_reg(apic, APIC_LVTx(i), APIC_LVT_MASKED);
2785 apic_update_lvtt(apic);
2786 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2787 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2788 kvm_lapic_set_reg(apic, APIC_LVT0,
2789 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2790 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2791
2792 kvm_apic_set_dfr(apic, 0xffffffffU);
2793 apic_set_spiv(apic, 0xff);
2794 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2795 if (!apic_x2apic_mode(apic))
2796 kvm_apic_set_ldr(apic, 0);
2797 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2798 if (!apic_x2apic_mode(apic)) {
2799 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2800 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2801 } else {
2802 kvm_lapic_set_reg64(apic, APIC_ICR, 0);
2803 }
2804 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2805 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2806 for (i = 0; i < 8; i++) {
2807 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2808 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2809 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2810 }
2811 kvm_apic_update_apicv(vcpu);
2812 update_divide_count(apic);
2813 atomic_set(&apic->lapic_timer.pending, 0);
2814
2815 vcpu->arch.pv_eoi.msr_val = 0;
2816 apic_update_ppr(apic);
2817 if (apic->apicv_active) {
2818 kvm_x86_call(apicv_post_state_restore)(vcpu);
2819 kvm_x86_call(hwapic_irr_update)(vcpu, -1);
2820 kvm_x86_call(hwapic_isr_update)(vcpu, -1);
2821 }
2822
2823 vcpu->arch.apic_arb_prio = 0;
2824 vcpu->arch.apic_attention = 0;
2825
2826 kvm_recalculate_apic_map(vcpu->kvm);
2827}
2828
2829/*
2830 *----------------------------------------------------------------------
2831 * timer interface
2832 *----------------------------------------------------------------------
2833 */
2834
2835static bool lapic_is_periodic(struct kvm_lapic *apic)
2836{
2837 return apic_lvtt_period(apic);
2838}
2839
2840int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2841{
2842 struct kvm_lapic *apic = vcpu->arch.apic;
2843
2844 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2845 return atomic_read(&apic->lapic_timer.pending);
2846
2847 return 0;
2848}
2849
2850int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2851{
2852 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2853 int vector, mode, trig_mode;
2854 int r;
2855
2856 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2857 vector = reg & APIC_VECTOR_MASK;
2858 mode = reg & APIC_MODE_MASK;
2859 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2860
2861 r = __apic_accept_irq(apic, mode, vector, 1, trig_mode, NULL);
2862 if (r && lvt_type == APIC_LVTPC &&
2863 guest_cpuid_is_intel_compatible(apic->vcpu))
2864 kvm_lapic_set_reg(apic, APIC_LVTPC, reg | APIC_LVT_MASKED);
2865 return r;
2866 }
2867 return 0;
2868}
2869
2870void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2871{
2872 struct kvm_lapic *apic = vcpu->arch.apic;
2873
2874 if (apic)
2875 kvm_apic_local_deliver(apic, APIC_LVT0);
2876}
2877
2878static const struct kvm_io_device_ops apic_mmio_ops = {
2879 .read = apic_mmio_read,
2880 .write = apic_mmio_write,
2881};
2882
2883static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2884{
2885 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2886 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2887
2888 apic_timer_expired(apic, true);
2889
2890 if (lapic_is_periodic(apic)) {
2891 advance_periodic_target_expiration(apic);
2892 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2893 return HRTIMER_RESTART;
2894 } else
2895 return HRTIMER_NORESTART;
2896}
2897
2898int kvm_create_lapic(struct kvm_vcpu *vcpu)
2899{
2900 struct kvm_lapic *apic;
2901
2902 ASSERT(vcpu != NULL);
2903
2904 if (!irqchip_in_kernel(vcpu->kvm)) {
2905 static_branch_inc(&kvm_has_noapic_vcpu);
2906 return 0;
2907 }
2908
2909 apic = kzalloc(sizeof(*apic), GFP_KERNEL_ACCOUNT);
2910 if (!apic)
2911 goto nomem;
2912
2913 vcpu->arch.apic = apic;
2914
2915 if (kvm_x86_ops.alloc_apic_backing_page)
2916 apic->regs = kvm_x86_call(alloc_apic_backing_page)(vcpu);
2917 else
2918 apic->regs = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
2919 if (!apic->regs) {
2920 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2921 vcpu->vcpu_id);
2922 goto nomem_free_apic;
2923 }
2924 apic->vcpu = vcpu;
2925
2926 apic->nr_lvt_entries = kvm_apic_calc_nr_lvt_entries(vcpu);
2927
2928 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2929 HRTIMER_MODE_ABS_HARD);
2930 apic->lapic_timer.timer.function = apic_timer_fn;
2931 if (lapic_timer_advance)
2932 apic->lapic_timer.timer_advance_ns = LAPIC_TIMER_ADVANCE_NS_INIT;
2933
2934 /*
2935 * Stuff the APIC ENABLE bit in lieu of temporarily incrementing
2936 * apic_hw_disabled; the full RESET value is set by kvm_lapic_reset().
2937 */
2938 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2939 static_branch_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2940 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2941
2942 /*
2943 * Defer evaluating inhibits until the vCPU is first run, as this vCPU
2944 * will not get notified of any changes until this vCPU is visible to
2945 * other vCPUs (marked online and added to the set of vCPUs).
2946 *
2947 * Opportunistically mark APICv active as VMX in particularly is highly
2948 * unlikely to have inhibits. Ignore the current per-VM APICv state so
2949 * that vCPU creation is guaranteed to run with a deterministic value,
2950 * the request will ensure the vCPU gets the correct state before VM-Entry.
2951 */
2952 if (enable_apicv) {
2953 apic->apicv_active = true;
2954 kvm_make_request(KVM_REQ_APICV_UPDATE, vcpu);
2955 }
2956
2957 return 0;
2958nomem_free_apic:
2959 kfree(apic);
2960 vcpu->arch.apic = NULL;
2961nomem:
2962 return -ENOMEM;
2963}
2964
2965int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2966{
2967 struct kvm_lapic *apic = vcpu->arch.apic;
2968 u32 ppr;
2969
2970 if (!kvm_apic_present(vcpu))
2971 return -1;
2972
2973 __apic_update_ppr(apic, &ppr);
2974 return apic_has_interrupt_for_ppr(apic, ppr);
2975}
2976EXPORT_SYMBOL_GPL(kvm_apic_has_interrupt);
2977
2978int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2979{
2980 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2981
2982 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2983 return 1;
2984 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2985 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2986 return 1;
2987 return 0;
2988}
2989
2990void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2991{
2992 struct kvm_lapic *apic = vcpu->arch.apic;
2993
2994 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2995 kvm_apic_inject_pending_timer_irqs(apic);
2996 atomic_set(&apic->lapic_timer.pending, 0);
2997 }
2998}
2999
3000void kvm_apic_ack_interrupt(struct kvm_vcpu *vcpu, int vector)
3001{
3002 struct kvm_lapic *apic = vcpu->arch.apic;
3003 u32 ppr;
3004
3005 if (WARN_ON_ONCE(vector < 0 || !apic))
3006 return;
3007
3008 /*
3009 * We get here even with APIC virtualization enabled, if doing
3010 * nested virtualization and L1 runs with the "acknowledge interrupt
3011 * on exit" mode. Then we cannot inject the interrupt via RVI,
3012 * because the process would deliver it through the IDT.
3013 */
3014
3015 apic_clear_irr(vector, apic);
3016 if (kvm_hv_synic_auto_eoi_set(vcpu, vector)) {
3017 /*
3018 * For auto-EOI interrupts, there might be another pending
3019 * interrupt above PPR, so check whether to raise another
3020 * KVM_REQ_EVENT.
3021 */
3022 apic_update_ppr(apic);
3023 } else {
3024 /*
3025 * For normal interrupts, PPR has been raised and there cannot
3026 * be a higher-priority pending interrupt---except if there was
3027 * a concurrent interrupt injection, but that would have
3028 * triggered KVM_REQ_EVENT already.
3029 */
3030 apic_set_isr(vector, apic);
3031 __apic_update_ppr(apic, &ppr);
3032 }
3033
3034}
3035EXPORT_SYMBOL_GPL(kvm_apic_ack_interrupt);
3036
3037static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
3038 struct kvm_lapic_state *s, bool set)
3039{
3040 if (apic_x2apic_mode(vcpu->arch.apic)) {
3041 u32 x2apic_id = kvm_x2apic_id(vcpu->arch.apic);
3042 u32 *id = (u32 *)(s->regs + APIC_ID);
3043 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
3044 u64 icr;
3045
3046 if (vcpu->kvm->arch.x2apic_format) {
3047 if (*id != x2apic_id)
3048 return -EINVAL;
3049 } else {
3050 /*
3051 * Ignore the userspace value when setting APIC state.
3052 * KVM's model is that the x2APIC ID is readonly, e.g.
3053 * KVM only supports delivering interrupts to KVM's
3054 * version of the x2APIC ID. However, for backwards
3055 * compatibility, don't reject attempts to set a
3056 * mismatched ID for userspace that hasn't opted into
3057 * x2apic_format.
3058 */
3059 if (set)
3060 *id = x2apic_id;
3061 else
3062 *id = x2apic_id << 24;
3063 }
3064
3065 /*
3066 * In x2APIC mode, the LDR is fixed and based on the id. And
3067 * if the ICR is _not_ split, ICR is internally a single 64-bit
3068 * register, but needs to be split to ICR+ICR2 in userspace for
3069 * backwards compatibility.
3070 */
3071 if (set)
3072 *ldr = kvm_apic_calc_x2apic_ldr(x2apic_id);
3073
3074 if (!kvm_x86_ops.x2apic_icr_is_split) {
3075 if (set) {
3076 icr = __kvm_lapic_get_reg(s->regs, APIC_ICR) |
3077 (u64)__kvm_lapic_get_reg(s->regs, APIC_ICR2) << 32;
3078 __kvm_lapic_set_reg64(s->regs, APIC_ICR, icr);
3079 } else {
3080 icr = __kvm_lapic_get_reg64(s->regs, APIC_ICR);
3081 __kvm_lapic_set_reg(s->regs, APIC_ICR2, icr >> 32);
3082 }
3083 }
3084 }
3085
3086 return 0;
3087}
3088
3089int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
3090{
3091 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
3092
3093 /*
3094 * Get calculated timer current count for remaining timer period (if
3095 * any) and store it in the returned register set.
3096 */
3097 __kvm_lapic_set_reg(s->regs, APIC_TMCCT,
3098 __apic_read(vcpu->arch.apic, APIC_TMCCT));
3099
3100 return kvm_apic_state_fixup(vcpu, s, false);
3101}
3102
3103int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
3104{
3105 struct kvm_lapic *apic = vcpu->arch.apic;
3106 int r;
3107
3108 kvm_x86_call(apicv_pre_state_restore)(vcpu);
3109
3110 /* set SPIV separately to get count of SW disabled APICs right */
3111 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
3112
3113 r = kvm_apic_state_fixup(vcpu, s, true);
3114 if (r) {
3115 kvm_recalculate_apic_map(vcpu->kvm);
3116 return r;
3117 }
3118 memcpy(vcpu->arch.apic->regs, s->regs, sizeof(*s));
3119
3120 atomic_set_release(&apic->vcpu->kvm->arch.apic_map_dirty, DIRTY);
3121 kvm_recalculate_apic_map(vcpu->kvm);
3122 kvm_apic_set_version(vcpu);
3123
3124 apic_update_ppr(apic);
3125 cancel_apic_timer(apic);
3126 apic->lapic_timer.expired_tscdeadline = 0;
3127 apic_update_lvtt(apic);
3128 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
3129 update_divide_count(apic);
3130 __start_apic_timer(apic, APIC_TMCCT);
3131 kvm_lapic_set_reg(apic, APIC_TMCCT, 0);
3132 kvm_apic_update_apicv(vcpu);
3133 if (apic->apicv_active) {
3134 kvm_x86_call(apicv_post_state_restore)(vcpu);
3135 kvm_x86_call(hwapic_irr_update)(vcpu, apic_find_highest_irr(apic));
3136 kvm_x86_call(hwapic_isr_update)(vcpu, apic_find_highest_isr(apic));
3137 }
3138 kvm_make_request(KVM_REQ_EVENT, vcpu);
3139 if (ioapic_in_kernel(vcpu->kvm))
3140 kvm_rtc_eoi_tracking_restore_one(vcpu);
3141
3142 vcpu->arch.apic_arb_prio = 0;
3143
3144 return 0;
3145}
3146
3147void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
3148{
3149 struct hrtimer *timer;
3150
3151 if (!lapic_in_kernel(vcpu) ||
3152 kvm_can_post_timer_interrupt(vcpu))
3153 return;
3154
3155 timer = &vcpu->arch.apic->lapic_timer.timer;
3156 if (hrtimer_cancel(timer))
3157 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_HARD);
3158}
3159
3160/*
3161 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
3162 *
3163 * Detect whether guest triggered PV EOI since the
3164 * last entry. If yes, set EOI on guests's behalf.
3165 * Clear PV EOI in guest memory in any case.
3166 */
3167static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
3168 struct kvm_lapic *apic)
3169{
3170 int vector;
3171 /*
3172 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
3173 * and KVM_PV_EOI_ENABLED in guest memory as follows:
3174 *
3175 * KVM_APIC_PV_EOI_PENDING is unset:
3176 * -> host disabled PV EOI.
3177 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
3178 * -> host enabled PV EOI, guest did not execute EOI yet.
3179 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
3180 * -> host enabled PV EOI, guest executed EOI.
3181 */
3182 BUG_ON(!pv_eoi_enabled(vcpu));
3183
3184 if (pv_eoi_test_and_clr_pending(vcpu))
3185 return;
3186 vector = apic_set_eoi(apic);
3187 trace_kvm_pv_eoi(apic, vector);
3188}
3189
3190void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
3191{
3192 u32 data;
3193
3194 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
3195 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
3196
3197 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
3198 return;
3199
3200 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
3201 sizeof(u32)))
3202 return;
3203
3204 apic_set_tpr(vcpu->arch.apic, data & 0xff);
3205}
3206
3207/*
3208 * apic_sync_pv_eoi_to_guest - called before vmentry
3209 *
3210 * Detect whether it's safe to enable PV EOI and
3211 * if yes do so.
3212 */
3213static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
3214 struct kvm_lapic *apic)
3215{
3216 if (!pv_eoi_enabled(vcpu) ||
3217 /* IRR set or many bits in ISR: could be nested. */
3218 apic->irr_pending ||
3219 /* Cache not set: could be safe but we don't bother. */
3220 apic->highest_isr_cache == -1 ||
3221 /* Need EOI to update ioapic. */
3222 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
3223 /*
3224 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
3225 * so we need not do anything here.
3226 */
3227 return;
3228 }
3229
3230 pv_eoi_set_pending(apic->vcpu);
3231}
3232
3233void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
3234{
3235 u32 data, tpr;
3236 int max_irr, max_isr;
3237 struct kvm_lapic *apic = vcpu->arch.apic;
3238
3239 apic_sync_pv_eoi_to_guest(vcpu, apic);
3240
3241 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
3242 return;
3243
3244 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
3245 max_irr = apic_find_highest_irr(apic);
3246 if (max_irr < 0)
3247 max_irr = 0;
3248 max_isr = apic_find_highest_isr(apic);
3249 if (max_isr < 0)
3250 max_isr = 0;
3251 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
3252
3253 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
3254 sizeof(u32));
3255}
3256
3257int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
3258{
3259 if (vapic_addr) {
3260 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
3261 &vcpu->arch.apic->vapic_cache,
3262 vapic_addr, sizeof(u32)))
3263 return -EINVAL;
3264 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
3265 } else {
3266 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
3267 }
3268
3269 vcpu->arch.apic->vapic_addr = vapic_addr;
3270 return 0;
3271}
3272
3273static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data)
3274{
3275 u32 low;
3276
3277 if (reg == APIC_ICR) {
3278 *data = kvm_x2apic_icr_read(apic);
3279 return 0;
3280 }
3281
3282 if (kvm_lapic_reg_read(apic, reg, 4, &low))
3283 return 1;
3284
3285 *data = low;
3286
3287 return 0;
3288}
3289
3290static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data)
3291{
3292 /*
3293 * ICR is a 64-bit register in x2APIC mode (and Hyper-V PV vAPIC) and
3294 * can be written as such, all other registers remain accessible only
3295 * through 32-bit reads/writes.
3296 */
3297 if (reg == APIC_ICR)
3298 return kvm_x2apic_icr_write(apic, data);
3299
3300 /* Bits 63:32 are reserved in all other registers. */
3301 if (data >> 32)
3302 return 1;
3303
3304 return kvm_lapic_reg_write(apic, reg, (u32)data);
3305}
3306
3307int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
3308{
3309 struct kvm_lapic *apic = vcpu->arch.apic;
3310 u32 reg = (msr - APIC_BASE_MSR) << 4;
3311
3312 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
3313 return 1;
3314
3315 return kvm_lapic_msr_write(apic, reg, data);
3316}
3317
3318int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
3319{
3320 struct kvm_lapic *apic = vcpu->arch.apic;
3321 u32 reg = (msr - APIC_BASE_MSR) << 4;
3322
3323 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
3324 return 1;
3325
3326 return kvm_lapic_msr_read(apic, reg, data);
3327}
3328
3329int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
3330{
3331 if (!lapic_in_kernel(vcpu))
3332 return 1;
3333
3334 return kvm_lapic_msr_write(vcpu->arch.apic, reg, data);
3335}
3336
3337int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
3338{
3339 if (!lapic_in_kernel(vcpu))
3340 return 1;
3341
3342 return kvm_lapic_msr_read(vcpu->arch.apic, reg, data);
3343}
3344
3345int kvm_lapic_set_pv_eoi(struct kvm_vcpu *vcpu, u64 data, unsigned long len)
3346{
3347 u64 addr = data & ~KVM_MSR_ENABLED;
3348 struct gfn_to_hva_cache *ghc = &vcpu->arch.pv_eoi.data;
3349 unsigned long new_len;
3350 int ret;
3351
3352 if (!IS_ALIGNED(addr, 4))
3353 return 1;
3354
3355 if (data & KVM_MSR_ENABLED) {
3356 if (addr == ghc->gpa && len <= ghc->len)
3357 new_len = ghc->len;
3358 else
3359 new_len = len;
3360
3361 ret = kvm_gfn_to_hva_cache_init(vcpu->kvm, ghc, addr, new_len);
3362 if (ret)
3363 return ret;
3364 }
3365
3366 vcpu->arch.pv_eoi.msr_val = data;
3367
3368 return 0;
3369}
3370
3371int kvm_apic_accept_events(struct kvm_vcpu *vcpu)
3372{
3373 struct kvm_lapic *apic = vcpu->arch.apic;
3374 u8 sipi_vector;
3375 int r;
3376
3377 if (!kvm_apic_has_pending_init_or_sipi(vcpu))
3378 return 0;
3379
3380 if (is_guest_mode(vcpu)) {
3381 r = kvm_check_nested_events(vcpu);
3382 if (r < 0)
3383 return r == -EBUSY ? 0 : r;
3384 /*
3385 * Continue processing INIT/SIPI even if a nested VM-Exit
3386 * occurred, e.g. pending SIPIs should be dropped if INIT+SIPI
3387 * are blocked as a result of transitioning to VMX root mode.
3388 */
3389 }
3390
3391 /*
3392 * INITs are blocked while CPU is in specific states (SMM, VMX root
3393 * mode, SVM with GIF=0), while SIPIs are dropped if the CPU isn't in
3394 * wait-for-SIPI (WFS).
3395 */
3396 if (!kvm_apic_init_sipi_allowed(vcpu)) {
3397 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
3398 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
3399 return 0;
3400 }
3401
3402 if (test_and_clear_bit(KVM_APIC_INIT, &apic->pending_events)) {
3403 kvm_vcpu_reset(vcpu, true);
3404 if (kvm_vcpu_is_bsp(apic->vcpu))
3405 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3406 else
3407 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
3408 }
3409 if (test_and_clear_bit(KVM_APIC_SIPI, &apic->pending_events)) {
3410 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
3411 /* evaluate pending_events before reading the vector */
3412 smp_rmb();
3413 sipi_vector = apic->sipi_vector;
3414 kvm_x86_call(vcpu_deliver_sipi_vector)(vcpu,
3415 sipi_vector);
3416 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
3417 }
3418 }
3419 return 0;
3420}
3421
3422void kvm_lapic_exit(void)
3423{
3424 static_key_deferred_flush(&apic_hw_disabled);
3425 WARN_ON(static_branch_unlikely(&apic_hw_disabled.key));
3426 static_key_deferred_flush(&apic_sw_disabled);
3427 WARN_ON(static_branch_unlikely(&apic_sw_disabled.key));
3428}
1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
21#include <linux/kvm_host.h>
22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
28#include <linux/export.h>
29#include <linux/math64.h>
30#include <linux/slab.h>
31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
36#include <asm/delay.h>
37#include <linux/atomic.h>
38#include <linux/jump_label.h>
39#include "kvm_cache_regs.h"
40#include "irq.h"
41#include "trace.h"
42#include "x86.h"
43#include "cpuid.h"
44#include "hyperv.h"
45
46#ifndef CONFIG_X86_64
47#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48#else
49#define mod_64(x, y) ((x) % (y))
50#endif
51
52#define PRId64 "d"
53#define PRIx64 "llx"
54#define PRIu64 "u"
55#define PRIo64 "o"
56
57/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
58#define apic_debug(fmt, arg...)
59
60/* 14 is the version for Xeon and Pentium 8.4.8*/
61#define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
62#define LAPIC_MMIO_LENGTH (1 << 12)
63/* followed define is not in apicdef.h */
64#define APIC_SHORT_MASK 0xc0000
65#define APIC_DEST_NOSHORT 0x0
66#define APIC_DEST_MASK 0x800
67#define MAX_APIC_VECTOR 256
68#define APIC_VECTORS_PER_REG 32
69
70#define APIC_BROADCAST 0xFF
71#define X2APIC_BROADCAST 0xFFFFFFFFul
72
73static inline int apic_test_vector(int vec, void *bitmap)
74{
75 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
76}
77
78bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
79{
80 struct kvm_lapic *apic = vcpu->arch.apic;
81
82 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
83 apic_test_vector(vector, apic->regs + APIC_IRR);
84}
85
86static inline void apic_clear_vector(int vec, void *bitmap)
87{
88 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
89}
90
91static inline int __apic_test_and_set_vector(int vec, void *bitmap)
92{
93 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
94}
95
96static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
97{
98 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
99}
100
101struct static_key_deferred apic_hw_disabled __read_mostly;
102struct static_key_deferred apic_sw_disabled __read_mostly;
103
104static inline int apic_enabled(struct kvm_lapic *apic)
105{
106 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
107}
108
109#define LVT_MASK \
110 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
111
112#define LINT_MASK \
113 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
114 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
115
116static inline u8 kvm_xapic_id(struct kvm_lapic *apic)
117{
118 return kvm_lapic_get_reg(apic, APIC_ID) >> 24;
119}
120
121static inline u32 kvm_x2apic_id(struct kvm_lapic *apic)
122{
123 return apic->vcpu->vcpu_id;
124}
125
126static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
127 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
128 switch (map->mode) {
129 case KVM_APIC_MODE_X2APIC: {
130 u32 offset = (dest_id >> 16) * 16;
131 u32 max_apic_id = map->max_apic_id;
132
133 if (offset <= max_apic_id) {
134 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
135
136 *cluster = &map->phys_map[offset];
137 *mask = dest_id & (0xffff >> (16 - cluster_size));
138 } else {
139 *mask = 0;
140 }
141
142 return true;
143 }
144 case KVM_APIC_MODE_XAPIC_FLAT:
145 *cluster = map->xapic_flat_map;
146 *mask = dest_id & 0xff;
147 return true;
148 case KVM_APIC_MODE_XAPIC_CLUSTER:
149 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
150 *mask = dest_id & 0xf;
151 return true;
152 default:
153 /* Not optimized. */
154 return false;
155 }
156}
157
158static void kvm_apic_map_free(struct rcu_head *rcu)
159{
160 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
161
162 kvfree(map);
163}
164
165static void recalculate_apic_map(struct kvm *kvm)
166{
167 struct kvm_apic_map *new, *old = NULL;
168 struct kvm_vcpu *vcpu;
169 int i;
170 u32 max_id = 255; /* enough space for any xAPIC ID */
171
172 mutex_lock(&kvm->arch.apic_map_lock);
173
174 kvm_for_each_vcpu(i, vcpu, kvm)
175 if (kvm_apic_present(vcpu))
176 max_id = max(max_id, kvm_x2apic_id(vcpu->arch.apic));
177
178 new = kvzalloc(sizeof(struct kvm_apic_map) +
179 sizeof(struct kvm_lapic *) * ((u64)max_id + 1), GFP_KERNEL);
180
181 if (!new)
182 goto out;
183
184 new->max_apic_id = max_id;
185
186 kvm_for_each_vcpu(i, vcpu, kvm) {
187 struct kvm_lapic *apic = vcpu->arch.apic;
188 struct kvm_lapic **cluster;
189 u16 mask;
190 u32 ldr;
191 u8 xapic_id;
192 u32 x2apic_id;
193
194 if (!kvm_apic_present(vcpu))
195 continue;
196
197 xapic_id = kvm_xapic_id(apic);
198 x2apic_id = kvm_x2apic_id(apic);
199
200 /* Hotplug hack: see kvm_apic_match_physical_addr(), ... */
201 if ((apic_x2apic_mode(apic) || x2apic_id > 0xff) &&
202 x2apic_id <= new->max_apic_id)
203 new->phys_map[x2apic_id] = apic;
204 /*
205 * ... xAPIC ID of VCPUs with APIC ID > 0xff will wrap-around,
206 * prevent them from masking VCPUs with APIC ID <= 0xff.
207 */
208 if (!apic_x2apic_mode(apic) && !new->phys_map[xapic_id])
209 new->phys_map[xapic_id] = apic;
210
211 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
212
213 if (apic_x2apic_mode(apic)) {
214 new->mode |= KVM_APIC_MODE_X2APIC;
215 } else if (ldr) {
216 ldr = GET_APIC_LOGICAL_ID(ldr);
217 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
218 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
219 else
220 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
221 }
222
223 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
224 continue;
225
226 if (mask)
227 cluster[ffs(mask) - 1] = apic;
228 }
229out:
230 old = rcu_dereference_protected(kvm->arch.apic_map,
231 lockdep_is_held(&kvm->arch.apic_map_lock));
232 rcu_assign_pointer(kvm->arch.apic_map, new);
233 mutex_unlock(&kvm->arch.apic_map_lock);
234
235 if (old)
236 call_rcu(&old->rcu, kvm_apic_map_free);
237
238 kvm_make_scan_ioapic_request(kvm);
239}
240
241static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
242{
243 bool enabled = val & APIC_SPIV_APIC_ENABLED;
244
245 kvm_lapic_set_reg(apic, APIC_SPIV, val);
246
247 if (enabled != apic->sw_enabled) {
248 apic->sw_enabled = enabled;
249 if (enabled) {
250 static_key_slow_dec_deferred(&apic_sw_disabled);
251 recalculate_apic_map(apic->vcpu->kvm);
252 } else
253 static_key_slow_inc(&apic_sw_disabled.key);
254 }
255}
256
257static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
258{
259 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
260 recalculate_apic_map(apic->vcpu->kvm);
261}
262
263static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
264{
265 kvm_lapic_set_reg(apic, APIC_LDR, id);
266 recalculate_apic_map(apic->vcpu->kvm);
267}
268
269static inline u32 kvm_apic_calc_x2apic_ldr(u32 id)
270{
271 return ((id >> 4) << 16) | (1 << (id & 0xf));
272}
273
274static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
275{
276 u32 ldr = kvm_apic_calc_x2apic_ldr(id);
277
278 WARN_ON_ONCE(id != apic->vcpu->vcpu_id);
279
280 kvm_lapic_set_reg(apic, APIC_ID, id);
281 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
282 recalculate_apic_map(apic->vcpu->kvm);
283}
284
285static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
286{
287 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
288}
289
290static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
291{
292 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
293}
294
295static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
296{
297 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
298}
299
300static inline int apic_lvtt_period(struct kvm_lapic *apic)
301{
302 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
303}
304
305static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
306{
307 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
308}
309
310static inline int apic_lvt_nmi_mode(u32 lvt_val)
311{
312 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
313}
314
315void kvm_apic_set_version(struct kvm_vcpu *vcpu)
316{
317 struct kvm_lapic *apic = vcpu->arch.apic;
318 struct kvm_cpuid_entry2 *feat;
319 u32 v = APIC_VERSION;
320
321 if (!lapic_in_kernel(vcpu))
322 return;
323
324 /*
325 * KVM emulates 82093AA datasheet (with in-kernel IOAPIC implementation)
326 * which doesn't have EOI register; Some buggy OSes (e.g. Windows with
327 * Hyper-V role) disable EOI broadcast in lapic not checking for IOAPIC
328 * version first and level-triggered interrupts never get EOIed in
329 * IOAPIC.
330 */
331 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
332 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))) &&
333 !ioapic_in_kernel(vcpu->kvm))
334 v |= APIC_LVR_DIRECTED_EOI;
335 kvm_lapic_set_reg(apic, APIC_LVR, v);
336}
337
338static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
339 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
340 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
341 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
342 LINT_MASK, LINT_MASK, /* LVT0-1 */
343 LVT_MASK /* LVTERR */
344};
345
346static int find_highest_vector(void *bitmap)
347{
348 int vec;
349 u32 *reg;
350
351 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
352 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
353 reg = bitmap + REG_POS(vec);
354 if (*reg)
355 return __fls(*reg) + vec;
356 }
357
358 return -1;
359}
360
361static u8 count_vectors(void *bitmap)
362{
363 int vec;
364 u32 *reg;
365 u8 count = 0;
366
367 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
368 reg = bitmap + REG_POS(vec);
369 count += hweight32(*reg);
370 }
371
372 return count;
373}
374
375bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
376{
377 u32 i, vec;
378 u32 pir_val, irr_val, prev_irr_val;
379 int max_updated_irr;
380
381 max_updated_irr = -1;
382 *max_irr = -1;
383
384 for (i = vec = 0; i <= 7; i++, vec += 32) {
385 pir_val = READ_ONCE(pir[i]);
386 irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
387 if (pir_val) {
388 prev_irr_val = irr_val;
389 irr_val |= xchg(&pir[i], 0);
390 *((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
391 if (prev_irr_val != irr_val) {
392 max_updated_irr =
393 __fls(irr_val ^ prev_irr_val) + vec;
394 }
395 }
396 if (irr_val)
397 *max_irr = __fls(irr_val) + vec;
398 }
399
400 return ((max_updated_irr != -1) &&
401 (max_updated_irr == *max_irr));
402}
403EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
404
405bool kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir, int *max_irr)
406{
407 struct kvm_lapic *apic = vcpu->arch.apic;
408
409 return __kvm_apic_update_irr(pir, apic->regs, max_irr);
410}
411EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
412
413static inline int apic_search_irr(struct kvm_lapic *apic)
414{
415 return find_highest_vector(apic->regs + APIC_IRR);
416}
417
418static inline int apic_find_highest_irr(struct kvm_lapic *apic)
419{
420 int result;
421
422 /*
423 * Note that irr_pending is just a hint. It will be always
424 * true with virtual interrupt delivery enabled.
425 */
426 if (!apic->irr_pending)
427 return -1;
428
429 result = apic_search_irr(apic);
430 ASSERT(result == -1 || result >= 16);
431
432 return result;
433}
434
435static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
436{
437 struct kvm_vcpu *vcpu;
438
439 vcpu = apic->vcpu;
440
441 if (unlikely(vcpu->arch.apicv_active)) {
442 /* need to update RVI */
443 apic_clear_vector(vec, apic->regs + APIC_IRR);
444 kvm_x86_ops->hwapic_irr_update(vcpu,
445 apic_find_highest_irr(apic));
446 } else {
447 apic->irr_pending = false;
448 apic_clear_vector(vec, apic->regs + APIC_IRR);
449 if (apic_search_irr(apic) != -1)
450 apic->irr_pending = true;
451 }
452}
453
454static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
455{
456 struct kvm_vcpu *vcpu;
457
458 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
459 return;
460
461 vcpu = apic->vcpu;
462
463 /*
464 * With APIC virtualization enabled, all caching is disabled
465 * because the processor can modify ISR under the hood. Instead
466 * just set SVI.
467 */
468 if (unlikely(vcpu->arch.apicv_active))
469 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
470 else {
471 ++apic->isr_count;
472 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
473 /*
474 * ISR (in service register) bit is set when injecting an interrupt.
475 * The highest vector is injected. Thus the latest bit set matches
476 * the highest bit in ISR.
477 */
478 apic->highest_isr_cache = vec;
479 }
480}
481
482static inline int apic_find_highest_isr(struct kvm_lapic *apic)
483{
484 int result;
485
486 /*
487 * Note that isr_count is always 1, and highest_isr_cache
488 * is always -1, with APIC virtualization enabled.
489 */
490 if (!apic->isr_count)
491 return -1;
492 if (likely(apic->highest_isr_cache != -1))
493 return apic->highest_isr_cache;
494
495 result = find_highest_vector(apic->regs + APIC_ISR);
496 ASSERT(result == -1 || result >= 16);
497
498 return result;
499}
500
501static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
502{
503 struct kvm_vcpu *vcpu;
504 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
505 return;
506
507 vcpu = apic->vcpu;
508
509 /*
510 * We do get here for APIC virtualization enabled if the guest
511 * uses the Hyper-V APIC enlightenment. In this case we may need
512 * to trigger a new interrupt delivery by writing the SVI field;
513 * on the other hand isr_count and highest_isr_cache are unused
514 * and must be left alone.
515 */
516 if (unlikely(vcpu->arch.apicv_active))
517 kvm_x86_ops->hwapic_isr_update(vcpu,
518 apic_find_highest_isr(apic));
519 else {
520 --apic->isr_count;
521 BUG_ON(apic->isr_count < 0);
522 apic->highest_isr_cache = -1;
523 }
524}
525
526int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
527{
528 /* This may race with setting of irr in __apic_accept_irq() and
529 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
530 * will cause vmexit immediately and the value will be recalculated
531 * on the next vmentry.
532 */
533 return apic_find_highest_irr(vcpu->arch.apic);
534}
535EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
536
537static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
538 int vector, int level, int trig_mode,
539 struct dest_map *dest_map);
540
541int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
542 struct dest_map *dest_map)
543{
544 struct kvm_lapic *apic = vcpu->arch.apic;
545
546 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
547 irq->level, irq->trig_mode, dest_map);
548}
549
550static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
551{
552
553 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
554 sizeof(val));
555}
556
557static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
558{
559
560 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
561 sizeof(*val));
562}
563
564static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
565{
566 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
567}
568
569static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
570{
571 u8 val;
572 if (pv_eoi_get_user(vcpu, &val) < 0)
573 apic_debug("Can't read EOI MSR value: 0x%llx\n",
574 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
575 return val & 0x1;
576}
577
578static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
579{
580 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
581 apic_debug("Can't set EOI MSR value: 0x%llx\n",
582 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
583 return;
584 }
585 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
586}
587
588static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
589{
590 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
591 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
592 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
593 return;
594 }
595 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
596}
597
598static int apic_has_interrupt_for_ppr(struct kvm_lapic *apic, u32 ppr)
599{
600 int highest_irr;
601 if (apic->vcpu->arch.apicv_active)
602 highest_irr = kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
603 else
604 highest_irr = apic_find_highest_irr(apic);
605 if (highest_irr == -1 || (highest_irr & 0xF0) <= ppr)
606 return -1;
607 return highest_irr;
608}
609
610static bool __apic_update_ppr(struct kvm_lapic *apic, u32 *new_ppr)
611{
612 u32 tpr, isrv, ppr, old_ppr;
613 int isr;
614
615 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
616 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
617 isr = apic_find_highest_isr(apic);
618 isrv = (isr != -1) ? isr : 0;
619
620 if ((tpr & 0xf0) >= (isrv & 0xf0))
621 ppr = tpr & 0xff;
622 else
623 ppr = isrv & 0xf0;
624
625 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
626 apic, ppr, isr, isrv);
627
628 *new_ppr = ppr;
629 if (old_ppr != ppr)
630 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
631
632 return ppr < old_ppr;
633}
634
635static void apic_update_ppr(struct kvm_lapic *apic)
636{
637 u32 ppr;
638
639 if (__apic_update_ppr(apic, &ppr) &&
640 apic_has_interrupt_for_ppr(apic, ppr) != -1)
641 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
642}
643
644void kvm_apic_update_ppr(struct kvm_vcpu *vcpu)
645{
646 apic_update_ppr(vcpu->arch.apic);
647}
648EXPORT_SYMBOL_GPL(kvm_apic_update_ppr);
649
650static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
651{
652 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
653 apic_update_ppr(apic);
654}
655
656static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
657{
658 return mda == (apic_x2apic_mode(apic) ?
659 X2APIC_BROADCAST : APIC_BROADCAST);
660}
661
662static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
663{
664 if (kvm_apic_broadcast(apic, mda))
665 return true;
666
667 if (apic_x2apic_mode(apic))
668 return mda == kvm_x2apic_id(apic);
669
670 /*
671 * Hotplug hack: Make LAPIC in xAPIC mode also accept interrupts as if
672 * it were in x2APIC mode. Hotplugged VCPUs start in xAPIC mode and
673 * this allows unique addressing of VCPUs with APIC ID over 0xff.
674 * The 0xff condition is needed because writeable xAPIC ID.
675 */
676 if (kvm_x2apic_id(apic) > 0xff && mda == kvm_x2apic_id(apic))
677 return true;
678
679 return mda == kvm_xapic_id(apic);
680}
681
682static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
683{
684 u32 logical_id;
685
686 if (kvm_apic_broadcast(apic, mda))
687 return true;
688
689 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
690
691 if (apic_x2apic_mode(apic))
692 return ((logical_id >> 16) == (mda >> 16))
693 && (logical_id & mda & 0xffff) != 0;
694
695 logical_id = GET_APIC_LOGICAL_ID(logical_id);
696
697 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
698 case APIC_DFR_FLAT:
699 return (logical_id & mda) != 0;
700 case APIC_DFR_CLUSTER:
701 return ((logical_id >> 4) == (mda >> 4))
702 && (logical_id & mda & 0xf) != 0;
703 default:
704 apic_debug("Bad DFR vcpu %d: %08x\n",
705 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
706 return false;
707 }
708}
709
710/* The KVM local APIC implementation has two quirks:
711 *
712 * - Real hardware delivers interrupts destined to x2APIC ID > 0xff to LAPICs
713 * in xAPIC mode if the "destination & 0xff" matches its xAPIC ID.
714 * KVM doesn't do that aliasing.
715 *
716 * - in-kernel IOAPIC messages have to be delivered directly to
717 * x2APIC, because the kernel does not support interrupt remapping.
718 * In order to support broadcast without interrupt remapping, x2APIC
719 * rewrites the destination of non-IPI messages from APIC_BROADCAST
720 * to X2APIC_BROADCAST.
721 *
722 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
723 * important when userspace wants to use x2APIC-format MSIs, because
724 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
725 */
726static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
727 struct kvm_lapic *source, struct kvm_lapic *target)
728{
729 bool ipi = source != NULL;
730
731 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
732 !ipi && dest_id == APIC_BROADCAST && apic_x2apic_mode(target))
733 return X2APIC_BROADCAST;
734
735 return dest_id;
736}
737
738bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
739 int short_hand, unsigned int dest, int dest_mode)
740{
741 struct kvm_lapic *target = vcpu->arch.apic;
742 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
743
744 apic_debug("target %p, source %p, dest 0x%x, "
745 "dest_mode 0x%x, short_hand 0x%x\n",
746 target, source, dest, dest_mode, short_hand);
747
748 ASSERT(target);
749 switch (short_hand) {
750 case APIC_DEST_NOSHORT:
751 if (dest_mode == APIC_DEST_PHYSICAL)
752 return kvm_apic_match_physical_addr(target, mda);
753 else
754 return kvm_apic_match_logical_addr(target, mda);
755 case APIC_DEST_SELF:
756 return target == source;
757 case APIC_DEST_ALLINC:
758 return true;
759 case APIC_DEST_ALLBUT:
760 return target != source;
761 default:
762 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
763 short_hand);
764 return false;
765 }
766}
767EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
768
769int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
770 const unsigned long *bitmap, u32 bitmap_size)
771{
772 u32 mod;
773 int i, idx = -1;
774
775 mod = vector % dest_vcpus;
776
777 for (i = 0; i <= mod; i++) {
778 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
779 BUG_ON(idx == bitmap_size);
780 }
781
782 return idx;
783}
784
785static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
786{
787 if (!kvm->arch.disabled_lapic_found) {
788 kvm->arch.disabled_lapic_found = true;
789 printk(KERN_INFO
790 "Disabled LAPIC found during irq injection\n");
791 }
792}
793
794static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
795 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
796{
797 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
798 if ((irq->dest_id == APIC_BROADCAST &&
799 map->mode != KVM_APIC_MODE_X2APIC))
800 return true;
801 if (irq->dest_id == X2APIC_BROADCAST)
802 return true;
803 } else {
804 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
805 if (irq->dest_id == (x2apic_ipi ?
806 X2APIC_BROADCAST : APIC_BROADCAST))
807 return true;
808 }
809
810 return false;
811}
812
813/* Return true if the interrupt can be handled by using *bitmap as index mask
814 * for valid destinations in *dst array.
815 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
816 * Note: we may have zero kvm_lapic destinations when we return true, which
817 * means that the interrupt should be dropped. In this case, *bitmap would be
818 * zero and *dst undefined.
819 */
820static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
821 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
822 struct kvm_apic_map *map, struct kvm_lapic ***dst,
823 unsigned long *bitmap)
824{
825 int i, lowest;
826
827 if (irq->shorthand == APIC_DEST_SELF && src) {
828 *dst = src;
829 *bitmap = 1;
830 return true;
831 } else if (irq->shorthand)
832 return false;
833
834 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
835 return false;
836
837 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
838 if (irq->dest_id > map->max_apic_id) {
839 *bitmap = 0;
840 } else {
841 *dst = &map->phys_map[irq->dest_id];
842 *bitmap = 1;
843 }
844 return true;
845 }
846
847 *bitmap = 0;
848 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
849 (u16 *)bitmap))
850 return false;
851
852 if (!kvm_lowest_prio_delivery(irq))
853 return true;
854
855 if (!kvm_vector_hashing_enabled()) {
856 lowest = -1;
857 for_each_set_bit(i, bitmap, 16) {
858 if (!(*dst)[i])
859 continue;
860 if (lowest < 0)
861 lowest = i;
862 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
863 (*dst)[lowest]->vcpu) < 0)
864 lowest = i;
865 }
866 } else {
867 if (!*bitmap)
868 return true;
869
870 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
871 bitmap, 16);
872
873 if (!(*dst)[lowest]) {
874 kvm_apic_disabled_lapic_found(kvm);
875 *bitmap = 0;
876 return true;
877 }
878 }
879
880 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
881
882 return true;
883}
884
885bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
886 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
887{
888 struct kvm_apic_map *map;
889 unsigned long bitmap;
890 struct kvm_lapic **dst = NULL;
891 int i;
892 bool ret;
893
894 *r = -1;
895
896 if (irq->shorthand == APIC_DEST_SELF) {
897 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
898 return true;
899 }
900
901 rcu_read_lock();
902 map = rcu_dereference(kvm->arch.apic_map);
903
904 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
905 if (ret)
906 for_each_set_bit(i, &bitmap, 16) {
907 if (!dst[i])
908 continue;
909 if (*r < 0)
910 *r = 0;
911 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
912 }
913
914 rcu_read_unlock();
915 return ret;
916}
917
918/*
919 * This routine tries to handler interrupts in posted mode, here is how
920 * it deals with different cases:
921 * - For single-destination interrupts, handle it in posted mode
922 * - Else if vector hashing is enabled and it is a lowest-priority
923 * interrupt, handle it in posted mode and use the following mechanism
924 * to find the destinaiton vCPU.
925 * 1. For lowest-priority interrupts, store all the possible
926 * destination vCPUs in an array.
927 * 2. Use "guest vector % max number of destination vCPUs" to find
928 * the right destination vCPU in the array for the lowest-priority
929 * interrupt.
930 * - Otherwise, use remapped mode to inject the interrupt.
931 */
932bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
933 struct kvm_vcpu **dest_vcpu)
934{
935 struct kvm_apic_map *map;
936 unsigned long bitmap;
937 struct kvm_lapic **dst = NULL;
938 bool ret = false;
939
940 if (irq->shorthand)
941 return false;
942
943 rcu_read_lock();
944 map = rcu_dereference(kvm->arch.apic_map);
945
946 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
947 hweight16(bitmap) == 1) {
948 unsigned long i = find_first_bit(&bitmap, 16);
949
950 if (dst[i]) {
951 *dest_vcpu = dst[i]->vcpu;
952 ret = true;
953 }
954 }
955
956 rcu_read_unlock();
957 return ret;
958}
959
960/*
961 * Add a pending IRQ into lapic.
962 * Return 1 if successfully added and 0 if discarded.
963 */
964static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
965 int vector, int level, int trig_mode,
966 struct dest_map *dest_map)
967{
968 int result = 0;
969 struct kvm_vcpu *vcpu = apic->vcpu;
970
971 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
972 trig_mode, vector);
973 switch (delivery_mode) {
974 case APIC_DM_LOWEST:
975 vcpu->arch.apic_arb_prio++;
976 case APIC_DM_FIXED:
977 if (unlikely(trig_mode && !level))
978 break;
979
980 /* FIXME add logic for vcpu on reset */
981 if (unlikely(!apic_enabled(apic)))
982 break;
983
984 result = 1;
985
986 if (dest_map) {
987 __set_bit(vcpu->vcpu_id, dest_map->map);
988 dest_map->vectors[vcpu->vcpu_id] = vector;
989 }
990
991 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
992 if (trig_mode)
993 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
994 else
995 apic_clear_vector(vector, apic->regs + APIC_TMR);
996 }
997
998 if (vcpu->arch.apicv_active)
999 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
1000 else {
1001 kvm_lapic_set_irr(vector, apic);
1002
1003 kvm_make_request(KVM_REQ_EVENT, vcpu);
1004 kvm_vcpu_kick(vcpu);
1005 }
1006 break;
1007
1008 case APIC_DM_REMRD:
1009 result = 1;
1010 vcpu->arch.pv.pv_unhalted = 1;
1011 kvm_make_request(KVM_REQ_EVENT, vcpu);
1012 kvm_vcpu_kick(vcpu);
1013 break;
1014
1015 case APIC_DM_SMI:
1016 result = 1;
1017 kvm_make_request(KVM_REQ_SMI, vcpu);
1018 kvm_vcpu_kick(vcpu);
1019 break;
1020
1021 case APIC_DM_NMI:
1022 result = 1;
1023 kvm_inject_nmi(vcpu);
1024 kvm_vcpu_kick(vcpu);
1025 break;
1026
1027 case APIC_DM_INIT:
1028 if (!trig_mode || level) {
1029 result = 1;
1030 /* assumes that there are only KVM_APIC_INIT/SIPI */
1031 apic->pending_events = (1UL << KVM_APIC_INIT);
1032 /* make sure pending_events is visible before sending
1033 * the request */
1034 smp_wmb();
1035 kvm_make_request(KVM_REQ_EVENT, vcpu);
1036 kvm_vcpu_kick(vcpu);
1037 } else {
1038 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
1039 vcpu->vcpu_id);
1040 }
1041 break;
1042
1043 case APIC_DM_STARTUP:
1044 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
1045 vcpu->vcpu_id, vector);
1046 result = 1;
1047 apic->sipi_vector = vector;
1048 /* make sure sipi_vector is visible for the receiver */
1049 smp_wmb();
1050 set_bit(KVM_APIC_SIPI, &apic->pending_events);
1051 kvm_make_request(KVM_REQ_EVENT, vcpu);
1052 kvm_vcpu_kick(vcpu);
1053 break;
1054
1055 case APIC_DM_EXTINT:
1056 /*
1057 * Should only be called by kvm_apic_local_deliver() with LVT0,
1058 * before NMI watchdog was enabled. Already handled by
1059 * kvm_apic_accept_pic_intr().
1060 */
1061 break;
1062
1063 default:
1064 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
1065 delivery_mode);
1066 break;
1067 }
1068 return result;
1069}
1070
1071int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
1072{
1073 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
1074}
1075
1076static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
1077{
1078 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
1079}
1080
1081static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1082{
1083 int trigger_mode;
1084
1085 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1086 if (!kvm_ioapic_handles_vector(apic, vector))
1087 return;
1088
1089 /* Request a KVM exit to inform the userspace IOAPIC. */
1090 if (irqchip_split(apic->vcpu->kvm)) {
1091 apic->vcpu->arch.pending_ioapic_eoi = vector;
1092 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1093 return;
1094 }
1095
1096 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1097 trigger_mode = IOAPIC_LEVEL_TRIG;
1098 else
1099 trigger_mode = IOAPIC_EDGE_TRIG;
1100
1101 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
1102}
1103
1104static int apic_set_eoi(struct kvm_lapic *apic)
1105{
1106 int vector = apic_find_highest_isr(apic);
1107
1108 trace_kvm_eoi(apic, vector);
1109
1110 /*
1111 * Not every write EOI will has corresponding ISR,
1112 * one example is when Kernel check timer on setup_IO_APIC
1113 */
1114 if (vector == -1)
1115 return vector;
1116
1117 apic_clear_isr(vector, apic);
1118 apic_update_ppr(apic);
1119
1120 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1121 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1122
1123 kvm_ioapic_send_eoi(apic, vector);
1124 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1125 return vector;
1126}
1127
1128/*
1129 * this interface assumes a trap-like exit, which has already finished
1130 * desired side effect including vISR and vPPR update.
1131 */
1132void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1133{
1134 struct kvm_lapic *apic = vcpu->arch.apic;
1135
1136 trace_kvm_eoi(apic, vector);
1137
1138 kvm_ioapic_send_eoi(apic, vector);
1139 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1140}
1141EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1142
1143static void apic_send_ipi(struct kvm_lapic *apic)
1144{
1145 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1146 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
1147 struct kvm_lapic_irq irq;
1148
1149 irq.vector = icr_low & APIC_VECTOR_MASK;
1150 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1151 irq.dest_mode = icr_low & APIC_DEST_MASK;
1152 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
1153 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1154 irq.shorthand = icr_low & APIC_SHORT_MASK;
1155 irq.msi_redir_hint = false;
1156 if (apic_x2apic_mode(apic))
1157 irq.dest_id = icr_high;
1158 else
1159 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
1160
1161 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1162
1163 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1164 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
1165 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1166 "msi_redir_hint 0x%x\n",
1167 icr_high, icr_low, irq.shorthand, irq.dest_id,
1168 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
1169 irq.vector, irq.msi_redir_hint);
1170
1171 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
1172}
1173
1174static u32 apic_get_tmcct(struct kvm_lapic *apic)
1175{
1176 ktime_t remaining, now;
1177 s64 ns;
1178 u32 tmcct;
1179
1180 ASSERT(apic != NULL);
1181
1182 /* if initial count is 0, current count should also be 0 */
1183 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
1184 apic->lapic_timer.period == 0)
1185 return 0;
1186
1187 now = ktime_get();
1188 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1189 if (ktime_to_ns(remaining) < 0)
1190 remaining = 0;
1191
1192 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1193 tmcct = div64_u64(ns,
1194 (APIC_BUS_CYCLE_NS * apic->divide_count));
1195
1196 return tmcct;
1197}
1198
1199static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1200{
1201 struct kvm_vcpu *vcpu = apic->vcpu;
1202 struct kvm_run *run = vcpu->run;
1203
1204 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
1205 run->tpr_access.rip = kvm_rip_read(vcpu);
1206 run->tpr_access.is_write = write;
1207}
1208
1209static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1210{
1211 if (apic->vcpu->arch.tpr_access_reporting)
1212 __report_tpr_access(apic, write);
1213}
1214
1215static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1216{
1217 u32 val = 0;
1218
1219 if (offset >= LAPIC_MMIO_LENGTH)
1220 return 0;
1221
1222 switch (offset) {
1223 case APIC_ARBPRI:
1224 apic_debug("Access APIC ARBPRI register which is for P6\n");
1225 break;
1226
1227 case APIC_TMCCT: /* Timer CCR */
1228 if (apic_lvtt_tscdeadline(apic))
1229 return 0;
1230
1231 val = apic_get_tmcct(apic);
1232 break;
1233 case APIC_PROCPRI:
1234 apic_update_ppr(apic);
1235 val = kvm_lapic_get_reg(apic, offset);
1236 break;
1237 case APIC_TASKPRI:
1238 report_tpr_access(apic, false);
1239 /* fall thru */
1240 default:
1241 val = kvm_lapic_get_reg(apic, offset);
1242 break;
1243 }
1244
1245 return val;
1246}
1247
1248static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1249{
1250 return container_of(dev, struct kvm_lapic, dev);
1251}
1252
1253int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
1254 void *data)
1255{
1256 unsigned char alignment = offset & 0xf;
1257 u32 result;
1258 /* this bitmask has a bit cleared for each reserved register */
1259 static const u64 rmask = 0x43ff01ffffffe70cULL;
1260
1261 if ((alignment + len) > 4) {
1262 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1263 offset, len);
1264 return 1;
1265 }
1266
1267 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
1268 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1269 offset);
1270 return 1;
1271 }
1272
1273 result = __apic_read(apic, offset & ~0xf);
1274
1275 trace_kvm_apic_read(offset, result);
1276
1277 switch (len) {
1278 case 1:
1279 case 2:
1280 case 4:
1281 memcpy(data, (char *)&result + alignment, len);
1282 break;
1283 default:
1284 printk(KERN_ERR "Local APIC read with len = %x, "
1285 "should be 1,2, or 4 instead\n", len);
1286 break;
1287 }
1288 return 0;
1289}
1290EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
1291
1292static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1293{
1294 return kvm_apic_hw_enabled(apic) &&
1295 addr >= apic->base_address &&
1296 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1297}
1298
1299static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1300 gpa_t address, int len, void *data)
1301{
1302 struct kvm_lapic *apic = to_lapic(this);
1303 u32 offset = address - apic->base_address;
1304
1305 if (!apic_mmio_in_range(apic, address))
1306 return -EOPNOTSUPP;
1307
1308 kvm_lapic_reg_read(apic, offset, len, data);
1309
1310 return 0;
1311}
1312
1313static void update_divide_count(struct kvm_lapic *apic)
1314{
1315 u32 tmp1, tmp2, tdcr;
1316
1317 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
1318 tmp1 = tdcr & 0xf;
1319 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
1320 apic->divide_count = 0x1 << (tmp2 & 0x7);
1321
1322 apic_debug("timer divide count is 0x%x\n",
1323 apic->divide_count);
1324}
1325
1326static void limit_periodic_timer_frequency(struct kvm_lapic *apic)
1327{
1328 /*
1329 * Do not allow the guest to program periodic timers with small
1330 * interval, since the hrtimers are not throttled by the host
1331 * scheduler.
1332 */
1333 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1334 s64 min_period = min_timer_period_us * 1000LL;
1335
1336 if (apic->lapic_timer.period < min_period) {
1337 pr_info_ratelimited(
1338 "kvm: vcpu %i: requested %lld ns "
1339 "lapic timer period limited to %lld ns\n",
1340 apic->vcpu->vcpu_id,
1341 apic->lapic_timer.period, min_period);
1342 apic->lapic_timer.period = min_period;
1343 }
1344 }
1345}
1346
1347static void apic_update_lvtt(struct kvm_lapic *apic)
1348{
1349 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
1350 apic->lapic_timer.timer_mode_mask;
1351
1352 if (apic->lapic_timer.timer_mode != timer_mode) {
1353 if (apic_lvtt_tscdeadline(apic) != (timer_mode ==
1354 APIC_LVT_TIMER_TSCDEADLINE)) {
1355 hrtimer_cancel(&apic->lapic_timer.timer);
1356 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
1357 apic->lapic_timer.period = 0;
1358 apic->lapic_timer.tscdeadline = 0;
1359 }
1360 apic->lapic_timer.timer_mode = timer_mode;
1361 limit_periodic_timer_frequency(apic);
1362 }
1363}
1364
1365static void apic_timer_expired(struct kvm_lapic *apic)
1366{
1367 struct kvm_vcpu *vcpu = apic->vcpu;
1368 struct swait_queue_head *q = &vcpu->wq;
1369 struct kvm_timer *ktimer = &apic->lapic_timer;
1370
1371 if (atomic_read(&apic->lapic_timer.pending))
1372 return;
1373
1374 atomic_inc(&apic->lapic_timer.pending);
1375 kvm_set_pending_timer(vcpu);
1376
1377 /*
1378 * For x86, the atomic_inc() is serialized, thus
1379 * using swait_active() is safe.
1380 */
1381 if (swait_active(q))
1382 swake_up(q);
1383
1384 if (apic_lvtt_tscdeadline(apic))
1385 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1386}
1387
1388/*
1389 * On APICv, this test will cause a busy wait
1390 * during a higher-priority task.
1391 */
1392
1393static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1394{
1395 struct kvm_lapic *apic = vcpu->arch.apic;
1396 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
1397
1398 if (kvm_apic_hw_enabled(apic)) {
1399 int vec = reg & APIC_VECTOR_MASK;
1400 void *bitmap = apic->regs + APIC_ISR;
1401
1402 if (vcpu->arch.apicv_active)
1403 bitmap = apic->regs + APIC_IRR;
1404
1405 if (apic_test_vector(vec, bitmap))
1406 return true;
1407 }
1408 return false;
1409}
1410
1411void wait_lapic_expire(struct kvm_vcpu *vcpu)
1412{
1413 struct kvm_lapic *apic = vcpu->arch.apic;
1414 u64 guest_tsc, tsc_deadline;
1415
1416 if (!lapic_in_kernel(vcpu))
1417 return;
1418
1419 if (apic->lapic_timer.expired_tscdeadline == 0)
1420 return;
1421
1422 if (!lapic_timer_int_injected(vcpu))
1423 return;
1424
1425 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1426 apic->lapic_timer.expired_tscdeadline = 0;
1427 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1428 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
1429
1430 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1431 if (guest_tsc < tsc_deadline)
1432 __delay(min(tsc_deadline - guest_tsc,
1433 nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
1434}
1435
1436static void start_sw_tscdeadline(struct kvm_lapic *apic)
1437{
1438 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1439 u64 ns = 0;
1440 ktime_t expire;
1441 struct kvm_vcpu *vcpu = apic->vcpu;
1442 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1443 unsigned long flags;
1444 ktime_t now;
1445
1446 if (unlikely(!tscdeadline || !this_tsc_khz))
1447 return;
1448
1449 local_irq_save(flags);
1450
1451 now = ktime_get();
1452 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1453 if (likely(tscdeadline > guest_tsc)) {
1454 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1455 do_div(ns, this_tsc_khz);
1456 expire = ktime_add_ns(now, ns);
1457 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1458 hrtimer_start(&apic->lapic_timer.timer,
1459 expire, HRTIMER_MODE_ABS_PINNED);
1460 } else
1461 apic_timer_expired(apic);
1462
1463 local_irq_restore(flags);
1464}
1465
1466static void update_target_expiration(struct kvm_lapic *apic, uint32_t old_divisor)
1467{
1468 ktime_t now, remaining;
1469 u64 ns_remaining_old, ns_remaining_new;
1470
1471 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1472 * APIC_BUS_CYCLE_NS * apic->divide_count;
1473 limit_periodic_timer_frequency(apic);
1474
1475 now = ktime_get();
1476 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
1477 if (ktime_to_ns(remaining) < 0)
1478 remaining = 0;
1479
1480 ns_remaining_old = ktime_to_ns(remaining);
1481 ns_remaining_new = mul_u64_u32_div(ns_remaining_old,
1482 apic->divide_count, old_divisor);
1483
1484 apic->lapic_timer.tscdeadline +=
1485 nsec_to_cycles(apic->vcpu, ns_remaining_new) -
1486 nsec_to_cycles(apic->vcpu, ns_remaining_old);
1487 apic->lapic_timer.target_expiration = ktime_add_ns(now, ns_remaining_new);
1488}
1489
1490static bool set_target_expiration(struct kvm_lapic *apic)
1491{
1492 ktime_t now;
1493 u64 tscl = rdtsc();
1494
1495 now = ktime_get();
1496 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
1497 * APIC_BUS_CYCLE_NS * apic->divide_count;
1498
1499 if (!apic->lapic_timer.period) {
1500 apic->lapic_timer.tscdeadline = 0;
1501 return false;
1502 }
1503
1504 limit_periodic_timer_frequency(apic);
1505
1506 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1507 PRIx64 ", "
1508 "timer initial count 0x%x, period %lldns, "
1509 "expire @ 0x%016" PRIx64 ".\n", __func__,
1510 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1511 kvm_lapic_get_reg(apic, APIC_TMICT),
1512 apic->lapic_timer.period,
1513 ktime_to_ns(ktime_add_ns(now,
1514 apic->lapic_timer.period)));
1515
1516 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1517 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1518 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1519
1520 return true;
1521}
1522
1523static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1524{
1525 ktime_t now = ktime_get();
1526 u64 tscl = rdtsc();
1527 ktime_t delta;
1528
1529 /*
1530 * Synchronize both deadlines to the same time source or
1531 * differences in the periods (caused by differences in the
1532 * underlying clocks or numerical approximation errors) will
1533 * cause the two to drift apart over time as the errors
1534 * accumulate.
1535 */
1536 apic->lapic_timer.target_expiration =
1537 ktime_add_ns(apic->lapic_timer.target_expiration,
1538 apic->lapic_timer.period);
1539 delta = ktime_sub(apic->lapic_timer.target_expiration, now);
1540 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1541 nsec_to_cycles(apic->vcpu, delta);
1542}
1543
1544static void start_sw_period(struct kvm_lapic *apic)
1545{
1546 if (!apic->lapic_timer.period)
1547 return;
1548
1549 if (ktime_after(ktime_get(),
1550 apic->lapic_timer.target_expiration)) {
1551 apic_timer_expired(apic);
1552
1553 if (apic_lvtt_oneshot(apic))
1554 return;
1555
1556 advance_periodic_target_expiration(apic);
1557 }
1558
1559 hrtimer_start(&apic->lapic_timer.timer,
1560 apic->lapic_timer.target_expiration,
1561 HRTIMER_MODE_ABS_PINNED);
1562}
1563
1564bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1565{
1566 if (!lapic_in_kernel(vcpu))
1567 return false;
1568
1569 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1570}
1571EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1572
1573static void cancel_hv_timer(struct kvm_lapic *apic)
1574{
1575 WARN_ON(preemptible());
1576 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1577 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1578 apic->lapic_timer.hv_timer_in_use = false;
1579}
1580
1581static bool start_hv_timer(struct kvm_lapic *apic)
1582{
1583 struct kvm_timer *ktimer = &apic->lapic_timer;
1584 int r;
1585
1586 WARN_ON(preemptible());
1587 if (!kvm_x86_ops->set_hv_timer)
1588 return false;
1589
1590 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1591 return false;
1592
1593 if (!ktimer->tscdeadline)
1594 return false;
1595
1596 r = kvm_x86_ops->set_hv_timer(apic->vcpu, ktimer->tscdeadline);
1597 if (r < 0)
1598 return false;
1599
1600 ktimer->hv_timer_in_use = true;
1601 hrtimer_cancel(&ktimer->timer);
1602
1603 /*
1604 * Also recheck ktimer->pending, in case the sw timer triggered in
1605 * the window. For periodic timer, leave the hv timer running for
1606 * simplicity, and the deadline will be recomputed on the next vmexit.
1607 */
1608 if (!apic_lvtt_period(apic) && (r || atomic_read(&ktimer->pending))) {
1609 if (r)
1610 apic_timer_expired(apic);
1611 return false;
1612 }
1613
1614 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, true);
1615 return true;
1616}
1617
1618static void start_sw_timer(struct kvm_lapic *apic)
1619{
1620 struct kvm_timer *ktimer = &apic->lapic_timer;
1621
1622 WARN_ON(preemptible());
1623 if (apic->lapic_timer.hv_timer_in_use)
1624 cancel_hv_timer(apic);
1625 if (!apic_lvtt_period(apic) && atomic_read(&ktimer->pending))
1626 return;
1627
1628 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1629 start_sw_period(apic);
1630 else if (apic_lvtt_tscdeadline(apic))
1631 start_sw_tscdeadline(apic);
1632 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, false);
1633}
1634
1635static void restart_apic_timer(struct kvm_lapic *apic)
1636{
1637 preempt_disable();
1638 if (!start_hv_timer(apic))
1639 start_sw_timer(apic);
1640 preempt_enable();
1641}
1642
1643void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1644{
1645 struct kvm_lapic *apic = vcpu->arch.apic;
1646
1647 preempt_disable();
1648 /* If the preempt notifier has already run, it also called apic_timer_expired */
1649 if (!apic->lapic_timer.hv_timer_in_use)
1650 goto out;
1651 WARN_ON(swait_active(&vcpu->wq));
1652 cancel_hv_timer(apic);
1653 apic_timer_expired(apic);
1654
1655 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1656 advance_periodic_target_expiration(apic);
1657 restart_apic_timer(apic);
1658 }
1659out:
1660 preempt_enable();
1661}
1662EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1663
1664void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1665{
1666 restart_apic_timer(vcpu->arch.apic);
1667}
1668EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1669
1670void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1671{
1672 struct kvm_lapic *apic = vcpu->arch.apic;
1673
1674 preempt_disable();
1675 /* Possibly the TSC deadline timer is not enabled yet */
1676 if (apic->lapic_timer.hv_timer_in_use)
1677 start_sw_timer(apic);
1678 preempt_enable();
1679}
1680EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1681
1682void kvm_lapic_restart_hv_timer(struct kvm_vcpu *vcpu)
1683{
1684 struct kvm_lapic *apic = vcpu->arch.apic;
1685
1686 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1687 restart_apic_timer(apic);
1688}
1689
1690static void start_apic_timer(struct kvm_lapic *apic)
1691{
1692 atomic_set(&apic->lapic_timer.pending, 0);
1693
1694 if ((apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1695 && !set_target_expiration(apic))
1696 return;
1697
1698 restart_apic_timer(apic);
1699}
1700
1701static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1702{
1703 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
1704
1705 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1706 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1707 if (lvt0_in_nmi_mode) {
1708 apic_debug("Receive NMI setting on APIC_LVT0 "
1709 "for cpu %d\n", apic->vcpu->vcpu_id);
1710 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1711 } else
1712 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1713 }
1714}
1715
1716int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
1717{
1718 int ret = 0;
1719
1720 trace_kvm_apic_write(reg, val);
1721
1722 switch (reg) {
1723 case APIC_ID: /* Local APIC ID */
1724 if (!apic_x2apic_mode(apic))
1725 kvm_apic_set_xapic_id(apic, val >> 24);
1726 else
1727 ret = 1;
1728 break;
1729
1730 case APIC_TASKPRI:
1731 report_tpr_access(apic, true);
1732 apic_set_tpr(apic, val & 0xff);
1733 break;
1734
1735 case APIC_EOI:
1736 apic_set_eoi(apic);
1737 break;
1738
1739 case APIC_LDR:
1740 if (!apic_x2apic_mode(apic))
1741 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
1742 else
1743 ret = 1;
1744 break;
1745
1746 case APIC_DFR:
1747 if (!apic_x2apic_mode(apic)) {
1748 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1749 recalculate_apic_map(apic->vcpu->kvm);
1750 } else
1751 ret = 1;
1752 break;
1753
1754 case APIC_SPIV: {
1755 u32 mask = 0x3ff;
1756 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
1757 mask |= APIC_SPIV_DIRECTED_EOI;
1758 apic_set_spiv(apic, val & mask);
1759 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1760 int i;
1761 u32 lvt_val;
1762
1763 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
1764 lvt_val = kvm_lapic_get_reg(apic,
1765 APIC_LVTT + 0x10 * i);
1766 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
1767 lvt_val | APIC_LVT_MASKED);
1768 }
1769 apic_update_lvtt(apic);
1770 atomic_set(&apic->lapic_timer.pending, 0);
1771
1772 }
1773 break;
1774 }
1775 case APIC_ICR:
1776 /* No delay here, so we always clear the pending bit */
1777 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
1778 apic_send_ipi(apic);
1779 break;
1780
1781 case APIC_ICR2:
1782 if (!apic_x2apic_mode(apic))
1783 val &= 0xff000000;
1784 kvm_lapic_set_reg(apic, APIC_ICR2, val);
1785 break;
1786
1787 case APIC_LVT0:
1788 apic_manage_nmi_watchdog(apic, val);
1789 case APIC_LVTTHMR:
1790 case APIC_LVTPC:
1791 case APIC_LVT1:
1792 case APIC_LVTERR:
1793 /* TODO: Check vector */
1794 if (!kvm_apic_sw_enabled(apic))
1795 val |= APIC_LVT_MASKED;
1796
1797 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1798 kvm_lapic_set_reg(apic, reg, val);
1799
1800 break;
1801
1802 case APIC_LVTT:
1803 if (!kvm_apic_sw_enabled(apic))
1804 val |= APIC_LVT_MASKED;
1805 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1806 kvm_lapic_set_reg(apic, APIC_LVTT, val);
1807 apic_update_lvtt(apic);
1808 break;
1809
1810 case APIC_TMICT:
1811 if (apic_lvtt_tscdeadline(apic))
1812 break;
1813
1814 hrtimer_cancel(&apic->lapic_timer.timer);
1815 kvm_lapic_set_reg(apic, APIC_TMICT, val);
1816 start_apic_timer(apic);
1817 break;
1818
1819 case APIC_TDCR: {
1820 uint32_t old_divisor = apic->divide_count;
1821
1822 if (val & 4)
1823 apic_debug("KVM_WRITE:TDCR %x\n", val);
1824 kvm_lapic_set_reg(apic, APIC_TDCR, val);
1825 update_divide_count(apic);
1826 if (apic->divide_count != old_divisor &&
1827 apic->lapic_timer.period) {
1828 hrtimer_cancel(&apic->lapic_timer.timer);
1829 update_target_expiration(apic, old_divisor);
1830 restart_apic_timer(apic);
1831 }
1832 break;
1833 }
1834 case APIC_ESR:
1835 if (apic_x2apic_mode(apic) && val != 0) {
1836 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
1837 ret = 1;
1838 }
1839 break;
1840
1841 case APIC_SELF_IPI:
1842 if (apic_x2apic_mode(apic)) {
1843 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
1844 } else
1845 ret = 1;
1846 break;
1847 default:
1848 ret = 1;
1849 break;
1850 }
1851 if (ret)
1852 apic_debug("Local APIC Write to read-only register %x\n", reg);
1853 return ret;
1854}
1855EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
1856
1857static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
1858 gpa_t address, int len, const void *data)
1859{
1860 struct kvm_lapic *apic = to_lapic(this);
1861 unsigned int offset = address - apic->base_address;
1862 u32 val;
1863
1864 if (!apic_mmio_in_range(apic, address))
1865 return -EOPNOTSUPP;
1866
1867 /*
1868 * APIC register must be aligned on 128-bits boundary.
1869 * 32/64/128 bits registers must be accessed thru 32 bits.
1870 * Refer SDM 8.4.1
1871 */
1872 if (len != 4 || (offset & 0xf)) {
1873 /* Don't shout loud, $infamous_os would cause only noise. */
1874 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
1875 return 0;
1876 }
1877
1878 val = *(u32*)data;
1879
1880 /* too common printing */
1881 if (offset != APIC_EOI)
1882 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1883 "0x%x\n", __func__, offset, len, val);
1884
1885 kvm_lapic_reg_write(apic, offset & 0xff0, val);
1886
1887 return 0;
1888}
1889
1890void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1891{
1892 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
1893}
1894EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1895
1896/* emulate APIC access in a trap manner */
1897void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1898{
1899 u32 val = 0;
1900
1901 /* hw has done the conditional check and inst decode */
1902 offset &= 0xff0;
1903
1904 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
1905
1906 /* TODO: optimize to just emulate side effect w/o one more write */
1907 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
1908}
1909EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1910
1911void kvm_free_lapic(struct kvm_vcpu *vcpu)
1912{
1913 struct kvm_lapic *apic = vcpu->arch.apic;
1914
1915 if (!vcpu->arch.apic)
1916 return;
1917
1918 hrtimer_cancel(&apic->lapic_timer.timer);
1919
1920 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1921 static_key_slow_dec_deferred(&apic_hw_disabled);
1922
1923 if (!apic->sw_enabled)
1924 static_key_slow_dec_deferred(&apic_sw_disabled);
1925
1926 if (apic->regs)
1927 free_page((unsigned long)apic->regs);
1928
1929 kfree(apic);
1930}
1931
1932/*
1933 *----------------------------------------------------------------------
1934 * LAPIC interface
1935 *----------------------------------------------------------------------
1936 */
1937u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1938{
1939 struct kvm_lapic *apic = vcpu->arch.apic;
1940
1941 if (!lapic_in_kernel(vcpu) ||
1942 !apic_lvtt_tscdeadline(apic))
1943 return 0;
1944
1945 return apic->lapic_timer.tscdeadline;
1946}
1947
1948void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1949{
1950 struct kvm_lapic *apic = vcpu->arch.apic;
1951
1952 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
1953 apic_lvtt_period(apic))
1954 return;
1955
1956 hrtimer_cancel(&apic->lapic_timer.timer);
1957 apic->lapic_timer.tscdeadline = data;
1958 start_apic_timer(apic);
1959}
1960
1961void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1962{
1963 struct kvm_lapic *apic = vcpu->arch.apic;
1964
1965 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
1966 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
1967}
1968
1969u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1970{
1971 u64 tpr;
1972
1973 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1974
1975 return (tpr & 0xf0) >> 4;
1976}
1977
1978void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1979{
1980 u64 old_value = vcpu->arch.apic_base;
1981 struct kvm_lapic *apic = vcpu->arch.apic;
1982
1983 if (!apic)
1984 value |= MSR_IA32_APICBASE_BSP;
1985
1986 vcpu->arch.apic_base = value;
1987
1988 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1989 kvm_update_cpuid(vcpu);
1990
1991 if (!apic)
1992 return;
1993
1994 /* update jump label if enable bit changes */
1995 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
1996 if (value & MSR_IA32_APICBASE_ENABLE) {
1997 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
1998 static_key_slow_dec_deferred(&apic_hw_disabled);
1999 } else {
2000 static_key_slow_inc(&apic_hw_disabled.key);
2001 recalculate_apic_map(vcpu->kvm);
2002 }
2003 }
2004
2005 if ((old_value ^ value) & X2APIC_ENABLE) {
2006 if (value & X2APIC_ENABLE) {
2007 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
2008 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
2009 } else
2010 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
2011 }
2012
2013 apic->base_address = apic->vcpu->arch.apic_base &
2014 MSR_IA32_APICBASE_BASE;
2015
2016 if ((value & MSR_IA32_APICBASE_ENABLE) &&
2017 apic->base_address != APIC_DEFAULT_PHYS_BASE)
2018 pr_warn_once("APIC base relocation is unsupported by KVM");
2019
2020 /* with FSB delivery interrupt, we can restart APIC functionality */
2021 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
2022 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
2023
2024}
2025
2026void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
2027{
2028 struct kvm_lapic *apic = vcpu->arch.apic;
2029 int i;
2030
2031 if (!apic)
2032 return;
2033
2034 apic_debug("%s\n", __func__);
2035
2036 /* Stop the timer in case it's a reset to an active apic */
2037 hrtimer_cancel(&apic->lapic_timer.timer);
2038
2039 if (!init_event) {
2040 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
2041 MSR_IA32_APICBASE_ENABLE);
2042 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
2043 }
2044 kvm_apic_set_version(apic->vcpu);
2045
2046 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
2047 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
2048 apic_update_lvtt(apic);
2049 if (kvm_vcpu_is_reset_bsp(vcpu) &&
2050 kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
2051 kvm_lapic_set_reg(apic, APIC_LVT0,
2052 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
2053 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2054
2055 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
2056 apic_set_spiv(apic, 0xff);
2057 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
2058 if (!apic_x2apic_mode(apic))
2059 kvm_apic_set_ldr(apic, 0);
2060 kvm_lapic_set_reg(apic, APIC_ESR, 0);
2061 kvm_lapic_set_reg(apic, APIC_ICR, 0);
2062 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
2063 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
2064 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
2065 for (i = 0; i < 8; i++) {
2066 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
2067 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
2068 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
2069 }
2070 apic->irr_pending = vcpu->arch.apicv_active;
2071 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
2072 apic->highest_isr_cache = -1;
2073 update_divide_count(apic);
2074 atomic_set(&apic->lapic_timer.pending, 0);
2075 if (kvm_vcpu_is_bsp(vcpu))
2076 kvm_lapic_set_base(vcpu,
2077 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
2078 vcpu->arch.pv_eoi.msr_val = 0;
2079 apic_update_ppr(apic);
2080 if (vcpu->arch.apicv_active) {
2081 kvm_x86_ops->apicv_post_state_restore(vcpu);
2082 kvm_x86_ops->hwapic_irr_update(vcpu, -1);
2083 kvm_x86_ops->hwapic_isr_update(vcpu, -1);
2084 }
2085
2086 vcpu->arch.apic_arb_prio = 0;
2087 vcpu->arch.apic_attention = 0;
2088
2089 apic_debug("%s: vcpu=%p, id=0x%x, base_msr="
2090 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
2091 vcpu, kvm_lapic_get_reg(apic, APIC_ID),
2092 vcpu->arch.apic_base, apic->base_address);
2093}
2094
2095/*
2096 *----------------------------------------------------------------------
2097 * timer interface
2098 *----------------------------------------------------------------------
2099 */
2100
2101static bool lapic_is_periodic(struct kvm_lapic *apic)
2102{
2103 return apic_lvtt_period(apic);
2104}
2105
2106int apic_has_pending_timer(struct kvm_vcpu *vcpu)
2107{
2108 struct kvm_lapic *apic = vcpu->arch.apic;
2109
2110 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
2111 return atomic_read(&apic->lapic_timer.pending);
2112
2113 return 0;
2114}
2115
2116int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
2117{
2118 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
2119 int vector, mode, trig_mode;
2120
2121 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
2122 vector = reg & APIC_VECTOR_MASK;
2123 mode = reg & APIC_MODE_MASK;
2124 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
2125 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
2126 NULL);
2127 }
2128 return 0;
2129}
2130
2131void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
2132{
2133 struct kvm_lapic *apic = vcpu->arch.apic;
2134
2135 if (apic)
2136 kvm_apic_local_deliver(apic, APIC_LVT0);
2137}
2138
2139static const struct kvm_io_device_ops apic_mmio_ops = {
2140 .read = apic_mmio_read,
2141 .write = apic_mmio_write,
2142};
2143
2144static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
2145{
2146 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2147 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
2148
2149 apic_timer_expired(apic);
2150
2151 if (lapic_is_periodic(apic)) {
2152 advance_periodic_target_expiration(apic);
2153 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
2154 return HRTIMER_RESTART;
2155 } else
2156 return HRTIMER_NORESTART;
2157}
2158
2159int kvm_create_lapic(struct kvm_vcpu *vcpu)
2160{
2161 struct kvm_lapic *apic;
2162
2163 ASSERT(vcpu != NULL);
2164 apic_debug("apic_init %d\n", vcpu->vcpu_id);
2165
2166 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
2167 if (!apic)
2168 goto nomem;
2169
2170 vcpu->arch.apic = apic;
2171
2172 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
2173 if (!apic->regs) {
2174 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
2175 vcpu->vcpu_id);
2176 goto nomem_free_apic;
2177 }
2178 apic->vcpu = vcpu;
2179
2180 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
2181 HRTIMER_MODE_ABS_PINNED);
2182 apic->lapic_timer.timer.function = apic_timer_fn;
2183
2184 /*
2185 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2186 * thinking that APIC satet has changed.
2187 */
2188 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
2189 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
2190 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
2191
2192 return 0;
2193nomem_free_apic:
2194 kfree(apic);
2195nomem:
2196 return -ENOMEM;
2197}
2198
2199int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2200{
2201 struct kvm_lapic *apic = vcpu->arch.apic;
2202 u32 ppr;
2203
2204 if (!apic_enabled(apic))
2205 return -1;
2206
2207 __apic_update_ppr(apic, &ppr);
2208 return apic_has_interrupt_for_ppr(apic, ppr);
2209}
2210
2211int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2212{
2213 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
2214 int r = 0;
2215
2216 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
2217 r = 1;
2218 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2219 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2220 r = 1;
2221 return r;
2222}
2223
2224void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2225{
2226 struct kvm_lapic *apic = vcpu->arch.apic;
2227
2228 if (atomic_read(&apic->lapic_timer.pending) > 0) {
2229 kvm_apic_local_deliver(apic, APIC_LVTT);
2230 if (apic_lvtt_tscdeadline(apic))
2231 apic->lapic_timer.tscdeadline = 0;
2232 if (apic_lvtt_oneshot(apic)) {
2233 apic->lapic_timer.tscdeadline = 0;
2234 apic->lapic_timer.target_expiration = 0;
2235 }
2236 atomic_set(&apic->lapic_timer.pending, 0);
2237 }
2238}
2239
2240int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2241{
2242 int vector = kvm_apic_has_interrupt(vcpu);
2243 struct kvm_lapic *apic = vcpu->arch.apic;
2244 u32 ppr;
2245
2246 if (vector == -1)
2247 return -1;
2248
2249 /*
2250 * We get here even with APIC virtualization enabled, if doing
2251 * nested virtualization and L1 runs with the "acknowledge interrupt
2252 * on exit" mode. Then we cannot inject the interrupt via RVI,
2253 * because the process would deliver it through the IDT.
2254 */
2255
2256 apic_clear_irr(vector, apic);
2257 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2258 /*
2259 * For auto-EOI interrupts, there might be another pending
2260 * interrupt above PPR, so check whether to raise another
2261 * KVM_REQ_EVENT.
2262 */
2263 apic_update_ppr(apic);
2264 } else {
2265 /*
2266 * For normal interrupts, PPR has been raised and there cannot
2267 * be a higher-priority pending interrupt---except if there was
2268 * a concurrent interrupt injection, but that would have
2269 * triggered KVM_REQ_EVENT already.
2270 */
2271 apic_set_isr(vector, apic);
2272 __apic_update_ppr(apic, &ppr);
2273 }
2274
2275 return vector;
2276}
2277
2278static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2279 struct kvm_lapic_state *s, bool set)
2280{
2281 if (apic_x2apic_mode(vcpu->arch.apic)) {
2282 u32 *id = (u32 *)(s->regs + APIC_ID);
2283 u32 *ldr = (u32 *)(s->regs + APIC_LDR);
2284
2285 if (vcpu->kvm->arch.x2apic_format) {
2286 if (*id != vcpu->vcpu_id)
2287 return -EINVAL;
2288 } else {
2289 if (set)
2290 *id >>= 24;
2291 else
2292 *id <<= 24;
2293 }
2294
2295 /* In x2APIC mode, the LDR is fixed and based on the id */
2296 if (set)
2297 *ldr = kvm_apic_calc_x2apic_ldr(*id);
2298 }
2299
2300 return 0;
2301}
2302
2303int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2304{
2305 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2306 return kvm_apic_state_fixup(vcpu, s, false);
2307}
2308
2309int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2310{
2311 struct kvm_lapic *apic = vcpu->arch.apic;
2312 int r;
2313
2314
2315 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
2316 /* set SPIV separately to get count of SW disabled APICs right */
2317 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
2318
2319 r = kvm_apic_state_fixup(vcpu, s, true);
2320 if (r)
2321 return r;
2322 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
2323
2324 recalculate_apic_map(vcpu->kvm);
2325 kvm_apic_set_version(vcpu);
2326
2327 apic_update_ppr(apic);
2328 hrtimer_cancel(&apic->lapic_timer.timer);
2329 apic_update_lvtt(apic);
2330 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
2331 update_divide_count(apic);
2332 start_apic_timer(apic);
2333 apic->irr_pending = true;
2334 apic->isr_count = vcpu->arch.apicv_active ?
2335 1 : count_vectors(apic->regs + APIC_ISR);
2336 apic->highest_isr_cache = -1;
2337 if (vcpu->arch.apicv_active) {
2338 kvm_x86_ops->apicv_post_state_restore(vcpu);
2339 kvm_x86_ops->hwapic_irr_update(vcpu,
2340 apic_find_highest_irr(apic));
2341 kvm_x86_ops->hwapic_isr_update(vcpu,
2342 apic_find_highest_isr(apic));
2343 }
2344 kvm_make_request(KVM_REQ_EVENT, vcpu);
2345 if (ioapic_in_kernel(vcpu->kvm))
2346 kvm_rtc_eoi_tracking_restore_one(vcpu);
2347
2348 vcpu->arch.apic_arb_prio = 0;
2349
2350 return 0;
2351}
2352
2353void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
2354{
2355 struct hrtimer *timer;
2356
2357 if (!lapic_in_kernel(vcpu))
2358 return;
2359
2360 timer = &vcpu->arch.apic->lapic_timer.timer;
2361 if (hrtimer_cancel(timer))
2362 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
2363}
2364
2365/*
2366 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2367 *
2368 * Detect whether guest triggered PV EOI since the
2369 * last entry. If yes, set EOI on guests's behalf.
2370 * Clear PV EOI in guest memory in any case.
2371 */
2372static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2373 struct kvm_lapic *apic)
2374{
2375 bool pending;
2376 int vector;
2377 /*
2378 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2379 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2380 *
2381 * KVM_APIC_PV_EOI_PENDING is unset:
2382 * -> host disabled PV EOI.
2383 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2384 * -> host enabled PV EOI, guest did not execute EOI yet.
2385 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2386 * -> host enabled PV EOI, guest executed EOI.
2387 */
2388 BUG_ON(!pv_eoi_enabled(vcpu));
2389 pending = pv_eoi_get_pending(vcpu);
2390 /*
2391 * Clear pending bit in any case: it will be set again on vmentry.
2392 * While this might not be ideal from performance point of view,
2393 * this makes sure pv eoi is only enabled when we know it's safe.
2394 */
2395 pv_eoi_clr_pending(vcpu);
2396 if (pending)
2397 return;
2398 vector = apic_set_eoi(apic);
2399 trace_kvm_pv_eoi(apic, vector);
2400}
2401
2402void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2403{
2404 u32 data;
2405
2406 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2407 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2408
2409 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2410 return;
2411
2412 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2413 sizeof(u32)))
2414 return;
2415
2416 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2417}
2418
2419/*
2420 * apic_sync_pv_eoi_to_guest - called before vmentry
2421 *
2422 * Detect whether it's safe to enable PV EOI and
2423 * if yes do so.
2424 */
2425static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2426 struct kvm_lapic *apic)
2427{
2428 if (!pv_eoi_enabled(vcpu) ||
2429 /* IRR set or many bits in ISR: could be nested. */
2430 apic->irr_pending ||
2431 /* Cache not set: could be safe but we don't bother. */
2432 apic->highest_isr_cache == -1 ||
2433 /* Need EOI to update ioapic. */
2434 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
2435 /*
2436 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2437 * so we need not do anything here.
2438 */
2439 return;
2440 }
2441
2442 pv_eoi_set_pending(apic->vcpu);
2443}
2444
2445void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2446{
2447 u32 data, tpr;
2448 int max_irr, max_isr;
2449 struct kvm_lapic *apic = vcpu->arch.apic;
2450
2451 apic_sync_pv_eoi_to_guest(vcpu, apic);
2452
2453 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
2454 return;
2455
2456 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
2457 max_irr = apic_find_highest_irr(apic);
2458 if (max_irr < 0)
2459 max_irr = 0;
2460 max_isr = apic_find_highest_isr(apic);
2461 if (max_isr < 0)
2462 max_isr = 0;
2463 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2464
2465 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2466 sizeof(u32));
2467}
2468
2469int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
2470{
2471 if (vapic_addr) {
2472 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2473 &vcpu->arch.apic->vapic_cache,
2474 vapic_addr, sizeof(u32)))
2475 return -EINVAL;
2476 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2477 } else {
2478 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
2479 }
2480
2481 vcpu->arch.apic->vapic_addr = vapic_addr;
2482 return 0;
2483}
2484
2485int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2486{
2487 struct kvm_lapic *apic = vcpu->arch.apic;
2488 u32 reg = (msr - APIC_BASE_MSR) << 4;
2489
2490 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2491 return 1;
2492
2493 if (reg == APIC_ICR2)
2494 return 1;
2495
2496 /* if this is ICR write vector before command */
2497 if (reg == APIC_ICR)
2498 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2499 return kvm_lapic_reg_write(apic, reg, (u32)data);
2500}
2501
2502int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2503{
2504 struct kvm_lapic *apic = vcpu->arch.apic;
2505 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2506
2507 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
2508 return 1;
2509
2510 if (reg == APIC_DFR || reg == APIC_ICR2) {
2511 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2512 reg);
2513 return 1;
2514 }
2515
2516 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2517 return 1;
2518 if (reg == APIC_ICR)
2519 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2520
2521 *data = (((u64)high) << 32) | low;
2522
2523 return 0;
2524}
2525
2526int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2527{
2528 struct kvm_lapic *apic = vcpu->arch.apic;
2529
2530 if (!lapic_in_kernel(vcpu))
2531 return 1;
2532
2533 /* if this is ICR write vector before command */
2534 if (reg == APIC_ICR)
2535 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2536 return kvm_lapic_reg_write(apic, reg, (u32)data);
2537}
2538
2539int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2540{
2541 struct kvm_lapic *apic = vcpu->arch.apic;
2542 u32 low, high = 0;
2543
2544 if (!lapic_in_kernel(vcpu))
2545 return 1;
2546
2547 if (kvm_lapic_reg_read(apic, reg, 4, &low))
2548 return 1;
2549 if (reg == APIC_ICR)
2550 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
2551
2552 *data = (((u64)high) << 32) | low;
2553
2554 return 0;
2555}
2556
2557int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2558{
2559 u64 addr = data & ~KVM_MSR_ENABLED;
2560 if (!IS_ALIGNED(addr, 4))
2561 return 1;
2562
2563 vcpu->arch.pv_eoi.msr_val = data;
2564 if (!pv_eoi_enabled(vcpu))
2565 return 0;
2566 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
2567 addr, sizeof(u8));
2568}
2569
2570void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2571{
2572 struct kvm_lapic *apic = vcpu->arch.apic;
2573 u8 sipi_vector;
2574 unsigned long pe;
2575
2576 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
2577 return;
2578
2579 /*
2580 * INITs are latched while in SMM. Because an SMM CPU cannot
2581 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2582 * and delay processing of INIT until the next RSM.
2583 */
2584 if (is_smm(vcpu)) {
2585 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2586 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2587 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2588 return;
2589 }
2590
2591 pe = xchg(&apic->pending_events, 0);
2592 if (test_bit(KVM_APIC_INIT, &pe)) {
2593 kvm_vcpu_reset(vcpu, true);
2594 if (kvm_vcpu_is_bsp(apic->vcpu))
2595 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2596 else
2597 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2598 }
2599 if (test_bit(KVM_APIC_SIPI, &pe) &&
2600 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2601 /* evaluate pending_events before reading the vector */
2602 smp_rmb();
2603 sipi_vector = apic->sipi_vector;
2604 apic_debug("vcpu %d received sipi with vector # %x\n",
2605 vcpu->vcpu_id, sipi_vector);
2606 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2607 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2608 }
2609}
2610
2611void kvm_lapic_init(void)
2612{
2613 /* do not patch jump label more than once per second */
2614 jump_label_rate_limit(&apic_hw_disabled, HZ);
2615 jump_label_rate_limit(&apic_sw_disabled, HZ);
2616}
2617
2618void kvm_lapic_exit(void)
2619{
2620 static_key_deferred_flush(&apic_hw_disabled);
2621 static_key_deferred_flush(&apic_sw_disabled);
2622}