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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * psr.h: This file holds the macros for masking off various parts of
4 * the processor status register on the Sparc. This is valid
5 * for Version 8. On the V9 this is renamed to the PSTATE
6 * register and its members are accessed as fields like
7 * PSTATE.PRIV for the current CPU privilege level.
8 *
9 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
10 */
11
12#ifndef _UAPI__LINUX_SPARC_PSR_H
13#define _UAPI__LINUX_SPARC_PSR_H
14
15/* The Sparc PSR fields are laid out as the following:
16 *
17 * ------------------------------------------------------------------------
18 * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
19 * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
20 * ------------------------------------------------------------------------
21 */
22#define PSR_CWP 0x0000001f /* current window pointer */
23#define PSR_ET 0x00000020 /* enable traps field */
24#define PSR_PS 0x00000040 /* previous privilege level */
25#define PSR_S 0x00000080 /* current privilege level */
26#define PSR_PIL 0x00000f00 /* processor interrupt level */
27#define PSR_EF 0x00001000 /* enable floating point */
28#define PSR_EC 0x00002000 /* enable co-processor */
29#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
30#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
31#define PSR_ICC 0x00f00000 /* integer condition codes */
32#define PSR_C 0x00100000 /* carry bit */
33#define PSR_V 0x00200000 /* overflow bit */
34#define PSR_Z 0x00400000 /* zero bit */
35#define PSR_N 0x00800000 /* negative bit */
36#define PSR_VERS 0x0f000000 /* cpu-version field */
37#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
38
39#define PSR_VERS_SHIFT 24
40#define PSR_IMPL_SHIFT 28
41#define PSR_VERS_SHIFTED_MASK 0xf
42#define PSR_IMPL_SHIFTED_MASK 0xf
43
44#define PSR_IMPL_TI 0x4
45#define PSR_IMPL_LEON 0xf
46
47
48#endif /* _UAPI__LINUX_SPARC_PSR_H */
1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * psr.h: This file holds the macros for masking off various parts of
4 * the processor status register on the Sparc. This is valid
5 * for Version 8. On the V9 this is renamed to the PSTATE
6 * register and its members are accessed as fields like
7 * PSTATE.PRIV for the current CPU privilege level.
8 *
9 * Copyright (C) 1994 David S. Miller (davem@caip.rutgers.edu)
10 */
11
12#ifndef _UAPI__LINUX_SPARC_PSR_H
13#define _UAPI__LINUX_SPARC_PSR_H
14
15/* The Sparc PSR fields are laid out as the following:
16 *
17 * ------------------------------------------------------------------------
18 * | impl | vers | icc | resv | EC | EF | PIL | S | PS | ET | CWP |
19 * | 31-28 | 27-24 | 23-20 | 19-14 | 13 | 12 | 11-8 | 7 | 6 | 5 | 4-0 |
20 * ------------------------------------------------------------------------
21 */
22#define PSR_CWP 0x0000001f /* current window pointer */
23#define PSR_ET 0x00000020 /* enable traps field */
24#define PSR_PS 0x00000040 /* previous privilege level */
25#define PSR_S 0x00000080 /* current privilege level */
26#define PSR_PIL 0x00000f00 /* processor interrupt level */
27#define PSR_EF 0x00001000 /* enable floating point */
28#define PSR_EC 0x00002000 /* enable co-processor */
29#define PSR_SYSCALL 0x00004000 /* inside of a syscall */
30#define PSR_LE 0x00008000 /* SuperSparcII little-endian */
31#define PSR_ICC 0x00f00000 /* integer condition codes */
32#define PSR_C 0x00100000 /* carry bit */
33#define PSR_V 0x00200000 /* overflow bit */
34#define PSR_Z 0x00400000 /* zero bit */
35#define PSR_N 0x00800000 /* negative bit */
36#define PSR_VERS 0x0f000000 /* cpu-version field */
37#define PSR_IMPL 0xf0000000 /* cpu-implementation field */
38
39#define PSR_VERS_SHIFT 24
40#define PSR_IMPL_SHIFT 28
41#define PSR_VERS_SHIFTED_MASK 0xf
42#define PSR_IMPL_SHIFTED_MASK 0xf
43
44#define PSR_IMPL_TI 0x4
45#define PSR_IMPL_LEON 0xf
46
47
48#endif /* _UAPI__LINUX_SPARC_PSR_H */