Loading...
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra210-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra210-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
7#include <dt-bindings/reset/tegra210-car.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9#include <dt-bindings/thermal/tegra124-soctherm.h>
10#include <dt-bindings/soc/tegra-pmc.h>
11
12/ {
13 compatible = "nvidia,tegra210";
14 interrupt-parent = <&lic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 pcie@1003000 {
19 compatible = "nvidia,tegra210-pcie";
20 device_type = "pci";
21 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */
22 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */
23 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */
24 reg-names = "pads", "afi", "cs";
25 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
26 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
27 interrupt-names = "intr", "msi";
28
29 #interrupt-cells = <1>;
30 interrupt-map-mask = <0 0 0 0>;
31 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32
33 bus-range = <0x00 0xff>;
34 #address-cells = <3>;
35 #size-cells = <2>;
36
37 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */
38 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */
39 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */
40 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */
41 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
42
43 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
44 <&tegra_car TEGRA210_CLK_AFI>,
45 <&tegra_car TEGRA210_CLK_PLL_E>,
46 <&tegra_car TEGRA210_CLK_CML0>;
47 clock-names = "pex", "afi", "pll_e", "cml";
48 resets = <&tegra_car 70>,
49 <&tegra_car 72>,
50 <&tegra_car 74>;
51 reset-names = "pex", "afi", "pcie_x";
52
53 pinctrl-names = "default", "idle";
54 pinctrl-0 = <&pex_dpd_disable>;
55 pinctrl-1 = <&pex_dpd_enable>;
56
57 status = "disabled";
58
59 pci@1,0 {
60 device_type = "pci";
61 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
62 reg = <0x000800 0 0 0 0>;
63 bus-range = <0x00 0xff>;
64 status = "disabled";
65
66 #address-cells = <3>;
67 #size-cells = <2>;
68 ranges;
69
70 nvidia,num-lanes = <4>;
71 };
72
73 pci@2,0 {
74 device_type = "pci";
75 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
76 reg = <0x001000 0 0 0 0>;
77 bus-range = <0x00 0xff>;
78 status = "disabled";
79
80 #address-cells = <3>;
81 #size-cells = <2>;
82 ranges;
83
84 nvidia,num-lanes = <1>;
85 };
86 };
87
88 host1x@50000000 {
89 compatible = "nvidia,tegra210-host1x";
90 reg = <0x0 0x50000000 0x0 0x00034000>;
91 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
92 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
93 interrupt-names = "syncpt", "host1x";
94 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
95 clock-names = "host1x";
96 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>;
97 reset-names = "host1x", "mc";
98
99 #address-cells = <2>;
100 #size-cells = <2>;
101
102 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
103
104 iommus = <&mc TEGRA_SWGROUP_HC>;
105
106 dpaux1: dpaux@54040000 {
107 compatible = "nvidia,tegra210-dpaux";
108 reg = <0x0 0x54040000 0x0 0x00040000>;
109 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
111 <&tegra_car TEGRA210_CLK_PLL_DP>;
112 clock-names = "dpaux", "parent";
113 resets = <&tegra_car 207>;
114 reset-names = "dpaux";
115 power-domains = <&pd_sor>;
116 status = "disabled";
117
118 state_dpaux1_aux: pinmux-aux {
119 groups = "dpaux-io";
120 function = "aux";
121 };
122
123 state_dpaux1_i2c: pinmux-i2c {
124 groups = "dpaux-io";
125 function = "i2c";
126 };
127
128 state_dpaux1_off: pinmux-off {
129 groups = "dpaux-io";
130 function = "off";
131 };
132
133 i2c-bus {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 };
137 };
138
139 vi@54080000 {
140 compatible = "nvidia,tegra210-vi";
141 reg = <0x0 0x54080000 0x0 0x700>;
142 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
143 status = "disabled";
144 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>;
145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
146
147 clocks = <&tegra_car TEGRA210_CLK_VI>;
148 power-domains = <&pd_venc>;
149
150 #address-cells = <1>;
151 #size-cells = <1>;
152
153 ranges = <0x0 0x0 0x54080000 0x2000>;
154
155 csi@838 {
156 compatible = "nvidia,tegra210-csi";
157 reg = <0x838 0x1300>;
158 status = "disabled";
159 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>,
160 <&tegra_car TEGRA210_CLK_CILCD>,
161 <&tegra_car TEGRA210_CLK_CILE>,
162 <&tegra_car TEGRA210_CLK_CSI_TPG>;
163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164 <&tegra_car TEGRA210_CLK_PLL_P>,
165 <&tegra_car TEGRA210_CLK_PLL_P>;
166 assigned-clock-rates = <102000000>,
167 <102000000>,
168 <102000000>,
169 <972000000>;
170
171 clocks = <&tegra_car TEGRA210_CLK_CSI>,
172 <&tegra_car TEGRA210_CLK_CILAB>,
173 <&tegra_car TEGRA210_CLK_CILCD>,
174 <&tegra_car TEGRA210_CLK_CILE>,
175 <&tegra_car TEGRA210_CLK_CSI_TPG>;
176 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg";
177 power-domains = <&pd_sor>;
178 };
179 };
180
181 tsec@54100000 {
182 compatible = "nvidia,tegra210-tsec";
183 reg = <0x0 0x54100000 0x0 0x00040000>;
184 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&tegra_car TEGRA210_CLK_TSEC>;
186 clock-names = "tsec";
187 resets = <&tegra_car 83>;
188 reset-names = "tsec";
189 status = "disabled";
190 };
191
192 dc@54200000 {
193 compatible = "nvidia,tegra210-dc";
194 reg = <0x0 0x54200000 0x0 0x00040000>;
195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
196 clocks = <&tegra_car TEGRA210_CLK_DISP1>;
197 clock-names = "dc";
198 resets = <&tegra_car 27>;
199 reset-names = "dc";
200
201 iommus = <&mc TEGRA_SWGROUP_DC>;
202
203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
204 nvidia,head = <0>;
205 };
206
207 dc@54240000 {
208 compatible = "nvidia,tegra210-dc";
209 reg = <0x0 0x54240000 0x0 0x00040000>;
210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
211 clocks = <&tegra_car TEGRA210_CLK_DISP2>;
212 clock-names = "dc";
213 resets = <&tegra_car 26>;
214 reset-names = "dc";
215
216 iommus = <&mc TEGRA_SWGROUP_DCB>;
217
218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>;
219 nvidia,head = <1>;
220 };
221
222 dsia: dsi@54300000 {
223 compatible = "nvidia,tegra210-dsi";
224 reg = <0x0 0x54300000 0x0 0x00040000>;
225 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
226 <&tegra_car TEGRA210_CLK_DSIALP>,
227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
228 clock-names = "dsi", "lp", "parent";
229 resets = <&tegra_car 48>;
230 reset-names = "dsi";
231 power-domains = <&pd_sor>;
232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
233
234 status = "disabled";
235
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 vic@54340000 {
241 compatible = "nvidia,tegra210-vic";
242 reg = <0x0 0x54340000 0x0 0x00040000>;
243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
244 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
245 clock-names = "vic";
246 resets = <&tegra_car 178>;
247 reset-names = "vic";
248
249 iommus = <&mc TEGRA_SWGROUP_VIC>;
250 power-domains = <&pd_vic>;
251 };
252
253 nvjpg@54380000 {
254 compatible = "nvidia,tegra210-nvjpg";
255 reg = <0x0 0x54380000 0x0 0x00040000>;
256 status = "disabled";
257 };
258
259 dsib: dsi@54400000 {
260 compatible = "nvidia,tegra210-dsi";
261 reg = <0x0 0x54400000 0x0 0x00040000>;
262 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
263 <&tegra_car TEGRA210_CLK_DSIBLP>,
264 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
265 clock-names = "dsi", "lp", "parent";
266 resets = <&tegra_car 82>;
267 reset-names = "dsi";
268 power-domains = <&pd_sor>;
269 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
270
271 status = "disabled";
272
273 #address-cells = <1>;
274 #size-cells = <0>;
275 };
276
277 nvdec@54480000 {
278 compatible = "nvidia,tegra210-nvdec";
279 reg = <0x0 0x54480000 0x0 0x00040000>;
280 status = "disabled";
281 };
282
283 nvenc@544c0000 {
284 compatible = "nvidia,tegra210-nvenc";
285 reg = <0x0 0x544c0000 0x0 0x00040000>;
286 status = "disabled";
287 };
288
289 tsec@54500000 {
290 compatible = "nvidia,tegra210-tsec";
291 reg = <0x0 0x54500000 0x0 0x00040000>;
292 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&tegra_car TEGRA210_CLK_TSECB>;
294 clock-names = "tsec";
295 resets = <&tegra_car 206>;
296 reset-names = "tsec";
297 status = "disabled";
298 };
299
300 sor0: sor@54540000 {
301 compatible = "nvidia,tegra210-sor";
302 reg = <0x0 0x54540000 0x0 0x00040000>;
303 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
305 <&tegra_car TEGRA210_CLK_SOR0_OUT>,
306 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
307 <&tegra_car TEGRA210_CLK_PLL_DP>,
308 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
309 clock-names = "sor", "out", "parent", "dp", "safe";
310 resets = <&tegra_car 182>;
311 reset-names = "sor";
312 pinctrl-0 = <&state_dpaux_aux>;
313 pinctrl-1 = <&state_dpaux_i2c>;
314 pinctrl-2 = <&state_dpaux_off>;
315 pinctrl-names = "aux", "i2c", "off";
316 power-domains = <&pd_sor>;
317 status = "disabled";
318 };
319
320 sor1: sor@54580000 {
321 compatible = "nvidia,tegra210-sor1";
322 reg = <0x0 0x54580000 0x0 0x00040000>;
323 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
325 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
326 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
327 <&tegra_car TEGRA210_CLK_PLL_DP>,
328 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
329 clock-names = "sor", "out", "parent", "dp", "safe";
330 resets = <&tegra_car 183>;
331 reset-names = "sor";
332 pinctrl-0 = <&state_dpaux1_aux>;
333 pinctrl-1 = <&state_dpaux1_i2c>;
334 pinctrl-2 = <&state_dpaux1_off>;
335 pinctrl-names = "aux", "i2c", "off";
336 power-domains = <&pd_sor>;
337 status = "disabled";
338 };
339
340 dpaux: dpaux@545c0000 {
341 compatible = "nvidia,tegra210-dpaux";
342 reg = <0x0 0x545c0000 0x0 0x00040000>;
343 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
345 <&tegra_car TEGRA210_CLK_PLL_DP>;
346 clock-names = "dpaux", "parent";
347 resets = <&tegra_car 181>;
348 reset-names = "dpaux";
349 power-domains = <&pd_sor>;
350 status = "disabled";
351
352 state_dpaux_aux: pinmux-aux {
353 groups = "dpaux-io";
354 function = "aux";
355 };
356
357 state_dpaux_i2c: pinmux-i2c {
358 groups = "dpaux-io";
359 function = "i2c";
360 };
361
362 state_dpaux_off: pinmux-off {
363 groups = "dpaux-io";
364 function = "off";
365 };
366
367 i2c-bus {
368 #address-cells = <1>;
369 #size-cells = <0>;
370 };
371 };
372
373 isp@54600000 {
374 compatible = "nvidia,tegra210-isp";
375 reg = <0x0 0x54600000 0x0 0x00040000>;
376 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&tegra_car TEGRA210_CLK_ISPA>;
378 resets = <&tegra_car 23>;
379 reset-names = "isp";
380 status = "disabled";
381 };
382
383 isp@54680000 {
384 compatible = "nvidia,tegra210-isp";
385 reg = <0x0 0x54680000 0x0 0x00040000>;
386 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
387 clocks = <&tegra_car TEGRA210_CLK_ISPB>;
388 resets = <&tegra_car 3>;
389 reset-names = "isp";
390 status = "disabled";
391 };
392
393 i2c@546c0000 {
394 compatible = "nvidia,tegra210-i2c-vi";
395 reg = <0x0 0x546c0000 0x0 0x00040000>;
396 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>,
398 <&tegra_car TEGRA210_CLK_I2CSLOW>;
399 clock-names = "div-clk", "slow";
400 resets = <&tegra_car 208>;
401 reset-names = "i2c";
402 power-domains = <&pd_venc>;
403 status = "disabled";
404
405 #address-cells = <1>;
406 #size-cells = <0>;
407 };
408 };
409
410 gic: interrupt-controller@50041000 {
411 compatible = "arm,gic-400";
412 #interrupt-cells = <3>;
413 interrupt-controller;
414 reg = <0x0 0x50041000 0x0 0x1000>,
415 <0x0 0x50042000 0x0 0x2000>,
416 <0x0 0x50044000 0x0 0x2000>,
417 <0x0 0x50046000 0x0 0x2000>;
418 interrupts = <GIC_PPI 9
419 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
420 interrupt-parent = <&gic>;
421 };
422
423 gpu@57000000 {
424 compatible = "nvidia,gm20b";
425 reg = <0x0 0x57000000 0x0 0x01000000>,
426 <0x0 0x58000000 0x0 0x01000000>;
427 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
429 interrupt-names = "stall", "nonstall";
430 clocks = <&tegra_car TEGRA210_CLK_GPU>,
431 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
432 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
433 clock-names = "gpu", "pwr", "ref";
434 resets = <&tegra_car 184>;
435 reset-names = "gpu";
436
437 iommus = <&mc TEGRA_SWGROUP_GPU>;
438
439 status = "disabled";
440 };
441
442 lic: interrupt-controller@60004000 {
443 compatible = "nvidia,tegra210-ictlr";
444 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
445 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
446 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
447 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
448 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
449 <0x0 0x60004500 0x0 0x40>; /* senary controller */
450 interrupt-controller;
451 #interrupt-cells = <3>;
452 interrupt-parent = <&gic>;
453 };
454
455 timer@60005000 {
456 compatible = "nvidia,tegra210-timer";
457 reg = <0x0 0x60005000 0x0 0x400>;
458 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
473 clock-names = "timer";
474 };
475
476 tegra_car: clock@60006000 {
477 compatible = "nvidia,tegra210-car";
478 reg = <0x0 0x60006000 0x0 0x1000>;
479 #clock-cells = <1>;
480 #reset-cells = <1>;
481 };
482
483 flow-controller@60007000 {
484 compatible = "nvidia,tegra210-flowctrl";
485 reg = <0x0 0x60007000 0x0 0x1000>;
486 };
487
488 gpio: gpio@6000d000 {
489 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
490 reg = <0x0 0x6000d000 0x0 0x1000>;
491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
499 #gpio-cells = <2>;
500 gpio-controller;
501 #interrupt-cells = <2>;
502 interrupt-controller;
503 };
504
505 apbdma: dma@60020000 {
506 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
507 reg = <0x0 0x60020000 0x0 0x1400>;
508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
541 clock-names = "dma";
542 resets = <&tegra_car 34>;
543 reset-names = "dma";
544 #dma-cells = <1>;
545 };
546
547 apbmisc@70000800 {
548 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
549 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
550 <0x0 0x70000008 0x0 0x04>; /* Strapping options */
551 };
552
553 pinmux: pinmux@700008d4 {
554 compatible = "nvidia,tegra210-pinmux";
555 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
556 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
557
558 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv {
559 sdmmc1 {
560 nvidia,pins = "drive_sdmmc1";
561 nvidia,pull-down-strength = <0x4>;
562 nvidia,pull-up-strength = <0x3>;
563 };
564 };
565
566 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv {
567 sdmmc1 {
568 nvidia,pins = "drive_sdmmc1";
569 nvidia,pull-down-strength = <0x8>;
570 nvidia,pull-up-strength = <0x8>;
571 };
572 };
573
574 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv {
575 sdmmc2 {
576 nvidia,pins = "drive_sdmmc2";
577 nvidia,pull-down-strength = <0x10>;
578 nvidia,pull-up-strength = <0x10>;
579 };
580 };
581
582 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv {
583 sdmmc3 {
584 nvidia,pins = "drive_sdmmc3";
585 nvidia,pull-down-strength = <0x4>;
586 nvidia,pull-up-strength = <0x3>;
587 };
588 };
589
590 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv {
591 sdmmc3 {
592 nvidia,pins = "drive_sdmmc3";
593 nvidia,pull-down-strength = <0x8>;
594 nvidia,pull-up-strength = <0x8>;
595 };
596 };
597
598 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv {
599 sdmmc4 {
600 nvidia,pins = "drive_sdmmc4";
601 nvidia,pull-down-strength = <0x10>;
602 nvidia,pull-up-strength = <0x10>;
603 };
604 };
605 };
606
607 /*
608 * There are two serial driver i.e. 8250 based simple serial
609 * driver and APB DMA based serial driver for higher baudrate
610 * and performance. To enable the 8250 based driver, the compatible
611 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
612 * the APB DMA based serial driver, the compatible is
613 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
614 */
615 uarta: serial@70006000 {
616 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
617 reg = <0x0 0x70006000 0x0 0x40>;
618 reg-shift = <2>;
619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
621 resets = <&tegra_car 6>;
622 dmas = <&apbdma 8>, <&apbdma 8>;
623 dma-names = "rx", "tx";
624 status = "disabled";
625 };
626
627 uartb: serial@70006040 {
628 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
629 reg = <0x0 0x70006040 0x0 0x40>;
630 reg-shift = <2>;
631 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
633 resets = <&tegra_car 7>;
634 dmas = <&apbdma 9>, <&apbdma 9>;
635 dma-names = "rx", "tx";
636 status = "disabled";
637 };
638
639 uartc: serial@70006200 {
640 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
641 reg = <0x0 0x70006200 0x0 0x40>;
642 reg-shift = <2>;
643 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
645 resets = <&tegra_car 55>;
646 dmas = <&apbdma 10>, <&apbdma 10>;
647 dma-names = "rx", "tx";
648 status = "disabled";
649 };
650
651 uartd: serial@70006300 {
652 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
653 reg = <0x0 0x70006300 0x0 0x40>;
654 reg-shift = <2>;
655 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
657 resets = <&tegra_car 65>;
658 dmas = <&apbdma 19>, <&apbdma 19>;
659 dma-names = "rx", "tx";
660 status = "disabled";
661 };
662
663 pwm: pwm@7000a000 {
664 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
665 reg = <0x0 0x7000a000 0x0 0x100>;
666 #pwm-cells = <2>;
667 clocks = <&tegra_car TEGRA210_CLK_PWM>;
668 resets = <&tegra_car 17>;
669 reset-names = "pwm";
670 status = "disabled";
671 };
672
673 i2c@7000c000 {
674 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
675 reg = <0x0 0x7000c000 0x0 0x100>;
676 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
677 #address-cells = <1>;
678 #size-cells = <0>;
679 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
680 clock-names = "div-clk";
681 resets = <&tegra_car 12>;
682 reset-names = "i2c";
683 dmas = <&apbdma 21>, <&apbdma 21>;
684 dma-names = "rx", "tx";
685 status = "disabled";
686 };
687
688 i2c@7000c400 {
689 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
690 reg = <0x0 0x7000c400 0x0 0x100>;
691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
692 #address-cells = <1>;
693 #size-cells = <0>;
694 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
695 clock-names = "div-clk";
696 resets = <&tegra_car 54>;
697 reset-names = "i2c";
698 dmas = <&apbdma 22>, <&apbdma 22>;
699 dma-names = "rx", "tx";
700 status = "disabled";
701 };
702
703 i2c@7000c500 {
704 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
705 reg = <0x0 0x7000c500 0x0 0x100>;
706 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
707 #address-cells = <1>;
708 #size-cells = <0>;
709 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
710 clock-names = "div-clk";
711 resets = <&tegra_car 67>;
712 reset-names = "i2c";
713 dmas = <&apbdma 23>, <&apbdma 23>;
714 dma-names = "rx", "tx";
715 status = "disabled";
716 };
717
718 i2c@7000c700 {
719 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
720 reg = <0x0 0x7000c700 0x0 0x100>;
721 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
722 #address-cells = <1>;
723 #size-cells = <0>;
724 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
725 clock-names = "div-clk";
726 resets = <&tegra_car 103>;
727 reset-names = "i2c";
728 dmas = <&apbdma 26>, <&apbdma 26>;
729 dma-names = "rx", "tx";
730 pinctrl-0 = <&state_dpaux1_i2c>;
731 pinctrl-1 = <&state_dpaux1_off>;
732 pinctrl-names = "default", "idle";
733 status = "disabled";
734 };
735
736 i2c@7000d000 {
737 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
738 reg = <0x0 0x7000d000 0x0 0x100>;
739 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
740 #address-cells = <1>;
741 #size-cells = <0>;
742 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
743 clock-names = "div-clk";
744 resets = <&tegra_car 47>;
745 reset-names = "i2c";
746 dmas = <&apbdma 24>, <&apbdma 24>;
747 dma-names = "rx", "tx";
748 status = "disabled";
749 };
750
751 i2c@7000d100 {
752 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c";
753 reg = <0x0 0x7000d100 0x0 0x100>;
754 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
755 #address-cells = <1>;
756 #size-cells = <0>;
757 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
758 clock-names = "div-clk";
759 resets = <&tegra_car 166>;
760 reset-names = "i2c";
761 dmas = <&apbdma 30>, <&apbdma 30>;
762 dma-names = "rx", "tx";
763 pinctrl-0 = <&state_dpaux_i2c>;
764 pinctrl-1 = <&state_dpaux_off>;
765 pinctrl-names = "default", "idle";
766 status = "disabled";
767 };
768
769 spi@7000d400 {
770 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
771 reg = <0x0 0x7000d400 0x0 0x200>;
772 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
773 #address-cells = <1>;
774 #size-cells = <0>;
775 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
776 clock-names = "spi";
777 resets = <&tegra_car 41>;
778 reset-names = "spi";
779 dmas = <&apbdma 15>, <&apbdma 15>;
780 dma-names = "rx", "tx";
781 status = "disabled";
782 };
783
784 spi@7000d600 {
785 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
786 reg = <0x0 0x7000d600 0x0 0x200>;
787 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
788 #address-cells = <1>;
789 #size-cells = <0>;
790 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
791 clock-names = "spi";
792 resets = <&tegra_car 44>;
793 reset-names = "spi";
794 dmas = <&apbdma 16>, <&apbdma 16>;
795 dma-names = "rx", "tx";
796 status = "disabled";
797 };
798
799 spi@7000d800 {
800 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
801 reg = <0x0 0x7000d800 0x0 0x200>;
802 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
803 #address-cells = <1>;
804 #size-cells = <0>;
805 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
806 clock-names = "spi";
807 resets = <&tegra_car 46>;
808 reset-names = "spi";
809 dmas = <&apbdma 17>, <&apbdma 17>;
810 dma-names = "rx", "tx";
811 status = "disabled";
812 };
813
814 spi@7000da00 {
815 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
816 reg = <0x0 0x7000da00 0x0 0x200>;
817 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
818 #address-cells = <1>;
819 #size-cells = <0>;
820 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
821 clock-names = "spi";
822 resets = <&tegra_car 68>;
823 reset-names = "spi";
824 dmas = <&apbdma 18>, <&apbdma 18>;
825 dma-names = "rx", "tx";
826 status = "disabled";
827 };
828
829 rtc@7000e000 {
830 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
831 reg = <0x0 0x7000e000 0x0 0x100>;
832 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
833 interrupt-parent = <&tegra_pmc>;
834 clocks = <&tegra_car TEGRA210_CLK_RTC>;
835 clock-names = "rtc";
836 };
837
838 tegra_pmc: pmc@7000e400 {
839 compatible = "nvidia,tegra210-pmc";
840 reg = <0x0 0x7000e400 0x0 0x400>;
841 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
842 clock-names = "pclk", "clk32k_in";
843 #clock-cells = <1>;
844 #interrupt-cells = <2>;
845 interrupt-controller;
846
847 pinmux {
848 pex_dpd_disable: pex-dpd-disable {
849 pins = "pex-bias", "pex-clk1", "pex-clk2";
850 low-power-disable;
851 };
852
853 pex_dpd_enable: pex-dpd-enable {
854 pins = "pex-bias", "pex-clk1", "pex-clk2";
855 low-power-enable;
856 };
857
858 sdmmc1_1v8: sdmmc1-1v8 {
859 pins = "sdmmc1";
860 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
861 };
862
863 sdmmc1_3v3: sdmmc1-3v3 {
864 pins = "sdmmc1";
865 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
866 };
867
868 sdmmc3_1v8: sdmmc3-1v8 {
869 pins = "sdmmc3";
870 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
871 };
872
873 sdmmc3_3v3: sdmmc3-3v3 {
874 pins = "sdmmc3";
875 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
876 };
877 };
878
879 powergates {
880 pd_audio: aud {
881 clocks = <&tegra_car TEGRA210_CLK_APE>,
882 <&tegra_car TEGRA210_CLK_APB2APE>;
883 resets = <&tegra_car 198>;
884 #power-domain-cells = <0>;
885 };
886
887 pd_sor: sor {
888 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
889 <&tegra_car TEGRA210_CLK_SOR1>,
890 <&tegra_car TEGRA210_CLK_CILAB>,
891 <&tegra_car TEGRA210_CLK_CILCD>,
892 <&tegra_car TEGRA210_CLK_CILE>,
893 <&tegra_car TEGRA210_CLK_DSIA>,
894 <&tegra_car TEGRA210_CLK_DSIB>,
895 <&tegra_car TEGRA210_CLK_DPAUX>,
896 <&tegra_car TEGRA210_CLK_DPAUX1>,
897 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
898 resets = <&tegra_car TEGRA210_CLK_SOR0>,
899 <&tegra_car TEGRA210_CLK_SOR1>,
900 <&tegra_car TEGRA210_CLK_DSIA>,
901 <&tegra_car TEGRA210_CLK_DSIB>,
902 <&tegra_car TEGRA210_CLK_DPAUX>,
903 <&tegra_car TEGRA210_CLK_DPAUX1>,
904 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
905 #power-domain-cells = <0>;
906 };
907
908 pd_venc: venc {
909 clocks = <&tegra_car TEGRA210_CLK_VI>,
910 <&tegra_car TEGRA210_CLK_CSI>;
911 resets = <&mc TEGRA210_MC_RESET_VI>,
912 <&tegra_car 20>,
913 <&tegra_car 52>;
914 #power-domain-cells = <0>;
915 };
916
917 pd_vic: vic {
918 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
919 resets = <&tegra_car 178>;
920 #power-domain-cells = <0>;
921 };
922
923 pd_xusbss: xusba {
924 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
925 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
926 #power-domain-cells = <0>;
927 };
928
929 pd_xusbdev: xusbb {
930 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
931 resets = <&tegra_car 95>;
932 #power-domain-cells = <0>;
933 };
934
935 pd_xusbhost: xusbc {
936 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
937 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
938 #power-domain-cells = <0>;
939 };
940 };
941 };
942
943 fuse@7000f800 {
944 compatible = "nvidia,tegra210-efuse";
945 reg = <0x0 0x7000f800 0x0 0x400>;
946 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
947 clock-names = "fuse";
948 resets = <&tegra_car 39>;
949 reset-names = "fuse";
950 };
951
952 mc: memory-controller@70019000 {
953 compatible = "nvidia,tegra210-mc";
954 reg = <0x0 0x70019000 0x0 0x1000>;
955 clocks = <&tegra_car TEGRA210_CLK_MC>;
956 clock-names = "mc";
957
958 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
959
960 #iommu-cells = <1>;
961 #reset-cells = <1>;
962 };
963
964 emc: external-memory-controller@7001b000 {
965 compatible = "nvidia,tegra210-emc";
966 reg = <0x0 0x7001b000 0x0 0x1000>,
967 <0x0 0x7001e000 0x0 0x1000>,
968 <0x0 0x7001f000 0x0 0x1000>;
969 clocks = <&tegra_car TEGRA210_CLK_EMC>;
970 clock-names = "emc";
971 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
972 nvidia,memory-controller = <&mc>;
973 #cooling-cells = <2>;
974 };
975
976 sata@70020000 {
977 compatible = "nvidia,tegra210-ahci";
978 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
979 <0x0 0x70020000 0x0 0x7000>, /* SATA */
980 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
981 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&tegra_car TEGRA210_CLK_SATA>,
983 <&tegra_car TEGRA210_CLK_SATA_OOB>;
984 clock-names = "sata", "sata-oob";
985 resets = <&tegra_car 124>,
986 <&tegra_car 129>,
987 <&tegra_car 123>;
988 reset-names = "sata", "sata-cold", "sata-oob";
989 status = "disabled";
990 };
991
992 hda@70030000 {
993 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
994 reg = <0x0 0x70030000 0x0 0x10000>;
995 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&tegra_car TEGRA210_CLK_HDA>,
997 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
998 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
999 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
1000 resets = <&tegra_car 125>, /* hda */
1001 <&tegra_car 128>, /* hda2hdmi */
1002 <&tegra_car 111>; /* hda2codec_2x */
1003 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
1004 power-domains = <&pd_sor>;
1005 status = "disabled";
1006 };
1007
1008 usb@70090000 {
1009 compatible = "nvidia,tegra210-xusb";
1010 reg = <0x0 0x70090000 0x0 0x8000>,
1011 <0x0 0x70098000 0x0 0x1000>,
1012 <0x0 0x70099000 0x0 0x1000>;
1013 reg-names = "hcd", "fpci", "ipfs";
1014
1015 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1016 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1017
1018 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
1019 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
1020 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
1021 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1022 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
1023 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
1024 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
1025 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1026 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
1027 <&tegra_car TEGRA210_CLK_CLK_M>,
1028 <&tegra_car TEGRA210_CLK_PLL_E>;
1029 clock-names = "xusb_host", "xusb_host_src",
1030 "xusb_falcon_src", "xusb_ss",
1031 "xusb_ss_div2", "xusb_ss_src",
1032 "xusb_hs_src", "xusb_fs_src",
1033 "pll_u_480m", "clk_m", "pll_e";
1034 resets = <&tegra_car 89>, <&tegra_car 156>,
1035 <&tegra_car 143>;
1036 reset-names = "xusb_host", "xusb_ss", "xusb_src";
1037 power-domains = <&pd_xusbhost>, <&pd_xusbss>;
1038 power-domain-names = "xusb_host", "xusb_ss";
1039
1040 nvidia,xusb-padctl = <&padctl>;
1041
1042 status = "disabled";
1043 };
1044
1045 padctl: padctl@7009f000 {
1046 compatible = "nvidia,tegra210-xusb-padctl";
1047 reg = <0x0 0x7009f000 0x0 0x1000>;
1048 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1049 resets = <&tegra_car 142>;
1050 reset-names = "padctl";
1051 nvidia,pmc = <&tegra_pmc>;
1052
1053 status = "disabled";
1054
1055 pads {
1056 usb2 {
1057 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
1058 clock-names = "trk";
1059 status = "disabled";
1060
1061 lanes {
1062 usb2-0 {
1063 status = "disabled";
1064 #phy-cells = <0>;
1065 };
1066
1067 usb2-1 {
1068 status = "disabled";
1069 #phy-cells = <0>;
1070 };
1071
1072 usb2-2 {
1073 status = "disabled";
1074 #phy-cells = <0>;
1075 };
1076
1077 usb2-3 {
1078 status = "disabled";
1079 #phy-cells = <0>;
1080 };
1081 };
1082 };
1083
1084 hsic {
1085 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
1086 clock-names = "trk";
1087 status = "disabled";
1088
1089 lanes {
1090 hsic-0 {
1091 status = "disabled";
1092 #phy-cells = <0>;
1093 };
1094
1095 hsic-1 {
1096 status = "disabled";
1097 #phy-cells = <0>;
1098 };
1099 };
1100 };
1101
1102 pcie {
1103 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1104 clock-names = "pll";
1105 resets = <&tegra_car 205>;
1106 reset-names = "phy";
1107 status = "disabled";
1108
1109 lanes {
1110 pcie-0 {
1111 status = "disabled";
1112 #phy-cells = <0>;
1113 };
1114
1115 pcie-1 {
1116 status = "disabled";
1117 #phy-cells = <0>;
1118 };
1119
1120 pcie-2 {
1121 status = "disabled";
1122 #phy-cells = <0>;
1123 };
1124
1125 pcie-3 {
1126 status = "disabled";
1127 #phy-cells = <0>;
1128 };
1129
1130 pcie-4 {
1131 status = "disabled";
1132 #phy-cells = <0>;
1133 };
1134
1135 pcie-5 {
1136 status = "disabled";
1137 #phy-cells = <0>;
1138 };
1139
1140 pcie-6 {
1141 status = "disabled";
1142 #phy-cells = <0>;
1143 };
1144 };
1145 };
1146
1147 sata {
1148 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
1149 clock-names = "pll";
1150 resets = <&tegra_car 204>;
1151 reset-names = "phy";
1152 status = "disabled";
1153
1154 lanes {
1155 sata-0 {
1156 status = "disabled";
1157 #phy-cells = <0>;
1158 };
1159 };
1160 };
1161 };
1162
1163 ports {
1164 usb2-0 {
1165 status = "disabled";
1166 };
1167
1168 usb2-1 {
1169 status = "disabled";
1170 };
1171
1172 usb2-2 {
1173 status = "disabled";
1174 };
1175
1176 usb2-3 {
1177 status = "disabled";
1178 };
1179
1180 hsic-0 {
1181 status = "disabled";
1182 };
1183
1184 usb3-0 {
1185 status = "disabled";
1186 };
1187
1188 usb3-1 {
1189 status = "disabled";
1190 };
1191
1192 usb3-2 {
1193 status = "disabled";
1194 };
1195
1196 usb3-3 {
1197 status = "disabled";
1198 };
1199 };
1200 };
1201
1202 mmc@700b0000 {
1203 compatible = "nvidia,tegra210-sdhci";
1204 reg = <0x0 0x700b0000 0x0 0x200>;
1205 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
1207 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1208 clock-names = "sdhci", "tmclk";
1209 resets = <&tegra_car 14>;
1210 reset-names = "sdhci";
1211 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1212 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1213 pinctrl-0 = <&sdmmc1_3v3>;
1214 pinctrl-1 = <&sdmmc1_1v8>;
1215 pinctrl-2 = <&sdmmc1_3v3_drv>;
1216 pinctrl-3 = <&sdmmc1_1v8_drv>;
1217 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1218 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1219 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1220 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1221 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x0>;
1222 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x0>;
1223 nvidia,default-tap = <0x2>;
1224 nvidia,default-trim = <0x4>;
1225 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1226 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1227 <&tegra_car TEGRA210_CLK_PLL_C4>;
1228 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1229 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;
1230 status = "disabled";
1231 };
1232
1233 mmc@700b0200 {
1234 compatible = "nvidia,tegra210-sdhci";
1235 reg = <0x0 0x700b0200 0x0 0x200>;
1236 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
1238 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1239 clock-names = "sdhci", "tmclk";
1240 resets = <&tegra_car 9>;
1241 reset-names = "sdhci";
1242 pinctrl-names = "sdmmc-1v8-drv";
1243 pinctrl-0 = <&sdmmc2_1v8_drv>;
1244 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1245 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1246 nvidia,default-tap = <0x8>;
1247 nvidia,default-trim = <0x0>;
1248 status = "disabled";
1249 };
1250
1251 mmc@700b0400 {
1252 compatible = "nvidia,tegra210-sdhci";
1253 reg = <0x0 0x700b0400 0x0 0x200>;
1254 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1255 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
1256 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1257 clock-names = "sdhci", "tmclk";
1258 resets = <&tegra_car 69>;
1259 reset-names = "sdhci";
1260 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
1261 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1262 pinctrl-0 = <&sdmmc3_3v3>;
1263 pinctrl-1 = <&sdmmc3_1v8>;
1264 pinctrl-2 = <&sdmmc3_3v3_drv>;
1265 pinctrl-3 = <&sdmmc3_1v8_drv>;
1266 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
1267 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
1268 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
1269 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
1270 nvidia,default-tap = <0x3>;
1271 nvidia,default-trim = <0x3>;
1272 status = "disabled";
1273 };
1274
1275 mmc@700b0600 {
1276 compatible = "nvidia,tegra210-sdhci";
1277 reg = <0x0 0x700b0600 0x0 0x200>;
1278 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1279 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1280 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
1281 clock-names = "sdhci", "tmclk";
1282 resets = <&tegra_car 15>;
1283 reset-names = "sdhci";
1284 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
1285 pinctrl-0 = <&sdmmc4_1v8_drv>;
1286 pinctrl-1 = <&sdmmc4_1v8_drv>;
1287 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
1288 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
1289 nvidia,default-tap = <0x8>;
1290 nvidia,default-trim = <0x0>;
1291 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
1292 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1293 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1294 nvidia,dqs-trim = <40>;
1295 mmc-hs400-1_8v;
1296 status = "disabled";
1297 };
1298
1299 usb@700d0000 {
1300 compatible = "nvidia,tegra210-xudc";
1301 reg = <0x0 0x700d0000 0x0 0x8000>,
1302 <0x0 0x700d8000 0x0 0x1000>,
1303 <0x0 0x700d9000 0x0 0x1000>;
1304 reg-names = "base", "fpci", "ipfs";
1305 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1306 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>,
1307 <&tegra_car TEGRA210_CLK_XUSB_SS>,
1308 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>,
1309 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
1310 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>;
1311 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src";
1312 power-domains = <&pd_xusbdev>, <&pd_xusbss>;
1313 power-domain-names = "dev", "ss";
1314 nvidia,xusb-padctl = <&padctl>;
1315 status = "disabled";
1316 };
1317
1318 soctherm: thermal-sensor@700e2000 {
1319 compatible = "nvidia,tegra210-soctherm";
1320 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1321 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1322 reg-names = "soctherm-reg", "car-reg";
1323 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1325 interrupt-names = "thermal", "edp";
1326 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1327 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1328 clock-names = "tsensor", "soctherm";
1329 resets = <&tegra_car 78>;
1330 reset-names = "soctherm";
1331 #thermal-sensor-cells = <1>;
1332
1333 throttle-cfgs {
1334 throttle_heavy: heavy {
1335 nvidia,priority = <100>;
1336 nvidia,cpu-throt-percent = <85>;
1337 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>;
1338
1339 #cooling-cells = <2>;
1340 };
1341 };
1342 };
1343
1344 mipi: mipi@700e3000 {
1345 compatible = "nvidia,tegra210-mipi";
1346 reg = <0x0 0x700e3000 0x0 0x100>;
1347 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1348 clock-names = "mipi-cal";
1349 power-domains = <&pd_sor>;
1350 #nvidia,mipi-calibrate-cells = <1>;
1351 };
1352
1353 dfll: clock@70110000 {
1354 compatible = "nvidia,tegra210-dfll";
1355 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1356 <0 0x70110000 0 0x100>, /* I2C output control */
1357 <0 0x70110100 0 0x100>, /* Integrated I2C controller */
1358 <0 0x70110200 0 0x100>; /* Look-up table RAM */
1359 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1360 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
1361 <&tegra_car TEGRA210_CLK_DFLL_REF>,
1362 <&tegra_car TEGRA210_CLK_I2C5>;
1363 clock-names = "soc", "ref", "i2c";
1364 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
1365 <&tegra_car 155>;
1366 reset-names = "dvco", "dfll";
1367 #clock-cells = <0>;
1368 clock-output-names = "dfllCPU_out";
1369 status = "disabled";
1370 };
1371
1372 aconnect@702c0000 {
1373 compatible = "nvidia,tegra210-aconnect";
1374 clocks = <&tegra_car TEGRA210_CLK_APE>,
1375 <&tegra_car TEGRA210_CLK_APB2APE>;
1376 clock-names = "ape", "apb2ape";
1377 power-domains = <&pd_audio>;
1378 #address-cells = <1>;
1379 #size-cells = <1>;
1380 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1381 status = "disabled";
1382
1383 tegra_ahub: ahub@702d0800 {
1384 compatible = "nvidia,tegra210-ahub";
1385 reg = <0x702d0800 0x800>;
1386 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1387 clock-names = "ahub";
1388 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1389 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;
1390 assigned-clock-rates = <81600000>;
1391 #address-cells = <1>;
1392 #size-cells = <1>;
1393 ranges = <0x702d0000 0x702d0000 0x0000e400>;
1394 status = "disabled";
1395
1396 tegra_admaif: admaif@702d0000 {
1397 compatible = "nvidia,tegra210-admaif";
1398 reg = <0x702d0000 0x800>;
1399 dmas = <&adma 1>, <&adma 1>,
1400 <&adma 2>, <&adma 2>,
1401 <&adma 3>, <&adma 3>,
1402 <&adma 4>, <&adma 4>,
1403 <&adma 5>, <&adma 5>,
1404 <&adma 6>, <&adma 6>,
1405 <&adma 7>, <&adma 7>,
1406 <&adma 8>, <&adma 8>,
1407 <&adma 9>, <&adma 9>,
1408 <&adma 10>, <&adma 10>;
1409 dma-names = "rx1", "tx1",
1410 "rx2", "tx2",
1411 "rx3", "tx3",
1412 "rx4", "tx4",
1413 "rx5", "tx5",
1414 "rx6", "tx6",
1415 "rx7", "tx7",
1416 "rx8", "tx8",
1417 "rx9", "tx9",
1418 "rx10", "tx10";
1419 status = "disabled";
1420
1421 ports {
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1424
1425 admaif1_port: port@0 {
1426 reg = <0>;
1427
1428 admaif1_ep: endpoint {
1429 remote-endpoint = <&xbar_admaif1_ep>;
1430 };
1431 };
1432
1433 admaif2_port: port@1 {
1434 reg = <1>;
1435
1436 admaif2_ep: endpoint {
1437 remote-endpoint = <&xbar_admaif2_ep>;
1438 };
1439 };
1440
1441 admaif3_port: port@2 {
1442 reg = <2>;
1443
1444 admaif3_ep: endpoint {
1445 remote-endpoint = <&xbar_admaif3_ep>;
1446 };
1447 };
1448
1449 admaif4_port: port@3 {
1450 reg = <3>;
1451
1452 admaif4_ep: endpoint {
1453 remote-endpoint = <&xbar_admaif4_ep>;
1454 };
1455 };
1456
1457 admaif5_port: port@4 {
1458 reg = <4>;
1459
1460 admaif5_ep: endpoint {
1461 remote-endpoint = <&xbar_admaif5_ep>;
1462 };
1463 };
1464
1465 admaif6_port: port@5 {
1466 reg = <5>;
1467
1468 admaif6_ep: endpoint {
1469 remote-endpoint = <&xbar_admaif6_ep>;
1470 };
1471 };
1472
1473 admaif7_port: port@6 {
1474 reg = <6>;
1475
1476 admaif7_ep: endpoint {
1477 remote-endpoint = <&xbar_admaif7_ep>;
1478 };
1479 };
1480
1481 admaif8_port: port@7 {
1482 reg = <7>;
1483
1484 admaif8_ep: endpoint {
1485 remote-endpoint = <&xbar_admaif8_ep>;
1486 };
1487 };
1488
1489 admaif9_port: port@8 {
1490 reg = <8>;
1491
1492 admaif9_ep: endpoint {
1493 remote-endpoint = <&xbar_admaif9_ep>;
1494 };
1495 };
1496
1497 admaif10_port: port@9 {
1498 reg = <9>;
1499
1500 admaif10_ep: endpoint {
1501 remote-endpoint = <&xbar_admaif10_ep>;
1502 };
1503 };
1504 };
1505 };
1506
1507 tegra_i2s1: i2s@702d1000 {
1508 compatible = "nvidia,tegra210-i2s";
1509 reg = <0x702d1000 0x100>;
1510 clocks = <&tegra_car TEGRA210_CLK_I2S0>,
1511 <&tegra_car TEGRA210_CLK_I2S0_SYNC>;
1512 clock-names = "i2s", "sync_input";
1513 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
1514 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1515 assigned-clock-rates = <1536000>;
1516 sound-name-prefix = "I2S1";
1517 status = "disabled";
1518 };
1519
1520 tegra_i2s2: i2s@702d1100 {
1521 compatible = "nvidia,tegra210-i2s";
1522 reg = <0x702d1100 0x100>;
1523 clocks = <&tegra_car TEGRA210_CLK_I2S1>,
1524 <&tegra_car TEGRA210_CLK_I2S1_SYNC>;
1525 clock-names = "i2s", "sync_input";
1526 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>;
1527 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1528 assigned-clock-rates = <1536000>;
1529 sound-name-prefix = "I2S2";
1530 status = "disabled";
1531 };
1532
1533 tegra_i2s3: i2s@702d1200 {
1534 compatible = "nvidia,tegra210-i2s";
1535 reg = <0x702d1200 0x100>;
1536 clocks = <&tegra_car TEGRA210_CLK_I2S2>,
1537 <&tegra_car TEGRA210_CLK_I2S2_SYNC>;
1538 clock-names = "i2s", "sync_input";
1539 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>;
1540 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1541 assigned-clock-rates = <1536000>;
1542 sound-name-prefix = "I2S3";
1543 status = "disabled";
1544 };
1545
1546 tegra_i2s4: i2s@702d1300 {
1547 compatible = "nvidia,tegra210-i2s";
1548 reg = <0x702d1300 0x100>;
1549 clocks = <&tegra_car TEGRA210_CLK_I2S3>,
1550 <&tegra_car TEGRA210_CLK_I2S3_SYNC>;
1551 clock-names = "i2s", "sync_input";
1552 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>;
1553 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1554 assigned-clock-rates = <1536000>;
1555 sound-name-prefix = "I2S4";
1556 status = "disabled";
1557 };
1558
1559 tegra_i2s5: i2s@702d1400 {
1560 compatible = "nvidia,tegra210-i2s";
1561 reg = <0x702d1400 0x100>;
1562 clocks = <&tegra_car TEGRA210_CLK_I2S4>,
1563 <&tegra_car TEGRA210_CLK_I2S4_SYNC>;
1564 clock-names = "i2s", "sync_input";
1565 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>;
1566 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1567 assigned-clock-rates = <1536000>;
1568 sound-name-prefix = "I2S5";
1569 status = "disabled";
1570 };
1571
1572 tegra_sfc1: sfc@702d2000 {
1573 compatible = "nvidia,tegra210-sfc";
1574 reg = <0x702d2000 0x200>;
1575 sound-name-prefix = "SFC1";
1576 status = "disabled";
1577 };
1578
1579 tegra_sfc2: sfc@702d2200 {
1580 compatible = "nvidia,tegra210-sfc";
1581 reg = <0x702d2200 0x200>;
1582 sound-name-prefix = "SFC2";
1583 status = "disabled";
1584 };
1585
1586 tegra_sfc3: sfc@702d2400 {
1587 compatible = "nvidia,tegra210-sfc";
1588 reg = <0x702d2400 0x200>;
1589 sound-name-prefix = "SFC3";
1590 status = "disabled";
1591 };
1592
1593 tegra_sfc4: sfc@702d2600 {
1594 compatible = "nvidia,tegra210-sfc";
1595 reg = <0x702d2600 0x200>;
1596 sound-name-prefix = "SFC4";
1597 status = "disabled";
1598 };
1599
1600 tegra_amx1: amx@702d3000 {
1601 compatible = "nvidia,tegra210-amx";
1602 reg = <0x702d3000 0x100>;
1603 sound-name-prefix = "AMX1";
1604 status = "disabled";
1605 };
1606
1607 tegra_amx2: amx@702d3100 {
1608 compatible = "nvidia,tegra210-amx";
1609 reg = <0x702d3100 0x100>;
1610 sound-name-prefix = "AMX2";
1611 status = "disabled";
1612 };
1613
1614 tegra_adx1: adx@702d3800 {
1615 compatible = "nvidia,tegra210-adx";
1616 reg = <0x702d3800 0x100>;
1617 sound-name-prefix = "ADX1";
1618 status = "disabled";
1619 };
1620
1621 tegra_adx2: adx@702d3900 {
1622 compatible = "nvidia,tegra210-adx";
1623 reg = <0x702d3900 0x100>;
1624 sound-name-prefix = "ADX2";
1625 status = "disabled";
1626 };
1627
1628 tegra_dmic1: dmic@702d4000 {
1629 compatible = "nvidia,tegra210-dmic";
1630 reg = <0x702d4000 0x100>;
1631 clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1632 clock-names = "dmic";
1633 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>;
1634 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1635 assigned-clock-rates = <3072000>;
1636 sound-name-prefix = "DMIC1";
1637 status = "disabled";
1638 };
1639
1640 tegra_dmic2: dmic@702d4100 {
1641 compatible = "nvidia,tegra210-dmic";
1642 reg = <0x702d4100 0x100>;
1643 clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1644 clock-names = "dmic";
1645 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>;
1646 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1647 assigned-clock-rates = <3072000>;
1648 sound-name-prefix = "DMIC2";
1649 status = "disabled";
1650 };
1651
1652 tegra_dmic3: dmic@702d4200 {
1653 compatible = "nvidia,tegra210-dmic";
1654 reg = <0x702d4200 0x100>;
1655 clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1656 clock-names = "dmic";
1657 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>;
1658 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1659 assigned-clock-rates = <3072000>;
1660 sound-name-prefix = "DMIC3";
1661 status = "disabled";
1662 };
1663
1664 tegra_ope1: processing-engine@702d8000 {
1665 compatible = "nvidia,tegra210-ope";
1666 reg = <0x702d8000 0x100>;
1667 #address-cells = <1>;
1668 #size-cells = <1>;
1669 ranges;
1670 sound-name-prefix = "OPE1";
1671 status = "disabled";
1672
1673 equalizer@702d8100 {
1674 compatible = "nvidia,tegra210-peq";
1675 reg = <0x702d8100 0x100>;
1676 };
1677
1678 dynamic-range-compressor@702d8200 {
1679 compatible = "nvidia,tegra210-mbdrc";
1680 reg = <0x702d8200 0x200>;
1681 };
1682 };
1683
1684 tegra_ope2: processing-engine@702d8400 {
1685 compatible = "nvidia,tegra210-ope";
1686 reg = <0x702d8400 0x100>;
1687 #address-cells = <1>;
1688 #size-cells = <1>;
1689 ranges;
1690 sound-name-prefix = "OPE2";
1691 status = "disabled";
1692
1693 equalizer@702d8500 {
1694 compatible = "nvidia,tegra210-peq";
1695 reg = <0x702d8500 0x100>;
1696 };
1697
1698 dynamic-range-compressor@702d8600 {
1699 compatible = "nvidia,tegra210-mbdrc";
1700 reg = <0x702d8600 0x200>;
1701 };
1702 };
1703
1704 tegra_mvc1: mvc@702da000 {
1705 compatible = "nvidia,tegra210-mvc";
1706 reg = <0x702da000 0x200>;
1707 sound-name-prefix = "MVC1";
1708 status = "disabled";
1709 };
1710
1711 tegra_mvc2: mvc@702da200 {
1712 compatible = "nvidia,tegra210-mvc";
1713 reg = <0x702da200 0x200>;
1714 sound-name-prefix = "MVC2";
1715 status = "disabled";
1716 };
1717
1718 tegra_amixer: amixer@702dbb00 {
1719 compatible = "nvidia,tegra210-amixer";
1720 reg = <0x702dbb00 0x800>;
1721 sound-name-prefix = "MIXER1";
1722 status = "disabled";
1723 };
1724
1725 ports {
1726 #address-cells = <1>;
1727 #size-cells = <0>;
1728
1729 port@0 {
1730 reg = <0x0>;
1731
1732 xbar_admaif1_ep: endpoint {
1733 remote-endpoint = <&admaif1_ep>;
1734 };
1735 };
1736
1737 port@1 {
1738 reg = <0x1>;
1739
1740 xbar_admaif2_ep: endpoint {
1741 remote-endpoint = <&admaif2_ep>;
1742 };
1743 };
1744
1745 port@2 {
1746 reg = <0x2>;
1747
1748 xbar_admaif3_ep: endpoint {
1749 remote-endpoint = <&admaif3_ep>;
1750 };
1751 };
1752
1753 port@3 {
1754 reg = <0x3>;
1755
1756 xbar_admaif4_ep: endpoint {
1757 remote-endpoint = <&admaif4_ep>;
1758 };
1759 };
1760
1761 port@4 {
1762 reg = <0x4>;
1763 xbar_admaif5_ep: endpoint {
1764 remote-endpoint = <&admaif5_ep>;
1765 };
1766 };
1767 port@5 {
1768 reg = <0x5>;
1769
1770 xbar_admaif6_ep: endpoint {
1771 remote-endpoint = <&admaif6_ep>;
1772 };
1773 };
1774
1775 port@6 {
1776 reg = <0x6>;
1777
1778 xbar_admaif7_ep: endpoint {
1779 remote-endpoint = <&admaif7_ep>;
1780 };
1781 };
1782
1783 port@7 {
1784 reg = <0x7>;
1785
1786 xbar_admaif8_ep: endpoint {
1787 remote-endpoint = <&admaif8_ep>;
1788 };
1789 };
1790
1791 port@8 {
1792 reg = <0x8>;
1793
1794 xbar_admaif9_ep: endpoint {
1795 remote-endpoint = <&admaif9_ep>;
1796 };
1797 };
1798
1799 port@9 {
1800 reg = <0x9>;
1801
1802 xbar_admaif10_ep: endpoint {
1803 remote-endpoint = <&admaif10_ep>;
1804 };
1805 };
1806 };
1807 };
1808
1809 adma: dma-controller@702e2000 {
1810 compatible = "nvidia,tegra210-adma";
1811 reg = <0x702e2000 0x2000>;
1812 interrupt-parent = <&agic>;
1813 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1835 #dma-cells = <1>;
1836 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1837 clock-names = "d_audio";
1838 status = "disabled";
1839 };
1840
1841 agic: interrupt-controller@702f9000 {
1842 compatible = "nvidia,tegra210-agic";
1843 #interrupt-cells = <3>;
1844 interrupt-controller;
1845 reg = <0x702f9000 0x1000>,
1846 <0x702fa000 0x2000>;
1847 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1848 clocks = <&tegra_car TEGRA210_CLK_APE>;
1849 clock-names = "clk";
1850 status = "disabled";
1851 };
1852 };
1853
1854 spi@70410000 {
1855 compatible = "nvidia,tegra210-qspi";
1856 reg = <0x0 0x70410000 0x0 0x1000>;
1857 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1858 #address-cells = <1>;
1859 #size-cells = <0>;
1860 clocks = <&tegra_car TEGRA210_CLK_QSPI>,
1861 <&tegra_car TEGRA210_CLK_QSPI_PM>;
1862 clock-names = "qspi", "qspi_out";
1863 resets = <&tegra_car 211>;
1864 dmas = <&apbdma 5>, <&apbdma 5>;
1865 dma-names = "rx", "tx";
1866 status = "disabled";
1867 };
1868
1869 usb@7d000000 {
1870 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
1871 reg = <0x0 0x7d000000 0x0 0x4000>;
1872 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1873 phy_type = "utmi";
1874 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1875 clock-names = "usb";
1876 resets = <&tegra_car 22>;
1877 reset-names = "usb";
1878 nvidia,phy = <&phy1>;
1879 status = "disabled";
1880 };
1881
1882 phy1: usb-phy@7d000000 {
1883 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1884 reg = <0x0 0x7d000000 0x0 0x4000>,
1885 <0x0 0x7d000000 0x0 0x4000>;
1886 phy_type = "utmi";
1887 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1888 <&tegra_car TEGRA210_CLK_PLL_U>,
1889 <&tegra_car TEGRA210_CLK_USBD>;
1890 clock-names = "reg", "pll_u", "utmi-pads";
1891 resets = <&tegra_car 22>, <&tegra_car 22>;
1892 reset-names = "usb", "utmi-pads";
1893 nvidia,hssync-start-delay = <0>;
1894 nvidia,idle-wait-delay = <17>;
1895 nvidia,elastic-limit = <16>;
1896 nvidia,term-range-adj = <6>;
1897 nvidia,xcvr-setup = <9>;
1898 nvidia,xcvr-lsfslew = <0>;
1899 nvidia,xcvr-lsrslew = <3>;
1900 nvidia,hssquelch-level = <2>;
1901 nvidia,hsdiscon-level = <5>;
1902 nvidia,xcvr-hsslew = <12>;
1903 nvidia,has-utmi-pad-registers;
1904 status = "disabled";
1905 };
1906
1907 usb@7d004000 {
1908 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci";
1909 reg = <0x0 0x7d004000 0x0 0x4000>;
1910 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1911 phy_type = "utmi";
1912 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1913 clock-names = "usb";
1914 resets = <&tegra_car 58>;
1915 reset-names = "usb";
1916 nvidia,phy = <&phy2>;
1917 status = "disabled";
1918 };
1919
1920 phy2: usb-phy@7d004000 {
1921 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1922 reg = <0x0 0x7d004000 0x0 0x4000>,
1923 <0x0 0x7d000000 0x0 0x4000>;
1924 phy_type = "utmi";
1925 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1926 <&tegra_car TEGRA210_CLK_PLL_U>,
1927 <&tegra_car TEGRA210_CLK_USBD>;
1928 clock-names = "reg", "pll_u", "utmi-pads";
1929 resets = <&tegra_car 58>, <&tegra_car 22>;
1930 reset-names = "usb", "utmi-pads";
1931 nvidia,hssync-start-delay = <0>;
1932 nvidia,idle-wait-delay = <17>;
1933 nvidia,elastic-limit = <16>;
1934 nvidia,term-range-adj = <6>;
1935 nvidia,xcvr-setup = <9>;
1936 nvidia,xcvr-lsfslew = <0>;
1937 nvidia,xcvr-lsrslew = <3>;
1938 nvidia,hssquelch-level = <2>;
1939 nvidia,hsdiscon-level = <5>;
1940 nvidia,xcvr-hsslew = <12>;
1941 status = "disabled";
1942 };
1943
1944 cpus {
1945 #address-cells = <1>;
1946 #size-cells = <0>;
1947
1948 cpu@0 {
1949 device_type = "cpu";
1950 compatible = "arm,cortex-a57";
1951 reg = <0>;
1952 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
1953 <&tegra_car TEGRA210_CLK_PLL_X>,
1954 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>,
1955 <&dfll>;
1956 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
1957 clock-latency = <300000>;
1958 cpu-idle-states = <&CPU_SLEEP>;
1959 next-level-cache = <&L2>;
1960 };
1961
1962 cpu@1 {
1963 device_type = "cpu";
1964 compatible = "arm,cortex-a57";
1965 reg = <1>;
1966 cpu-idle-states = <&CPU_SLEEP>;
1967 next-level-cache = <&L2>;
1968 };
1969
1970 cpu@2 {
1971 device_type = "cpu";
1972 compatible = "arm,cortex-a57";
1973 reg = <2>;
1974 cpu-idle-states = <&CPU_SLEEP>;
1975 next-level-cache = <&L2>;
1976 };
1977
1978 cpu@3 {
1979 device_type = "cpu";
1980 compatible = "arm,cortex-a57";
1981 reg = <3>;
1982 cpu-idle-states = <&CPU_SLEEP>;
1983 next-level-cache = <&L2>;
1984 };
1985
1986 idle-states {
1987 entry-method = "psci";
1988
1989 CPU_SLEEP: cpu-sleep {
1990 compatible = "arm,idle-state";
1991 arm,psci-suspend-param = <0x40000007>;
1992 entry-latency-us = <100>;
1993 exit-latency-us = <30>;
1994 min-residency-us = <1000>;
1995 wakeup-latency-us = <130>;
1996 idle-state-name = "cpu-sleep";
1997 status = "disabled";
1998 };
1999 };
2000
2001 L2: l2-cache {
2002 compatible = "cache";
2003 cache-level = <2>;
2004 cache-unified;
2005 };
2006 };
2007
2008 pmu {
2009 compatible = "arm,cortex-a57-pmu";
2010 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2013 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2014 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1}
2015 &{/cpus/cpu@2} &{/cpus/cpu@3}>;
2016 };
2017
2018 sound {
2019 status = "disabled";
2020
2021 clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
2022 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2023 clock-names = "pll_a", "plla_out0";
2024
2025 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
2026 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
2027 <&tegra_car TEGRA210_CLK_EXTERN1>;
2028 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2029 assigned-clock-rates = <368640000>, <49152000>, <12288000>;
2030 };
2031
2032 thermal-zones {
2033 cpu-thermal {
2034 polling-delay-passive = <1000>;
2035 polling-delay = <0>;
2036
2037 thermal-sensors =
2038 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
2039
2040 trips {
2041 cpu-shutdown-trip {
2042 temperature = <102500>;
2043 hysteresis = <0>;
2044 type = "critical";
2045 };
2046
2047 cpu_throttle_trip: throttle-trip {
2048 temperature = <98500>;
2049 hysteresis = <1000>;
2050 type = "hot";
2051 };
2052 };
2053
2054 cooling-maps {
2055 map0 {
2056 trip = <&cpu_throttle_trip>;
2057 cooling-device = <&throttle_heavy 1 1>;
2058 };
2059 };
2060 };
2061
2062 mem-thermal {
2063 polling-delay-passive = <0>;
2064 polling-delay = <0>;
2065
2066 thermal-sensors =
2067 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
2068
2069 trips {
2070 dram_nominal: mem-nominal-trip {
2071 temperature = <50000>;
2072 hysteresis = <1000>;
2073 type = "passive";
2074 };
2075
2076 dram_throttle: mem-throttle-trip {
2077 temperature = <70000>;
2078 hysteresis = <1000>;
2079 type = "active";
2080 };
2081
2082 mem-hot-trip {
2083 temperature = <100000>;
2084 hysteresis = <1000>;
2085 type = "hot";
2086 };
2087
2088 mem-shutdown-trip {
2089 temperature = <103000>;
2090 hysteresis = <0>;
2091 type = "critical";
2092 };
2093 };
2094
2095 cooling-maps {
2096 dram-passive {
2097 cooling-device = <&emc 0 0>;
2098 trip = <&dram_nominal>;
2099 };
2100
2101 dram-active {
2102 cooling-device = <&emc 1 1>;
2103 trip = <&dram_throttle>;
2104 };
2105 };
2106 };
2107
2108 gpu-thermal {
2109 polling-delay-passive = <1000>;
2110 polling-delay = <0>;
2111
2112 thermal-sensors =
2113 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
2114
2115 trips {
2116 gpu-shutdown-trip {
2117 temperature = <103000>;
2118 hysteresis = <0>;
2119 type = "critical";
2120 };
2121
2122 gpu_throttle_trip: throttle-trip {
2123 temperature = <100000>;
2124 hysteresis = <1000>;
2125 type = "hot";
2126 };
2127 };
2128
2129 cooling-maps {
2130 map0 {
2131 trip = <&gpu_throttle_trip>;
2132 cooling-device = <&throttle_heavy 1 1>;
2133 };
2134 };
2135 };
2136
2137 pllx-thermal {
2138 polling-delay-passive = <0>;
2139 polling-delay = <0>;
2140
2141 thermal-sensors =
2142 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
2143
2144 trips {
2145 pllx-shutdown-trip {
2146 temperature = <103000>;
2147 hysteresis = <0>;
2148 type = "critical";
2149 };
2150
2151 pllx-throttle-trip {
2152 temperature = <100000>;
2153 hysteresis = <1000>;
2154 type = "hot";
2155 };
2156 };
2157
2158 cooling-maps {
2159 /*
2160 * There are currently no cooling maps,
2161 * because there are no cooling devices.
2162 */
2163 };
2164 };
2165 };
2166
2167 timer {
2168 compatible = "arm,armv8-timer";
2169 interrupts = <GIC_PPI 13
2170 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2171 <GIC_PPI 14
2172 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2173 <GIC_PPI 11
2174 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
2175 <GIC_PPI 10
2176 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
2177 interrupt-parent = <&gic>;
2178 arm,no-tick-in-suspend;
2179 };
2180};
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra210-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra210-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/thermal/tegra124-soctherm.h>
8
9/ {
10 compatible = "nvidia,tegra210";
11 interrupt-parent = <&lic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 pcie@1003000 {
16 compatible = "nvidia,tegra210-pcie";
17 device_type = "pci";
18 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
19 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
20 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
21 reg-names = "pads", "afi", "cs";
22 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
23 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
24 interrupt-names = "intr", "msi";
25
26 #interrupt-cells = <1>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29
30 bus-range = <0x00 0xff>;
31 #address-cells = <3>;
32 #size-cells = <2>;
33
34 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
35 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
36 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
37 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
38 0xc2000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */
39
40 clocks = <&tegra_car TEGRA210_CLK_PCIE>,
41 <&tegra_car TEGRA210_CLK_AFI>,
42 <&tegra_car TEGRA210_CLK_PLL_E>,
43 <&tegra_car TEGRA210_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
46 <&tegra_car 72>,
47 <&tegra_car 74>;
48 reset-names = "pex", "afi", "pcie_x";
49 status = "disabled";
50
51 pci@1,0 {
52 device_type = "pci";
53 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>;
54 reg = <0x000800 0 0 0 0>;
55 bus-range = <0x00 0xff>;
56 status = "disabled";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges;
61
62 nvidia,num-lanes = <4>;
63 };
64
65 pci@2,0 {
66 device_type = "pci";
67 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
69 bus-range = <0x00 0xff>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <1>;
77 };
78 };
79
80 host1x@50000000 {
81 compatible = "nvidia,tegra210-host1x", "simple-bus";
82 reg = <0x0 0x50000000 0x0 0x00034000>;
83 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
84 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
85 clocks = <&tegra_car TEGRA210_CLK_HOST1X>;
86 clock-names = "host1x";
87 resets = <&tegra_car 28>;
88 reset-names = "host1x";
89
90 #address-cells = <2>;
91 #size-cells = <2>;
92
93 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>;
94
95 iommus = <&mc TEGRA_SWGROUP_HC>;
96
97 dpaux1: dpaux@54040000 {
98 compatible = "nvidia,tegra210-dpaux";
99 reg = <0x0 0x54040000 0x0 0x00040000>;
100 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
101 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>,
102 <&tegra_car TEGRA210_CLK_PLL_DP>;
103 clock-names = "dpaux", "parent";
104 resets = <&tegra_car 207>;
105 reset-names = "dpaux";
106 power-domains = <&pd_sor>;
107 status = "disabled";
108
109 state_dpaux1_aux: pinmux-aux {
110 groups = "dpaux-io";
111 function = "aux";
112 };
113
114 state_dpaux1_i2c: pinmux-i2c {
115 groups = "dpaux-io";
116 function = "i2c";
117 };
118
119 state_dpaux1_off: pinmux-off {
120 groups = "dpaux-io";
121 function = "off";
122 };
123
124 i2c-bus {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 };
128 };
129
130 vi@54080000 {
131 compatible = "nvidia,tegra210-vi";
132 reg = <0x0 0x54080000 0x0 0x00040000>;
133 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
134 status = "disabled";
135 };
136
137 tsec@54100000 {
138 compatible = "nvidia,tegra210-tsec";
139 reg = <0x0 0x54100000 0x0 0x00040000>;
140 };
141
142 dc@54200000 {
143 compatible = "nvidia,tegra210-dc";
144 reg = <0x0 0x54200000 0x0 0x00040000>;
145 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&tegra_car TEGRA210_CLK_DISP1>,
147 <&tegra_car TEGRA210_CLK_PLL_P>;
148 clock-names = "dc", "parent";
149 resets = <&tegra_car 27>;
150 reset-names = "dc";
151
152 iommus = <&mc TEGRA_SWGROUP_DC>;
153
154 nvidia,head = <0>;
155 };
156
157 dc@54240000 {
158 compatible = "nvidia,tegra210-dc";
159 reg = <0x0 0x54240000 0x0 0x00040000>;
160 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&tegra_car TEGRA210_CLK_DISP2>,
162 <&tegra_car TEGRA210_CLK_PLL_P>;
163 clock-names = "dc", "parent";
164 resets = <&tegra_car 26>;
165 reset-names = "dc";
166
167 iommus = <&mc TEGRA_SWGROUP_DCB>;
168
169 nvidia,head = <1>;
170 };
171
172 dsi@54300000 {
173 compatible = "nvidia,tegra210-dsi";
174 reg = <0x0 0x54300000 0x0 0x00040000>;
175 clocks = <&tegra_car TEGRA210_CLK_DSIA>,
176 <&tegra_car TEGRA210_CLK_DSIALP>,
177 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
178 clock-names = "dsi", "lp", "parent";
179 resets = <&tegra_car 48>;
180 reset-names = "dsi";
181 power-domains = <&pd_sor>;
182 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */
183
184 status = "disabled";
185
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
189
190 vic@54340000 {
191 compatible = "nvidia,tegra210-vic";
192 reg = <0x0 0x54340000 0x0 0x00040000>;
193 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
195 clock-names = "vic";
196 resets = <&tegra_car 178>;
197 reset-names = "vic";
198
199 iommus = <&mc TEGRA_SWGROUP_VIC>;
200 power-domains = <&pd_vic>;
201 };
202
203 nvjpg@54380000 {
204 compatible = "nvidia,tegra210-nvjpg";
205 reg = <0x0 0x54380000 0x0 0x00040000>;
206 status = "disabled";
207 };
208
209 dsi@54400000 {
210 compatible = "nvidia,tegra210-dsi";
211 reg = <0x0 0x54400000 0x0 0x00040000>;
212 clocks = <&tegra_car TEGRA210_CLK_DSIB>,
213 <&tegra_car TEGRA210_CLK_DSIBLP>,
214 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>;
215 clock-names = "dsi", "lp", "parent";
216 resets = <&tegra_car 82>;
217 reset-names = "dsi";
218 power-domains = <&pd_sor>;
219 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */
220
221 status = "disabled";
222
223 #address-cells = <1>;
224 #size-cells = <0>;
225 };
226
227 nvdec@54480000 {
228 compatible = "nvidia,tegra210-nvdec";
229 reg = <0x0 0x54480000 0x0 0x00040000>;
230 status = "disabled";
231 };
232
233 nvenc@544c0000 {
234 compatible = "nvidia,tegra210-nvenc";
235 reg = <0x0 0x544c0000 0x0 0x00040000>;
236 status = "disabled";
237 };
238
239 tsec@54500000 {
240 compatible = "nvidia,tegra210-tsec";
241 reg = <0x0 0x54500000 0x0 0x00040000>;
242 status = "disabled";
243 };
244
245 sor@54540000 {
246 compatible = "nvidia,tegra210-sor";
247 reg = <0x0 0x54540000 0x0 0x00040000>;
248 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
250 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>,
251 <&tegra_car TEGRA210_CLK_PLL_DP>,
252 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
253 clock-names = "sor", "parent", "dp", "safe";
254 resets = <&tegra_car 182>;
255 reset-names = "sor";
256 pinctrl-0 = <&state_dpaux_aux>;
257 pinctrl-1 = <&state_dpaux_i2c>;
258 pinctrl-2 = <&state_dpaux_off>;
259 pinctrl-names = "aux", "i2c", "off";
260 power-domains = <&pd_sor>;
261 status = "disabled";
262 };
263
264 sor@54580000 {
265 compatible = "nvidia,tegra210-sor1";
266 reg = <0x0 0x54580000 0x0 0x00040000>;
267 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
268 clocks = <&tegra_car TEGRA210_CLK_SOR1>,
269 <&tegra_car TEGRA210_CLK_SOR1_OUT>,
270 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>,
271 <&tegra_car TEGRA210_CLK_PLL_DP>,
272 <&tegra_car TEGRA210_CLK_SOR_SAFE>;
273 clock-names = "sor", "out", "parent", "dp", "safe";
274 resets = <&tegra_car 183>;
275 reset-names = "sor";
276 pinctrl-0 = <&state_dpaux1_aux>;
277 pinctrl-1 = <&state_dpaux1_i2c>;
278 pinctrl-2 = <&state_dpaux1_off>;
279 pinctrl-names = "aux", "i2c", "off";
280 power-domains = <&pd_sor>;
281 status = "disabled";
282 };
283
284 dpaux: dpaux@545c0000 {
285 compatible = "nvidia,tegra124-dpaux";
286 reg = <0x0 0x545c0000 0x0 0x00040000>;
287 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&tegra_car TEGRA210_CLK_DPAUX>,
289 <&tegra_car TEGRA210_CLK_PLL_DP>;
290 clock-names = "dpaux", "parent";
291 resets = <&tegra_car 181>;
292 reset-names = "dpaux";
293 power-domains = <&pd_sor>;
294 status = "disabled";
295
296 state_dpaux_aux: pinmux-aux {
297 groups = "dpaux-io";
298 function = "aux";
299 };
300
301 state_dpaux_i2c: pinmux-i2c {
302 groups = "dpaux-io";
303 function = "i2c";
304 };
305
306 state_dpaux_off: pinmux-off {
307 groups = "dpaux-io";
308 function = "off";
309 };
310
311 i2c-bus {
312 #address-cells = <1>;
313 #size-cells = <0>;
314 };
315 };
316
317 isp@54600000 {
318 compatible = "nvidia,tegra210-isp";
319 reg = <0x0 0x54600000 0x0 0x00040000>;
320 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
321 status = "disabled";
322 };
323
324 isp@54680000 {
325 compatible = "nvidia,tegra210-isp";
326 reg = <0x0 0x54680000 0x0 0x00040000>;
327 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
328 status = "disabled";
329 };
330
331 i2c@546c0000 {
332 compatible = "nvidia,tegra210-i2c-vi";
333 reg = <0x0 0x546c0000 0x0 0x00040000>;
334 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
335 status = "disabled";
336 };
337 };
338
339 gic: interrupt-controller@50041000 {
340 compatible = "arm,gic-400";
341 #interrupt-cells = <3>;
342 interrupt-controller;
343 reg = <0x0 0x50041000 0x0 0x1000>,
344 <0x0 0x50042000 0x0 0x2000>,
345 <0x0 0x50044000 0x0 0x2000>,
346 <0x0 0x50046000 0x0 0x2000>;
347 interrupts = <GIC_PPI 9
348 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
349 interrupt-parent = <&gic>;
350 };
351
352 gpu@57000000 {
353 compatible = "nvidia,gm20b";
354 reg = <0x0 0x57000000 0x0 0x01000000>,
355 <0x0 0x58000000 0x0 0x01000000>;
356 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
358 interrupt-names = "stall", "nonstall";
359 clocks = <&tegra_car TEGRA210_CLK_GPU>,
360 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
361 <&tegra_car TEGRA210_CLK_PLL_G_REF>;
362 clock-names = "gpu", "pwr", "ref";
363 resets = <&tegra_car 184>;
364 reset-names = "gpu";
365
366 iommus = <&mc TEGRA_SWGROUP_GPU>;
367
368 status = "disabled";
369 };
370
371 lic: interrupt-controller@60004000 {
372 compatible = "nvidia,tegra210-ictlr";
373 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */
374 <0x0 0x60004100 0x0 0x40>, /* secondary controller */
375 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */
376 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */
377 <0x0 0x60004400 0x0 0x40>, /* quinary controller */
378 <0x0 0x60004500 0x0 0x40>; /* senary controller */
379 interrupt-controller;
380 #interrupt-cells = <3>;
381 interrupt-parent = <&gic>;
382 };
383
384 timer@60005000 {
385 compatible = "nvidia,tegra210-timer", "nvidia,tegra20-timer";
386 reg = <0x0 0x60005000 0x0 0x400>;
387 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
390 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
391 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
392 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&tegra_car TEGRA210_CLK_TIMER>;
394 clock-names = "timer";
395 };
396
397 tegra_car: clock@60006000 {
398 compatible = "nvidia,tegra210-car";
399 reg = <0x0 0x60006000 0x0 0x1000>;
400 #clock-cells = <1>;
401 #reset-cells = <1>;
402 };
403
404 flow-controller@60007000 {
405 compatible = "nvidia,tegra210-flowctrl";
406 reg = <0x0 0x60007000 0x0 0x1000>;
407 };
408
409 gpio: gpio@6000d000 {
410 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
411 reg = <0x0 0x6000d000 0x0 0x1000>;
412 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
413 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
414 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
420 #gpio-cells = <2>;
421 gpio-controller;
422 #interrupt-cells = <2>;
423 interrupt-controller;
424 };
425
426 apbdma: dma@60020000 {
427 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma";
428 reg = <0x0 0x60020000 0x0 0x1400>;
429 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
432 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
433 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
434 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
435 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
447 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
448 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
449 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
453 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
461 clocks = <&tegra_car TEGRA210_CLK_APBDMA>;
462 clock-names = "dma";
463 resets = <&tegra_car 34>;
464 reset-names = "dma";
465 #dma-cells = <1>;
466 };
467
468 apbmisc@70000800 {
469 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc";
470 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */
471 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */
472 };
473
474 pinmux: pinmux@700008d4 {
475 compatible = "nvidia,tegra210-pinmux";
476 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
477 <0x0 0x70003000 0x0 0x294>; /* Mux registers */
478 };
479
480 /*
481 * There are two serial driver i.e. 8250 based simple serial
482 * driver and APB DMA based serial driver for higher baudrate
483 * and performance. To enable the 8250 based driver, the compatible
484 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable
485 * the APB DMA based serial driver, the compatible is
486 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart".
487 */
488 uarta: serial@70006000 {
489 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
490 reg = <0x0 0x70006000 0x0 0x40>;
491 reg-shift = <2>;
492 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
493 clocks = <&tegra_car TEGRA210_CLK_UARTA>;
494 clock-names = "serial";
495 resets = <&tegra_car 6>;
496 reset-names = "serial";
497 dmas = <&apbdma 8>, <&apbdma 8>;
498 dma-names = "rx", "tx";
499 status = "disabled";
500 };
501
502 uartb: serial@70006040 {
503 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
504 reg = <0x0 0x70006040 0x0 0x40>;
505 reg-shift = <2>;
506 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&tegra_car TEGRA210_CLK_UARTB>;
508 clock-names = "serial";
509 resets = <&tegra_car 7>;
510 reset-names = "serial";
511 dmas = <&apbdma 9>, <&apbdma 9>;
512 dma-names = "rx", "tx";
513 status = "disabled";
514 };
515
516 uartc: serial@70006200 {
517 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
518 reg = <0x0 0x70006200 0x0 0x40>;
519 reg-shift = <2>;
520 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&tegra_car TEGRA210_CLK_UARTC>;
522 clock-names = "serial";
523 resets = <&tegra_car 55>;
524 reset-names = "serial";
525 dmas = <&apbdma 10>, <&apbdma 10>;
526 dma-names = "rx", "tx";
527 status = "disabled";
528 };
529
530 uartd: serial@70006300 {
531 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
532 reg = <0x0 0x70006300 0x0 0x40>;
533 reg-shift = <2>;
534 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&tegra_car TEGRA210_CLK_UARTD>;
536 clock-names = "serial";
537 resets = <&tegra_car 65>;
538 reset-names = "serial";
539 dmas = <&apbdma 19>, <&apbdma 19>;
540 dma-names = "rx", "tx";
541 status = "disabled";
542 };
543
544 pwm: pwm@7000a000 {
545 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm";
546 reg = <0x0 0x7000a000 0x0 0x100>;
547 #pwm-cells = <2>;
548 clocks = <&tegra_car TEGRA210_CLK_PWM>;
549 clock-names = "pwm";
550 resets = <&tegra_car 17>;
551 reset-names = "pwm";
552 status = "disabled";
553 };
554
555 i2c@7000c000 {
556 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
557 reg = <0x0 0x7000c000 0x0 0x100>;
558 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
559 #address-cells = <1>;
560 #size-cells = <0>;
561 clocks = <&tegra_car TEGRA210_CLK_I2C1>;
562 clock-names = "div-clk";
563 resets = <&tegra_car 12>;
564 reset-names = "i2c";
565 dmas = <&apbdma 21>, <&apbdma 21>;
566 dma-names = "rx", "tx";
567 status = "disabled";
568 };
569
570 i2c@7000c400 {
571 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
572 reg = <0x0 0x7000c400 0x0 0x100>;
573 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 clocks = <&tegra_car TEGRA210_CLK_I2C2>;
577 clock-names = "div-clk";
578 resets = <&tegra_car 54>;
579 reset-names = "i2c";
580 dmas = <&apbdma 22>, <&apbdma 22>;
581 dma-names = "rx", "tx";
582 status = "disabled";
583 };
584
585 i2c@7000c500 {
586 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
587 reg = <0x0 0x7000c500 0x0 0x100>;
588 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
589 #address-cells = <1>;
590 #size-cells = <0>;
591 clocks = <&tegra_car TEGRA210_CLK_I2C3>;
592 clock-names = "div-clk";
593 resets = <&tegra_car 67>;
594 reset-names = "i2c";
595 dmas = <&apbdma 23>, <&apbdma 23>;
596 dma-names = "rx", "tx";
597 status = "disabled";
598 };
599
600 i2c@7000c700 {
601 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
602 reg = <0x0 0x7000c700 0x0 0x100>;
603 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
604 #address-cells = <1>;
605 #size-cells = <0>;
606 clocks = <&tegra_car TEGRA210_CLK_I2C4>;
607 clock-names = "div-clk";
608 resets = <&tegra_car 103>;
609 reset-names = "i2c";
610 dmas = <&apbdma 26>, <&apbdma 26>;
611 dma-names = "rx", "tx";
612 pinctrl-0 = <&state_dpaux1_i2c>;
613 pinctrl-1 = <&state_dpaux1_off>;
614 pinctrl-names = "default", "idle";
615 status = "disabled";
616 };
617
618 i2c@7000d000 {
619 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
620 reg = <0x0 0x7000d000 0x0 0x100>;
621 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
622 #address-cells = <1>;
623 #size-cells = <0>;
624 clocks = <&tegra_car TEGRA210_CLK_I2C5>;
625 clock-names = "div-clk";
626 resets = <&tegra_car 47>;
627 reset-names = "i2c";
628 dmas = <&apbdma 24>, <&apbdma 24>;
629 dma-names = "rx", "tx";
630 status = "disabled";
631 };
632
633 i2c@7000d100 {
634 compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
635 reg = <0x0 0x7000d100 0x0 0x100>;
636 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
637 #address-cells = <1>;
638 #size-cells = <0>;
639 clocks = <&tegra_car TEGRA210_CLK_I2C6>;
640 clock-names = "div-clk";
641 resets = <&tegra_car 166>;
642 reset-names = "i2c";
643 dmas = <&apbdma 30>, <&apbdma 30>;
644 dma-names = "rx", "tx";
645 pinctrl-0 = <&state_dpaux_i2c>;
646 pinctrl-1 = <&state_dpaux_off>;
647 pinctrl-names = "default", "idle";
648 status = "disabled";
649 };
650
651 spi@7000d400 {
652 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
653 reg = <0x0 0x7000d400 0x0 0x200>;
654 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
655 #address-cells = <1>;
656 #size-cells = <0>;
657 clocks = <&tegra_car TEGRA210_CLK_SBC1>;
658 clock-names = "spi";
659 resets = <&tegra_car 41>;
660 reset-names = "spi";
661 dmas = <&apbdma 15>, <&apbdma 15>;
662 dma-names = "rx", "tx";
663 status = "disabled";
664 };
665
666 spi@7000d600 {
667 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
668 reg = <0x0 0x7000d600 0x0 0x200>;
669 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
670 #address-cells = <1>;
671 #size-cells = <0>;
672 clocks = <&tegra_car TEGRA210_CLK_SBC2>;
673 clock-names = "spi";
674 resets = <&tegra_car 44>;
675 reset-names = "spi";
676 dmas = <&apbdma 16>, <&apbdma 16>;
677 dma-names = "rx", "tx";
678 status = "disabled";
679 };
680
681 spi@7000d800 {
682 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
683 reg = <0x0 0x7000d800 0x0 0x200>;
684 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clocks = <&tegra_car TEGRA210_CLK_SBC3>;
688 clock-names = "spi";
689 resets = <&tegra_car 46>;
690 reset-names = "spi";
691 dmas = <&apbdma 17>, <&apbdma 17>;
692 dma-names = "rx", "tx";
693 status = "disabled";
694 };
695
696 spi@7000da00 {
697 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
698 reg = <0x0 0x7000da00 0x0 0x200>;
699 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
700 #address-cells = <1>;
701 #size-cells = <0>;
702 clocks = <&tegra_car TEGRA210_CLK_SBC4>;
703 clock-names = "spi";
704 resets = <&tegra_car 68>;
705 reset-names = "spi";
706 dmas = <&apbdma 18>, <&apbdma 18>;
707 dma-names = "rx", "tx";
708 status = "disabled";
709 };
710
711 rtc@7000e000 {
712 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc";
713 reg = <0x0 0x7000e000 0x0 0x100>;
714 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&tegra_car TEGRA210_CLK_RTC>;
716 clock-names = "rtc";
717 };
718
719 pmc: pmc@7000e400 {
720 compatible = "nvidia,tegra210-pmc";
721 reg = <0x0 0x7000e400 0x0 0x400>;
722 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
723 clock-names = "pclk", "clk32k_in";
724
725 powergates {
726 pd_audio: aud {
727 clocks = <&tegra_car TEGRA210_CLK_APE>,
728 <&tegra_car TEGRA210_CLK_APB2APE>;
729 resets = <&tegra_car 198>;
730 #power-domain-cells = <0>;
731 };
732
733 pd_sor: sor {
734 clocks = <&tegra_car TEGRA210_CLK_SOR0>,
735 <&tegra_car TEGRA210_CLK_SOR1>,
736 <&tegra_car TEGRA210_CLK_CSI>,
737 <&tegra_car TEGRA210_CLK_DSIA>,
738 <&tegra_car TEGRA210_CLK_DSIB>,
739 <&tegra_car TEGRA210_CLK_DPAUX>,
740 <&tegra_car TEGRA210_CLK_DPAUX1>,
741 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
742 resets = <&tegra_car TEGRA210_CLK_SOR0>,
743 <&tegra_car TEGRA210_CLK_SOR1>,
744 <&tegra_car TEGRA210_CLK_CSI>,
745 <&tegra_car TEGRA210_CLK_DSIA>,
746 <&tegra_car TEGRA210_CLK_DSIB>,
747 <&tegra_car TEGRA210_CLK_DPAUX>,
748 <&tegra_car TEGRA210_CLK_DPAUX1>,
749 <&tegra_car TEGRA210_CLK_MIPI_CAL>;
750 #power-domain-cells = <0>;
751 };
752
753 pd_xusbss: xusba {
754 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
755 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
756 #power-domain-cells = <0>;
757 };
758
759 pd_xusbdev: xusbb {
760 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>;
761 resets = <&tegra_car 95>;
762 #power-domain-cells = <0>;
763 };
764
765 pd_xusbhost: xusbc {
766 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
767 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>;
768 #power-domain-cells = <0>;
769 };
770
771 pd_vic: vic {
772 clocks = <&tegra_car TEGRA210_CLK_VIC03>;
773 clock-names = "vic";
774 resets = <&tegra_car 178>;
775 reset-names = "vic";
776 #power-domain-cells = <0>;
777 };
778 };
779 };
780
781 fuse@7000f800 {
782 compatible = "nvidia,tegra210-efuse";
783 reg = <0x0 0x7000f800 0x0 0x400>;
784 clocks = <&tegra_car TEGRA210_CLK_FUSE>;
785 clock-names = "fuse";
786 resets = <&tegra_car 39>;
787 reset-names = "fuse";
788 };
789
790 mc: memory-controller@70019000 {
791 compatible = "nvidia,tegra210-mc";
792 reg = <0x0 0x70019000 0x0 0x1000>;
793 clocks = <&tegra_car TEGRA210_CLK_MC>;
794 clock-names = "mc";
795
796 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
797
798 #iommu-cells = <1>;
799 };
800
801 sata@70020000 {
802 compatible = "nvidia,tegra210-ahci";
803 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */
804 <0x0 0x70020000 0x0 0x7000>, /* SATA */
805 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */
806 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&tegra_car TEGRA210_CLK_SATA>,
808 <&tegra_car TEGRA210_CLK_SATA_OOB>;
809 clock-names = "sata", "sata-oob";
810 resets = <&tegra_car 124>,
811 <&tegra_car 123>,
812 <&tegra_car 129>;
813 reset-names = "sata", "sata-oob", "sata-cold";
814 status = "disabled";
815 };
816
817 hda@70030000 {
818 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda";
819 reg = <0x0 0x70030000 0x0 0x10000>;
820 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
821 clocks = <&tegra_car TEGRA210_CLK_HDA>,
822 <&tegra_car TEGRA210_CLK_HDA2HDMI>,
823 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>;
824 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
825 resets = <&tegra_car 125>, /* hda */
826 <&tegra_car 128>, /* hda2hdmi */
827 <&tegra_car 111>; /* hda2codec_2x */
828 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
829 status = "disabled";
830 };
831
832 usb@70090000 {
833 compatible = "nvidia,tegra210-xusb";
834 reg = <0x0 0x70090000 0x0 0x8000>,
835 <0x0 0x70098000 0x0 0x1000>,
836 <0x0 0x70099000 0x0 0x1000>;
837 reg-names = "hcd", "fpci", "ipfs";
838
839 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
841
842 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>,
843 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>,
844 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>,
845 <&tegra_car TEGRA210_CLK_XUSB_SS>,
846 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>,
847 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>,
848 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>,
849 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>,
850 <&tegra_car TEGRA210_CLK_PLL_U_480M>,
851 <&tegra_car TEGRA210_CLK_CLK_M>,
852 <&tegra_car TEGRA210_CLK_PLL_E>;
853 clock-names = "xusb_host", "xusb_host_src",
854 "xusb_falcon_src", "xusb_ss",
855 "xusb_ss_div2", "xusb_ss_src",
856 "xusb_hs_src", "xusb_fs_src",
857 "pll_u_480m", "clk_m", "pll_e";
858 resets = <&tegra_car 89>, <&tegra_car 156>,
859 <&tegra_car 143>;
860 reset-names = "xusb_host", "xusb_ss", "xusb_src";
861
862 nvidia,xusb-padctl = <&padctl>;
863
864 status = "disabled";
865 };
866
867 padctl: padctl@7009f000 {
868 compatible = "nvidia,tegra210-xusb-padctl";
869 reg = <0x0 0x7009f000 0x0 0x1000>;
870 resets = <&tegra_car 142>;
871 reset-names = "padctl";
872
873 status = "disabled";
874
875 pads {
876 usb2 {
877 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>;
878 clock-names = "trk";
879 status = "disabled";
880
881 lanes {
882 usb2-0 {
883 status = "disabled";
884 #phy-cells = <0>;
885 };
886
887 usb2-1 {
888 status = "disabled";
889 #phy-cells = <0>;
890 };
891
892 usb2-2 {
893 status = "disabled";
894 #phy-cells = <0>;
895 };
896
897 usb2-3 {
898 status = "disabled";
899 #phy-cells = <0>;
900 };
901 };
902 };
903
904 hsic {
905 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>;
906 clock-names = "trk";
907 status = "disabled";
908
909 lanes {
910 hsic-0 {
911 status = "disabled";
912 #phy-cells = <0>;
913 };
914
915 hsic-1 {
916 status = "disabled";
917 #phy-cells = <0>;
918 };
919 };
920 };
921
922 pcie {
923 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
924 clock-names = "pll";
925 resets = <&tegra_car 205>;
926 reset-names = "phy";
927 status = "disabled";
928
929 lanes {
930 pcie-0 {
931 status = "disabled";
932 #phy-cells = <0>;
933 };
934
935 pcie-1 {
936 status = "disabled";
937 #phy-cells = <0>;
938 };
939
940 pcie-2 {
941 status = "disabled";
942 #phy-cells = <0>;
943 };
944
945 pcie-3 {
946 status = "disabled";
947 #phy-cells = <0>;
948 };
949
950 pcie-4 {
951 status = "disabled";
952 #phy-cells = <0>;
953 };
954
955 pcie-5 {
956 status = "disabled";
957 #phy-cells = <0>;
958 };
959
960 pcie-6 {
961 status = "disabled";
962 #phy-cells = <0>;
963 };
964 };
965 };
966
967 sata {
968 clocks = <&tegra_car TEGRA210_CLK_PLL_E>;
969 clock-names = "pll";
970 resets = <&tegra_car 204>;
971 reset-names = "phy";
972 status = "disabled";
973
974 lanes {
975 sata-0 {
976 status = "disabled";
977 #phy-cells = <0>;
978 };
979 };
980 };
981 };
982
983 ports {
984 usb2-0 {
985 status = "disabled";
986 };
987
988 usb2-1 {
989 status = "disabled";
990 };
991
992 usb2-2 {
993 status = "disabled";
994 };
995
996 usb2-3 {
997 status = "disabled";
998 };
999
1000 hsic-0 {
1001 status = "disabled";
1002 };
1003
1004 usb3-0 {
1005 status = "disabled";
1006 };
1007
1008 usb3-1 {
1009 status = "disabled";
1010 };
1011
1012 usb3-2 {
1013 status = "disabled";
1014 };
1015
1016 usb3-3 {
1017 status = "disabled";
1018 };
1019 };
1020 };
1021
1022 sdhci@700b0000 {
1023 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1024 reg = <0x0 0x700b0000 0x0 0x200>;
1025 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
1027 clock-names = "sdhci";
1028 resets = <&tegra_car 14>;
1029 reset-names = "sdhci";
1030 status = "disabled";
1031 };
1032
1033 sdhci@700b0200 {
1034 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1035 reg = <0x0 0x700b0200 0x0 0x200>;
1036 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
1038 clock-names = "sdhci";
1039 resets = <&tegra_car 9>;
1040 reset-names = "sdhci";
1041 status = "disabled";
1042 };
1043
1044 sdhci@700b0400 {
1045 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1046 reg = <0x0 0x700b0400 0x0 0x200>;
1047 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
1049 clock-names = "sdhci";
1050 resets = <&tegra_car 69>;
1051 reset-names = "sdhci";
1052 status = "disabled";
1053 };
1054
1055 sdhci@700b0600 {
1056 compatible = "nvidia,tegra210-sdhci", "nvidia,tegra124-sdhci";
1057 reg = <0x0 0x700b0600 0x0 0x200>;
1058 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1059 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
1060 clock-names = "sdhci";
1061 resets = <&tegra_car 15>;
1062 reset-names = "sdhci";
1063 status = "disabled";
1064 };
1065
1066 mipi: mipi@700e3000 {
1067 compatible = "nvidia,tegra210-mipi";
1068 reg = <0x0 0x700e3000 0x0 0x100>;
1069 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>;
1070 clock-names = "mipi-cal";
1071 power-domains = <&pd_sor>;
1072 #nvidia,mipi-calibrate-cells = <1>;
1073 };
1074
1075 aconnect@702c0000 {
1076 compatible = "nvidia,tegra210-aconnect";
1077 clocks = <&tegra_car TEGRA210_CLK_APE>,
1078 <&tegra_car TEGRA210_CLK_APB2APE>;
1079 clock-names = "ape", "apb2ape";
1080 power-domains = <&pd_audio>;
1081 #address-cells = <1>;
1082 #size-cells = <1>;
1083 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>;
1084 status = "disabled";
1085
1086 adma: dma@702e2000 {
1087 compatible = "nvidia,tegra210-adma";
1088 reg = <0x702e2000 0x2000>;
1089 interrupt-parent = <&agic>;
1090 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1092 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
1093 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
1094 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
1103 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
1105 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
1106 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
1107 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
1110 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1111 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1112 #dma-cells = <1>;
1113 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
1114 clock-names = "d_audio";
1115 status = "disabled";
1116 };
1117
1118 agic: agic@702f9000 {
1119 compatible = "nvidia,tegra210-agic";
1120 #interrupt-cells = <3>;
1121 interrupt-controller;
1122 reg = <0x702f9000 0x2000>,
1123 <0x702fa000 0x2000>;
1124 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1125 clocks = <&tegra_car TEGRA210_CLK_APE>;
1126 clock-names = "clk";
1127 status = "disabled";
1128 };
1129 };
1130
1131 spi@70410000 {
1132 compatible = "nvidia,tegra210-qspi";
1133 reg = <0x0 0x70410000 0x0 0x1000>;
1134 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1135 #address-cells = <1>;
1136 #size-cells = <0>;
1137 clocks = <&tegra_car TEGRA210_CLK_QSPI>;
1138 clock-names = "qspi";
1139 resets = <&tegra_car 211>;
1140 reset-names = "qspi";
1141 dmas = <&apbdma 5>, <&apbdma 5>;
1142 dma-names = "rx", "tx";
1143 status = "disabled";
1144 };
1145
1146 usb@7d000000 {
1147 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1148 reg = <0x0 0x7d000000 0x0 0x4000>;
1149 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1150 phy_type = "utmi";
1151 clocks = <&tegra_car TEGRA210_CLK_USBD>;
1152 clock-names = "usb";
1153 resets = <&tegra_car 22>;
1154 reset-names = "usb";
1155 nvidia,phy = <&phy1>;
1156 status = "disabled";
1157 };
1158
1159 phy1: usb-phy@7d000000 {
1160 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1161 reg = <0x0 0x7d000000 0x0 0x4000>,
1162 <0x0 0x7d000000 0x0 0x4000>;
1163 phy_type = "utmi";
1164 clocks = <&tegra_car TEGRA210_CLK_USBD>,
1165 <&tegra_car TEGRA210_CLK_PLL_U>,
1166 <&tegra_car TEGRA210_CLK_USBD>;
1167 clock-names = "reg", "pll_u", "utmi-pads";
1168 resets = <&tegra_car 22>, <&tegra_car 22>;
1169 reset-names = "usb", "utmi-pads";
1170 nvidia,hssync-start-delay = <0>;
1171 nvidia,idle-wait-delay = <17>;
1172 nvidia,elastic-limit = <16>;
1173 nvidia,term-range-adj = <6>;
1174 nvidia,xcvr-setup = <9>;
1175 nvidia,xcvr-lsfslew = <0>;
1176 nvidia,xcvr-lsrslew = <3>;
1177 nvidia,hssquelch-level = <2>;
1178 nvidia,hsdiscon-level = <5>;
1179 nvidia,xcvr-hsslew = <12>;
1180 nvidia,has-utmi-pad-registers;
1181 status = "disabled";
1182 };
1183
1184 usb@7d004000 {
1185 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci";
1186 reg = <0x0 0x7d004000 0x0 0x4000>;
1187 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
1188 phy_type = "utmi";
1189 clocks = <&tegra_car TEGRA210_CLK_USB2>;
1190 clock-names = "usb";
1191 resets = <&tegra_car 58>;
1192 reset-names = "usb";
1193 nvidia,phy = <&phy2>;
1194 status = "disabled";
1195 };
1196
1197 phy2: usb-phy@7d004000 {
1198 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy";
1199 reg = <0x0 0x7d004000 0x0 0x4000>,
1200 <0x0 0x7d000000 0x0 0x4000>;
1201 phy_type = "utmi";
1202 clocks = <&tegra_car TEGRA210_CLK_USB2>,
1203 <&tegra_car TEGRA210_CLK_PLL_U>,
1204 <&tegra_car TEGRA210_CLK_USBD>;
1205 clock-names = "reg", "pll_u", "utmi-pads";
1206 resets = <&tegra_car 58>, <&tegra_car 22>;
1207 reset-names = "usb", "utmi-pads";
1208 nvidia,hssync-start-delay = <0>;
1209 nvidia,idle-wait-delay = <17>;
1210 nvidia,elastic-limit = <16>;
1211 nvidia,term-range-adj = <6>;
1212 nvidia,xcvr-setup = <9>;
1213 nvidia,xcvr-lsfslew = <0>;
1214 nvidia,xcvr-lsrslew = <3>;
1215 nvidia,hssquelch-level = <2>;
1216 nvidia,hsdiscon-level = <5>;
1217 nvidia,xcvr-hsslew = <12>;
1218 status = "disabled";
1219 };
1220
1221 cpus {
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1224
1225 cpu@0 {
1226 device_type = "cpu";
1227 compatible = "arm,cortex-a57";
1228 reg = <0>;
1229 };
1230
1231 cpu@1 {
1232 device_type = "cpu";
1233 compatible = "arm,cortex-a57";
1234 reg = <1>;
1235 };
1236
1237 cpu@2 {
1238 device_type = "cpu";
1239 compatible = "arm,cortex-a57";
1240 reg = <2>;
1241 };
1242
1243 cpu@3 {
1244 device_type = "cpu";
1245 compatible = "arm,cortex-a57";
1246 reg = <3>;
1247 };
1248 };
1249
1250 timer {
1251 compatible = "arm,armv8-timer";
1252 interrupts = <GIC_PPI 13
1253 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1254 <GIC_PPI 14
1255 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1256 <GIC_PPI 11
1257 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
1258 <GIC_PPI 10
1259 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
1260 interrupt-parent = <&gic>;
1261 };
1262
1263 soctherm: thermal-sensor@700e2000 {
1264 compatible = "nvidia,tegra210-soctherm";
1265 reg = <0x0 0x700e2000 0x0 0x600 /* SOC_THERM reg_base */
1266 0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
1267 reg-names = "soctherm-reg", "car-reg";
1268 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1269 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>,
1270 <&tegra_car TEGRA210_CLK_SOC_THERM>;
1271 clock-names = "tsensor", "soctherm";
1272 resets = <&tegra_car 78>;
1273 reset-names = "soctherm";
1274 #thermal-sensor-cells = <1>;
1275
1276 throttle-cfgs {
1277 throttle_heavy: heavy {
1278 nvidia,priority = <100>;
1279 nvidia,cpu-throt-percent = <85>;
1280
1281 #cooling-cells = <2>;
1282 };
1283 };
1284 };
1285
1286 thermal-zones {
1287 cpu {
1288 polling-delay-passive = <1000>;
1289 polling-delay = <0>;
1290
1291 thermal-sensors =
1292 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>;
1293
1294 trips {
1295 cpu-shutdown-trip {
1296 temperature = <102500>;
1297 hysteresis = <0>;
1298 type = "critical";
1299 };
1300
1301 cpu_throttle_trip: throttle-trip {
1302 temperature = <98500>;
1303 hysteresis = <1000>;
1304 type = "hot";
1305 };
1306 };
1307
1308 cooling-maps {
1309 map0 {
1310 trip = <&cpu_throttle_trip>;
1311 cooling-device = <&throttle_heavy 1 1>;
1312 };
1313 };
1314 };
1315 mem {
1316 polling-delay-passive = <0>;
1317 polling-delay = <0>;
1318
1319 thermal-sensors =
1320 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>;
1321
1322 trips {
1323 mem-shutdown-trip {
1324 temperature = <103000>;
1325 hysteresis = <0>;
1326 type = "critical";
1327 };
1328 };
1329
1330 cooling-maps {
1331 /*
1332 * There are currently no cooling maps,
1333 * because there are no cooling devices.
1334 */
1335 };
1336 };
1337 gpu {
1338 polling-delay-passive = <1000>;
1339 polling-delay = <0>;
1340
1341 thermal-sensors =
1342 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>;
1343
1344 trips {
1345 gpu-shutdown-trip {
1346 temperature = <103000>;
1347 hysteresis = <0>;
1348 type = "critical";
1349 };
1350
1351 gpu_throttle_trip: throttle-trip {
1352 temperature = <100000>;
1353 hysteresis = <1000>;
1354 type = "hot";
1355 };
1356 };
1357
1358 cooling-maps {
1359 map0 {
1360 trip = <&gpu_throttle_trip>;
1361 cooling-device = <&throttle_heavy 1 1>;
1362 };
1363 };
1364 };
1365 pllx {
1366 polling-delay-passive = <0>;
1367 polling-delay = <0>;
1368
1369 thermal-sensors =
1370 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>;
1371
1372 trips {
1373 pllx-shutdown-trip {
1374 temperature = <103000>;
1375 hysteresis = <0>;
1376 type = "critical";
1377 };
1378 };
1379
1380 cooling-maps {
1381 /*
1382 * There are currently no cooling maps,
1383 * because there are no cooling devices.
1384 */
1385 };
1386 };
1387 };
1388};