1/*
   2 * Hardware modules present on the OMAP44xx chips
   3 *
   4 * Copyright (C) 2009-2012 Texas Instruments, Inc.
   5 * Copyright (C) 2009-2010 Nokia Corporation
   6 *
   7 * Paul Walmsley
   8 * Benoit Cousson
   9 *
  10 * This file is automatically generated from the OMAP hardware databases.
  11 * We respectfully ask that any modifications to this file be coordinated
  12 * with the public linux-omap@vger.kernel.org mailing list and the
  13 * authors above to ensure that the autogeneration scripts are kept
  14 * up-to-date with the file contents.
  15 * Note that this file is currently not in sync with autogeneration scripts.
  16 * The above note to be removed, once it is synced up.
  17 *
  18 * This program is free software; you can redistribute it and/or modify
  19 * it under the terms of the GNU General Public License version 2 as
  20 * published by the Free Software Foundation.
  21 */
  22
  23#include <linux/io.h>
  24#include <linux/platform_data/hsmmc-omap.h>
  25#include <linux/power/smartreflex.h>
  26#include <linux/i2c-omap.h>
  27
  28#include <linux/omap-dma.h>
  29
  30#include "omap_hwmod.h"
  31#include "omap_hwmod_common_data.h"
  32#include "cm1_44xx.h"
  33#include "cm2_44xx.h"
  34#include "prm44xx.h"
  35#include "prm-regbits-44xx.h"
  36#include "i2c.h"
  37#include "wd_timer.h"
  38
  39/* Base offset for all OMAP4 interrupts external to MPUSS */
  40#define OMAP44XX_IRQ_GIC_START	32
  41
  42/* Base offset for all OMAP4 dma requests */
  43#define OMAP44XX_DMA_REQ_START	1
  44
  45/*
  46 * IP blocks
  47 */
  48
  49/*
  50 * 'dmm' class
  51 * instance(s): dmm
  52 */
  53static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
  54	.name	= "dmm",
  55};
  56
  57/* dmm */
  58static struct omap_hwmod omap44xx_dmm_hwmod = {
  59	.name		= "dmm",
  60	.class		= &omap44xx_dmm_hwmod_class,
  61	.clkdm_name	= "l3_emif_clkdm",
  62	.prcm = {
  63		.omap4 = {
  64			.clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
  65			.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
  66		},
  67	},
  68};
  69
  70/*
  71 * 'l3' class
  72 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
  73 */
  74static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
  75	.name	= "l3",
  76};
  77
  78/* l3_instr */
  79static struct omap_hwmod omap44xx_l3_instr_hwmod = {
  80	.name		= "l3_instr",
  81	.class		= &omap44xx_l3_hwmod_class,
  82	.clkdm_name	= "l3_instr_clkdm",
  83	.prcm = {
  84		.omap4 = {
  85			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
  86			.context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
  87			.modulemode   = MODULEMODE_HWCTRL,
  88		},
  89	},
  90};
  91
  92/* l3_main_1 */
  93static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
  94	.name		= "l3_main_1",
  95	.class		= &omap44xx_l3_hwmod_class,
  96	.clkdm_name	= "l3_1_clkdm",
  97	.prcm = {
  98		.omap4 = {
  99			.clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
 100			.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
 101		},
 102	},
 103};
 104
 105/* l3_main_2 */
 106static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
 107	.name		= "l3_main_2",
 108	.class		= &omap44xx_l3_hwmod_class,
 109	.clkdm_name	= "l3_2_clkdm",
 110	.prcm = {
 111		.omap4 = {
 112			.clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
 113			.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
 114		},
 115	},
 116};
 117
 118/* l3_main_3 */
 119static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
 120	.name		= "l3_main_3",
 121	.class		= &omap44xx_l3_hwmod_class,
 122	.clkdm_name	= "l3_instr_clkdm",
 123	.prcm = {
 124		.omap4 = {
 125			.clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
 126			.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
 127			.modulemode   = MODULEMODE_HWCTRL,
 128		},
 129	},
 130};
 131
 132/*
 133 * 'l4' class
 134 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
 135 */
 136static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
 137	.name	= "l4",
 138};
 139
 140/* l4_abe */
 141static struct omap_hwmod omap44xx_l4_abe_hwmod = {
 142	.name		= "l4_abe",
 143	.class		= &omap44xx_l4_hwmod_class,
 144	.clkdm_name	= "abe_clkdm",
 145	.prcm = {
 146		.omap4 = {
 147			.clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
 148			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 149			.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
 150			.flags	      = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 151		},
 152	},
 153};
 154
 155/* l4_cfg */
 156static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
 157	.name		= "l4_cfg",
 158	.class		= &omap44xx_l4_hwmod_class,
 159	.clkdm_name	= "l4_cfg_clkdm",
 160	.prcm = {
 161		.omap4 = {
 162			.clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
 163			.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
 164		},
 165	},
 166};
 167
 168/* l4_per */
 169static struct omap_hwmod omap44xx_l4_per_hwmod = {
 170	.name		= "l4_per",
 171	.class		= &omap44xx_l4_hwmod_class,
 172	.clkdm_name	= "l4_per_clkdm",
 173	.prcm = {
 174		.omap4 = {
 175			.clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
 176			.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
 177		},
 178	},
 179};
 180
 181/* l4_wkup */
 182static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
 183	.name		= "l4_wkup",
 184	.class		= &omap44xx_l4_hwmod_class,
 185	.clkdm_name	= "l4_wkup_clkdm",
 186	.prcm = {
 187		.omap4 = {
 188			.clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
 189			.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
 190		},
 191	},
 192};
 193
 194/*
 195 * 'mpu_bus' class
 196 * instance(s): mpu_private
 197 */
 198static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
 199	.name	= "mpu_bus",
 200};
 201
 202/* mpu_private */
 203static struct omap_hwmod omap44xx_mpu_private_hwmod = {
 204	.name		= "mpu_private",
 205	.class		= &omap44xx_mpu_bus_hwmod_class,
 206	.clkdm_name	= "mpuss_clkdm",
 207	.prcm = {
 208		.omap4 = {
 209			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 210		},
 211	},
 212};
 213
 214/*
 215 * 'ocp_wp_noc' class
 216 * instance(s): ocp_wp_noc
 217 */
 218static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
 219	.name	= "ocp_wp_noc",
 220};
 221
 222/* ocp_wp_noc */
 223static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
 224	.name		= "ocp_wp_noc",
 225	.class		= &omap44xx_ocp_wp_noc_hwmod_class,
 226	.clkdm_name	= "l3_instr_clkdm",
 227	.prcm = {
 228		.omap4 = {
 229			.clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
 230			.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
 231			.modulemode   = MODULEMODE_HWCTRL,
 232		},
 233	},
 234};
 235
 236/*
 237 * Modules omap_hwmod structures
 238 *
 239 * The following IPs are excluded for the moment because:
 240 * - They do not need an explicit SW control using omap_hwmod API.
 241 * - They still need to be validated with the driver
 242 *   properly adapted to omap_hwmod / omap_device
 243 *
 244 * usim
 245 */
 246
 247/*
 248 * 'aess' class
 249 * audio engine sub system
 250 */
 251
 252static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
 253	.rev_offs	= 0x0000,
 254	.sysc_offs	= 0x0010,
 255	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
 256	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 257			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
 258			   MSTANDBY_SMART_WKUP),
 259	.sysc_fields	= &omap_hwmod_sysc_type2,
 260};
 261
 262static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
 263	.name	= "aess",
 264	.sysc	= &omap44xx_aess_sysc,
 265	.enable_preprogram = omap_hwmod_aess_preprogram,
 266};
 267
 268/* aess */
 269static struct omap_hwmod omap44xx_aess_hwmod = {
 270	.name		= "aess",
 271	.class		= &omap44xx_aess_hwmod_class,
 272	.clkdm_name	= "abe_clkdm",
 273	.main_clk	= "aess_fclk",
 274	.prcm = {
 275		.omap4 = {
 276			.clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
 277			.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
 278			.lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
 279			.modulemode   = MODULEMODE_SWCTRL,
 280		},
 281	},
 282};
 283
 284/*
 285 * 'c2c' class
 286 * chip 2 chip interface used to plug the ape soc (omap) with an external modem
 287 * soc
 288 */
 289
 290static struct omap_hwmod_class omap44xx_c2c_hwmod_class = {
 291	.name	= "c2c",
 292};
 293
 294/* c2c */
 295static struct omap_hwmod omap44xx_c2c_hwmod = {
 296	.name		= "c2c",
 297	.class		= &omap44xx_c2c_hwmod_class,
 298	.clkdm_name	= "d2d_clkdm",
 299	.prcm = {
 300		.omap4 = {
 301			.clkctrl_offs = OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET,
 302			.context_offs = OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET,
 303		},
 304	},
 305};
 306
 307/*
 308 * 'counter' class
 309 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
 310 */
 311
 312static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = {
 313	.rev_offs	= 0x0000,
 314	.sysc_offs	= 0x0004,
 315	.sysc_flags	= SYSC_HAS_SIDLEMODE,
 316	.idlemodes	= (SIDLE_FORCE | SIDLE_NO),
 317	.sysc_fields	= &omap_hwmod_sysc_type1,
 318};
 319
 320static struct omap_hwmod_class omap44xx_counter_hwmod_class = {
 321	.name	= "counter",
 322	.sysc	= &omap44xx_counter_sysc,
 323};
 324
 325/* counter_32k */
 326static struct omap_hwmod omap44xx_counter_32k_hwmod = {
 327	.name		= "counter_32k",
 328	.class		= &omap44xx_counter_hwmod_class,
 329	.clkdm_name	= "l4_wkup_clkdm",
 330	.flags		= HWMOD_SWSUP_SIDLE,
 331	.main_clk	= "sys_32k_ck",
 332	.prcm = {
 333		.omap4 = {
 334			.clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
 335			.context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
 336		},
 337	},
 338};
 339
 340/*
 341 * 'ctrl_module' class
 342 * attila core control module + core pad control module + wkup pad control
 343 * module + attila wkup control module
 344 */
 345
 346static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
 347	.rev_offs	= 0x0000,
 348	.sysc_offs	= 0x0010,
 349	.sysc_flags	= SYSC_HAS_SIDLEMODE,
 350	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 351			   SIDLE_SMART_WKUP),
 352	.sysc_fields	= &omap_hwmod_sysc_type2,
 353};
 354
 355static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
 356	.name	= "ctrl_module",
 357	.sysc	= &omap44xx_ctrl_module_sysc,
 358};
 359
 360/* ctrl_module_core */
 361static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
 362	.name		= "ctrl_module_core",
 363	.class		= &omap44xx_ctrl_module_hwmod_class,
 364	.clkdm_name	= "l4_cfg_clkdm",
 365	.prcm = {
 366		.omap4 = {
 367			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 368		},
 369	},
 370};
 371
 372/* ctrl_module_pad_core */
 373static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
 374	.name		= "ctrl_module_pad_core",
 375	.class		= &omap44xx_ctrl_module_hwmod_class,
 376	.clkdm_name	= "l4_cfg_clkdm",
 377	.prcm = {
 378		.omap4 = {
 379			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 380		},
 381	},
 382};
 383
 384/* ctrl_module_wkup */
 385static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
 386	.name		= "ctrl_module_wkup",
 387	.class		= &omap44xx_ctrl_module_hwmod_class,
 388	.clkdm_name	= "l4_wkup_clkdm",
 389	.prcm = {
 390		.omap4 = {
 391			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 392		},
 393	},
 394};
 395
 396/* ctrl_module_pad_wkup */
 397static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
 398	.name		= "ctrl_module_pad_wkup",
 399	.class		= &omap44xx_ctrl_module_hwmod_class,
 400	.clkdm_name	= "l4_wkup_clkdm",
 401	.prcm = {
 402		.omap4 = {
 403			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
 404		},
 405	},
 406};
 407
 408/*
 409 * 'debugss' class
 410 * debug and emulation sub system
 411 */
 412
 413static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
 414	.name	= "debugss",
 415};
 416
 417/* debugss */
 418static struct omap_hwmod omap44xx_debugss_hwmod = {
 419	.name		= "debugss",
 420	.class		= &omap44xx_debugss_hwmod_class,
 421	.clkdm_name	= "emu_sys_clkdm",
 422	.main_clk	= "trace_clk_div_ck",
 423	.prcm = {
 424		.omap4 = {
 425			.clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
 426			.context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
 427		},
 428	},
 429};
 430
 431/*
 432 * 'dma' class
 433 * dma controller for data exchange between memory to memory (i.e. internal or
 434 * external memory) and gp peripherals to memory or memory to gp peripherals
 435 */
 436
 437static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = {
 438	.rev_offs	= 0x0000,
 439	.sysc_offs	= 0x002c,
 440	.syss_offs	= 0x0028,
 441	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 442			   SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
 443			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 444			   SYSS_HAS_RESET_STATUS),
 445	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 446			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 447	.sysc_fields	= &omap_hwmod_sysc_type1,
 448};
 449
 450static struct omap_hwmod_class omap44xx_dma_hwmod_class = {
 451	.name	= "dma",
 452	.sysc	= &omap44xx_dma_sysc,
 453};
 454
 455/* dma dev_attr */
 456static struct omap_dma_dev_attr dma_dev_attr = {
 457	.dev_caps	= RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
 458			  IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
 459	.lch_count	= 32,
 460};
 461
 462/* dma_system */
 463static struct omap_hwmod omap44xx_dma_system_hwmod = {
 464	.name		= "dma_system",
 465	.class		= &omap44xx_dma_hwmod_class,
 466	.clkdm_name	= "l3_dma_clkdm",
 467	.main_clk	= "l3_div_ck",
 468	.prcm = {
 469		.omap4 = {
 470			.clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
 471			.context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
 472		},
 473	},
 474	.dev_attr	= &dma_dev_attr,
 475};
 476
 477/*
 478 * 'dmic' class
 479 * digital microphone controller
 480 */
 481
 482static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = {
 483	.rev_offs	= 0x0000,
 484	.sysc_offs	= 0x0010,
 485	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
 486			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
 487	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 488			   SIDLE_SMART_WKUP),
 489	.sysc_fields	= &omap_hwmod_sysc_type2,
 490};
 491
 492static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
 493	.name	= "dmic",
 494	.sysc	= &omap44xx_dmic_sysc,
 495};
 496
 497/* dmic */
 498static struct omap_hwmod omap44xx_dmic_hwmod = {
 499	.name		= "dmic",
 500	.class		= &omap44xx_dmic_hwmod_class,
 501	.clkdm_name	= "abe_clkdm",
 502	.main_clk	= "func_dmic_abe_gfclk",
 503	.prcm = {
 504		.omap4 = {
 505			.clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
 506			.context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
 507			.modulemode   = MODULEMODE_SWCTRL,
 508		},
 509	},
 510};
 511
 512/*
 513 * 'dsp' class
 514 * dsp sub-system
 515 */
 516
 517static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
 518	.name	= "dsp",
 519};
 520
 521/* dsp */
 522static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
 523	{ .name = "dsp", .rst_shift = 0 },
 524};
 525
 526static struct omap_hwmod omap44xx_dsp_hwmod = {
 527	.name		= "dsp",
 528	.class		= &omap44xx_dsp_hwmod_class,
 529	.clkdm_name	= "tesla_clkdm",
 530	.rst_lines	= omap44xx_dsp_resets,
 531	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_dsp_resets),
 532	.main_clk	= "dpll_iva_m4x2_ck",
 533	.prcm = {
 534		.omap4 = {
 535			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
 536			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
 537			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
 538			.modulemode   = MODULEMODE_HWCTRL,
 539		},
 540	},
 541};
 542
 543/*
 544 * 'dss' class
 545 * display sub-system
 546 */
 547
 548static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = {
 549	.rev_offs	= 0x0000,
 550	.syss_offs	= 0x0014,
 551	.sysc_flags	= SYSS_HAS_RESET_STATUS,
 552};
 553
 554static struct omap_hwmod_class omap44xx_dss_hwmod_class = {
 555	.name	= "dss",
 556	.sysc	= &omap44xx_dss_sysc,
 557	.reset	= omap_dss_reset,
 558};
 559
 560/* dss */
 561static struct omap_hwmod_opt_clk dss_opt_clks[] = {
 562	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 563	{ .role = "tv_clk", .clk = "dss_tv_clk" },
 564	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 565};
 566
 567static struct omap_hwmod omap44xx_dss_hwmod = {
 568	.name		= "dss_core",
 569	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 570	.class		= &omap44xx_dss_hwmod_class,
 571	.clkdm_name	= "l3_dss_clkdm",
 572	.main_clk	= "dss_dss_clk",
 573	.prcm = {
 574		.omap4 = {
 575			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 576			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 577			.modulemode   = MODULEMODE_SWCTRL,
 578		},
 579	},
 580	.opt_clks	= dss_opt_clks,
 581	.opt_clks_cnt	= ARRAY_SIZE(dss_opt_clks),
 582};
 583
 584/*
 585 * 'dispc' class
 586 * display controller
 587 */
 588
 589static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = {
 590	.rev_offs	= 0x0000,
 591	.sysc_offs	= 0x0010,
 592	.syss_offs	= 0x0014,
 593	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 594			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
 595			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 596			   SYSS_HAS_RESET_STATUS),
 597	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 598			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
 599	.sysc_fields	= &omap_hwmod_sysc_type1,
 600};
 601
 602static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
 603	.name	= "dispc",
 604	.sysc	= &omap44xx_dispc_sysc,
 605};
 606
 607/* dss_dispc */
 608static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = {
 609	.manager_count		= 3,
 610	.has_framedonetv_irq	= 1
 611};
 612
 613static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
 614	.name		= "dss_dispc",
 615	.class		= &omap44xx_dispc_hwmod_class,
 616	.clkdm_name	= "l3_dss_clkdm",
 617	.main_clk	= "dss_dss_clk",
 618	.prcm = {
 619		.omap4 = {
 620			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 621			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 622		},
 623	},
 624	.dev_attr	= &omap44xx_dss_dispc_dev_attr,
 625	.parent_hwmod	= &omap44xx_dss_hwmod,
 626};
 627
 628/*
 629 * 'dsi' class
 630 * display serial interface controller
 631 */
 632
 633static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = {
 634	.rev_offs	= 0x0000,
 635	.sysc_offs	= 0x0010,
 636	.syss_offs	= 0x0014,
 637	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 638			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
 639			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 640	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 641	.sysc_fields	= &omap_hwmod_sysc_type1,
 642};
 643
 644static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
 645	.name	= "dsi",
 646	.sysc	= &omap44xx_dsi_sysc,
 647};
 648
 649/* dss_dsi1 */
 650static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
 651	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 652};
 653
 654static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
 655	.name		= "dss_dsi1",
 656	.class		= &omap44xx_dsi_hwmod_class,
 657	.clkdm_name	= "l3_dss_clkdm",
 658	.main_clk	= "dss_dss_clk",
 659	.prcm = {
 660		.omap4 = {
 661			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 662			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 663		},
 664	},
 665	.opt_clks	= dss_dsi1_opt_clks,
 666	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi1_opt_clks),
 667	.parent_hwmod	= &omap44xx_dss_hwmod,
 668};
 669
 670/* dss_dsi2 */
 671static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
 672	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 673};
 674
 675static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
 676	.name		= "dss_dsi2",
 677	.class		= &omap44xx_dsi_hwmod_class,
 678	.clkdm_name	= "l3_dss_clkdm",
 679	.main_clk	= "dss_dss_clk",
 680	.prcm = {
 681		.omap4 = {
 682			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 683			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 684		},
 685	},
 686	.opt_clks	= dss_dsi2_opt_clks,
 687	.opt_clks_cnt	= ARRAY_SIZE(dss_dsi2_opt_clks),
 688	.parent_hwmod	= &omap44xx_dss_hwmod,
 689};
 690
 691/*
 692 * 'hdmi' class
 693 * hdmi controller
 694 */
 695
 696static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = {
 697	.rev_offs	= 0x0000,
 698	.sysc_offs	= 0x0010,
 699	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
 700			   SYSC_HAS_SOFTRESET),
 701	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
 702			   SIDLE_SMART_WKUP),
 703	.sysc_fields	= &omap_hwmod_sysc_type2,
 704};
 705
 706static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
 707	.name	= "hdmi",
 708	.sysc	= &omap44xx_hdmi_sysc,
 709};
 710
 711/* dss_hdmi */
 712static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
 713	{ .role = "sys_clk", .clk = "dss_sys_clk" },
 714	{ .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
 715};
 716
 717static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
 718	.name		= "dss_hdmi",
 719	.class		= &omap44xx_hdmi_hwmod_class,
 720	.clkdm_name	= "l3_dss_clkdm",
 721	/*
 722	 * HDMI audio requires to use no-idle mode. Hence,
 723	 * set idle mode by software.
 724	 */
 725	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_OPT_CLKS_NEEDED,
 726	.main_clk	= "dss_48mhz_clk",
 727	.prcm = {
 728		.omap4 = {
 729			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 730			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 731		},
 732	},
 733	.opt_clks	= dss_hdmi_opt_clks,
 734	.opt_clks_cnt	= ARRAY_SIZE(dss_hdmi_opt_clks),
 735	.parent_hwmod	= &omap44xx_dss_hwmod,
 736};
 737
 738/*
 739 * 'rfbi' class
 740 * remote frame buffer interface
 741 */
 742
 743static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = {
 744	.rev_offs	= 0x0000,
 745	.sysc_offs	= 0x0010,
 746	.syss_offs	= 0x0014,
 747	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
 748			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
 749	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 750	.sysc_fields	= &omap_hwmod_sysc_type1,
 751};
 752
 753static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
 754	.name	= "rfbi",
 755	.sysc	= &omap44xx_rfbi_sysc,
 756};
 757
 758/* dss_rfbi */
 759static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
 760	{ .role = "ick", .clk = "l3_div_ck" },
 761};
 762
 763static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
 764	.name		= "dss_rfbi",
 765	.class		= &omap44xx_rfbi_hwmod_class,
 766	.clkdm_name	= "l3_dss_clkdm",
 767	.main_clk	= "dss_dss_clk",
 768	.prcm = {
 769		.omap4 = {
 770			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 771			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 772		},
 773	},
 774	.opt_clks	= dss_rfbi_opt_clks,
 775	.opt_clks_cnt	= ARRAY_SIZE(dss_rfbi_opt_clks),
 776	.parent_hwmod	= &omap44xx_dss_hwmod,
 777};
 778
 779/*
 780 * 'venc' class
 781 * video encoder
 782 */
 783
 784static struct omap_hwmod_class omap44xx_venc_hwmod_class = {
 785	.name	= "venc",
 786};
 787
 788/* dss_venc */
 789static struct omap_hwmod_opt_clk dss_venc_opt_clks[] = {
 790	{ .role = "tv_clk", .clk = "dss_tv_clk" },
 791};
 792
 793static struct omap_hwmod omap44xx_dss_venc_hwmod = {
 794	.name		= "dss_venc",
 795	.class		= &omap44xx_venc_hwmod_class,
 796	.clkdm_name	= "l3_dss_clkdm",
 797	.main_clk	= "dss_tv_clk",
 798	.flags		= HWMOD_OPT_CLKS_NEEDED,
 799	.prcm = {
 800		.omap4 = {
 801			.clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
 802			.context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
 803		},
 804	},
 805	.parent_hwmod	= &omap44xx_dss_hwmod,
 806	.opt_clks	= dss_venc_opt_clks,
 807	.opt_clks_cnt	= ARRAY_SIZE(dss_venc_opt_clks),
 808};
 809
 810/* sha0 HIB2 (the 'P' (public) device) */
 811static struct omap_hwmod_class_sysconfig omap44xx_sha0_sysc = {
 812	.rev_offs	= 0x100,
 813	.sysc_offs	= 0x110,
 814	.syss_offs	= 0x114,
 815	.sysc_flags	= SYSS_HAS_RESET_STATUS,
 816};
 817
 818static struct omap_hwmod_class omap44xx_sha0_hwmod_class = {
 819	.name		= "sham",
 820	.sysc		= &omap44xx_sha0_sysc,
 821};
 822
 823struct omap_hwmod omap44xx_sha0_hwmod = {
 824	.name		= "sham",
 825	.class		= &omap44xx_sha0_hwmod_class,
 826	.clkdm_name	= "l4_secure_clkdm",
 827	.main_clk	= "l3_div_ck",
 828	.prcm		= {
 829		.omap4 = {
 830			.clkctrl_offs = OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET,
 831			.context_offs = OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET,
 832			.modulemode   = MODULEMODE_SWCTRL,
 833		},
 834	},
 835};
 836
 837/*
 838 * 'elm' class
 839 * bch error location module
 840 */
 841
 842static struct omap_hwmod_class_sysconfig omap44xx_elm_sysc = {
 843	.rev_offs	= 0x0000,
 844	.sysc_offs	= 0x0010,
 845	.syss_offs	= 0x0014,
 846	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
 847			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
 848			   SYSS_HAS_RESET_STATUS),
 849	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
 850	.sysc_fields	= &omap_hwmod_sysc_type1,
 851};
 852
 853static struct omap_hwmod_class omap44xx_elm_hwmod_class = {
 854	.name	= "elm",
 855	.sysc	= &omap44xx_elm_sysc,
 856};
 857
 858/* elm */
 859static struct omap_hwmod omap44xx_elm_hwmod = {
 860	.name		= "elm",
 861	.class		= &omap44xx_elm_hwmod_class,
 862	.clkdm_name	= "l4_per_clkdm",
 863	.prcm = {
 864		.omap4 = {
 865			.clkctrl_offs = OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET,
 866			.context_offs = OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET,
 867		},
 868	},
 869};
 870
 871/*
 872 * 'emif' class
 873 * external memory interface no1
 874 */
 875
 876static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
 877	.rev_offs	= 0x0000,
 878};
 879
 880static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
 881	.name	= "emif",
 882	.sysc	= &omap44xx_emif_sysc,
 883};
 884
 885/* emif1 */
 886static struct omap_hwmod omap44xx_emif1_hwmod = {
 887	.name		= "emif1",
 888	.class		= &omap44xx_emif_hwmod_class,
 889	.clkdm_name	= "l3_emif_clkdm",
 890	.flags		= HWMOD_INIT_NO_IDLE,
 891	.main_clk	= "ddrphy_ck",
 892	.prcm = {
 893		.omap4 = {
 894			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
 895			.context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
 896			.modulemode   = MODULEMODE_HWCTRL,
 897		},
 898	},
 899};
 900
 901/* emif2 */
 902static struct omap_hwmod omap44xx_emif2_hwmod = {
 903	.name		= "emif2",
 904	.class		= &omap44xx_emif_hwmod_class,
 905	.clkdm_name	= "l3_emif_clkdm",
 906	.flags		= HWMOD_INIT_NO_IDLE,
 907	.main_clk	= "ddrphy_ck",
 908	.prcm = {
 909		.omap4 = {
 910			.clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
 911			.context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
 912			.modulemode   = MODULEMODE_HWCTRL,
 913		},
 914	},
 915};
 916
 917/*
 918    Crypto modules AES0/1 belong to:
 919	PD_L4_PER power domain
 920	CD_L4_SEC clock domain
 921	On the L3, the AES modules are mapped to
 922	L3_CLK2: Peripherals and multimedia sub clock domain
 923*/
 924static struct omap_hwmod_class_sysconfig omap44xx_aes_sysc = {
 925	.rev_offs	= 0x80,
 926	.sysc_offs	= 0x84,
 927	.syss_offs	= 0x88,
 928	.sysc_flags	= SYSS_HAS_RESET_STATUS,
 929};
 930
 931static struct omap_hwmod_class omap44xx_aes_hwmod_class = {
 932	.name		= "aes",
 933	.sysc		= &omap44xx_aes_sysc,
 934};
 935
 936static struct omap_hwmod omap44xx_aes1_hwmod = {
 937	.name		= "aes1",
 938	.class		= &omap44xx_aes_hwmod_class,
 939	.clkdm_name	= "l4_secure_clkdm",
 940	.main_clk	= "l3_div_ck",
 941	.prcm		= {
 942		.omap4	= {
 943			.context_offs	= OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET,
 944			.clkctrl_offs	= OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET,
 945			.modulemode	= MODULEMODE_SWCTRL,
 946		},
 947	},
 948};
 949
 950static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes1 = {
 951	.master		= &omap44xx_l4_per_hwmod,
 952	.slave		= &omap44xx_aes1_hwmod,
 953	.clk		= "l3_div_ck",
 954	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 955};
 956
 957static struct omap_hwmod omap44xx_aes2_hwmod = {
 958	.name		= "aes2",
 959	.class		= &omap44xx_aes_hwmod_class,
 960	.clkdm_name	= "l4_secure_clkdm",
 961	.main_clk	= "l3_div_ck",
 962	.prcm		= {
 963		.omap4	= {
 964			.context_offs	= OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET,
 965			.clkctrl_offs	= OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET,
 966			.modulemode	= MODULEMODE_SWCTRL,
 967		},
 968	},
 969};
 970
 971static struct omap_hwmod_ocp_if omap44xx_l3_main_2__aes2 = {
 972	.master		= &omap44xx_l4_per_hwmod,
 973	.slave		= &omap44xx_aes2_hwmod,
 974	.clk		= "l3_div_ck",
 975	.user		= OCP_USER_MPU | OCP_USER_SDMA,
 976};
 977
 978/*
 979 * 'des' class for DES3DES module
 980 */
 981static struct omap_hwmod_class_sysconfig omap44xx_des_sysc = {
 982	.rev_offs	= 0x30,
 983	.sysc_offs	= 0x34,
 984	.syss_offs	= 0x38,
 985	.sysc_flags	= SYSS_HAS_RESET_STATUS,
 986};
 987
 988static struct omap_hwmod_class omap44xx_des_hwmod_class = {
 989	.name		= "des",
 990	.sysc		= &omap44xx_des_sysc,
 991};
 992
 993static struct omap_hwmod omap44xx_des_hwmod = {
 994	.name		= "des",
 995	.class		= &omap44xx_des_hwmod_class,
 996	.clkdm_name	= "l4_secure_clkdm",
 997	.main_clk	= "l3_div_ck",
 998	.prcm		= {
 999		.omap4	= {
1000			.context_offs	= OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET,
1001			.clkctrl_offs	= OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET,
1002			.modulemode	= MODULEMODE_SWCTRL,
1003		},
1004	},
1005};
1006
1007struct omap_hwmod_ocp_if omap44xx_l3_main_2__des = {
1008	.master		= &omap44xx_l3_main_2_hwmod,
1009	.slave		= &omap44xx_des_hwmod,
1010	.clk		= "l3_div_ck",
1011	.user		= OCP_USER_MPU | OCP_USER_SDMA,
1012};
1013
1014/*
1015 * 'fdif' class
1016 * face detection hw accelerator module
1017 */
1018
1019static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = {
1020	.rev_offs	= 0x0000,
1021	.sysc_offs	= 0x0010,
1022	/*
1023	 * FDIF needs 100 OCP clk cycles delay after a softreset before
1024	 * accessing sysconfig again.
1025	 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1026	 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1027	 *
1028	 * TODO: Indicate errata when available.
1029	 */
1030	.srst_udelay	= 2,
1031	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1032			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1033	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1034			   MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
1035	.sysc_fields	= &omap_hwmod_sysc_type2,
1036};
1037
1038static struct omap_hwmod_class omap44xx_fdif_hwmod_class = {
1039	.name	= "fdif",
1040	.sysc	= &omap44xx_fdif_sysc,
1041};
1042
1043/* fdif */
1044static struct omap_hwmod omap44xx_fdif_hwmod = {
1045	.name		= "fdif",
1046	.class		= &omap44xx_fdif_hwmod_class,
1047	.clkdm_name	= "iss_clkdm",
1048	.main_clk	= "fdif_fck",
1049	.prcm = {
1050		.omap4 = {
1051			.clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET,
1052			.context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET,
1053			.modulemode   = MODULEMODE_SWCTRL,
1054		},
1055	},
1056};
1057
1058/*
1059 * 'gpio' class
1060 * general purpose io module
1061 */
1062
1063static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = {
1064	.rev_offs	= 0x0000,
1065	.sysc_offs	= 0x0010,
1066	.syss_offs	= 0x0114,
1067	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1068			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1069			   SYSS_HAS_RESET_STATUS),
1070	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1071			   SIDLE_SMART_WKUP),
1072	.sysc_fields	= &omap_hwmod_sysc_type1,
1073};
1074
1075static struct omap_hwmod_class omap44xx_gpio_hwmod_class = {
1076	.name	= "gpio",
1077	.sysc	= &omap44xx_gpio_sysc,
1078	.rev	= 2,
1079};
1080
1081/* gpio1 */
1082static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
1083	{ .role = "dbclk", .clk = "gpio1_dbclk" },
1084};
1085
1086static struct omap_hwmod omap44xx_gpio1_hwmod = {
1087	.name		= "gpio1",
1088	.class		= &omap44xx_gpio_hwmod_class,
1089	.clkdm_name	= "l4_wkup_clkdm",
1090	.main_clk	= "l4_wkup_clk_mux_ck",
1091	.prcm = {
1092		.omap4 = {
1093			.clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
1094			.context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
1095			.modulemode   = MODULEMODE_HWCTRL,
1096		},
1097	},
1098	.opt_clks	= gpio1_opt_clks,
1099	.opt_clks_cnt	= ARRAY_SIZE(gpio1_opt_clks),
1100};
1101
1102/* gpio2 */
1103static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
1104	{ .role = "dbclk", .clk = "gpio2_dbclk" },
1105};
1106
1107static struct omap_hwmod omap44xx_gpio2_hwmod = {
1108	.name		= "gpio2",
1109	.class		= &omap44xx_gpio_hwmod_class,
1110	.clkdm_name	= "l4_per_clkdm",
1111	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1112	.main_clk	= "l4_div_ck",
1113	.prcm = {
1114		.omap4 = {
1115			.clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
1116			.context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
1117			.modulemode   = MODULEMODE_HWCTRL,
1118		},
1119	},
1120	.opt_clks	= gpio2_opt_clks,
1121	.opt_clks_cnt	= ARRAY_SIZE(gpio2_opt_clks),
1122};
1123
1124/* gpio3 */
1125static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
1126	{ .role = "dbclk", .clk = "gpio3_dbclk" },
1127};
1128
1129static struct omap_hwmod omap44xx_gpio3_hwmod = {
1130	.name		= "gpio3",
1131	.class		= &omap44xx_gpio_hwmod_class,
1132	.clkdm_name	= "l4_per_clkdm",
1133	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1134	.main_clk	= "l4_div_ck",
1135	.prcm = {
1136		.omap4 = {
1137			.clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
1138			.context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
1139			.modulemode   = MODULEMODE_HWCTRL,
1140		},
1141	},
1142	.opt_clks	= gpio3_opt_clks,
1143	.opt_clks_cnt	= ARRAY_SIZE(gpio3_opt_clks),
1144};
1145
1146/* gpio4 */
1147static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
1148	{ .role = "dbclk", .clk = "gpio4_dbclk" },
1149};
1150
1151static struct omap_hwmod omap44xx_gpio4_hwmod = {
1152	.name		= "gpio4",
1153	.class		= &omap44xx_gpio_hwmod_class,
1154	.clkdm_name	= "l4_per_clkdm",
1155	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1156	.main_clk	= "l4_div_ck",
1157	.prcm = {
1158		.omap4 = {
1159			.clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
1160			.context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
1161			.modulemode   = MODULEMODE_HWCTRL,
1162		},
1163	},
1164	.opt_clks	= gpio4_opt_clks,
1165	.opt_clks_cnt	= ARRAY_SIZE(gpio4_opt_clks),
1166};
1167
1168/* gpio5 */
1169static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
1170	{ .role = "dbclk", .clk = "gpio5_dbclk" },
1171};
1172
1173static struct omap_hwmod omap44xx_gpio5_hwmod = {
1174	.name		= "gpio5",
1175	.class		= &omap44xx_gpio_hwmod_class,
1176	.clkdm_name	= "l4_per_clkdm",
1177	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1178	.main_clk	= "l4_div_ck",
1179	.prcm = {
1180		.omap4 = {
1181			.clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
1182			.context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
1183			.modulemode   = MODULEMODE_HWCTRL,
1184		},
1185	},
1186	.opt_clks	= gpio5_opt_clks,
1187	.opt_clks_cnt	= ARRAY_SIZE(gpio5_opt_clks),
1188};
1189
1190/* gpio6 */
1191static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
1192	{ .role = "dbclk", .clk = "gpio6_dbclk" },
1193};
1194
1195static struct omap_hwmod omap44xx_gpio6_hwmod = {
1196	.name		= "gpio6",
1197	.class		= &omap44xx_gpio_hwmod_class,
1198	.clkdm_name	= "l4_per_clkdm",
1199	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
1200	.main_clk	= "l4_div_ck",
1201	.prcm = {
1202		.omap4 = {
1203			.clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
1204			.context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
1205			.modulemode   = MODULEMODE_HWCTRL,
1206		},
1207	},
1208	.opt_clks	= gpio6_opt_clks,
1209	.opt_clks_cnt	= ARRAY_SIZE(gpio6_opt_clks),
1210};
1211
1212/*
1213 * 'gpmc' class
1214 * general purpose memory controller
1215 */
1216
1217static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = {
1218	.rev_offs	= 0x0000,
1219	.sysc_offs	= 0x0010,
1220	.syss_offs	= 0x0014,
1221	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1222			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1223	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1224	.sysc_fields	= &omap_hwmod_sysc_type1,
1225};
1226
1227static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = {
1228	.name	= "gpmc",
1229	.sysc	= &omap44xx_gpmc_sysc,
1230};
1231
1232/* gpmc */
1233static struct omap_hwmod omap44xx_gpmc_hwmod = {
1234	.name		= "gpmc",
1235	.class		= &omap44xx_gpmc_hwmod_class,
1236	.clkdm_name	= "l3_2_clkdm",
1237	/* Skip reset for CONFIG_OMAP_GPMC_DEBUG for bootloader timings */
1238	.flags		= DEBUG_OMAP_GPMC_HWMOD_FLAGS,
1239	.prcm = {
1240		.omap4 = {
1241			.clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET,
1242			.context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET,
1243			.modulemode   = MODULEMODE_HWCTRL,
1244		},
1245	},
1246};
1247
1248/*
1249 * 'gpu' class
1250 * 2d/3d graphics accelerator
1251 */
1252
1253static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = {
1254	.rev_offs	= 0x1fc00,
1255	.sysc_offs	= 0x1fc10,
1256	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1257	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1258			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1259			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1260	.sysc_fields	= &omap_hwmod_sysc_type2,
1261};
1262
1263static struct omap_hwmod_class omap44xx_gpu_hwmod_class = {
1264	.name	= "gpu",
1265	.sysc	= &omap44xx_gpu_sysc,
1266};
1267
1268/* gpu */
1269static struct omap_hwmod omap44xx_gpu_hwmod = {
1270	.name		= "gpu",
1271	.class		= &omap44xx_gpu_hwmod_class,
1272	.clkdm_name	= "l3_gfx_clkdm",
1273	.main_clk	= "sgx_clk_mux",
1274	.prcm = {
1275		.omap4 = {
1276			.clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET,
1277			.context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET,
1278			.modulemode   = MODULEMODE_SWCTRL,
1279		},
1280	},
1281};
1282
1283/*
1284 * 'hdq1w' class
1285 * hdq / 1-wire serial interface controller
1286 */
1287
1288static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = {
1289	.rev_offs	= 0x0000,
1290	.sysc_offs	= 0x0014,
1291	.syss_offs	= 0x0018,
1292	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
1293			   SYSS_HAS_RESET_STATUS),
1294	.sysc_fields	= &omap_hwmod_sysc_type1,
1295};
1296
1297static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = {
1298	.name	= "hdq1w",
1299	.sysc	= &omap44xx_hdq1w_sysc,
1300};
1301
1302/* hdq1w */
1303static struct omap_hwmod omap44xx_hdq1w_hwmod = {
1304	.name		= "hdq1w",
1305	.class		= &omap44xx_hdq1w_hwmod_class,
1306	.clkdm_name	= "l4_per_clkdm",
1307	.flags		= HWMOD_INIT_NO_RESET, /* XXX temporary */
1308	.main_clk	= "func_12m_fclk",
1309	.prcm = {
1310		.omap4 = {
1311			.clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
1312			.context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
1313			.modulemode   = MODULEMODE_SWCTRL,
1314		},
1315	},
1316};
1317
1318/*
1319 * 'hsi' class
1320 * mipi high-speed synchronous serial interface (multichannel and full-duplex
1321 * serial if)
1322 */
1323
1324static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
1325	.rev_offs	= 0x0000,
1326	.sysc_offs	= 0x0010,
1327	.syss_offs	= 0x0014,
1328	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE |
1329			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
1330			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1331	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1332			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1333			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1334	.sysc_fields	= &omap_hwmod_sysc_type1,
1335};
1336
1337static struct omap_hwmod_class omap44xx_hsi_hwmod_class = {
1338	.name	= "hsi",
1339	.sysc	= &omap44xx_hsi_sysc,
1340};
1341
1342/* hsi */
1343static struct omap_hwmod omap44xx_hsi_hwmod = {
1344	.name		= "hsi",
1345	.class		= &omap44xx_hsi_hwmod_class,
1346	.clkdm_name	= "l3_init_clkdm",
1347	.main_clk	= "hsi_fck",
1348	.prcm = {
1349		.omap4 = {
1350			.clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
1351			.context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
1352			.modulemode   = MODULEMODE_HWCTRL,
1353		},
1354	},
1355};
1356
1357/*
1358 * 'i2c' class
1359 * multimaster high-speed i2c controller
1360 */
1361
1362static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
1363	.sysc_offs	= 0x0010,
1364	.syss_offs	= 0x0090,
1365	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1366			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1367			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1368	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1369			   SIDLE_SMART_WKUP),
1370	.sysc_fields	= &omap_hwmod_sysc_type1,
1371};
1372
1373static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
1374	.name	= "i2c",
1375	.sysc	= &omap44xx_i2c_sysc,
1376	.rev	= OMAP_I2C_IP_VERSION_2,
1377	.reset	= &omap_i2c_reset,
1378};
1379
1380/* i2c1 */
1381static struct omap_hwmod omap44xx_i2c1_hwmod = {
1382	.name		= "i2c1",
1383	.class		= &omap44xx_i2c_hwmod_class,
1384	.clkdm_name	= "l4_per_clkdm",
1385	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1386	.main_clk	= "func_96m_fclk",
1387	.prcm = {
1388		.omap4 = {
1389			.clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
1390			.context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
1391			.modulemode   = MODULEMODE_SWCTRL,
1392		},
1393	},
1394};
1395
1396/* i2c2 */
1397static struct omap_hwmod omap44xx_i2c2_hwmod = {
1398	.name		= "i2c2",
1399	.class		= &omap44xx_i2c_hwmod_class,
1400	.clkdm_name	= "l4_per_clkdm",
1401	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1402	.main_clk	= "func_96m_fclk",
1403	.prcm = {
1404		.omap4 = {
1405			.clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
1406			.context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
1407			.modulemode   = MODULEMODE_SWCTRL,
1408		},
1409	},
1410};
1411
1412/* i2c3 */
1413static struct omap_hwmod omap44xx_i2c3_hwmod = {
1414	.name		= "i2c3",
1415	.class		= &omap44xx_i2c_hwmod_class,
1416	.clkdm_name	= "l4_per_clkdm",
1417	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1418	.main_clk	= "func_96m_fclk",
1419	.prcm = {
1420		.omap4 = {
1421			.clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
1422			.context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
1423			.modulemode   = MODULEMODE_SWCTRL,
1424		},
1425	},
1426};
1427
1428/* i2c4 */
1429static struct omap_hwmod omap44xx_i2c4_hwmod = {
1430	.name		= "i2c4",
1431	.class		= &omap44xx_i2c_hwmod_class,
1432	.clkdm_name	= "l4_per_clkdm",
1433	.flags		= HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
1434	.main_clk	= "func_96m_fclk",
1435	.prcm = {
1436		.omap4 = {
1437			.clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
1438			.context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
1439			.modulemode   = MODULEMODE_SWCTRL,
1440		},
1441	},
1442};
1443
1444/*
1445 * 'ipu' class
1446 * imaging processor unit
1447 */
1448
1449static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
1450	.name	= "ipu",
1451};
1452
1453/* ipu */
1454static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
1455	{ .name = "cpu0", .rst_shift = 0 },
1456	{ .name = "cpu1", .rst_shift = 1 },
1457};
1458
1459static struct omap_hwmod omap44xx_ipu_hwmod = {
1460	.name		= "ipu",
1461	.class		= &omap44xx_ipu_hwmod_class,
1462	.clkdm_name	= "ducati_clkdm",
1463	.rst_lines	= omap44xx_ipu_resets,
1464	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_ipu_resets),
1465	.main_clk	= "ducati_clk_mux_ck",
1466	.prcm = {
1467		.omap4 = {
1468			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
1469			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
1470			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
1471			.modulemode   = MODULEMODE_HWCTRL,
1472		},
1473	},
1474};
1475
1476/*
1477 * 'iss' class
1478 * external images sensor pixel data processor
1479 */
1480
1481static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
1482	.rev_offs	= 0x0000,
1483	.sysc_offs	= 0x0010,
1484	/*
1485	 * ISS needs 100 OCP clk cycles delay after a softreset before
1486	 * accessing sysconfig again.
1487	 * The lowest frequency at the moment for L3 bus is 100 MHz, so
1488	 * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
1489	 *
1490	 * TODO: Indicate errata when available.
1491	 */
1492	.srst_udelay	= 2,
1493	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1494			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1495	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1496			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1497			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1498	.sysc_fields	= &omap_hwmod_sysc_type2,
1499};
1500
1501static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
1502	.name	= "iss",
1503	.sysc	= &omap44xx_iss_sysc,
1504};
1505
1506/* iss */
1507static struct omap_hwmod_opt_clk iss_opt_clks[] = {
1508	{ .role = "ctrlclk", .clk = "iss_ctrlclk" },
1509};
1510
1511static struct omap_hwmod omap44xx_iss_hwmod = {
1512	.name		= "iss",
1513	.class		= &omap44xx_iss_hwmod_class,
1514	.clkdm_name	= "iss_clkdm",
1515	.main_clk	= "ducati_clk_mux_ck",
1516	.prcm = {
1517		.omap4 = {
1518			.clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
1519			.context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
1520			.modulemode   = MODULEMODE_SWCTRL,
1521		},
1522	},
1523	.opt_clks	= iss_opt_clks,
1524	.opt_clks_cnt	= ARRAY_SIZE(iss_opt_clks),
1525};
1526
1527/*
1528 * 'iva' class
1529 * multi-standard video encoder/decoder hardware accelerator
1530 */
1531
1532static struct omap_hwmod_class omap44xx_iva_hwmod_class = {
1533	.name	= "iva",
1534};
1535
1536/* iva */
1537static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
1538	{ .name = "seq0", .rst_shift = 0 },
1539	{ .name = "seq1", .rst_shift = 1 },
1540	{ .name = "logic", .rst_shift = 2 },
1541};
1542
1543static struct omap_hwmod omap44xx_iva_hwmod = {
1544	.name		= "iva",
1545	.class		= &omap44xx_iva_hwmod_class,
1546	.clkdm_name	= "ivahd_clkdm",
1547	.rst_lines	= omap44xx_iva_resets,
1548	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_iva_resets),
1549	.main_clk	= "dpll_iva_m5x2_ck",
1550	.prcm = {
1551		.omap4 = {
1552			.clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
1553			.rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
1554			.context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
1555			.modulemode   = MODULEMODE_HWCTRL,
1556		},
1557	},
1558};
1559
1560/*
1561 * 'kbd' class
1562 * keyboard controller
1563 */
1564
1565static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = {
1566	.rev_offs	= 0x0000,
1567	.sysc_offs	= 0x0010,
1568	.syss_offs	= 0x0014,
1569	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1570			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
1571			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1572			   SYSS_HAS_RESET_STATUS),
1573	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1574	.sysc_fields	= &omap_hwmod_sysc_type1,
1575};
1576
1577static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
1578	.name	= "kbd",
1579	.sysc	= &omap44xx_kbd_sysc,
1580};
1581
1582/* kbd */
1583static struct omap_hwmod omap44xx_kbd_hwmod = {
1584	.name		= "kbd",
1585	.class		= &omap44xx_kbd_hwmod_class,
1586	.clkdm_name	= "l4_wkup_clkdm",
1587	.main_clk	= "sys_32k_ck",
1588	.prcm = {
1589		.omap4 = {
1590			.clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
1591			.context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
1592			.modulemode   = MODULEMODE_SWCTRL,
1593		},
1594	},
1595};
1596
1597/*
1598 * 'mailbox' class
1599 * mailbox module allowing communication between the on-chip processors using a
1600 * queued mailbox-interrupt mechanism.
1601 */
1602
1603static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = {
1604	.rev_offs	= 0x0000,
1605	.sysc_offs	= 0x0010,
1606	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1607			   SYSC_HAS_SOFTRESET),
1608	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1609	.sysc_fields	= &omap_hwmod_sysc_type2,
1610};
1611
1612static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
1613	.name	= "mailbox",
1614	.sysc	= &omap44xx_mailbox_sysc,
1615};
1616
1617/* mailbox */
1618static struct omap_hwmod omap44xx_mailbox_hwmod = {
1619	.name		= "mailbox",
1620	.class		= &omap44xx_mailbox_hwmod_class,
1621	.clkdm_name	= "l4_cfg_clkdm",
1622	.prcm = {
1623		.omap4 = {
1624			.clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
1625			.context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
1626		},
1627	},
1628};
1629
1630/*
1631 * 'mcasp' class
1632 * multi-channel audio serial port controller
1633 */
1634
1635/* The IP is not compliant to type1 / type2 scheme */
1636static struct omap_hwmod_class_sysconfig omap44xx_mcasp_sysc = {
1637	.sysc_offs	= 0x0004,
1638	.sysc_flags	= SYSC_HAS_SIDLEMODE,
1639	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1640			   SIDLE_SMART_WKUP),
1641	.sysc_fields	= &omap_hwmod_sysc_type_mcasp,
1642};
1643
1644static struct omap_hwmod_class omap44xx_mcasp_hwmod_class = {
1645	.name	= "mcasp",
1646	.sysc	= &omap44xx_mcasp_sysc,
1647};
1648
1649/* mcasp */
1650static struct omap_hwmod omap44xx_mcasp_hwmod = {
1651	.name		= "mcasp",
1652	.class		= &omap44xx_mcasp_hwmod_class,
1653	.clkdm_name	= "abe_clkdm",
1654	.main_clk	= "func_mcasp_abe_gfclk",
1655	.prcm = {
1656		.omap4 = {
1657			.clkctrl_offs = OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET,
1658			.context_offs = OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET,
1659			.modulemode   = MODULEMODE_SWCTRL,
1660		},
1661	},
1662};
1663
1664/*
1665 * 'mcbsp' class
1666 * multi channel buffered serial port controller
1667 */
1668
1669static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = {
1670	.sysc_offs	= 0x008c,
1671	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
1672			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1673	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1674	.sysc_fields	= &omap_hwmod_sysc_type1,
1675};
1676
1677static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
1678	.name	= "mcbsp",
1679	.sysc	= &omap44xx_mcbsp_sysc,
1680};
1681
1682/* mcbsp1 */
1683static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
1684	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1685	{ .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
1686};
1687
1688static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
1689	.name		= "mcbsp1",
1690	.class		= &omap44xx_mcbsp_hwmod_class,
1691	.clkdm_name	= "abe_clkdm",
1692	.main_clk	= "func_mcbsp1_gfclk",
1693	.prcm = {
1694		.omap4 = {
1695			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
1696			.context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
1697			.modulemode   = MODULEMODE_SWCTRL,
1698		},
1699	},
1700	.opt_clks	= mcbsp1_opt_clks,
1701	.opt_clks_cnt	= ARRAY_SIZE(mcbsp1_opt_clks),
1702};
1703
1704/* mcbsp2 */
1705static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
1706	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1707	{ .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
1708};
1709
1710static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
1711	.name		= "mcbsp2",
1712	.class		= &omap44xx_mcbsp_hwmod_class,
1713	.clkdm_name	= "abe_clkdm",
1714	.main_clk	= "func_mcbsp2_gfclk",
1715	.prcm = {
1716		.omap4 = {
1717			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
1718			.context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
1719			.modulemode   = MODULEMODE_SWCTRL,
1720		},
1721	},
1722	.opt_clks	= mcbsp2_opt_clks,
1723	.opt_clks_cnt	= ARRAY_SIZE(mcbsp2_opt_clks),
1724};
1725
1726/* mcbsp3 */
1727static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
1728	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1729	{ .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
1730};
1731
1732static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
1733	.name		= "mcbsp3",
1734	.class		= &omap44xx_mcbsp_hwmod_class,
1735	.clkdm_name	= "abe_clkdm",
1736	.main_clk	= "func_mcbsp3_gfclk",
1737	.prcm = {
1738		.omap4 = {
1739			.clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
1740			.context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
1741			.modulemode   = MODULEMODE_SWCTRL,
1742		},
1743	},
1744	.opt_clks	= mcbsp3_opt_clks,
1745	.opt_clks_cnt	= ARRAY_SIZE(mcbsp3_opt_clks),
1746};
1747
1748/* mcbsp4 */
1749static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = {
1750	{ .role = "pad_fck", .clk = "pad_clks_ck" },
1751	{ .role = "prcm_fck", .clk = "mcbsp4_sync_mux_ck" },
1752};
1753
1754static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
1755	.name		= "mcbsp4",
1756	.class		= &omap44xx_mcbsp_hwmod_class,
1757	.clkdm_name	= "l4_per_clkdm",
1758	.main_clk	= "per_mcbsp4_gfclk",
1759	.prcm = {
1760		.omap4 = {
1761			.clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
1762			.context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
1763			.modulemode   = MODULEMODE_SWCTRL,
1764		},
1765	},
1766	.opt_clks	= mcbsp4_opt_clks,
1767	.opt_clks_cnt	= ARRAY_SIZE(mcbsp4_opt_clks),
1768};
1769
1770/*
1771 * 'mcpdm' class
1772 * multi channel pdm controller (proprietary interface with phoenix power
1773 * ic)
1774 */
1775
1776static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = {
1777	.rev_offs	= 0x0000,
1778	.sysc_offs	= 0x0010,
1779	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1780			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1781	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1782			   SIDLE_SMART_WKUP),
1783	.sysc_fields	= &omap_hwmod_sysc_type2,
1784};
1785
1786static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
1787	.name	= "mcpdm",
1788	.sysc	= &omap44xx_mcpdm_sysc,
1789};
1790
1791/* mcpdm */
1792static struct omap_hwmod omap44xx_mcpdm_hwmod = {
1793	.name		= "mcpdm",
1794	.class		= &omap44xx_mcpdm_hwmod_class,
1795	.clkdm_name	= "abe_clkdm",
1796	/*
1797	 * It's suspected that the McPDM requires an off-chip main
1798	 * functional clock, controlled via I2C.  This IP block is
1799	 * currently reset very early during boot, before I2C is
1800	 * available, so it doesn't seem that we have any choice in
1801	 * the kernel other than to avoid resetting it.
1802	 *
1803	 * Also, McPDM needs to be configured to NO_IDLE mode when it
1804	 * is in used otherwise vital clocks will be gated which
1805	 * results 'slow motion' audio playback.
1806	 */
1807	.flags		= HWMOD_EXT_OPT_MAIN_CLK | HWMOD_SWSUP_SIDLE,
1808	.main_clk	= "pad_clks_ck",
1809	.prcm = {
1810		.omap4 = {
1811			.clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
1812			.context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
1813			.modulemode   = MODULEMODE_SWCTRL,
1814		},
1815	},
1816};
1817
1818/*
1819 * 'mcspi' class
1820 * multichannel serial port interface (mcspi) / master/slave synchronous serial
1821 * bus
1822 */
1823
1824static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
1825	.rev_offs	= 0x0000,
1826	.sysc_offs	= 0x0010,
1827	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1828			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1829	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1830			   SIDLE_SMART_WKUP),
1831	.sysc_fields	= &omap_hwmod_sysc_type2,
1832};
1833
1834static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
1835	.name	= "mcspi",
1836	.sysc	= &omap44xx_mcspi_sysc,
1837};
1838
1839/* mcspi1 */
1840static struct omap_hwmod omap44xx_mcspi1_hwmod = {
1841	.name		= "mcspi1",
1842	.class		= &omap44xx_mcspi_hwmod_class,
1843	.clkdm_name	= "l4_per_clkdm",
1844	.main_clk	= "func_48m_fclk",
1845	.prcm = {
1846		.omap4 = {
1847			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
1848			.context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
1849			.modulemode   = MODULEMODE_SWCTRL,
1850		},
1851	},
1852};
1853
1854/* mcspi2 */
1855static struct omap_hwmod omap44xx_mcspi2_hwmod = {
1856	.name		= "mcspi2",
1857	.class		= &omap44xx_mcspi_hwmod_class,
1858	.clkdm_name	= "l4_per_clkdm",
1859	.main_clk	= "func_48m_fclk",
1860	.prcm = {
1861		.omap4 = {
1862			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
1863			.context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
1864			.modulemode   = MODULEMODE_SWCTRL,
1865		},
1866	},
1867};
1868
1869/* mcspi3 */
1870static struct omap_hwmod omap44xx_mcspi3_hwmod = {
1871	.name		= "mcspi3",
1872	.class		= &omap44xx_mcspi_hwmod_class,
1873	.clkdm_name	= "l4_per_clkdm",
1874	.main_clk	= "func_48m_fclk",
1875	.prcm = {
1876		.omap4 = {
1877			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1878			.context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1879			.modulemode   = MODULEMODE_SWCTRL,
1880		},
1881	},
1882};
1883
1884/* mcspi4 */
1885static struct omap_hwmod omap44xx_mcspi4_hwmod = {
1886	.name		= "mcspi4",
1887	.class		= &omap44xx_mcspi_hwmod_class,
1888	.clkdm_name	= "l4_per_clkdm",
1889	.main_clk	= "func_48m_fclk",
1890	.prcm = {
1891		.omap4 = {
1892			.clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1893			.context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1894			.modulemode   = MODULEMODE_SWCTRL,
1895		},
1896	},
1897};
1898
1899/*
1900 * 'mmc' class
1901 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1902 */
1903
1904static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
1905	.rev_offs	= 0x0000,
1906	.sysc_offs	= 0x0010,
1907	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1908			   SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1909			   SYSC_HAS_SOFTRESET),
1910	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1911			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1912			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1913	.sysc_fields	= &omap_hwmod_sysc_type2,
1914};
1915
1916static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
1917	.name	= "mmc",
1918	.sysc	= &omap44xx_mmc_sysc,
1919};
1920
1921/* mmc1 */
1922static struct omap_hsmmc_dev_attr mmc1_dev_attr = {
1923	.flags	= OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1924};
1925
1926static struct omap_hwmod omap44xx_mmc1_hwmod = {
1927	.name		= "mmc1",
1928	.class		= &omap44xx_mmc_hwmod_class,
1929	.clkdm_name	= "l3_init_clkdm",
1930	.main_clk	= "hsmmc1_fclk",
1931	.prcm = {
1932		.omap4 = {
1933			.clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1934			.context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1935			.modulemode   = MODULEMODE_SWCTRL,
1936		},
1937	},
1938	.dev_attr	= &mmc1_dev_attr,
1939};
1940
1941/* mmc2 */
1942static struct omap_hwmod omap44xx_mmc2_hwmod = {
1943	.name		= "mmc2",
1944	.class		= &omap44xx_mmc_hwmod_class,
1945	.clkdm_name	= "l3_init_clkdm",
1946	.main_clk	= "hsmmc2_fclk",
1947	.prcm = {
1948		.omap4 = {
1949			.clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1950			.context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1951			.modulemode   = MODULEMODE_SWCTRL,
1952		},
1953	},
1954};
1955
1956/* mmc3 */
1957static struct omap_hwmod omap44xx_mmc3_hwmod = {
1958	.name		= "mmc3",
1959	.class		= &omap44xx_mmc_hwmod_class,
1960	.clkdm_name	= "l4_per_clkdm",
1961	.main_clk	= "func_48m_fclk",
1962	.prcm = {
1963		.omap4 = {
1964			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
1965			.context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
1966			.modulemode   = MODULEMODE_SWCTRL,
1967		},
1968	},
1969};
1970
1971/* mmc4 */
1972static struct omap_hwmod omap44xx_mmc4_hwmod = {
1973	.name		= "mmc4",
1974	.class		= &omap44xx_mmc_hwmod_class,
1975	.clkdm_name	= "l4_per_clkdm",
1976	.main_clk	= "func_48m_fclk",
1977	.prcm = {
1978		.omap4 = {
1979			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
1980			.context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
1981			.modulemode   = MODULEMODE_SWCTRL,
1982		},
1983	},
1984};
1985
1986/* mmc5 */
1987static struct omap_hwmod omap44xx_mmc5_hwmod = {
1988	.name		= "mmc5",
1989	.class		= &omap44xx_mmc_hwmod_class,
1990	.clkdm_name	= "l4_per_clkdm",
1991	.main_clk	= "func_48m_fclk",
1992	.prcm = {
1993		.omap4 = {
1994			.clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
1995			.context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
1996			.modulemode   = MODULEMODE_SWCTRL,
1997		},
1998	},
1999};
2000
2001/*
2002 * 'mmu' class
2003 * The memory management unit performs virtual to physical address translation
2004 * for its requestors.
2005 */
2006
2007static struct omap_hwmod_class_sysconfig mmu_sysc = {
2008	.rev_offs	= 0x000,
2009	.sysc_offs	= 0x010,
2010	.syss_offs	= 0x014,
2011	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2012			   SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
2013	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2014	.sysc_fields	= &omap_hwmod_sysc_type1,
2015};
2016
2017static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
2018	.name = "mmu",
2019	.sysc = &mmu_sysc,
2020};
2021
2022/* mmu ipu */
2023
2024static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
2025static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
2026	{ .name = "mmu_cache", .rst_shift = 2 },
2027};
2028
2029/* l3_main_2 -> mmu_ipu */
2030static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
2031	.master		= &omap44xx_l3_main_2_hwmod,
2032	.slave		= &omap44xx_mmu_ipu_hwmod,
2033	.clk		= "l3_div_ck",
2034	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2035};
2036
2037static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
2038	.name		= "mmu_ipu",
2039	.class		= &omap44xx_mmu_hwmod_class,
2040	.clkdm_name	= "ducati_clkdm",
2041	.rst_lines	= omap44xx_mmu_ipu_resets,
2042	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_ipu_resets),
2043	.main_clk	= "ducati_clk_mux_ck",
2044	.prcm = {
2045		.omap4 = {
2046			.clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
2047			.rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
2048			.context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
2049			.modulemode   = MODULEMODE_HWCTRL,
2050		},
2051	},
2052};
2053
2054/* mmu dsp */
2055
2056static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
2057static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
2058	{ .name = "mmu_cache", .rst_shift = 1 },
2059};
2060
2061/* l4_cfg -> dsp */
2062static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
2063	.master		= &omap44xx_l4_cfg_hwmod,
2064	.slave		= &omap44xx_mmu_dsp_hwmod,
2065	.clk		= "l4_div_ck",
2066	.user		= OCP_USER_MPU | OCP_USER_SDMA,
2067};
2068
2069static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
2070	.name		= "mmu_dsp",
2071	.class		= &omap44xx_mmu_hwmod_class,
2072	.clkdm_name	= "tesla_clkdm",
2073	.rst_lines	= omap44xx_mmu_dsp_resets,
2074	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_mmu_dsp_resets),
2075	.main_clk	= "dpll_iva_m4x2_ck",
2076	.prcm = {
2077		.omap4 = {
2078			.clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
2079			.rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
2080			.context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
2081			.modulemode   = MODULEMODE_HWCTRL,
2082		},
2083	},
2084};
2085
2086/*
2087 * 'mpu' class
2088 * mpu sub-system
2089 */
2090
2091static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
2092	.name	= "mpu",
2093};
2094
2095/* mpu */
2096static struct omap_hwmod omap44xx_mpu_hwmod = {
2097	.name		= "mpu",
2098	.class		= &omap44xx_mpu_hwmod_class,
2099	.clkdm_name	= "mpuss_clkdm",
2100	.flags		= HWMOD_INIT_NO_IDLE,
2101	.main_clk	= "dpll_mpu_m2_ck",
2102	.prcm = {
2103		.omap4 = {
2104			.clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
2105			.context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
2106		},
2107	},
2108};
2109
2110/*
2111 * 'ocmc_ram' class
2112 * top-level core on-chip ram
2113 */
2114
2115static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
2116	.name	= "ocmc_ram",
2117};
2118
2119/* ocmc_ram */
2120static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
2121	.name		= "ocmc_ram",
2122	.class		= &omap44xx_ocmc_ram_hwmod_class,
2123	.clkdm_name	= "l3_2_clkdm",
2124	.prcm = {
2125		.omap4 = {
2126			.clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
2127			.context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
2128		},
2129	},
2130};
2131
2132/*
2133 * 'ocp2scp' class
2134 * bridge to transform ocp interface protocol to scp (serial control port)
2135 * protocol
2136 */
2137
2138static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
2139	.rev_offs	= 0x0000,
2140	.sysc_offs	= 0x0010,
2141	.syss_offs	= 0x0014,
2142	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
2143			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2144	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2145	.sysc_fields	= &omap_hwmod_sysc_type1,
2146};
2147
2148static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
2149	.name	= "ocp2scp",
2150	.sysc	= &omap44xx_ocp2scp_sysc,
2151};
2152
2153/* ocp2scp_usb_phy */
2154static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
2155	.name		= "ocp2scp_usb_phy",
2156	.class		= &omap44xx_ocp2scp_hwmod_class,
2157	.clkdm_name	= "l3_init_clkdm",
2158	/*
2159	 * ocp2scp_usb_phy_phy_48m is provided by the OMAP4 PRCM IP
2160	 * block as an "optional clock," and normally should never be
2161	 * specified as the main_clk for an OMAP IP block.  However it
2162	 * turns out that this clock is actually the main clock for
2163	 * the ocp2scp_usb_phy IP block:
2164	 * http://lists.infradead.org/pipermail/linux-arm-kernel/2012-September/119943.html
2165	 * So listing ocp2scp_usb_phy_phy_48m as a main_clk here seems
2166	 * to be the best workaround.
2167	 */
2168	.main_clk	= "ocp2scp_usb_phy_phy_48m",
2169	.prcm = {
2170		.omap4 = {
2171			.clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
2172			.context_offs = OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET,
2173			.modulemode   = MODULEMODE_HWCTRL,
2174		},
2175	},
2176};
2177
2178/*
2179 * 'prcm' class
2180 * power and reset manager (part of the prcm infrastructure) + clock manager 2
2181 * + clock manager 1 (in always on power domain) + local prm in mpu
2182 */
2183
2184static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
2185	.name	= "prcm",
2186};
2187
2188/* prcm_mpu */
2189static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
2190	.name		= "prcm_mpu",
2191	.class		= &omap44xx_prcm_hwmod_class,
2192	.clkdm_name	= "l4_wkup_clkdm",
2193	.flags		= HWMOD_NO_IDLEST,
2194	.prcm = {
2195		.omap4 = {
2196			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2197		},
2198	},
2199};
2200
2201/* cm_core_aon */
2202static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
2203	.name		= "cm_core_aon",
2204	.class		= &omap44xx_prcm_hwmod_class,
2205	.flags		= HWMOD_NO_IDLEST,
2206	.prcm = {
2207		.omap4 = {
2208			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2209		},
2210	},
2211};
2212
2213/* cm_core */
2214static struct omap_hwmod omap44xx_cm_core_hwmod = {
2215	.name		= "cm_core",
2216	.class		= &omap44xx_prcm_hwmod_class,
2217	.flags		= HWMOD_NO_IDLEST,
2218	.prcm = {
2219		.omap4 = {
2220			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2221		},
2222	},
2223};
2224
2225/* prm */
2226static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
2227	{ .name = "rst_global_warm_sw", .rst_shift = 0 },
2228	{ .name = "rst_global_cold_sw", .rst_shift = 1 },
2229};
2230
2231static struct omap_hwmod omap44xx_prm_hwmod = {
2232	.name		= "prm",
2233	.class		= &omap44xx_prcm_hwmod_class,
2234	.rst_lines	= omap44xx_prm_resets,
2235	.rst_lines_cnt	= ARRAY_SIZE(omap44xx_prm_resets),
2236};
2237
2238/*
2239 * 'scrm' class
2240 * system clock and reset manager
2241 */
2242
2243static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
2244	.name	= "scrm",
2245};
2246
2247/* scrm */
2248static struct omap_hwmod omap44xx_scrm_hwmod = {
2249	.name		= "scrm",
2250	.class		= &omap44xx_scrm_hwmod_class,
2251	.clkdm_name	= "l4_wkup_clkdm",
2252	.prcm = {
2253		.omap4 = {
2254			.flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
2255		},
2256	},
2257};
2258
2259/*
2260 * 'sl2if' class
2261 * shared level 2 memory interface
2262 */
2263
2264static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
2265	.name	= "sl2if",
2266};
2267
2268/* sl2if */
2269static struct omap_hwmod omap44xx_sl2if_hwmod = {
2270	.name		= "sl2if",
2271	.class		= &omap44xx_sl2if_hwmod_class,
2272	.clkdm_name	= "ivahd_clkdm",
2273	.prcm = {
2274		.omap4 = {
2275			.clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
2276			.context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
2277			.modulemode   = MODULEMODE_HWCTRL,
2278		},
2279	},
2280};
2281
2282/*
2283 * 'slimbus' class
2284 * bidirectional, multi-drop, multi-channel two-line serial interface between
2285 * the device and external components
2286 */
2287
2288static struct omap_hwmod_class_sysconfig omap44xx_slimbus_sysc = {
2289	.rev_offs	= 0x0000,
2290	.sysc_offs	= 0x0010,
2291	.sysc_flags	= (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
2292			   SYSC_HAS_SOFTRESET),
2293	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2294			   SIDLE_SMART_WKUP),
2295	.sysc_fields	= &omap_hwmod_sysc_type2,
2296};
2297
2298static struct omap_hwmod_class omap44xx_slimbus_hwmod_class = {
2299	.name	= "slimbus",
2300	.sysc	= &omap44xx_slimbus_sysc,
2301};
2302
2303/* slimbus1 */
2304static struct omap_hwmod_opt_clk slimbus1_opt_clks[] = {
2305	{ .role = "fclk_1", .clk = "slimbus1_fclk_1" },
2306	{ .role = "fclk_0", .clk = "slimbus1_fclk_0" },
2307	{ .role = "fclk_2", .clk = "slimbus1_fclk_2" },
2308	{ .role = "slimbus_clk", .clk = "slimbus1_slimbus_clk" },
2309};
2310
2311static struct omap_hwmod omap44xx_slimbus1_hwmod = {
2312	.name		= "slimbus1",
2313	.class		= &omap44xx_slimbus_hwmod_class,
2314	.clkdm_name	= "abe_clkdm",
2315	.prcm = {
2316		.omap4 = {
2317			.clkctrl_offs = OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET,
2318			.context_offs = OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET,
2319			.modulemode   = MODULEMODE_SWCTRL,
2320		},
2321	},
2322	.opt_clks	= slimbus1_opt_clks,
2323	.opt_clks_cnt	= ARRAY_SIZE(slimbus1_opt_clks),
2324};
2325
2326/* slimbus2 */
2327static struct omap_hwmod_opt_clk slimbus2_opt_clks[] = {
2328	{ .role = "fclk_1", .clk = "slimbus2_fclk_1" },
2329	{ .role = "fclk_0", .clk = "slimbus2_fclk_0" },
2330	{ .role = "slimbus_clk", .clk = "slimbus2_slimbus_clk" },
2331};
2332
2333static struct omap_hwmod omap44xx_slimbus2_hwmod = {
2334	.name		= "slimbus2",
2335	.class		= &omap44xx_slimbus_hwmod_class,
2336	.clkdm_name	= "l4_per_clkdm",
2337	.prcm = {
2338		.omap4 = {
2339			.clkctrl_offs = OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET,
2340			.context_offs = OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET,
2341			.modulemode   = MODULEMODE_SWCTRL,
2342		},
2343	},
2344	.opt_clks	= slimbus2_opt_clks,
2345	.opt_clks_cnt	= ARRAY_SIZE(slimbus2_opt_clks),
2346};
2347
2348/*
2349 * 'smartreflex' class
2350 * smartreflex module (monitor silicon performance and outputs a measure of
2351 * performance error)
2352 */
2353
2354/* The IP is not compliant to type1 / type2 scheme */
2355static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = {
2356	.sysc_offs	= 0x0038,
2357	.sysc_flags	= (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
2358	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2359			   SIDLE_SMART_WKUP),
2360	.sysc_fields	= &omap36xx_sr_sysc_fields,
2361};
2362
2363static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
2364	.name	= "smartreflex",
2365	.sysc	= &omap44xx_smartreflex_sysc,
2366	.rev	= 2,
2367};
2368
2369/* smartreflex_core */
2370static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
2371	.sensor_voltdm_name   = "core",
2372};
2373
2374static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
2375	.name		= "smartreflex_core",
2376	.class		= &omap44xx_smartreflex_hwmod_class,
2377	.clkdm_name	= "l4_ao_clkdm",
2378
2379	.main_clk	= "smartreflex_core_fck",
2380	.prcm = {
2381		.omap4 = {
2382			.clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
2383			.context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
2384			.modulemode   = MODULEMODE_SWCTRL,
2385		},
2386	},
2387	.dev_attr	= &smartreflex_core_dev_attr,
2388};
2389
2390/* smartreflex_iva */
2391static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = {
2392	.sensor_voltdm_name	= "iva",
2393};
2394
2395static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
2396	.name		= "smartreflex_iva",
2397	.class		= &omap44xx_smartreflex_hwmod_class,
2398	.clkdm_name	= "l4_ao_clkdm",
2399	.main_clk	= "smartreflex_iva_fck",
2400	.prcm = {
2401		.omap4 = {
2402			.clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
2403			.context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
2404			.modulemode   = MODULEMODE_SWCTRL,
2405		},
2406	},
2407	.dev_attr	= &smartreflex_iva_dev_attr,
2408};
2409
2410/* smartreflex_mpu */
2411static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
2412	.sensor_voltdm_name	= "mpu",
2413};
2414
2415static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
2416	.name		= "smartreflex_mpu",
2417	.class		= &omap44xx_smartreflex_hwmod_class,
2418	.clkdm_name	= "l4_ao_clkdm",
2419	.main_clk	= "smartreflex_mpu_fck",
2420	.prcm = {
2421		.omap4 = {
2422			.clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
2423			.context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
2424			.modulemode   = MODULEMODE_SWCTRL,
2425		},
2426	},
2427	.dev_attr	= &smartreflex_mpu_dev_attr,
2428};
2429
2430/*
2431 * 'spinlock' class
2432 * spinlock provides hardware assistance for synchronizing the processes
2433 * running on multiple processors
2434 */
2435
2436static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = {
2437	.rev_offs	= 0x0000,
2438	.sysc_offs	= 0x0010,
2439	.syss_offs	= 0x0014,
2440	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2441			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
2442			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2443	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2444	.sysc_fields	= &omap_hwmod_sysc_type1,
2445};
2446
2447static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = {
2448	.name	= "spinlock",
2449	.sysc	= &omap44xx_spinlock_sysc,
2450};
2451
2452/* spinlock */
2453static struct omap_hwmod omap44xx_spinlock_hwmod = {
2454	.name		= "spinlock",
2455	.class		= &omap44xx_spinlock_hwmod_class,
2456	.clkdm_name	= "l4_cfg_clkdm",
2457	.prcm = {
2458		.omap4 = {
2459			.clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
2460			.context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
2461		},
2462	},
2463};
2464
2465/*
2466 * 'timer' class
2467 * general purpose timer module with accurate 1ms tick
2468 * This class contains several variants: ['timer_1ms', 'timer']
2469 */
2470
2471static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = {
2472	.rev_offs	= 0x0000,
2473	.sysc_offs	= 0x0010,
2474	.syss_offs	= 0x0014,
2475	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
2476			   SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP |
2477			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2478			   SYSS_HAS_RESET_STATUS),
2479	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2480	.sysc_fields	= &omap_hwmod_sysc_type1,
2481};
2482
2483static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = {
2484	.name	= "timer",
2485	.sysc	= &omap44xx_timer_1ms_sysc,
2486};
2487
2488static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = {
2489	.rev_offs	= 0x0000,
2490	.sysc_offs	= 0x0010,
2491	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
2492			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
2493	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2494			   SIDLE_SMART_WKUP),
2495	.sysc_fields	= &omap_hwmod_sysc_type2,
2496};
2497
2498static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
2499	.name	= "timer",
2500	.sysc	= &omap44xx_timer_sysc,
2501};
2502
2503/* timer1 */
2504static struct omap_hwmod omap44xx_timer1_hwmod = {
2505	.name		= "timer1",
2506	.class		= &omap44xx_timer_1ms_hwmod_class,
2507	.clkdm_name	= "l4_wkup_clkdm",
2508	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2509	.main_clk	= "dmt1_clk_mux",
2510	.prcm = {
2511		.omap4 = {
2512			.clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
2513			.context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
2514			.modulemode   = MODULEMODE_SWCTRL,
2515		},
2516	},
2517};
2518
2519/* timer2 */
2520static struct omap_hwmod omap44xx_timer2_hwmod = {
2521	.name		= "timer2",
2522	.class		= &omap44xx_timer_1ms_hwmod_class,
2523	.clkdm_name	= "l4_per_clkdm",
2524	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2525	.main_clk	= "cm2_dm2_mux",
2526	.prcm = {
2527		.omap4 = {
2528			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
2529			.context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
2530			.modulemode   = MODULEMODE_SWCTRL,
2531		},
2532	},
2533};
2534
2535/* timer3 */
2536static struct omap_hwmod omap44xx_timer3_hwmod = {
2537	.name		= "timer3",
2538	.class		= &omap44xx_timer_hwmod_class,
2539	.clkdm_name	= "l4_per_clkdm",
2540	.main_clk	= "cm2_dm3_mux",
2541	.prcm = {
2542		.omap4 = {
2543			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
2544			.context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
2545			.modulemode   = MODULEMODE_SWCTRL,
2546		},
2547	},
2548};
2549
2550/* timer4 */
2551static struct omap_hwmod omap44xx_timer4_hwmod = {
2552	.name		= "timer4",
2553	.class		= &omap44xx_timer_hwmod_class,
2554	.clkdm_name	= "l4_per_clkdm",
2555	.main_clk	= "cm2_dm4_mux",
2556	.prcm = {
2557		.omap4 = {
2558			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
2559			.context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
2560			.modulemode   = MODULEMODE_SWCTRL,
2561		},
2562	},
2563};
2564
2565/* timer5 */
2566static struct omap_hwmod omap44xx_timer5_hwmod = {
2567	.name		= "timer5",
2568	.class		= &omap44xx_timer_hwmod_class,
2569	.clkdm_name	= "abe_clkdm",
2570	.main_clk	= "timer5_sync_mux",
2571	.prcm = {
2572		.omap4 = {
2573			.clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
2574			.context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
2575			.modulemode   = MODULEMODE_SWCTRL,
2576		},
2577	},
2578};
2579
2580/* timer6 */
2581static struct omap_hwmod omap44xx_timer6_hwmod = {
2582	.name		= "timer6",
2583	.class		= &omap44xx_timer_hwmod_class,
2584	.clkdm_name	= "abe_clkdm",
2585	.main_clk	= "timer6_sync_mux",
2586	.prcm = {
2587		.omap4 = {
2588			.clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
2589			.context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
2590			.modulemode   = MODULEMODE_SWCTRL,
2591		},
2592	},
2593};
2594
2595/* timer7 */
2596static struct omap_hwmod omap44xx_timer7_hwmod = {
2597	.name		= "timer7",
2598	.class		= &omap44xx_timer_hwmod_class,
2599	.clkdm_name	= "abe_clkdm",
2600	.main_clk	= "timer7_sync_mux",
2601	.prcm = {
2602		.omap4 = {
2603			.clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
2604			.context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
2605			.modulemode   = MODULEMODE_SWCTRL,
2606		},
2607	},
2608};
2609
2610/* timer8 */
2611static struct omap_hwmod omap44xx_timer8_hwmod = {
2612	.name		= "timer8",
2613	.class		= &omap44xx_timer_hwmod_class,
2614	.clkdm_name	= "abe_clkdm",
2615	.main_clk	= "timer8_sync_mux",
2616	.prcm = {
2617		.omap4 = {
2618			.clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
2619			.context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
2620			.modulemode   = MODULEMODE_SWCTRL,
2621		},
2622	},
2623};
2624
2625/* timer9 */
2626static struct omap_hwmod omap44xx_timer9_hwmod = {
2627	.name		= "timer9",
2628	.class		= &omap44xx_timer_hwmod_class,
2629	.clkdm_name	= "l4_per_clkdm",
2630	.main_clk	= "cm2_dm9_mux",
2631	.prcm = {
2632		.omap4 = {
2633			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
2634			.context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
2635			.modulemode   = MODULEMODE_SWCTRL,
2636		},
2637	},
2638};
2639
2640/* timer10 */
2641static struct omap_hwmod omap44xx_timer10_hwmod = {
2642	.name		= "timer10",
2643	.class		= &omap44xx_timer_1ms_hwmod_class,
2644	.clkdm_name	= "l4_per_clkdm",
2645	.flags		= HWMOD_SET_DEFAULT_CLOCKACT,
2646	.main_clk	= "cm2_dm10_mux",
2647	.prcm = {
2648		.omap4 = {
2649			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
2650			.context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
2651			.modulemode   = MODULEMODE_SWCTRL,
2652		},
2653	},
2654};
2655
2656/* timer11 */
2657static struct omap_hwmod omap44xx_timer11_hwmod = {
2658	.name		= "timer11",
2659	.class		= &omap44xx_timer_hwmod_class,
2660	.clkdm_name	= "l4_per_clkdm",
2661	.main_clk	= "cm2_dm11_mux",
2662	.prcm = {
2663		.omap4 = {
2664			.clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
2665			.context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
2666			.modulemode   = MODULEMODE_SWCTRL,
2667		},
2668	},
2669};
2670
2671/*
2672 * 'uart' class
2673 * universal asynchronous receiver/transmitter (uart)
2674 */
2675
2676static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = {
2677	.rev_offs	= 0x0050,
2678	.sysc_offs	= 0x0054,
2679	.syss_offs	= 0x0058,
2680	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2681			   SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
2682			   SYSS_HAS_RESET_STATUS),
2683	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2684			   SIDLE_SMART_WKUP),
2685	.sysc_fields	= &omap_hwmod_sysc_type1,
2686};
2687
2688static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
2689	.name	= "uart",
2690	.sysc	= &omap44xx_uart_sysc,
2691};
2692
2693/* uart1 */
2694static struct omap_hwmod omap44xx_uart1_hwmod = {
2695	.name		= "uart1",
2696	.class		= &omap44xx_uart_hwmod_class,
2697	.clkdm_name	= "l4_per_clkdm",
2698	.flags		= HWMOD_SWSUP_SIDLE_ACT,
2699	.main_clk	= "func_48m_fclk",
2700	.prcm = {
2701		.omap4 = {
2702			.clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
2703			.context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
2704			.modulemode   = MODULEMODE_SWCTRL,
2705		},
2706	},
2707};
2708
2709/* uart2 */
2710static struct omap_hwmod omap44xx_uart2_hwmod = {
2711	.name		= "uart2",
2712	.class		= &omap44xx_uart_hwmod_class,
2713	.clkdm_name	= "l4_per_clkdm",
2714	.flags		= HWMOD_SWSUP_SIDLE_ACT,
2715	.main_clk	= "func_48m_fclk",
2716	.prcm = {
2717		.omap4 = {
2718			.clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
2719			.context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
2720			.modulemode   = MODULEMODE_SWCTRL,
2721		},
2722	},
2723};
2724
2725/* uart3 */
2726static struct omap_hwmod omap44xx_uart3_hwmod = {
2727	.name		= "uart3",
2728	.class		= &omap44xx_uart_hwmod_class,
2729	.clkdm_name	= "l4_per_clkdm",
2730	.flags		= DEBUG_OMAP4UART3_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2731	.main_clk	= "func_48m_fclk",
2732	.prcm = {
2733		.omap4 = {
2734			.clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
2735			.context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
2736			.modulemode   = MODULEMODE_SWCTRL,
2737		},
2738	},
2739};
2740
2741/* uart4 */
2742static struct omap_hwmod omap44xx_uart4_hwmod = {
2743	.name		= "uart4",
2744	.class		= &omap44xx_uart_hwmod_class,
2745	.clkdm_name	= "l4_per_clkdm",
2746	.flags		= DEBUG_OMAP4UART4_FLAGS | HWMOD_SWSUP_SIDLE_ACT,
2747	.main_clk	= "func_48m_fclk",
2748	.prcm = {
2749		.omap4 = {
2750			.clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
2751			.context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
2752			.modulemode   = MODULEMODE_SWCTRL,
2753		},
2754	},
2755};
2756
2757/*
2758 * 'usb_host_fs' class
2759 * full-speed usb host controller
2760 */
2761
2762/* The IP is not compliant to type1 / type2 scheme */
2763static struct omap_hwmod_class_sysconfig omap44xx_usb_host_fs_sysc = {
2764	.rev_offs	= 0x0000,
2765	.sysc_offs	= 0x0210,
2766	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2767			   SYSC_HAS_SOFTRESET),
2768	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2769			   SIDLE_SMART_WKUP),
2770	.sysc_fields	= &omap_hwmod_sysc_type_usb_host_fs,
2771};
2772
2773static struct omap_hwmod_class omap44xx_usb_host_fs_hwmod_class = {
2774	.name	= "usb_host_fs",
2775	.sysc	= &omap44xx_usb_host_fs_sysc,
2776};
2777
2778/* usb_host_fs */
2779static struct omap_hwmod omap44xx_usb_host_fs_hwmod = {
2780	.name		= "usb_host_fs",
2781	.class		= &omap44xx_usb_host_fs_hwmod_class,
2782	.clkdm_name	= "l3_init_clkdm",
2783	.main_clk	= "usb_host_fs_fck",
2784	.prcm = {
2785		.omap4 = {
2786			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET,
2787			.context_offs = OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET,
2788			.modulemode   = MODULEMODE_SWCTRL,
2789		},
2790	},
2791};
2792
2793/*
2794 * 'usb_host_hs' class
2795 * high-speed multi-port usb host controller
2796 */
2797
2798static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = {
2799	.rev_offs	= 0x0000,
2800	.sysc_offs	= 0x0010,
2801	.syss_offs	= 0x0014,
2802	.sysc_flags	= (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2803			   SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
2804	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2805			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2806			   MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
2807	.sysc_fields	= &omap_hwmod_sysc_type2,
2808};
2809
2810static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = {
2811	.name	= "usb_host_hs",
2812	.sysc	= &omap44xx_usb_host_hs_sysc,
2813};
2814
2815/* usb_host_hs */
2816static struct omap_hwmod omap44xx_usb_host_hs_hwmod = {
2817	.name		= "usb_host_hs",
2818	.class		= &omap44xx_usb_host_hs_hwmod_class,
2819	.clkdm_name	= "l3_init_clkdm",
2820	.main_clk	= "usb_host_hs_fck",
2821	.prcm = {
2822		.omap4 = {
2823			.clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET,
2824			.context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET,
2825			.modulemode   = MODULEMODE_SWCTRL,
2826		},
2827	},
2828
2829	/*
2830	 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
2831	 * id: i660
2832	 *
2833	 * Description:
2834	 * In the following configuration :
2835	 * - USBHOST module is set to smart-idle mode
2836	 * - PRCM asserts idle_req to the USBHOST module ( This typically
2837	 *   happens when the system is going to a low power mode : all ports
2838	 *   have been suspended, the master part of the USBHOST module has
2839	 *   entered the standby state, and SW has cut the functional clocks)
2840	 * - an USBHOST interrupt occurs before the module is able to answer
2841	 *   idle_ack, typically a remote wakeup IRQ.
2842	 * Then the USB HOST module will enter a deadlock situation where it
2843	 * is no more accessible nor functional.
2844	 *
2845	 * Workaround:
2846	 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
2847	 */
2848
2849	/*
2850	 * Errata: USB host EHCI may stall when entering smart-standby mode
2851	 * Id: i571
2852	 *
2853	 * Description:
2854	 * When the USBHOST module is set to smart-standby mode, and when it is
2855	 * ready to enter the standby state (i.e. all ports are suspended and
2856	 * all attached devices are in suspend mode), then it can wrongly assert
2857	 * the Mstandby signal too early while there are still some residual OCP
2858	 * transactions ongoing. If this condition occurs, the internal state
2859	 * machine may go to an undefined state and the USB link may be stuck
2860	 * upon the next resume.
2861	 *
2862	 * Workaround:
2863	 * Don't use smart standby; use only force standby,
2864	 * hence HWMOD_SWSUP_MSTANDBY
2865	 */
2866
2867	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2868};
2869
2870/*
2871 * 'usb_otg_hs' class
2872 * high-speed on-the-go universal serial bus (usb_otg_hs) controller
2873 */
2874
2875static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
2876	.rev_offs	= 0x0400,
2877	.sysc_offs	= 0x0404,
2878	.syss_offs	= 0x0408,
2879	.sysc_flags	= (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
2880			   SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE |
2881			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2882	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2883			   SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
2884			   MSTANDBY_SMART),
2885	.sysc_fields	= &omap_hwmod_sysc_type1,
2886};
2887
2888static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
2889	.name	= "usb_otg_hs",
2890	.sysc	= &omap44xx_usb_otg_hs_sysc,
2891};
2892
2893/* usb_otg_hs */
2894static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
2895	{ .role = "xclk", .clk = "usb_otg_hs_xclk" },
2896};
2897
2898static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
2899	.name		= "usb_otg_hs",
2900	.class		= &omap44xx_usb_otg_hs_hwmod_class,
2901	.clkdm_name	= "l3_init_clkdm",
2902	.flags		= HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
2903	.main_clk	= "usb_otg_hs_ick",
2904	.prcm = {
2905		.omap4 = {
2906			.clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
2907			.context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
2908			.modulemode   = MODULEMODE_HWCTRL,
2909		},
2910	},
2911	.opt_clks	= usb_otg_hs_opt_clks,
2912	.opt_clks_cnt	= ARRAY_SIZE(usb_otg_hs_opt_clks),
2913};
2914
2915/*
2916 * 'usb_tll_hs' class
2917 * usb_tll_hs module is the adapter on the usb_host_hs ports
2918 */
2919
2920static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = {
2921	.rev_offs	= 0x0000,
2922	.sysc_offs	= 0x0010,
2923	.syss_offs	= 0x0014,
2924	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
2925			   SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
2926			   SYSC_HAS_AUTOIDLE),
2927	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
2928	.sysc_fields	= &omap_hwmod_sysc_type1,
2929};
2930
2931static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = {
2932	.name	= "usb_tll_hs",
2933	.sysc	= &omap44xx_usb_tll_hs_sysc,
2934};
2935
2936static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = {
2937	.name		= "usb_tll_hs",
2938	.class		= &omap44xx_usb_tll_hs_hwmod_class,
2939	.clkdm_name	= "l3_init_clkdm",
2940	.main_clk	= "usb_tll_hs_ick",
2941	.prcm = {
2942		.omap4 = {
2943			.clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET,
2944			.context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET,
2945			.modulemode   = MODULEMODE_HWCTRL,
2946		},
2947	},
2948};
2949
2950/*
2951 * 'wd_timer' class
2952 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
2953 * overflow condition
2954 */
2955
2956static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = {
2957	.rev_offs	= 0x0000,
2958	.sysc_offs	= 0x0010,
2959	.syss_offs	= 0x0014,
2960	.sysc_flags	= (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
2961			   SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
2962	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
2963			   SIDLE_SMART_WKUP),
2964	.sysc_fields	= &omap_hwmod_sysc_type1,
2965};
2966
2967static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
2968	.name		= "wd_timer",
2969	.sysc		= &omap44xx_wd_timer_sysc,
2970	.pre_shutdown	= &omap2_wd_timer_disable,
2971	.reset		= &omap2_wd_timer_reset,
2972};
2973
2974/* wd_timer2 */
2975static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
2976	.name		= "wd_timer2",
2977	.class		= &omap44xx_wd_timer_hwmod_class,
2978	.clkdm_name	= "l4_wkup_clkdm",
2979	.main_clk	= "sys_32k_ck",
2980	.prcm = {
2981		.omap4 = {
2982			.clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
2983			.context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
2984			.modulemode   = MODULEMODE_SWCTRL,
2985		},
2986	},
2987};
2988
2989/* wd_timer3 */
2990static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
2991	.name		= "wd_timer3",
2992	.class		= &omap44xx_wd_timer_hwmod_class,
2993	.clkdm_name	= "abe_clkdm",
2994	.main_clk	= "sys_32k_ck",
2995	.prcm = {
2996		.omap4 = {
2997			.clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
2998			.context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
2999			.modulemode   = MODULEMODE_SWCTRL,
3000		},
3001	},
3002};
3003
3004
3005/*
3006 * interfaces
3007 */
3008
3009/* l3_main_1 -> dmm */
3010static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
3011	.master		= &omap44xx_l3_main_1_hwmod,
3012	.slave		= &omap44xx_dmm_hwmod,
3013	.clk		= "l3_div_ck",
3014	.user		= OCP_USER_SDMA,
3015};
3016
3017/* mpu -> dmm */
3018static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
3019	.master		= &omap44xx_mpu_hwmod,
3020	.slave		= &omap44xx_dmm_hwmod,
3021	.clk		= "l3_div_ck",
3022	.user		= OCP_USER_MPU,
3023};
3024
3025/* iva -> l3_instr */
3026static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
3027	.master		= &omap44xx_iva_hwmod,
3028	.slave		= &omap44xx_l3_instr_hwmod,
3029	.clk		= "l3_div_ck",
3030	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3031};
3032
3033/* l3_main_3 -> l3_instr */
3034static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
3035	.master		= &omap44xx_l3_main_3_hwmod,
3036	.slave		= &omap44xx_l3_instr_hwmod,
3037	.clk		= "l3_div_ck",
3038	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3039};
3040
3041/* ocp_wp_noc -> l3_instr */
3042static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
3043	.master		= &omap44xx_ocp_wp_noc_hwmod,
3044	.slave		= &omap44xx_l3_instr_hwmod,
3045	.clk		= "l3_div_ck",
3046	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3047};
3048
3049/* dsp -> l3_main_1 */
3050static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
3051	.master		= &omap44xx_dsp_hwmod,
3052	.slave		= &omap44xx_l3_main_1_hwmod,
3053	.clk		= "l3_div_ck",
3054	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3055};
3056
3057/* dss -> l3_main_1 */
3058static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = {
3059	.master		= &omap44xx_dss_hwmod,
3060	.slave		= &omap44xx_l3_main_1_hwmod,
3061	.clk		= "l3_div_ck",
3062	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3063};
3064
3065/* l3_main_2 -> l3_main_1 */
3066static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
3067	.master		= &omap44xx_l3_main_2_hwmod,
3068	.slave		= &omap44xx_l3_main_1_hwmod,
3069	.clk		= "l3_div_ck",
3070	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3071};
3072
3073/* l4_cfg -> l3_main_1 */
3074static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
3075	.master		= &omap44xx_l4_cfg_hwmod,
3076	.slave		= &omap44xx_l3_main_1_hwmod,
3077	.clk		= "l4_div_ck",
3078	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3079};
3080
3081/* mmc1 -> l3_main_1 */
3082static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = {
3083	.master		= &omap44xx_mmc1_hwmod,
3084	.slave		= &omap44xx_l3_main_1_hwmod,
3085	.clk		= "l3_div_ck",
3086	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3087};
3088
3089/* mmc2 -> l3_main_1 */
3090static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
3091	.master		= &omap44xx_mmc2_hwmod,
3092	.slave		= &omap44xx_l3_main_1_hwmod,
3093	.clk		= "l3_div_ck",
3094	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3095};
3096
3097/* mpu -> l3_main_1 */
3098static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
3099	.master		= &omap44xx_mpu_hwmod,
3100	.slave		= &omap44xx_l3_main_1_hwmod,
3101	.clk		= "l3_div_ck",
3102	.user		= OCP_USER_MPU,
3103};
3104
3105/* debugss -> l3_main_2 */
3106static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
3107	.master		= &omap44xx_debugss_hwmod,
3108	.slave		= &omap44xx_l3_main_2_hwmod,
3109	.clk		= "dbgclk_mux_ck",
3110	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3111};
3112
3113/* dma_system -> l3_main_2 */
3114static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
3115	.master		= &omap44xx_dma_system_hwmod,
3116	.slave		= &omap44xx_l3_main_2_hwmod,
3117	.clk		= "l3_div_ck",
3118	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3119};
3120
3121/* fdif -> l3_main_2 */
3122static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = {
3123	.master		= &omap44xx_fdif_hwmod,
3124	.slave		= &omap44xx_l3_main_2_hwmod,
3125	.clk		= "l3_div_ck",
3126	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3127};
3128
3129/* gpu -> l3_main_2 */
3130static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = {
3131	.master		= &omap44xx_gpu_hwmod,
3132	.slave		= &omap44xx_l3_main_2_hwmod,
3133	.clk		= "l3_div_ck",
3134	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3135};
3136
3137/* hsi -> l3_main_2 */
3138static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = {
3139	.master		= &omap44xx_hsi_hwmod,
3140	.slave		= &omap44xx_l3_main_2_hwmod,
3141	.clk		= "l3_div_ck",
3142	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3143};
3144
3145/* ipu -> l3_main_2 */
3146static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = {
3147	.master		= &omap44xx_ipu_hwmod,
3148	.slave		= &omap44xx_l3_main_2_hwmod,
3149	.clk		= "l3_div_ck",
3150	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3151};
3152
3153/* iss -> l3_main_2 */
3154static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
3155	.master		= &omap44xx_iss_hwmod,
3156	.slave		= &omap44xx_l3_main_2_hwmod,
3157	.clk		= "l3_div_ck",
3158	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3159};
3160
3161/* iva -> l3_main_2 */
3162static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = {
3163	.master		= &omap44xx_iva_hwmod,
3164	.slave		= &omap44xx_l3_main_2_hwmod,
3165	.clk		= "l3_div_ck",
3166	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3167};
3168
3169/* l3_main_1 -> l3_main_2 */
3170static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
3171	.master		= &omap44xx_l3_main_1_hwmod,
3172	.slave		= &omap44xx_l3_main_2_hwmod,
3173	.clk		= "l3_div_ck",
3174	.user		= OCP_USER_MPU,
3175};
3176
3177/* l4_cfg -> l3_main_2 */
3178static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
3179	.master		= &omap44xx_l4_cfg_hwmod,
3180	.slave		= &omap44xx_l3_main_2_hwmod,
3181	.clk		= "l4_div_ck",
3182	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3183};
3184
3185/* usb_host_fs -> l3_main_2 */
3186static struct omap_hwmod_ocp_if __maybe_unused omap44xx_usb_host_fs__l3_main_2 = {
3187	.master		= &omap44xx_usb_host_fs_hwmod,
3188	.slave		= &omap44xx_l3_main_2_hwmod,
3189	.clk		= "l3_div_ck",
3190	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3191};
3192
3193/* usb_host_hs -> l3_main_2 */
3194static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = {
3195	.master		= &omap44xx_usb_host_hs_hwmod,
3196	.slave		= &omap44xx_l3_main_2_hwmod,
3197	.clk		= "l3_div_ck",
3198	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3199};
3200
3201/* usb_otg_hs -> l3_main_2 */
3202static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = {
3203	.master		= &omap44xx_usb_otg_hs_hwmod,
3204	.slave		= &omap44xx_l3_main_2_hwmod,
3205	.clk		= "l3_div_ck",
3206	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3207};
3208
3209/* l3_main_1 -> l3_main_3 */
3210static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
3211	.master		= &omap44xx_l3_main_1_hwmod,
3212	.slave		= &omap44xx_l3_main_3_hwmod,
3213	.clk		= "l3_div_ck",
3214	.user		= OCP_USER_MPU,
3215};
3216
3217/* l3_main_2 -> l3_main_3 */
3218static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
3219	.master		= &omap44xx_l3_main_2_hwmod,
3220	.slave		= &omap44xx_l3_main_3_hwmod,
3221	.clk		= "l3_div_ck",
3222	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3223};
3224
3225/* l4_cfg -> l3_main_3 */
3226static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
3227	.master		= &omap44xx_l4_cfg_hwmod,
3228	.slave		= &omap44xx_l3_main_3_hwmod,
3229	.clk		= "l4_div_ck",
3230	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3231};
3232
3233/* aess -> l4_abe */
3234static struct omap_hwmod_ocp_if __maybe_unused omap44xx_aess__l4_abe = {
3235	.master		= &omap44xx_aess_hwmod,
3236	.slave		= &omap44xx_l4_abe_hwmod,
3237	.clk		= "ocp_abe_iclk",
3238	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3239};
3240
3241/* dsp -> l4_abe */
3242static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = {
3243	.master		= &omap44xx_dsp_hwmod,
3244	.slave		= &omap44xx_l4_abe_hwmod,
3245	.clk		= "ocp_abe_iclk",
3246	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3247};
3248
3249/* l3_main_1 -> l4_abe */
3250static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = {
3251	.master		= &omap44xx_l3_main_1_hwmod,
3252	.slave		= &omap44xx_l4_abe_hwmod,
3253	.clk		= "l3_div_ck",
3254	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3255};
3256
3257/* mpu -> l4_abe */
3258static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = {
3259	.master		= &omap44xx_mpu_hwmod,
3260	.slave		= &omap44xx_l4_abe_hwmod,
3261	.clk		= "ocp_abe_iclk",
3262	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3263};
3264
3265/* l3_main_1 -> l4_cfg */
3266static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
3267	.master		= &omap44xx_l3_main_1_hwmod,
3268	.slave		= &omap44xx_l4_cfg_hwmod,
3269	.clk		= "l3_div_ck",
3270	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3271};
3272
3273/* l3_main_2 -> l4_per */
3274static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
3275	.master		= &omap44xx_l3_main_2_hwmod,
3276	.slave		= &omap44xx_l4_per_hwmod,
3277	.clk		= "l3_div_ck",
3278	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3279};
3280
3281/* l4_cfg -> l4_wkup */
3282static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
3283	.master		= &omap44xx_l4_cfg_hwmod,
3284	.slave		= &omap44xx_l4_wkup_hwmod,
3285	.clk		= "l4_div_ck",
3286	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3287};
3288
3289/* mpu -> mpu_private */
3290static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
3291	.master		= &omap44xx_mpu_hwmod,
3292	.slave		= &omap44xx_mpu_private_hwmod,
3293	.clk		= "l3_div_ck",
3294	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3295};
3296
3297/* l4_cfg -> ocp_wp_noc */
3298static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
3299	.master		= &omap44xx_l4_cfg_hwmod,
3300	.slave		= &omap44xx_ocp_wp_noc_hwmod,
3301	.clk		= "l4_div_ck",
3302	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3303};
3304
3305/* l4_abe -> aess */
3306static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
3307	.master		= &omap44xx_l4_abe_hwmod,
3308	.slave		= &omap44xx_aess_hwmod,
3309	.clk		= "ocp_abe_iclk",
3310	.user		= OCP_USER_MPU,
3311};
3312
3313/* l4_abe -> aess (dma) */
3314static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess_dma = {
3315	.master		= &omap44xx_l4_abe_hwmod,
3316	.slave		= &omap44xx_aess_hwmod,
3317	.clk		= "ocp_abe_iclk",
3318	.user		= OCP_USER_SDMA,
3319};
3320
3321/* l3_main_2 -> c2c */
3322static struct omap_hwmod_ocp_if omap44xx_l3_main_2__c2c = {
3323	.master		= &omap44xx_l3_main_2_hwmod,
3324	.slave		= &omap44xx_c2c_hwmod,
3325	.clk		= "l3_div_ck",
3326	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3327};
3328
3329/* l4_wkup -> counter_32k */
3330static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
3331	.master		= &omap44xx_l4_wkup_hwmod,
3332	.slave		= &omap44xx_counter_32k_hwmod,
3333	.clk		= "l4_wkup_clk_mux_ck",
3334	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3335};
3336
3337/* l4_cfg -> ctrl_module_core */
3338static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
3339	.master		= &omap44xx_l4_cfg_hwmod,
3340	.slave		= &omap44xx_ctrl_module_core_hwmod,
3341	.clk		= "l4_div_ck",
3342	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3343};
3344
3345/* l4_cfg -> ctrl_module_pad_core */
3346static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
3347	.master		= &omap44xx_l4_cfg_hwmod,
3348	.slave		= &omap44xx_ctrl_module_pad_core_hwmod,
3349	.clk		= "l4_div_ck",
3350	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3351};
3352
3353/* l4_wkup -> ctrl_module_wkup */
3354static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
3355	.master		= &omap44xx_l4_wkup_hwmod,
3356	.slave		= &omap44xx_ctrl_module_wkup_hwmod,
3357	.clk		= "l4_wkup_clk_mux_ck",
3358	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3359};
3360
3361/* l4_wkup -> ctrl_module_pad_wkup */
3362static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
3363	.master		= &omap44xx_l4_wkup_hwmod,
3364	.slave		= &omap44xx_ctrl_module_pad_wkup_hwmod,
3365	.clk		= "l4_wkup_clk_mux_ck",
3366	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3367};
3368
3369/* l3_instr -> debugss */
3370static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
3371	.master		= &omap44xx_l3_instr_hwmod,
3372	.slave		= &omap44xx_debugss_hwmod,
3373	.clk		= "l3_div_ck",
3374	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3375};
3376
3377/* l4_cfg -> dma_system */
3378static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
3379	.master		= &omap44xx_l4_cfg_hwmod,
3380	.slave		= &omap44xx_dma_system_hwmod,
3381	.clk		= "l4_div_ck",
3382	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3383};
3384
3385/* l4_abe -> dmic */
3386static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
3387	.master		= &omap44xx_l4_abe_hwmod,
3388	.slave		= &omap44xx_dmic_hwmod,
3389	.clk		= "ocp_abe_iclk",
3390	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3391};
3392
3393/* dsp -> iva */
3394static struct omap_hwmod_ocp_if omap44xx_dsp__iva = {
3395	.master		= &omap44xx_dsp_hwmod,
3396	.slave		= &omap44xx_iva_hwmod,
3397	.clk		= "dpll_iva_m5x2_ck",
3398	.user		= OCP_USER_DSP,
3399};
3400
3401/* dsp -> sl2if */
3402static struct omap_hwmod_ocp_if __maybe_unused omap44xx_dsp__sl2if = {
3403	.master		= &omap44xx_dsp_hwmod,
3404	.slave		= &omap44xx_sl2if_hwmod,
3405	.clk		= "dpll_iva_m5x2_ck",
3406	.user		= OCP_USER_DSP,
3407};
3408
3409/* l4_cfg -> dsp */
3410static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = {
3411	.master		= &omap44xx_l4_cfg_hwmod,
3412	.slave		= &omap44xx_dsp_hwmod,
3413	.clk		= "l4_div_ck",
3414	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3415};
3416
3417/* l3_main_2 -> dss */
3418static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
3419	.master		= &omap44xx_l3_main_2_hwmod,
3420	.slave		= &omap44xx_dss_hwmod,
3421	.clk		= "l3_div_ck",
3422	.user		= OCP_USER_SDMA,
3423};
3424
3425/* l4_per -> dss */
3426static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
3427	.master		= &omap44xx_l4_per_hwmod,
3428	.slave		= &omap44xx_dss_hwmod,
3429	.clk		= "l4_div_ck",
3430	.user		= OCP_USER_MPU,
3431};
3432
3433/* l3_main_2 -> dss_dispc */
3434static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
3435	.master		= &omap44xx_l3_main_2_hwmod,
3436	.slave		= &omap44xx_dss_dispc_hwmod,
3437	.clk		= "l3_div_ck",
3438	.user		= OCP_USER_SDMA,
3439};
3440
3441/* l4_per -> dss_dispc */
3442static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
3443	.master		= &omap44xx_l4_per_hwmod,
3444	.slave		= &omap44xx_dss_dispc_hwmod,
3445	.clk		= "l4_div_ck",
3446	.user		= OCP_USER_MPU,
3447};
3448
3449/* l3_main_2 -> dss_dsi1 */
3450static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
3451	.master		= &omap44xx_l3_main_2_hwmod,
3452	.slave		= &omap44xx_dss_dsi1_hwmod,
3453	.clk		= "l3_div_ck",
3454	.user		= OCP_USER_SDMA,
3455};
3456
3457/* l4_per -> dss_dsi1 */
3458static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
3459	.master		= &omap44xx_l4_per_hwmod,
3460	.slave		= &omap44xx_dss_dsi1_hwmod,
3461	.clk		= "l4_div_ck",
3462	.user		= OCP_USER_MPU,
3463};
3464
3465/* l3_main_2 -> dss_dsi2 */
3466static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
3467	.master		= &omap44xx_l3_main_2_hwmod,
3468	.slave		= &omap44xx_dss_dsi2_hwmod,
3469	.clk		= "l3_div_ck",
3470	.user		= OCP_USER_SDMA,
3471};
3472
3473/* l4_per -> dss_dsi2 */
3474static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
3475	.master		= &omap44xx_l4_per_hwmod,
3476	.slave		= &omap44xx_dss_dsi2_hwmod,
3477	.clk		= "l4_div_ck",
3478	.user		= OCP_USER_MPU,
3479};
3480
3481/* l3_main_2 -> dss_hdmi */
3482static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
3483	.master		= &omap44xx_l3_main_2_hwmod,
3484	.slave		= &omap44xx_dss_hdmi_hwmod,
3485	.clk		= "l3_div_ck",
3486	.user		= OCP_USER_SDMA,
3487};
3488
3489/* l4_per -> dss_hdmi */
3490static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
3491	.master		= &omap44xx_l4_per_hwmod,
3492	.slave		= &omap44xx_dss_hdmi_hwmod,
3493	.clk		= "l4_div_ck",
3494	.user		= OCP_USER_MPU,
3495};
3496
3497/* l3_main_2 -> dss_rfbi */
3498static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
3499	.master		= &omap44xx_l3_main_2_hwmod,
3500	.slave		= &omap44xx_dss_rfbi_hwmod,
3501	.clk		= "l3_div_ck",
3502	.user		= OCP_USER_SDMA,
3503};
3504
3505/* l4_per -> dss_rfbi */
3506static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
3507	.master		= &omap44xx_l4_per_hwmod,
3508	.slave		= &omap44xx_dss_rfbi_hwmod,
3509	.clk		= "l4_div_ck",
3510	.user		= OCP_USER_MPU,
3511};
3512
3513/* l3_main_2 -> dss_venc */
3514static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
3515	.master		= &omap44xx_l3_main_2_hwmod,
3516	.slave		= &omap44xx_dss_venc_hwmod,
3517	.clk		= "l3_div_ck",
3518	.user		= OCP_USER_SDMA,
3519};
3520
3521/* l4_per -> dss_venc */
3522static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
3523	.master		= &omap44xx_l4_per_hwmod,
3524	.slave		= &omap44xx_dss_venc_hwmod,
3525	.clk		= "l4_div_ck",
3526	.user		= OCP_USER_MPU,
3527};
3528
3529/* l3_main_2 -> sham */
3530static struct omap_hwmod_ocp_if omap44xx_l3_main_2__sha0 = {
3531	.master		= &omap44xx_l3_main_2_hwmod,
3532	.slave		= &omap44xx_sha0_hwmod,
3533	.clk		= "l3_div_ck",
3534	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3535};
3536
3537/* l4_per -> elm */
3538static struct omap_hwmod_ocp_if omap44xx_l4_per__elm = {
3539	.master		= &omap44xx_l4_per_hwmod,
3540	.slave		= &omap44xx_elm_hwmod,
3541	.clk		= "l4_div_ck",
3542	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3543};
3544
3545/* l4_cfg -> fdif */
3546static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = {
3547	.master		= &omap44xx_l4_cfg_hwmod,
3548	.slave		= &omap44xx_fdif_hwmod,
3549	.clk		= "l4_div_ck",
3550	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3551};
3552
3553/* l4_wkup -> gpio1 */
3554static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
3555	.master		= &omap44xx_l4_wkup_hwmod,
3556	.slave		= &omap44xx_gpio1_hwmod,
3557	.clk		= "l4_wkup_clk_mux_ck",
3558	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3559};
3560
3561/* l4_per -> gpio2 */
3562static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
3563	.master		= &omap44xx_l4_per_hwmod,
3564	.slave		= &omap44xx_gpio2_hwmod,
3565	.clk		= "l4_div_ck",
3566	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3567};
3568
3569/* l4_per -> gpio3 */
3570static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
3571	.master		= &omap44xx_l4_per_hwmod,
3572	.slave		= &omap44xx_gpio3_hwmod,
3573	.clk		= "l4_div_ck",
3574	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3575};
3576
3577/* l4_per -> gpio4 */
3578static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
3579	.master		= &omap44xx_l4_per_hwmod,
3580	.slave		= &omap44xx_gpio4_hwmod,
3581	.clk		= "l4_div_ck",
3582	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3583};
3584
3585/* l4_per -> gpio5 */
3586static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
3587	.master		= &omap44xx_l4_per_hwmod,
3588	.slave		= &omap44xx_gpio5_hwmod,
3589	.clk		= "l4_div_ck",
3590	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3591};
3592
3593/* l4_per -> gpio6 */
3594static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
3595	.master		= &omap44xx_l4_per_hwmod,
3596	.slave		= &omap44xx_gpio6_hwmod,
3597	.clk		= "l4_div_ck",
3598	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3599};
3600
3601/* l3_main_2 -> gpmc */
3602static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = {
3603	.master		= &omap44xx_l3_main_2_hwmod,
3604	.slave		= &omap44xx_gpmc_hwmod,
3605	.clk		= "l3_div_ck",
3606	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3607};
3608
3609/* l3_main_2 -> gpu */
3610static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = {
3611	.master		= &omap44xx_l3_main_2_hwmod,
3612	.slave		= &omap44xx_gpu_hwmod,
3613	.clk		= "l3_div_ck",
3614	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3615};
3616
3617/* l4_per -> hdq1w */
3618static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = {
3619	.master		= &omap44xx_l4_per_hwmod,
3620	.slave		= &omap44xx_hdq1w_hwmod,
3621	.clk		= "l4_div_ck",
3622	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3623};
3624
3625/* l4_cfg -> hsi */
3626static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
3627	.master		= &omap44xx_l4_cfg_hwmod,
3628	.slave		= &omap44xx_hsi_hwmod,
3629	.clk		= "l4_div_ck",
3630	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3631};
3632
3633/* l4_per -> i2c1 */
3634static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
3635	.master		= &omap44xx_l4_per_hwmod,
3636	.slave		= &omap44xx_i2c1_hwmod,
3637	.clk		= "l4_div_ck",
3638	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3639};
3640
3641/* l4_per -> i2c2 */
3642static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
3643	.master		= &omap44xx_l4_per_hwmod,
3644	.slave		= &omap44xx_i2c2_hwmod,
3645	.clk		= "l4_div_ck",
3646	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3647};
3648
3649/* l4_per -> i2c3 */
3650static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
3651	.master		= &omap44xx_l4_per_hwmod,
3652	.slave		= &omap44xx_i2c3_hwmod,
3653	.clk		= "l4_div_ck",
3654	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3655};
3656
3657/* l4_per -> i2c4 */
3658static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
3659	.master		= &omap44xx_l4_per_hwmod,
3660	.slave		= &omap44xx_i2c4_hwmod,
3661	.clk		= "l4_div_ck",
3662	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3663};
3664
3665/* l3_main_2 -> ipu */
3666static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = {
3667	.master		= &omap44xx_l3_main_2_hwmod,
3668	.slave		= &omap44xx_ipu_hwmod,
3669	.clk		= "l3_div_ck",
3670	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3671};
3672
3673/* l3_main_2 -> iss */
3674static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
3675	.master		= &omap44xx_l3_main_2_hwmod,
3676	.slave		= &omap44xx_iss_hwmod,
3677	.clk		= "l3_div_ck",
3678	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3679};
3680
3681/* iva -> sl2if */
3682static struct omap_hwmod_ocp_if __maybe_unused omap44xx_iva__sl2if = {
3683	.master		= &omap44xx_iva_hwmod,
3684	.slave		= &omap44xx_sl2if_hwmod,
3685	.clk		= "dpll_iva_m5x2_ck",
3686	.user		= OCP_USER_IVA,
3687};
3688
3689/* l3_main_2 -> iva */
3690static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
3691	.master		= &omap44xx_l3_main_2_hwmod,
3692	.slave		= &omap44xx_iva_hwmod,
3693	.clk		= "l3_div_ck",
3694	.user		= OCP_USER_MPU,
3695};
3696
3697/* l4_wkup -> kbd */
3698static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
3699	.master		= &omap44xx_l4_wkup_hwmod,
3700	.slave		= &omap44xx_kbd_hwmod,
3701	.clk		= "l4_wkup_clk_mux_ck",
3702	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3703};
3704
3705/* l4_cfg -> mailbox */
3706static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
3707	.master		= &omap44xx_l4_cfg_hwmod,
3708	.slave		= &omap44xx_mailbox_hwmod,
3709	.clk		= "l4_div_ck",
3710	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3711};
3712
3713/* l4_abe -> mcasp */
3714static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp = {
3715	.master		= &omap44xx_l4_abe_hwmod,
3716	.slave		= &omap44xx_mcasp_hwmod,
3717	.clk		= "ocp_abe_iclk",
3718	.user		= OCP_USER_MPU,
3719};
3720
3721/* l4_abe -> mcasp (dma) */
3722static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcasp_dma = {
3723	.master		= &omap44xx_l4_abe_hwmod,
3724	.slave		= &omap44xx_mcasp_hwmod,
3725	.clk		= "ocp_abe_iclk",
3726	.user		= OCP_USER_SDMA,
3727};
3728
3729/* l4_abe -> mcbsp1 */
3730static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
3731	.master		= &omap44xx_l4_abe_hwmod,
3732	.slave		= &omap44xx_mcbsp1_hwmod,
3733	.clk		= "ocp_abe_iclk",
3734	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3735};
3736
3737/* l4_abe -> mcbsp2 */
3738static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
3739	.master		= &omap44xx_l4_abe_hwmod,
3740	.slave		= &omap44xx_mcbsp2_hwmod,
3741	.clk		= "ocp_abe_iclk",
3742	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3743};
3744
3745/* l4_abe -> mcbsp3 */
3746static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
3747	.master		= &omap44xx_l4_abe_hwmod,
3748	.slave		= &omap44xx_mcbsp3_hwmod,
3749	.clk		= "ocp_abe_iclk",
3750	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3751};
3752
3753/* l4_per -> mcbsp4 */
3754static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
3755	.master		= &omap44xx_l4_per_hwmod,
3756	.slave		= &omap44xx_mcbsp4_hwmod,
3757	.clk		= "l4_div_ck",
3758	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3759};
3760
3761/* l4_abe -> mcpdm */
3762static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
3763	.master		= &omap44xx_l4_abe_hwmod,
3764	.slave		= &omap44xx_mcpdm_hwmod,
3765	.clk		= "ocp_abe_iclk",
3766	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3767};
3768
3769/* l4_per -> mcspi1 */
3770static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
3771	.master		= &omap44xx_l4_per_hwmod,
3772	.slave		= &omap44xx_mcspi1_hwmod,
3773	.clk		= "l4_div_ck",
3774	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3775};
3776
3777/* l4_per -> mcspi2 */
3778static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
3779	.master		= &omap44xx_l4_per_hwmod,
3780	.slave		= &omap44xx_mcspi2_hwmod,
3781	.clk		= "l4_div_ck",
3782	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3783};
3784
3785/* l4_per -> mcspi3 */
3786static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
3787	.master		= &omap44xx_l4_per_hwmod,
3788	.slave		= &omap44xx_mcspi3_hwmod,
3789	.clk		= "l4_div_ck",
3790	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3791};
3792
3793/* l4_per -> mcspi4 */
3794static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
3795	.master		= &omap44xx_l4_per_hwmod,
3796	.slave		= &omap44xx_mcspi4_hwmod,
3797	.clk		= "l4_div_ck",
3798	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3799};
3800
3801/* l4_per -> mmc1 */
3802static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
3803	.master		= &omap44xx_l4_per_hwmod,
3804	.slave		= &omap44xx_mmc1_hwmod,
3805	.clk		= "l4_div_ck",
3806	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3807};
3808
3809/* l4_per -> mmc2 */
3810static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
3811	.master		= &omap44xx_l4_per_hwmod,
3812	.slave		= &omap44xx_mmc2_hwmod,
3813	.clk		= "l4_div_ck",
3814	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3815};
3816
3817/* l4_per -> mmc3 */
3818static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
3819	.master		= &omap44xx_l4_per_hwmod,
3820	.slave		= &omap44xx_mmc3_hwmod,
3821	.clk		= "l4_div_ck",
3822	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3823};
3824
3825/* l4_per -> mmc4 */
3826static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
3827	.master		= &omap44xx_l4_per_hwmod,
3828	.slave		= &omap44xx_mmc4_hwmod,
3829	.clk		= "l4_div_ck",
3830	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3831};
3832
3833/* l4_per -> mmc5 */
3834static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
3835	.master		= &omap44xx_l4_per_hwmod,
3836	.slave		= &omap44xx_mmc5_hwmod,
3837	.clk		= "l4_div_ck",
3838	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3839};
3840
3841/* l3_main_2 -> ocmc_ram */
3842static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
3843	.master		= &omap44xx_l3_main_2_hwmod,
3844	.slave		= &omap44xx_ocmc_ram_hwmod,
3845	.clk		= "l3_div_ck",
3846	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3847};
3848
3849/* l4_cfg -> ocp2scp_usb_phy */
3850static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
3851	.master		= &omap44xx_l4_cfg_hwmod,
3852	.slave		= &omap44xx_ocp2scp_usb_phy_hwmod,
3853	.clk		= "l4_div_ck",
3854	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3855};
3856
3857/* mpu_private -> prcm_mpu */
3858static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
3859	.master		= &omap44xx_mpu_private_hwmod,
3860	.slave		= &omap44xx_prcm_mpu_hwmod,
3861	.clk		= "l3_div_ck",
3862	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3863};
3864
3865/* l4_wkup -> cm_core_aon */
3866static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
3867	.master		= &omap44xx_l4_wkup_hwmod,
3868	.slave		= &omap44xx_cm_core_aon_hwmod,
3869	.clk		= "l4_wkup_clk_mux_ck",
3870	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3871};
3872
3873/* l4_cfg -> cm_core */
3874static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
3875	.master		= &omap44xx_l4_cfg_hwmod,
3876	.slave		= &omap44xx_cm_core_hwmod,
3877	.clk		= "l4_div_ck",
3878	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3879};
3880
3881/* l4_wkup -> prm */
3882static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
3883	.master		= &omap44xx_l4_wkup_hwmod,
3884	.slave		= &omap44xx_prm_hwmod,
3885	.clk		= "l4_wkup_clk_mux_ck",
3886	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3887};
3888
3889/* l4_wkup -> scrm */
3890static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
3891	.master		= &omap44xx_l4_wkup_hwmod,
3892	.slave		= &omap44xx_scrm_hwmod,
3893	.clk		= "l4_wkup_clk_mux_ck",
3894	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3895};
3896
3897/* l3_main_2 -> sl2if */
3898static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
3899	.master		= &omap44xx_l3_main_2_hwmod,
3900	.slave		= &omap44xx_sl2if_hwmod,
3901	.clk		= "l3_div_ck",
3902	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3903};
3904
3905/* l4_abe -> slimbus1 */
3906static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1 = {
3907	.master		= &omap44xx_l4_abe_hwmod,
3908	.slave		= &omap44xx_slimbus1_hwmod,
3909	.clk		= "ocp_abe_iclk",
3910	.user		= OCP_USER_MPU,
3911};
3912
3913/* l4_abe -> slimbus1 (dma) */
3914static struct omap_hwmod_ocp_if omap44xx_l4_abe__slimbus1_dma = {
3915	.master		= &omap44xx_l4_abe_hwmod,
3916	.slave		= &omap44xx_slimbus1_hwmod,
3917	.clk		= "ocp_abe_iclk",
3918	.user		= OCP_USER_SDMA,
3919};
3920
3921/* l4_per -> slimbus2 */
3922static struct omap_hwmod_ocp_if omap44xx_l4_per__slimbus2 = {
3923	.master		= &omap44xx_l4_per_hwmod,
3924	.slave		= &omap44xx_slimbus2_hwmod,
3925	.clk		= "l4_div_ck",
3926	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3927};
3928
3929/* l4_cfg -> smartreflex_core */
3930static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
3931	.master		= &omap44xx_l4_cfg_hwmod,
3932	.slave		= &omap44xx_smartreflex_core_hwmod,
3933	.clk		= "l4_div_ck",
3934	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3935};
3936
3937/* l4_cfg -> smartreflex_iva */
3938static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
3939	.master		= &omap44xx_l4_cfg_hwmod,
3940	.slave		= &omap44xx_smartreflex_iva_hwmod,
3941	.clk		= "l4_div_ck",
3942	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3943};
3944
3945/* l4_cfg -> smartreflex_mpu */
3946static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
3947	.master		= &omap44xx_l4_cfg_hwmod,
3948	.slave		= &omap44xx_smartreflex_mpu_hwmod,
3949	.clk		= "l4_div_ck",
3950	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3951};
3952
3953/* l4_cfg -> spinlock */
3954static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
3955	.master		= &omap44xx_l4_cfg_hwmod,
3956	.slave		= &omap44xx_spinlock_hwmod,
3957	.clk		= "l4_div_ck",
3958	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3959};
3960
3961/* l4_wkup -> timer1 */
3962static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
3963	.master		= &omap44xx_l4_wkup_hwmod,
3964	.slave		= &omap44xx_timer1_hwmod,
3965	.clk		= "l4_wkup_clk_mux_ck",
3966	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3967};
3968
3969/* l4_per -> timer2 */
3970static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
3971	.master		= &omap44xx_l4_per_hwmod,
3972	.slave		= &omap44xx_timer2_hwmod,
3973	.clk		= "l4_div_ck",
3974	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3975};
3976
3977/* l4_per -> timer3 */
3978static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
3979	.master		= &omap44xx_l4_per_hwmod,
3980	.slave		= &omap44xx_timer3_hwmod,
3981	.clk		= "l4_div_ck",
3982	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3983};
3984
3985/* l4_per -> timer4 */
3986static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
3987	.master		= &omap44xx_l4_per_hwmod,
3988	.slave		= &omap44xx_timer4_hwmod,
3989	.clk		= "l4_div_ck",
3990	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3991};
3992
3993/* l4_abe -> timer5 */
3994static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
3995	.master		= &omap44xx_l4_abe_hwmod,
3996	.slave		= &omap44xx_timer5_hwmod,
3997	.clk		= "ocp_abe_iclk",
3998	.user		= OCP_USER_MPU | OCP_USER_SDMA,
3999};
4000
4001/* l4_abe -> timer6 */
4002static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
4003	.master		= &omap44xx_l4_abe_hwmod,
4004	.slave		= &omap44xx_timer6_hwmod,
4005	.clk		= "ocp_abe_iclk",
4006	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4007};
4008
4009/* l4_abe -> timer7 */
4010static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
4011	.master		= &omap44xx_l4_abe_hwmod,
4012	.slave		= &omap44xx_timer7_hwmod,
4013	.clk		= "ocp_abe_iclk",
4014	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4015};
4016
4017/* l4_abe -> timer8 */
4018static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
4019	.master		= &omap44xx_l4_abe_hwmod,
4020	.slave		= &omap44xx_timer8_hwmod,
4021	.clk		= "ocp_abe_iclk",
4022	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4023};
4024
4025/* l4_per -> timer9 */
4026static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
4027	.master		= &omap44xx_l4_per_hwmod,
4028	.slave		= &omap44xx_timer9_hwmod,
4029	.clk		= "l4_div_ck",
4030	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4031};
4032
4033/* l4_per -> timer10 */
4034static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
4035	.master		= &omap44xx_l4_per_hwmod,
4036	.slave		= &omap44xx_timer10_hwmod,
4037	.clk		= "l4_div_ck",
4038	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4039};
4040
4041/* l4_per -> timer11 */
4042static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
4043	.master		= &omap44xx_l4_per_hwmod,
4044	.slave		= &omap44xx_timer11_hwmod,
4045	.clk		= "l4_div_ck",
4046	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4047};
4048
4049/* l4_per -> uart1 */
4050static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
4051	.master		= &omap44xx_l4_per_hwmod,
4052	.slave		= &omap44xx_uart1_hwmod,
4053	.clk		= "l4_div_ck",
4054	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4055};
4056
4057/* l4_per -> uart2 */
4058static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
4059	.master		= &omap44xx_l4_per_hwmod,
4060	.slave		= &omap44xx_uart2_hwmod,
4061	.clk		= "l4_div_ck",
4062	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4063};
4064
4065/* l4_per -> uart3 */
4066static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
4067	.master		= &omap44xx_l4_per_hwmod,
4068	.slave		= &omap44xx_uart3_hwmod,
4069	.clk		= "l4_div_ck",
4070	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4071};
4072
4073/* l4_per -> uart4 */
4074static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
4075	.master		= &omap44xx_l4_per_hwmod,
4076	.slave		= &omap44xx_uart4_hwmod,
4077	.clk		= "l4_div_ck",
4078	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4079};
4080
4081/* l4_cfg -> usb_host_fs */
4082static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_cfg__usb_host_fs = {
4083	.master		= &omap44xx_l4_cfg_hwmod,
4084	.slave		= &omap44xx_usb_host_fs_hwmod,
4085	.clk		= "l4_div_ck",
4086	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4087};
4088
4089/* l4_cfg -> usb_host_hs */
4090static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
4091	.master		= &omap44xx_l4_cfg_hwmod,
4092	.slave		= &omap44xx_usb_host_hs_hwmod,
4093	.clk		= "l4_div_ck",
4094	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4095};
4096
4097/* l4_cfg -> usb_otg_hs */
4098static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
4099	.master		= &omap44xx_l4_cfg_hwmod,
4100	.slave		= &omap44xx_usb_otg_hs_hwmod,
4101	.clk		= "l4_div_ck",
4102	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4103};
4104
4105/* l4_cfg -> usb_tll_hs */
4106static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = {
4107	.master		= &omap44xx_l4_cfg_hwmod,
4108	.slave		= &omap44xx_usb_tll_hs_hwmod,
4109	.clk		= "l4_div_ck",
4110	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4111};
4112
4113/* l4_wkup -> wd_timer2 */
4114static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
4115	.master		= &omap44xx_l4_wkup_hwmod,
4116	.slave		= &omap44xx_wd_timer2_hwmod,
4117	.clk		= "l4_wkup_clk_mux_ck",
4118	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4119};
4120
4121/* l4_abe -> wd_timer3 */
4122static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
4123	.master		= &omap44xx_l4_abe_hwmod,
4124	.slave		= &omap44xx_wd_timer3_hwmod,
4125	.clk		= "ocp_abe_iclk",
4126	.user		= OCP_USER_MPU,
4127};
4128
4129/* l4_abe -> wd_timer3 (dma) */
4130static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
4131	.master		= &omap44xx_l4_abe_hwmod,
4132	.slave		= &omap44xx_wd_timer3_hwmod,
4133	.clk		= "ocp_abe_iclk",
4134	.user		= OCP_USER_SDMA,
4135};
4136
4137/* mpu -> emif1 */
4138static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
4139	.master		= &omap44xx_mpu_hwmod,
4140	.slave		= &omap44xx_emif1_hwmod,
4141	.clk		= "l3_div_ck",
4142	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4143};
4144
4145/* mpu -> emif2 */
4146static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
4147	.master		= &omap44xx_mpu_hwmod,
4148	.slave		= &omap44xx_emif2_hwmod,
4149	.clk		= "l3_div_ck",
4150	.user		= OCP_USER_MPU | OCP_USER_SDMA,
4151};
4152
4153static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
4154	&omap44xx_l3_main_1__dmm,
4155	&omap44xx_mpu__dmm,
4156	&omap44xx_iva__l3_instr,
4157	&omap44xx_l3_main_3__l3_instr,
4158	&omap44xx_ocp_wp_noc__l3_instr,
4159	&omap44xx_dsp__l3_main_1,
4160	&omap44xx_dss__l3_main_1,
4161	&omap44xx_l3_main_2__l3_main_1,
4162	&omap44xx_l4_cfg__l3_main_1,
4163	&omap44xx_mmc1__l3_main_1,
4164	&omap44xx_mmc2__l3_main_1,
4165	&omap44xx_mpu__l3_main_1,
4166	&omap44xx_debugss__l3_main_2,
4167	&omap44xx_dma_system__l3_main_2,
4168	&omap44xx_fdif__l3_main_2,
4169	&omap44xx_gpu__l3_main_2,
4170	&omap44xx_hsi__l3_main_2,
4171	&omap44xx_ipu__l3_main_2,
4172	&omap44xx_iss__l3_main_2,
4173	&omap44xx_iva__l3_main_2,
4174	&omap44xx_l3_main_1__l3_main_2,
4175	&omap44xx_l4_cfg__l3_main_2,
4176	/* &omap44xx_usb_host_fs__l3_main_2, */
4177	&omap44xx_usb_host_hs__l3_main_2,
4178	&omap44xx_usb_otg_hs__l3_main_2,
4179	&omap44xx_l3_main_1__l3_main_3,
4180	&omap44xx_l3_main_2__l3_main_3,
4181	&omap44xx_l4_cfg__l3_main_3,
4182	&omap44xx_aess__l4_abe,
4183	&omap44xx_dsp__l4_abe,
4184	&omap44xx_l3_main_1__l4_abe,
4185	&omap44xx_mpu__l4_abe,
4186	&omap44xx_l3_main_1__l4_cfg,
4187	&omap44xx_l3_main_2__l4_per,
4188	&omap44xx_l4_cfg__l4_wkup,
4189	&omap44xx_mpu__mpu_private,
4190	&omap44xx_l4_cfg__ocp_wp_noc,
4191	&omap44xx_l4_abe__aess,
4192	&omap44xx_l4_abe__aess_dma,
4193	&omap44xx_l3_main_2__c2c,
4194	&omap44xx_l4_wkup__counter_32k,
4195	&omap44xx_l4_cfg__ctrl_module_core,
4196	&omap44xx_l4_cfg__ctrl_module_pad_core,
4197	&omap44xx_l4_wkup__ctrl_module_wkup,
4198	&omap44xx_l4_wkup__ctrl_module_pad_wkup,
4199	&omap44xx_l3_instr__debugss,
4200	&omap44xx_l4_cfg__dma_system,
4201	&omap44xx_l4_abe__dmic,
4202	&omap44xx_dsp__iva,
4203	/* &omap44xx_dsp__sl2if, */
4204	&omap44xx_l4_cfg__dsp,
4205	&omap44xx_l3_main_2__dss,
4206	&omap44xx_l4_per__dss,
4207	&omap44xx_l3_main_2__dss_dispc,
4208	&omap44xx_l4_per__dss_dispc,
4209	&omap44xx_l3_main_2__dss_dsi1,
4210	&omap44xx_l4_per__dss_dsi1,
4211	&omap44xx_l3_main_2__dss_dsi2,
4212	&omap44xx_l4_per__dss_dsi2,
4213	&omap44xx_l3_main_2__dss_hdmi,
4214	&omap44xx_l4_per__dss_hdmi,
4215	&omap44xx_l3_main_2__dss_rfbi,
4216	&omap44xx_l4_per__dss_rfbi,
4217	&omap44xx_l3_main_2__dss_venc,
4218	&omap44xx_l4_per__dss_venc,
4219	&omap44xx_l4_per__elm,
4220	&omap44xx_l4_cfg__fdif,
4221	&omap44xx_l4_wkup__gpio1,
4222	&omap44xx_l4_per__gpio2,
4223	&omap44xx_l4_per__gpio3,
4224	&omap44xx_l4_per__gpio4,
4225	&omap44xx_l4_per__gpio5,
4226	&omap44xx_l4_per__gpio6,
4227	&omap44xx_l3_main_2__gpmc,
4228	&omap44xx_l3_main_2__gpu,
4229	&omap44xx_l4_per__hdq1w,
4230	&omap44xx_l4_cfg__hsi,
4231	&omap44xx_l4_per__i2c1,
4232	&omap44xx_l4_per__i2c2,
4233	&omap44xx_l4_per__i2c3,
4234	&omap44xx_l4_per__i2c4,
4235	&omap44xx_l3_main_2__ipu,
4236	&omap44xx_l3_main_2__iss,
4237	/* &omap44xx_iva__sl2if, */
4238	&omap44xx_l3_main_2__iva,
4239	&omap44xx_l4_wkup__kbd,
4240	&omap44xx_l4_cfg__mailbox,
4241	&omap44xx_l4_abe__mcasp,
4242	&omap44xx_l4_abe__mcasp_dma,
4243	&omap44xx_l4_abe__mcbsp1,
4244	&omap44xx_l4_abe__mcbsp2,
4245	&omap44xx_l4_abe__mcbsp3,
4246	&omap44xx_l4_per__mcbsp4,
4247	&omap44xx_l4_abe__mcpdm,
4248	&omap44xx_l4_per__mcspi1,
4249	&omap44xx_l4_per__mcspi2,
4250	&omap44xx_l4_per__mcspi3,
4251	&omap44xx_l4_per__mcspi4,
4252	&omap44xx_l4_per__mmc1,
4253	&omap44xx_l4_per__mmc2,
4254	&omap44xx_l4_per__mmc3,
4255	&omap44xx_l4_per__mmc4,
4256	&omap44xx_l4_per__mmc5,
4257	&omap44xx_l3_main_2__mmu_ipu,
4258	&omap44xx_l4_cfg__mmu_dsp,
4259	&omap44xx_l3_main_2__ocmc_ram,
4260	&omap44xx_l4_cfg__ocp2scp_usb_phy,
4261	&omap44xx_mpu_private__prcm_mpu,
4262	&omap44xx_l4_wkup__cm_core_aon,
4263	&omap44xx_l4_cfg__cm_core,
4264	&omap44xx_l4_wkup__prm,
4265	&omap44xx_l4_wkup__scrm,
4266	/* &omap44xx_l3_main_2__sl2if, */
4267	&omap44xx_l4_abe__slimbus1,
4268	&omap44xx_l4_abe__slimbus1_dma,
4269	&omap44xx_l4_per__slimbus2,
4270	&omap44xx_l4_cfg__smartreflex_core,
4271	&omap44xx_l4_cfg__smartreflex_iva,
4272	&omap44xx_l4_cfg__smartreflex_mpu,
4273	&omap44xx_l4_cfg__spinlock,
4274	&omap44xx_l4_wkup__timer1,
4275	&omap44xx_l4_per__timer2,
4276	&omap44xx_l4_per__timer3,
4277	&omap44xx_l4_per__timer4,
4278	&omap44xx_l4_abe__timer5,
4279	&omap44xx_l4_abe__timer6,
4280	&omap44xx_l4_abe__timer7,
4281	&omap44xx_l4_abe__timer8,
4282	&omap44xx_l4_per__timer9,
4283	&omap44xx_l4_per__timer10,
4284	&omap44xx_l4_per__timer11,
4285	&omap44xx_l4_per__uart1,
4286	&omap44xx_l4_per__uart2,
4287	&omap44xx_l4_per__uart3,
4288	&omap44xx_l4_per__uart4,
4289	/* &omap44xx_l4_cfg__usb_host_fs, */
4290	&omap44xx_l4_cfg__usb_host_hs,
4291	&omap44xx_l4_cfg__usb_otg_hs,
4292	&omap44xx_l4_cfg__usb_tll_hs,
4293	&omap44xx_l4_wkup__wd_timer2,
4294	&omap44xx_l4_abe__wd_timer3,
4295	&omap44xx_l4_abe__wd_timer3_dma,
4296	&omap44xx_mpu__emif1,
4297	&omap44xx_mpu__emif2,
4298	&omap44xx_l3_main_2__aes1,
4299	&omap44xx_l3_main_2__aes2,
4300	&omap44xx_l3_main_2__des,
4301	&omap44xx_l3_main_2__sha0,
4302	NULL,
4303};
4304
4305int __init omap44xx_hwmod_init(void)
4306{
4307	omap_hwmod_init();
4308	return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
4309}
4310