1// SPDX-License-Identifier: GPL-2.0
  2#include <linux/module.h>
  3#include <linux/kernel.h>
  4#include <linux/init.h>
  5#include <linux/list.h>
  6#include <linux/io.h>
  7#include <linux/clk.h>
  8#include <linux/clk/mmp.h>
  9
 10#include "addr-map.h"
 11
 12#include "common.h"
 13#include "clock.h"
 14
 15/*
 16 * APB Clock register offsets for MMP2
 17 */
 18#define APBC_RTC	APBC_REG(0x000)
 19#define APBC_TWSI1	APBC_REG(0x004)
 20#define APBC_TWSI2	APBC_REG(0x008)
 21#define APBC_TWSI3	APBC_REG(0x00c)
 22#define APBC_TWSI4	APBC_REG(0x010)
 23#define APBC_KPC	APBC_REG(0x018)
 24#define APBC_UART1	APBC_REG(0x02c)
 25#define APBC_UART2	APBC_REG(0x030)
 26#define APBC_UART3	APBC_REG(0x034)
 27#define APBC_GPIO	APBC_REG(0x038)
 28#define APBC_PWM0	APBC_REG(0x03c)
 29#define APBC_PWM1	APBC_REG(0x040)
 30#define APBC_PWM2	APBC_REG(0x044)
 31#define APBC_PWM3	APBC_REG(0x048)
 32#define APBC_SSP0	APBC_REG(0x04c)
 33#define APBC_SSP1	APBC_REG(0x050)
 34#define APBC_SSP2	APBC_REG(0x054)
 35#define APBC_SSP3	APBC_REG(0x058)
 36#define APBC_SSP4	APBC_REG(0x05c)
 37#define APBC_SSP5	APBC_REG(0x060)
 38#define APBC_TWSI5	APBC_REG(0x07c)
 39#define APBC_TWSI6	APBC_REG(0x080)
 40#define APBC_UART4	APBC_REG(0x088)
 41
 42#define APMU_USB	APMU_REG(0x05c)
 43#define APMU_NAND	APMU_REG(0x060)
 44#define APMU_SDH0	APMU_REG(0x054)
 45#define APMU_SDH1	APMU_REG(0x058)
 46#define APMU_SDH2	APMU_REG(0x0e8)
 47#define APMU_SDH3	APMU_REG(0x0ec)
 48
 49static void sdhc_clk_enable(struct clk *clk)
 50{
 51	uint32_t clk_rst;
 52
 53	clk_rst  =  __raw_readl(clk->clk_rst);
 54	clk_rst |= clk->enable_val;
 55	__raw_writel(clk_rst, clk->clk_rst);
 56}
 57
 58static void sdhc_clk_disable(struct clk *clk)
 59{
 60	uint32_t clk_rst;
 61
 62	clk_rst  =  __raw_readl(clk->clk_rst);
 63	clk_rst &= ~clk->enable_val;
 64	__raw_writel(clk_rst, clk->clk_rst);
 65}
 66
 67struct clkops sdhc_clk_ops = {
 68	.enable		= sdhc_clk_enable,
 69	.disable	= sdhc_clk_disable,
 70};
 71
 72/* APB peripheral clocks */
 73static APBC_CLK(uart1, UART1, 1, 26000000);
 74static APBC_CLK(uart2, UART2, 1, 26000000);
 75static APBC_CLK(uart3, UART3, 1, 26000000);
 76static APBC_CLK(uart4, UART4, 1, 26000000);
 77static APBC_CLK(twsi1, TWSI1, 0, 26000000);
 78static APBC_CLK(twsi2, TWSI2, 0, 26000000);
 79static APBC_CLK(twsi3, TWSI3, 0, 26000000);
 80static APBC_CLK(twsi4, TWSI4, 0, 26000000);
 81static APBC_CLK(twsi5, TWSI5, 0, 26000000);
 82static APBC_CLK(twsi6, TWSI6, 0, 26000000);
 83static APBC_CLK(gpio, GPIO, 0, 26000000);
 84
 85static APMU_CLK(nand, NAND, 0xbf, 100000000);
 86static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
 87static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
 88static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
 89static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
 90
 91static struct clk_lookup mmp2_clkregs[] = {
 92	INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
 93	INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
 94	INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
 95	INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
 96	INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
 97	INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
 98	INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
 99	INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
100	INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
101	INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
102	INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
103	INIT_CLKREG(&clk_gpio, "mmp2-gpio", NULL),
104	INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
105	INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
106	INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
107	INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
108};
109
110void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
111			  phys_addr_t apbc_phys)
112{
113	clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
114}