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1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
4 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License, version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
18 */
19
20#ifndef __ARM_KVM_H__
21#define __ARM_KVM_H__
22
23#include <linux/types.h>
24#include <linux/psci.h>
25#include <asm/ptrace.h>
26
27#define __KVM_HAVE_GUEST_DEBUG
28#define __KVM_HAVE_IRQ_LINE
29#define __KVM_HAVE_READONLY_MEM
30
31#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
32
33#define KVM_REG_SIZE(id) \
34 (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
35
36/* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
37#define KVM_ARM_SVC_sp svc_regs[0]
38#define KVM_ARM_SVC_lr svc_regs[1]
39#define KVM_ARM_SVC_spsr svc_regs[2]
40#define KVM_ARM_ABT_sp abt_regs[0]
41#define KVM_ARM_ABT_lr abt_regs[1]
42#define KVM_ARM_ABT_spsr abt_regs[2]
43#define KVM_ARM_UND_sp und_regs[0]
44#define KVM_ARM_UND_lr und_regs[1]
45#define KVM_ARM_UND_spsr und_regs[2]
46#define KVM_ARM_IRQ_sp irq_regs[0]
47#define KVM_ARM_IRQ_lr irq_regs[1]
48#define KVM_ARM_IRQ_spsr irq_regs[2]
49
50/* Valid only for fiq_regs in struct kvm_regs */
51#define KVM_ARM_FIQ_r8 fiq_regs[0]
52#define KVM_ARM_FIQ_r9 fiq_regs[1]
53#define KVM_ARM_FIQ_r10 fiq_regs[2]
54#define KVM_ARM_FIQ_fp fiq_regs[3]
55#define KVM_ARM_FIQ_ip fiq_regs[4]
56#define KVM_ARM_FIQ_sp fiq_regs[5]
57#define KVM_ARM_FIQ_lr fiq_regs[6]
58#define KVM_ARM_FIQ_spsr fiq_regs[7]
59
60struct kvm_regs {
61 struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
62 unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
63 unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
64 unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
65 unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
66 unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
67};
68
69/* Supported Processor Types */
70#define KVM_ARM_TARGET_CORTEX_A15 0
71#define KVM_ARM_TARGET_CORTEX_A7 1
72#define KVM_ARM_NUM_TARGETS 2
73
74/* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
75#define KVM_ARM_DEVICE_TYPE_SHIFT 0
76#define KVM_ARM_DEVICE_TYPE_MASK (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
77#define KVM_ARM_DEVICE_ID_SHIFT 16
78#define KVM_ARM_DEVICE_ID_MASK (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
79
80/* Supported device IDs */
81#define KVM_ARM_DEVICE_VGIC_V2 0
82
83/* Supported VGIC address types */
84#define KVM_VGIC_V2_ADDR_TYPE_DIST 0
85#define KVM_VGIC_V2_ADDR_TYPE_CPU 1
86
87#define KVM_VGIC_V2_DIST_SIZE 0x1000
88#define KVM_VGIC_V2_CPU_SIZE 0x2000
89
90/* Supported VGICv3 address types */
91#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
92#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
93#define KVM_VGIC_ITS_ADDR_TYPE 4
94
95#define KVM_VGIC_V3_DIST_SIZE SZ_64K
96#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
97#define KVM_VGIC_V3_ITS_SIZE (2 * SZ_64K)
98
99#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
100#define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */
101
102struct kvm_vcpu_init {
103 __u32 target;
104 __u32 features[7];
105};
106
107struct kvm_sregs {
108};
109
110struct kvm_fpu {
111};
112
113struct kvm_guest_debug_arch {
114};
115
116struct kvm_debug_exit_arch {
117};
118
119struct kvm_sync_regs {
120 /* Used with KVM_CAP_ARM_USER_IRQ */
121 __u64 device_irq_level;
122};
123
124struct kvm_arch_memory_slot {
125};
126
127/* If you need to interpret the index values, here is the key: */
128#define KVM_REG_ARM_COPROC_MASK 0x000000000FFF0000
129#define KVM_REG_ARM_COPROC_SHIFT 16
130#define KVM_REG_ARM_32_OPC2_MASK 0x0000000000000007
131#define KVM_REG_ARM_32_OPC2_SHIFT 0
132#define KVM_REG_ARM_OPC1_MASK 0x0000000000000078
133#define KVM_REG_ARM_OPC1_SHIFT 3
134#define KVM_REG_ARM_CRM_MASK 0x0000000000000780
135#define KVM_REG_ARM_CRM_SHIFT 7
136#define KVM_REG_ARM_32_CRN_MASK 0x0000000000007800
137#define KVM_REG_ARM_32_CRN_SHIFT 11
138/*
139 * For KVM currently all guest registers are nonsecure, but we reserve a bit
140 * in the encoding to distinguish secure from nonsecure for AArch32 system
141 * registers that are banked by security. This is 1 for the secure banked
142 * register, and 0 for the nonsecure banked register or if the register is
143 * not banked by security.
144 */
145#define KVM_REG_ARM_SECURE_MASK 0x0000000010000000
146#define KVM_REG_ARM_SECURE_SHIFT 28
147
148#define ARM_CP15_REG_SHIFT_MASK(x,n) \
149 (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
150
151#define __ARM_CP15_REG(op1,crn,crm,op2) \
152 (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
153 ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
154 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
155 ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
156 ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
157
158#define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
159
160#define __ARM_CP15_REG64(op1,crm) \
161 (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
162#define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
163
164/* PL1 Physical Timer Registers */
165#define KVM_REG_ARM_PTIMER_CTL ARM_CP15_REG32(0, 14, 2, 1)
166#define KVM_REG_ARM_PTIMER_CNT ARM_CP15_REG64(0, 14)
167#define KVM_REG_ARM_PTIMER_CVAL ARM_CP15_REG64(2, 14)
168
169/* Virtual Timer Registers */
170#define KVM_REG_ARM_TIMER_CTL ARM_CP15_REG32(0, 14, 3, 1)
171#define KVM_REG_ARM_TIMER_CNT ARM_CP15_REG64(1, 14)
172#define KVM_REG_ARM_TIMER_CVAL ARM_CP15_REG64(3, 14)
173
174/* Normal registers are mapped as coprocessor 16. */
175#define KVM_REG_ARM_CORE (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
176#define KVM_REG_ARM_CORE_REG(name) (offsetof(struct kvm_regs, name) / 4)
177
178/* Some registers need more space to represent values. */
179#define KVM_REG_ARM_DEMUX (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
180#define KVM_REG_ARM_DEMUX_ID_MASK 0x000000000000FF00
181#define KVM_REG_ARM_DEMUX_ID_SHIFT 8
182#define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
183#define KVM_REG_ARM_DEMUX_VAL_MASK 0x00000000000000FF
184#define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
185
186/* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
187#define KVM_REG_ARM_VFP (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
188#define KVM_REG_ARM_VFP_MASK 0x000000000000FFFF
189#define KVM_REG_ARM_VFP_BASE_REG 0x0
190#define KVM_REG_ARM_VFP_FPSID 0x1000
191#define KVM_REG_ARM_VFP_FPSCR 0x1001
192#define KVM_REG_ARM_VFP_MVFR1 0x1006
193#define KVM_REG_ARM_VFP_MVFR0 0x1007
194#define KVM_REG_ARM_VFP_FPEXC 0x1008
195#define KVM_REG_ARM_VFP_FPINST 0x1009
196#define KVM_REG_ARM_VFP_FPINST2 0x100A
197
198/* KVM-as-firmware specific pseudo-registers */
199#define KVM_REG_ARM_FW (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
200#define KVM_REG_ARM_FW_REG(r) (KVM_REG_ARM | KVM_REG_SIZE_U64 | \
201 KVM_REG_ARM_FW | ((r) & 0xffff))
202#define KVM_REG_ARM_PSCI_VERSION KVM_REG_ARM_FW_REG(0)
203
204/* Device Control API: ARM VGIC */
205#define KVM_DEV_ARM_VGIC_GRP_ADDR 0
206#define KVM_DEV_ARM_VGIC_GRP_DIST_REGS 1
207#define KVM_DEV_ARM_VGIC_GRP_CPU_REGS 2
208#define KVM_DEV_ARM_VGIC_CPUID_SHIFT 32
209#define KVM_DEV_ARM_VGIC_CPUID_MASK (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
210#define KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
211#define KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
212 (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
213#define KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
214#define KVM_DEV_ARM_VGIC_OFFSET_MASK (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
215#define KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
216#define KVM_DEV_ARM_VGIC_GRP_NR_IRQS 3
217#define KVM_DEV_ARM_VGIC_GRP_CTRL 4
218#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
219#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
220#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
221#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
222#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
223#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
224 (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
225#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
226#define VGIC_LEVEL_INFO_LINE_LEVEL 0
227
228/* Device Control API on vcpu fd */
229#define KVM_ARM_VCPU_PMU_V3_CTRL 0
230#define KVM_ARM_VCPU_PMU_V3_IRQ 0
231#define KVM_ARM_VCPU_PMU_V3_INIT 1
232#define KVM_ARM_VCPU_TIMER_CTRL 1
233#define KVM_ARM_VCPU_TIMER_IRQ_VTIMER 0
234#define KVM_ARM_VCPU_TIMER_IRQ_PTIMER 1
235
236#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
237#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
238#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
239#define KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES 3
240#define KVM_DEV_ARM_ITS_CTRL_RESET 4
241
242/* KVM_IRQ_LINE irq field index values */
243#define KVM_ARM_IRQ_TYPE_SHIFT 24
244#define KVM_ARM_IRQ_TYPE_MASK 0xff
245#define KVM_ARM_IRQ_VCPU_SHIFT 16
246#define KVM_ARM_IRQ_VCPU_MASK 0xff
247#define KVM_ARM_IRQ_NUM_SHIFT 0
248#define KVM_ARM_IRQ_NUM_MASK 0xffff
249
250/* irq_type field */
251#define KVM_ARM_IRQ_TYPE_CPU 0
252#define KVM_ARM_IRQ_TYPE_SPI 1
253#define KVM_ARM_IRQ_TYPE_PPI 2
254
255/* out-of-kernel GIC cpu interrupt injection irq_number field */
256#define KVM_ARM_IRQ_CPU_IRQ 0
257#define KVM_ARM_IRQ_CPU_FIQ 1
258
259/*
260 * This used to hold the highest supported SPI, but it is now obsolete
261 * and only here to provide source code level compatibility with older
262 * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
263 */
264#ifndef __KERNEL__
265#define KVM_ARM_IRQ_GIC_MAX 127
266#endif
267
268/* One single KVM irqchip, ie. the VGIC */
269#define KVM_NR_IRQCHIPS 1
270
271/* PSCI interface */
272#define KVM_PSCI_FN_BASE 0x95c1ba5e
273#define KVM_PSCI_FN(n) (KVM_PSCI_FN_BASE + (n))
274
275#define KVM_PSCI_FN_CPU_SUSPEND KVM_PSCI_FN(0)
276#define KVM_PSCI_FN_CPU_OFF KVM_PSCI_FN(1)
277#define KVM_PSCI_FN_CPU_ON KVM_PSCI_FN(2)
278#define KVM_PSCI_FN_MIGRATE KVM_PSCI_FN(3)
279
280#define KVM_PSCI_RET_SUCCESS PSCI_RET_SUCCESS
281#define KVM_PSCI_RET_NI PSCI_RET_NOT_SUPPORTED
282#define KVM_PSCI_RET_INVAL PSCI_RET_INVALID_PARAMS
283#define KVM_PSCI_RET_DENIED PSCI_RET_DENIED
284
285#endif /* __ARM_KVM_H__ */