1/*
  2 * Copyright (C) 2015 - ARM Ltd
  3 * Author: Marc Zyngier <marc.zyngier@arm.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 as
  7 * published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful,
 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12 * GNU General Public License for more details.
 13 *
 14 * You should have received a copy of the GNU General Public License
 15 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 16 */
 17
 18#ifndef __ARM_KVM_HYP_H__
 19#define __ARM_KVM_HYP_H__
 20
 21#include <linux/compiler.h>
 22#include <linux/kvm_host.h>
 23#include <asm/cp15.h>
 24#include <asm/vfp.h>
 25
 26#define __hyp_text __section(.hyp.text) notrace
 27
 28#define __ACCESS_VFP(CRn)			\
 29	"mrc", "mcr", __stringify(p10, 7, %0, CRn, cr0, 0), u32
 30
 31#define write_special(v, r)					\
 32	asm volatile("msr " __stringify(r) ", %0" : : "r" (v))
 33#define read_special(r) ({					\
 34	u32 __val;						\
 35	asm volatile("mrs %0, " __stringify(r) : "=r" (__val));	\
 36	__val;							\
 37})
 38
 39#define TTBR0		__ACCESS_CP15_64(0, c2)
 40#define TTBR1		__ACCESS_CP15_64(1, c2)
 41#define VTTBR		__ACCESS_CP15_64(6, c2)
 42#define PAR		__ACCESS_CP15_64(0, c7)
 43#define CNTV_CVAL	__ACCESS_CP15_64(3, c14)
 44#define CNTVOFF		__ACCESS_CP15_64(4, c14)
 45
 46#define MIDR		__ACCESS_CP15(c0, 0, c0, 0)
 47#define CSSELR		__ACCESS_CP15(c0, 2, c0, 0)
 48#define VPIDR		__ACCESS_CP15(c0, 4, c0, 0)
 49#define VMPIDR		__ACCESS_CP15(c0, 4, c0, 5)
 50#define SCTLR		__ACCESS_CP15(c1, 0, c0, 0)
 51#define CPACR		__ACCESS_CP15(c1, 0, c0, 2)
 52#define HCR		__ACCESS_CP15(c1, 4, c1, 0)
 53#define HDCR		__ACCESS_CP15(c1, 4, c1, 1)
 54#define HCPTR		__ACCESS_CP15(c1, 4, c1, 2)
 55#define HSTR		__ACCESS_CP15(c1, 4, c1, 3)
 56#define TTBCR		__ACCESS_CP15(c2, 0, c0, 2)
 57#define HTCR		__ACCESS_CP15(c2, 4, c0, 2)
 58#define VTCR		__ACCESS_CP15(c2, 4, c1, 2)
 59#define DACR		__ACCESS_CP15(c3, 0, c0, 0)
 60#define DFSR		__ACCESS_CP15(c5, 0, c0, 0)
 61#define IFSR		__ACCESS_CP15(c5, 0, c0, 1)
 62#define ADFSR		__ACCESS_CP15(c5, 0, c1, 0)
 63#define AIFSR		__ACCESS_CP15(c5, 0, c1, 1)
 64#define HSR		__ACCESS_CP15(c5, 4, c2, 0)
 65#define DFAR		__ACCESS_CP15(c6, 0, c0, 0)
 66#define IFAR		__ACCESS_CP15(c6, 0, c0, 2)
 67#define HDFAR		__ACCESS_CP15(c6, 4, c0, 0)
 68#define HIFAR		__ACCESS_CP15(c6, 4, c0, 2)
 69#define HPFAR		__ACCESS_CP15(c6, 4, c0, 4)
 70#define ICIALLUIS	__ACCESS_CP15(c7, 0, c1, 0)
 71#define BPIALLIS	__ACCESS_CP15(c7, 0, c1, 6)
 72#define ICIMVAU		__ACCESS_CP15(c7, 0, c5, 1)
 73#define ATS1CPR		__ACCESS_CP15(c7, 0, c8, 0)
 74#define TLBIALLIS	__ACCESS_CP15(c8, 0, c3, 0)
 75#define TLBIALL		__ACCESS_CP15(c8, 0, c7, 0)
 76#define TLBIALLNSNHIS	__ACCESS_CP15(c8, 4, c3, 4)
 77#define PRRR		__ACCESS_CP15(c10, 0, c2, 0)
 78#define NMRR		__ACCESS_CP15(c10, 0, c2, 1)
 79#define AMAIR0		__ACCESS_CP15(c10, 0, c3, 0)
 80#define AMAIR1		__ACCESS_CP15(c10, 0, c3, 1)
 81#define VBAR		__ACCESS_CP15(c12, 0, c0, 0)
 82#define CID		__ACCESS_CP15(c13, 0, c0, 1)
 83#define TID_URW		__ACCESS_CP15(c13, 0, c0, 2)
 84#define TID_URO		__ACCESS_CP15(c13, 0, c0, 3)
 85#define TID_PRIV	__ACCESS_CP15(c13, 0, c0, 4)
 86#define HTPIDR		__ACCESS_CP15(c13, 4, c0, 2)
 87#define CNTKCTL		__ACCESS_CP15(c14, 0, c1, 0)
 88#define CNTV_CTL	__ACCESS_CP15(c14, 0, c3, 1)
 89#define CNTHCTL		__ACCESS_CP15(c14, 4, c1, 0)
 90
 91#define VFP_FPEXC	__ACCESS_VFP(FPEXC)
 92
 93/* AArch64 compatibility macros, only for the timer so far */
 94#define read_sysreg_el0(r)		read_sysreg(r##_el0)
 95#define write_sysreg_el0(v, r)		write_sysreg(v, r##_el0)
 96
 97#define cntv_ctl_el0			CNTV_CTL
 98#define cntv_cval_el0			CNTV_CVAL
 99#define cntvoff_el2			CNTVOFF
100#define cnthctl_el2			CNTHCTL
101
102void __timer_enable_traps(struct kvm_vcpu *vcpu);
103void __timer_disable_traps(struct kvm_vcpu *vcpu);
104
105void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
106void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
107
108void __sysreg_save_state(struct kvm_cpu_context *ctxt);
109void __sysreg_restore_state(struct kvm_cpu_context *ctxt);
110
111void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
112void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
113void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu);
114void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu);
115void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu);
116void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu);
117
118asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp);
119asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp);
120static inline bool __vfp_enabled(void)
121{
122	return !(read_sysreg(HCPTR) & (HCPTR_TCP(11) | HCPTR_TCP(10)));
123}
124
125void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt);
126void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt);
127
128asmlinkage int __guest_enter(struct kvm_vcpu *vcpu,
129			     struct kvm_cpu_context *host);
130asmlinkage int __hyp_do_panic(const char *, int, u32);
131
132#endif /* __ARM_KVM_HYP_H__ */