1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Samsung's S3C64xx SoC series common device tree source
  4 *
  5 * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
  6 *
  7 * Samsung's S3C64xx SoC series device nodes are listed in this file.
  8 * Particular SoCs from S3C64xx series can include this file and provide
  9 * values for SoCs specfic bindings.
 10 *
 11 * Note: This file does not include device nodes for all the controllers in
 12 * S3C64xx SoCs. As device tree coverage for S3C64xx increases, additional
 13 * nodes can be added to this file.
 14 */
 15
 16#include "skeleton.dtsi"
 17#include <dt-bindings/clock/samsung,s3c64xx-clock.h>
 18
 19/ {
 20	aliases {
 21		i2c0 = &i2c0;
 22		pinctrl0 = &pinctrl0;
 23		serial0 = &uart0;
 24		serial1 = &uart1;
 25		serial2 = &uart2;
 26		serial3 = &uart3;
 27	};
 28
 29	cpus {
 30		#address-cells = <1>;
 31		#size-cells = <0>;
 32
 33		cpu@0 {
 34			device_type = "cpu";
 35			compatible = "arm,arm1176jzf-s", "arm,arm1176";
 36			reg = <0x0>;
 37		};
 38	};
 39
 40	soc: soc {
 41		compatible = "simple-bus";
 42		#address-cells = <1>;
 43		#size-cells = <1>;
 44		ranges;
 45
 46		vic0: interrupt-controller@71200000 {
 47			compatible = "arm,pl192-vic";
 48			interrupt-controller;
 49			reg = <0x71200000 0x1000>;
 50			#interrupt-cells = <1>;
 51		};
 52
 53		vic1: interrupt-controller@71300000 {
 54			compatible = "arm,pl192-vic";
 55			interrupt-controller;
 56			reg = <0x71300000 0x1000>;
 57			#interrupt-cells = <1>;
 58		};
 59
 60		sdhci0: sdhci@7c200000 {
 61			compatible = "samsung,s3c6410-sdhci";
 62			reg = <0x7c200000 0x100>;
 63			interrupt-parent = <&vic1>;
 64			interrupts = <24>;
 65			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
 66			clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>,
 67					<&clocks SCLK_MMC0>;
 68			status = "disabled";
 69		};
 70
 71		sdhci1: sdhci@7c300000 {
 72			compatible = "samsung,s3c6410-sdhci";
 73			reg = <0x7c300000 0x100>;
 74			interrupt-parent = <&vic1>;
 75			interrupts = <25>;
 76			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
 77			clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>,
 78					<&clocks SCLK_MMC1>;
 79			status = "disabled";
 80		};
 81
 82		sdhci2: sdhci@7c400000 {
 83			compatible = "samsung,s3c6410-sdhci";
 84			reg = <0x7c400000 0x100>;
 85			interrupt-parent = <&vic1>;
 86			interrupts = <17>;
 87			clock-names = "hsmmc", "mmc_busclk.0", "mmc_busclk.2";
 88			clocks = <&clocks HCLK_HSMMC2>, <&clocks HCLK_HSMMC2>,
 89					<&clocks SCLK_MMC2>;
 90			status = "disabled";
 91		};
 92
 93		watchdog: watchdog@7e004000 {
 94			compatible = "samsung,s3c6410-wdt";
 95			reg = <0x7e004000 0x1000>;
 96			interrupt-parent = <&vic0>;
 97			interrupts = <26>;
 98			clock-names = "watchdog";
 99			clocks = <&clocks PCLK_WDT>;
100		};
101
102		i2c0: i2c@7f004000 {
103			compatible = "samsung,s3c2440-i2c";
104			reg = <0x7f004000 0x1000>;
105			interrupt-parent = <&vic1>;
106			interrupts = <18>;
107			clock-names = "i2c";
108			clocks = <&clocks PCLK_IIC0>;
109			status = "disabled";
110			#address-cells = <1>;
111			#size-cells = <0>;
112		};
113
114		uart0: serial@7f005000 {
115			compatible = "samsung,s3c6400-uart";
116			reg = <0x7f005000 0x100>;
117			interrupt-parent = <&vic1>;
118			interrupts = <5>;
119			clock-names = "uart", "clk_uart_baud2",
120					"clk_uart_baud3";
121			clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
122					<&clocks SCLK_UART>;
123			status = "disabled";
124		};
125
126		uart1: serial@7f005400 {
127			compatible = "samsung,s3c6400-uart";
128			reg = <0x7f005400 0x100>;
129			interrupt-parent = <&vic1>;
130			interrupts = <6>;
131			clock-names = "uart", "clk_uart_baud2",
132					"clk_uart_baud3";
133			clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>,
134					<&clocks SCLK_UART>;
135			status = "disabled";
136		};
137
138		uart2: serial@7f005800 {
139			compatible = "samsung,s3c6400-uart";
140			reg = <0x7f005800 0x100>;
141			interrupt-parent = <&vic1>;
142			interrupts = <7>;
143			clock-names = "uart", "clk_uart_baud2",
144					"clk_uart_baud3";
145			clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>,
146					<&clocks SCLK_UART>;
147			status = "disabled";
148		};
149
150		uart3: serial@7f005c00 {
151			compatible = "samsung,s3c6400-uart";
152			reg = <0x7f005c00 0x100>;
153			interrupt-parent = <&vic1>;
154			interrupts = <8>;
155			clock-names = "uart", "clk_uart_baud2",
156					"clk_uart_baud3";
157			clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
158					<&clocks SCLK_UART>;
159			status = "disabled";
160		};
161
162		pwm: pwm@7f006000 {
163			compatible = "samsung,s3c6400-pwm";
164			reg = <0x7f006000 0x1000>;
165			interrupt-parent = <&vic0>;
166			interrupts = <23>, <24>, <25>, <27>, <28>;
167			clock-names = "timers";
168			clocks = <&clocks PCLK_PWM>;
169			samsung,pwm-outputs = <0>, <1>;
170			#pwm-cells = <3>;
171		};
172
173		pinctrl0: pinctrl@7f008000 {
174			compatible = "samsung,s3c64xx-pinctrl";
175			reg = <0x7f008000 0x1000>;
176			interrupt-parent = <&vic1>;
177			interrupts = <21>;
178
179			pctrl_int_map: pinctrl-interrupt-map {
180				interrupt-map = <0 &vic0 0>,
181						<1 &vic0 1>,
182						<2 &vic1 0>,
183						<3 &vic1 1>;
184				#address-cells = <0>;
185				#size-cells = <0>;
186				#interrupt-cells = <1>;
187			};
188
189			wakeup-interrupt-controller {
190				compatible = "samsung,s3c64xx-wakeup-eint";
191				interrupts = <0>, <1>, <2>, <3>;
192				interrupt-parent = <&pctrl_int_map>;
193			};
194		};
195	};
196};
197
198#include "s3c64xx-pinctrl.dtsi"