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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "skeleton.dtsi"
5#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10 model = "Qualcomm IPQ8064";
11 compatible = "qcom,ipq8064";
12 interrupt-parent = <&intc>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 qcom,acc = <&acc0>;
25 qcom,saw = <&saw0>;
26 };
27
28 cpu@1 {
29 compatible = "qcom,krait";
30 enable-method = "qcom,kpss-acc-v1";
31 device_type = "cpu";
32 reg = <1>;
33 next-level-cache = <&L2>;
34 qcom,acc = <&acc1>;
35 qcom,saw = <&saw1>;
36 };
37
38 L2: l2-cache {
39 compatible = "cache";
40 cache-level = <2>;
41 };
42 };
43
44 cpu-pmu {
45 compatible = "qcom,krait-pmu";
46 interrupts = <1 10 0x304>;
47 };
48
49 reserved-memory {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 nss@40000000 {
55 reg = <0x40000000 0x1000000>;
56 no-map;
57 };
58
59 smem@41000000 {
60 reg = <0x41000000 0x200000>;
61 no-map;
62 };
63 };
64
65 clocks {
66 cxo_board {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <25000000>;
70 };
71
72 pxo_board {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <25000000>;
76 };
77
78 sleep_clk: sleep_clk {
79 compatible = "fixed-clock";
80 clock-frequency = <32768>;
81 #clock-cells = <0>;
82 };
83 };
84
85 soc: soc {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 compatible = "simple-bus";
90
91 lpass@28100000 {
92 compatible = "qcom,lpass-cpu";
93 status = "disabled";
94 clocks = <&lcc AHBIX_CLK>,
95 <&lcc MI2S_OSR_CLK>,
96 <&lcc MI2S_BIT_CLK>;
97 clock-names = "ahbix-clk",
98 "mi2s-osr-clk",
99 "mi2s-bit-clk";
100 interrupts = <0 85 1>;
101 interrupt-names = "lpass-irq-lpaif";
102 reg = <0x28100000 0x10000>;
103 reg-names = "lpass-lpaif";
104 };
105
106 qcom_pinmux: pinmux@800000 {
107 compatible = "qcom,ipq8064-pinctrl";
108 reg = <0x800000 0x4000>;
109
110 gpio-controller;
111 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 interrupts = <0 16 0x4>;
115 };
116
117 intc: interrupt-controller@2000000 {
118 compatible = "qcom,msm-qgic2";
119 interrupt-controller;
120 #interrupt-cells = <3>;
121 reg = <0x02000000 0x1000>,
122 <0x02002000 0x1000>;
123 };
124
125 timer@200a000 {
126 compatible = "qcom,kpss-timer",
127 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
128 interrupts = <1 1 0x301>,
129 <1 2 0x301>,
130 <1 3 0x301>,
131 <1 4 0x301>,
132 <1 5 0x301>;
133 reg = <0x0200a000 0x100>;
134 clock-frequency = <25000000>,
135 <32768>;
136 clocks = <&sleep_clk>;
137 clock-names = "sleep";
138 cpu-offset = <0x80000>;
139 };
140
141 acc0: clock-controller@2088000 {
142 compatible = "qcom,kpss-acc-v1";
143 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
144 };
145
146 acc1: clock-controller@2098000 {
147 compatible = "qcom,kpss-acc-v1";
148 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
149 };
150
151 saw0: regulator@2089000 {
152 compatible = "qcom,saw2";
153 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
154 regulator;
155 };
156
157 saw1: regulator@2099000 {
158 compatible = "qcom,saw2";
159 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
160 regulator;
161 };
162
163 gsbi2: gsbi@12480000 {
164 compatible = "qcom,gsbi-v1.0.0";
165 cell-index = <2>;
166 reg = <0x12480000 0x100>;
167 clocks = <&gcc GSBI2_H_CLK>;
168 clock-names = "iface";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges;
172 status = "disabled";
173
174 syscon-tcsr = <&tcsr>;
175
176 serial@12490000 {
177 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
178 reg = <0x12490000 0x1000>,
179 <0x12480000 0x1000>;
180 interrupts = <0 195 0x0>;
181 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
182 clock-names = "core", "iface";
183 status = "disabled";
184 };
185
186 i2c@124a0000 {
187 compatible = "qcom,i2c-qup-v1.1.1";
188 reg = <0x124a0000 0x1000>;
189 interrupts = <0 196 0>;
190
191 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
192 clock-names = "core", "iface";
193 status = "disabled";
194
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
198
199 };
200
201 gsbi4: gsbi@16300000 {
202 compatible = "qcom,gsbi-v1.0.0";
203 cell-index = <4>;
204 reg = <0x16300000 0x100>;
205 clocks = <&gcc GSBI4_H_CLK>;
206 clock-names = "iface";
207 #address-cells = <1>;
208 #size-cells = <1>;
209 ranges;
210 status = "disabled";
211
212 syscon-tcsr = <&tcsr>;
213
214 gsbi4_serial: serial@16340000 {
215 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
216 reg = <0x16340000 0x1000>,
217 <0x16300000 0x1000>;
218 interrupts = <0 152 0x0>;
219 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
220 clock-names = "core", "iface";
221 status = "disabled";
222 };
223
224 i2c@16380000 {
225 compatible = "qcom,i2c-qup-v1.1.1";
226 reg = <0x16380000 0x1000>;
227 interrupts = <0 153 0>;
228
229 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
230 clock-names = "core", "iface";
231 status = "disabled";
232
233 #address-cells = <1>;
234 #size-cells = <0>;
235 };
236 };
237
238 gsbi5: gsbi@1a200000 {
239 compatible = "qcom,gsbi-v1.0.0";
240 cell-index = <5>;
241 reg = <0x1a200000 0x100>;
242 clocks = <&gcc GSBI5_H_CLK>;
243 clock-names = "iface";
244 #address-cells = <1>;
245 #size-cells = <1>;
246 ranges;
247 status = "disabled";
248
249 syscon-tcsr = <&tcsr>;
250
251 serial@1a240000 {
252 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
253 reg = <0x1a240000 0x1000>,
254 <0x1a200000 0x1000>;
255 interrupts = <0 154 0x0>;
256 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
257 clock-names = "core", "iface";
258 status = "disabled";
259 };
260
261 i2c@1a280000 {
262 compatible = "qcom,i2c-qup-v1.1.1";
263 reg = <0x1a280000 0x1000>;
264 interrupts = <0 155 0>;
265
266 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
267 clock-names = "core", "iface";
268 status = "disabled";
269
270 #address-cells = <1>;
271 #size-cells = <0>;
272 };
273
274 spi@1a280000 {
275 compatible = "qcom,spi-qup-v1.1.1";
276 reg = <0x1a280000 0x1000>;
277 interrupts = <0 155 0>;
278
279 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
280 clock-names = "core", "iface";
281 status = "disabled";
282
283 #address-cells = <1>;
284 #size-cells = <0>;
285 };
286 };
287
288 gsbi7: gsbi@16600000 {
289 status = "disabled";
290 compatible = "qcom,gsbi-v1.0.0";
291 cell-index = <7>;
292 reg = <0x16600000 0x100>;
293 clocks = <&gcc GSBI7_H_CLK>;
294 clock-names = "iface";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges;
298 syscon-tcsr = <&tcsr>;
299
300 gsbi7_serial: serial@16640000 {
301 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
302 reg = <0x16640000 0x1000>,
303 <0x16600000 0x1000>;
304 interrupts = <0 158 0x0>;
305 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
306 clock-names = "core", "iface";
307 status = "disabled";
308 };
309 };
310
311 sata_phy: sata-phy@1b400000 {
312 compatible = "qcom,ipq806x-sata-phy";
313 reg = <0x1b400000 0x200>;
314
315 clocks = <&gcc SATA_PHY_CFG_CLK>;
316 clock-names = "cfg";
317
318 #phy-cells = <0>;
319 status = "disabled";
320 };
321
322 sata@29000000 {
323 compatible = "qcom,ipq806x-ahci", "generic-ahci";
324 reg = <0x29000000 0x180>;
325
326 interrupts = <0 209 0x0>;
327
328 clocks = <&gcc SFAB_SATA_S_H_CLK>,
329 <&gcc SATA_H_CLK>,
330 <&gcc SATA_A_CLK>,
331 <&gcc SATA_RXOOB_CLK>,
332 <&gcc SATA_PMALIVE_CLK>;
333 clock-names = "slave_face", "iface", "core",
334 "rxoob", "pmalive";
335
336 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
337 assigned-clock-rates = <100000000>, <100000000>;
338
339 phys = <&sata_phy>;
340 phy-names = "sata-phy";
341 status = "disabled";
342 };
343
344 qcom,ssbi@500000 {
345 compatible = "qcom,ssbi";
346 reg = <0x00500000 0x1000>;
347 qcom,controller-type = "pmic-arbiter";
348 };
349
350 gcc: clock-controller@900000 {
351 compatible = "qcom,gcc-ipq8064";
352 reg = <0x00900000 0x4000>;
353 #clock-cells = <1>;
354 #reset-cells = <1>;
355 };
356
357 tcsr: syscon@1a400000 {
358 compatible = "qcom,tcsr-ipq8064", "syscon";
359 reg = <0x1a400000 0x100>;
360 };
361
362 lcc: clock-controller@28000000 {
363 compatible = "qcom,lcc-ipq8064";
364 reg = <0x28000000 0x1000>;
365 #clock-cells = <1>;
366 #reset-cells = <1>;
367 };
368
369 };
370};