1// SPDX-License-Identifier: GPL-2.0
  2/* The pxa3xx skeleton simply augments the 2xx version */
  3#include "pxa2xx.dtsi"
  4#include "dt-bindings/clock/pxa-clock.h"
  5
  6/ {
  7	model = "Marvell PXA27x familiy SoC";
  8	compatible = "marvell,pxa27x";
  9
 10	pxabus {
 11		pdma: dma-controller@40000000 {
 12			compatible = "marvell,pdma-1.0";
 13			reg = <0x40000000 0x10000>;
 14			interrupts = <25>;
 15			#dma-channels = <32>;
 16			#dma-cells = <2>;
 17			#dma-requests = <75>;
 18			status = "okay";
 19		};
 20
 21		pxairq: interrupt-controller@40d00000 {
 22			marvell,intc-priority;
 23			marvell,intc-nr-irqs = <34>;
 24		};
 25
 26		pinctrl: pinctrl@40e00000 {
 27			reg = <0x40e00054 0x20 0x40e0000c 0xc 0x40e0010c 4
 28			       0x40f00020 0x10>;
 29			compatible = "marvell,pxa27x-pinctrl";
 30		};
 31
 32		gpio: gpio@40e00000 {
 33			compatible = "intel,pxa27x-gpio";
 34			gpio-ranges = <&pinctrl 0 0 128>;
 35			clocks = <&clks CLK_NONE>;
 36		};
 37
 38		pxa27x_ohci: usb@4c000000 {
 39			compatible = "marvell,pxa-ohci";
 40			reg = <0x4c000000 0x10000>;
 41			interrupts = <3>;
 42			clocks = <&clks CLK_USBHOST>;
 43			status = "disabled";
 44		};
 45
 46		pwm0: pwm@40b00000 {
 47			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
 48			reg = <0x40b00000 0x10>;
 49			#pwm-cells = <1>;
 50			clocks = <&clks CLK_PWM0>;
 51		};
 52
 53		pwm1: pwm@40b00010 {
 54			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
 55			reg = <0x40b00010 0x10>;
 56			#pwm-cells = <1>;
 57			clocks = <&clks CLK_PWM1>;
 58		};
 59
 60		pwm2: pwm@40c00000 {
 61			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
 62			reg = <0x40c00000 0x10>;
 63			#pwm-cells = <1>;
 64			clocks = <&clks CLK_PWM0>;
 65		};
 66
 67		pwm3: pwm@40c00010 {
 68			compatible = "marvell,pxa270-pwm", "marvell,pxa250-pwm";
 69			reg = <0x40c00010 0x10>;
 70			#pwm-cells = <1>;
 71			clocks = <&clks CLK_PWM1>;
 72		};
 73
 74		pwri2c: i2c@40f000180 {
 75			compatible = "mrvl,pxa-i2c";
 76			reg = <0x40f00180 0x24>;
 77			interrupts = <6>;
 78			clocks = <&clks CLK_PWRI2C>;
 79			#address-cells = <0x1>;
 80			#size-cells = <0>;
 81			status = "disabled";
 82		};
 83
 84		pxa27x_udc: udc@40600000 {
 85			compatible = "marvell,pxa270-udc";
 86			reg = <0x40600000 0x10000>;
 87			interrupts = <11>;
 88			clocks = <&clks CLK_USB>;
 89			status = "disabled";
 90		};
 91
 92		keypad: keypad@41500000 {
 93			compatible = "marvell,pxa27x-keypad";
 94			reg = <0x41500000 0x4c>;
 95			interrupts = <4>;
 96			clocks = <&clks CLK_KEYPAD>;
 97			status = "disabled";
 98		};
 99
100		pxa_camera: imaging@50000000 {
101			compatible = "marvell,pxa270-qci";
102			reg = <0x50000000 0x1000>;
103			interrupts = <33>;
104			dmas = <&pdma 68 0	/* Y channel */
105				&pdma 69 0	/* U channel */
106				&pdma 70 0>;	/* V channel */
107			dma-names = "CI_Y", "CI_U", "CI_V";
108
109			clocks = <&clks CLK_CAMERA>;
110			clock-names = "ciclk";
111			clock-frequency = <5000000>;
112			clock-output-names = "qci_mclk";
113
114			status = "disabled";
115		};
116	};
117
118	clocks {
119	       /*
120		* The muxing of external clocks/internal dividers for osc* clock
121		* sources has been hidden under the carpet by now.
122		*/
123		#address-cells = <1>;
124		#size-cells = <1>;
125		ranges;
126
127		clks: pxa2xx_clks@41300004 {
128			compatible = "marvell,pxa270-clocks";
129			#clock-cells = <1>;
130			status = "okay";
131		};
132	};
133
134	timer@40a00000 {
135		compatible = "marvell,pxa-timer";
136		reg = <0x40a00000 0x20>;
137		interrupts = <26>;
138		clocks = <&clks CLK_OSTIMER>;
139		status = "okay";
140	};
141
142	pxa270_opp_table: opp_table0 {
143		compatible = "operating-points-v2";
144
145		opp-104000000 {
146			opp-hz = /bits/ 64 <104000000>;
147			opp-microvolt = <900000 900000 1705000>;
148			clock-latency-ns = <20>;
149		};
150		opp-156000000 {
151			opp-hz = /bits/ 64 <156000000>;
152			opp-microvolt = <1000000 1000000 1705000>;
153			clock-latency-ns = <20>;
154		};
155		opp-208000000 {
156			opp-hz = /bits/ 64 <208000000>;
157			opp-microvolt = <1180000 1180000 1705000>;
158			clock-latency-ns = <20>;
159		};
160		opp-312000000 {
161			opp-hz = /bits/ 64 <312000000>;
162			opp-microvolt = <1250000 1250000 1705000>;
163			clock-latency-ns = <20>;
164		};
165		opp-416000000 {
166			opp-hz = /bits/ 64 <416000000>;
167			opp-microvolt = <1350000 1350000 1705000>;
168			clock-latency-ns = <20>;
169		};
170		opp-520000000 {
171			opp-hz = /bits/ 64 <520000000>;
172			opp-microvolt = <1450000 1450000 1705000>;
173			clock-latency-ns = <20>;
174		};
175		opp-624000000 {
176			opp-hz = /bits/ 64 <624000000>;
177			opp-microvolt = <1550000 1550000 1705000>;
178			clock-latency-ns = <20>;
179		};
180	};
181};