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1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#include <dt-bindings/clock/imx6qdl-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17 #address-cells = <1>;
18 #size-cells = <1>;
19 /*
20 * The decompressor and also some bootloaders rely on a
21 * pre-existing /chosen node to be available to insert the
22 * command line and merge other ATAGS info.
23 * Also for U-Boot there must be a pre-existing /memory node.
24 */
25 chosen {};
26 memory { device_type = "memory"; };
27
28 aliases {
29 ethernet0 = &fec;
30 can0 = &can1;
31 can1 = &can2;
32 gpio0 = &gpio1;
33 gpio1 = &gpio2;
34 gpio2 = &gpio3;
35 gpio3 = &gpio4;
36 gpio4 = &gpio5;
37 gpio5 = &gpio6;
38 gpio6 = &gpio7;
39 i2c0 = &i2c1;
40 i2c1 = &i2c2;
41 i2c2 = &i2c3;
42 ipu0 = &ipu1;
43 mmc0 = &usdhc1;
44 mmc1 = &usdhc2;
45 mmc2 = &usdhc3;
46 mmc3 = &usdhc4;
47 serial0 = &uart1;
48 serial1 = &uart2;
49 serial2 = &uart3;
50 serial3 = &uart4;
51 serial4 = &uart5;
52 spi0 = &ecspi1;
53 spi1 = &ecspi2;
54 spi2 = &ecspi3;
55 spi3 = &ecspi4;
56 usbphy0 = &usbphy1;
57 usbphy1 = &usbphy2;
58 };
59
60 clocks {
61 #address-cells = <1>;
62 #size-cells = <0>;
63
64 ckil {
65 compatible = "fsl,imx-ckil", "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <32768>;
68 };
69
70 ckih1 {
71 compatible = "fsl,imx-ckih1", "fixed-clock";
72 #clock-cells = <0>;
73 clock-frequency = <0>;
74 };
75
76 osc {
77 compatible = "fsl,imx-osc", "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <24000000>;
80 };
81 };
82
83 tempmon: tempmon {
84 compatible = "fsl,imx6q-tempmon";
85 interrupt-parent = <&gpc>;
86 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
87 fsl,tempmon = <&anatop>;
88 fsl,tempmon-data = <&ocotp>;
89 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
90 };
91
92 ldb: ldb {
93 #address-cells = <1>;
94 #size-cells = <0>;
95 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
96 gpr = <&gpr>;
97 status = "disabled";
98
99 lvds-channel@0 {
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0>;
103 status = "disabled";
104
105 port@0 {
106 reg = <0>;
107
108 lvds0_mux_0: endpoint {
109 remote-endpoint = <&ipu1_di0_lvds0>;
110 };
111 };
112
113 port@1 {
114 reg = <1>;
115
116 lvds0_mux_1: endpoint {
117 remote-endpoint = <&ipu1_di1_lvds0>;
118 };
119 };
120 };
121
122 lvds-channel@1 {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 reg = <1>;
126 status = "disabled";
127
128 port@0 {
129 reg = <0>;
130
131 lvds1_mux_0: endpoint {
132 remote-endpoint = <&ipu1_di0_lvds1>;
133 };
134 };
135
136 port@1 {
137 reg = <1>;
138
139 lvds1_mux_1: endpoint {
140 remote-endpoint = <&ipu1_di1_lvds1>;
141 };
142 };
143 };
144 };
145
146 pmu: pmu {
147 compatible = "arm,cortex-a9-pmu";
148 interrupt-parent = <&gpc>;
149 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
150 };
151
152 soc {
153 #address-cells = <1>;
154 #size-cells = <1>;
155 compatible = "simple-bus";
156 interrupt-parent = <&gpc>;
157 ranges;
158
159 dma_apbh: dma-apbh@110000 {
160 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
161 reg = <0x00110000 0x2000>;
162 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
163 <0 13 IRQ_TYPE_LEVEL_HIGH>,
164 <0 13 IRQ_TYPE_LEVEL_HIGH>,
165 <0 13 IRQ_TYPE_LEVEL_HIGH>;
166 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
167 #dma-cells = <1>;
168 dma-channels = <4>;
169 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
170 };
171
172 gpmi: gpmi-nand@112000 {
173 compatible = "fsl,imx6q-gpmi-nand";
174 #address-cells = <1>;
175 #size-cells = <1>;
176 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
177 reg-names = "gpmi-nand", "bch";
178 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-names = "bch";
180 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
181 <&clks IMX6QDL_CLK_GPMI_APB>,
182 <&clks IMX6QDL_CLK_GPMI_BCH>,
183 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
184 <&clks IMX6QDL_CLK_PER1_BCH>;
185 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
186 "gpmi_bch_apb", "per1_bch";
187 dmas = <&dma_apbh 0>;
188 dma-names = "rx-tx";
189 status = "disabled";
190 };
191
192 hdmi: hdmi@120000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 reg = <0x00120000 0x9000>;
196 interrupts = <0 115 0x04>;
197 gpr = <&gpr>;
198 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
199 <&clks IMX6QDL_CLK_HDMI_ISFR>;
200 clock-names = "iahb", "isfr";
201 status = "disabled";
202
203 port@0 {
204 reg = <0>;
205
206 hdmi_mux_0: endpoint {
207 remote-endpoint = <&ipu1_di0_hdmi>;
208 };
209 };
210
211 port@1 {
212 reg = <1>;
213
214 hdmi_mux_1: endpoint {
215 remote-endpoint = <&ipu1_di1_hdmi>;
216 };
217 };
218 };
219
220 gpu_3d: gpu@130000 {
221 compatible = "vivante,gc";
222 reg = <0x00130000 0x4000>;
223 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
224 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
225 <&clks IMX6QDL_CLK_GPU3D_CORE>,
226 <&clks IMX6QDL_CLK_GPU3D_SHADER>;
227 clock-names = "bus", "core", "shader";
228 power-domains = <&pd_pu>;
229 };
230
231 gpu_2d: gpu@134000 {
232 compatible = "vivante,gc";
233 reg = <0x00134000 0x4000>;
234 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
235 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>,
236 <&clks IMX6QDL_CLK_GPU2D_CORE>;
237 clock-names = "bus", "core";
238 power-domains = <&pd_pu>;
239 };
240
241 timer@a00600 {
242 compatible = "arm,cortex-a9-twd-timer";
243 reg = <0x00a00600 0x20>;
244 interrupts = <1 13 0xf01>;
245 interrupt-parent = <&intc>;
246 clocks = <&clks IMX6QDL_CLK_TWD>;
247 };
248
249 intc: interrupt-controller@a01000 {
250 compatible = "arm,cortex-a9-gic";
251 #interrupt-cells = <3>;
252 interrupt-controller;
253 reg = <0x00a01000 0x1000>,
254 <0x00a00100 0x100>;
255 interrupt-parent = <&intc>;
256 };
257
258 L2: l2-cache@a02000 {
259 compatible = "arm,pl310-cache";
260 reg = <0x00a02000 0x1000>;
261 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
262 cache-unified;
263 cache-level = <2>;
264 arm,tag-latency = <4 2 3>;
265 arm,data-latency = <4 2 3>;
266 arm,shared-override;
267 };
268
269 pcie: pcie@1ffc000 {
270 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
271 reg = <0x01ffc000 0x04000>,
272 <0x01f00000 0x80000>;
273 reg-names = "dbi", "config";
274 #address-cells = <3>;
275 #size-cells = <2>;
276 device_type = "pci";
277 bus-range = <0x00 0xff>;
278 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
279 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
280 num-lanes = <1>;
281 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
282 interrupt-names = "msi";
283 #interrupt-cells = <1>;
284 interrupt-map-mask = <0 0 0 0x7>;
285 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
286 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
287 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
288 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
290 <&clks IMX6QDL_CLK_LVDS1_GATE>,
291 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
292 clock-names = "pcie", "pcie_bus", "pcie_phy";
293 status = "disabled";
294 };
295
296 aips-bus@2000000 { /* AIPS1 */
297 compatible = "fsl,aips-bus", "simple-bus";
298 #address-cells = <1>;
299 #size-cells = <1>;
300 reg = <0x02000000 0x100000>;
301 ranges;
302
303 spba-bus@2000000 {
304 compatible = "fsl,spba-bus", "simple-bus";
305 #address-cells = <1>;
306 #size-cells = <1>;
307 reg = <0x02000000 0x40000>;
308 ranges;
309
310 spdif: spdif@2004000 {
311 compatible = "fsl,imx35-spdif";
312 reg = <0x02004000 0x4000>;
313 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
314 dmas = <&sdma 14 18 0>,
315 <&sdma 15 18 0>;
316 dma-names = "rx", "tx";
317 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
318 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
319 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
320 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
321 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
322 clock-names = "core", "rxtx0",
323 "rxtx1", "rxtx2",
324 "rxtx3", "rxtx4",
325 "rxtx5", "rxtx6",
326 "rxtx7", "spba";
327 status = "disabled";
328 };
329
330 ecspi1: ecspi@2008000 {
331 #address-cells = <1>;
332 #size-cells = <0>;
333 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
334 reg = <0x02008000 0x4000>;
335 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&clks IMX6QDL_CLK_ECSPI1>,
337 <&clks IMX6QDL_CLK_ECSPI1>;
338 clock-names = "ipg", "per";
339 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>;
340 dma-names = "rx", "tx";
341 status = "disabled";
342 };
343
344 ecspi2: ecspi@200c000 {
345 #address-cells = <1>;
346 #size-cells = <0>;
347 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
348 reg = <0x0200c000 0x4000>;
349 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clks IMX6QDL_CLK_ECSPI2>,
351 <&clks IMX6QDL_CLK_ECSPI2>;
352 clock-names = "ipg", "per";
353 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>;
354 dma-names = "rx", "tx";
355 status = "disabled";
356 };
357
358 ecspi3: ecspi@2010000 {
359 #address-cells = <1>;
360 #size-cells = <0>;
361 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
362 reg = <0x02010000 0x4000>;
363 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
364 clocks = <&clks IMX6QDL_CLK_ECSPI3>,
365 <&clks IMX6QDL_CLK_ECSPI3>;
366 clock-names = "ipg", "per";
367 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>;
368 dma-names = "rx", "tx";
369 status = "disabled";
370 };
371
372 ecspi4: ecspi@2014000 {
373 #address-cells = <1>;
374 #size-cells = <0>;
375 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
376 reg = <0x02014000 0x4000>;
377 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&clks IMX6QDL_CLK_ECSPI4>,
379 <&clks IMX6QDL_CLK_ECSPI4>;
380 clock-names = "ipg", "per";
381 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>;
382 dma-names = "rx", "tx";
383 status = "disabled";
384 };
385
386 uart1: serial@2020000 {
387 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
388 reg = <0x02020000 0x4000>;
389 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
391 <&clks IMX6QDL_CLK_UART_SERIAL>;
392 clock-names = "ipg", "per";
393 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
394 dma-names = "rx", "tx";
395 status = "disabled";
396 };
397
398 esai: esai@2024000 {
399 #sound-dai-cells = <0>;
400 compatible = "fsl,imx35-esai";
401 reg = <0x02024000 0x4000>;
402 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>,
404 <&clks IMX6QDL_CLK_ESAI_MEM>,
405 <&clks IMX6QDL_CLK_ESAI_EXTAL>,
406 <&clks IMX6QDL_CLK_ESAI_IPG>,
407 <&clks IMX6QDL_CLK_SPBA>;
408 clock-names = "core", "mem", "extal", "fsys", "spba";
409 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>;
410 dma-names = "rx", "tx";
411 status = "disabled";
412 };
413
414 ssi1: ssi@2028000 {
415 #sound-dai-cells = <0>;
416 compatible = "fsl,imx6q-ssi",
417 "fsl,imx51-ssi";
418 reg = <0x02028000 0x4000>;
419 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
421 <&clks IMX6QDL_CLK_SSI1>;
422 clock-names = "ipg", "baud";
423 dmas = <&sdma 37 1 0>,
424 <&sdma 38 1 0>;
425 dma-names = "rx", "tx";
426 fsl,fifo-depth = <15>;
427 status = "disabled";
428 };
429
430 ssi2: ssi@202c000 {
431 #sound-dai-cells = <0>;
432 compatible = "fsl,imx6q-ssi",
433 "fsl,imx51-ssi";
434 reg = <0x0202c000 0x4000>;
435 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>,
437 <&clks IMX6QDL_CLK_SSI2>;
438 clock-names = "ipg", "baud";
439 dmas = <&sdma 41 1 0>,
440 <&sdma 42 1 0>;
441 dma-names = "rx", "tx";
442 fsl,fifo-depth = <15>;
443 status = "disabled";
444 };
445
446 ssi3: ssi@2030000 {
447 #sound-dai-cells = <0>;
448 compatible = "fsl,imx6q-ssi",
449 "fsl,imx51-ssi";
450 reg = <0x02030000 0x4000>;
451 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>,
453 <&clks IMX6QDL_CLK_SSI3>;
454 clock-names = "ipg", "baud";
455 dmas = <&sdma 45 1 0>,
456 <&sdma 46 1 0>;
457 dma-names = "rx", "tx";
458 fsl,fifo-depth = <15>;
459 status = "disabled";
460 };
461
462 asrc: asrc@2034000 {
463 compatible = "fsl,imx53-asrc";
464 reg = <0x02034000 0x4000>;
465 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>,
467 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>,
468 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
469 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
470 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
471 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>,
472 <&clks IMX6QDL_CLK_SPBA>;
473 clock-names = "mem", "ipg", "asrck_0",
474 "asrck_1", "asrck_2", "asrck_3", "asrck_4",
475 "asrck_5", "asrck_6", "asrck_7", "asrck_8",
476 "asrck_9", "asrck_a", "asrck_b", "asrck_c",
477 "asrck_d", "asrck_e", "asrck_f", "spba";
478 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
479 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
480 dma-names = "rxa", "rxb", "rxc",
481 "txa", "txb", "txc";
482 fsl,asrc-rate = <48000>;
483 fsl,asrc-width = <16>;
484 status = "okay";
485 };
486
487 spba@203c000 {
488 reg = <0x0203c000 0x4000>;
489 };
490 };
491
492 vpu: vpu@2040000 {
493 compatible = "cnm,coda960";
494 reg = <0x02040000 0x3c000>;
495 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
496 <0 3 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "bit", "jpeg";
498 clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
499 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>;
500 clock-names = "per", "ahb";
501 power-domains = <&pd_pu>;
502 resets = <&src 1>;
503 iram = <&ocram>;
504 };
505
506 aipstz@207c000 { /* AIPSTZ1 */
507 reg = <0x0207c000 0x4000>;
508 };
509
510 pwm1: pwm@2080000 {
511 #pwm-cells = <2>;
512 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
513 reg = <0x02080000 0x4000>;
514 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&clks IMX6QDL_CLK_IPG>,
516 <&clks IMX6QDL_CLK_PWM1>;
517 clock-names = "ipg", "per";
518 status = "disabled";
519 };
520
521 pwm2: pwm@2084000 {
522 #pwm-cells = <2>;
523 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
524 reg = <0x02084000 0x4000>;
525 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&clks IMX6QDL_CLK_IPG>,
527 <&clks IMX6QDL_CLK_PWM2>;
528 clock-names = "ipg", "per";
529 status = "disabled";
530 };
531
532 pwm3: pwm@2088000 {
533 #pwm-cells = <2>;
534 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
535 reg = <0x02088000 0x4000>;
536 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
537 clocks = <&clks IMX6QDL_CLK_IPG>,
538 <&clks IMX6QDL_CLK_PWM3>;
539 clock-names = "ipg", "per";
540 status = "disabled";
541 };
542
543 pwm4: pwm@208c000 {
544 #pwm-cells = <2>;
545 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
546 reg = <0x0208c000 0x4000>;
547 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&clks IMX6QDL_CLK_IPG>,
549 <&clks IMX6QDL_CLK_PWM4>;
550 clock-names = "ipg", "per";
551 status = "disabled";
552 };
553
554 can1: flexcan@2090000 {
555 compatible = "fsl,imx6q-flexcan";
556 reg = <0x02090000 0x4000>;
557 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>,
559 <&clks IMX6QDL_CLK_CAN1_SERIAL>;
560 clock-names = "ipg", "per";
561 status = "disabled";
562 };
563
564 can2: flexcan@2094000 {
565 compatible = "fsl,imx6q-flexcan";
566 reg = <0x02094000 0x4000>;
567 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
568 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>,
569 <&clks IMX6QDL_CLK_CAN2_SERIAL>;
570 clock-names = "ipg", "per";
571 status = "disabled";
572 };
573
574 gpt: gpt@2098000 {
575 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
576 reg = <0x02098000 0x4000>;
577 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&clks IMX6QDL_CLK_GPT_IPG>,
579 <&clks IMX6QDL_CLK_GPT_IPG_PER>,
580 <&clks IMX6QDL_CLK_GPT_3M>;
581 clock-names = "ipg", "per", "osc_per";
582 };
583
584 gpio1: gpio@209c000 {
585 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
586 reg = <0x0209c000 0x4000>;
587 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
588 <0 67 IRQ_TYPE_LEVEL_HIGH>;
589 gpio-controller;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 };
594
595 gpio2: gpio@20a0000 {
596 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
597 reg = <0x020a0000 0x4000>;
598 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
599 <0 69 IRQ_TYPE_LEVEL_HIGH>;
600 gpio-controller;
601 #gpio-cells = <2>;
602 interrupt-controller;
603 #interrupt-cells = <2>;
604 };
605
606 gpio3: gpio@20a4000 {
607 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
608 reg = <0x020a4000 0x4000>;
609 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
610 <0 71 IRQ_TYPE_LEVEL_HIGH>;
611 gpio-controller;
612 #gpio-cells = <2>;
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 };
616
617 gpio4: gpio@20a8000 {
618 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
619 reg = <0x020a8000 0x4000>;
620 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
621 <0 73 IRQ_TYPE_LEVEL_HIGH>;
622 gpio-controller;
623 #gpio-cells = <2>;
624 interrupt-controller;
625 #interrupt-cells = <2>;
626 };
627
628 gpio5: gpio@20ac000 {
629 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
630 reg = <0x020ac000 0x4000>;
631 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
632 <0 75 IRQ_TYPE_LEVEL_HIGH>;
633 gpio-controller;
634 #gpio-cells = <2>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 };
638
639 gpio6: gpio@20b0000 {
640 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
641 reg = <0x020b0000 0x4000>;
642 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
643 <0 77 IRQ_TYPE_LEVEL_HIGH>;
644 gpio-controller;
645 #gpio-cells = <2>;
646 interrupt-controller;
647 #interrupt-cells = <2>;
648 };
649
650 gpio7: gpio@20b4000 {
651 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
652 reg = <0x020b4000 0x4000>;
653 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
654 <0 79 IRQ_TYPE_LEVEL_HIGH>;
655 gpio-controller;
656 #gpio-cells = <2>;
657 interrupt-controller;
658 #interrupt-cells = <2>;
659 };
660
661 kpp: kpp@20b8000 {
662 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
663 reg = <0x020b8000 0x4000>;
664 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&clks IMX6QDL_CLK_IPG>;
666 status = "disabled";
667 };
668
669 wdog1: wdog@20bc000 {
670 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
671 reg = <0x020bc000 0x4000>;
672 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&clks IMX6QDL_CLK_DUMMY>;
674 };
675
676 wdog2: wdog@20c0000 {
677 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
678 reg = <0x020c0000 0x4000>;
679 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
680 clocks = <&clks IMX6QDL_CLK_DUMMY>;
681 status = "disabled";
682 };
683
684 clks: ccm@20c4000 {
685 compatible = "fsl,imx6q-ccm";
686 reg = <0x020c4000 0x4000>;
687 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
688 <0 88 IRQ_TYPE_LEVEL_HIGH>;
689 #clock-cells = <1>;
690 };
691
692 anatop: anatop@20c8000 {
693 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
694 reg = <0x020c8000 0x1000>;
695 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
696 <0 54 IRQ_TYPE_LEVEL_HIGH>,
697 <0 127 IRQ_TYPE_LEVEL_HIGH>;
698 #address-cells = <1>;
699 #size-cells = <0>;
700
701 regulator-1p1@20c8110 {
702 reg = <0x20c8110>;
703 compatible = "fsl,anatop-regulator";
704 regulator-name = "vdd1p1";
705 regulator-min-microvolt = <1000000>;
706 regulator-max-microvolt = <1200000>;
707 regulator-always-on;
708 anatop-reg-offset = <0x110>;
709 anatop-vol-bit-shift = <8>;
710 anatop-vol-bit-width = <5>;
711 anatop-min-bit-val = <4>;
712 anatop-min-voltage = <800000>;
713 anatop-max-voltage = <1375000>;
714 anatop-enable-bit = <0>;
715 };
716
717 regulator-3p0@20c8120 {
718 reg = <0x20c8120>;
719 compatible = "fsl,anatop-regulator";
720 regulator-name = "vdd3p0";
721 regulator-min-microvolt = <2800000>;
722 regulator-max-microvolt = <3150000>;
723 regulator-always-on;
724 anatop-reg-offset = <0x120>;
725 anatop-vol-bit-shift = <8>;
726 anatop-vol-bit-width = <5>;
727 anatop-min-bit-val = <0>;
728 anatop-min-voltage = <2625000>;
729 anatop-max-voltage = <3400000>;
730 anatop-enable-bit = <0>;
731 };
732
733 regulator-2p5@20c8130 {
734 reg = <0x20c8130>;
735 compatible = "fsl,anatop-regulator";
736 regulator-name = "vdd2p5";
737 regulator-min-microvolt = <2250000>;
738 regulator-max-microvolt = <2750000>;
739 regulator-always-on;
740 anatop-reg-offset = <0x130>;
741 anatop-vol-bit-shift = <8>;
742 anatop-vol-bit-width = <5>;
743 anatop-min-bit-val = <0>;
744 anatop-min-voltage = <2100000>;
745 anatop-max-voltage = <2875000>;
746 anatop-enable-bit = <0>;
747 };
748
749 reg_arm: regulator-vddcore@20c8140 {
750 reg = <0x20c8140>;
751 compatible = "fsl,anatop-regulator";
752 regulator-name = "vddarm";
753 regulator-min-microvolt = <725000>;
754 regulator-max-microvolt = <1450000>;
755 regulator-always-on;
756 anatop-reg-offset = <0x140>;
757 anatop-vol-bit-shift = <0>;
758 anatop-vol-bit-width = <5>;
759 anatop-delay-reg-offset = <0x170>;
760 anatop-delay-bit-shift = <24>;
761 anatop-delay-bit-width = <2>;
762 anatop-min-bit-val = <1>;
763 anatop-min-voltage = <725000>;
764 anatop-max-voltage = <1450000>;
765 };
766
767 reg_pu: regulator-vddpu@20c8140 {
768 reg = <0x20c8140>;
769 compatible = "fsl,anatop-regulator";
770 regulator-name = "vddpu";
771 regulator-min-microvolt = <725000>;
772 regulator-max-microvolt = <1450000>;
773 regulator-enable-ramp-delay = <150>;
774 anatop-reg-offset = <0x140>;
775 anatop-vol-bit-shift = <9>;
776 anatop-vol-bit-width = <5>;
777 anatop-delay-reg-offset = <0x170>;
778 anatop-delay-bit-shift = <26>;
779 anatop-delay-bit-width = <2>;
780 anatop-min-bit-val = <1>;
781 anatop-min-voltage = <725000>;
782 anatop-max-voltage = <1450000>;
783 };
784
785 reg_soc: regulator-vddsoc@20c8140 {
786 reg = <0x20c8140>;
787 compatible = "fsl,anatop-regulator";
788 regulator-name = "vddsoc";
789 regulator-min-microvolt = <725000>;
790 regulator-max-microvolt = <1450000>;
791 regulator-always-on;
792 anatop-reg-offset = <0x140>;
793 anatop-vol-bit-shift = <18>;
794 anatop-vol-bit-width = <5>;
795 anatop-delay-reg-offset = <0x170>;
796 anatop-delay-bit-shift = <28>;
797 anatop-delay-bit-width = <2>;
798 anatop-min-bit-val = <1>;
799 anatop-min-voltage = <725000>;
800 anatop-max-voltage = <1450000>;
801 };
802 };
803
804 usbphy1: usbphy@20c9000 {
805 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
806 reg = <0x020c9000 0x1000>;
807 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
808 clocks = <&clks IMX6QDL_CLK_USBPHY1>;
809 fsl,anatop = <&anatop>;
810 };
811
812 usbphy2: usbphy@20ca000 {
813 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
814 reg = <0x020ca000 0x1000>;
815 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&clks IMX6QDL_CLK_USBPHY2>;
817 fsl,anatop = <&anatop>;
818 };
819
820 snvs: snvs@20cc000 {
821 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
822 reg = <0x020cc000 0x4000>;
823
824 snvs_rtc: snvs-rtc-lp {
825 compatible = "fsl,sec-v4.0-mon-rtc-lp";
826 regmap = <&snvs>;
827 offset = <0x34>;
828 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
829 <0 20 IRQ_TYPE_LEVEL_HIGH>;
830 };
831
832 snvs_poweroff: snvs-poweroff {
833 compatible = "syscon-poweroff";
834 regmap = <&snvs>;
835 offset = <0x38>;
836 value = <0x60>;
837 mask = <0x60>;
838 status = "disabled";
839 };
840
841 snvs_lpgpr: snvs-lpgpr {
842 compatible = "fsl,imx6q-snvs-lpgpr";
843 };
844 };
845
846 epit1: epit@20d0000 { /* EPIT1 */
847 reg = <0x020d0000 0x4000>;
848 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
849 };
850
851 epit2: epit@20d4000 { /* EPIT2 */
852 reg = <0x020d4000 0x4000>;
853 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
854 };
855
856 src: src@20d8000 {
857 compatible = "fsl,imx6q-src", "fsl,imx51-src";
858 reg = <0x020d8000 0x4000>;
859 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
860 <0 96 IRQ_TYPE_LEVEL_HIGH>;
861 #reset-cells = <1>;
862 };
863
864 gpc: gpc@20dc000 {
865 compatible = "fsl,imx6q-gpc";
866 reg = <0x020dc000 0x4000>;
867 interrupt-controller;
868 #interrupt-cells = <3>;
869 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
870 <0 90 IRQ_TYPE_LEVEL_HIGH>;
871 interrupt-parent = <&intc>;
872 clocks = <&clks IMX6QDL_CLK_IPG>;
873 clock-names = "ipg";
874
875 pgc {
876 #address-cells = <1>;
877 #size-cells = <0>;
878
879 power-domain@0 {
880 reg = <0>;
881 #power-domain-cells = <0>;
882 };
883 pd_pu: power-domain@1 {
884 reg = <1>;
885 #power-domain-cells = <0>;
886 power-supply = <®_pu>;
887 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
888 <&clks IMX6QDL_CLK_GPU3D_SHADER>,
889 <&clks IMX6QDL_CLK_GPU2D_CORE>,
890 <&clks IMX6QDL_CLK_GPU2D_AXI>,
891 <&clks IMX6QDL_CLK_OPENVG_AXI>,
892 <&clks IMX6QDL_CLK_VPU_AXI>;
893 };
894 };
895 };
896
897 gpr: iomuxc-gpr@20e0000 {
898 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
899 reg = <0x20e0000 0x38>;
900
901 mux: mux-controller {
902 compatible = "mmio-mux";
903 #mux-control-cells = <1>;
904 };
905 };
906
907 iomuxc: iomuxc@20e0000 {
908 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
909 reg = <0x20e0000 0x4000>;
910 };
911
912 dcic1: dcic@20e4000 {
913 reg = <0x020e4000 0x4000>;
914 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
915 };
916
917 dcic2: dcic@20e8000 {
918 reg = <0x020e8000 0x4000>;
919 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
920 };
921
922 sdma: sdma@20ec000 {
923 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
924 reg = <0x020ec000 0x4000>;
925 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&clks IMX6QDL_CLK_SDMA>,
927 <&clks IMX6QDL_CLK_SDMA>;
928 clock-names = "ipg", "ahb";
929 #dma-cells = <3>;
930 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
931 };
932 };
933
934 aips-bus@2100000 { /* AIPS2 */
935 compatible = "fsl,aips-bus", "simple-bus";
936 #address-cells = <1>;
937 #size-cells = <1>;
938 reg = <0x02100000 0x100000>;
939 ranges;
940
941 crypto: caam@2100000 {
942 compatible = "fsl,sec-v4.0";
943 fsl,sec-era = <4>;
944 #address-cells = <1>;
945 #size-cells = <1>;
946 reg = <0x2100000 0x10000>;
947 ranges = <0 0x2100000 0x10000>;
948 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
949 <&clks IMX6QDL_CLK_CAAM_ACLK>,
950 <&clks IMX6QDL_CLK_CAAM_IPG>,
951 <&clks IMX6QDL_CLK_EIM_SLOW>;
952 clock-names = "mem", "aclk", "ipg", "emi_slow";
953
954 sec_jr0: jr0@1000 {
955 compatible = "fsl,sec-v4.0-job-ring";
956 reg = <0x1000 0x1000>;
957 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
958 };
959
960 sec_jr1: jr1@2000 {
961 compatible = "fsl,sec-v4.0-job-ring";
962 reg = <0x2000 0x1000>;
963 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
964 };
965 };
966
967 aipstz@217c000 { /* AIPSTZ2 */
968 reg = <0x0217c000 0x4000>;
969 };
970
971 usbotg: usb@2184000 {
972 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
973 reg = <0x02184000 0x200>;
974 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
975 clocks = <&clks IMX6QDL_CLK_USBOH3>;
976 fsl,usbphy = <&usbphy1>;
977 fsl,usbmisc = <&usbmisc 0>;
978 ahb-burst-config = <0x0>;
979 tx-burst-size-dword = <0x10>;
980 rx-burst-size-dword = <0x10>;
981 status = "disabled";
982 };
983
984 usbh1: usb@2184200 {
985 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
986 reg = <0x02184200 0x200>;
987 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&clks IMX6QDL_CLK_USBOH3>;
989 fsl,usbphy = <&usbphy2>;
990 fsl,usbmisc = <&usbmisc 1>;
991 dr_mode = "host";
992 ahb-burst-config = <0x0>;
993 tx-burst-size-dword = <0x10>;
994 rx-burst-size-dword = <0x10>;
995 status = "disabled";
996 };
997
998 usbh2: usb@2184400 {
999 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1000 reg = <0x02184400 0x200>;
1001 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1003 fsl,usbmisc = <&usbmisc 2>;
1004 dr_mode = "host";
1005 ahb-burst-config = <0x0>;
1006 tx-burst-size-dword = <0x10>;
1007 rx-burst-size-dword = <0x10>;
1008 status = "disabled";
1009 };
1010
1011 usbh3: usb@2184600 {
1012 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1013 reg = <0x02184600 0x200>;
1014 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1016 fsl,usbmisc = <&usbmisc 3>;
1017 dr_mode = "host";
1018 ahb-burst-config = <0x0>;
1019 tx-burst-size-dword = <0x10>;
1020 rx-burst-size-dword = <0x10>;
1021 status = "disabled";
1022 };
1023
1024 usbmisc: usbmisc@2184800 {
1025 #index-cells = <1>;
1026 compatible = "fsl,imx6q-usbmisc";
1027 reg = <0x02184800 0x200>;
1028 clocks = <&clks IMX6QDL_CLK_USBOH3>;
1029 };
1030
1031 fec: ethernet@2188000 {
1032 compatible = "fsl,imx6q-fec";
1033 reg = <0x02188000 0x4000>;
1034 interrupt-names = "int0", "pps";
1035 interrupts-extended =
1036 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
1037 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
1038 clocks = <&clks IMX6QDL_CLK_ENET>,
1039 <&clks IMX6QDL_CLK_ENET>,
1040 <&clks IMX6QDL_CLK_ENET_REF>;
1041 clock-names = "ipg", "ahb", "ptp";
1042 status = "disabled";
1043 };
1044
1045 mlb@218c000 {
1046 reg = <0x0218c000 0x4000>;
1047 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
1048 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1049 <0 126 IRQ_TYPE_LEVEL_HIGH>;
1050 };
1051
1052 usdhc1: usdhc@2190000 {
1053 compatible = "fsl,imx6q-usdhc";
1054 reg = <0x02190000 0x4000>;
1055 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
1056 clocks = <&clks IMX6QDL_CLK_USDHC1>,
1057 <&clks IMX6QDL_CLK_USDHC1>,
1058 <&clks IMX6QDL_CLK_USDHC1>;
1059 clock-names = "ipg", "ahb", "per";
1060 bus-width = <4>;
1061 status = "disabled";
1062 };
1063
1064 usdhc2: usdhc@2194000 {
1065 compatible = "fsl,imx6q-usdhc";
1066 reg = <0x02194000 0x4000>;
1067 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
1068 clocks = <&clks IMX6QDL_CLK_USDHC2>,
1069 <&clks IMX6QDL_CLK_USDHC2>,
1070 <&clks IMX6QDL_CLK_USDHC2>;
1071 clock-names = "ipg", "ahb", "per";
1072 bus-width = <4>;
1073 status = "disabled";
1074 };
1075
1076 usdhc3: usdhc@2198000 {
1077 compatible = "fsl,imx6q-usdhc";
1078 reg = <0x02198000 0x4000>;
1079 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&clks IMX6QDL_CLK_USDHC3>,
1081 <&clks IMX6QDL_CLK_USDHC3>,
1082 <&clks IMX6QDL_CLK_USDHC3>;
1083 clock-names = "ipg", "ahb", "per";
1084 bus-width = <4>;
1085 status = "disabled";
1086 };
1087
1088 usdhc4: usdhc@219c000 {
1089 compatible = "fsl,imx6q-usdhc";
1090 reg = <0x0219c000 0x4000>;
1091 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
1092 clocks = <&clks IMX6QDL_CLK_USDHC4>,
1093 <&clks IMX6QDL_CLK_USDHC4>,
1094 <&clks IMX6QDL_CLK_USDHC4>;
1095 clock-names = "ipg", "ahb", "per";
1096 bus-width = <4>;
1097 status = "disabled";
1098 };
1099
1100 i2c1: i2c@21a0000 {
1101 #address-cells = <1>;
1102 #size-cells = <0>;
1103 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1104 reg = <0x021a0000 0x4000>;
1105 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clks IMX6QDL_CLK_I2C1>;
1107 status = "disabled";
1108 };
1109
1110 i2c2: i2c@21a4000 {
1111 #address-cells = <1>;
1112 #size-cells = <0>;
1113 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1114 reg = <0x021a4000 0x4000>;
1115 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&clks IMX6QDL_CLK_I2C2>;
1117 status = "disabled";
1118 };
1119
1120 i2c3: i2c@21a8000 {
1121 #address-cells = <1>;
1122 #size-cells = <0>;
1123 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
1124 reg = <0x021a8000 0x4000>;
1125 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&clks IMX6QDL_CLK_I2C3>;
1127 status = "disabled";
1128 };
1129
1130 romcp@21ac000 {
1131 reg = <0x021ac000 0x4000>;
1132 };
1133
1134 mmdc0: mmdc@21b0000 { /* MMDC0 */
1135 compatible = "fsl,imx6q-mmdc";
1136 reg = <0x021b0000 0x4000>;
1137 };
1138
1139 mmdc1: mmdc@21b4000 { /* MMDC1 */
1140 reg = <0x021b4000 0x4000>;
1141 };
1142
1143 weim: weim@21b8000 {
1144 #address-cells = <2>;
1145 #size-cells = <1>;
1146 compatible = "fsl,imx6q-weim";
1147 reg = <0x021b8000 0x4000>;
1148 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
1149 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>;
1150 fsl,weim-cs-gpr = <&gpr>;
1151 status = "disabled";
1152 };
1153
1154 ocotp: ocotp@21bc000 {
1155 compatible = "fsl,imx6q-ocotp", "syscon";
1156 reg = <0x021bc000 0x4000>;
1157 clocks = <&clks IMX6QDL_CLK_IIM>;
1158 };
1159
1160 tzasc@21d0000 { /* TZASC1 */
1161 reg = <0x021d0000 0x4000>;
1162 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1163 };
1164
1165 tzasc@21d4000 { /* TZASC2 */
1166 reg = <0x021d4000 0x4000>;
1167 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
1168 };
1169
1170 audmux: audmux@21d8000 {
1171 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
1172 reg = <0x021d8000 0x4000>;
1173 status = "disabled";
1174 };
1175
1176 mipi_csi: mipi@21dc000 {
1177 compatible = "fsl,imx6-mipi-csi2";
1178 reg = <0x021dc000 0x4000>;
1179 #address-cells = <1>;
1180 #size-cells = <0>;
1181 interrupts = <0 100 0x04>, <0 101 0x04>;
1182 clocks = <&clks IMX6QDL_CLK_HSI_TX>,
1183 <&clks IMX6QDL_CLK_VIDEO_27M>,
1184 <&clks IMX6QDL_CLK_EIM_PODF>;
1185 clock-names = "dphy", "ref", "pix";
1186 status = "disabled";
1187 };
1188
1189 mipi_dsi: mipi@21e0000 {
1190 #address-cells = <1>;
1191 #size-cells = <0>;
1192 reg = <0x021e0000 0x4000>;
1193 status = "disabled";
1194
1195 ports {
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198
1199 port@0 {
1200 reg = <0>;
1201
1202 mipi_mux_0: endpoint {
1203 remote-endpoint = <&ipu1_di0_mipi>;
1204 };
1205 };
1206
1207 port@1 {
1208 reg = <1>;
1209
1210 mipi_mux_1: endpoint {
1211 remote-endpoint = <&ipu1_di1_mipi>;
1212 };
1213 };
1214 };
1215 };
1216
1217 vdoa@21e4000 {
1218 compatible = "fsl,imx6q-vdoa";
1219 reg = <0x021e4000 0x4000>;
1220 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1221 clocks = <&clks IMX6QDL_CLK_VDOA>;
1222 };
1223
1224 uart2: serial@21e8000 {
1225 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1226 reg = <0x021e8000 0x4000>;
1227 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1229 <&clks IMX6QDL_CLK_UART_SERIAL>;
1230 clock-names = "ipg", "per";
1231 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1232 dma-names = "rx", "tx";
1233 status = "disabled";
1234 };
1235
1236 uart3: serial@21ec000 {
1237 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1238 reg = <0x021ec000 0x4000>;
1239 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1240 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1241 <&clks IMX6QDL_CLK_UART_SERIAL>;
1242 clock-names = "ipg", "per";
1243 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1244 dma-names = "rx", "tx";
1245 status = "disabled";
1246 };
1247
1248 uart4: serial@21f0000 {
1249 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1250 reg = <0x021f0000 0x4000>;
1251 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1252 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1253 <&clks IMX6QDL_CLK_UART_SERIAL>;
1254 clock-names = "ipg", "per";
1255 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1256 dma-names = "rx", "tx";
1257 status = "disabled";
1258 };
1259
1260 uart5: serial@21f4000 {
1261 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1262 reg = <0x021f4000 0x4000>;
1263 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&clks IMX6QDL_CLK_UART_IPG>,
1265 <&clks IMX6QDL_CLK_UART_SERIAL>;
1266 clock-names = "ipg", "per";
1267 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1268 dma-names = "rx", "tx";
1269 status = "disabled";
1270 };
1271 };
1272
1273 ipu1: ipu@2400000 {
1274 #address-cells = <1>;
1275 #size-cells = <0>;
1276 compatible = "fsl,imx6q-ipu";
1277 reg = <0x02400000 0x400000>;
1278 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1279 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1280 clocks = <&clks IMX6QDL_CLK_IPU1>,
1281 <&clks IMX6QDL_CLK_IPU1_DI0>,
1282 <&clks IMX6QDL_CLK_IPU1_DI1>;
1283 clock-names = "bus", "di0", "di1";
1284 resets = <&src 2>;
1285
1286 ipu1_csi0: port@0 {
1287 reg = <0>;
1288
1289 ipu1_csi0_from_ipu1_csi0_mux: endpoint {
1290 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
1291 };
1292 };
1293
1294 ipu1_csi1: port@1 {
1295 reg = <1>;
1296 };
1297
1298 ipu1_di0: port@2 {
1299 #address-cells = <1>;
1300 #size-cells = <0>;
1301 reg = <2>;
1302
1303 ipu1_di0_disp0: disp0-endpoint {
1304 };
1305
1306 ipu1_di0_hdmi: hdmi-endpoint {
1307 remote-endpoint = <&hdmi_mux_0>;
1308 };
1309
1310 ipu1_di0_mipi: mipi-endpoint {
1311 remote-endpoint = <&mipi_mux_0>;
1312 };
1313
1314 ipu1_di0_lvds0: lvds0-endpoint {
1315 remote-endpoint = <&lvds0_mux_0>;
1316 };
1317
1318 ipu1_di0_lvds1: lvds1-endpoint {
1319 remote-endpoint = <&lvds1_mux_0>;
1320 };
1321 };
1322
1323 ipu1_di1: port@3 {
1324 #address-cells = <1>;
1325 #size-cells = <0>;
1326 reg = <3>;
1327
1328 ipu1_di1_disp1: disp1-endpoint {
1329 };
1330
1331 ipu1_di1_hdmi: hdmi-endpoint {
1332 remote-endpoint = <&hdmi_mux_1>;
1333 };
1334
1335 ipu1_di1_mipi: mipi-endpoint {
1336 remote-endpoint = <&mipi_mux_1>;
1337 };
1338
1339 ipu1_di1_lvds0: lvds0-endpoint {
1340 remote-endpoint = <&lvds0_mux_1>;
1341 };
1342
1343 ipu1_di1_lvds1: lvds1-endpoint {
1344 remote-endpoint = <&lvds1_mux_1>;
1345 };
1346 };
1347 };
1348 };
1349};