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1/*
2 * Device Tree Include file for Marvell Armada 1500-mini (Berlin BG2CD) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/clock/berlin2.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44
45/ {
46 model = "Marvell Armada 1500-mini (BG2CD) SoC";
47 compatible = "marvell,berlin2cd", "marvell,berlin";
48 #address-cells = <1>;
49 #size-cells = <1>;
50
51 aliases {
52 serial0 = &uart0;
53 serial1 = &uart1;
54 };
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 cpu@0 {
61 compatible = "arm,cortex-a9";
62 device_type = "cpu";
63 next-level-cache = <&l2>;
64 reg = <0>;
65
66 clocks = <&chip_clk CLKID_CPU>;
67 clock-latency = <100000>;
68 operating-points = <
69 /* kHz uV */
70 800000 1200000
71 600000 1200000
72 >;
73 };
74 };
75
76 refclk: oscillator {
77 compatible = "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <25000000>;
80 };
81
82 soc@f7000000 {
83 compatible = "simple-bus";
84 #address-cells = <1>;
85 #size-cells = <1>;
86 interrupt-parent = <&gic>;
87
88 ranges = <0 0xf7000000 0x1000000>;
89
90 pmu {
91 compatible = "arm,cortex-a9-pmu";
92 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
93 };
94
95 sdhci0: sdhci@ab0000 {
96 compatible = "mrvl,pxav3-mmc";
97 reg = <0xab0000 0x200>;
98 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
99 clock-names = "io", "core";
100 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
101 status = "disabled";
102 };
103
104 l2: l2-cache-controller@ac0000 {
105 compatible = "arm,pl310-cache";
106 reg = <0xac0000 0x1000>;
107 cache-unified;
108 cache-level = <2>;
109 };
110
111 gic: interrupt-controller@ad1000 {
112 compatible = "arm,cortex-a9-gic";
113 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
114 interrupt-controller;
115 #interrupt-cells = <3>;
116 };
117
118 local-timer@ad0600 {
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0xad0600 0x20>;
121 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
122 clocks = <&chip_clk CLKID_TWD>;
123 };
124
125 usb_phy0: usb-phy@b74000 {
126 compatible = "marvell,berlin2cd-usb-phy";
127 reg = <0xb74000 0x128>;
128 #phy-cells = <0>;
129 resets = <&chip_rst 0x178 23>;
130 status = "disabled";
131 };
132
133 usb_phy1: usb-phy@b78000 {
134 compatible = "marvell,berlin2cd-usb-phy";
135 reg = <0xb78000 0x128>;
136 #phy-cells = <0>;
137 resets = <&chip_rst 0x178 24>;
138 status = "disabled";
139 };
140
141 eth1: ethernet@b90000 {
142 compatible = "marvell,pxa168-eth";
143 reg = <0xb90000 0x10000>;
144 clocks = <&chip_clk CLKID_GETH1>;
145 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
146 /* set by bootloader */
147 local-mac-address = [00 00 00 00 00 00];
148 #address-cells = <1>;
149 #size-cells = <0>;
150 phy-connection-type = "mii";
151 phy-handle = <ðphy1>;
152 status = "disabled";
153
154 ethphy1: ethernet-phy@0 {
155 reg = <0>;
156 };
157 };
158
159 eth0: ethernet@e50000 {
160 compatible = "marvell,pxa168-eth";
161 reg = <0xe50000 0x10000>;
162 clocks = <&chip_clk CLKID_GETH0>;
163 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
164 /* set by bootloader */
165 local-mac-address = [00 00 00 00 00 00];
166 #address-cells = <1>;
167 #size-cells = <0>;
168 phy-connection-type = "mii";
169 phy-handle = <ðphy0>;
170 status = "disabled";
171
172 ethphy0: ethernet-phy@0 {
173 reg = <0>;
174 };
175 };
176
177 apb@e80000 {
178 compatible = "simple-bus";
179 #address-cells = <1>;
180 #size-cells = <1>;
181
182 ranges = <0 0xe80000 0x10000>;
183 interrupt-parent = <&aic>;
184
185 gpio0: gpio@400 {
186 compatible = "snps,dw-apb-gpio";
187 reg = <0x0400 0x400>;
188 #address-cells = <1>;
189 #size-cells = <0>;
190
191 porta: gpio-port@0 {
192 compatible = "snps,dw-apb-gpio-port";
193 gpio-controller;
194 #gpio-cells = <2>;
195 snps,nr-gpios = <8>;
196 reg = <0>;
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 interrupts = <0>;
200 };
201 };
202
203 gpio1: gpio@800 {
204 compatible = "snps,dw-apb-gpio";
205 reg = <0x0800 0x400>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208
209 portb: gpio-port@1 {
210 compatible = "snps,dw-apb-gpio-port";
211 gpio-controller;
212 #gpio-cells = <2>;
213 snps,nr-gpios = <8>;
214 reg = <0>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 interrupts = <1>;
218 };
219 };
220
221 gpio2: gpio@c00 {
222 compatible = "snps,dw-apb-gpio";
223 reg = <0x0c00 0x400>;
224 #address-cells = <1>;
225 #size-cells = <0>;
226
227 portc: gpio-port@2 {
228 compatible = "snps,dw-apb-gpio-port";
229 gpio-controller;
230 #gpio-cells = <2>;
231 snps,nr-gpios = <8>;
232 reg = <0>;
233 interrupt-controller;
234 #interrupt-cells = <2>;
235 interrupts = <2>;
236 };
237 };
238
239 gpio3: gpio@1000 {
240 compatible = "snps,dw-apb-gpio";
241 reg = <0x1000 0x400>;
242 #address-cells = <1>;
243 #size-cells = <0>;
244
245 portd: gpio-port@3 {
246 compatible = "snps,dw-apb-gpio-port";
247 gpio-controller;
248 #gpio-cells = <2>;
249 snps,nr-gpios = <8>;
250 reg = <0>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 interrupts = <3>;
254 };
255 };
256
257 timer0: timer@2c00 {
258 compatible = "snps,dw-apb-timer";
259 reg = <0x2c00 0x14>;
260 interrupts = <8>;
261 clocks = <&chip_clk CLKID_CFG>;
262 clock-names = "timer";
263 status = "okay";
264 };
265
266 timer1: timer@2c14 {
267 compatible = "snps,dw-apb-timer";
268 reg = <0x2c14 0x14>;
269 interrupts = <9>;
270 clocks = <&chip_clk CLKID_CFG>;
271 clock-names = "timer";
272 status = "okay";
273 };
274
275 timer2: timer@2c28 {
276 compatible = "snps,dw-apb-timer";
277 reg = <0x2c28 0x14>;
278 interrupts = <10>;
279 clocks = <&chip_clk CLKID_CFG>;
280 clock-names = "timer";
281 status = "disabled";
282 };
283
284 timer3: timer@2c3c {
285 compatible = "snps,dw-apb-timer";
286 reg = <0x2c3c 0x14>;
287 interrupts = <11>;
288 clocks = <&chip_clk CLKID_CFG>;
289 clock-names = "timer";
290 status = "disabled";
291 };
292
293 timer4: timer@2c50 {
294 compatible = "snps,dw-apb-timer";
295 reg = <0x2c50 0x14>;
296 interrupts = <12>;
297 clocks = <&chip_clk CLKID_CFG>;
298 clock-names = "timer";
299 status = "disabled";
300 };
301
302 timer5: timer@2c64 {
303 compatible = "snps,dw-apb-timer";
304 reg = <0x2c64 0x14>;
305 interrupts = <13>;
306 clocks = <&chip_clk CLKID_CFG>;
307 clock-names = "timer";
308 status = "disabled";
309 };
310
311 timer6: timer@2c78 {
312 compatible = "snps,dw-apb-timer";
313 reg = <0x2c78 0x14>;
314 interrupts = <14>;
315 clocks = <&chip_clk CLKID_CFG>;
316 clock-names = "timer";
317 status = "disabled";
318 };
319
320 timer7: timer@2c8c {
321 compatible = "snps,dw-apb-timer";
322 reg = <0x2c8c 0x14>;
323 interrupts = <15>;
324 clocks = <&chip_clk CLKID_CFG>;
325 clock-names = "timer";
326 status = "disabled";
327 };
328
329 aic: interrupt-controller@3000 {
330 compatible = "snps,dw-apb-ictl";
331 reg = <0x3000 0xc00>;
332 interrupt-controller;
333 #interrupt-cells = <1>;
334 interrupt-parent = <&gic>;
335 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
336 };
337 };
338
339 chip: chip-control@ea0000 {
340 compatible = "simple-mfd", "syscon";
341 reg = <0xea0000 0x400>;
342
343 chip_clk: clock {
344 compatible = "marvell,berlin2-clk";
345 #clock-cells = <1>;
346 clocks = <&refclk>;
347 clock-names = "refclk";
348 };
349
350 soc_pinctrl: pin-controller {
351 compatible = "marvell,berlin2cd-soc-pinctrl";
352
353 uart0_pmux: uart0-pmux {
354 groups = "G6";
355 function = "uart0";
356 };
357 };
358
359 chip_rst: reset {
360 compatible = "marvell,berlin2-reset";
361 #reset-cells = <2>;
362 };
363 };
364
365 usb0: usb@ed0000 {
366 compatible = "chipidea,usb2";
367 reg = <0xed0000 0x200>;
368 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&chip_clk CLKID_USB0>;
370 phys = <&usb_phy0>;
371 phy-names = "usb-phy";
372 status = "disabled";
373 };
374
375 usb1: usb@ee0000 {
376 compatible = "chipidea,usb2";
377 reg = <0xee0000 0x200>;
378 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
379 clocks = <&chip_clk CLKID_USB1>;
380 phys = <&usb_phy1>;
381 phy-names = "usb-phy";
382 status = "disabled";
383 };
384
385 pwm: pwm@f20000 {
386 compatible = "marvell,berlin-pwm";
387 reg = <0xf20000 0x40>;
388 clocks = <&chip_clk CLKID_CFG>;
389 #pwm-cells = <3>;
390 };
391
392 apb@fc0000 {
393 compatible = "simple-bus";
394 #address-cells = <1>;
395 #size-cells = <1>;
396
397 ranges = <0 0xfc0000 0x10000>;
398 interrupt-parent = <&sic>;
399
400 wdt0: watchdog@1000 {
401 compatible = "snps,dw-wdt";
402 reg = <0x1000 0x100>;
403 clocks = <&refclk>;
404 interrupts = <0>;
405 };
406
407 wdt1: watchdog@2000 {
408 compatible = "snps,dw-wdt";
409 reg = <0x2000 0x100>;
410 clocks = <&refclk>;
411 interrupts = <1>;
412 status = "disabled";
413 };
414
415 wdt2: watchdog@3000 {
416 compatible = "snps,dw-wdt";
417 reg = <0x3000 0x100>;
418 clocks = <&refclk>;
419 interrupts = <2>;
420 status = "disabled";
421 };
422
423 sm_gpio1: gpio@5000 {
424 compatible = "snps,dw-apb-gpio";
425 reg = <0x5000 0x400>;
426 #address-cells = <1>;
427 #size-cells = <0>;
428
429 portf: gpio-port@5 {
430 compatible = "snps,dw-apb-gpio-port";
431 gpio-controller;
432 #gpio-cells = <2>;
433 snps,nr-gpios = <8>;
434 reg = <0>;
435 };
436 };
437
438 sm_gpio0: gpio@c000 {
439 compatible = "snps,dw-apb-gpio";
440 reg = <0xc000 0x400>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443
444 porte: gpio-port@4 {
445 compatible = "snps,dw-apb-gpio-port";
446 gpio-controller;
447 #gpio-cells = <2>;
448 snps,nr-gpios = <8>;
449 reg = <0>;
450 };
451 };
452
453 uart0: serial@9000 {
454 compatible = "snps,dw-apb-uart";
455 reg = <0x9000 0x100>;
456 reg-shift = <2>;
457 reg-io-width = <1>;
458 interrupts = <8>;
459 clocks = <&refclk>;
460 pinctrl-0 = <&uart0_pmux>;
461 pinctrl-names = "default";
462 status = "disabled";
463 };
464
465 uart1: serial@a000 {
466 compatible = "snps,dw-apb-uart";
467 reg = <0xa000 0x100>;
468 reg-shift = <2>;
469 reg-io-width = <1>;
470 interrupts = <9>;
471 clocks = <&refclk>;
472 status = "disabled";
473 };
474
475 sysctrl: system-controller@d000 {
476 compatible = "simple-mfd", "syscon";
477 reg = <0xd000 0x100>;
478
479 sys_pinctrl: pin-controller {
480 compatible = "marvell,berlin2cd-system-pinctrl";
481 };
482 };
483
484 sic: interrupt-controller@e000 {
485 compatible = "snps,dw-apb-ictl";
486 reg = <0xe000 0x400>;
487 interrupt-controller;
488 #interrupt-cells = <1>;
489 interrupt-parent = <&gic>;
490 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
491 };
492 };
493 };
494};