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1Heterogeneous Memory Management (HMM)
2
3Provide infrastructure and helpers to integrate non-conventional memory (device
4memory like GPU on board memory) into regular kernel path, with the cornerstone
5of this being specialized struct page for such memory (see sections 5 to 7 of
6this document).
7
8HMM also provides optional helpers for SVM (Share Virtual Memory), i.e.,
9allowing a device to transparently access program address coherently with the
10CPU meaning that any valid pointer on the CPU is also a valid pointer for the
11device. This is becoming mandatory to simplify the use of advanced hetero-
12geneous computing where GPU, DSP, or FPGA are used to perform various
13computations on behalf of a process.
14
15This document is divided as follows: in the first section I expose the problems
16related to using device specific memory allocators. In the second section, I
17expose the hardware limitations that are inherent to many platforms. The third
18section gives an overview of the HMM design. The fourth section explains how
19CPU page-table mirroring works and the purpose of HMM in this context. The
20fifth section deals with how device memory is represented inside the kernel.
21Finally, the last section presents a new migration helper that allows lever-
22aging the device DMA engine.
23
24
251) Problems of using a device specific memory allocator:
262) I/O bus, device memory characteristics
273) Shared address space and migration
284) Address space mirroring implementation and API
295) Represent and manage device memory from core kernel point of view
306) Migration to and from device memory
317) Memory cgroup (memcg) and rss accounting
32
33
34-------------------------------------------------------------------------------
35
361) Problems of using a device specific memory allocator:
37
38Devices with a large amount of on board memory (several gigabytes) like GPUs
39have historically managed their memory through dedicated driver specific APIs.
40This creates a disconnect between memory allocated and managed by a device
41driver and regular application memory (private anonymous, shared memory, or
42regular file backed memory). From here on I will refer to this aspect as split
43address space. I use shared address space to refer to the opposite situation:
44i.e., one in which any application memory region can be used by a device
45transparently.
46
47Split address space happens because device can only access memory allocated
48through device specific API. This implies that all memory objects in a program
49are not equal from the device point of view which complicates large programs
50that rely on a wide set of libraries.
51
52Concretely this means that code that wants to leverage devices like GPUs needs
53to copy object between generically allocated memory (malloc, mmap private, mmap
54share) and memory allocated through the device driver API (this still ends up
55with an mmap but of the device file).
56
57For flat data sets (array, grid, image, ...) this isn't too hard to achieve but
58complex data sets (list, tree, ...) are hard to get right. Duplicating a
59complex data set needs to re-map all the pointer relations between each of its
60elements. This is error prone and program gets harder to debug because of the
61duplicate data set and addresses.
62
63Split address space also means that libraries cannot transparently use data
64they are getting from the core program or another library and thus each library
65might have to duplicate its input data set using the device specific memory
66allocator. Large projects suffer from this and waste resources because of the
67various memory copies.
68
69Duplicating each library API to accept as input or output memory allocated by
70each device specific allocator is not a viable option. It would lead to a
71combinatorial explosion in the library entry points.
72
73Finally, with the advance of high level language constructs (in C++ but in
74other languages too) it is now possible for the compiler to leverage GPUs and
75other devices without programmer knowledge. Some compiler identified patterns
76are only do-able with a shared address space. It is also more reasonable to use
77a shared address space for all other patterns.
78
79
80-------------------------------------------------------------------------------
81
822) I/O bus, device memory characteristics
83
84I/O buses cripple shared address spaces due to a few limitations. Most I/O
85buses only allow basic memory access from device to main memory; even cache
86coherency is often optional. Access to device memory from CPU is even more
87limited. More often than not, it is not cache coherent.
88
89If we only consider the PCIE bus, then a device can access main memory (often
90through an IOMMU) and be cache coherent with the CPUs. However, it only allows
91a limited set of atomic operations from device on main memory. This is worse
92in the other direction: the CPU can only access a limited range of the device
93memory and cannot perform atomic operations on it. Thus device memory cannot
94be considered the same as regular memory from the kernel point of view.
95
96Another crippling factor is the limited bandwidth (~32GBytes/s with PCIE 4.0
97and 16 lanes). This is 33 times less than the fastest GPU memory (1 TBytes/s).
98The final limitation is latency. Access to main memory from the device has an
99order of magnitude higher latency than when the device accesses its own memory.
100
101Some platforms are developing new I/O buses or additions/modifications to PCIE
102to address some of these limitations (OpenCAPI, CCIX). They mainly allow two-
103way cache coherency between CPU and device and allow all atomic operations the
104architecture supports. Sadly, not all platforms are following this trend and
105some major architectures are left without hardware solutions to these problems.
106
107So for shared address space to make sense, not only must we allow devices to
108access any memory but we must also permit any memory to be migrated to device
109memory while device is using it (blocking CPU access while it happens).
110
111
112-------------------------------------------------------------------------------
113
1143) Shared address space and migration
115
116HMM intends to provide two main features. First one is to share the address
117space by duplicating the CPU page table in the device page table so the same
118address points to the same physical memory for any valid main memory address in
119the process address space.
120
121To achieve this, HMM offers a set of helpers to populate the device page table
122while keeping track of CPU page table updates. Device page table updates are
123not as easy as CPU page table updates. To update the device page table, you must
124allocate a buffer (or use a pool of pre-allocated buffers) and write GPU
125specific commands in it to perform the update (unmap, cache invalidations, and
126flush, ...). This cannot be done through common code for all devices. Hence
127why HMM provides helpers to factor out everything that can be while leaving the
128hardware specific details to the device driver.
129
130The second mechanism HMM provides is a new kind of ZONE_DEVICE memory that
131allows allocating a struct page for each page of the device memory. Those pages
132are special because the CPU cannot map them. However, they allow migrating
133main memory to device memory using existing migration mechanisms and everything
134looks like a page is swapped out to disk from the CPU point of view. Using a
135struct page gives the easiest and cleanest integration with existing mm mech-
136anisms. Here again, HMM only provides helpers, first to hotplug new ZONE_DEVICE
137memory for the device memory and second to perform migration. Policy decisions
138of what and when to migrate things is left to the device driver.
139
140Note that any CPU access to a device page triggers a page fault and a migration
141back to main memory. For example, when a page backing a given CPU address A is
142migrated from a main memory page to a device page, then any CPU access to
143address A triggers a page fault and initiates a migration back to main memory.
144
145With these two features, HMM not only allows a device to mirror process address
146space and keeping both CPU and device page table synchronized, but also lever-
147ages device memory by migrating the part of the data set that is actively being
148used by the device.
149
150
151-------------------------------------------------------------------------------
152
1534) Address space mirroring implementation and API
154
155Address space mirroring's main objective is to allow duplication of a range of
156CPU page table into a device page table; HMM helps keep both synchronized. A
157device driver that wants to mirror a process address space must start with the
158registration of an hmm_mirror struct:
159
160 int hmm_mirror_register(struct hmm_mirror *mirror,
161 struct mm_struct *mm);
162 int hmm_mirror_register_locked(struct hmm_mirror *mirror,
163 struct mm_struct *mm);
164
165The locked variant is to be used when the driver is already holding mmap_sem
166of the mm in write mode. The mirror struct has a set of callbacks that are used
167to propagate CPU page tables:
168
169 struct hmm_mirror_ops {
170 /* sync_cpu_device_pagetables() - synchronize page tables
171 *
172 * @mirror: pointer to struct hmm_mirror
173 * @update_type: type of update that occurred to the CPU page table
174 * @start: virtual start address of the range to update
175 * @end: virtual end address of the range to update
176 *
177 * This callback ultimately originates from mmu_notifiers when the CPU
178 * page table is updated. The device driver must update its page table
179 * in response to this callback. The update argument tells what action
180 * to perform.
181 *
182 * The device driver must not return from this callback until the device
183 * page tables are completely updated (TLBs flushed, etc); this is a
184 * synchronous call.
185 */
186 void (*update)(struct hmm_mirror *mirror,
187 enum hmm_update action,
188 unsigned long start,
189 unsigned long end);
190 };
191
192The device driver must perform the update action to the range (mark range
193read only, or fully unmap, ...). The device must be done with the update before
194the driver callback returns.
195
196
197When the device driver wants to populate a range of virtual addresses, it can
198use either:
199 int hmm_vma_get_pfns(struct vm_area_struct *vma,
200 struct hmm_range *range,
201 unsigned long start,
202 unsigned long end,
203 hmm_pfn_t *pfns);
204 int hmm_vma_fault(struct vm_area_struct *vma,
205 struct hmm_range *range,
206 unsigned long start,
207 unsigned long end,
208 hmm_pfn_t *pfns,
209 bool write,
210 bool block);
211
212The first one (hmm_vma_get_pfns()) will only fetch present CPU page table
213entries and will not trigger a page fault on missing or non-present entries.
214The second one does trigger a page fault on missing or read-only entry if the
215write parameter is true. Page faults use the generic mm page fault code path
216just like a CPU page fault.
217
218Both functions copy CPU page table entries into their pfns array argument. Each
219entry in that array corresponds to an address in the virtual range. HMM
220provides a set of flags to help the driver identify special CPU page table
221entries.
222
223Locking with the update() callback is the most important aspect the driver must
224respect in order to keep things properly synchronized. The usage pattern is:
225
226 int driver_populate_range(...)
227 {
228 struct hmm_range range;
229 ...
230 again:
231 ret = hmm_vma_get_pfns(vma, &range, start, end, pfns);
232 if (ret)
233 return ret;
234 take_lock(driver->update);
235 if (!hmm_vma_range_done(vma, &range)) {
236 release_lock(driver->update);
237 goto again;
238 }
239
240 // Use pfns array content to update device page table
241
242 release_lock(driver->update);
243 return 0;
244 }
245
246The driver->update lock is the same lock that the driver takes inside its
247update() callback. That lock must be held before hmm_vma_range_done() to avoid
248any race with a concurrent CPU page table update.
249
250HMM implements all this on top of the mmu_notifier API because we wanted a
251simpler API and also to be able to perform optimizations latter on like doing
252concurrent device updates in multi-devices scenario.
253
254HMM also serves as an impedance mismatch between how CPU page table updates
255are done (by CPU write to the page table and TLB flushes) and how devices
256update their own page table. Device updates are a multi-step process. First,
257appropriate commands are written to a buffer, then this buffer is scheduled for
258execution on the device. It is only once the device has executed commands in
259the buffer that the update is done. Creating and scheduling the update command
260buffer can happen concurrently for multiple devices. Waiting for each device to
261report commands as executed is serialized (there is no point in doing this
262concurrently).
263
264
265-------------------------------------------------------------------------------
266
2675) Represent and manage device memory from core kernel point of view
268
269Several different designs were tried to support device memory. First one used
270a device specific data structure to keep information about migrated memory and
271HMM hooked itself in various places of mm code to handle any access to
272addresses that were backed by device memory. It turns out that this ended up
273replicating most of the fields of struct page and also needed many kernel code
274paths to be updated to understand this new kind of memory.
275
276Most kernel code paths never try to access the memory behind a page
277but only care about struct page contents. Because of this, HMM switched to
278directly using struct page for device memory which left most kernel code paths
279unaware of the difference. We only need to make sure that no one ever tries to
280map those pages from the CPU side.
281
282HMM provides a set of helpers to register and hotplug device memory as a new
283region needing a struct page. This is offered through a very simple API:
284
285 struct hmm_devmem *hmm_devmem_add(const struct hmm_devmem_ops *ops,
286 struct device *device,
287 unsigned long size);
288 void hmm_devmem_remove(struct hmm_devmem *devmem);
289
290The hmm_devmem_ops is where most of the important things are:
291
292 struct hmm_devmem_ops {
293 void (*free)(struct hmm_devmem *devmem, struct page *page);
294 int (*fault)(struct hmm_devmem *devmem,
295 struct vm_area_struct *vma,
296 unsigned long addr,
297 struct page *page,
298 unsigned flags,
299 pmd_t *pmdp);
300 };
301
302The first callback (free()) happens when the last reference on a device page is
303dropped. This means the device page is now free and no longer used by anyone.
304The second callback happens whenever the CPU tries to access a device page
305which it cannot do. This second callback must trigger a migration back to
306system memory.
307
308
309-------------------------------------------------------------------------------
310
3116) Migration to and from device memory
312
313Because the CPU cannot access device memory, migration must use the device DMA
314engine to perform copy from and to device memory. For this we need a new
315migration helper:
316
317 int migrate_vma(const struct migrate_vma_ops *ops,
318 struct vm_area_struct *vma,
319 unsigned long mentries,
320 unsigned long start,
321 unsigned long end,
322 unsigned long *src,
323 unsigned long *dst,
324 void *private);
325
326Unlike other migration functions it works on a range of virtual address, there
327are two reasons for that. First, device DMA copy has a high setup overhead cost
328and thus batching multiple pages is needed as otherwise the migration overhead
329makes the whole exercise pointless. The second reason is because the
330migration might be for a range of addresses the device is actively accessing.
331
332The migrate_vma_ops struct defines two callbacks. First one (alloc_and_copy())
333controls destination memory allocation and copy operation. Second one is there
334to allow the device driver to perform cleanup operations after migration.
335
336 struct migrate_vma_ops {
337 void (*alloc_and_copy)(struct vm_area_struct *vma,
338 const unsigned long *src,
339 unsigned long *dst,
340 unsigned long start,
341 unsigned long end,
342 void *private);
343 void (*finalize_and_map)(struct vm_area_struct *vma,
344 const unsigned long *src,
345 const unsigned long *dst,
346 unsigned long start,
347 unsigned long end,
348 void *private);
349 };
350
351It is important to stress that these migration helpers allow for holes in the
352virtual address range. Some pages in the range might not be migrated for all
353the usual reasons (page is pinned, page is locked, ...). This helper does not
354fail but just skips over those pages.
355
356The alloc_and_copy() might decide to not migrate all pages in the
357range (for reasons under the callback control). For those, the callback just
358has to leave the corresponding dst entry empty.
359
360Finally, the migration of the struct page might fail (for file backed page) for
361various reasons (failure to freeze reference, or update page cache, ...). If
362that happens, then the finalize_and_map() can catch any pages that were not
363migrated. Note those pages were still copied to a new page and thus we wasted
364bandwidth but this is considered as a rare event and a price that we are
365willing to pay to keep all the code simpler.
366
367
368-------------------------------------------------------------------------------
369
3707) Memory cgroup (memcg) and rss accounting
371
372For now device memory is accounted as any regular page in rss counters (either
373anonymous if device page is used for anonymous, file if device page is used for
374file backed page or shmem if device page is used for shared memory). This is a
375deliberate choice to keep existing applications, that might start using device
376memory without knowing about it, running unimpacted.
377
378A drawback is that the OOM killer might kill an application using a lot of
379device memory and not a lot of regular system memory and thus not freeing much
380system memory. We want to gather more real world experience on how applications
381and system react under memory pressure in the presence of device memory before
382deciding to account device memory differently.
383
384
385Same decision was made for memory cgroup. Device memory pages are accounted
386against same memory cgroup a regular page would be accounted to. This does
387simplify migration to and from device memory. This also means that migration
388back from device memory to regular memory cannot fail because it would
389go above memory cgroup limit. We might revisit this choice latter on once we
390get more experience in how device memory is used and its impact on memory
391resource control.
392
393
394Note that device memory can never be pinned by device driver nor through GUP
395and thus such memory is always free upon process exit. Or when last reference
396is dropped in case of shared memory or file backed memory.