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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Generic barrier definitions.
4 *
5 * It should be possible to use these on really simple architectures,
6 * but it serves more as a starting point for new ports.
7 *
8 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
9 * Written by David Howells (dhowells@redhat.com)
10 */
11#ifndef __ASM_GENERIC_BARRIER_H
12#define __ASM_GENERIC_BARRIER_H
13
14#ifndef __ASSEMBLY__
15
16#include <linux/compiler.h>
17#include <linux/kcsan-checks.h>
18#include <asm/rwonce.h>
19
20#ifndef nop
21#define nop() asm volatile ("nop")
22#endif
23
24/*
25 * Architectures that want generic instrumentation can define __ prefixed
26 * variants of all barriers.
27 */
28
29#ifdef __mb
30#define mb() do { kcsan_mb(); __mb(); } while (0)
31#endif
32
33#ifdef __rmb
34#define rmb() do { kcsan_rmb(); __rmb(); } while (0)
35#endif
36
37#ifdef __wmb
38#define wmb() do { kcsan_wmb(); __wmb(); } while (0)
39#endif
40
41#ifdef __dma_mb
42#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0)
43#endif
44
45#ifdef __dma_rmb
46#define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0)
47#endif
48
49#ifdef __dma_wmb
50#define dma_wmb() do { kcsan_wmb(); __dma_wmb(); } while (0)
51#endif
52
53/*
54 * Force strict CPU ordering. And yes, this is required on UP too when we're
55 * talking to devices.
56 *
57 * Fall back to compiler barriers if nothing better is provided.
58 */
59
60#ifndef mb
61#define mb() barrier()
62#endif
63
64#ifndef rmb
65#define rmb() mb()
66#endif
67
68#ifndef wmb
69#define wmb() mb()
70#endif
71
72#ifndef dma_mb
73#define dma_mb() mb()
74#endif
75
76#ifndef dma_rmb
77#define dma_rmb() rmb()
78#endif
79
80#ifndef dma_wmb
81#define dma_wmb() wmb()
82#endif
83
84#ifndef __smp_mb
85#define __smp_mb() mb()
86#endif
87
88#ifndef __smp_rmb
89#define __smp_rmb() rmb()
90#endif
91
92#ifndef __smp_wmb
93#define __smp_wmb() wmb()
94#endif
95
96#ifdef CONFIG_SMP
97
98#ifndef smp_mb
99#define smp_mb() do { kcsan_mb(); __smp_mb(); } while (0)
100#endif
101
102#ifndef smp_rmb
103#define smp_rmb() do { kcsan_rmb(); __smp_rmb(); } while (0)
104#endif
105
106#ifndef smp_wmb
107#define smp_wmb() do { kcsan_wmb(); __smp_wmb(); } while (0)
108#endif
109
110#else /* !CONFIG_SMP */
111
112#ifndef smp_mb
113#define smp_mb() barrier()
114#endif
115
116#ifndef smp_rmb
117#define smp_rmb() barrier()
118#endif
119
120#ifndef smp_wmb
121#define smp_wmb() barrier()
122#endif
123
124#endif /* CONFIG_SMP */
125
126#ifndef __smp_store_mb
127#define __smp_store_mb(var, value) do { WRITE_ONCE(var, value); __smp_mb(); } while (0)
128#endif
129
130#ifndef __smp_mb__before_atomic
131#define __smp_mb__before_atomic() __smp_mb()
132#endif
133
134#ifndef __smp_mb__after_atomic
135#define __smp_mb__after_atomic() __smp_mb()
136#endif
137
138#ifndef __smp_store_release
139#define __smp_store_release(p, v) \
140do { \
141 compiletime_assert_atomic_type(*p); \
142 __smp_mb(); \
143 WRITE_ONCE(*p, v); \
144} while (0)
145#endif
146
147#ifndef __smp_load_acquire
148#define __smp_load_acquire(p) \
149({ \
150 __unqual_scalar_typeof(*p) ___p1 = READ_ONCE(*p); \
151 compiletime_assert_atomic_type(*p); \
152 __smp_mb(); \
153 (typeof(*p))___p1; \
154})
155#endif
156
157#ifdef CONFIG_SMP
158
159#ifndef smp_store_mb
160#define smp_store_mb(var, value) do { kcsan_mb(); __smp_store_mb(var, value); } while (0)
161#endif
162
163#ifndef smp_mb__before_atomic
164#define smp_mb__before_atomic() do { kcsan_mb(); __smp_mb__before_atomic(); } while (0)
165#endif
166
167#ifndef smp_mb__after_atomic
168#define smp_mb__after_atomic() do { kcsan_mb(); __smp_mb__after_atomic(); } while (0)
169#endif
170
171#ifndef smp_store_release
172#define smp_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
173#endif
174
175#ifndef smp_load_acquire
176#define smp_load_acquire(p) __smp_load_acquire(p)
177#endif
178
179#else /* !CONFIG_SMP */
180
181#ifndef smp_store_mb
182#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
183#endif
184
185#ifndef smp_mb__before_atomic
186#define smp_mb__before_atomic() barrier()
187#endif
188
189#ifndef smp_mb__after_atomic
190#define smp_mb__after_atomic() barrier()
191#endif
192
193#ifndef smp_store_release
194#define smp_store_release(p, v) \
195do { \
196 barrier(); \
197 WRITE_ONCE(*p, v); \
198} while (0)
199#endif
200
201#ifndef smp_load_acquire
202#define smp_load_acquire(p) \
203({ \
204 __unqual_scalar_typeof(*p) ___p1 = READ_ONCE(*p); \
205 barrier(); \
206 (typeof(*p))___p1; \
207})
208#endif
209
210#endif /* CONFIG_SMP */
211
212/* Barriers for virtual machine guests when talking to an SMP host */
213#define virt_mb() do { kcsan_mb(); __smp_mb(); } while (0)
214#define virt_rmb() do { kcsan_rmb(); __smp_rmb(); } while (0)
215#define virt_wmb() do { kcsan_wmb(); __smp_wmb(); } while (0)
216#define virt_store_mb(var, value) do { kcsan_mb(); __smp_store_mb(var, value); } while (0)
217#define virt_mb__before_atomic() do { kcsan_mb(); __smp_mb__before_atomic(); } while (0)
218#define virt_mb__after_atomic() do { kcsan_mb(); __smp_mb__after_atomic(); } while (0)
219#define virt_store_release(p, v) do { kcsan_release(); __smp_store_release(p, v); } while (0)
220#define virt_load_acquire(p) __smp_load_acquire(p)
221
222/**
223 * smp_acquire__after_ctrl_dep() - Provide ACQUIRE ordering after a control dependency
224 *
225 * A control dependency provides a LOAD->STORE order, the additional RMB
226 * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,
227 * aka. (load)-ACQUIRE.
228 *
229 * Architectures that do not do load speculation can have this be barrier().
230 */
231#ifndef smp_acquire__after_ctrl_dep
232#define smp_acquire__after_ctrl_dep() smp_rmb()
233#endif
234
235/**
236 * smp_cond_load_relaxed() - (Spin) wait for cond with no ordering guarantees
237 * @ptr: pointer to the variable to wait on
238 * @cond: boolean expression to wait for
239 *
240 * Equivalent to using READ_ONCE() on the condition variable.
241 *
242 * Due to C lacking lambda expressions we load the value of *ptr into a
243 * pre-named variable @VAL to be used in @cond.
244 */
245#ifndef smp_cond_load_relaxed
246#define smp_cond_load_relaxed(ptr, cond_expr) ({ \
247 typeof(ptr) __PTR = (ptr); \
248 __unqual_scalar_typeof(*ptr) VAL; \
249 for (;;) { \
250 VAL = READ_ONCE(*__PTR); \
251 if (cond_expr) \
252 break; \
253 cpu_relax(); \
254 } \
255 (typeof(*ptr))VAL; \
256})
257#endif
258
259/**
260 * smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering
261 * @ptr: pointer to the variable to wait on
262 * @cond: boolean expression to wait for
263 *
264 * Equivalent to using smp_load_acquire() on the condition variable but employs
265 * the control dependency of the wait to reduce the barrier on many platforms.
266 */
267#ifndef smp_cond_load_acquire
268#define smp_cond_load_acquire(ptr, cond_expr) ({ \
269 __unqual_scalar_typeof(*ptr) _val; \
270 _val = smp_cond_load_relaxed(ptr, cond_expr); \
271 smp_acquire__after_ctrl_dep(); \
272 (typeof(*ptr))_val; \
273})
274#endif
275
276/*
277 * pmem_wmb() ensures that all stores for which the modification
278 * are written to persistent storage by preceding instructions have
279 * updated persistent storage before any data access or data transfer
280 * caused by subsequent instructions is initiated.
281 */
282#ifndef pmem_wmb
283#define pmem_wmb() wmb()
284#endif
285
286/*
287 * ioremap_wc() maps I/O memory as memory with write-combining attributes. For
288 * this kind of memory accesses, the CPU may wait for prior accesses to be
289 * merged with subsequent ones. In some situation, such wait is bad for the
290 * performance. io_stop_wc() can be used to prevent the merging of
291 * write-combining memory accesses before this macro with those after it.
292 */
293#ifndef io_stop_wc
294#define io_stop_wc() do { } while (0)
295#endif
296
297/*
298 * Architectures that guarantee an implicit smp_mb() in switch_mm()
299 * can override smp_mb__after_switch_mm.
300 */
301#ifndef smp_mb__after_switch_mm
302# define smp_mb__after_switch_mm() smp_mb()
303#endif
304
305#endif /* !__ASSEMBLY__ */
306#endif /* __ASM_GENERIC_BARRIER_H */
1/*
2 * Generic barrier definitions.
3 *
4 * It should be possible to use these on really simple architectures,
5 * but it serves more as a starting point for new ports.
6 *
7 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
8 * Written by David Howells (dhowells@redhat.com)
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public Licence
12 * as published by the Free Software Foundation; either version
13 * 2 of the Licence, or (at your option) any later version.
14 */
15#ifndef __ASM_GENERIC_BARRIER_H
16#define __ASM_GENERIC_BARRIER_H
17
18#ifndef __ASSEMBLY__
19
20#include <linux/compiler.h>
21
22#ifndef nop
23#define nop() asm volatile ("nop")
24#endif
25
26/*
27 * Force strict CPU ordering. And yes, this is required on UP too when we're
28 * talking to devices.
29 *
30 * Fall back to compiler barriers if nothing better is provided.
31 */
32
33#ifndef mb
34#define mb() barrier()
35#endif
36
37#ifndef rmb
38#define rmb() mb()
39#endif
40
41#ifndef wmb
42#define wmb() mb()
43#endif
44
45#ifndef dma_rmb
46#define dma_rmb() rmb()
47#endif
48
49#ifndef dma_wmb
50#define dma_wmb() wmb()
51#endif
52
53#ifndef read_barrier_depends
54#define read_barrier_depends() do { } while (0)
55#endif
56
57#ifndef __smp_mb
58#define __smp_mb() mb()
59#endif
60
61#ifndef __smp_rmb
62#define __smp_rmb() rmb()
63#endif
64
65#ifndef __smp_wmb
66#define __smp_wmb() wmb()
67#endif
68
69#ifndef __smp_read_barrier_depends
70#define __smp_read_barrier_depends() read_barrier_depends()
71#endif
72
73#ifdef CONFIG_SMP
74
75#ifndef smp_mb
76#define smp_mb() __smp_mb()
77#endif
78
79#ifndef smp_rmb
80#define smp_rmb() __smp_rmb()
81#endif
82
83#ifndef smp_wmb
84#define smp_wmb() __smp_wmb()
85#endif
86
87#ifndef smp_read_barrier_depends
88#define smp_read_barrier_depends() __smp_read_barrier_depends()
89#endif
90
91#else /* !CONFIG_SMP */
92
93#ifndef smp_mb
94#define smp_mb() barrier()
95#endif
96
97#ifndef smp_rmb
98#define smp_rmb() barrier()
99#endif
100
101#ifndef smp_wmb
102#define smp_wmb() barrier()
103#endif
104
105#ifndef smp_read_barrier_depends
106#define smp_read_barrier_depends() do { } while (0)
107#endif
108
109#endif /* CONFIG_SMP */
110
111#ifndef __smp_store_mb
112#define __smp_store_mb(var, value) do { WRITE_ONCE(var, value); __smp_mb(); } while (0)
113#endif
114
115#ifndef __smp_mb__before_atomic
116#define __smp_mb__before_atomic() __smp_mb()
117#endif
118
119#ifndef __smp_mb__after_atomic
120#define __smp_mb__after_atomic() __smp_mb()
121#endif
122
123#ifndef __smp_store_release
124#define __smp_store_release(p, v) \
125do { \
126 compiletime_assert_atomic_type(*p); \
127 __smp_mb(); \
128 WRITE_ONCE(*p, v); \
129} while (0)
130#endif
131
132#ifndef __smp_load_acquire
133#define __smp_load_acquire(p) \
134({ \
135 typeof(*p) ___p1 = READ_ONCE(*p); \
136 compiletime_assert_atomic_type(*p); \
137 __smp_mb(); \
138 ___p1; \
139})
140#endif
141
142#ifdef CONFIG_SMP
143
144#ifndef smp_store_mb
145#define smp_store_mb(var, value) __smp_store_mb(var, value)
146#endif
147
148#ifndef smp_mb__before_atomic
149#define smp_mb__before_atomic() __smp_mb__before_atomic()
150#endif
151
152#ifndef smp_mb__after_atomic
153#define smp_mb__after_atomic() __smp_mb__after_atomic()
154#endif
155
156#ifndef smp_store_release
157#define smp_store_release(p, v) __smp_store_release(p, v)
158#endif
159
160#ifndef smp_load_acquire
161#define smp_load_acquire(p) __smp_load_acquire(p)
162#endif
163
164#else /* !CONFIG_SMP */
165
166#ifndef smp_store_mb
167#define smp_store_mb(var, value) do { WRITE_ONCE(var, value); barrier(); } while (0)
168#endif
169
170#ifndef smp_mb__before_atomic
171#define smp_mb__before_atomic() barrier()
172#endif
173
174#ifndef smp_mb__after_atomic
175#define smp_mb__after_atomic() barrier()
176#endif
177
178#ifndef smp_store_release
179#define smp_store_release(p, v) \
180do { \
181 compiletime_assert_atomic_type(*p); \
182 barrier(); \
183 WRITE_ONCE(*p, v); \
184} while (0)
185#endif
186
187#ifndef smp_load_acquire
188#define smp_load_acquire(p) \
189({ \
190 typeof(*p) ___p1 = READ_ONCE(*p); \
191 compiletime_assert_atomic_type(*p); \
192 barrier(); \
193 ___p1; \
194})
195#endif
196
197#endif /* CONFIG_SMP */
198
199/* Barriers for virtual machine guests when talking to an SMP host */
200#define virt_mb() __smp_mb()
201#define virt_rmb() __smp_rmb()
202#define virt_wmb() __smp_wmb()
203#define virt_read_barrier_depends() __smp_read_barrier_depends()
204#define virt_store_mb(var, value) __smp_store_mb(var, value)
205#define virt_mb__before_atomic() __smp_mb__before_atomic()
206#define virt_mb__after_atomic() __smp_mb__after_atomic()
207#define virt_store_release(p, v) __smp_store_release(p, v)
208#define virt_load_acquire(p) __smp_load_acquire(p)
209
210/**
211 * smp_acquire__after_ctrl_dep() - Provide ACQUIRE ordering after a control dependency
212 *
213 * A control dependency provides a LOAD->STORE order, the additional RMB
214 * provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,
215 * aka. (load)-ACQUIRE.
216 *
217 * Architectures that do not do load speculation can have this be barrier().
218 */
219#ifndef smp_acquire__after_ctrl_dep
220#define smp_acquire__after_ctrl_dep() smp_rmb()
221#endif
222
223/**
224 * smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering
225 * @ptr: pointer to the variable to wait on
226 * @cond: boolean expression to wait for
227 *
228 * Equivalent to using smp_load_acquire() on the condition variable but employs
229 * the control dependency of the wait to reduce the barrier on many platforms.
230 *
231 * Due to C lacking lambda expressions we load the value of *ptr into a
232 * pre-named variable @VAL to be used in @cond.
233 */
234#ifndef smp_cond_load_acquire
235#define smp_cond_load_acquire(ptr, cond_expr) ({ \
236 typeof(ptr) __PTR = (ptr); \
237 typeof(*ptr) VAL; \
238 for (;;) { \
239 VAL = READ_ONCE(*__PTR); \
240 if (cond_expr) \
241 break; \
242 cpu_relax(); \
243 } \
244 smp_acquire__after_ctrl_dep(); \
245 VAL; \
246})
247#endif
248
249#endif /* !__ASSEMBLY__ */
250#endif /* __ASM_GENERIC_BARRIER_H */