Loading...
1// SPDX-License-Identifier: GPL-2.0+
2// Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3// Copyright (C) 2008 Juergen Beisert
4
5#include <linux/bits.h>
6#include <linux/bitfield.h>
7#include <linux/clk.h>
8#include <linux/completion.h>
9#include <linux/delay.h>
10#include <linux/dmaengine.h>
11#include <linux/dma-mapping.h>
12#include <linux/err.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/kernel.h>
17#include <linux/math.h>
18#include <linux/math64.h>
19#include <linux/module.h>
20#include <linux/overflow.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/platform_device.h>
23#include <linux/pm_runtime.h>
24#include <linux/slab.h>
25#include <linux/spi/spi.h>
26#include <linux/types.h>
27#include <linux/of.h>
28#include <linux/property.h>
29
30#include <linux/dma/imx-dma.h>
31
32#define DRIVER_NAME "spi_imx"
33
34static bool use_dma = true;
35module_param(use_dma, bool, 0644);
36MODULE_PARM_DESC(use_dma, "Enable usage of DMA when available (default)");
37
38/* define polling limits */
39static unsigned int polling_limit_us = 30;
40module_param(polling_limit_us, uint, 0664);
41MODULE_PARM_DESC(polling_limit_us,
42 "time in us to run a transfer in polling mode\n");
43
44#define MXC_RPM_TIMEOUT 2000 /* 2000ms */
45
46#define MXC_CSPIRXDATA 0x00
47#define MXC_CSPITXDATA 0x04
48#define MXC_CSPICTRL 0x08
49#define MXC_CSPIINT 0x0c
50#define MXC_RESET 0x1c
51
52/* generic defines to abstract from the different register layouts */
53#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
54#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
55#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
56
57/* The maximum bytes that a sdma BD can transfer. */
58#define MAX_SDMA_BD_BYTES (1 << 15)
59#define MX51_ECSPI_CTRL_MAX_BURST 512
60/* The maximum bytes that IMX53_ECSPI can transfer in target mode.*/
61#define MX53_MAX_TRANSFER_BYTES 512
62
63enum spi_imx_devtype {
64 IMX1_CSPI,
65 IMX21_CSPI,
66 IMX27_CSPI,
67 IMX31_CSPI,
68 IMX35_CSPI, /* CSPI on all i.mx except above */
69 IMX51_ECSPI, /* ECSPI on i.mx51 */
70 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
71};
72
73struct spi_imx_data;
74
75struct spi_imx_devtype_data {
76 void (*intctrl)(struct spi_imx_data *spi_imx, int enable);
77 int (*prepare_message)(struct spi_imx_data *spi_imx, struct spi_message *msg);
78 int (*prepare_transfer)(struct spi_imx_data *spi_imx, struct spi_device *spi,
79 struct spi_transfer *t);
80 void (*trigger)(struct spi_imx_data *spi_imx);
81 int (*rx_available)(struct spi_imx_data *spi_imx);
82 void (*reset)(struct spi_imx_data *spi_imx);
83 void (*setup_wml)(struct spi_imx_data *spi_imx);
84 void (*disable)(struct spi_imx_data *spi_imx);
85 bool has_dmamode;
86 bool has_targetmode;
87 unsigned int fifo_size;
88 bool dynamic_burst;
89 /*
90 * ERR009165 fixed or not:
91 * https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf
92 */
93 bool tx_glitch_fixed;
94 enum spi_imx_devtype devtype;
95};
96
97struct spi_imx_data {
98 struct spi_controller *controller;
99 struct device *dev;
100
101 struct completion xfer_done;
102 void __iomem *base;
103 unsigned long base_phys;
104
105 struct clk *clk_per;
106 struct clk *clk_ipg;
107 unsigned long spi_clk;
108 unsigned int spi_bus_clk;
109
110 unsigned int bits_per_word;
111 unsigned int spi_drctl;
112
113 unsigned int count, remainder;
114 void (*tx)(struct spi_imx_data *spi_imx);
115 void (*rx)(struct spi_imx_data *spi_imx);
116 void *rx_buf;
117 const void *tx_buf;
118 unsigned int txfifo; /* number of words pushed in tx FIFO */
119 unsigned int dynamic_burst;
120 bool rx_only;
121
122 /* Target mode */
123 bool target_mode;
124 bool target_aborted;
125 unsigned int target_burst;
126
127 /* DMA */
128 bool usedma;
129 u32 wml;
130 struct completion dma_rx_completion;
131 struct completion dma_tx_completion;
132
133 const struct spi_imx_devtype_data *devtype_data;
134};
135
136static inline int is_imx27_cspi(struct spi_imx_data *d)
137{
138 return d->devtype_data->devtype == IMX27_CSPI;
139}
140
141static inline int is_imx35_cspi(struct spi_imx_data *d)
142{
143 return d->devtype_data->devtype == IMX35_CSPI;
144}
145
146static inline int is_imx51_ecspi(struct spi_imx_data *d)
147{
148 return d->devtype_data->devtype == IMX51_ECSPI;
149}
150
151static inline int is_imx53_ecspi(struct spi_imx_data *d)
152{
153 return d->devtype_data->devtype == IMX53_ECSPI;
154}
155
156#define MXC_SPI_BUF_RX(type) \
157static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
158{ \
159 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
160 \
161 if (spi_imx->rx_buf) { \
162 *(type *)spi_imx->rx_buf = val; \
163 spi_imx->rx_buf += sizeof(type); \
164 } \
165 \
166 spi_imx->remainder -= sizeof(type); \
167}
168
169#define MXC_SPI_BUF_TX(type) \
170static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
171{ \
172 type val = 0; \
173 \
174 if (spi_imx->tx_buf) { \
175 val = *(type *)spi_imx->tx_buf; \
176 spi_imx->tx_buf += sizeof(type); \
177 } \
178 \
179 spi_imx->count -= sizeof(type); \
180 \
181 writel(val, spi_imx->base + MXC_CSPITXDATA); \
182}
183
184MXC_SPI_BUF_RX(u8)
185MXC_SPI_BUF_TX(u8)
186MXC_SPI_BUF_RX(u16)
187MXC_SPI_BUF_TX(u16)
188MXC_SPI_BUF_RX(u32)
189MXC_SPI_BUF_TX(u32)
190
191/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
192 * (which is currently not the case in this driver)
193 */
194static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
195 256, 384, 512, 768, 1024};
196
197/* MX21, MX27 */
198static unsigned int spi_imx_clkdiv_1(unsigned int fin,
199 unsigned int fspi, unsigned int max, unsigned int *fres)
200{
201 int i;
202
203 for (i = 2; i < max; i++)
204 if (fspi * mxc_clkdivs[i] >= fin)
205 break;
206
207 *fres = fin / mxc_clkdivs[i];
208 return i;
209}
210
211/* MX1, MX31, MX35, MX51 CSPI */
212static unsigned int spi_imx_clkdiv_2(unsigned int fin,
213 unsigned int fspi, unsigned int *fres)
214{
215 int i, div = 4;
216
217 for (i = 0; i < 7; i++) {
218 if (fspi * div >= fin)
219 goto out;
220 div <<= 1;
221 }
222
223out:
224 *fres = fin / div;
225 return i;
226}
227
228static int spi_imx_bytes_per_word(const int bits_per_word)
229{
230 if (bits_per_word <= 8)
231 return 1;
232 else if (bits_per_word <= 16)
233 return 2;
234 else
235 return 4;
236}
237
238static bool spi_imx_can_dma(struct spi_controller *controller, struct spi_device *spi,
239 struct spi_transfer *transfer)
240{
241 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
242
243 if (!use_dma || controller->fallback)
244 return false;
245
246 if (!controller->dma_rx)
247 return false;
248
249 if (spi_imx->target_mode)
250 return false;
251
252 if (transfer->len < spi_imx->devtype_data->fifo_size)
253 return false;
254
255 spi_imx->dynamic_burst = 0;
256
257 return true;
258}
259
260/*
261 * Note the number of natively supported chip selects for MX51 is 4. Some
262 * devices may have less actual SS pins but the register map supports 4. When
263 * using gpio chip selects the cs values passed into the macros below can go
264 * outside the range 0 - 3. We therefore need to limit the cs value to avoid
265 * corrupting bits outside the allocated locations.
266 *
267 * The simplest way to do this is to just mask the cs bits to 2 bits. This
268 * still allows all 4 native chip selects to work as well as gpio chip selects
269 * (which can use any of the 4 chip select configurations).
270 */
271
272#define MX51_ECSPI_CTRL 0x08
273#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
274#define MX51_ECSPI_CTRL_XCH (1 << 2)
275#define MX51_ECSPI_CTRL_SMC (1 << 3)
276#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
277#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
278#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
279#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
280#define MX51_ECSPI_CTRL_CS(cs) ((cs & 3) << 18)
281#define MX51_ECSPI_CTRL_BL_OFFSET 20
282#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
283
284#define MX51_ECSPI_CONFIG 0x0c
285#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs & 3) + 0))
286#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs & 3) + 4))
287#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs & 3) + 8))
288#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs & 3) + 12))
289#define MX51_ECSPI_CONFIG_DATACTL(cs) (1 << ((cs & 3) + 16))
290#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs & 3) + 20))
291
292#define MX51_ECSPI_INT 0x10
293#define MX51_ECSPI_INT_TEEN (1 << 0)
294#define MX51_ECSPI_INT_RREN (1 << 3)
295#define MX51_ECSPI_INT_RDREN (1 << 4)
296
297#define MX51_ECSPI_DMA 0x14
298#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
299#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
300#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
301
302#define MX51_ECSPI_DMA_TEDEN (1 << 7)
303#define MX51_ECSPI_DMA_RXDEN (1 << 23)
304#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
305
306#define MX51_ECSPI_STAT 0x18
307#define MX51_ECSPI_STAT_RR (1 << 3)
308
309#define MX51_ECSPI_PERIOD 0x1c
310#define MX51_ECSPI_PERIOD_MASK 0x7fff
311/*
312 * As measured on the i.MX6, the SPI host controller inserts a 4 SPI-Clock
313 * (SCLK) delay after each burst if the PERIOD reg is 0x0. This value will be
314 * called MX51_ECSPI_PERIOD_MIN_DELAY_SCK.
315 *
316 * If the PERIOD register is != 0, the controller inserts a delay of
317 * MX51_ECSPI_PERIOD_MIN_DELAY_SCK + register value + 1 SCLK after each burst.
318 */
319#define MX51_ECSPI_PERIOD_MIN_DELAY_SCK 4
320
321#define MX51_ECSPI_TESTREG 0x20
322#define MX51_ECSPI_TESTREG_LBC BIT(31)
323
324static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
325{
326 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
327
328 if (spi_imx->rx_buf) {
329#ifdef __LITTLE_ENDIAN
330 unsigned int bytes_per_word;
331
332 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
333 if (bytes_per_word == 1)
334 swab32s(&val);
335 else if (bytes_per_word == 2)
336 swahw32s(&val);
337#endif
338 *(u32 *)spi_imx->rx_buf = val;
339 spi_imx->rx_buf += sizeof(u32);
340 }
341
342 spi_imx->remainder -= sizeof(u32);
343}
344
345static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
346{
347 int unaligned;
348 u32 val;
349
350 unaligned = spi_imx->remainder % 4;
351
352 if (!unaligned) {
353 spi_imx_buf_rx_swap_u32(spi_imx);
354 return;
355 }
356
357 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
358 spi_imx_buf_rx_u16(spi_imx);
359 return;
360 }
361
362 val = readl(spi_imx->base + MXC_CSPIRXDATA);
363
364 while (unaligned--) {
365 if (spi_imx->rx_buf) {
366 *(u8 *)spi_imx->rx_buf = (val >> (8 * unaligned)) & 0xff;
367 spi_imx->rx_buf++;
368 }
369 spi_imx->remainder--;
370 }
371}
372
373static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
374{
375 u32 val = 0;
376#ifdef __LITTLE_ENDIAN
377 unsigned int bytes_per_word;
378#endif
379
380 if (spi_imx->tx_buf) {
381 val = *(u32 *)spi_imx->tx_buf;
382 spi_imx->tx_buf += sizeof(u32);
383 }
384
385 spi_imx->count -= sizeof(u32);
386#ifdef __LITTLE_ENDIAN
387 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
388
389 if (bytes_per_word == 1)
390 swab32s(&val);
391 else if (bytes_per_word == 2)
392 swahw32s(&val);
393#endif
394 writel(val, spi_imx->base + MXC_CSPITXDATA);
395}
396
397static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
398{
399 int unaligned;
400 u32 val = 0;
401
402 unaligned = spi_imx->count % 4;
403
404 if (!unaligned) {
405 spi_imx_buf_tx_swap_u32(spi_imx);
406 return;
407 }
408
409 if (spi_imx_bytes_per_word(spi_imx->bits_per_word) == 2) {
410 spi_imx_buf_tx_u16(spi_imx);
411 return;
412 }
413
414 while (unaligned--) {
415 if (spi_imx->tx_buf) {
416 val |= *(u8 *)spi_imx->tx_buf << (8 * unaligned);
417 spi_imx->tx_buf++;
418 }
419 spi_imx->count--;
420 }
421
422 writel(val, spi_imx->base + MXC_CSPITXDATA);
423}
424
425static void mx53_ecspi_rx_target(struct spi_imx_data *spi_imx)
426{
427 u32 val = ioread32be(spi_imx->base + MXC_CSPIRXDATA);
428
429 if (spi_imx->rx_buf) {
430 int n_bytes = spi_imx->target_burst % sizeof(val);
431
432 if (!n_bytes)
433 n_bytes = sizeof(val);
434
435 memcpy(spi_imx->rx_buf,
436 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
437
438 spi_imx->rx_buf += n_bytes;
439 spi_imx->target_burst -= n_bytes;
440 }
441
442 spi_imx->remainder -= sizeof(u32);
443}
444
445static void mx53_ecspi_tx_target(struct spi_imx_data *spi_imx)
446{
447 u32 val = 0;
448 int n_bytes = spi_imx->count % sizeof(val);
449
450 if (!n_bytes)
451 n_bytes = sizeof(val);
452
453 if (spi_imx->tx_buf) {
454 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
455 spi_imx->tx_buf, n_bytes);
456 spi_imx->tx_buf += n_bytes;
457 }
458
459 spi_imx->count -= n_bytes;
460
461 iowrite32be(val, spi_imx->base + MXC_CSPITXDATA);
462}
463
464/* MX51 eCSPI */
465static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
466 unsigned int fspi, unsigned int *fres)
467{
468 /*
469 * there are two 4-bit dividers, the pre-divider divides by
470 * $pre, the post-divider by 2^$post
471 */
472 unsigned int pre, post;
473 unsigned int fin = spi_imx->spi_clk;
474
475 fspi = min(fspi, fin);
476
477 post = fls(fin) - fls(fspi);
478 if (fin > fspi << post)
479 post++;
480
481 /* now we have: (fin <= fspi << post) with post being minimal */
482
483 post = max(4U, post) - 4;
484 if (unlikely(post > 0xf)) {
485 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
486 fspi, fin);
487 return 0xff;
488 }
489
490 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
491
492 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
493 __func__, fin, fspi, post, pre);
494
495 /* Resulting frequency for the SCLK line. */
496 *fres = (fin / (pre + 1)) >> post;
497
498 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
499 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
500}
501
502static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
503{
504 unsigned int val = 0;
505
506 if (enable & MXC_INT_TE)
507 val |= MX51_ECSPI_INT_TEEN;
508
509 if (enable & MXC_INT_RR)
510 val |= MX51_ECSPI_INT_RREN;
511
512 if (enable & MXC_INT_RDR)
513 val |= MX51_ECSPI_INT_RDREN;
514
515 writel(val, spi_imx->base + MX51_ECSPI_INT);
516}
517
518static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
519{
520 u32 reg;
521
522 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
523 reg |= MX51_ECSPI_CTRL_XCH;
524 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
525}
526
527static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
528{
529 u32 ctrl;
530
531 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
532 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
533 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
534}
535
536static int mx51_ecspi_channel(const struct spi_device *spi)
537{
538 if (!spi_get_csgpiod(spi, 0))
539 return spi_get_chipselect(spi, 0);
540 return spi->controller->unused_native_cs;
541}
542
543static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
544 struct spi_message *msg)
545{
546 struct spi_device *spi = msg->spi;
547 struct spi_transfer *xfer;
548 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
549 u32 min_speed_hz = ~0U;
550 u32 testreg, delay;
551 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
552 u32 current_cfg = cfg;
553 int channel = mx51_ecspi_channel(spi);
554
555 /* set Host or Target mode */
556 if (spi_imx->target_mode)
557 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
558 else
559 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
560
561 /*
562 * Enable SPI_RDY handling (falling edge/level triggered).
563 */
564 if (spi->mode & SPI_READY)
565 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
566
567 /* set chip select to use */
568 ctrl |= MX51_ECSPI_CTRL_CS(channel);
569
570 /*
571 * The ctrl register must be written first, with the EN bit set other
572 * registers must not be written to.
573 */
574 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
575
576 testreg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
577 if (spi->mode & SPI_LOOP)
578 testreg |= MX51_ECSPI_TESTREG_LBC;
579 else
580 testreg &= ~MX51_ECSPI_TESTREG_LBC;
581 writel(testreg, spi_imx->base + MX51_ECSPI_TESTREG);
582
583 /*
584 * eCSPI burst completion by Chip Select signal in Target mode
585 * is not functional for imx53 Soc, config SPI burst completed when
586 * BURST_LENGTH + 1 bits are received
587 */
588 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
589 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel);
590 else
591 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel);
592
593 if (spi->mode & SPI_CPOL) {
594 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel);
595 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel);
596 } else {
597 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel);
598 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel);
599 }
600
601 if (spi->mode & SPI_MOSI_IDLE_LOW)
602 cfg |= MX51_ECSPI_CONFIG_DATACTL(channel);
603 else
604 cfg &= ~MX51_ECSPI_CONFIG_DATACTL(channel);
605
606 if (spi->mode & SPI_CS_HIGH)
607 cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel);
608 else
609 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel);
610
611 if (cfg == current_cfg)
612 return 0;
613
614 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
615
616 /*
617 * Wait until the changes in the configuration register CONFIGREG
618 * propagate into the hardware. It takes exactly one tick of the
619 * SCLK clock, but we will wait two SCLK clock just to be sure. The
620 * effect of the delay it takes for the hardware to apply changes
621 * is noticable if the SCLK clock run very slow. In such a case, if
622 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
623 * be asserted before the SCLK polarity changes, which would disrupt
624 * the SPI communication as the device on the other end would consider
625 * the change of SCLK polarity as a clock tick already.
626 *
627 * Because spi_imx->spi_bus_clk is only set in prepare_message
628 * callback, iterate over all the transfers in spi_message, find the
629 * one with lowest bus frequency, and use that bus frequency for the
630 * delay calculation. In case all transfers have speed_hz == 0, then
631 * min_speed_hz is ~0 and the resulting delay is zero.
632 */
633 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
634 if (!xfer->speed_hz)
635 continue;
636 min_speed_hz = min(xfer->speed_hz, min_speed_hz);
637 }
638
639 delay = (2 * 1000000) / min_speed_hz;
640 if (likely(delay < 10)) /* SCLK is faster than 200 kHz */
641 udelay(delay);
642 else /* SCLK is _very_ slow */
643 usleep_range(delay, delay + 10);
644
645 return 0;
646}
647
648static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
649 struct spi_device *spi)
650{
651 bool cpha = (spi->mode & SPI_CPHA);
652 bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only;
653 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
654 int channel = mx51_ecspi_channel(spi);
655
656 /* Flip cpha logical value iff flip_cpha */
657 cpha ^= flip_cpha;
658
659 if (cpha)
660 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel);
661 else
662 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel);
663
664 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
665}
666
667static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
668 struct spi_device *spi, struct spi_transfer *t)
669{
670 u32 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
671 u64 word_delay_sck;
672 u32 clk;
673
674 /* Clear BL field and set the right value */
675 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
676 if (spi_imx->target_mode && is_imx53_ecspi(spi_imx))
677 ctrl |= (spi_imx->target_burst * 8 - 1)
678 << MX51_ECSPI_CTRL_BL_OFFSET;
679 else {
680 ctrl |= (spi_imx->bits_per_word - 1)
681 << MX51_ECSPI_CTRL_BL_OFFSET;
682 }
683
684 /* set clock speed */
685 ctrl &= ~(0xf << MX51_ECSPI_CTRL_POSTDIV_OFFSET |
686 0xf << MX51_ECSPI_CTRL_PREDIV_OFFSET);
687 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
688 spi_imx->spi_bus_clk = clk;
689
690 mx51_configure_cpha(spi_imx, spi);
691
692 /*
693 * ERR009165: work in XHC mode instead of SMC as PIO on the chips
694 * before i.mx6ul.
695 */
696 if (spi_imx->usedma && spi_imx->devtype_data->tx_glitch_fixed)
697 ctrl |= MX51_ECSPI_CTRL_SMC;
698 else
699 ctrl &= ~MX51_ECSPI_CTRL_SMC;
700
701 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
702
703 /* calculate word delay in SPI Clock (SCLK) cycles */
704 if (t->word_delay.value == 0) {
705 word_delay_sck = 0;
706 } else if (t->word_delay.unit == SPI_DELAY_UNIT_SCK) {
707 word_delay_sck = t->word_delay.value;
708
709 if (word_delay_sck <= MX51_ECSPI_PERIOD_MIN_DELAY_SCK)
710 word_delay_sck = 0;
711 else if (word_delay_sck <= MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1)
712 word_delay_sck = 1;
713 else
714 word_delay_sck -= MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1;
715 } else {
716 int word_delay_ns;
717
718 word_delay_ns = spi_delay_to_ns(&t->word_delay, t);
719 if (word_delay_ns < 0)
720 return word_delay_ns;
721
722 if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC,
723 MX51_ECSPI_PERIOD_MIN_DELAY_SCK,
724 spi_imx->spi_bus_clk)) {
725 word_delay_sck = 0;
726 } else if (word_delay_ns <= mul_u64_u32_div(NSEC_PER_SEC,
727 MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1,
728 spi_imx->spi_bus_clk)) {
729 word_delay_sck = 1;
730 } else {
731 word_delay_ns -= mul_u64_u32_div(NSEC_PER_SEC,
732 MX51_ECSPI_PERIOD_MIN_DELAY_SCK + 1,
733 spi_imx->spi_bus_clk);
734
735 word_delay_sck = DIV_U64_ROUND_UP((u64)word_delay_ns * spi_imx->spi_bus_clk,
736 NSEC_PER_SEC);
737 }
738 }
739
740 if (!FIELD_FIT(MX51_ECSPI_PERIOD_MASK, word_delay_sck))
741 return -EINVAL;
742
743 writel(FIELD_PREP(MX51_ECSPI_PERIOD_MASK, word_delay_sck),
744 spi_imx->base + MX51_ECSPI_PERIOD);
745
746 return 0;
747}
748
749static void mx51_setup_wml(struct spi_imx_data *spi_imx)
750{
751 u32 tx_wml = 0;
752
753 if (spi_imx->devtype_data->tx_glitch_fixed)
754 tx_wml = spi_imx->wml;
755 /*
756 * Configure the DMA register: setup the watermark
757 * and enable DMA request.
758 */
759 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml - 1) |
760 MX51_ECSPI_DMA_TX_WML(tx_wml) |
761 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
762 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
763 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
764}
765
766static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
767{
768 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
769}
770
771static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
772{
773 /* drain receive buffer */
774 while (mx51_ecspi_rx_available(spi_imx))
775 readl(spi_imx->base + MXC_CSPIRXDATA);
776}
777
778#define MX31_INTREG_TEEN (1 << 0)
779#define MX31_INTREG_RREN (1 << 3)
780
781#define MX31_CSPICTRL_ENABLE (1 << 0)
782#define MX31_CSPICTRL_HOST (1 << 1)
783#define MX31_CSPICTRL_XCH (1 << 2)
784#define MX31_CSPICTRL_SMC (1 << 3)
785#define MX31_CSPICTRL_POL (1 << 4)
786#define MX31_CSPICTRL_PHA (1 << 5)
787#define MX31_CSPICTRL_SSCTL (1 << 6)
788#define MX31_CSPICTRL_SSPOL (1 << 7)
789#define MX31_CSPICTRL_BC_SHIFT 8
790#define MX35_CSPICTRL_BL_SHIFT 20
791#define MX31_CSPICTRL_CS_SHIFT 24
792#define MX35_CSPICTRL_CS_SHIFT 12
793#define MX31_CSPICTRL_DR_SHIFT 16
794
795#define MX31_CSPI_DMAREG 0x10
796#define MX31_DMAREG_RH_DEN (1<<4)
797#define MX31_DMAREG_TH_DEN (1<<1)
798
799#define MX31_CSPISTATUS 0x14
800#define MX31_STATUS_RR (1 << 3)
801
802#define MX31_CSPI_TESTREG 0x1C
803#define MX31_TEST_LBC (1 << 14)
804
805/* These functions also work for the i.MX35, but be aware that
806 * the i.MX35 has a slightly different register layout for bits
807 * we do not use here.
808 */
809static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
810{
811 unsigned int val = 0;
812
813 if (enable & MXC_INT_TE)
814 val |= MX31_INTREG_TEEN;
815 if (enable & MXC_INT_RR)
816 val |= MX31_INTREG_RREN;
817
818 writel(val, spi_imx->base + MXC_CSPIINT);
819}
820
821static void mx31_trigger(struct spi_imx_data *spi_imx)
822{
823 unsigned int reg;
824
825 reg = readl(spi_imx->base + MXC_CSPICTRL);
826 reg |= MX31_CSPICTRL_XCH;
827 writel(reg, spi_imx->base + MXC_CSPICTRL);
828}
829
830static int mx31_prepare_message(struct spi_imx_data *spi_imx,
831 struct spi_message *msg)
832{
833 return 0;
834}
835
836static int mx31_prepare_transfer(struct spi_imx_data *spi_imx,
837 struct spi_device *spi, struct spi_transfer *t)
838{
839 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_HOST;
840 unsigned int clk;
841
842 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
843 MX31_CSPICTRL_DR_SHIFT;
844 spi_imx->spi_bus_clk = clk;
845
846 if (is_imx35_cspi(spi_imx)) {
847 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
848 reg |= MX31_CSPICTRL_SSCTL;
849 } else {
850 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
851 }
852
853 if (spi->mode & SPI_CPHA)
854 reg |= MX31_CSPICTRL_PHA;
855 if (spi->mode & SPI_CPOL)
856 reg |= MX31_CSPICTRL_POL;
857 if (spi->mode & SPI_CS_HIGH)
858 reg |= MX31_CSPICTRL_SSPOL;
859 if (!spi_get_csgpiod(spi, 0))
860 reg |= (spi_get_chipselect(spi, 0)) <<
861 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
862 MX31_CSPICTRL_CS_SHIFT);
863
864 if (spi_imx->usedma)
865 reg |= MX31_CSPICTRL_SMC;
866
867 writel(reg, spi_imx->base + MXC_CSPICTRL);
868
869 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
870 if (spi->mode & SPI_LOOP)
871 reg |= MX31_TEST_LBC;
872 else
873 reg &= ~MX31_TEST_LBC;
874 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
875
876 if (spi_imx->usedma) {
877 /*
878 * configure DMA requests when RXFIFO is half full and
879 * when TXFIFO is half empty
880 */
881 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
882 spi_imx->base + MX31_CSPI_DMAREG);
883 }
884
885 return 0;
886}
887
888static int mx31_rx_available(struct spi_imx_data *spi_imx)
889{
890 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
891}
892
893static void mx31_reset(struct spi_imx_data *spi_imx)
894{
895 /* drain receive buffer */
896 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
897 readl(spi_imx->base + MXC_CSPIRXDATA);
898}
899
900#define MX21_INTREG_RR (1 << 4)
901#define MX21_INTREG_TEEN (1 << 9)
902#define MX21_INTREG_RREN (1 << 13)
903
904#define MX21_CSPICTRL_POL (1 << 5)
905#define MX21_CSPICTRL_PHA (1 << 6)
906#define MX21_CSPICTRL_SSPOL (1 << 8)
907#define MX21_CSPICTRL_XCH (1 << 9)
908#define MX21_CSPICTRL_ENABLE (1 << 10)
909#define MX21_CSPICTRL_HOST (1 << 11)
910#define MX21_CSPICTRL_DR_SHIFT 14
911#define MX21_CSPICTRL_CS_SHIFT 19
912
913static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
914{
915 unsigned int val = 0;
916
917 if (enable & MXC_INT_TE)
918 val |= MX21_INTREG_TEEN;
919 if (enable & MXC_INT_RR)
920 val |= MX21_INTREG_RREN;
921
922 writel(val, spi_imx->base + MXC_CSPIINT);
923}
924
925static void mx21_trigger(struct spi_imx_data *spi_imx)
926{
927 unsigned int reg;
928
929 reg = readl(spi_imx->base + MXC_CSPICTRL);
930 reg |= MX21_CSPICTRL_XCH;
931 writel(reg, spi_imx->base + MXC_CSPICTRL);
932}
933
934static int mx21_prepare_message(struct spi_imx_data *spi_imx,
935 struct spi_message *msg)
936{
937 return 0;
938}
939
940static int mx21_prepare_transfer(struct spi_imx_data *spi_imx,
941 struct spi_device *spi, struct spi_transfer *t)
942{
943 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_HOST;
944 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
945 unsigned int clk;
946
947 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->spi_bus_clk, max, &clk)
948 << MX21_CSPICTRL_DR_SHIFT;
949 spi_imx->spi_bus_clk = clk;
950
951 reg |= spi_imx->bits_per_word - 1;
952
953 if (spi->mode & SPI_CPHA)
954 reg |= MX21_CSPICTRL_PHA;
955 if (spi->mode & SPI_CPOL)
956 reg |= MX21_CSPICTRL_POL;
957 if (spi->mode & SPI_CS_HIGH)
958 reg |= MX21_CSPICTRL_SSPOL;
959 if (!spi_get_csgpiod(spi, 0))
960 reg |= spi_get_chipselect(spi, 0) << MX21_CSPICTRL_CS_SHIFT;
961
962 writel(reg, spi_imx->base + MXC_CSPICTRL);
963
964 return 0;
965}
966
967static int mx21_rx_available(struct spi_imx_data *spi_imx)
968{
969 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
970}
971
972static void mx21_reset(struct spi_imx_data *spi_imx)
973{
974 writel(1, spi_imx->base + MXC_RESET);
975}
976
977#define MX1_INTREG_RR (1 << 3)
978#define MX1_INTREG_TEEN (1 << 8)
979#define MX1_INTREG_RREN (1 << 11)
980
981#define MX1_CSPICTRL_POL (1 << 4)
982#define MX1_CSPICTRL_PHA (1 << 5)
983#define MX1_CSPICTRL_XCH (1 << 8)
984#define MX1_CSPICTRL_ENABLE (1 << 9)
985#define MX1_CSPICTRL_HOST (1 << 10)
986#define MX1_CSPICTRL_DR_SHIFT 13
987
988static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
989{
990 unsigned int val = 0;
991
992 if (enable & MXC_INT_TE)
993 val |= MX1_INTREG_TEEN;
994 if (enable & MXC_INT_RR)
995 val |= MX1_INTREG_RREN;
996
997 writel(val, spi_imx->base + MXC_CSPIINT);
998}
999
1000static void mx1_trigger(struct spi_imx_data *spi_imx)
1001{
1002 unsigned int reg;
1003
1004 reg = readl(spi_imx->base + MXC_CSPICTRL);
1005 reg |= MX1_CSPICTRL_XCH;
1006 writel(reg, spi_imx->base + MXC_CSPICTRL);
1007}
1008
1009static int mx1_prepare_message(struct spi_imx_data *spi_imx,
1010 struct spi_message *msg)
1011{
1012 return 0;
1013}
1014
1015static int mx1_prepare_transfer(struct spi_imx_data *spi_imx,
1016 struct spi_device *spi, struct spi_transfer *t)
1017{
1018 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_HOST;
1019 unsigned int clk;
1020
1021 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->spi_bus_clk, &clk) <<
1022 MX1_CSPICTRL_DR_SHIFT;
1023 spi_imx->spi_bus_clk = clk;
1024
1025 reg |= spi_imx->bits_per_word - 1;
1026
1027 if (spi->mode & SPI_CPHA)
1028 reg |= MX1_CSPICTRL_PHA;
1029 if (spi->mode & SPI_CPOL)
1030 reg |= MX1_CSPICTRL_POL;
1031
1032 writel(reg, spi_imx->base + MXC_CSPICTRL);
1033
1034 return 0;
1035}
1036
1037static int mx1_rx_available(struct spi_imx_data *spi_imx)
1038{
1039 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
1040}
1041
1042static void mx1_reset(struct spi_imx_data *spi_imx)
1043{
1044 writel(1, spi_imx->base + MXC_RESET);
1045}
1046
1047static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
1048 .intctrl = mx1_intctrl,
1049 .prepare_message = mx1_prepare_message,
1050 .prepare_transfer = mx1_prepare_transfer,
1051 .trigger = mx1_trigger,
1052 .rx_available = mx1_rx_available,
1053 .reset = mx1_reset,
1054 .fifo_size = 8,
1055 .has_dmamode = false,
1056 .dynamic_burst = false,
1057 .has_targetmode = false,
1058 .devtype = IMX1_CSPI,
1059};
1060
1061static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
1062 .intctrl = mx21_intctrl,
1063 .prepare_message = mx21_prepare_message,
1064 .prepare_transfer = mx21_prepare_transfer,
1065 .trigger = mx21_trigger,
1066 .rx_available = mx21_rx_available,
1067 .reset = mx21_reset,
1068 .fifo_size = 8,
1069 .has_dmamode = false,
1070 .dynamic_burst = false,
1071 .has_targetmode = false,
1072 .devtype = IMX21_CSPI,
1073};
1074
1075static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
1076 /* i.mx27 cspi shares the functions with i.mx21 one */
1077 .intctrl = mx21_intctrl,
1078 .prepare_message = mx21_prepare_message,
1079 .prepare_transfer = mx21_prepare_transfer,
1080 .trigger = mx21_trigger,
1081 .rx_available = mx21_rx_available,
1082 .reset = mx21_reset,
1083 .fifo_size = 8,
1084 .has_dmamode = false,
1085 .dynamic_burst = false,
1086 .has_targetmode = false,
1087 .devtype = IMX27_CSPI,
1088};
1089
1090static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
1091 .intctrl = mx31_intctrl,
1092 .prepare_message = mx31_prepare_message,
1093 .prepare_transfer = mx31_prepare_transfer,
1094 .trigger = mx31_trigger,
1095 .rx_available = mx31_rx_available,
1096 .reset = mx31_reset,
1097 .fifo_size = 8,
1098 .has_dmamode = false,
1099 .dynamic_burst = false,
1100 .has_targetmode = false,
1101 .devtype = IMX31_CSPI,
1102};
1103
1104static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
1105 /* i.mx35 and later cspi shares the functions with i.mx31 one */
1106 .intctrl = mx31_intctrl,
1107 .prepare_message = mx31_prepare_message,
1108 .prepare_transfer = mx31_prepare_transfer,
1109 .trigger = mx31_trigger,
1110 .rx_available = mx31_rx_available,
1111 .reset = mx31_reset,
1112 .fifo_size = 8,
1113 .has_dmamode = false,
1114 .dynamic_burst = false,
1115 .has_targetmode = false,
1116 .devtype = IMX35_CSPI,
1117};
1118
1119static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
1120 .intctrl = mx51_ecspi_intctrl,
1121 .prepare_message = mx51_ecspi_prepare_message,
1122 .prepare_transfer = mx51_ecspi_prepare_transfer,
1123 .trigger = mx51_ecspi_trigger,
1124 .rx_available = mx51_ecspi_rx_available,
1125 .reset = mx51_ecspi_reset,
1126 .setup_wml = mx51_setup_wml,
1127 .fifo_size = 64,
1128 .has_dmamode = true,
1129 .dynamic_burst = true,
1130 .has_targetmode = true,
1131 .disable = mx51_ecspi_disable,
1132 .devtype = IMX51_ECSPI,
1133};
1134
1135static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
1136 .intctrl = mx51_ecspi_intctrl,
1137 .prepare_message = mx51_ecspi_prepare_message,
1138 .prepare_transfer = mx51_ecspi_prepare_transfer,
1139 .trigger = mx51_ecspi_trigger,
1140 .rx_available = mx51_ecspi_rx_available,
1141 .reset = mx51_ecspi_reset,
1142 .fifo_size = 64,
1143 .has_dmamode = true,
1144 .has_targetmode = true,
1145 .disable = mx51_ecspi_disable,
1146 .devtype = IMX53_ECSPI,
1147};
1148
1149static struct spi_imx_devtype_data imx6ul_ecspi_devtype_data = {
1150 .intctrl = mx51_ecspi_intctrl,
1151 .prepare_message = mx51_ecspi_prepare_message,
1152 .prepare_transfer = mx51_ecspi_prepare_transfer,
1153 .trigger = mx51_ecspi_trigger,
1154 .rx_available = mx51_ecspi_rx_available,
1155 .reset = mx51_ecspi_reset,
1156 .setup_wml = mx51_setup_wml,
1157 .fifo_size = 64,
1158 .has_dmamode = true,
1159 .dynamic_burst = true,
1160 .has_targetmode = true,
1161 .tx_glitch_fixed = true,
1162 .disable = mx51_ecspi_disable,
1163 .devtype = IMX51_ECSPI,
1164};
1165
1166static const struct of_device_id spi_imx_dt_ids[] = {
1167 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
1168 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
1169 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
1170 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
1171 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1172 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1173 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1174 { .compatible = "fsl,imx6ul-ecspi", .data = &imx6ul_ecspi_devtype_data, },
1175 { /* sentinel */ }
1176};
1177MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1178
1179static void spi_imx_set_burst_len(struct spi_imx_data *spi_imx, int n_bits)
1180{
1181 u32 ctrl;
1182
1183 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
1184 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
1185 ctrl |= ((n_bits - 1) << MX51_ECSPI_CTRL_BL_OFFSET);
1186 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
1187}
1188
1189static void spi_imx_push(struct spi_imx_data *spi_imx)
1190{
1191 unsigned int burst_len;
1192
1193 /*
1194 * Reload the FIFO when the remaining bytes to be transferred in the
1195 * current burst is 0. This only applies when bits_per_word is a
1196 * multiple of 8.
1197 */
1198 if (!spi_imx->remainder) {
1199 if (spi_imx->dynamic_burst) {
1200
1201 /* We need to deal unaligned data first */
1202 burst_len = spi_imx->count % MX51_ECSPI_CTRL_MAX_BURST;
1203
1204 if (!burst_len)
1205 burst_len = MX51_ECSPI_CTRL_MAX_BURST;
1206
1207 spi_imx_set_burst_len(spi_imx, burst_len * 8);
1208
1209 spi_imx->remainder = burst_len;
1210 } else {
1211 spi_imx->remainder = spi_imx_bytes_per_word(spi_imx->bits_per_word);
1212 }
1213 }
1214
1215 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1216 if (!spi_imx->count)
1217 break;
1218 if (spi_imx->dynamic_burst &&
1219 spi_imx->txfifo >= DIV_ROUND_UP(spi_imx->remainder, 4))
1220 break;
1221 spi_imx->tx(spi_imx);
1222 spi_imx->txfifo++;
1223 }
1224
1225 if (!spi_imx->target_mode)
1226 spi_imx->devtype_data->trigger(spi_imx);
1227}
1228
1229static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1230{
1231 struct spi_imx_data *spi_imx = dev_id;
1232
1233 while (spi_imx->txfifo &&
1234 spi_imx->devtype_data->rx_available(spi_imx)) {
1235 spi_imx->rx(spi_imx);
1236 spi_imx->txfifo--;
1237 }
1238
1239 if (spi_imx->count) {
1240 spi_imx_push(spi_imx);
1241 return IRQ_HANDLED;
1242 }
1243
1244 if (spi_imx->txfifo) {
1245 /* No data left to push, but still waiting for rx data,
1246 * enable receive data available interrupt.
1247 */
1248 spi_imx->devtype_data->intctrl(
1249 spi_imx, MXC_INT_RR);
1250 return IRQ_HANDLED;
1251 }
1252
1253 spi_imx->devtype_data->intctrl(spi_imx, 0);
1254 complete(&spi_imx->xfer_done);
1255
1256 return IRQ_HANDLED;
1257}
1258
1259static int spi_imx_dma_configure(struct spi_controller *controller)
1260{
1261 int ret;
1262 enum dma_slave_buswidth buswidth;
1263 struct dma_slave_config rx = {}, tx = {};
1264 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1265
1266 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1267 case 4:
1268 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1269 break;
1270 case 2:
1271 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1272 break;
1273 case 1:
1274 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1275 break;
1276 default:
1277 return -EINVAL;
1278 }
1279
1280 tx.direction = DMA_MEM_TO_DEV;
1281 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1282 tx.dst_addr_width = buswidth;
1283 tx.dst_maxburst = spi_imx->wml;
1284 ret = dmaengine_slave_config(controller->dma_tx, &tx);
1285 if (ret) {
1286 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1287 return ret;
1288 }
1289
1290 rx.direction = DMA_DEV_TO_MEM;
1291 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1292 rx.src_addr_width = buswidth;
1293 rx.src_maxburst = spi_imx->wml;
1294 ret = dmaengine_slave_config(controller->dma_rx, &rx);
1295 if (ret) {
1296 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1297 return ret;
1298 }
1299
1300 return 0;
1301}
1302
1303static int spi_imx_setupxfer(struct spi_device *spi,
1304 struct spi_transfer *t)
1305{
1306 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1307
1308 if (!t)
1309 return 0;
1310
1311 if (!t->speed_hz) {
1312 if (!spi->max_speed_hz) {
1313 dev_err(&spi->dev, "no speed_hz provided!\n");
1314 return -EINVAL;
1315 }
1316 dev_dbg(&spi->dev, "using spi->max_speed_hz!\n");
1317 spi_imx->spi_bus_clk = spi->max_speed_hz;
1318 } else
1319 spi_imx->spi_bus_clk = t->speed_hz;
1320
1321 spi_imx->bits_per_word = t->bits_per_word;
1322 spi_imx->count = t->len;
1323
1324 /*
1325 * Initialize the functions for transfer. To transfer non byte-aligned
1326 * words, we have to use multiple word-size bursts. To insert word
1327 * delay, the burst size has to equal the word size. We can't use
1328 * dynamic_burst in these cases.
1329 */
1330 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->target_mode &&
1331 !(spi->mode & SPI_CS_WORD) &&
1332 !(t->word_delay.value) &&
1333 (spi_imx->bits_per_word == 8 ||
1334 spi_imx->bits_per_word == 16 ||
1335 spi_imx->bits_per_word == 32)) {
1336
1337 spi_imx->rx = spi_imx_buf_rx_swap;
1338 spi_imx->tx = spi_imx_buf_tx_swap;
1339 spi_imx->dynamic_burst = 1;
1340
1341 } else {
1342 if (spi_imx->bits_per_word <= 8) {
1343 spi_imx->rx = spi_imx_buf_rx_u8;
1344 spi_imx->tx = spi_imx_buf_tx_u8;
1345 } else if (spi_imx->bits_per_word <= 16) {
1346 spi_imx->rx = spi_imx_buf_rx_u16;
1347 spi_imx->tx = spi_imx_buf_tx_u16;
1348 } else {
1349 spi_imx->rx = spi_imx_buf_rx_u32;
1350 spi_imx->tx = spi_imx_buf_tx_u32;
1351 }
1352 spi_imx->dynamic_burst = 0;
1353 }
1354
1355 if (spi_imx_can_dma(spi_imx->controller, spi, t))
1356 spi_imx->usedma = true;
1357 else
1358 spi_imx->usedma = false;
1359
1360 spi_imx->rx_only = ((t->tx_buf == NULL)
1361 || (t->tx_buf == spi->controller->dummy_tx));
1362
1363 if (is_imx53_ecspi(spi_imx) && spi_imx->target_mode) {
1364 spi_imx->rx = mx53_ecspi_rx_target;
1365 spi_imx->tx = mx53_ecspi_tx_target;
1366 spi_imx->target_burst = t->len;
1367 }
1368
1369 spi_imx->devtype_data->prepare_transfer(spi_imx, spi, t);
1370
1371 return 0;
1372}
1373
1374static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1375{
1376 struct spi_controller *controller = spi_imx->controller;
1377
1378 if (controller->dma_rx) {
1379 dma_release_channel(controller->dma_rx);
1380 controller->dma_rx = NULL;
1381 }
1382
1383 if (controller->dma_tx) {
1384 dma_release_channel(controller->dma_tx);
1385 controller->dma_tx = NULL;
1386 }
1387}
1388
1389static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1390 struct spi_controller *controller)
1391{
1392 int ret;
1393
1394 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1395
1396 /* Prepare for TX DMA: */
1397 controller->dma_tx = dma_request_chan(dev, "tx");
1398 if (IS_ERR(controller->dma_tx)) {
1399 ret = PTR_ERR(controller->dma_tx);
1400 dev_err_probe(dev, ret, "can't get the TX DMA channel!\n");
1401 controller->dma_tx = NULL;
1402 goto err;
1403 }
1404
1405 /* Prepare for RX : */
1406 controller->dma_rx = dma_request_chan(dev, "rx");
1407 if (IS_ERR(controller->dma_rx)) {
1408 ret = PTR_ERR(controller->dma_rx);
1409 dev_err_probe(dev, ret, "can't get the RX DMA channel!\n");
1410 controller->dma_rx = NULL;
1411 goto err;
1412 }
1413
1414 init_completion(&spi_imx->dma_rx_completion);
1415 init_completion(&spi_imx->dma_tx_completion);
1416 controller->can_dma = spi_imx_can_dma;
1417 controller->max_dma_len = MAX_SDMA_BD_BYTES;
1418 spi_imx->controller->flags = SPI_CONTROLLER_MUST_RX |
1419 SPI_CONTROLLER_MUST_TX;
1420
1421 return 0;
1422err:
1423 spi_imx_sdma_exit(spi_imx);
1424 return ret;
1425}
1426
1427static void spi_imx_dma_rx_callback(void *cookie)
1428{
1429 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1430
1431 complete(&spi_imx->dma_rx_completion);
1432}
1433
1434static void spi_imx_dma_tx_callback(void *cookie)
1435{
1436 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1437
1438 complete(&spi_imx->dma_tx_completion);
1439}
1440
1441static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1442{
1443 unsigned long timeout = 0;
1444
1445 /* Time with actual data transfer and CS change delay related to HW */
1446 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1447
1448 /* Add extra second for scheduler related activities */
1449 timeout += 1;
1450
1451 /* Double calculated timeout */
1452 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1453}
1454
1455static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1456 struct spi_transfer *transfer)
1457{
1458 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1459 unsigned long transfer_timeout;
1460 unsigned long time_left;
1461 struct spi_controller *controller = spi_imx->controller;
1462 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1463 struct scatterlist *last_sg = sg_last(rx->sgl, rx->nents);
1464 unsigned int bytes_per_word, i;
1465 int ret;
1466
1467 /* Get the right burst length from the last sg to ensure no tail data */
1468 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
1469 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
1470 if (!(sg_dma_len(last_sg) % (i * bytes_per_word)))
1471 break;
1472 }
1473 /* Use 1 as wml in case no available burst length got */
1474 if (i == 0)
1475 i = 1;
1476
1477 spi_imx->wml = i;
1478
1479 ret = spi_imx_dma_configure(controller);
1480 if (ret)
1481 goto dma_failure_no_start;
1482
1483 if (!spi_imx->devtype_data->setup_wml) {
1484 dev_err(spi_imx->dev, "No setup_wml()?\n");
1485 ret = -EINVAL;
1486 goto dma_failure_no_start;
1487 }
1488 spi_imx->devtype_data->setup_wml(spi_imx);
1489
1490 /*
1491 * The TX DMA setup starts the transfer, so make sure RX is configured
1492 * before TX.
1493 */
1494 desc_rx = dmaengine_prep_slave_sg(controller->dma_rx,
1495 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1496 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1497 if (!desc_rx) {
1498 ret = -EINVAL;
1499 goto dma_failure_no_start;
1500 }
1501
1502 desc_rx->callback = spi_imx_dma_rx_callback;
1503 desc_rx->callback_param = (void *)spi_imx;
1504 dmaengine_submit(desc_rx);
1505 reinit_completion(&spi_imx->dma_rx_completion);
1506 dma_async_issue_pending(controller->dma_rx);
1507
1508 desc_tx = dmaengine_prep_slave_sg(controller->dma_tx,
1509 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1510 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1511 if (!desc_tx) {
1512 dmaengine_terminate_all(controller->dma_tx);
1513 dmaengine_terminate_all(controller->dma_rx);
1514 return -EINVAL;
1515 }
1516
1517 desc_tx->callback = spi_imx_dma_tx_callback;
1518 desc_tx->callback_param = (void *)spi_imx;
1519 dmaengine_submit(desc_tx);
1520 reinit_completion(&spi_imx->dma_tx_completion);
1521 dma_async_issue_pending(controller->dma_tx);
1522
1523 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1524
1525 /* Wait SDMA to finish the data transfer.*/
1526 time_left = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1527 transfer_timeout);
1528 if (!time_left) {
1529 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1530 dmaengine_terminate_all(controller->dma_tx);
1531 dmaengine_terminate_all(controller->dma_rx);
1532 return -ETIMEDOUT;
1533 }
1534
1535 time_left = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1536 transfer_timeout);
1537 if (!time_left) {
1538 dev_err(&controller->dev, "I/O Error in DMA RX\n");
1539 spi_imx->devtype_data->reset(spi_imx);
1540 dmaengine_terminate_all(controller->dma_rx);
1541 return -ETIMEDOUT;
1542 }
1543
1544 return 0;
1545/* fallback to pio */
1546dma_failure_no_start:
1547 transfer->error |= SPI_TRANS_FAIL_NO_START;
1548 return ret;
1549}
1550
1551static int spi_imx_pio_transfer(struct spi_device *spi,
1552 struct spi_transfer *transfer)
1553{
1554 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1555 unsigned long transfer_timeout;
1556 unsigned long time_left;
1557
1558 spi_imx->tx_buf = transfer->tx_buf;
1559 spi_imx->rx_buf = transfer->rx_buf;
1560 spi_imx->count = transfer->len;
1561 spi_imx->txfifo = 0;
1562 spi_imx->remainder = 0;
1563
1564 reinit_completion(&spi_imx->xfer_done);
1565
1566 spi_imx_push(spi_imx);
1567
1568 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1569
1570 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1571
1572 time_left = wait_for_completion_timeout(&spi_imx->xfer_done,
1573 transfer_timeout);
1574 if (!time_left) {
1575 dev_err(&spi->dev, "I/O Error in PIO\n");
1576 spi_imx->devtype_data->reset(spi_imx);
1577 return -ETIMEDOUT;
1578 }
1579
1580 return 0;
1581}
1582
1583static int spi_imx_poll_transfer(struct spi_device *spi,
1584 struct spi_transfer *transfer)
1585{
1586 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1587 unsigned long timeout;
1588
1589 spi_imx->tx_buf = transfer->tx_buf;
1590 spi_imx->rx_buf = transfer->rx_buf;
1591 spi_imx->count = transfer->len;
1592 spi_imx->txfifo = 0;
1593 spi_imx->remainder = 0;
1594
1595 /* fill in the fifo before timeout calculations if we are
1596 * interrupted here, then the data is getting transferred by
1597 * the HW while we are interrupted
1598 */
1599 spi_imx_push(spi_imx);
1600
1601 timeout = spi_imx_calculate_timeout(spi_imx, transfer->len) + jiffies;
1602 while (spi_imx->txfifo) {
1603 /* RX */
1604 while (spi_imx->txfifo &&
1605 spi_imx->devtype_data->rx_available(spi_imx)) {
1606 spi_imx->rx(spi_imx);
1607 spi_imx->txfifo--;
1608 }
1609
1610 /* TX */
1611 if (spi_imx->count) {
1612 spi_imx_push(spi_imx);
1613 continue;
1614 }
1615
1616 if (spi_imx->txfifo &&
1617 time_after(jiffies, timeout)) {
1618
1619 dev_err_ratelimited(&spi->dev,
1620 "timeout period reached: jiffies: %lu- falling back to interrupt mode\n",
1621 jiffies - timeout);
1622
1623 /* fall back to interrupt mode */
1624 return spi_imx_pio_transfer(spi, transfer);
1625 }
1626 }
1627
1628 return 0;
1629}
1630
1631static int spi_imx_pio_transfer_target(struct spi_device *spi,
1632 struct spi_transfer *transfer)
1633{
1634 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1635 int ret = 0;
1636
1637 if (is_imx53_ecspi(spi_imx) &&
1638 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1639 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1640 MX53_MAX_TRANSFER_BYTES);
1641 return -EMSGSIZE;
1642 }
1643
1644 spi_imx->tx_buf = transfer->tx_buf;
1645 spi_imx->rx_buf = transfer->rx_buf;
1646 spi_imx->count = transfer->len;
1647 spi_imx->txfifo = 0;
1648 spi_imx->remainder = 0;
1649
1650 reinit_completion(&spi_imx->xfer_done);
1651 spi_imx->target_aborted = false;
1652
1653 spi_imx_push(spi_imx);
1654
1655 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1656
1657 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1658 spi_imx->target_aborted) {
1659 dev_dbg(&spi->dev, "interrupted\n");
1660 ret = -EINTR;
1661 }
1662
1663 /* ecspi has a HW issue when works in Target mode,
1664 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1665 * ECSPI_TXDATA keeps shift out the last word data,
1666 * so we have to disable ECSPI when in target mode after the
1667 * transfer completes
1668 */
1669 if (spi_imx->devtype_data->disable)
1670 spi_imx->devtype_data->disable(spi_imx);
1671
1672 return ret;
1673}
1674
1675static unsigned int spi_imx_transfer_estimate_time_us(struct spi_transfer *transfer)
1676{
1677 u64 result;
1678
1679 result = DIV_U64_ROUND_CLOSEST((u64)USEC_PER_SEC * transfer->len * BITS_PER_BYTE,
1680 transfer->effective_speed_hz);
1681 if (transfer->word_delay.value) {
1682 unsigned int word_delay_us;
1683 unsigned int words;
1684
1685 words = DIV_ROUND_UP(transfer->len * BITS_PER_BYTE, transfer->bits_per_word);
1686 word_delay_us = DIV_ROUND_CLOSEST(spi_delay_to_ns(&transfer->word_delay, transfer),
1687 NSEC_PER_USEC);
1688 result += (u64)words * word_delay_us;
1689 }
1690
1691 return min(result, U32_MAX);
1692}
1693
1694static int spi_imx_transfer_one(struct spi_controller *controller,
1695 struct spi_device *spi,
1696 struct spi_transfer *transfer)
1697{
1698 struct spi_imx_data *spi_imx = spi_controller_get_devdata(spi->controller);
1699
1700 spi_imx_setupxfer(spi, transfer);
1701 transfer->effective_speed_hz = spi_imx->spi_bus_clk;
1702
1703 /* flush rxfifo before transfer */
1704 while (spi_imx->devtype_data->rx_available(spi_imx))
1705 readl(spi_imx->base + MXC_CSPIRXDATA);
1706
1707 if (spi_imx->target_mode)
1708 return spi_imx_pio_transfer_target(spi, transfer);
1709
1710 /*
1711 * If we decided in spi_imx_can_dma() that we want to do a DMA
1712 * transfer, the SPI transfer has already been mapped, so we
1713 * have to do the DMA transfer here.
1714 */
1715 if (spi_imx->usedma)
1716 return spi_imx_dma_transfer(spi_imx, transfer);
1717
1718 /* run in polling mode for short transfers */
1719 if (transfer->len == 1 || (polling_limit_us &&
1720 spi_imx_transfer_estimate_time_us(transfer) < polling_limit_us))
1721 return spi_imx_poll_transfer(spi, transfer);
1722
1723 return spi_imx_pio_transfer(spi, transfer);
1724}
1725
1726static int spi_imx_setup(struct spi_device *spi)
1727{
1728 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1729 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1730
1731 return 0;
1732}
1733
1734static int
1735spi_imx_prepare_message(struct spi_controller *controller, struct spi_message *msg)
1736{
1737 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1738 int ret;
1739
1740 ret = pm_runtime_resume_and_get(spi_imx->dev);
1741 if (ret < 0) {
1742 dev_err(spi_imx->dev, "failed to enable clock\n");
1743 return ret;
1744 }
1745
1746 ret = spi_imx->devtype_data->prepare_message(spi_imx, msg);
1747 if (ret) {
1748 pm_runtime_mark_last_busy(spi_imx->dev);
1749 pm_runtime_put_autosuspend(spi_imx->dev);
1750 }
1751
1752 return ret;
1753}
1754
1755static int
1756spi_imx_unprepare_message(struct spi_controller *controller, struct spi_message *msg)
1757{
1758 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1759
1760 pm_runtime_mark_last_busy(spi_imx->dev);
1761 pm_runtime_put_autosuspend(spi_imx->dev);
1762 return 0;
1763}
1764
1765static int spi_imx_target_abort(struct spi_controller *controller)
1766{
1767 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1768
1769 spi_imx->target_aborted = true;
1770 complete(&spi_imx->xfer_done);
1771
1772 return 0;
1773}
1774
1775static int spi_imx_probe(struct platform_device *pdev)
1776{
1777 struct device_node *np = pdev->dev.of_node;
1778 struct spi_controller *controller;
1779 struct spi_imx_data *spi_imx;
1780 struct resource *res;
1781 int ret, irq, spi_drctl;
1782 const struct spi_imx_devtype_data *devtype_data =
1783 of_device_get_match_data(&pdev->dev);
1784 bool target_mode;
1785 u32 val;
1786
1787 target_mode = devtype_data->has_targetmode &&
1788 of_property_read_bool(np, "spi-slave");
1789 if (target_mode)
1790 controller = spi_alloc_target(&pdev->dev,
1791 sizeof(struct spi_imx_data));
1792 else
1793 controller = spi_alloc_host(&pdev->dev,
1794 sizeof(struct spi_imx_data));
1795 if (!controller)
1796 return -ENOMEM;
1797
1798 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1799 if ((ret < 0) || (spi_drctl >= 0x3)) {
1800 /* '11' is reserved */
1801 spi_drctl = 0;
1802 }
1803
1804 platform_set_drvdata(pdev, controller);
1805
1806 controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1807 controller->bus_num = np ? -1 : pdev->id;
1808 controller->use_gpio_descriptors = true;
1809
1810 spi_imx = spi_controller_get_devdata(controller);
1811 spi_imx->controller = controller;
1812 spi_imx->dev = &pdev->dev;
1813 spi_imx->target_mode = target_mode;
1814
1815 spi_imx->devtype_data = devtype_data;
1816
1817 /*
1818 * Get number of chip selects from device properties. This can be
1819 * coming from device tree or boardfiles, if it is not defined,
1820 * a default value of 3 chip selects will be used, as all the legacy
1821 * board files have <= 3 chip selects.
1822 */
1823 if (!device_property_read_u32(&pdev->dev, "num-cs", &val))
1824 controller->num_chipselect = val;
1825 else
1826 controller->num_chipselect = 3;
1827
1828 controller->transfer_one = spi_imx_transfer_one;
1829 controller->setup = spi_imx_setup;
1830 controller->prepare_message = spi_imx_prepare_message;
1831 controller->unprepare_message = spi_imx_unprepare_message;
1832 controller->target_abort = spi_imx_target_abort;
1833 controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS |
1834 SPI_MOSI_IDLE_LOW;
1835
1836 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1837 is_imx53_ecspi(spi_imx))
1838 controller->mode_bits |= SPI_LOOP | SPI_READY;
1839
1840 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))
1841 controller->mode_bits |= SPI_RX_CPHA_FLIP;
1842
1843 if (is_imx51_ecspi(spi_imx) &&
1844 device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
1845 /*
1846 * When using HW-CS implementing SPI_CS_WORD can be done by just
1847 * setting the burst length to the word size. This is
1848 * considerably faster than manually controlling the CS.
1849 */
1850 controller->mode_bits |= SPI_CS_WORD;
1851
1852 if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) {
1853 controller->max_native_cs = 4;
1854 controller->flags |= SPI_CONTROLLER_GPIO_SS;
1855 }
1856
1857 spi_imx->spi_drctl = spi_drctl;
1858
1859 init_completion(&spi_imx->xfer_done);
1860
1861 spi_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1862 if (IS_ERR(spi_imx->base)) {
1863 ret = PTR_ERR(spi_imx->base);
1864 goto out_controller_put;
1865 }
1866 spi_imx->base_phys = res->start;
1867
1868 irq = platform_get_irq(pdev, 0);
1869 if (irq < 0) {
1870 ret = irq;
1871 goto out_controller_put;
1872 }
1873
1874 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1875 dev_name(&pdev->dev), spi_imx);
1876 if (ret) {
1877 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1878 goto out_controller_put;
1879 }
1880
1881 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1882 if (IS_ERR(spi_imx->clk_ipg)) {
1883 ret = PTR_ERR(spi_imx->clk_ipg);
1884 goto out_controller_put;
1885 }
1886
1887 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1888 if (IS_ERR(spi_imx->clk_per)) {
1889 ret = PTR_ERR(spi_imx->clk_per);
1890 goto out_controller_put;
1891 }
1892
1893 ret = clk_prepare_enable(spi_imx->clk_per);
1894 if (ret)
1895 goto out_controller_put;
1896
1897 ret = clk_prepare_enable(spi_imx->clk_ipg);
1898 if (ret)
1899 goto out_put_per;
1900
1901 pm_runtime_set_autosuspend_delay(spi_imx->dev, MXC_RPM_TIMEOUT);
1902 pm_runtime_use_autosuspend(spi_imx->dev);
1903 pm_runtime_get_noresume(spi_imx->dev);
1904 pm_runtime_set_active(spi_imx->dev);
1905 pm_runtime_enable(spi_imx->dev);
1906
1907 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1908 /*
1909 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1910 * if validated on other chips.
1911 */
1912 if (spi_imx->devtype_data->has_dmamode) {
1913 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, controller);
1914 if (ret == -EPROBE_DEFER)
1915 goto out_runtime_pm_put;
1916
1917 if (ret < 0)
1918 dev_dbg(&pdev->dev, "dma setup error %d, use pio\n",
1919 ret);
1920 }
1921
1922 spi_imx->devtype_data->reset(spi_imx);
1923
1924 spi_imx->devtype_data->intctrl(spi_imx, 0);
1925
1926 controller->dev.of_node = pdev->dev.of_node;
1927 ret = spi_register_controller(controller);
1928 if (ret) {
1929 dev_err_probe(&pdev->dev, ret, "register controller failed\n");
1930 goto out_register_controller;
1931 }
1932
1933 pm_runtime_mark_last_busy(spi_imx->dev);
1934 pm_runtime_put_autosuspend(spi_imx->dev);
1935
1936 return ret;
1937
1938out_register_controller:
1939 if (spi_imx->devtype_data->has_dmamode)
1940 spi_imx_sdma_exit(spi_imx);
1941out_runtime_pm_put:
1942 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1943 pm_runtime_disable(spi_imx->dev);
1944 pm_runtime_set_suspended(&pdev->dev);
1945
1946 clk_disable_unprepare(spi_imx->clk_ipg);
1947out_put_per:
1948 clk_disable_unprepare(spi_imx->clk_per);
1949out_controller_put:
1950 spi_controller_put(controller);
1951
1952 return ret;
1953}
1954
1955static void spi_imx_remove(struct platform_device *pdev)
1956{
1957 struct spi_controller *controller = platform_get_drvdata(pdev);
1958 struct spi_imx_data *spi_imx = spi_controller_get_devdata(controller);
1959 int ret;
1960
1961 spi_unregister_controller(controller);
1962
1963 ret = pm_runtime_get_sync(spi_imx->dev);
1964 if (ret >= 0)
1965 writel(0, spi_imx->base + MXC_CSPICTRL);
1966 else
1967 dev_warn(spi_imx->dev, "failed to enable clock, skip hw disable\n");
1968
1969 pm_runtime_dont_use_autosuspend(spi_imx->dev);
1970 pm_runtime_put_sync(spi_imx->dev);
1971 pm_runtime_disable(spi_imx->dev);
1972
1973 spi_imx_sdma_exit(spi_imx);
1974}
1975
1976static int spi_imx_runtime_resume(struct device *dev)
1977{
1978 struct spi_controller *controller = dev_get_drvdata(dev);
1979 struct spi_imx_data *spi_imx;
1980 int ret;
1981
1982 spi_imx = spi_controller_get_devdata(controller);
1983
1984 ret = clk_prepare_enable(spi_imx->clk_per);
1985 if (ret)
1986 return ret;
1987
1988 ret = clk_prepare_enable(spi_imx->clk_ipg);
1989 if (ret) {
1990 clk_disable_unprepare(spi_imx->clk_per);
1991 return ret;
1992 }
1993
1994 return 0;
1995}
1996
1997static int spi_imx_runtime_suspend(struct device *dev)
1998{
1999 struct spi_controller *controller = dev_get_drvdata(dev);
2000 struct spi_imx_data *spi_imx;
2001
2002 spi_imx = spi_controller_get_devdata(controller);
2003
2004 clk_disable_unprepare(spi_imx->clk_per);
2005 clk_disable_unprepare(spi_imx->clk_ipg);
2006
2007 return 0;
2008}
2009
2010static int spi_imx_suspend(struct device *dev)
2011{
2012 pinctrl_pm_select_sleep_state(dev);
2013 return 0;
2014}
2015
2016static int spi_imx_resume(struct device *dev)
2017{
2018 pinctrl_pm_select_default_state(dev);
2019 return 0;
2020}
2021
2022static const struct dev_pm_ops imx_spi_pm = {
2023 RUNTIME_PM_OPS(spi_imx_runtime_suspend, spi_imx_runtime_resume, NULL)
2024 SYSTEM_SLEEP_PM_OPS(spi_imx_suspend, spi_imx_resume)
2025};
2026
2027static struct platform_driver spi_imx_driver = {
2028 .driver = {
2029 .name = DRIVER_NAME,
2030 .of_match_table = spi_imx_dt_ids,
2031 .pm = pm_ptr(&imx_spi_pm),
2032 },
2033 .probe = spi_imx_probe,
2034 .remove = spi_imx_remove,
2035};
2036module_platform_driver(spi_imx_driver);
2037
2038MODULE_DESCRIPTION("i.MX SPI Controller driver");
2039MODULE_AUTHOR("Sascha Hauer, Pengutronix");
2040MODULE_LICENSE("GPL");
2041MODULE_ALIAS("platform:" DRIVER_NAME);
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/dmaengine.h>
25#include <linux/dma-mapping.h>
26#include <linux/err.h>
27#include <linux/gpio.h>
28#include <linux/interrupt.h>
29#include <linux/io.h>
30#include <linux/irq.h>
31#include <linux/kernel.h>
32#include <linux/module.h>
33#include <linux/platform_device.h>
34#include <linux/slab.h>
35#include <linux/spi/spi.h>
36#include <linux/spi/spi_bitbang.h>
37#include <linux/types.h>
38#include <linux/of.h>
39#include <linux/of_device.h>
40#include <linux/of_gpio.h>
41
42#include <linux/platform_data/dma-imx.h>
43#include <linux/platform_data/spi-imx.h>
44
45#define DRIVER_NAME "spi_imx"
46
47#define MXC_CSPIRXDATA 0x00
48#define MXC_CSPITXDATA 0x04
49#define MXC_CSPICTRL 0x08
50#define MXC_CSPIINT 0x0c
51#define MXC_RESET 0x1c
52
53/* generic defines to abstract from the different register layouts */
54#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
55#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
56#define MXC_INT_RDR BIT(4) /* Receive date threshold interrupt */
57
58/* The maximum bytes that a sdma BD can transfer.*/
59#define MAX_SDMA_BD_BYTES (1 << 15)
60#define MX51_ECSPI_CTRL_MAX_BURST 512
61/* The maximum bytes that IMX53_ECSPI can transfer in slave mode.*/
62#define MX53_MAX_TRANSFER_BYTES 512
63
64enum spi_imx_devtype {
65 IMX1_CSPI,
66 IMX21_CSPI,
67 IMX27_CSPI,
68 IMX31_CSPI,
69 IMX35_CSPI, /* CSPI on all i.mx except above */
70 IMX51_ECSPI, /* ECSPI on i.mx51 */
71 IMX53_ECSPI, /* ECSPI on i.mx53 and later */
72};
73
74struct spi_imx_data;
75
76struct spi_imx_devtype_data {
77 void (*intctrl)(struct spi_imx_data *, int);
78 int (*config)(struct spi_device *);
79 void (*trigger)(struct spi_imx_data *);
80 int (*rx_available)(struct spi_imx_data *);
81 void (*reset)(struct spi_imx_data *);
82 void (*disable)(struct spi_imx_data *);
83 bool has_dmamode;
84 bool has_slavemode;
85 unsigned int fifo_size;
86 bool dynamic_burst;
87 enum spi_imx_devtype devtype;
88};
89
90struct spi_imx_data {
91 struct spi_bitbang bitbang;
92 struct device *dev;
93
94 struct completion xfer_done;
95 void __iomem *base;
96 unsigned long base_phys;
97
98 struct clk *clk_per;
99 struct clk *clk_ipg;
100 unsigned long spi_clk;
101 unsigned int spi_bus_clk;
102
103 unsigned int speed_hz;
104 unsigned int bits_per_word;
105 unsigned int spi_drctl;
106
107 unsigned int count, remainder;
108 void (*tx)(struct spi_imx_data *);
109 void (*rx)(struct spi_imx_data *);
110 void *rx_buf;
111 const void *tx_buf;
112 unsigned int txfifo; /* number of words pushed in tx FIFO */
113 unsigned int dynamic_burst, read_u32;
114 unsigned int word_mask;
115
116 /* Slave mode */
117 bool slave_mode;
118 bool slave_aborted;
119 unsigned int slave_burst;
120
121 /* DMA */
122 bool usedma;
123 u32 wml;
124 struct completion dma_rx_completion;
125 struct completion dma_tx_completion;
126
127 const struct spi_imx_devtype_data *devtype_data;
128};
129
130static inline int is_imx27_cspi(struct spi_imx_data *d)
131{
132 return d->devtype_data->devtype == IMX27_CSPI;
133}
134
135static inline int is_imx35_cspi(struct spi_imx_data *d)
136{
137 return d->devtype_data->devtype == IMX35_CSPI;
138}
139
140static inline int is_imx51_ecspi(struct spi_imx_data *d)
141{
142 return d->devtype_data->devtype == IMX51_ECSPI;
143}
144
145static inline int is_imx53_ecspi(struct spi_imx_data *d)
146{
147 return d->devtype_data->devtype == IMX53_ECSPI;
148}
149
150#define MXC_SPI_BUF_RX(type) \
151static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
152{ \
153 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
154 \
155 if (spi_imx->rx_buf) { \
156 *(type *)spi_imx->rx_buf = val; \
157 spi_imx->rx_buf += sizeof(type); \
158 } \
159}
160
161#define MXC_SPI_BUF_TX(type) \
162static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
163{ \
164 type val = 0; \
165 \
166 if (spi_imx->tx_buf) { \
167 val = *(type *)spi_imx->tx_buf; \
168 spi_imx->tx_buf += sizeof(type); \
169 } \
170 \
171 spi_imx->count -= sizeof(type); \
172 \
173 writel(val, spi_imx->base + MXC_CSPITXDATA); \
174}
175
176MXC_SPI_BUF_RX(u8)
177MXC_SPI_BUF_TX(u8)
178MXC_SPI_BUF_RX(u16)
179MXC_SPI_BUF_TX(u16)
180MXC_SPI_BUF_RX(u32)
181MXC_SPI_BUF_TX(u32)
182
183/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
184 * (which is currently not the case in this driver)
185 */
186static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
187 256, 384, 512, 768, 1024};
188
189/* MX21, MX27 */
190static unsigned int spi_imx_clkdiv_1(unsigned int fin,
191 unsigned int fspi, unsigned int max, unsigned int *fres)
192{
193 int i;
194
195 for (i = 2; i < max; i++)
196 if (fspi * mxc_clkdivs[i] >= fin)
197 break;
198
199 *fres = fin / mxc_clkdivs[i];
200 return i;
201}
202
203/* MX1, MX31, MX35, MX51 CSPI */
204static unsigned int spi_imx_clkdiv_2(unsigned int fin,
205 unsigned int fspi, unsigned int *fres)
206{
207 int i, div = 4;
208
209 for (i = 0; i < 7; i++) {
210 if (fspi * div >= fin)
211 goto out;
212 div <<= 1;
213 }
214
215out:
216 *fres = fin / div;
217 return i;
218}
219
220static int spi_imx_bytes_per_word(const int bits_per_word)
221{
222 return DIV_ROUND_UP(bits_per_word, BITS_PER_BYTE);
223}
224
225static bool spi_imx_can_dma(struct spi_master *master, struct spi_device *spi,
226 struct spi_transfer *transfer)
227{
228 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
229 unsigned int bytes_per_word, i;
230
231 if (!master->dma_rx)
232 return false;
233
234 if (spi_imx->slave_mode)
235 return false;
236
237 bytes_per_word = spi_imx_bytes_per_word(transfer->bits_per_word);
238
239 if (bytes_per_word != 1 && bytes_per_word != 2 && bytes_per_word != 4)
240 return false;
241
242 for (i = spi_imx->devtype_data->fifo_size / 2; i > 0; i--) {
243 if (!(transfer->len % (i * bytes_per_word)))
244 break;
245 }
246
247 if (i == 0)
248 return false;
249
250 spi_imx->wml = i;
251 spi_imx->dynamic_burst = 0;
252
253 return true;
254}
255
256#define MX51_ECSPI_CTRL 0x08
257#define MX51_ECSPI_CTRL_ENABLE (1 << 0)
258#define MX51_ECSPI_CTRL_XCH (1 << 2)
259#define MX51_ECSPI_CTRL_SMC (1 << 3)
260#define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
261#define MX51_ECSPI_CTRL_DRCTL(drctl) ((drctl) << 16)
262#define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
263#define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
264#define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
265#define MX51_ECSPI_CTRL_BL_OFFSET 20
266#define MX51_ECSPI_CTRL_BL_MASK (0xfff << 20)
267
268#define MX51_ECSPI_CONFIG 0x0c
269#define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
270#define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
271#define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
272#define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
273#define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
274
275#define MX51_ECSPI_INT 0x10
276#define MX51_ECSPI_INT_TEEN (1 << 0)
277#define MX51_ECSPI_INT_RREN (1 << 3)
278#define MX51_ECSPI_INT_RDREN (1 << 4)
279
280#define MX51_ECSPI_DMA 0x14
281#define MX51_ECSPI_DMA_TX_WML(wml) ((wml) & 0x3f)
282#define MX51_ECSPI_DMA_RX_WML(wml) (((wml) & 0x3f) << 16)
283#define MX51_ECSPI_DMA_RXT_WML(wml) (((wml) & 0x3f) << 24)
284
285#define MX51_ECSPI_DMA_TEDEN (1 << 7)
286#define MX51_ECSPI_DMA_RXDEN (1 << 23)
287#define MX51_ECSPI_DMA_RXTDEN (1 << 31)
288
289#define MX51_ECSPI_STAT 0x18
290#define MX51_ECSPI_STAT_RR (1 << 3)
291
292#define MX51_ECSPI_TESTREG 0x20
293#define MX51_ECSPI_TESTREG_LBC BIT(31)
294
295static void spi_imx_buf_rx_swap_u32(struct spi_imx_data *spi_imx)
296{
297 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA);
298#ifdef __LITTLE_ENDIAN
299 unsigned int bytes_per_word;
300#endif
301
302 if (spi_imx->rx_buf) {
303#ifdef __LITTLE_ENDIAN
304 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
305 if (bytes_per_word == 1)
306 val = cpu_to_be32(val);
307 else if (bytes_per_word == 2)
308 val = (val << 16) | (val >> 16);
309#endif
310 val &= spi_imx->word_mask;
311 *(u32 *)spi_imx->rx_buf = val;
312 spi_imx->rx_buf += sizeof(u32);
313 }
314}
315
316static void spi_imx_buf_rx_swap(struct spi_imx_data *spi_imx)
317{
318 unsigned int bytes_per_word;
319
320 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
321 if (spi_imx->read_u32) {
322 spi_imx_buf_rx_swap_u32(spi_imx);
323 return;
324 }
325
326 if (bytes_per_word == 1)
327 spi_imx_buf_rx_u8(spi_imx);
328 else if (bytes_per_word == 2)
329 spi_imx_buf_rx_u16(spi_imx);
330}
331
332static void spi_imx_buf_tx_swap_u32(struct spi_imx_data *spi_imx)
333{
334 u32 val = 0;
335#ifdef __LITTLE_ENDIAN
336 unsigned int bytes_per_word;
337#endif
338
339 if (spi_imx->tx_buf) {
340 val = *(u32 *)spi_imx->tx_buf;
341 val &= spi_imx->word_mask;
342 spi_imx->tx_buf += sizeof(u32);
343 }
344
345 spi_imx->count -= sizeof(u32);
346#ifdef __LITTLE_ENDIAN
347 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
348
349 if (bytes_per_word == 1)
350 val = cpu_to_be32(val);
351 else if (bytes_per_word == 2)
352 val = (val << 16) | (val >> 16);
353#endif
354 writel(val, spi_imx->base + MXC_CSPITXDATA);
355}
356
357static void spi_imx_buf_tx_swap(struct spi_imx_data *spi_imx)
358{
359 u32 ctrl, val;
360 unsigned int bytes_per_word;
361
362 if (spi_imx->count == spi_imx->remainder) {
363 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
364 ctrl &= ~MX51_ECSPI_CTRL_BL_MASK;
365 if (spi_imx->count > MX51_ECSPI_CTRL_MAX_BURST) {
366 spi_imx->remainder = spi_imx->count %
367 MX51_ECSPI_CTRL_MAX_BURST;
368 val = MX51_ECSPI_CTRL_MAX_BURST * 8 - 1;
369 } else if (spi_imx->count >= sizeof(u32)) {
370 spi_imx->remainder = spi_imx->count % sizeof(u32);
371 val = (spi_imx->count - spi_imx->remainder) * 8 - 1;
372 } else {
373 spi_imx->remainder = 0;
374 val = spi_imx->bits_per_word - 1;
375 spi_imx->read_u32 = 0;
376 }
377
378 ctrl |= (val << MX51_ECSPI_CTRL_BL_OFFSET);
379 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
380 }
381
382 if (spi_imx->count >= sizeof(u32)) {
383 spi_imx_buf_tx_swap_u32(spi_imx);
384 return;
385 }
386
387 bytes_per_word = spi_imx_bytes_per_word(spi_imx->bits_per_word);
388
389 if (bytes_per_word == 1)
390 spi_imx_buf_tx_u8(spi_imx);
391 else if (bytes_per_word == 2)
392 spi_imx_buf_tx_u16(spi_imx);
393}
394
395static void mx53_ecspi_rx_slave(struct spi_imx_data *spi_imx)
396{
397 u32 val = be32_to_cpu(readl(spi_imx->base + MXC_CSPIRXDATA));
398
399 if (spi_imx->rx_buf) {
400 int n_bytes = spi_imx->slave_burst % sizeof(val);
401
402 if (!n_bytes)
403 n_bytes = sizeof(val);
404
405 memcpy(spi_imx->rx_buf,
406 ((u8 *)&val) + sizeof(val) - n_bytes, n_bytes);
407
408 spi_imx->rx_buf += n_bytes;
409 spi_imx->slave_burst -= n_bytes;
410 }
411}
412
413static void mx53_ecspi_tx_slave(struct spi_imx_data *spi_imx)
414{
415 u32 val = 0;
416 int n_bytes = spi_imx->count % sizeof(val);
417
418 if (!n_bytes)
419 n_bytes = sizeof(val);
420
421 if (spi_imx->tx_buf) {
422 memcpy(((u8 *)&val) + sizeof(val) - n_bytes,
423 spi_imx->tx_buf, n_bytes);
424 val = cpu_to_be32(val);
425 spi_imx->tx_buf += n_bytes;
426 }
427
428 spi_imx->count -= n_bytes;
429
430 writel(val, spi_imx->base + MXC_CSPITXDATA);
431}
432
433/* MX51 eCSPI */
434static unsigned int mx51_ecspi_clkdiv(struct spi_imx_data *spi_imx,
435 unsigned int fspi, unsigned int *fres)
436{
437 /*
438 * there are two 4-bit dividers, the pre-divider divides by
439 * $pre, the post-divider by 2^$post
440 */
441 unsigned int pre, post;
442 unsigned int fin = spi_imx->spi_clk;
443
444 if (unlikely(fspi > fin))
445 return 0;
446
447 post = fls(fin) - fls(fspi);
448 if (fin > fspi << post)
449 post++;
450
451 /* now we have: (fin <= fspi << post) with post being minimal */
452
453 post = max(4U, post) - 4;
454 if (unlikely(post > 0xf)) {
455 dev_err(spi_imx->dev, "cannot set clock freq: %u (base freq: %u)\n",
456 fspi, fin);
457 return 0xff;
458 }
459
460 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
461
462 dev_dbg(spi_imx->dev, "%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
463 __func__, fin, fspi, post, pre);
464
465 /* Resulting frequency for the SCLK line. */
466 *fres = (fin / (pre + 1)) >> post;
467
468 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
469 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
470}
471
472static void mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
473{
474 unsigned val = 0;
475
476 if (enable & MXC_INT_TE)
477 val |= MX51_ECSPI_INT_TEEN;
478
479 if (enable & MXC_INT_RR)
480 val |= MX51_ECSPI_INT_RREN;
481
482 if (enable & MXC_INT_RDR)
483 val |= MX51_ECSPI_INT_RDREN;
484
485 writel(val, spi_imx->base + MX51_ECSPI_INT);
486}
487
488static void mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
489{
490 u32 reg;
491
492 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
493 reg |= MX51_ECSPI_CTRL_XCH;
494 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
495}
496
497static void mx51_ecspi_disable(struct spi_imx_data *spi_imx)
498{
499 u32 ctrl;
500
501 ctrl = readl(spi_imx->base + MX51_ECSPI_CTRL);
502 ctrl &= ~MX51_ECSPI_CTRL_ENABLE;
503 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
504}
505
506static int mx51_ecspi_config(struct spi_device *spi)
507{
508 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
509 u32 ctrl = MX51_ECSPI_CTRL_ENABLE;
510 u32 clk = spi_imx->speed_hz, delay, reg;
511 u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
512
513 /* set Master or Slave mode */
514 if (spi_imx->slave_mode)
515 ctrl &= ~MX51_ECSPI_CTRL_MODE_MASK;
516 else
517 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
518
519 /*
520 * Enable SPI_RDY handling (falling edge/level triggered).
521 */
522 if (spi->mode & SPI_READY)
523 ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl);
524
525 /* set clock speed */
526 ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->speed_hz, &clk);
527 spi_imx->spi_bus_clk = clk;
528
529 /* set chip select to use */
530 ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select);
531
532 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
533 ctrl |= (spi_imx->slave_burst * 8 - 1)
534 << MX51_ECSPI_CTRL_BL_OFFSET;
535 else
536 ctrl |= (spi_imx->bits_per_word - 1)
537 << MX51_ECSPI_CTRL_BL_OFFSET;
538
539 /*
540 * eCSPI burst completion by Chip Select signal in Slave mode
541 * is not functional for imx53 Soc, config SPI burst completed when
542 * BURST_LENGTH + 1 bits are received
543 */
544 if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx))
545 cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
546 else
547 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
548
549 if (spi->mode & SPI_CPHA)
550 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
551 else
552 cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
553
554 if (spi->mode & SPI_CPOL) {
555 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
556 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
557 } else {
558 cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
559 cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
560 }
561 if (spi->mode & SPI_CS_HIGH)
562 cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
563 else
564 cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select);
565
566 if (spi_imx->usedma)
567 ctrl |= MX51_ECSPI_CTRL_SMC;
568
569 /* CTRL register always go first to bring out controller from reset */
570 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
571
572 reg = readl(spi_imx->base + MX51_ECSPI_TESTREG);
573 if (spi->mode & SPI_LOOP)
574 reg |= MX51_ECSPI_TESTREG_LBC;
575 else
576 reg &= ~MX51_ECSPI_TESTREG_LBC;
577 writel(reg, spi_imx->base + MX51_ECSPI_TESTREG);
578
579 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
580
581 /*
582 * Wait until the changes in the configuration register CONFIGREG
583 * propagate into the hardware. It takes exactly one tick of the
584 * SCLK clock, but we will wait two SCLK clock just to be sure. The
585 * effect of the delay it takes for the hardware to apply changes
586 * is noticable if the SCLK clock run very slow. In such a case, if
587 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
588 * be asserted before the SCLK polarity changes, which would disrupt
589 * the SPI communication as the device on the other end would consider
590 * the change of SCLK polarity as a clock tick already.
591 */
592 delay = (2 * 1000000) / clk;
593 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
594 udelay(delay);
595 else /* SCLK is _very_ slow */
596 usleep_range(delay, delay + 10);
597
598 /*
599 * Configure the DMA register: setup the watermark
600 * and enable DMA request.
601 */
602
603 writel(MX51_ECSPI_DMA_RX_WML(spi_imx->wml) |
604 MX51_ECSPI_DMA_TX_WML(spi_imx->wml) |
605 MX51_ECSPI_DMA_RXT_WML(spi_imx->wml) |
606 MX51_ECSPI_DMA_TEDEN | MX51_ECSPI_DMA_RXDEN |
607 MX51_ECSPI_DMA_RXTDEN, spi_imx->base + MX51_ECSPI_DMA);
608
609 return 0;
610}
611
612static int mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
613{
614 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
615}
616
617static void mx51_ecspi_reset(struct spi_imx_data *spi_imx)
618{
619 /* drain receive buffer */
620 while (mx51_ecspi_rx_available(spi_imx))
621 readl(spi_imx->base + MXC_CSPIRXDATA);
622}
623
624#define MX31_INTREG_TEEN (1 << 0)
625#define MX31_INTREG_RREN (1 << 3)
626
627#define MX31_CSPICTRL_ENABLE (1 << 0)
628#define MX31_CSPICTRL_MASTER (1 << 1)
629#define MX31_CSPICTRL_XCH (1 << 2)
630#define MX31_CSPICTRL_SMC (1 << 3)
631#define MX31_CSPICTRL_POL (1 << 4)
632#define MX31_CSPICTRL_PHA (1 << 5)
633#define MX31_CSPICTRL_SSCTL (1 << 6)
634#define MX31_CSPICTRL_SSPOL (1 << 7)
635#define MX31_CSPICTRL_BC_SHIFT 8
636#define MX35_CSPICTRL_BL_SHIFT 20
637#define MX31_CSPICTRL_CS_SHIFT 24
638#define MX35_CSPICTRL_CS_SHIFT 12
639#define MX31_CSPICTRL_DR_SHIFT 16
640
641#define MX31_CSPI_DMAREG 0x10
642#define MX31_DMAREG_RH_DEN (1<<4)
643#define MX31_DMAREG_TH_DEN (1<<1)
644
645#define MX31_CSPISTATUS 0x14
646#define MX31_STATUS_RR (1 << 3)
647
648#define MX31_CSPI_TESTREG 0x1C
649#define MX31_TEST_LBC (1 << 14)
650
651/* These functions also work for the i.MX35, but be aware that
652 * the i.MX35 has a slightly different register layout for bits
653 * we do not use here.
654 */
655static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
656{
657 unsigned int val = 0;
658
659 if (enable & MXC_INT_TE)
660 val |= MX31_INTREG_TEEN;
661 if (enable & MXC_INT_RR)
662 val |= MX31_INTREG_RREN;
663
664 writel(val, spi_imx->base + MXC_CSPIINT);
665}
666
667static void mx31_trigger(struct spi_imx_data *spi_imx)
668{
669 unsigned int reg;
670
671 reg = readl(spi_imx->base + MXC_CSPICTRL);
672 reg |= MX31_CSPICTRL_XCH;
673 writel(reg, spi_imx->base + MXC_CSPICTRL);
674}
675
676static int mx31_config(struct spi_device *spi)
677{
678 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
679 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
680 unsigned int clk;
681
682 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
683 MX31_CSPICTRL_DR_SHIFT;
684 spi_imx->spi_bus_clk = clk;
685
686 if (is_imx35_cspi(spi_imx)) {
687 reg |= (spi_imx->bits_per_word - 1) << MX35_CSPICTRL_BL_SHIFT;
688 reg |= MX31_CSPICTRL_SSCTL;
689 } else {
690 reg |= (spi_imx->bits_per_word - 1) << MX31_CSPICTRL_BC_SHIFT;
691 }
692
693 if (spi->mode & SPI_CPHA)
694 reg |= MX31_CSPICTRL_PHA;
695 if (spi->mode & SPI_CPOL)
696 reg |= MX31_CSPICTRL_POL;
697 if (spi->mode & SPI_CS_HIGH)
698 reg |= MX31_CSPICTRL_SSPOL;
699 if (!gpio_is_valid(spi->cs_gpio))
700 reg |= (spi->chip_select) <<
701 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
702 MX31_CSPICTRL_CS_SHIFT);
703
704 if (spi_imx->usedma)
705 reg |= MX31_CSPICTRL_SMC;
706
707 writel(reg, spi_imx->base + MXC_CSPICTRL);
708
709 reg = readl(spi_imx->base + MX31_CSPI_TESTREG);
710 if (spi->mode & SPI_LOOP)
711 reg |= MX31_TEST_LBC;
712 else
713 reg &= ~MX31_TEST_LBC;
714 writel(reg, spi_imx->base + MX31_CSPI_TESTREG);
715
716 if (spi_imx->usedma) {
717 /* configure DMA requests when RXFIFO is half full and
718 when TXFIFO is half empty */
719 writel(MX31_DMAREG_RH_DEN | MX31_DMAREG_TH_DEN,
720 spi_imx->base + MX31_CSPI_DMAREG);
721 }
722
723 return 0;
724}
725
726static int mx31_rx_available(struct spi_imx_data *spi_imx)
727{
728 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
729}
730
731static void mx31_reset(struct spi_imx_data *spi_imx)
732{
733 /* drain receive buffer */
734 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
735 readl(spi_imx->base + MXC_CSPIRXDATA);
736}
737
738#define MX21_INTREG_RR (1 << 4)
739#define MX21_INTREG_TEEN (1 << 9)
740#define MX21_INTREG_RREN (1 << 13)
741
742#define MX21_CSPICTRL_POL (1 << 5)
743#define MX21_CSPICTRL_PHA (1 << 6)
744#define MX21_CSPICTRL_SSPOL (1 << 8)
745#define MX21_CSPICTRL_XCH (1 << 9)
746#define MX21_CSPICTRL_ENABLE (1 << 10)
747#define MX21_CSPICTRL_MASTER (1 << 11)
748#define MX21_CSPICTRL_DR_SHIFT 14
749#define MX21_CSPICTRL_CS_SHIFT 19
750
751static void mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
752{
753 unsigned int val = 0;
754
755 if (enable & MXC_INT_TE)
756 val |= MX21_INTREG_TEEN;
757 if (enable & MXC_INT_RR)
758 val |= MX21_INTREG_RREN;
759
760 writel(val, spi_imx->base + MXC_CSPIINT);
761}
762
763static void mx21_trigger(struct spi_imx_data *spi_imx)
764{
765 unsigned int reg;
766
767 reg = readl(spi_imx->base + MXC_CSPICTRL);
768 reg |= MX21_CSPICTRL_XCH;
769 writel(reg, spi_imx->base + MXC_CSPICTRL);
770}
771
772static int mx21_config(struct spi_device *spi)
773{
774 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
775 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
776 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
777 unsigned int clk;
778
779 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, spi_imx->speed_hz, max, &clk)
780 << MX21_CSPICTRL_DR_SHIFT;
781 spi_imx->spi_bus_clk = clk;
782
783 reg |= spi_imx->bits_per_word - 1;
784
785 if (spi->mode & SPI_CPHA)
786 reg |= MX21_CSPICTRL_PHA;
787 if (spi->mode & SPI_CPOL)
788 reg |= MX21_CSPICTRL_POL;
789 if (spi->mode & SPI_CS_HIGH)
790 reg |= MX21_CSPICTRL_SSPOL;
791 if (!gpio_is_valid(spi->cs_gpio))
792 reg |= spi->chip_select << MX21_CSPICTRL_CS_SHIFT;
793
794 writel(reg, spi_imx->base + MXC_CSPICTRL);
795
796 return 0;
797}
798
799static int mx21_rx_available(struct spi_imx_data *spi_imx)
800{
801 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
802}
803
804static void mx21_reset(struct spi_imx_data *spi_imx)
805{
806 writel(1, spi_imx->base + MXC_RESET);
807}
808
809#define MX1_INTREG_RR (1 << 3)
810#define MX1_INTREG_TEEN (1 << 8)
811#define MX1_INTREG_RREN (1 << 11)
812
813#define MX1_CSPICTRL_POL (1 << 4)
814#define MX1_CSPICTRL_PHA (1 << 5)
815#define MX1_CSPICTRL_XCH (1 << 8)
816#define MX1_CSPICTRL_ENABLE (1 << 9)
817#define MX1_CSPICTRL_MASTER (1 << 10)
818#define MX1_CSPICTRL_DR_SHIFT 13
819
820static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
821{
822 unsigned int val = 0;
823
824 if (enable & MXC_INT_TE)
825 val |= MX1_INTREG_TEEN;
826 if (enable & MXC_INT_RR)
827 val |= MX1_INTREG_RREN;
828
829 writel(val, spi_imx->base + MXC_CSPIINT);
830}
831
832static void mx1_trigger(struct spi_imx_data *spi_imx)
833{
834 unsigned int reg;
835
836 reg = readl(spi_imx->base + MXC_CSPICTRL);
837 reg |= MX1_CSPICTRL_XCH;
838 writel(reg, spi_imx->base + MXC_CSPICTRL);
839}
840
841static int mx1_config(struct spi_device *spi)
842{
843 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
844 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
845 unsigned int clk;
846
847 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, spi_imx->speed_hz, &clk) <<
848 MX1_CSPICTRL_DR_SHIFT;
849 spi_imx->spi_bus_clk = clk;
850
851 reg |= spi_imx->bits_per_word - 1;
852
853 if (spi->mode & SPI_CPHA)
854 reg |= MX1_CSPICTRL_PHA;
855 if (spi->mode & SPI_CPOL)
856 reg |= MX1_CSPICTRL_POL;
857
858 writel(reg, spi_imx->base + MXC_CSPICTRL);
859
860 return 0;
861}
862
863static int mx1_rx_available(struct spi_imx_data *spi_imx)
864{
865 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
866}
867
868static void mx1_reset(struct spi_imx_data *spi_imx)
869{
870 writel(1, spi_imx->base + MXC_RESET);
871}
872
873static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
874 .intctrl = mx1_intctrl,
875 .config = mx1_config,
876 .trigger = mx1_trigger,
877 .rx_available = mx1_rx_available,
878 .reset = mx1_reset,
879 .fifo_size = 8,
880 .has_dmamode = false,
881 .dynamic_burst = false,
882 .has_slavemode = false,
883 .devtype = IMX1_CSPI,
884};
885
886static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
887 .intctrl = mx21_intctrl,
888 .config = mx21_config,
889 .trigger = mx21_trigger,
890 .rx_available = mx21_rx_available,
891 .reset = mx21_reset,
892 .fifo_size = 8,
893 .has_dmamode = false,
894 .dynamic_burst = false,
895 .has_slavemode = false,
896 .devtype = IMX21_CSPI,
897};
898
899static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
900 /* i.mx27 cspi shares the functions with i.mx21 one */
901 .intctrl = mx21_intctrl,
902 .config = mx21_config,
903 .trigger = mx21_trigger,
904 .rx_available = mx21_rx_available,
905 .reset = mx21_reset,
906 .fifo_size = 8,
907 .has_dmamode = false,
908 .dynamic_burst = false,
909 .has_slavemode = false,
910 .devtype = IMX27_CSPI,
911};
912
913static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
914 .intctrl = mx31_intctrl,
915 .config = mx31_config,
916 .trigger = mx31_trigger,
917 .rx_available = mx31_rx_available,
918 .reset = mx31_reset,
919 .fifo_size = 8,
920 .has_dmamode = false,
921 .dynamic_burst = false,
922 .has_slavemode = false,
923 .devtype = IMX31_CSPI,
924};
925
926static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
927 /* i.mx35 and later cspi shares the functions with i.mx31 one */
928 .intctrl = mx31_intctrl,
929 .config = mx31_config,
930 .trigger = mx31_trigger,
931 .rx_available = mx31_rx_available,
932 .reset = mx31_reset,
933 .fifo_size = 8,
934 .has_dmamode = true,
935 .dynamic_burst = false,
936 .has_slavemode = false,
937 .devtype = IMX35_CSPI,
938};
939
940static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
941 .intctrl = mx51_ecspi_intctrl,
942 .config = mx51_ecspi_config,
943 .trigger = mx51_ecspi_trigger,
944 .rx_available = mx51_ecspi_rx_available,
945 .reset = mx51_ecspi_reset,
946 .fifo_size = 64,
947 .has_dmamode = true,
948 .dynamic_burst = true,
949 .has_slavemode = true,
950 .disable = mx51_ecspi_disable,
951 .devtype = IMX51_ECSPI,
952};
953
954static struct spi_imx_devtype_data imx53_ecspi_devtype_data = {
955 .intctrl = mx51_ecspi_intctrl,
956 .config = mx51_ecspi_config,
957 .trigger = mx51_ecspi_trigger,
958 .rx_available = mx51_ecspi_rx_available,
959 .reset = mx51_ecspi_reset,
960 .fifo_size = 64,
961 .has_dmamode = true,
962 .has_slavemode = true,
963 .disable = mx51_ecspi_disable,
964 .devtype = IMX53_ECSPI,
965};
966
967static const struct platform_device_id spi_imx_devtype[] = {
968 {
969 .name = "imx1-cspi",
970 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
971 }, {
972 .name = "imx21-cspi",
973 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
974 }, {
975 .name = "imx27-cspi",
976 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
977 }, {
978 .name = "imx31-cspi",
979 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
980 }, {
981 .name = "imx35-cspi",
982 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
983 }, {
984 .name = "imx51-ecspi",
985 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
986 }, {
987 .name = "imx53-ecspi",
988 .driver_data = (kernel_ulong_t) &imx53_ecspi_devtype_data,
989 }, {
990 /* sentinel */
991 }
992};
993
994static const struct of_device_id spi_imx_dt_ids[] = {
995 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
996 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
997 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
998 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
999 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
1000 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
1001 { .compatible = "fsl,imx53-ecspi", .data = &imx53_ecspi_devtype_data, },
1002 { /* sentinel */ }
1003};
1004MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
1005
1006static void spi_imx_chipselect(struct spi_device *spi, int is_active)
1007{
1008 int active = is_active != BITBANG_CS_INACTIVE;
1009 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
1010
1011 if (spi->mode & SPI_NO_CS)
1012 return;
1013
1014 if (!gpio_is_valid(spi->cs_gpio))
1015 return;
1016
1017 gpio_set_value(spi->cs_gpio, dev_is_lowactive ^ active);
1018}
1019
1020static void spi_imx_push(struct spi_imx_data *spi_imx)
1021{
1022 while (spi_imx->txfifo < spi_imx->devtype_data->fifo_size) {
1023 if (!spi_imx->count)
1024 break;
1025 if (spi_imx->txfifo && (spi_imx->count == spi_imx->remainder))
1026 break;
1027 spi_imx->tx(spi_imx);
1028 spi_imx->txfifo++;
1029 }
1030
1031 if (!spi_imx->slave_mode)
1032 spi_imx->devtype_data->trigger(spi_imx);
1033}
1034
1035static irqreturn_t spi_imx_isr(int irq, void *dev_id)
1036{
1037 struct spi_imx_data *spi_imx = dev_id;
1038
1039 while (spi_imx->txfifo &&
1040 spi_imx->devtype_data->rx_available(spi_imx)) {
1041 spi_imx->rx(spi_imx);
1042 spi_imx->txfifo--;
1043 }
1044
1045 if (spi_imx->count) {
1046 spi_imx_push(spi_imx);
1047 return IRQ_HANDLED;
1048 }
1049
1050 if (spi_imx->txfifo) {
1051 /* No data left to push, but still waiting for rx data,
1052 * enable receive data available interrupt.
1053 */
1054 spi_imx->devtype_data->intctrl(
1055 spi_imx, MXC_INT_RR);
1056 return IRQ_HANDLED;
1057 }
1058
1059 spi_imx->devtype_data->intctrl(spi_imx, 0);
1060 complete(&spi_imx->xfer_done);
1061
1062 return IRQ_HANDLED;
1063}
1064
1065static int spi_imx_dma_configure(struct spi_master *master)
1066{
1067 int ret;
1068 enum dma_slave_buswidth buswidth;
1069 struct dma_slave_config rx = {}, tx = {};
1070 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1071
1072 switch (spi_imx_bytes_per_word(spi_imx->bits_per_word)) {
1073 case 4:
1074 buswidth = DMA_SLAVE_BUSWIDTH_4_BYTES;
1075 break;
1076 case 2:
1077 buswidth = DMA_SLAVE_BUSWIDTH_2_BYTES;
1078 break;
1079 case 1:
1080 buswidth = DMA_SLAVE_BUSWIDTH_1_BYTE;
1081 break;
1082 default:
1083 return -EINVAL;
1084 }
1085
1086 tx.direction = DMA_MEM_TO_DEV;
1087 tx.dst_addr = spi_imx->base_phys + MXC_CSPITXDATA;
1088 tx.dst_addr_width = buswidth;
1089 tx.dst_maxburst = spi_imx->wml;
1090 ret = dmaengine_slave_config(master->dma_tx, &tx);
1091 if (ret) {
1092 dev_err(spi_imx->dev, "TX dma configuration failed with %d\n", ret);
1093 return ret;
1094 }
1095
1096 rx.direction = DMA_DEV_TO_MEM;
1097 rx.src_addr = spi_imx->base_phys + MXC_CSPIRXDATA;
1098 rx.src_addr_width = buswidth;
1099 rx.src_maxburst = spi_imx->wml;
1100 ret = dmaengine_slave_config(master->dma_rx, &rx);
1101 if (ret) {
1102 dev_err(spi_imx->dev, "RX dma configuration failed with %d\n", ret);
1103 return ret;
1104 }
1105
1106 return 0;
1107}
1108
1109static int spi_imx_setupxfer(struct spi_device *spi,
1110 struct spi_transfer *t)
1111{
1112 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1113 int ret;
1114
1115 if (!t)
1116 return 0;
1117
1118 spi_imx->bits_per_word = t->bits_per_word;
1119 spi_imx->speed_hz = t->speed_hz;
1120
1121 /* Initialize the functions for transfer */
1122 if (spi_imx->devtype_data->dynamic_burst && !spi_imx->slave_mode) {
1123 u32 mask;
1124
1125 spi_imx->dynamic_burst = 0;
1126 spi_imx->remainder = 0;
1127 spi_imx->read_u32 = 1;
1128
1129 mask = (1 << spi_imx->bits_per_word) - 1;
1130 spi_imx->rx = spi_imx_buf_rx_swap;
1131 spi_imx->tx = spi_imx_buf_tx_swap;
1132 spi_imx->dynamic_burst = 1;
1133 spi_imx->remainder = t->len;
1134
1135 if (spi_imx->bits_per_word <= 8)
1136 spi_imx->word_mask = mask << 24 | mask << 16
1137 | mask << 8 | mask;
1138 else if (spi_imx->bits_per_word <= 16)
1139 spi_imx->word_mask = mask << 16 | mask;
1140 else
1141 spi_imx->word_mask = mask;
1142 } else {
1143 if (spi_imx->bits_per_word <= 8) {
1144 spi_imx->rx = spi_imx_buf_rx_u8;
1145 spi_imx->tx = spi_imx_buf_tx_u8;
1146 } else if (spi_imx->bits_per_word <= 16) {
1147 spi_imx->rx = spi_imx_buf_rx_u16;
1148 spi_imx->tx = spi_imx_buf_tx_u16;
1149 } else {
1150 spi_imx->rx = spi_imx_buf_rx_u32;
1151 spi_imx->tx = spi_imx_buf_tx_u32;
1152 }
1153 }
1154
1155 if (spi_imx_can_dma(spi_imx->bitbang.master, spi, t))
1156 spi_imx->usedma = 1;
1157 else
1158 spi_imx->usedma = 0;
1159
1160 if (spi_imx->usedma) {
1161 ret = spi_imx_dma_configure(spi->master);
1162 if (ret)
1163 return ret;
1164 }
1165
1166 if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
1167 spi_imx->rx = mx53_ecspi_rx_slave;
1168 spi_imx->tx = mx53_ecspi_tx_slave;
1169 spi_imx->slave_burst = t->len;
1170 }
1171
1172 spi_imx->devtype_data->config(spi);
1173
1174 return 0;
1175}
1176
1177static void spi_imx_sdma_exit(struct spi_imx_data *spi_imx)
1178{
1179 struct spi_master *master = spi_imx->bitbang.master;
1180
1181 if (master->dma_rx) {
1182 dma_release_channel(master->dma_rx);
1183 master->dma_rx = NULL;
1184 }
1185
1186 if (master->dma_tx) {
1187 dma_release_channel(master->dma_tx);
1188 master->dma_tx = NULL;
1189 }
1190}
1191
1192static int spi_imx_sdma_init(struct device *dev, struct spi_imx_data *spi_imx,
1193 struct spi_master *master)
1194{
1195 int ret;
1196
1197 /* use pio mode for i.mx6dl chip TKT238285 */
1198 if (of_machine_is_compatible("fsl,imx6dl"))
1199 return 0;
1200
1201 spi_imx->wml = spi_imx->devtype_data->fifo_size / 2;
1202
1203 /* Prepare for TX DMA: */
1204 master->dma_tx = dma_request_slave_channel_reason(dev, "tx");
1205 if (IS_ERR(master->dma_tx)) {
1206 ret = PTR_ERR(master->dma_tx);
1207 dev_dbg(dev, "can't get the TX DMA channel, error %d!\n", ret);
1208 master->dma_tx = NULL;
1209 goto err;
1210 }
1211
1212 /* Prepare for RX : */
1213 master->dma_rx = dma_request_slave_channel_reason(dev, "rx");
1214 if (IS_ERR(master->dma_rx)) {
1215 ret = PTR_ERR(master->dma_rx);
1216 dev_dbg(dev, "can't get the RX DMA channel, error %d\n", ret);
1217 master->dma_rx = NULL;
1218 goto err;
1219 }
1220
1221 init_completion(&spi_imx->dma_rx_completion);
1222 init_completion(&spi_imx->dma_tx_completion);
1223 master->can_dma = spi_imx_can_dma;
1224 master->max_dma_len = MAX_SDMA_BD_BYTES;
1225 spi_imx->bitbang.master->flags = SPI_MASTER_MUST_RX |
1226 SPI_MASTER_MUST_TX;
1227
1228 return 0;
1229err:
1230 spi_imx_sdma_exit(spi_imx);
1231 return ret;
1232}
1233
1234static void spi_imx_dma_rx_callback(void *cookie)
1235{
1236 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1237
1238 complete(&spi_imx->dma_rx_completion);
1239}
1240
1241static void spi_imx_dma_tx_callback(void *cookie)
1242{
1243 struct spi_imx_data *spi_imx = (struct spi_imx_data *)cookie;
1244
1245 complete(&spi_imx->dma_tx_completion);
1246}
1247
1248static int spi_imx_calculate_timeout(struct spi_imx_data *spi_imx, int size)
1249{
1250 unsigned long timeout = 0;
1251
1252 /* Time with actual data transfer and CS change delay related to HW */
1253 timeout = (8 + 4) * size / spi_imx->spi_bus_clk;
1254
1255 /* Add extra second for scheduler related activities */
1256 timeout += 1;
1257
1258 /* Double calculated timeout */
1259 return msecs_to_jiffies(2 * timeout * MSEC_PER_SEC);
1260}
1261
1262static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
1263 struct spi_transfer *transfer)
1264{
1265 struct dma_async_tx_descriptor *desc_tx, *desc_rx;
1266 unsigned long transfer_timeout;
1267 unsigned long timeout;
1268 struct spi_master *master = spi_imx->bitbang.master;
1269 struct sg_table *tx = &transfer->tx_sg, *rx = &transfer->rx_sg;
1270
1271 /*
1272 * The TX DMA setup starts the transfer, so make sure RX is configured
1273 * before TX.
1274 */
1275 desc_rx = dmaengine_prep_slave_sg(master->dma_rx,
1276 rx->sgl, rx->nents, DMA_DEV_TO_MEM,
1277 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1278 if (!desc_rx)
1279 return -EINVAL;
1280
1281 desc_rx->callback = spi_imx_dma_rx_callback;
1282 desc_rx->callback_param = (void *)spi_imx;
1283 dmaengine_submit(desc_rx);
1284 reinit_completion(&spi_imx->dma_rx_completion);
1285 dma_async_issue_pending(master->dma_rx);
1286
1287 desc_tx = dmaengine_prep_slave_sg(master->dma_tx,
1288 tx->sgl, tx->nents, DMA_MEM_TO_DEV,
1289 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1290 if (!desc_tx) {
1291 dmaengine_terminate_all(master->dma_tx);
1292 return -EINVAL;
1293 }
1294
1295 desc_tx->callback = spi_imx_dma_tx_callback;
1296 desc_tx->callback_param = (void *)spi_imx;
1297 dmaengine_submit(desc_tx);
1298 reinit_completion(&spi_imx->dma_tx_completion);
1299 dma_async_issue_pending(master->dma_tx);
1300
1301 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1302
1303 /* Wait SDMA to finish the data transfer.*/
1304 timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
1305 transfer_timeout);
1306 if (!timeout) {
1307 dev_err(spi_imx->dev, "I/O Error in DMA TX\n");
1308 dmaengine_terminate_all(master->dma_tx);
1309 dmaengine_terminate_all(master->dma_rx);
1310 return -ETIMEDOUT;
1311 }
1312
1313 timeout = wait_for_completion_timeout(&spi_imx->dma_rx_completion,
1314 transfer_timeout);
1315 if (!timeout) {
1316 dev_err(&master->dev, "I/O Error in DMA RX\n");
1317 spi_imx->devtype_data->reset(spi_imx);
1318 dmaengine_terminate_all(master->dma_rx);
1319 return -ETIMEDOUT;
1320 }
1321
1322 return transfer->len;
1323}
1324
1325static int spi_imx_pio_transfer(struct spi_device *spi,
1326 struct spi_transfer *transfer)
1327{
1328 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1329 unsigned long transfer_timeout;
1330 unsigned long timeout;
1331
1332 spi_imx->tx_buf = transfer->tx_buf;
1333 spi_imx->rx_buf = transfer->rx_buf;
1334 spi_imx->count = transfer->len;
1335 spi_imx->txfifo = 0;
1336
1337 reinit_completion(&spi_imx->xfer_done);
1338
1339 spi_imx_push(spi_imx);
1340
1341 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
1342
1343 transfer_timeout = spi_imx_calculate_timeout(spi_imx, transfer->len);
1344
1345 timeout = wait_for_completion_timeout(&spi_imx->xfer_done,
1346 transfer_timeout);
1347 if (!timeout) {
1348 dev_err(&spi->dev, "I/O Error in PIO\n");
1349 spi_imx->devtype_data->reset(spi_imx);
1350 return -ETIMEDOUT;
1351 }
1352
1353 return transfer->len;
1354}
1355
1356static int spi_imx_pio_transfer_slave(struct spi_device *spi,
1357 struct spi_transfer *transfer)
1358{
1359 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1360 int ret = transfer->len;
1361
1362 if (is_imx53_ecspi(spi_imx) &&
1363 transfer->len > MX53_MAX_TRANSFER_BYTES) {
1364 dev_err(&spi->dev, "Transaction too big, max size is %d bytes\n",
1365 MX53_MAX_TRANSFER_BYTES);
1366 return -EMSGSIZE;
1367 }
1368
1369 spi_imx->tx_buf = transfer->tx_buf;
1370 spi_imx->rx_buf = transfer->rx_buf;
1371 spi_imx->count = transfer->len;
1372 spi_imx->txfifo = 0;
1373
1374 reinit_completion(&spi_imx->xfer_done);
1375 spi_imx->slave_aborted = false;
1376
1377 spi_imx_push(spi_imx);
1378
1379 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE | MXC_INT_RDR);
1380
1381 if (wait_for_completion_interruptible(&spi_imx->xfer_done) ||
1382 spi_imx->slave_aborted) {
1383 dev_dbg(&spi->dev, "interrupted\n");
1384 ret = -EINTR;
1385 }
1386
1387 /* ecspi has a HW issue when works in Slave mode,
1388 * after 64 words writtern to TXFIFO, even TXFIFO becomes empty,
1389 * ECSPI_TXDATA keeps shift out the last word data,
1390 * so we have to disable ECSPI when in slave mode after the
1391 * transfer completes
1392 */
1393 if (spi_imx->devtype_data->disable)
1394 spi_imx->devtype_data->disable(spi_imx);
1395
1396 return ret;
1397}
1398
1399static int spi_imx_transfer(struct spi_device *spi,
1400 struct spi_transfer *transfer)
1401{
1402 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
1403
1404 /* flush rxfifo before transfer */
1405 while (spi_imx->devtype_data->rx_available(spi_imx))
1406 spi_imx->rx(spi_imx);
1407
1408 if (spi_imx->slave_mode)
1409 return spi_imx_pio_transfer_slave(spi, transfer);
1410
1411 if (spi_imx->usedma)
1412 return spi_imx_dma_transfer(spi_imx, transfer);
1413 else
1414 return spi_imx_pio_transfer(spi, transfer);
1415}
1416
1417static int spi_imx_setup(struct spi_device *spi)
1418{
1419 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
1420 spi->mode, spi->bits_per_word, spi->max_speed_hz);
1421
1422 if (spi->mode & SPI_NO_CS)
1423 return 0;
1424
1425 if (gpio_is_valid(spi->cs_gpio))
1426 gpio_direction_output(spi->cs_gpio,
1427 spi->mode & SPI_CS_HIGH ? 0 : 1);
1428
1429 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
1430
1431 return 0;
1432}
1433
1434static void spi_imx_cleanup(struct spi_device *spi)
1435{
1436}
1437
1438static int
1439spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
1440{
1441 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1442 int ret;
1443
1444 ret = clk_enable(spi_imx->clk_per);
1445 if (ret)
1446 return ret;
1447
1448 ret = clk_enable(spi_imx->clk_ipg);
1449 if (ret) {
1450 clk_disable(spi_imx->clk_per);
1451 return ret;
1452 }
1453
1454 return 0;
1455}
1456
1457static int
1458spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
1459{
1460 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1461
1462 clk_disable(spi_imx->clk_ipg);
1463 clk_disable(spi_imx->clk_per);
1464 return 0;
1465}
1466
1467static int spi_imx_slave_abort(struct spi_master *master)
1468{
1469 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1470
1471 spi_imx->slave_aborted = true;
1472 complete(&spi_imx->xfer_done);
1473
1474 return 0;
1475}
1476
1477static int spi_imx_probe(struct platform_device *pdev)
1478{
1479 struct device_node *np = pdev->dev.of_node;
1480 const struct of_device_id *of_id =
1481 of_match_device(spi_imx_dt_ids, &pdev->dev);
1482 struct spi_imx_master *mxc_platform_info =
1483 dev_get_platdata(&pdev->dev);
1484 struct spi_master *master;
1485 struct spi_imx_data *spi_imx;
1486 struct resource *res;
1487 int i, ret, irq, spi_drctl;
1488 const struct spi_imx_devtype_data *devtype_data = of_id ? of_id->data :
1489 (struct spi_imx_devtype_data *)pdev->id_entry->driver_data;
1490 bool slave_mode;
1491
1492 if (!np && !mxc_platform_info) {
1493 dev_err(&pdev->dev, "can't get the platform data\n");
1494 return -EINVAL;
1495 }
1496
1497 slave_mode = devtype_data->has_slavemode &&
1498 of_property_read_bool(np, "spi-slave");
1499 if (slave_mode)
1500 master = spi_alloc_slave(&pdev->dev,
1501 sizeof(struct spi_imx_data));
1502 else
1503 master = spi_alloc_master(&pdev->dev,
1504 sizeof(struct spi_imx_data));
1505 if (!master)
1506 return -ENOMEM;
1507
1508 ret = of_property_read_u32(np, "fsl,spi-rdy-drctl", &spi_drctl);
1509 if ((ret < 0) || (spi_drctl >= 0x3)) {
1510 /* '11' is reserved */
1511 spi_drctl = 0;
1512 }
1513
1514 platform_set_drvdata(pdev, master);
1515
1516 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
1517 master->bus_num = np ? -1 : pdev->id;
1518
1519 spi_imx = spi_master_get_devdata(master);
1520 spi_imx->bitbang.master = master;
1521 spi_imx->dev = &pdev->dev;
1522 spi_imx->slave_mode = slave_mode;
1523
1524 spi_imx->devtype_data = devtype_data;
1525
1526 /* Get number of chip selects, either platform data or OF */
1527 if (mxc_platform_info) {
1528 master->num_chipselect = mxc_platform_info->num_chipselect;
1529 if (mxc_platform_info->chipselect) {
1530 master->cs_gpios = devm_kzalloc(&master->dev,
1531 sizeof(int) * master->num_chipselect, GFP_KERNEL);
1532 if (!master->cs_gpios)
1533 return -ENOMEM;
1534
1535 for (i = 0; i < master->num_chipselect; i++)
1536 master->cs_gpios[i] = mxc_platform_info->chipselect[i];
1537 }
1538 } else {
1539 u32 num_cs;
1540
1541 if (!of_property_read_u32(np, "num-cs", &num_cs))
1542 master->num_chipselect = num_cs;
1543 /* If not preset, default value of 1 is used */
1544 }
1545
1546 spi_imx->bitbang.chipselect = spi_imx_chipselect;
1547 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
1548 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
1549 spi_imx->bitbang.master->setup = spi_imx_setup;
1550 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
1551 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
1552 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
1553 spi_imx->bitbang.master->slave_abort = spi_imx_slave_abort;
1554 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH \
1555 | SPI_NO_CS;
1556 if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) ||
1557 is_imx53_ecspi(spi_imx))
1558 spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
1559
1560 spi_imx->spi_drctl = spi_drctl;
1561
1562 init_completion(&spi_imx->xfer_done);
1563
1564 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1565 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
1566 if (IS_ERR(spi_imx->base)) {
1567 ret = PTR_ERR(spi_imx->base);
1568 goto out_master_put;
1569 }
1570 spi_imx->base_phys = res->start;
1571
1572 irq = platform_get_irq(pdev, 0);
1573 if (irq < 0) {
1574 ret = irq;
1575 goto out_master_put;
1576 }
1577
1578 ret = devm_request_irq(&pdev->dev, irq, spi_imx_isr, 0,
1579 dev_name(&pdev->dev), spi_imx);
1580 if (ret) {
1581 dev_err(&pdev->dev, "can't get irq%d: %d\n", irq, ret);
1582 goto out_master_put;
1583 }
1584
1585 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1586 if (IS_ERR(spi_imx->clk_ipg)) {
1587 ret = PTR_ERR(spi_imx->clk_ipg);
1588 goto out_master_put;
1589 }
1590
1591 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
1592 if (IS_ERR(spi_imx->clk_per)) {
1593 ret = PTR_ERR(spi_imx->clk_per);
1594 goto out_master_put;
1595 }
1596
1597 ret = clk_prepare_enable(spi_imx->clk_per);
1598 if (ret)
1599 goto out_master_put;
1600
1601 ret = clk_prepare_enable(spi_imx->clk_ipg);
1602 if (ret)
1603 goto out_put_per;
1604
1605 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
1606 /*
1607 * Only validated on i.mx35 and i.mx6 now, can remove the constraint
1608 * if validated on other chips.
1609 */
1610 if (spi_imx->devtype_data->has_dmamode) {
1611 ret = spi_imx_sdma_init(&pdev->dev, spi_imx, master);
1612 if (ret == -EPROBE_DEFER)
1613 goto out_clk_put;
1614
1615 if (ret < 0)
1616 dev_err(&pdev->dev, "dma setup error %d, use pio\n",
1617 ret);
1618 }
1619
1620 spi_imx->devtype_data->reset(spi_imx);
1621
1622 spi_imx->devtype_data->intctrl(spi_imx, 0);
1623
1624 master->dev.of_node = pdev->dev.of_node;
1625 ret = spi_bitbang_start(&spi_imx->bitbang);
1626 if (ret) {
1627 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
1628 goto out_clk_put;
1629 }
1630
1631 /* Request GPIO CS lines, if any */
1632 if (!spi_imx->slave_mode && master->cs_gpios) {
1633 for (i = 0; i < master->num_chipselect; i++) {
1634 if (!gpio_is_valid(master->cs_gpios[i]))
1635 continue;
1636
1637 ret = devm_gpio_request(&pdev->dev,
1638 master->cs_gpios[i],
1639 DRIVER_NAME);
1640 if (ret) {
1641 dev_err(&pdev->dev, "Can't get CS GPIO %i\n",
1642 master->cs_gpios[i]);
1643 goto out_spi_bitbang;
1644 }
1645 }
1646 }
1647
1648 dev_info(&pdev->dev, "probed\n");
1649
1650 clk_disable(spi_imx->clk_ipg);
1651 clk_disable(spi_imx->clk_per);
1652 return ret;
1653
1654out_spi_bitbang:
1655 spi_bitbang_stop(&spi_imx->bitbang);
1656out_clk_put:
1657 clk_disable_unprepare(spi_imx->clk_ipg);
1658out_put_per:
1659 clk_disable_unprepare(spi_imx->clk_per);
1660out_master_put:
1661 spi_master_put(master);
1662
1663 return ret;
1664}
1665
1666static int spi_imx_remove(struct platform_device *pdev)
1667{
1668 struct spi_master *master = platform_get_drvdata(pdev);
1669 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
1670 int ret;
1671
1672 spi_bitbang_stop(&spi_imx->bitbang);
1673
1674 ret = clk_enable(spi_imx->clk_per);
1675 if (ret)
1676 return ret;
1677
1678 ret = clk_enable(spi_imx->clk_ipg);
1679 if (ret) {
1680 clk_disable(spi_imx->clk_per);
1681 return ret;
1682 }
1683
1684 writel(0, spi_imx->base + MXC_CSPICTRL);
1685 clk_disable_unprepare(spi_imx->clk_ipg);
1686 clk_disable_unprepare(spi_imx->clk_per);
1687 spi_imx_sdma_exit(spi_imx);
1688 spi_master_put(master);
1689
1690 return 0;
1691}
1692
1693static struct platform_driver spi_imx_driver = {
1694 .driver = {
1695 .name = DRIVER_NAME,
1696 .of_match_table = spi_imx_dt_ids,
1697 },
1698 .id_table = spi_imx_devtype,
1699 .probe = spi_imx_probe,
1700 .remove = spi_imx_remove,
1701};
1702module_platform_driver(spi_imx_driver);
1703
1704MODULE_DESCRIPTION("SPI Controller driver");
1705MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1706MODULE_LICENSE("GPL");
1707MODULE_ALIAS("platform:" DRIVER_NAME);