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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#include <linux/pci.h>
6
7/* Number of possible devfns: 0.0 to 1f.7 inclusive */
8#define MAX_NR_DEVFNS 256
9
10#define PCI_FIND_CAP_TTL 48
11
12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
15
16/*
17 * Power stable to PERST# inactive.
18 *
19 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
20 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
21 * "T_PVPERL".
22 */
23#define PCIE_T_PVPERL_MS 100
24
25/*
26 * REFCLK stable before PERST# inactive.
27 *
28 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
29 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
30 * "T_PERST-CLK".
31 */
32#define PCIE_T_PERST_CLK_US 100
33
34/*
35 * End of conventional reset (PERST# de-asserted) to first configuration
36 * request (device able to respond with a "Request Retry Status" completion),
37 * from PCIe r6.0, sec 6.6.1.
38 */
39#define PCIE_T_RRS_READY_MS 100
40
41/*
42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
43 * Recommends 1ms to 10ms timeout to check L2 ready.
44 */
45#define PCIE_PME_TO_L2_TIMEOUT_US 10000
46
47/*
48 * PCIe r6.0, sec 6.6.1 <Conventional Reset>
49 *
50 * - "With a Downstream Port that does not support Link speeds greater
51 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit
52 * from a Conventional Reset before sending a Configuration Request to
53 * the device immediately below that Port."
54 *
55 * - "With a Downstream Port that supports Link speeds greater than
56 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training
57 * completes before sending a Configuration Request to the device
58 * immediately below that Port."
59 */
60#define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100
61
62/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
63#define PCIE_MSG_TYPE_R_RC 0
64#define PCIE_MSG_TYPE_R_ADDR 1
65#define PCIE_MSG_TYPE_R_ID 2
66#define PCIE_MSG_TYPE_R_BC 3
67#define PCIE_MSG_TYPE_R_LOCAL 4
68#define PCIE_MSG_TYPE_R_GATHER 5
69
70/* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */
71#define PCIE_MSG_CODE_PME_TURN_OFF 0x19
72
73/* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */
74#define PCIE_MSG_CODE_ASSERT_INTA 0x20
75#define PCIE_MSG_CODE_ASSERT_INTB 0x21
76#define PCIE_MSG_CODE_ASSERT_INTC 0x22
77#define PCIE_MSG_CODE_ASSERT_INTD 0x23
78#define PCIE_MSG_CODE_DEASSERT_INTA 0x24
79#define PCIE_MSG_CODE_DEASSERT_INTB 0x25
80#define PCIE_MSG_CODE_DEASSERT_INTC 0x26
81#define PCIE_MSG_CODE_DEASSERT_INTD 0x27
82
83extern const unsigned char pcie_link_speed[];
84extern bool pci_early_dump;
85
86bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
87bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
88bool pcie_cap_has_rtctl(const struct pci_dev *dev);
89
90/* Functions internal to the PCI core code */
91
92#ifdef CONFIG_DMI
93extern const struct attribute_group pci_dev_smbios_attr_group;
94#endif
95
96enum pci_mmap_api {
97 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
98 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
99};
100int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
101 enum pci_mmap_api mmap_api);
102
103bool pci_reset_supported(struct pci_dev *dev);
104void pci_init_reset_methods(struct pci_dev *dev);
105int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
106int pci_bus_error_reset(struct pci_dev *dev);
107int __pci_reset_bus(struct pci_bus *bus);
108
109struct pci_cap_saved_data {
110 u16 cap_nr;
111 bool cap_extended;
112 unsigned int size;
113 u32 data[];
114};
115
116struct pci_cap_saved_state {
117 struct hlist_node next;
118 struct pci_cap_saved_data cap;
119};
120
121void pci_allocate_cap_save_buffers(struct pci_dev *dev);
122void pci_free_cap_save_buffers(struct pci_dev *dev);
123int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
124int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
125 u16 cap, unsigned int size);
126struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
127struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
128 u16 cap);
129
130#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
131#define PCI_PM_D3HOT_WAIT 10 /* msec */
132#define PCI_PM_D3COLD_WAIT 100 /* msec */
133
134void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
135void pci_refresh_power_state(struct pci_dev *dev);
136int pci_power_up(struct pci_dev *dev);
137void pci_disable_enabled_device(struct pci_dev *dev);
138int pci_finish_runtime_suspend(struct pci_dev *dev);
139void pcie_clear_device_status(struct pci_dev *dev);
140void pcie_clear_root_pme_status(struct pci_dev *dev);
141bool pci_check_pme_status(struct pci_dev *dev);
142void pci_pme_wakeup_bus(struct pci_bus *bus);
143void pci_pme_restore(struct pci_dev *dev);
144bool pci_dev_need_resume(struct pci_dev *dev);
145void pci_dev_adjust_pme(struct pci_dev *dev);
146void pci_dev_complete_resume(struct pci_dev *pci_dev);
147void pci_config_pm_runtime_get(struct pci_dev *dev);
148void pci_config_pm_runtime_put(struct pci_dev *dev);
149void pci_pm_init(struct pci_dev *dev);
150void pci_ea_init(struct pci_dev *dev);
151void pci_msi_init(struct pci_dev *dev);
152void pci_msix_init(struct pci_dev *dev);
153bool pci_bridge_d3_possible(struct pci_dev *dev);
154void pci_bridge_d3_update(struct pci_dev *dev);
155int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
156
157static inline bool pci_bus_rrs_vendor_id(u32 l)
158{
159 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
160}
161
162static inline void pci_wakeup_event(struct pci_dev *dev)
163{
164 /* Wait 100 ms before the system can be put into a sleep state. */
165 pm_wakeup_event(&dev->dev, 100);
166}
167
168static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
169{
170 return !!(pci_dev->subordinate);
171}
172
173static inline bool pci_power_manageable(struct pci_dev *pci_dev)
174{
175 /*
176 * Currently we allow normal PCI devices and PCI bridges transition
177 * into D3 if their bridge_d3 is set.
178 */
179 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
180}
181
182static inline bool pcie_downstream_port(const struct pci_dev *dev)
183{
184 int type = pci_pcie_type(dev);
185
186 return type == PCI_EXP_TYPE_ROOT_PORT ||
187 type == PCI_EXP_TYPE_DOWNSTREAM ||
188 type == PCI_EXP_TYPE_PCIE_BRIDGE;
189}
190
191void pci_vpd_init(struct pci_dev *dev);
192extern const struct attribute_group pci_dev_vpd_attr_group;
193
194/* PCI Virtual Channel */
195int pci_save_vc_state(struct pci_dev *dev);
196void pci_restore_vc_state(struct pci_dev *dev);
197void pci_allocate_vc_save_buffers(struct pci_dev *dev);
198
199/* PCI /proc functions */
200#ifdef CONFIG_PROC_FS
201int pci_proc_attach_device(struct pci_dev *dev);
202int pci_proc_detach_device(struct pci_dev *dev);
203int pci_proc_detach_bus(struct pci_bus *bus);
204#else
205static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
206static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
207static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
208#endif
209
210/* Functions for PCI Hotplug drivers to use */
211int pci_hp_add_bridge(struct pci_dev *dev);
212
213#if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)
214void pci_create_legacy_files(struct pci_bus *bus);
215void pci_remove_legacy_files(struct pci_bus *bus);
216#else
217static inline void pci_create_legacy_files(struct pci_bus *bus) { }
218static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
219#endif
220
221/* Lock for read/write access to pci device and bus lists */
222extern struct rw_semaphore pci_bus_sem;
223extern struct mutex pci_slot_mutex;
224
225extern raw_spinlock_t pci_lock;
226
227extern unsigned int pci_pm_d3hot_delay;
228
229#ifdef CONFIG_PCI_MSI
230void pci_no_msi(void);
231#else
232static inline void pci_no_msi(void) { }
233#endif
234
235void pci_realloc_get_opt(char *);
236
237static inline int pci_no_d1d2(struct pci_dev *dev)
238{
239 unsigned int parent_dstates = 0;
240
241 if (dev->bus->self)
242 parent_dstates = dev->bus->self->no_d1d2;
243 return (dev->no_d1d2 || parent_dstates);
244
245}
246
247#ifdef CONFIG_SYSFS
248int pci_create_sysfs_dev_files(struct pci_dev *pdev);
249void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
250extern const struct attribute_group *pci_dev_groups[];
251extern const struct attribute_group *pci_dev_attr_groups[];
252extern const struct attribute_group *pcibus_groups[];
253extern const struct attribute_group *pci_bus_groups[];
254#else
255static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
256static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
257#define pci_dev_groups NULL
258#define pci_dev_attr_groups NULL
259#define pcibus_groups NULL
260#define pci_bus_groups NULL
261#endif
262
263extern unsigned long pci_hotplug_io_size;
264extern unsigned long pci_hotplug_mmio_size;
265extern unsigned long pci_hotplug_mmio_pref_size;
266extern unsigned long pci_hotplug_bus_size;
267
268/**
269 * pci_match_one_device - Tell if a PCI device structure has a matching
270 * PCI device id structure
271 * @id: single PCI device id structure to match
272 * @dev: the PCI device structure to match against
273 *
274 * Returns the matching pci_device_id structure or %NULL if there is no match.
275 */
276static inline const struct pci_device_id *
277pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
278{
279 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
280 (id->device == PCI_ANY_ID || id->device == dev->device) &&
281 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
282 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
283 !((id->class ^ dev->class) & id->class_mask))
284 return id;
285 return NULL;
286}
287
288/* PCI slot sysfs helper code */
289#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
290
291extern struct kset *pci_slots_kset;
292
293struct pci_slot_attribute {
294 struct attribute attr;
295 ssize_t (*show)(struct pci_slot *, char *);
296 ssize_t (*store)(struct pci_slot *, const char *, size_t);
297};
298#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
299
300enum pci_bar_type {
301 pci_bar_unknown, /* Standard PCI BAR probe */
302 pci_bar_io, /* An I/O port BAR */
303 pci_bar_mem32, /* A 32-bit memory BAR */
304 pci_bar_mem64, /* A 64-bit memory BAR */
305};
306
307struct device *pci_get_host_bridge_device(struct pci_dev *dev);
308void pci_put_host_bridge_device(struct device *dev);
309
310int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
311bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
312 int rrs_timeout);
313bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
314 int rrs_timeout);
315int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);
316
317int pci_setup_device(struct pci_dev *dev);
318int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
319 struct resource *res, unsigned int reg);
320void pci_configure_ari(struct pci_dev *dev);
321void __pci_bus_size_bridges(struct pci_bus *bus,
322 struct list_head *realloc_head);
323void __pci_bus_assign_resources(const struct pci_bus *bus,
324 struct list_head *realloc_head,
325 struct list_head *fail_head);
326bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
327void pci_walk_bus_locked(struct pci_bus *top,
328 int (*cb)(struct pci_dev *, void *),
329 void *userdata);
330
331const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
332
333void pci_reassigndev_resource_alignment(struct pci_dev *dev);
334void pci_disable_bridge_window(struct pci_dev *dev);
335struct pci_bus *pci_bus_get(struct pci_bus *bus);
336void pci_bus_put(struct pci_bus *bus);
337
338#define PCIE_LNKCAP_SLS2SPEED(lnkcap) \
339({ \
340 ((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
341 (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
342 (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
343 (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
344 (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
345 (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
346 PCI_SPEED_UNKNOWN); \
347})
348
349/* PCIe link information from Link Capabilities 2 */
350#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
351 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
352 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
353 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
354 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
355 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
356 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
357 PCI_SPEED_UNKNOWN)
358
359#define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \
360 ((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
361 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
362 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
363 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
364 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
365 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
366 PCI_SPEED_UNKNOWN)
367
368/* PCIe speed to Mb/s reduced by encoding overhead */
369#define PCIE_SPEED2MBS_ENC(speed) \
370 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
371 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
372 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
373 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
374 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
375 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
376 0)
377
378static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
379{
380 switch (speed) {
381 case PCIE_SPEED_2_5GT:
382 return 2500;
383 case PCIE_SPEED_5_0GT:
384 return 5000;
385 case PCIE_SPEED_8_0GT:
386 return 8000;
387 case PCIE_SPEED_16_0GT:
388 return 16000;
389 case PCIE_SPEED_32_0GT:
390 return 32000;
391 case PCIE_SPEED_64_0GT:
392 return 64000;
393 default:
394 break;
395 }
396
397 return -EINVAL;
398}
399
400u8 pcie_get_supported_speeds(struct pci_dev *dev);
401const char *pci_speed_string(enum pci_bus_speed speed);
402void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
403void pcie_report_downtraining(struct pci_dev *dev);
404
405static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
406{
407 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
408}
409void pcie_update_link_speed(struct pci_bus *bus);
410
411/* Single Root I/O Virtualization */
412struct pci_sriov {
413 int pos; /* Capability position */
414 int nres; /* Number of resources */
415 u32 cap; /* SR-IOV Capabilities */
416 u16 ctrl; /* SR-IOV Control */
417 u16 total_VFs; /* Total VFs associated with the PF */
418 u16 initial_VFs; /* Initial VFs associated with the PF */
419 u16 num_VFs; /* Number of VFs available */
420 u16 offset; /* First VF Routing ID offset */
421 u16 stride; /* Following VF stride */
422 u16 vf_device; /* VF device ID */
423 u32 pgsz; /* Page size for BAR alignment */
424 u8 link; /* Function Dependency Link */
425 u8 max_VF_buses; /* Max buses consumed by VFs */
426 u16 driver_max_VFs; /* Max num VFs driver supports */
427 struct pci_dev *dev; /* Lowest numbered PF */
428 struct pci_dev *self; /* This PF */
429 u32 class; /* VF device */
430 u8 hdr_type; /* VF header type */
431 u16 subsystem_vendor; /* VF subsystem vendor */
432 u16 subsystem_device; /* VF subsystem device */
433 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
434 bool drivers_autoprobe; /* Auto probing of VFs by driver */
435};
436
437#ifdef CONFIG_PCI_DOE
438void pci_doe_init(struct pci_dev *pdev);
439void pci_doe_destroy(struct pci_dev *pdev);
440void pci_doe_disconnected(struct pci_dev *pdev);
441#else
442static inline void pci_doe_init(struct pci_dev *pdev) { }
443static inline void pci_doe_destroy(struct pci_dev *pdev) { }
444static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
445#endif
446
447#ifdef CONFIG_PCI_NPEM
448void pci_npem_create(struct pci_dev *dev);
449void pci_npem_remove(struct pci_dev *dev);
450#else
451static inline void pci_npem_create(struct pci_dev *dev) { }
452static inline void pci_npem_remove(struct pci_dev *dev) { }
453#endif
454
455/**
456 * pci_dev_set_io_state - Set the new error state if possible.
457 *
458 * @dev: PCI device to set new error_state
459 * @new: the state we want dev to be in
460 *
461 * If the device is experiencing perm_failure, it has to remain in that state.
462 * Any other transition is allowed.
463 *
464 * Returns true if state has been changed to the requested state.
465 */
466static inline bool pci_dev_set_io_state(struct pci_dev *dev,
467 pci_channel_state_t new)
468{
469 pci_channel_state_t old;
470
471 switch (new) {
472 case pci_channel_io_perm_failure:
473 xchg(&dev->error_state, pci_channel_io_perm_failure);
474 return true;
475 case pci_channel_io_frozen:
476 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
477 pci_channel_io_frozen);
478 return old != pci_channel_io_perm_failure;
479 case pci_channel_io_normal:
480 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
481 pci_channel_io_normal);
482 return old != pci_channel_io_perm_failure;
483 default:
484 return false;
485 }
486}
487
488static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
489{
490 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
491 pci_doe_disconnected(dev);
492
493 return 0;
494}
495
496/* pci_dev priv_flags */
497#define PCI_DEV_ADDED 0
498#define PCI_DPC_RECOVERED 1
499#define PCI_DPC_RECOVERING 2
500#define PCI_DEV_REMOVED 3
501
502static inline void pci_dev_assign_added(struct pci_dev *dev)
503{
504 smp_mb__before_atomic();
505 set_bit(PCI_DEV_ADDED, &dev->priv_flags);
506 smp_mb__after_atomic();
507}
508
509static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev)
510{
511 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags);
512}
513
514static inline bool pci_dev_is_added(const struct pci_dev *dev)
515{
516 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
517}
518
519static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev)
520{
521 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags);
522}
523
524#ifdef CONFIG_PCIEAER
525#include <linux/aer.h>
526
527#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
528
529struct aer_err_info {
530 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
531 int error_dev_num;
532
533 unsigned int id:16;
534
535 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
536 unsigned int __pad1:5;
537 unsigned int multi_error_valid:1;
538
539 unsigned int first_error:5;
540 unsigned int __pad2:2;
541 unsigned int tlp_header_valid:1;
542
543 unsigned int status; /* COR/UNCOR Error Status */
544 unsigned int mask; /* COR/UNCOR Error Mask */
545 struct pcie_tlp_log tlp; /* TLP Header */
546};
547
548int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
549void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
550#endif /* CONFIG_PCIEAER */
551
552#ifdef CONFIG_PCIEPORTBUS
553/* Cached RCEC Endpoint Association */
554struct rcec_ea {
555 u8 nextbusn;
556 u8 lastbusn;
557 u32 bitmap;
558};
559#endif
560
561#ifdef CONFIG_PCIE_DPC
562void pci_save_dpc_state(struct pci_dev *dev);
563void pci_restore_dpc_state(struct pci_dev *dev);
564void pci_dpc_init(struct pci_dev *pdev);
565void dpc_process_error(struct pci_dev *pdev);
566pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
567bool pci_dpc_recovered(struct pci_dev *pdev);
568#else
569static inline void pci_save_dpc_state(struct pci_dev *dev) { }
570static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
571static inline void pci_dpc_init(struct pci_dev *pdev) { }
572static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
573#endif
574
575#ifdef CONFIG_PCIEPORTBUS
576void pci_rcec_init(struct pci_dev *dev);
577void pci_rcec_exit(struct pci_dev *dev);
578void pcie_link_rcec(struct pci_dev *rcec);
579void pcie_walk_rcec(struct pci_dev *rcec,
580 int (*cb)(struct pci_dev *, void *),
581 void *userdata);
582#else
583static inline void pci_rcec_init(struct pci_dev *dev) { }
584static inline void pci_rcec_exit(struct pci_dev *dev) { }
585static inline void pcie_link_rcec(struct pci_dev *rcec) { }
586static inline void pcie_walk_rcec(struct pci_dev *rcec,
587 int (*cb)(struct pci_dev *, void *),
588 void *userdata) { }
589#endif
590
591#ifdef CONFIG_PCI_ATS
592/* Address Translation Service */
593void pci_ats_init(struct pci_dev *dev);
594void pci_restore_ats_state(struct pci_dev *dev);
595#else
596static inline void pci_ats_init(struct pci_dev *d) { }
597static inline void pci_restore_ats_state(struct pci_dev *dev) { }
598#endif /* CONFIG_PCI_ATS */
599
600#ifdef CONFIG_PCI_PRI
601void pci_pri_init(struct pci_dev *dev);
602void pci_restore_pri_state(struct pci_dev *pdev);
603#else
604static inline void pci_pri_init(struct pci_dev *dev) { }
605static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
606#endif
607
608#ifdef CONFIG_PCI_PASID
609void pci_pasid_init(struct pci_dev *dev);
610void pci_restore_pasid_state(struct pci_dev *pdev);
611#else
612static inline void pci_pasid_init(struct pci_dev *dev) { }
613static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
614#endif
615
616#ifdef CONFIG_PCI_IOV
617int pci_iov_init(struct pci_dev *dev);
618void pci_iov_release(struct pci_dev *dev);
619void pci_iov_remove(struct pci_dev *dev);
620void pci_iov_update_resource(struct pci_dev *dev, int resno);
621resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
622void pci_restore_iov_state(struct pci_dev *dev);
623int pci_iov_bus_range(struct pci_bus *bus);
624extern const struct attribute_group sriov_pf_dev_attr_group;
625extern const struct attribute_group sriov_vf_dev_attr_group;
626#else
627static inline int pci_iov_init(struct pci_dev *dev)
628{
629 return -ENODEV;
630}
631static inline void pci_iov_release(struct pci_dev *dev) { }
632static inline void pci_iov_remove(struct pci_dev *dev) { }
633static inline void pci_restore_iov_state(struct pci_dev *dev) { }
634static inline int pci_iov_bus_range(struct pci_bus *bus)
635{
636 return 0;
637}
638
639#endif /* CONFIG_PCI_IOV */
640
641#ifdef CONFIG_PCIE_TPH
642void pci_restore_tph_state(struct pci_dev *dev);
643void pci_save_tph_state(struct pci_dev *dev);
644void pci_no_tph(void);
645void pci_tph_init(struct pci_dev *dev);
646#else
647static inline void pci_restore_tph_state(struct pci_dev *dev) { }
648static inline void pci_save_tph_state(struct pci_dev *dev) { }
649static inline void pci_no_tph(void) { }
650static inline void pci_tph_init(struct pci_dev *dev) { }
651#endif
652
653#ifdef CONFIG_PCIE_PTM
654void pci_ptm_init(struct pci_dev *dev);
655void pci_save_ptm_state(struct pci_dev *dev);
656void pci_restore_ptm_state(struct pci_dev *dev);
657void pci_suspend_ptm(struct pci_dev *dev);
658void pci_resume_ptm(struct pci_dev *dev);
659#else
660static inline void pci_ptm_init(struct pci_dev *dev) { }
661static inline void pci_save_ptm_state(struct pci_dev *dev) { }
662static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
663static inline void pci_suspend_ptm(struct pci_dev *dev) { }
664static inline void pci_resume_ptm(struct pci_dev *dev) { }
665#endif
666
667unsigned long pci_cardbus_resource_alignment(struct resource *);
668
669static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
670 struct resource *res)
671{
672#ifdef CONFIG_PCI_IOV
673 int resno = res - dev->resource;
674
675 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
676 return pci_sriov_resource_alignment(dev, resno);
677#endif
678 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
679 return pci_cardbus_resource_alignment(res);
680 return resource_alignment(res);
681}
682
683void pci_acs_init(struct pci_dev *dev);
684#ifdef CONFIG_PCI_QUIRKS
685int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
686int pci_dev_specific_enable_acs(struct pci_dev *dev);
687int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
688int pcie_failed_link_retrain(struct pci_dev *dev);
689#else
690static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
691 u16 acs_flags)
692{
693 return -ENOTTY;
694}
695static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
696{
697 return -ENOTTY;
698}
699static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
700{
701 return -ENOTTY;
702}
703static inline int pcie_failed_link_retrain(struct pci_dev *dev)
704{
705 return -ENOTTY;
706}
707#endif
708
709/* PCI error reporting and recovery */
710pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
711 pci_channel_state_t state,
712 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
713
714bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
715int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
716
717/* ASPM-related functionality we need even without CONFIG_PCIEASPM */
718void pci_save_ltr_state(struct pci_dev *dev);
719void pci_restore_ltr_state(struct pci_dev *dev);
720void pci_configure_aspm_l1ss(struct pci_dev *dev);
721void pci_save_aspm_l1ss_state(struct pci_dev *dev);
722void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
723
724#ifdef CONFIG_PCIEASPM
725void pcie_aspm_init_link_state(struct pci_dev *pdev);
726void pcie_aspm_exit_link_state(struct pci_dev *pdev);
727void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
728void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
729void pci_configure_ltr(struct pci_dev *pdev);
730void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
731#else
732static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
733static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
734static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
735static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
736static inline void pci_configure_ltr(struct pci_dev *pdev) { }
737static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
738#endif
739
740#ifdef CONFIG_PCIE_ECRC
741void pcie_set_ecrc_checking(struct pci_dev *dev);
742void pcie_ecrc_get_policy(char *str);
743#else
744static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
745static inline void pcie_ecrc_get_policy(char *str) { }
746#endif
747
748#ifdef CONFIG_PCIEPORTBUS
749void pcie_reset_lbms_count(struct pci_dev *port);
750int pcie_lbms_count(struct pci_dev *port, unsigned long *val);
751#else
752static inline void pcie_reset_lbms_count(struct pci_dev *port) {}
753static inline int pcie_lbms_count(struct pci_dev *port, unsigned long *val)
754{
755 return -EOPNOTSUPP;
756}
757#endif
758
759struct pci_dev_reset_methods {
760 u16 vendor;
761 u16 device;
762 int (*reset)(struct pci_dev *dev, bool probe);
763};
764
765struct pci_reset_fn_method {
766 int (*reset_fn)(struct pci_dev *pdev, bool probe);
767 char *name;
768};
769
770#ifdef CONFIG_PCI_QUIRKS
771int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
772#else
773static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
774{
775 return -ENOTTY;
776}
777#endif
778
779#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
780int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
781 struct resource *res);
782#else
783static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
784 u16 segment, struct resource *res)
785{
786 return -ENODEV;
787}
788#endif
789
790int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
791int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
792static inline u64 pci_rebar_size_to_bytes(int size)
793{
794 return 1ULL << (size + 20);
795}
796
797struct device_node;
798
799#ifdef CONFIG_OF
800int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
801int of_get_pci_domain_nr(struct device_node *node);
802int of_pci_get_max_link_speed(struct device_node *node);
803u32 of_pci_get_slot_power_limit(struct device_node *node,
804 u8 *slot_power_limit_value,
805 u8 *slot_power_limit_scale);
806bool of_pci_preserve_config(struct device_node *node);
807int pci_set_of_node(struct pci_dev *dev);
808void pci_release_of_node(struct pci_dev *dev);
809void pci_set_bus_of_node(struct pci_bus *bus);
810void pci_release_bus_of_node(struct pci_bus *bus);
811
812int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
813bool of_pci_supply_present(struct device_node *np);
814
815#else
816static inline int
817of_pci_parse_bus_range(struct device_node *node, struct resource *res)
818{
819 return -EINVAL;
820}
821
822static inline int
823of_get_pci_domain_nr(struct device_node *node)
824{
825 return -1;
826}
827
828static inline int
829of_pci_get_max_link_speed(struct device_node *node)
830{
831 return -EINVAL;
832}
833
834static inline u32
835of_pci_get_slot_power_limit(struct device_node *node,
836 u8 *slot_power_limit_value,
837 u8 *slot_power_limit_scale)
838{
839 if (slot_power_limit_value)
840 *slot_power_limit_value = 0;
841 if (slot_power_limit_scale)
842 *slot_power_limit_scale = 0;
843 return 0;
844}
845
846static inline bool of_pci_preserve_config(struct device_node *node)
847{
848 return false;
849}
850
851static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
852static inline void pci_release_of_node(struct pci_dev *dev) { }
853static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
854static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
855
856static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
857{
858 return 0;
859}
860
861static inline bool of_pci_supply_present(struct device_node *np)
862{
863 return false;
864}
865#endif /* CONFIG_OF */
866
867struct of_changeset;
868
869#ifdef CONFIG_PCI_DYNAMIC_OF_NODES
870void of_pci_make_dev_node(struct pci_dev *pdev);
871void of_pci_remove_node(struct pci_dev *pdev);
872int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
873 struct device_node *np);
874#else
875static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
876static inline void of_pci_remove_node(struct pci_dev *pdev) { }
877#endif
878
879#ifdef CONFIG_PCIEAER
880void pci_no_aer(void);
881void pci_aer_init(struct pci_dev *dev);
882void pci_aer_exit(struct pci_dev *dev);
883extern const struct attribute_group aer_stats_attr_group;
884void pci_aer_clear_fatal_status(struct pci_dev *dev);
885int pci_aer_clear_status(struct pci_dev *dev);
886int pci_aer_raw_clear_status(struct pci_dev *dev);
887void pci_save_aer_state(struct pci_dev *dev);
888void pci_restore_aer_state(struct pci_dev *dev);
889#else
890static inline void pci_no_aer(void) { }
891static inline void pci_aer_init(struct pci_dev *d) { }
892static inline void pci_aer_exit(struct pci_dev *d) { }
893static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
894static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
895static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
896static inline void pci_save_aer_state(struct pci_dev *dev) { }
897static inline void pci_restore_aer_state(struct pci_dev *dev) { }
898#endif
899
900#ifdef CONFIG_ACPI
901bool pci_acpi_preserve_config(struct pci_host_bridge *bridge);
902int pci_acpi_program_hp_params(struct pci_dev *dev);
903extern const struct attribute_group pci_dev_acpi_attr_group;
904void pci_set_acpi_fwnode(struct pci_dev *dev);
905int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
906bool acpi_pci_power_manageable(struct pci_dev *dev);
907bool acpi_pci_bridge_d3(struct pci_dev *dev);
908int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
909pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
910void acpi_pci_refresh_power_state(struct pci_dev *dev);
911int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
912bool acpi_pci_need_resume(struct pci_dev *dev);
913pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
914#else
915static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge)
916{
917 return false;
918}
919static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
920{
921 return -ENOTTY;
922}
923static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
924static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
925{
926 return -ENODEV;
927}
928static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
929{
930 return false;
931}
932static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
933{
934 return false;
935}
936static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
937{
938 return -ENODEV;
939}
940static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
941{
942 return PCI_UNKNOWN;
943}
944static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
945static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
946{
947 return -ENODEV;
948}
949static inline bool acpi_pci_need_resume(struct pci_dev *dev)
950{
951 return false;
952}
953static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
954{
955 return PCI_POWER_ERROR;
956}
957#endif
958
959#ifdef CONFIG_PCIEASPM
960extern const struct attribute_group aspm_ctrl_attr_group;
961#endif
962
963extern const struct attribute_group pci_dev_reset_method_attr_group;
964
965#ifdef CONFIG_X86_INTEL_MID
966bool pci_use_mid_pm(void);
967int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
968pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
969#else
970static inline bool pci_use_mid_pm(void)
971{
972 return false;
973}
974static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
975{
976 return -ENODEV;
977}
978static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
979{
980 return PCI_UNKNOWN;
981}
982#endif
983
984int pcim_intx(struct pci_dev *dev, int enable);
985int pcim_request_region_exclusive(struct pci_dev *pdev, int bar,
986 const char *name);
987void pcim_release_region(struct pci_dev *pdev, int bar);
988
989/*
990 * Config Address for PCI Configuration Mechanism #1
991 *
992 * See PCI Local Bus Specification, Revision 3.0,
993 * Section 3.2.2.3.2, Figure 3-2, p. 50.
994 */
995
996#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
997#define PCI_CONF1_DEV_SHIFT 11 /* Device number */
998#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
999
1000#define PCI_CONF1_BUS_MASK 0xff
1001#define PCI_CONF1_DEV_MASK 0x1f
1002#define PCI_CONF1_FUNC_MASK 0x7
1003#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
1004
1005#define PCI_CONF1_ENABLE BIT(31)
1006#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
1007#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
1008#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
1009#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
1010
1011#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
1012 (PCI_CONF1_ENABLE | \
1013 PCI_CONF1_BUS(bus) | \
1014 PCI_CONF1_DEV(dev) | \
1015 PCI_CONF1_FUNC(func) | \
1016 PCI_CONF1_REG(reg))
1017
1018/*
1019 * Extension of PCI Config Address for accessing extended PCIe registers
1020 *
1021 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
1022 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
1023 * are used for specifying additional 4 high bits of PCI Express register.
1024 */
1025
1026#define PCI_CONF1_EXT_REG_SHIFT 16
1027#define PCI_CONF1_EXT_REG_MASK 0xf00
1028#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
1029
1030#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
1031 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
1032 PCI_CONF1_EXT_REG(reg))
1033
1034#endif /* DRIVERS_PCI_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#define PCI_FIND_CAP_TTL 48
6
7#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
8
9extern const unsigned char pcie_link_speed[];
10
11bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
12
13/* Functions internal to the PCI core code */
14
15int pci_create_sysfs_dev_files(struct pci_dev *pdev);
16void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
17#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
18static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
19{ return; }
20static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
21{ return; }
22#else
23void pci_create_firmware_label_files(struct pci_dev *pdev);
24void pci_remove_firmware_label_files(struct pci_dev *pdev);
25#endif
26void pci_cleanup_rom(struct pci_dev *dev);
27
28enum pci_mmap_api {
29 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
30 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
31};
32int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
33 enum pci_mmap_api mmap_api);
34
35int pci_probe_reset_function(struct pci_dev *dev);
36
37/**
38 * struct pci_platform_pm_ops - Firmware PM callbacks
39 *
40 * @is_manageable: returns 'true' if given device is power manageable by the
41 * platform firmware
42 *
43 * @set_state: invokes the platform firmware to set the device's power state
44 *
45 * @get_state: queries the platform firmware for a device's current power state
46 *
47 * @choose_state: returns PCI power state of given device preferred by the
48 * platform; to be used during system-wide transitions from a
49 * sleeping state to the working state and vice versa
50 *
51 * @set_wakeup: enables/disables wakeup capability for the device
52 *
53 * @need_resume: returns 'true' if the given device (which is currently
54 * suspended) needs to be resumed to be configured for system
55 * wakeup.
56 *
57 * If given platform is generally capable of power managing PCI devices, all of
58 * these callbacks are mandatory.
59 */
60struct pci_platform_pm_ops {
61 bool (*is_manageable)(struct pci_dev *dev);
62 int (*set_state)(struct pci_dev *dev, pci_power_t state);
63 pci_power_t (*get_state)(struct pci_dev *dev);
64 pci_power_t (*choose_state)(struct pci_dev *dev);
65 int (*set_wakeup)(struct pci_dev *dev, bool enable);
66 bool (*need_resume)(struct pci_dev *dev);
67};
68
69int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
70void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
71void pci_power_up(struct pci_dev *dev);
72void pci_disable_enabled_device(struct pci_dev *dev);
73int pci_finish_runtime_suspend(struct pci_dev *dev);
74void pcie_clear_root_pme_status(struct pci_dev *dev);
75int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
76void pci_pme_restore(struct pci_dev *dev);
77bool pci_dev_keep_suspended(struct pci_dev *dev);
78void pci_dev_complete_resume(struct pci_dev *pci_dev);
79void pci_config_pm_runtime_get(struct pci_dev *dev);
80void pci_config_pm_runtime_put(struct pci_dev *dev);
81void pci_pm_init(struct pci_dev *dev);
82void pci_ea_init(struct pci_dev *dev);
83void pci_allocate_cap_save_buffers(struct pci_dev *dev);
84void pci_free_cap_save_buffers(struct pci_dev *dev);
85bool pci_bridge_d3_possible(struct pci_dev *dev);
86void pci_bridge_d3_update(struct pci_dev *dev);
87
88static inline void pci_wakeup_event(struct pci_dev *dev)
89{
90 /* Wait 100 ms before the system can be put into a sleep state. */
91 pm_wakeup_event(&dev->dev, 100);
92}
93
94static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
95{
96 return !!(pci_dev->subordinate);
97}
98
99static inline bool pci_power_manageable(struct pci_dev *pci_dev)
100{
101 /*
102 * Currently we allow normal PCI devices and PCI bridges transition
103 * into D3 if their bridge_d3 is set.
104 */
105 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
106}
107
108int pci_vpd_init(struct pci_dev *dev);
109void pci_vpd_release(struct pci_dev *dev);
110void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
111void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
112
113/* PCI /proc functions */
114#ifdef CONFIG_PROC_FS
115int pci_proc_attach_device(struct pci_dev *dev);
116int pci_proc_detach_device(struct pci_dev *dev);
117int pci_proc_detach_bus(struct pci_bus *bus);
118#else
119static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
120static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
121static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
122#endif
123
124/* Functions for PCI Hotplug drivers to use */
125int pci_hp_add_bridge(struct pci_dev *dev);
126
127#ifdef HAVE_PCI_LEGACY
128void pci_create_legacy_files(struct pci_bus *bus);
129void pci_remove_legacy_files(struct pci_bus *bus);
130#else
131static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
132static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
133#endif
134
135/* Lock for read/write access to pci device and bus lists */
136extern struct rw_semaphore pci_bus_sem;
137
138extern raw_spinlock_t pci_lock;
139
140extern unsigned int pci_pm_d3_delay;
141
142#ifdef CONFIG_PCI_MSI
143void pci_no_msi(void);
144#else
145static inline void pci_no_msi(void) { }
146#endif
147
148static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
149{
150 u16 control;
151
152 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
153 control &= ~PCI_MSI_FLAGS_ENABLE;
154 if (enable)
155 control |= PCI_MSI_FLAGS_ENABLE;
156 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
157}
158
159static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
160{
161 u16 ctrl;
162
163 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
164 ctrl &= ~clear;
165 ctrl |= set;
166 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
167}
168
169void pci_realloc_get_opt(char *);
170
171static inline int pci_no_d1d2(struct pci_dev *dev)
172{
173 unsigned int parent_dstates = 0;
174
175 if (dev->bus->self)
176 parent_dstates = dev->bus->self->no_d1d2;
177 return (dev->no_d1d2 || parent_dstates);
178
179}
180extern const struct attribute_group *pci_dev_groups[];
181extern const struct attribute_group *pcibus_groups[];
182extern const struct device_type pci_dev_type;
183extern const struct attribute_group *pci_bus_groups[];
184
185
186/**
187 * pci_match_one_device - Tell if a PCI device structure has a matching
188 * PCI device id structure
189 * @id: single PCI device id structure to match
190 * @dev: the PCI device structure to match against
191 *
192 * Returns the matching pci_device_id structure or %NULL if there is no match.
193 */
194static inline const struct pci_device_id *
195pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
196{
197 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
198 (id->device == PCI_ANY_ID || id->device == dev->device) &&
199 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
200 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
201 !((id->class ^ dev->class) & id->class_mask))
202 return id;
203 return NULL;
204}
205
206/* PCI slot sysfs helper code */
207#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
208
209extern struct kset *pci_slots_kset;
210
211struct pci_slot_attribute {
212 struct attribute attr;
213 ssize_t (*show)(struct pci_slot *, char *);
214 ssize_t (*store)(struct pci_slot *, const char *, size_t);
215};
216#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
217
218enum pci_bar_type {
219 pci_bar_unknown, /* Standard PCI BAR probe */
220 pci_bar_io, /* An I/O port BAR */
221 pci_bar_mem32, /* A 32-bit memory BAR */
222 pci_bar_mem64, /* A 64-bit memory BAR */
223};
224
225int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
226bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
227 int crs_timeout);
228int pci_setup_device(struct pci_dev *dev);
229int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
230 struct resource *res, unsigned int reg);
231void pci_configure_ari(struct pci_dev *dev);
232void __pci_bus_size_bridges(struct pci_bus *bus,
233 struct list_head *realloc_head);
234void __pci_bus_assign_resources(const struct pci_bus *bus,
235 struct list_head *realloc_head,
236 struct list_head *fail_head);
237bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
238
239void pci_reassigndev_resource_alignment(struct pci_dev *dev);
240void pci_disable_bridge_window(struct pci_dev *dev);
241
242/* PCIe link information */
243#define PCIE_SPEED2STR(speed) \
244 ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
245 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
246 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
247 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
248 "Unknown speed")
249
250/* PCIe speed to Mb/s reduced by encoding overhead */
251#define PCIE_SPEED2MBS_ENC(speed) \
252 ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
253 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
254 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
255 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
256 0)
257
258enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
259enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
260u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
261 enum pcie_link_width *width);
262
263/* Single Root I/O Virtualization */
264struct pci_sriov {
265 int pos; /* Capability position */
266 int nres; /* Number of resources */
267 u32 cap; /* SR-IOV Capabilities */
268 u16 ctrl; /* SR-IOV Control */
269 u16 total_VFs; /* Total VFs associated with the PF */
270 u16 initial_VFs; /* Initial VFs associated with the PF */
271 u16 num_VFs; /* Number of VFs available */
272 u16 offset; /* First VF Routing ID offset */
273 u16 stride; /* Following VF stride */
274 u16 vf_device; /* VF device ID */
275 u32 pgsz; /* Page size for BAR alignment */
276 u8 link; /* Function Dependency Link */
277 u8 max_VF_buses; /* Max buses consumed by VFs */
278 u16 driver_max_VFs; /* Max num VFs driver supports */
279 struct pci_dev *dev; /* Lowest numbered PF */
280 struct pci_dev *self; /* This PF */
281 u32 class; /* VF device */
282 u8 hdr_type; /* VF header type */
283 u16 subsystem_vendor; /* VF subsystem vendor */
284 u16 subsystem_device; /* VF subsystem device */
285 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
286 bool drivers_autoprobe; /* Auto probing of VFs by driver */
287};
288
289/* pci_dev priv_flags */
290#define PCI_DEV_DISCONNECTED 0
291
292static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
293{
294 set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
295 return 0;
296}
297
298static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
299{
300 return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
301}
302
303#ifdef CONFIG_PCI_ATS
304void pci_restore_ats_state(struct pci_dev *dev);
305#else
306static inline void pci_restore_ats_state(struct pci_dev *dev)
307{
308}
309#endif /* CONFIG_PCI_ATS */
310
311#ifdef CONFIG_PCI_IOV
312int pci_iov_init(struct pci_dev *dev);
313void pci_iov_release(struct pci_dev *dev);
314void pci_iov_update_resource(struct pci_dev *dev, int resno);
315resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
316void pci_restore_iov_state(struct pci_dev *dev);
317int pci_iov_bus_range(struct pci_bus *bus);
318
319#else
320static inline int pci_iov_init(struct pci_dev *dev)
321{
322 return -ENODEV;
323}
324static inline void pci_iov_release(struct pci_dev *dev)
325
326{
327}
328static inline void pci_restore_iov_state(struct pci_dev *dev)
329{
330}
331static inline int pci_iov_bus_range(struct pci_bus *bus)
332{
333 return 0;
334}
335
336#endif /* CONFIG_PCI_IOV */
337
338unsigned long pci_cardbus_resource_alignment(struct resource *);
339
340static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
341 struct resource *res)
342{
343#ifdef CONFIG_PCI_IOV
344 int resno = res - dev->resource;
345
346 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
347 return pci_sriov_resource_alignment(dev, resno);
348#endif
349 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
350 return pci_cardbus_resource_alignment(res);
351 return resource_alignment(res);
352}
353
354void pci_enable_acs(struct pci_dev *dev);
355
356#ifdef CONFIG_PCIEASPM
357void pcie_aspm_init_link_state(struct pci_dev *pdev);
358void pcie_aspm_exit_link_state(struct pci_dev *pdev);
359void pcie_aspm_pm_state_change(struct pci_dev *pdev);
360void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
361#else
362static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
363static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
364static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
365static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
366#endif
367
368#ifdef CONFIG_PCIEASPM_DEBUG
369void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
370void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
371#else
372static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
373static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
374#endif
375
376#ifdef CONFIG_PCIE_PTM
377void pci_ptm_init(struct pci_dev *dev);
378#else
379static inline void pci_ptm_init(struct pci_dev *dev) { }
380#endif
381
382struct pci_dev_reset_methods {
383 u16 vendor;
384 u16 device;
385 int (*reset)(struct pci_dev *dev, int probe);
386};
387
388#ifdef CONFIG_PCI_QUIRKS
389int pci_dev_specific_reset(struct pci_dev *dev, int probe);
390#else
391static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
392{
393 return -ENOTTY;
394}
395#endif
396
397#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
398int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
399 struct resource *res);
400#endif
401
402u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
403int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
404int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
405static inline u64 pci_rebar_size_to_bytes(int size)
406{
407 return 1ULL << (size + 20);
408}
409
410#endif /* DRIVERS_PCI_H */