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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (C) 2018 Microchip Technology
3
4#include <linux/kernel.h>
5#include <linux/module.h>
6#include <linux/delay.h>
7#include <linux/mii.h>
8#include <linux/phy.h>
9#include <linux/sort.h>
10#include <linux/ethtool.h>
11#include <linux/ethtool_netlink.h>
12#include <linux/bitfield.h>
13
14#define PHY_ID_LAN87XX 0x0007c150
15#define PHY_ID_LAN937X 0x0007c180
16#define PHY_ID_LAN887X 0x0007c1f0
17
18/* External Register Control Register */
19#define LAN87XX_EXT_REG_CTL (0x14)
20#define LAN87XX_EXT_REG_CTL_RD_CTL (0x1000)
21#define LAN87XX_EXT_REG_CTL_WR_CTL (0x0800)
22#define LAN87XX_REG_BANK_SEL_MASK GENMASK(10, 8)
23#define LAN87XX_REG_ADDR_MASK GENMASK(7, 0)
24
25/* External Register Read Data Register */
26#define LAN87XX_EXT_REG_RD_DATA (0x15)
27
28/* External Register Write Data Register */
29#define LAN87XX_EXT_REG_WR_DATA (0x16)
30
31/* Interrupt Source Register */
32#define LAN87XX_INTERRUPT_SOURCE (0x18)
33#define LAN87XX_INTERRUPT_SOURCE_2 (0x08)
34
35/* Interrupt Mask Register */
36#define LAN87XX_INTERRUPT_MASK (0x19)
37#define LAN87XX_MASK_LINK_UP (0x0004)
38#define LAN87XX_MASK_LINK_DOWN (0x0002)
39
40#define LAN87XX_INTERRUPT_MASK_2 (0x09)
41#define LAN87XX_MASK_COMM_RDY BIT(10)
42
43/* MISC Control 1 Register */
44#define LAN87XX_CTRL_1 (0x11)
45#define LAN87XX_MASK_RGMII_TXC_DLY_EN (0x4000)
46#define LAN87XX_MASK_RGMII_RXC_DLY_EN (0x2000)
47
48/* phyaccess nested types */
49#define PHYACC_ATTR_MODE_READ 0
50#define PHYACC_ATTR_MODE_WRITE 1
51#define PHYACC_ATTR_MODE_MODIFY 2
52#define PHYACC_ATTR_MODE_POLL 3
53
54#define PHYACC_ATTR_BANK_SMI 0
55#define PHYACC_ATTR_BANK_MISC 1
56#define PHYACC_ATTR_BANK_PCS 2
57#define PHYACC_ATTR_BANK_AFE 3
58#define PHYACC_ATTR_BANK_DSP 4
59#define PHYACC_ATTR_BANK_MAX 7
60
61/* measurement defines */
62#define LAN87XX_CABLE_TEST_OK 0
63#define LAN87XX_CABLE_TEST_OPEN 1
64#define LAN87XX_CABLE_TEST_SAME_SHORT 2
65
66/* T1 Registers */
67#define T1_AFE_PORT_CFG1_REG 0x0B
68#define T1_POWER_DOWN_CONTROL_REG 0x1A
69#define T1_SLV_FD_MULT_CFG_REG 0x18
70#define T1_CDR_CFG_PRE_LOCK_REG 0x05
71#define T1_CDR_CFG_POST_LOCK_REG 0x06
72#define T1_LCK_STG2_MUFACT_CFG_REG 0x1A
73#define T1_LCK_STG3_MUFACT_CFG_REG 0x1B
74#define T1_POST_LCK_MUFACT_CFG_REG 0x1C
75#define T1_TX_RX_FIFO_CFG_REG 0x02
76#define T1_TX_LPF_FIR_CFG_REG 0x55
77#define T1_COEF_CLK_PWR_DN_CFG 0x04
78#define T1_COEF_RW_CTL_CFG 0x0D
79#define T1_SQI_CONFIG_REG 0x2E
80#define T1_SQI_CONFIG2_REG 0x4A
81#define T1_DCQ_SQI_REG 0xC3
82#define T1_DCQ_SQI_MSK GENMASK(3, 1)
83#define T1_MDIO_CONTROL2_REG 0x10
84#define T1_INTERRUPT_SOURCE_REG 0x18
85#define T1_INTERRUPT2_SOURCE_REG 0x08
86#define T1_EQ_FD_STG1_FRZ_CFG 0x69
87#define T1_EQ_FD_STG2_FRZ_CFG 0x6A
88#define T1_EQ_FD_STG3_FRZ_CFG 0x6B
89#define T1_EQ_FD_STG4_FRZ_CFG 0x6C
90#define T1_EQ_WT_FD_LCK_FRZ_CFG 0x6D
91#define T1_PST_EQ_LCK_STG1_FRZ_CFG 0x6E
92
93#define T1_MODE_STAT_REG 0x11
94#define T1_LINK_UP_MSK BIT(0)
95
96/* SQI defines */
97#define LAN87XX_MAX_SQI 0x07
98
99/* Chiptop registers */
100#define LAN887X_PMA_EXT_ABILITY_2 0x12
101#define LAN887X_PMA_EXT_ABILITY_2_1000T1 BIT(1)
102#define LAN887X_PMA_EXT_ABILITY_2_100T1 BIT(0)
103
104/* DSP 100M registers */
105#define LAN887x_CDR_CONFIG1_100 0x0405
106#define LAN887x_LOCK1_EQLSR_CONFIG_100 0x0411
107#define LAN887x_SLV_HD_MUFAC_CONFIG_100 0x0417
108#define LAN887x_PLOCK_MUFAC_CONFIG_100 0x041c
109#define LAN887x_PROT_DISABLE_100 0x0425
110#define LAN887x_KF_LOOP_SAT_CONFIG_100 0x0454
111
112/* DSP 1000M registers */
113#define LAN887X_LOCK1_EQLSR_CONFIG 0x0811
114#define LAN887X_LOCK3_EQLSR_CONFIG 0x0813
115#define LAN887X_PROT_DISABLE 0x0825
116#define LAN887X_FFE_GAIN6 0x0843
117#define LAN887X_FFE_GAIN7 0x0844
118#define LAN887X_FFE_GAIN8 0x0845
119#define LAN887X_FFE_GAIN9 0x0846
120#define LAN887X_ECHO_DELAY_CONFIG 0x08ec
121#define LAN887X_FFE_MAX_CONFIG 0x08ee
122
123/* PCS 1000M registers */
124#define LAN887X_SCR_CONFIG_3 0x8043
125#define LAN887X_INFO_FLD_CONFIG_5 0x8048
126
127/* T1 afe registers */
128#define LAN887X_ZQCAL_CONTROL_1 0x8080
129#define LAN887X_AFE_PORT_TESTBUS_CTRL2 0x8089
130#define LAN887X_AFE_PORT_TESTBUS_CTRL4 0x808b
131#define LAN887X_AFE_PORT_TESTBUS_CTRL6 0x808d
132#define LAN887X_TX_AMPLT_1000T1_REG 0x80b0
133#define LAN887X_INIT_COEFF_DFE1_100 0x0422
134
135/* PMA registers */
136#define LAN887X_DSP_PMA_CONTROL 0x810e
137#define LAN887X_DSP_PMA_CONTROL_LNK_SYNC BIT(4)
138
139/* PCS 100M registers */
140#define LAN887X_IDLE_ERR_TIMER_WIN 0x8204
141#define LAN887X_IDLE_ERR_CNT_THRESH 0x8213
142
143/* Misc registers */
144#define LAN887X_REG_REG26 0x001a
145#define LAN887X_REG_REG26_HW_INIT_SEQ_EN BIT(8)
146
147/* Mis registers */
148#define LAN887X_MIS_CFG_REG0 0xa00
149#define LAN887X_MIS_CFG_REG0_RCLKOUT_DIS BIT(5)
150#define LAN887X_MIS_CFG_REG0_MAC_MODE_SEL GENMASK(1, 0)
151
152#define LAN887X_MAC_MODE_RGMII 0x01
153#define LAN887X_MAC_MODE_SGMII 0x03
154
155#define LAN887X_MIS_DLL_CFG_REG0 0xa01
156#define LAN887X_MIS_DLL_CFG_REG1 0xa02
157
158#define LAN887X_MIS_DLL_DELAY_EN BIT(15)
159#define LAN887X_MIS_DLL_EN BIT(0)
160#define LAN887X_MIS_DLL_CONF (LAN887X_MIS_DLL_DELAY_EN |\
161 LAN887X_MIS_DLL_EN)
162
163#define LAN887X_MIS_CFG_REG2 0xa03
164#define LAN887X_MIS_CFG_REG2_FE_LPBK_EN BIT(2)
165
166#define LAN887X_MIS_PKT_STAT_REG0 0xa06
167#define LAN887X_MIS_PKT_STAT_REG1 0xa07
168#define LAN887X_MIS_PKT_STAT_REG3 0xa09
169#define LAN887X_MIS_PKT_STAT_REG4 0xa0a
170#define LAN887X_MIS_PKT_STAT_REG5 0xa0b
171#define LAN887X_MIS_PKT_STAT_REG6 0xa0c
172
173/* Chiptop common registers */
174#define LAN887X_COMMON_LED3_LED2 0xc05
175#define LAN887X_COMMON_LED2_MODE_SEL_MASK GENMASK(4, 0)
176#define LAN887X_LED_LINK_ACT_ANY_SPEED 0x0
177
178/* MX chip top registers */
179#define LAN887X_CHIP_HARD_RST 0xf03e
180#define LAN887X_CHIP_HARD_RST_RESET BIT(0)
181
182#define LAN887X_CHIP_SOFT_RST 0xf03f
183#define LAN887X_CHIP_SOFT_RST_RESET BIT(0)
184
185#define LAN887X_SGMII_CTL 0xf01a
186#define LAN887X_SGMII_CTL_SGMII_MUX_EN BIT(0)
187
188#define LAN887X_SGMII_PCS_CFG 0xf034
189#define LAN887X_SGMII_PCS_CFG_PCS_ENA BIT(9)
190
191#define LAN887X_EFUSE_READ_DAT9 0xf209
192#define LAN887X_EFUSE_READ_DAT9_SGMII_DIS BIT(9)
193#define LAN887X_EFUSE_READ_DAT9_MAC_MODE GENMASK(1, 0)
194
195#define LAN887X_CALIB_CONFIG_100 0x437
196#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL BIT(5)
197#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE BIT(4)
198#define LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE BIT(3)
199#define LAN887X_CALIB_CONFIG_100_VAL \
200 (LAN887X_CALIB_CONFIG_100_CBL_DIAG_CLK_ALGN_MODE |\
201 LAN887X_CALIB_CONFIG_100_CBL_DIAG_STB_SYNC_MODE |\
202 LAN887X_CALIB_CONFIG_100_CBL_DIAG_USE_LOCAL_SMPL)
203
204#define LAN887X_MAX_PGA_GAIN_100 0x44f
205#define LAN887X_MIN_PGA_GAIN_100 0x450
206#define LAN887X_START_CBL_DIAG_100 0x45a
207#define LAN887X_CBL_DIAG_DONE BIT(1)
208#define LAN887X_CBL_DIAG_START BIT(0)
209#define LAN887X_CBL_DIAG_STOP 0x0
210
211#define LAN887X_CBL_DIAG_TDR_THRESH_100 0x45b
212#define LAN887X_CBL_DIAG_AGC_THRESH_100 0x45c
213#define LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100 0x45d
214#define LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100 0x45e
215#define LAN887X_CBL_DIAG_CYC_CONFIG_100 0x45f
216#define LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100 0x460
217#define LAN887X_CBL_DIAG_MIN_PGA_GAIN_100 0x462
218#define LAN887X_CBL_DIAG_AGC_GAIN_100 0x497
219#define LAN887X_CBL_DIAG_POS_PEAK_VALUE_100 0x499
220#define LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100 0x49a
221#define LAN887X_CBL_DIAG_POS_PEAK_TIME_100 0x49c
222#define LAN887X_CBL_DIAG_NEG_PEAK_TIME_100 0x49d
223
224#define MICROCHIP_CABLE_NOISE_MARGIN 20
225#define MICROCHIP_CABLE_TIME_MARGIN 89
226#define MICROCHIP_CABLE_MIN_TIME_DIFF 96
227#define MICROCHIP_CABLE_MAX_TIME_DIFF \
228 (MICROCHIP_CABLE_MIN_TIME_DIFF + MICROCHIP_CABLE_TIME_MARGIN)
229
230#define LAN887X_INT_STS 0xf000
231#define LAN887X_INT_MSK 0xf001
232#define LAN887X_INT_MSK_T1_PHY_INT_MSK BIT(2)
233#define LAN887X_INT_MSK_LINK_UP_MSK BIT(1)
234#define LAN887X_INT_MSK_LINK_DOWN_MSK BIT(0)
235
236#define LAN887X_MX_CHIP_TOP_LINK_MSK (LAN887X_INT_MSK_LINK_UP_MSK |\
237 LAN887X_INT_MSK_LINK_DOWN_MSK)
238
239#define LAN887X_MX_CHIP_TOP_ALL_MSK (LAN887X_INT_MSK_T1_PHY_INT_MSK |\
240 LAN887X_MX_CHIP_TOP_LINK_MSK)
241
242#define LAN887X_COEFF_PWR_DN_CONFIG_100 0x0404
243#define LAN887X_COEFF_PWR_DN_CONFIG_100_V 0x16d6
244#define LAN887X_SQI_CONFIG_100 0x042e
245#define LAN887X_SQI_CONFIG_100_V 0x9572
246#define LAN887X_SQI_MSE_100 0x483
247
248#define LAN887X_POKE_PEEK_100 0x040d
249#define LAN887X_POKE_PEEK_100_EN BIT(0)
250
251#define LAN887X_COEFF_MOD_CONFIG 0x080d
252#define LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN BIT(8)
253
254#define LAN887X_DCQ_SQI_STATUS 0x08b2
255
256/* SQI raw samples count */
257#define SQI_SAMPLES 200
258
259/* Samples percentage considered for SQI calculation */
260#define SQI_INLINERS_PERCENT 60
261
262/* Samples count considered for SQI calculation */
263#define SQI_INLIERS_NUM (SQI_SAMPLES * SQI_INLINERS_PERCENT / 100)
264
265/* Start offset of samples */
266#define SQI_INLIERS_START ((SQI_SAMPLES - SQI_INLIERS_NUM) / 2)
267
268/* End offset of samples */
269#define SQI_INLIERS_END (SQI_INLIERS_START + SQI_INLIERS_NUM)
270
271#define DRIVER_AUTHOR "Nisar Sayed <nisar.sayed@microchip.com>"
272#define DRIVER_DESC "Microchip LAN87XX/LAN937x/LAN887x T1 PHY driver"
273
274/* TEST_MODE_NORMAL: Non-hybrid results to calculate cable status(open/short/ok)
275 * TEST_MODE_HYBRID: Hybrid results to calculate distance to fault
276 */
277enum cable_diag_mode {
278 TEST_MODE_NORMAL,
279 TEST_MODE_HYBRID
280};
281
282/* CD_TEST_INIT: Cable test is initated
283 * CD_TEST_DONE: Cable test is done
284 */
285enum cable_diag_state {
286 CD_TEST_INIT,
287 CD_TEST_DONE
288};
289
290struct access_ereg_val {
291 u8 mode;
292 u8 bank;
293 u8 offset;
294 u16 val;
295 u16 mask;
296};
297
298struct lan887x_hw_stat {
299 const char *string;
300 u8 mmd;
301 u16 reg;
302 u8 bits;
303};
304
305static const struct lan887x_hw_stat lan887x_hw_stats[] = {
306 { "TX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG0, 14},
307 { "RX Good Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG1, 14},
308 { "RX ERR Count detected by PCS", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG3, 16},
309 { "TX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG4, 8},
310 { "RX CRC ERR Count", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG5, 8},
311 { "RX ERR Count for SGMII MII2GMII", MDIO_MMD_VEND1, LAN887X_MIS_PKT_STAT_REG6, 8},
312};
313
314struct lan887x_regwr_map {
315 u8 mmd;
316 u16 reg;
317 u16 val;
318};
319
320struct lan887x_priv {
321 u64 stats[ARRAY_SIZE(lan887x_hw_stats)];
322};
323
324static int lan937x_dsp_workaround(struct phy_device *phydev, u16 ereg, u8 bank)
325{
326 u8 prev_bank;
327 int rc = 0;
328 u16 val;
329
330 mutex_lock(&phydev->lock);
331 /* Read previous selected bank */
332 rc = phy_read(phydev, LAN87XX_EXT_REG_CTL);
333 if (rc < 0)
334 goto out_unlock;
335
336 /* store the prev_bank */
337 prev_bank = FIELD_GET(LAN87XX_REG_BANK_SEL_MASK, rc);
338
339 if (bank != prev_bank && bank == PHYACC_ATTR_BANK_DSP) {
340 val = ereg & ~LAN87XX_REG_ADDR_MASK;
341
342 val &= ~LAN87XX_EXT_REG_CTL_WR_CTL;
343 val |= LAN87XX_EXT_REG_CTL_RD_CTL;
344
345 /* access twice for DSP bank change,dummy access */
346 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, val);
347 }
348
349out_unlock:
350 mutex_unlock(&phydev->lock);
351
352 return rc;
353}
354
355static int access_ereg(struct phy_device *phydev, u8 mode, u8 bank,
356 u8 offset, u16 val)
357{
358 u16 ereg = 0;
359 int rc = 0;
360
361 if (mode > PHYACC_ATTR_MODE_WRITE || bank > PHYACC_ATTR_BANK_MAX)
362 return -EINVAL;
363
364 if (bank == PHYACC_ATTR_BANK_SMI) {
365 if (mode == PHYACC_ATTR_MODE_WRITE)
366 rc = phy_write(phydev, offset, val);
367 else
368 rc = phy_read(phydev, offset);
369 return rc;
370 }
371
372 if (mode == PHYACC_ATTR_MODE_WRITE) {
373 ereg = LAN87XX_EXT_REG_CTL_WR_CTL;
374 rc = phy_write(phydev, LAN87XX_EXT_REG_WR_DATA, val);
375 if (rc < 0)
376 return rc;
377 } else {
378 ereg = LAN87XX_EXT_REG_CTL_RD_CTL;
379 }
380
381 ereg |= (bank << 8) | offset;
382
383 /* DSP bank access workaround for lan937x */
384 if (phydev->phy_id == PHY_ID_LAN937X) {
385 rc = lan937x_dsp_workaround(phydev, ereg, bank);
386 if (rc < 0)
387 return rc;
388 }
389
390 rc = phy_write(phydev, LAN87XX_EXT_REG_CTL, ereg);
391 if (rc < 0)
392 return rc;
393
394 if (mode == PHYACC_ATTR_MODE_READ)
395 rc = phy_read(phydev, LAN87XX_EXT_REG_RD_DATA);
396
397 return rc;
398}
399
400static int access_ereg_modify_changed(struct phy_device *phydev,
401 u8 bank, u8 offset, u16 val, u16 mask)
402{
403 int new = 0, rc = 0;
404
405 if (bank > PHYACC_ATTR_BANK_MAX)
406 return -EINVAL;
407
408 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, bank, offset, val);
409 if (rc < 0)
410 return rc;
411
412 new = val | (rc & (mask ^ 0xFFFF));
413 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE, bank, offset, new);
414
415 return rc;
416}
417
418static int access_smi_poll_timeout(struct phy_device *phydev,
419 u8 offset, u16 mask, u16 clr)
420{
421 int val;
422
423 return phy_read_poll_timeout(phydev, offset, val, (val & mask) == clr,
424 150, 30000, true);
425}
426
427static int lan87xx_config_rgmii_delay(struct phy_device *phydev)
428{
429 int rc;
430
431 if (!phy_interface_is_rgmii(phydev))
432 return 0;
433
434 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
435 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, 0);
436 if (rc < 0)
437 return rc;
438
439 switch (phydev->interface) {
440 case PHY_INTERFACE_MODE_RGMII:
441 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
442 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
443 break;
444 case PHY_INTERFACE_MODE_RGMII_ID:
445 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
446 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
447 break;
448 case PHY_INTERFACE_MODE_RGMII_RXID:
449 rc &= ~LAN87XX_MASK_RGMII_TXC_DLY_EN;
450 rc |= LAN87XX_MASK_RGMII_RXC_DLY_EN;
451 break;
452 case PHY_INTERFACE_MODE_RGMII_TXID:
453 rc |= LAN87XX_MASK_RGMII_TXC_DLY_EN;
454 rc &= ~LAN87XX_MASK_RGMII_RXC_DLY_EN;
455 break;
456 default:
457 return 0;
458 }
459
460 return access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
461 PHYACC_ATTR_BANK_MISC, LAN87XX_CTRL_1, rc);
462}
463
464static int lan87xx_phy_init_cmd(struct phy_device *phydev,
465 const struct access_ereg_val *cmd_seq, int cnt)
466{
467 int ret, i;
468
469 for (i = 0; i < cnt; i++) {
470 if (cmd_seq[i].mode == PHYACC_ATTR_MODE_POLL &&
471 cmd_seq[i].bank == PHYACC_ATTR_BANK_SMI) {
472 ret = access_smi_poll_timeout(phydev,
473 cmd_seq[i].offset,
474 cmd_seq[i].val,
475 cmd_seq[i].mask);
476 } else {
477 ret = access_ereg(phydev, cmd_seq[i].mode,
478 cmd_seq[i].bank, cmd_seq[i].offset,
479 cmd_seq[i].val);
480 }
481 if (ret < 0)
482 return ret;
483 }
484
485 return ret;
486}
487
488static int lan87xx_phy_init(struct phy_device *phydev)
489{
490 static const struct access_ereg_val hw_init[] = {
491 /* TXPD/TXAMP6 Configs */
492 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
493 T1_AFE_PORT_CFG1_REG, 0x002D, 0 },
494 /* HW_Init Hi and Force_ED */
495 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
496 T1_POWER_DOWN_CONTROL_REG, 0x0308, 0 },
497 };
498
499 static const struct access_ereg_val slave_init[] = {
500 /* Equalizer Full Duplex Freeze - T1 Slave */
501 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
502 T1_EQ_FD_STG1_FRZ_CFG, 0x0002, 0 },
503 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
504 T1_EQ_FD_STG2_FRZ_CFG, 0x0002, 0 },
505 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
506 T1_EQ_FD_STG3_FRZ_CFG, 0x0002, 0 },
507 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
508 T1_EQ_FD_STG4_FRZ_CFG, 0x0002, 0 },
509 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
510 T1_EQ_WT_FD_LCK_FRZ_CFG, 0x0002, 0 },
511 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
512 T1_PST_EQ_LCK_STG1_FRZ_CFG, 0x0002, 0 },
513 };
514
515 static const struct access_ereg_val phy_init[] = {
516 /* Slave Full Duplex Multi Configs */
517 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
518 T1_SLV_FD_MULT_CFG_REG, 0x0D53, 0 },
519 /* CDR Pre and Post Lock Configs */
520 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
521 T1_CDR_CFG_PRE_LOCK_REG, 0x0AB2, 0 },
522 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
523 T1_CDR_CFG_POST_LOCK_REG, 0x0AB3, 0 },
524 /* Lock Stage 2-3 Multi Factor Config */
525 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
526 T1_LCK_STG2_MUFACT_CFG_REG, 0x0AEA, 0 },
527 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
528 T1_LCK_STG3_MUFACT_CFG_REG, 0x0AEB, 0 },
529 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
530 T1_POST_LCK_MUFACT_CFG_REG, 0x0AEB, 0 },
531 /* Pointer delay */
532 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
533 T1_TX_RX_FIFO_CFG_REG, 0x1C00, 0 },
534 /* Tx iir edits */
535 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
536 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
537 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
538 T1_TX_LPF_FIR_CFG_REG, 0x1861, 0 },
539 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
540 T1_TX_LPF_FIR_CFG_REG, 0x1061, 0 },
541 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
542 T1_TX_LPF_FIR_CFG_REG, 0x1922, 0 },
543 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
544 T1_TX_LPF_FIR_CFG_REG, 0x1122, 0 },
545 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
546 T1_TX_LPF_FIR_CFG_REG, 0x1983, 0 },
547 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
548 T1_TX_LPF_FIR_CFG_REG, 0x1183, 0 },
549 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
550 T1_TX_LPF_FIR_CFG_REG, 0x1944, 0 },
551 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
552 T1_TX_LPF_FIR_CFG_REG, 0x1144, 0 },
553 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
554 T1_TX_LPF_FIR_CFG_REG, 0x18c5, 0 },
555 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
556 T1_TX_LPF_FIR_CFG_REG, 0x10c5, 0 },
557 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
558 T1_TX_LPF_FIR_CFG_REG, 0x1846, 0 },
559 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
560 T1_TX_LPF_FIR_CFG_REG, 0x1046, 0 },
561 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
562 T1_TX_LPF_FIR_CFG_REG, 0x1807, 0 },
563 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
564 T1_TX_LPF_FIR_CFG_REG, 0x1007, 0 },
565 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
566 T1_TX_LPF_FIR_CFG_REG, 0x1808, 0 },
567 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
568 T1_TX_LPF_FIR_CFG_REG, 0x1008, 0 },
569 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
570 T1_TX_LPF_FIR_CFG_REG, 0x1809, 0 },
571 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
572 T1_TX_LPF_FIR_CFG_REG, 0x1009, 0 },
573 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
574 T1_TX_LPF_FIR_CFG_REG, 0x180A, 0 },
575 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
576 T1_TX_LPF_FIR_CFG_REG, 0x100A, 0 },
577 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
578 T1_TX_LPF_FIR_CFG_REG, 0x180B, 0 },
579 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
580 T1_TX_LPF_FIR_CFG_REG, 0x100B, 0 },
581 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
582 T1_TX_LPF_FIR_CFG_REG, 0x180C, 0 },
583 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
584 T1_TX_LPF_FIR_CFG_REG, 0x100C, 0 },
585 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
586 T1_TX_LPF_FIR_CFG_REG, 0x180D, 0 },
587 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
588 T1_TX_LPF_FIR_CFG_REG, 0x100D, 0 },
589 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
590 T1_TX_LPF_FIR_CFG_REG, 0x180E, 0 },
591 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
592 T1_TX_LPF_FIR_CFG_REG, 0x100E, 0 },
593 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
594 T1_TX_LPF_FIR_CFG_REG, 0x180F, 0 },
595 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
596 T1_TX_LPF_FIR_CFG_REG, 0x100F, 0 },
597 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
598 T1_TX_LPF_FIR_CFG_REG, 0x1810, 0 },
599 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
600 T1_TX_LPF_FIR_CFG_REG, 0x1010, 0 },
601 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
602 T1_TX_LPF_FIR_CFG_REG, 0x1811, 0 },
603 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
604 T1_TX_LPF_FIR_CFG_REG, 0x1011, 0 },
605 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
606 T1_TX_LPF_FIR_CFG_REG, 0x1000, 0 },
607 /* Setup SQI measurement */
608 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
609 T1_COEF_CLK_PWR_DN_CFG, 0x16d6, 0 },
610 /* SQI enable */
611 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
612 T1_SQI_CONFIG_REG, 0x9572, 0 },
613 /* SQI select mode 5 */
614 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
615 T1_SQI_CONFIG2_REG, 0x0001, 0 },
616 /* Throws the first SQI reading */
617 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP,
618 T1_COEF_RW_CTL_CFG, 0x0301, 0 },
619 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
620 T1_DCQ_SQI_REG, 0, 0 },
621 /* Flag LPS and WUR as idle errors */
622 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
623 T1_MDIO_CONTROL2_REG, 0x0014, 0 },
624 /* HW_Init toggle, undo force ED, TXPD off */
625 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
626 T1_POWER_DOWN_CONTROL_REG, 0x0200, 0 },
627 /* Reset PCS to trigger hardware initialization */
628 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
629 T1_MDIO_CONTROL2_REG, 0x0094, 0 },
630 /* Poll till Hardware is initialized */
631 { PHYACC_ATTR_MODE_POLL, PHYACC_ATTR_BANK_SMI,
632 T1_MDIO_CONTROL2_REG, 0x0080, 0 },
633 /* Tx AMP - 0x06 */
634 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_AFE,
635 T1_AFE_PORT_CFG1_REG, 0x000C, 0 },
636 /* Read INTERRUPT_SOURCE Register */
637 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
638 T1_INTERRUPT_SOURCE_REG, 0, 0 },
639 /* Read INTERRUPT_SOURCE Register */
640 { PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_MISC,
641 T1_INTERRUPT2_SOURCE_REG, 0, 0 },
642 /* HW_Init Hi */
643 { PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_SMI,
644 T1_POWER_DOWN_CONTROL_REG, 0x0300, 0 },
645 };
646 int rc;
647
648 /* phy Soft reset */
649 rc = genphy_soft_reset(phydev);
650 if (rc < 0)
651 return rc;
652
653 /* PHY Initialization */
654 rc = lan87xx_phy_init_cmd(phydev, hw_init, ARRAY_SIZE(hw_init));
655 if (rc < 0)
656 return rc;
657
658 rc = genphy_read_master_slave(phydev);
659 if (rc)
660 return rc;
661
662 /* The following squence needs to run only if phydev is in
663 * slave mode.
664 */
665 if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE) {
666 rc = lan87xx_phy_init_cmd(phydev, slave_init,
667 ARRAY_SIZE(slave_init));
668 if (rc < 0)
669 return rc;
670 }
671
672 rc = lan87xx_phy_init_cmd(phydev, phy_init, ARRAY_SIZE(phy_init));
673 if (rc < 0)
674 return rc;
675
676 return lan87xx_config_rgmii_delay(phydev);
677}
678
679static int lan87xx_phy_config_intr(struct phy_device *phydev)
680{
681 int rc, val = 0;
682
683 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
684 /* clear all interrupt */
685 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
686 if (rc < 0)
687 return rc;
688
689 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
690 if (rc < 0)
691 return rc;
692
693 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
694 PHYACC_ATTR_BANK_MISC,
695 LAN87XX_INTERRUPT_MASK_2, val);
696 if (rc < 0)
697 return rc;
698
699 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
700 PHYACC_ATTR_BANK_MISC,
701 LAN87XX_INTERRUPT_SOURCE_2, 0);
702 if (rc < 0)
703 return rc;
704
705 /* enable link down and comm ready interrupt */
706 val = LAN87XX_MASK_LINK_DOWN;
707 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
708 if (rc < 0)
709 return rc;
710
711 val = LAN87XX_MASK_COMM_RDY;
712 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
713 PHYACC_ATTR_BANK_MISC,
714 LAN87XX_INTERRUPT_MASK_2, val);
715 } else {
716 rc = phy_write(phydev, LAN87XX_INTERRUPT_MASK, val);
717 if (rc < 0)
718 return rc;
719
720 rc = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
721 if (rc < 0)
722 return rc;
723
724 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
725 PHYACC_ATTR_BANK_MISC,
726 LAN87XX_INTERRUPT_MASK_2, val);
727 if (rc < 0)
728 return rc;
729
730 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
731 PHYACC_ATTR_BANK_MISC,
732 LAN87XX_INTERRUPT_SOURCE_2, 0);
733 }
734
735 return rc < 0 ? rc : 0;
736}
737
738static irqreturn_t lan87xx_handle_interrupt(struct phy_device *phydev)
739{
740 int irq_status;
741
742 irq_status = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
743 PHYACC_ATTR_BANK_MISC,
744 LAN87XX_INTERRUPT_SOURCE_2, 0);
745 if (irq_status < 0) {
746 phy_error(phydev);
747 return IRQ_NONE;
748 }
749
750 irq_status = phy_read(phydev, LAN87XX_INTERRUPT_SOURCE);
751 if (irq_status < 0) {
752 phy_error(phydev);
753 return IRQ_NONE;
754 }
755
756 if (irq_status == 0)
757 return IRQ_NONE;
758
759 phy_trigger_machine(phydev);
760
761 return IRQ_HANDLED;
762}
763
764static int lan87xx_config_init(struct phy_device *phydev)
765{
766 int rc = lan87xx_phy_init(phydev);
767
768 return rc < 0 ? rc : 0;
769}
770
771static int microchip_cable_test_start_common(struct phy_device *phydev)
772{
773 int bmcr, bmsr, ret;
774
775 /* If auto-negotiation is enabled, but not complete, the cable
776 * test never completes. So disable auto-neg.
777 */
778 bmcr = phy_read(phydev, MII_BMCR);
779 if (bmcr < 0)
780 return bmcr;
781
782 bmsr = phy_read(phydev, MII_BMSR);
783
784 if (bmsr < 0)
785 return bmsr;
786
787 if (bmcr & BMCR_ANENABLE) {
788 ret = phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0);
789 if (ret < 0)
790 return ret;
791 ret = genphy_soft_reset(phydev);
792 if (ret < 0)
793 return ret;
794 }
795
796 /* If the link is up, allow it some time to go down */
797 if (bmsr & BMSR_LSTATUS)
798 msleep(1500);
799
800 return 0;
801}
802
803static int lan87xx_cable_test_start(struct phy_device *phydev)
804{
805 static const struct access_ereg_val cable_test[] = {
806 /* min wait */
807 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 93,
808 0, 0},
809 /* max wait */
810 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
811 10, 0},
812 /* pulse cycle */
813 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 95,
814 90, 0},
815 /* cable diag thresh */
816 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 92,
817 60, 0},
818 /* max gain */
819 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 79,
820 31, 0},
821 /* clock align for each iteration */
822 {PHYACC_ATTR_MODE_MODIFY, PHYACC_ATTR_BANK_DSP, 55,
823 0, 0x0038},
824 /* max cycle wait config */
825 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 94,
826 70, 0},
827 /* start cable diag*/
828 {PHYACC_ATTR_MODE_WRITE, PHYACC_ATTR_BANK_DSP, 90,
829 1, 0},
830 };
831 int rc, i;
832
833 rc = microchip_cable_test_start_common(phydev);
834 if (rc < 0)
835 return rc;
836
837 /* start cable diag */
838 /* check if part is alive - if not, return diagnostic error */
839 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
840 0x00, 0);
841 if (rc < 0)
842 return rc;
843
844 /* master/slave specific configs */
845 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_SMI,
846 0x0A, 0);
847 if (rc < 0)
848 return rc;
849
850 if ((rc & 0x4000) != 0x4000) {
851 /* DUT is Slave */
852 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_AFE,
853 0x0E, 0x5, 0x7);
854 if (rc < 0)
855 return rc;
856 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
857 0x1A, 0x8, 0x8);
858 if (rc < 0)
859 return rc;
860 } else {
861 /* DUT is Master */
862 rc = access_ereg_modify_changed(phydev, PHYACC_ATTR_BANK_SMI,
863 0x10, 0x8, 0x40);
864 if (rc < 0)
865 return rc;
866 }
867
868 for (i = 0; i < ARRAY_SIZE(cable_test); i++) {
869 if (cable_test[i].mode == PHYACC_ATTR_MODE_MODIFY) {
870 rc = access_ereg_modify_changed(phydev,
871 cable_test[i].bank,
872 cable_test[i].offset,
873 cable_test[i].val,
874 cable_test[i].mask);
875 /* wait 50ms */
876 msleep(50);
877 } else {
878 rc = access_ereg(phydev, cable_test[i].mode,
879 cable_test[i].bank,
880 cable_test[i].offset,
881 cable_test[i].val);
882 }
883 if (rc < 0)
884 return rc;
885 }
886 /* cable diag started */
887
888 return 0;
889}
890
891static int lan87xx_cable_test_report_trans(u32 result)
892{
893 switch (result) {
894 case LAN87XX_CABLE_TEST_OK:
895 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
896 case LAN87XX_CABLE_TEST_OPEN:
897 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
898 case LAN87XX_CABLE_TEST_SAME_SHORT:
899 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
900 default:
901 /* DIAGNOSTIC_ERROR */
902 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
903 }
904}
905
906static int lan87xx_cable_test_report(struct phy_device *phydev)
907{
908 int pos_peak_cycle = 0, pos_peak_in_phases = 0, pos_peak_phase = 0;
909 int neg_peak_cycle = 0, neg_peak_in_phases = 0, neg_peak_phase = 0;
910 int noise_margin = 20, time_margin = 89, jitter_var = 30;
911 int min_time_diff = 96, max_time_diff = 96 + time_margin;
912 bool fault = false, check_a = false, check_b = false;
913 int gain_idx = 0, pos_peak = 0, neg_peak = 0;
914 int pos_peak_time = 0, neg_peak_time = 0;
915 int pos_peak_in_phases_hybrid = 0;
916 int detect = -1;
917
918 gain_idx = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
919 PHYACC_ATTR_BANK_DSP, 151, 0);
920 /* read non-hybrid results */
921 pos_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
922 PHYACC_ATTR_BANK_DSP, 153, 0);
923 neg_peak = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
924 PHYACC_ATTR_BANK_DSP, 154, 0);
925 pos_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
926 PHYACC_ATTR_BANK_DSP, 156, 0);
927 neg_peak_time = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
928 PHYACC_ATTR_BANK_DSP, 157, 0);
929
930 pos_peak_cycle = (pos_peak_time >> 7) & 0x7F;
931 /* calculate non-hybrid values */
932 pos_peak_phase = pos_peak_time & 0x7F;
933 pos_peak_in_phases = (pos_peak_cycle * 96) + pos_peak_phase;
934 neg_peak_cycle = (neg_peak_time >> 7) & 0x7F;
935 neg_peak_phase = neg_peak_time & 0x7F;
936 neg_peak_in_phases = (neg_peak_cycle * 96) + neg_peak_phase;
937
938 /* process values */
939 check_a =
940 ((pos_peak_in_phases - neg_peak_in_phases) >= min_time_diff) &&
941 ((pos_peak_in_phases - neg_peak_in_phases) < max_time_diff) &&
942 pos_peak_in_phases_hybrid < pos_peak_in_phases &&
943 (pos_peak_in_phases_hybrid < (neg_peak_in_phases + jitter_var));
944 check_b =
945 ((neg_peak_in_phases - pos_peak_in_phases) >= min_time_diff) &&
946 ((neg_peak_in_phases - pos_peak_in_phases) < max_time_diff) &&
947 pos_peak_in_phases_hybrid < neg_peak_in_phases &&
948 (pos_peak_in_phases_hybrid < (pos_peak_in_phases + jitter_var));
949
950 if (pos_peak_in_phases > neg_peak_in_phases && check_a)
951 detect = 2;
952 else if ((neg_peak_in_phases > pos_peak_in_phases) && check_b)
953 detect = 1;
954
955 if (pos_peak > noise_margin && neg_peak > noise_margin &&
956 gain_idx >= 0) {
957 if (detect == 1 || detect == 2)
958 fault = true;
959 }
960
961 if (!fault)
962 detect = 0;
963
964 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
965 lan87xx_cable_test_report_trans(detect));
966
967 return phy_init_hw(phydev);
968}
969
970static int lan87xx_cable_test_get_status(struct phy_device *phydev,
971 bool *finished)
972{
973 int rc = 0;
974
975 *finished = false;
976
977 /* check if cable diag was finished */
978 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ, PHYACC_ATTR_BANK_DSP,
979 90, 0);
980 if (rc < 0)
981 return rc;
982
983 if ((rc & 2) == 2) {
984 /* stop cable diag*/
985 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
986 PHYACC_ATTR_BANK_DSP,
987 90, 0);
988 if (rc < 0)
989 return rc;
990
991 *finished = true;
992
993 return lan87xx_cable_test_report(phydev);
994 }
995
996 return 0;
997}
998
999static int lan87xx_read_status(struct phy_device *phydev)
1000{
1001 int rc = 0;
1002
1003 rc = phy_read(phydev, T1_MODE_STAT_REG);
1004 if (rc < 0)
1005 return rc;
1006
1007 if (rc & T1_LINK_UP_MSK)
1008 phydev->link = 1;
1009 else
1010 phydev->link = 0;
1011
1012 phydev->speed = SPEED_UNKNOWN;
1013 phydev->duplex = DUPLEX_UNKNOWN;
1014 phydev->pause = 0;
1015 phydev->asym_pause = 0;
1016
1017 rc = genphy_read_master_slave(phydev);
1018 if (rc < 0)
1019 return rc;
1020
1021 rc = genphy_read_status_fixed(phydev);
1022 if (rc < 0)
1023 return rc;
1024
1025 return rc;
1026}
1027
1028static int lan87xx_config_aneg(struct phy_device *phydev)
1029{
1030 u16 ctl = 0;
1031 int ret;
1032
1033 switch (phydev->master_slave_set) {
1034 case MASTER_SLAVE_CFG_MASTER_FORCE:
1035 ctl |= CTL1000_AS_MASTER;
1036 break;
1037 case MASTER_SLAVE_CFG_SLAVE_FORCE:
1038 break;
1039 case MASTER_SLAVE_CFG_UNKNOWN:
1040 case MASTER_SLAVE_CFG_UNSUPPORTED:
1041 return 0;
1042 default:
1043 phydev_warn(phydev, "Unsupported Master/Slave mode\n");
1044 return -EOPNOTSUPP;
1045 }
1046
1047 ret = phy_modify_changed(phydev, MII_CTRL1000, CTL1000_AS_MASTER, ctl);
1048 if (ret == 1)
1049 return phy_init_hw(phydev);
1050
1051 return ret;
1052}
1053
1054static int lan87xx_get_sqi(struct phy_device *phydev)
1055{
1056 u8 sqi_value = 0;
1057 int rc;
1058
1059 rc = access_ereg(phydev, PHYACC_ATTR_MODE_WRITE,
1060 PHYACC_ATTR_BANK_DSP, T1_COEF_RW_CTL_CFG, 0x0301);
1061 if (rc < 0)
1062 return rc;
1063
1064 rc = access_ereg(phydev, PHYACC_ATTR_MODE_READ,
1065 PHYACC_ATTR_BANK_DSP, T1_DCQ_SQI_REG, 0x0);
1066 if (rc < 0)
1067 return rc;
1068
1069 sqi_value = FIELD_GET(T1_DCQ_SQI_MSK, rc);
1070
1071 return sqi_value;
1072}
1073
1074static int lan87xx_get_sqi_max(struct phy_device *phydev)
1075{
1076 return LAN87XX_MAX_SQI;
1077}
1078
1079static int lan887x_rgmii_init(struct phy_device *phydev)
1080{
1081 int ret;
1082
1083 /* SGMII mux disable */
1084 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1085 LAN887X_SGMII_CTL,
1086 LAN887X_SGMII_CTL_SGMII_MUX_EN);
1087 if (ret < 0)
1088 return ret;
1089
1090 /* Select MAC_MODE as RGMII */
1091 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1092 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
1093 LAN887X_MAC_MODE_RGMII);
1094 if (ret < 0)
1095 return ret;
1096
1097 /* Disable PCS */
1098 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1099 LAN887X_SGMII_PCS_CFG,
1100 LAN887X_SGMII_PCS_CFG_PCS_ENA);
1101 if (ret < 0)
1102 return ret;
1103
1104 /* LAN887x Errata: RGMII rx clock active in SGMII mode
1105 * Disabled it for SGMII mode
1106 * Re-enabling it for RGMII mode
1107 */
1108 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1109 LAN887X_MIS_CFG_REG0,
1110 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
1111}
1112
1113static int lan887x_sgmii_init(struct phy_device *phydev)
1114{
1115 int ret;
1116
1117 /* SGMII mux enable */
1118 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
1119 LAN887X_SGMII_CTL,
1120 LAN887X_SGMII_CTL_SGMII_MUX_EN);
1121 if (ret < 0)
1122 return ret;
1123
1124 /* Select MAC_MODE as SGMII */
1125 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1126 LAN887X_MIS_CFG_REG0_MAC_MODE_SEL,
1127 LAN887X_MAC_MODE_SGMII);
1128 if (ret < 0)
1129 return ret;
1130
1131 /* LAN887x Errata: RGMII rx clock active in SGMII mode.
1132 * So disabling it for SGMII mode
1133 */
1134 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_CFG_REG0,
1135 LAN887X_MIS_CFG_REG0_RCLKOUT_DIS);
1136 if (ret < 0)
1137 return ret;
1138
1139 /* Enable PCS */
1140 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SGMII_PCS_CFG,
1141 LAN887X_SGMII_PCS_CFG_PCS_ENA);
1142}
1143
1144static int lan887x_config_rgmii_en(struct phy_device *phydev)
1145{
1146 int txc;
1147 int rxc;
1148 int ret;
1149
1150 ret = lan887x_rgmii_init(phydev);
1151 if (ret < 0)
1152 return ret;
1153
1154 /* Control bit to enable/disable TX DLL delay line in signal path */
1155 txc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0);
1156 if (txc < 0)
1157 return txc;
1158
1159 /* Control bit to enable/disable RX DLL delay line in signal path */
1160 rxc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1);
1161 if (rxc < 0)
1162 return rxc;
1163
1164 /* Configures the phy to enable RX/TX delay
1165 * RGMII - TX & RX delays are either added by MAC or not needed,
1166 * phy should not add
1167 * RGMII_ID - Configures phy to enable TX & RX delays, MAC shouldn't add
1168 * RGMII_RX_ID - Configures the PHY to enable the RX delay.
1169 * The MAC shouldn't add the RX delay
1170 * RGMII_TX_ID - Configures the PHY to enable the TX delay.
1171 * The MAC shouldn't add the TX delay in this case
1172 */
1173 switch (phydev->interface) {
1174 case PHY_INTERFACE_MODE_RGMII:
1175 txc &= ~LAN887X_MIS_DLL_CONF;
1176 rxc &= ~LAN887X_MIS_DLL_CONF;
1177 break;
1178 case PHY_INTERFACE_MODE_RGMII_ID:
1179 txc |= LAN887X_MIS_DLL_CONF;
1180 rxc |= LAN887X_MIS_DLL_CONF;
1181 break;
1182 case PHY_INTERFACE_MODE_RGMII_RXID:
1183 txc &= ~LAN887X_MIS_DLL_CONF;
1184 rxc |= LAN887X_MIS_DLL_CONF;
1185 break;
1186 case PHY_INTERFACE_MODE_RGMII_TXID:
1187 txc |= LAN887X_MIS_DLL_CONF;
1188 rxc &= ~LAN887X_MIS_DLL_CONF;
1189 break;
1190 default:
1191 WARN_ONCE(1, "Invalid phydev interface %d\n", phydev->interface);
1192 return 0;
1193 }
1194
1195 /* Configures the PHY to enable/disable RX delay in signal path */
1196 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG1,
1197 LAN887X_MIS_DLL_CONF, rxc);
1198 if (ret < 0)
1199 return ret;
1200
1201 /* Configures the PHY to enable/disable the TX delay in signal path */
1202 return phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_MIS_DLL_CFG_REG0,
1203 LAN887X_MIS_DLL_CONF, txc);
1204}
1205
1206static int lan887x_config_phy_interface(struct phy_device *phydev)
1207{
1208 int interface_mode;
1209 int sgmii_dis;
1210 int ret;
1211
1212 /* Read sku efuse data for interfaces supported by sku */
1213 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_EFUSE_READ_DAT9);
1214 if (ret < 0)
1215 return ret;
1216
1217 /* If interface_mode is 1 then efuse sets RGMII operations.
1218 * If interface mode is 3 then efuse sets SGMII operations.
1219 */
1220 interface_mode = ret & LAN887X_EFUSE_READ_DAT9_MAC_MODE;
1221 /* SGMII disable is set for RGMII operations */
1222 sgmii_dis = ret & LAN887X_EFUSE_READ_DAT9_SGMII_DIS;
1223
1224 switch (phydev->interface) {
1225 case PHY_INTERFACE_MODE_RGMII:
1226 case PHY_INTERFACE_MODE_RGMII_ID:
1227 case PHY_INTERFACE_MODE_RGMII_RXID:
1228 case PHY_INTERFACE_MODE_RGMII_TXID:
1229 /* Reject RGMII settings for SGMII only sku */
1230 ret = -EOPNOTSUPP;
1231
1232 if (!((interface_mode & LAN887X_MAC_MODE_SGMII) ==
1233 LAN887X_MAC_MODE_SGMII))
1234 ret = lan887x_config_rgmii_en(phydev);
1235 break;
1236 case PHY_INTERFACE_MODE_SGMII:
1237 /* Reject SGMII setting for RGMII only sku */
1238 ret = -EOPNOTSUPP;
1239
1240 if (!sgmii_dis)
1241 ret = lan887x_sgmii_init(phydev);
1242 break;
1243 default:
1244 /* Reject setting for unsupported interfaces */
1245 ret = -EOPNOTSUPP;
1246 }
1247
1248 return ret;
1249}
1250
1251static int lan887x_get_features(struct phy_device *phydev)
1252{
1253 int ret;
1254
1255 ret = genphy_c45_pma_read_abilities(phydev);
1256 if (ret < 0)
1257 return ret;
1258
1259 /* Enable twisted pair */
1260 linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
1261
1262 /* First patch only supports 100Mbps and 1000Mbps force-mode.
1263 * T1 Auto-Negotiation (Clause 98 of IEEE 802.3) will be added later.
1264 */
1265 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
1266
1267 return 0;
1268}
1269
1270static int lan887x_phy_init(struct phy_device *phydev)
1271{
1272 int ret;
1273
1274 /* Clear loopback */
1275 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1,
1276 LAN887X_MIS_CFG_REG2,
1277 LAN887X_MIS_CFG_REG2_FE_LPBK_EN);
1278 if (ret < 0)
1279 return ret;
1280
1281 /* Configure default behavior of led to link and activity for any
1282 * speed
1283 */
1284 ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1285 LAN887X_COMMON_LED3_LED2,
1286 LAN887X_COMMON_LED2_MODE_SEL_MASK,
1287 LAN887X_LED_LINK_ACT_ANY_SPEED);
1288 if (ret < 0)
1289 return ret;
1290
1291 /* PHY interface setup */
1292 return lan887x_config_phy_interface(phydev);
1293}
1294
1295static int lan887x_phy_config(struct phy_device *phydev,
1296 const struct lan887x_regwr_map *reg_map, int cnt)
1297{
1298 int ret;
1299
1300 for (int i = 0; i < cnt; i++) {
1301 ret = phy_write_mmd(phydev, reg_map[i].mmd,
1302 reg_map[i].reg, reg_map[i].val);
1303 if (ret < 0)
1304 return ret;
1305 }
1306
1307 return 0;
1308}
1309
1310static int lan887x_phy_setup(struct phy_device *phydev)
1311{
1312 static const struct lan887x_regwr_map phy_cfg[] = {
1313 /* PORT_AFE writes */
1314 {MDIO_MMD_PMAPMD, LAN887X_ZQCAL_CONTROL_1, 0x4008},
1315 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL2, 0x0000},
1316 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL6, 0x0040},
1317 /* 100T1_PCS_VENDOR writes */
1318 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_CNT_THRESH, 0x0008},
1319 {MDIO_MMD_PCS, LAN887X_IDLE_ERR_TIMER_WIN, 0x800d},
1320 /* 100T1 DSP writes */
1321 {MDIO_MMD_VEND1, LAN887x_CDR_CONFIG1_100, 0x0ab1},
1322 {MDIO_MMD_VEND1, LAN887x_LOCK1_EQLSR_CONFIG_100, 0x5274},
1323 {MDIO_MMD_VEND1, LAN887x_SLV_HD_MUFAC_CONFIG_100, 0x0d74},
1324 {MDIO_MMD_VEND1, LAN887x_PLOCK_MUFAC_CONFIG_100, 0x0aea},
1325 {MDIO_MMD_VEND1, LAN887x_PROT_DISABLE_100, 0x0360},
1326 {MDIO_MMD_VEND1, LAN887x_KF_LOOP_SAT_CONFIG_100, 0x0c30},
1327 /* 1000T1 DSP writes */
1328 {MDIO_MMD_VEND1, LAN887X_LOCK1_EQLSR_CONFIG, 0x2a78},
1329 {MDIO_MMD_VEND1, LAN887X_LOCK3_EQLSR_CONFIG, 0x1368},
1330 {MDIO_MMD_VEND1, LAN887X_PROT_DISABLE, 0x1354},
1331 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN6, 0x3C84},
1332 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN7, 0x3ca5},
1333 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN8, 0x3ca5},
1334 {MDIO_MMD_VEND1, LAN887X_FFE_GAIN9, 0x3ca5},
1335 {MDIO_MMD_VEND1, LAN887X_ECHO_DELAY_CONFIG, 0x0024},
1336 {MDIO_MMD_VEND1, LAN887X_FFE_MAX_CONFIG, 0x227f},
1337 /* 1000T1 PCS writes */
1338 {MDIO_MMD_PCS, LAN887X_SCR_CONFIG_3, 0x1e00},
1339 {MDIO_MMD_PCS, LAN887X_INFO_FLD_CONFIG_5, 0x0fa1},
1340 };
1341
1342 return lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1343}
1344
1345static int lan887x_100M_setup(struct phy_device *phydev)
1346{
1347 int ret;
1348
1349 /* (Re)configure the speed/mode dependent T1 settings */
1350 if (phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_FORCE ||
1351 phydev->master_slave_set == MASTER_SLAVE_CFG_MASTER_PREFERRED){
1352 static const struct lan887x_regwr_map phy_cfg[] = {
1353 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1354 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x0038},
1355 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x000f},
1356 };
1357
1358 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1359 } else {
1360 static const struct lan887x_regwr_map phy_cfg[] = {
1361 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x0038},
1362 {MDIO_MMD_VEND1, LAN887X_INIT_COEFF_DFE1_100, 0x0014},
1363 };
1364
1365 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1366 }
1367 if (ret < 0)
1368 return ret;
1369
1370 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1371 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1372}
1373
1374static int lan887x_1000M_setup(struct phy_device *phydev)
1375{
1376 static const struct lan887x_regwr_map phy_cfg[] = {
1377 {MDIO_MMD_PMAPMD, LAN887X_TX_AMPLT_1000T1_REG, 0x003f},
1378 {MDIO_MMD_PMAPMD, LAN887X_AFE_PORT_TESTBUS_CTRL4, 0x00b8},
1379 };
1380 int ret;
1381
1382 /* (Re)configure the speed/mode dependent T1 settings */
1383 ret = lan887x_phy_config(phydev, phy_cfg, ARRAY_SIZE(phy_cfg));
1384 if (ret < 0)
1385 return ret;
1386
1387 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
1388 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
1389}
1390
1391static int lan887x_link_setup(struct phy_device *phydev)
1392{
1393 int ret = -EINVAL;
1394
1395 if (phydev->speed == SPEED_1000)
1396 ret = lan887x_1000M_setup(phydev);
1397 else if (phydev->speed == SPEED_100)
1398 ret = lan887x_100M_setup(phydev);
1399
1400 return ret;
1401}
1402
1403/* LAN887x Errata: speed configuration changes require soft reset
1404 * and chip soft reset
1405 */
1406static int lan887x_phy_reset(struct phy_device *phydev)
1407{
1408 int ret, val;
1409
1410 /* Clear 1000M link sync */
1411 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, LAN887X_DSP_PMA_CONTROL,
1412 LAN887X_DSP_PMA_CONTROL_LNK_SYNC);
1413 if (ret < 0)
1414 return ret;
1415
1416 /* Clear 100M link sync */
1417 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1418 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1419 if (ret < 0)
1420 return ret;
1421
1422 /* Chiptop soft-reset to allow the speed/mode change */
1423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_SOFT_RST,
1424 LAN887X_CHIP_SOFT_RST_RESET);
1425 if (ret < 0)
1426 return ret;
1427
1428 /* CL22 soft-reset to let the link re-train */
1429 ret = phy_modify(phydev, MII_BMCR, BMCR_RESET, BMCR_RESET);
1430 if (ret < 0)
1431 return ret;
1432
1433 /* Wait for reset complete or timeout if > 10ms */
1434 return phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1435 5000, 10000, true);
1436}
1437
1438static int lan887x_phy_reconfig(struct phy_device *phydev)
1439{
1440 int ret;
1441
1442 linkmode_zero(phydev->advertising);
1443
1444 ret = genphy_c45_pma_setup_forced(phydev);
1445 if (ret < 0)
1446 return ret;
1447
1448 return lan887x_link_setup(phydev);
1449}
1450
1451static int lan887x_config_aneg(struct phy_device *phydev)
1452{
1453 int ret;
1454
1455 /* LAN887x Errata: speed configuration changes require soft reset
1456 * and chip soft reset
1457 */
1458 ret = lan887x_phy_reset(phydev);
1459 if (ret < 0)
1460 return ret;
1461
1462 return lan887x_phy_reconfig(phydev);
1463}
1464
1465static int lan887x_probe(struct phy_device *phydev)
1466{
1467 struct lan887x_priv *priv;
1468
1469 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1470 if (!priv)
1471 return -ENOMEM;
1472
1473 phydev->priv = priv;
1474
1475 return lan887x_phy_setup(phydev);
1476}
1477
1478static u64 lan887x_get_stat(struct phy_device *phydev, int i)
1479{
1480 struct lan887x_hw_stat stat = lan887x_hw_stats[i];
1481 struct lan887x_priv *priv = phydev->priv;
1482 int val;
1483 u64 ret;
1484
1485 if (stat.mmd)
1486 val = phy_read_mmd(phydev, stat.mmd, stat.reg);
1487 else
1488 val = phy_read(phydev, stat.reg);
1489
1490 if (val < 0) {
1491 ret = U64_MAX;
1492 } else {
1493 val = val & ((1 << stat.bits) - 1);
1494 priv->stats[i] += val;
1495 ret = priv->stats[i];
1496 }
1497
1498 return ret;
1499}
1500
1501static void lan887x_get_stats(struct phy_device *phydev,
1502 struct ethtool_stats *stats, u64 *data)
1503{
1504 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1505 data[i] = lan887x_get_stat(phydev, i);
1506}
1507
1508static int lan887x_get_sset_count(struct phy_device *phydev)
1509{
1510 return ARRAY_SIZE(lan887x_hw_stats);
1511}
1512
1513static void lan887x_get_strings(struct phy_device *phydev, u8 *data)
1514{
1515 for (int i = 0; i < ARRAY_SIZE(lan887x_hw_stats); i++)
1516 ethtool_puts(&data, lan887x_hw_stats[i].string);
1517}
1518
1519static int lan887x_config_intr(struct phy_device *phydev)
1520{
1521 int rc;
1522
1523 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1524 /* Clear the interrupt status before enabling interrupts */
1525 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1526 if (rc < 0)
1527 return rc;
1528
1529 /* Unmask for enabling interrupt */
1530 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1531 (u16)~LAN887X_MX_CHIP_TOP_ALL_MSK);
1532 } else {
1533 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_MSK,
1534 GENMASK(15, 0));
1535 if (rc < 0)
1536 return rc;
1537
1538 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1539 }
1540
1541 return rc < 0 ? rc : 0;
1542}
1543
1544static irqreturn_t lan887x_handle_interrupt(struct phy_device *phydev)
1545{
1546 int irq_status;
1547
1548 irq_status = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_INT_STS);
1549 if (irq_status < 0) {
1550 phy_error(phydev);
1551 return IRQ_NONE;
1552 }
1553
1554 if (irq_status & LAN887X_MX_CHIP_TOP_LINK_MSK) {
1555 phy_trigger_machine(phydev);
1556 return IRQ_HANDLED;
1557 }
1558
1559 return IRQ_NONE;
1560}
1561
1562static int lan887x_cd_reset(struct phy_device *phydev,
1563 enum cable_diag_state cd_done)
1564{
1565 u16 val;
1566 int rc;
1567
1568 /* Chip hard-reset */
1569 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_CHIP_HARD_RST,
1570 LAN887X_CHIP_HARD_RST_RESET);
1571 if (rc < 0)
1572 return rc;
1573
1574 /* Wait for reset to complete */
1575 rc = phy_read_poll_timeout(phydev, MII_PHYSID2, val,
1576 ((val & GENMASK(15, 4)) ==
1577 (PHY_ID_LAN887X & GENMASK(15, 4))),
1578 5000, 50000, true);
1579 if (rc < 0)
1580 return rc;
1581
1582 if (cd_done == CD_TEST_DONE) {
1583 /* Cable diagnostics complete. Restore PHY. */
1584 rc = lan887x_phy_setup(phydev);
1585 if (rc < 0)
1586 return rc;
1587
1588 rc = lan887x_phy_init(phydev);
1589 if (rc < 0)
1590 return rc;
1591
1592 rc = lan887x_config_intr(phydev);
1593 if (rc < 0)
1594 return rc;
1595
1596 rc = lan887x_phy_reconfig(phydev);
1597 if (rc < 0)
1598 return rc;
1599 }
1600
1601 return 0;
1602}
1603
1604static int lan887x_cable_test_prep(struct phy_device *phydev,
1605 enum cable_diag_mode mode)
1606{
1607 static const struct lan887x_regwr_map values[] = {
1608 {MDIO_MMD_VEND1, LAN887X_MAX_PGA_GAIN_100, 0x1f},
1609 {MDIO_MMD_VEND1, LAN887X_MIN_PGA_GAIN_100, 0x0},
1610 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TDR_THRESH_100, 0x1},
1611 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_AGC_THRESH_100, 0x3c},
1612 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_WAIT_CONFIG_100, 0x0},
1613 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100, 0x46},
1614 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_CYC_CONFIG_100, 0x5a},
1615 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_TX_PULSE_CONFIG_100, 0x44d5},
1616 {MDIO_MMD_VEND1, LAN887X_CBL_DIAG_MIN_PGA_GAIN_100, 0x0},
1617
1618 };
1619 int rc;
1620
1621 rc = lan887x_cd_reset(phydev, CD_TEST_INIT);
1622 if (rc < 0)
1623 return rc;
1624
1625 /* Forcing DUT to master mode, as we don't care about
1626 * mode during diagnostics
1627 */
1628 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL,
1629 MDIO_PMA_PMD_BT1_CTRL_CFG_MST);
1630 if (rc < 0)
1631 return rc;
1632
1633 rc = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, 0x80b0, 0x0038);
1634 if (rc < 0)
1635 return rc;
1636
1637 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1,
1638 LAN887X_CALIB_CONFIG_100, 0,
1639 LAN887X_CALIB_CONFIG_100_VAL);
1640 if (rc < 0)
1641 return rc;
1642
1643 for (int i = 0; i < ARRAY_SIZE(values); i++) {
1644 rc = phy_write_mmd(phydev, values[i].mmd, values[i].reg,
1645 values[i].val);
1646 if (rc < 0)
1647 return rc;
1648
1649 if (mode &&
1650 values[i].reg == LAN887X_CBL_DIAG_MAX_WAIT_CONFIG_100) {
1651 rc = phy_write_mmd(phydev, values[i].mmd,
1652 values[i].reg, 0xa);
1653 if (rc < 0)
1654 return rc;
1655 }
1656 }
1657
1658 if (mode == TEST_MODE_HYBRID) {
1659 rc = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD,
1660 LAN887X_AFE_PORT_TESTBUS_CTRL4,
1661 BIT(0), BIT(0));
1662 if (rc < 0)
1663 return rc;
1664 }
1665
1666 /* HW_INIT 100T1, Get DUT running in 100T1 mode */
1667 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_REG_REG26,
1668 LAN887X_REG_REG26_HW_INIT_SEQ_EN,
1669 LAN887X_REG_REG26_HW_INIT_SEQ_EN);
1670 if (rc < 0)
1671 return rc;
1672
1673 /* Cable diag requires hard reset and is sensitive regarding the delays.
1674 * Hard reset is expected into and out of cable diag.
1675 * Wait for 50ms
1676 */
1677 msleep(50);
1678
1679 /* Start cable diag */
1680 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1681 LAN887X_START_CBL_DIAG_100,
1682 LAN887X_CBL_DIAG_START);
1683}
1684
1685static int lan887x_cable_test_chk(struct phy_device *phydev,
1686 enum cable_diag_mode mode)
1687{
1688 int val;
1689 int rc;
1690
1691 if (mode == TEST_MODE_HYBRID) {
1692 /* Cable diag requires hard reset and is sensitive regarding the delays.
1693 * Hard reset is expected into and out of cable diag.
1694 * Wait for cable diag to complete.
1695 * Minimum wait time is 50ms if the condition is not a match.
1696 */
1697 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
1698 LAN887X_START_CBL_DIAG_100, val,
1699 ((val & LAN887X_CBL_DIAG_DONE) ==
1700 LAN887X_CBL_DIAG_DONE),
1701 50000, 500000, false);
1702 if (rc < 0)
1703 return rc;
1704 } else {
1705 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1706 LAN887X_START_CBL_DIAG_100);
1707 if (rc < 0)
1708 return rc;
1709
1710 if ((rc & LAN887X_CBL_DIAG_DONE) != LAN887X_CBL_DIAG_DONE)
1711 return -EAGAIN;
1712 }
1713
1714 /* Stop cable diag */
1715 return phy_write_mmd(phydev, MDIO_MMD_VEND1,
1716 LAN887X_START_CBL_DIAG_100,
1717 LAN887X_CBL_DIAG_STOP);
1718}
1719
1720static int lan887x_cable_test_start(struct phy_device *phydev)
1721{
1722 int rc, ret;
1723
1724 rc = lan887x_cable_test_prep(phydev, TEST_MODE_NORMAL);
1725 if (rc < 0) {
1726 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);
1727 if (ret < 0)
1728 return ret;
1729
1730 return rc;
1731 }
1732
1733 return 0;
1734}
1735
1736static int lan887x_cable_test_report(struct phy_device *phydev)
1737{
1738 int pos_peak_cycle, pos_peak_cycle_hybrid, pos_peak_in_phases;
1739 int pos_peak_time, pos_peak_time_hybrid, neg_peak_time;
1740 int neg_peak_cycle, neg_peak_in_phases;
1741 int pos_peak_in_phases_hybrid;
1742 int gain_idx, gain_idx_hybrid;
1743 int pos_peak_phase_hybrid;
1744 int pos_peak, neg_peak;
1745 int distance;
1746 int detect;
1747 int length;
1748 int ret;
1749 int rc;
1750
1751 /* Read non-hybrid results */
1752 gain_idx = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1753 LAN887X_CBL_DIAG_AGC_GAIN_100);
1754 if (gain_idx < 0) {
1755 rc = gain_idx;
1756 goto error;
1757 }
1758
1759 pos_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1760 LAN887X_CBL_DIAG_POS_PEAK_VALUE_100);
1761 if (pos_peak < 0) {
1762 rc = pos_peak;
1763 goto error;
1764 }
1765
1766 neg_peak = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1767 LAN887X_CBL_DIAG_NEG_PEAK_VALUE_100);
1768 if (neg_peak < 0) {
1769 rc = neg_peak;
1770 goto error;
1771 }
1772
1773 pos_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1774 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);
1775 if (pos_peak_time < 0) {
1776 rc = pos_peak_time;
1777 goto error;
1778 }
1779
1780 neg_peak_time = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1781 LAN887X_CBL_DIAG_NEG_PEAK_TIME_100);
1782 if (neg_peak_time < 0) {
1783 rc = neg_peak_time;
1784 goto error;
1785 }
1786
1787 /* Calculate non-hybrid values */
1788 pos_peak_cycle = (pos_peak_time >> 7) & 0x7f;
1789 pos_peak_in_phases = (pos_peak_cycle * 96) + (pos_peak_time & 0x7f);
1790 neg_peak_cycle = (neg_peak_time >> 7) & 0x7f;
1791 neg_peak_in_phases = (neg_peak_cycle * 96) + (neg_peak_time & 0x7f);
1792
1793 /* Deriving the status of cable */
1794 if (pos_peak > MICROCHIP_CABLE_NOISE_MARGIN &&
1795 neg_peak > MICROCHIP_CABLE_NOISE_MARGIN && gain_idx >= 0) {
1796 if (pos_peak_in_phases > neg_peak_in_phases &&
1797 ((pos_peak_in_phases - neg_peak_in_phases) >=
1798 MICROCHIP_CABLE_MIN_TIME_DIFF) &&
1799 ((pos_peak_in_phases - neg_peak_in_phases) <
1800 MICROCHIP_CABLE_MAX_TIME_DIFF) &&
1801 pos_peak_in_phases > 0) {
1802 detect = LAN87XX_CABLE_TEST_SAME_SHORT;
1803 } else if (neg_peak_in_phases > pos_peak_in_phases &&
1804 ((neg_peak_in_phases - pos_peak_in_phases) >=
1805 MICROCHIP_CABLE_MIN_TIME_DIFF) &&
1806 ((neg_peak_in_phases - pos_peak_in_phases) <
1807 MICROCHIP_CABLE_MAX_TIME_DIFF) &&
1808 neg_peak_in_phases > 0) {
1809 detect = LAN87XX_CABLE_TEST_OPEN;
1810 } else {
1811 detect = LAN87XX_CABLE_TEST_OK;
1812 }
1813 } else {
1814 detect = LAN87XX_CABLE_TEST_OK;
1815 }
1816
1817 if (detect == LAN87XX_CABLE_TEST_OK) {
1818 distance = 0;
1819 goto get_len;
1820 }
1821
1822 /* Re-initialize PHY and start cable diag test */
1823 rc = lan887x_cable_test_prep(phydev, TEST_MODE_HYBRID);
1824 if (rc < 0)
1825 goto cd_stop;
1826
1827 /* Wait for cable diag test completion */
1828 rc = lan887x_cable_test_chk(phydev, TEST_MODE_HYBRID);
1829 if (rc < 0)
1830 goto cd_stop;
1831
1832 /* Read hybrid results */
1833 gain_idx_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1834 LAN887X_CBL_DIAG_AGC_GAIN_100);
1835 if (gain_idx_hybrid < 0) {
1836 rc = gain_idx_hybrid;
1837 goto error;
1838 }
1839
1840 pos_peak_time_hybrid = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1841 LAN887X_CBL_DIAG_POS_PEAK_TIME_100);
1842 if (pos_peak_time_hybrid < 0) {
1843 rc = pos_peak_time_hybrid;
1844 goto error;
1845 }
1846
1847 /* Calculate hybrid values to derive cable length to fault */
1848 pos_peak_cycle_hybrid = (pos_peak_time_hybrid >> 7) & 0x7f;
1849 pos_peak_phase_hybrid = pos_peak_time_hybrid & 0x7f;
1850 pos_peak_in_phases_hybrid = pos_peak_cycle_hybrid * 96 +
1851 pos_peak_phase_hybrid;
1852
1853 /* Distance to fault calculation.
1854 * distance = (peak_in_phases - peak_in_phases_hybrid) *
1855 * propagationconstant.
1856 * constant to convert number of phases to meters
1857 * propagationconstant = 0.015953
1858 * (0.6811 * 2.9979 * 156.2499 * 0.0001 * 0.5)
1859 * Applying constant 1.5953 as ethtool further devides by 100 to
1860 * convert to meters.
1861 */
1862 if (detect == LAN87XX_CABLE_TEST_OPEN) {
1863 distance = (((pos_peak_in_phases - pos_peak_in_phases_hybrid)
1864 * 15953) / 10000);
1865 } else if (detect == LAN87XX_CABLE_TEST_SAME_SHORT) {
1866 distance = (((neg_peak_in_phases - pos_peak_in_phases_hybrid)
1867 * 15953) / 10000);
1868 } else {
1869 distance = 0;
1870 }
1871
1872get_len:
1873 rc = lan887x_cd_reset(phydev, CD_TEST_DONE);
1874 if (rc < 0)
1875 return rc;
1876
1877 length = ((u32)distance & GENMASK(15, 0));
1878 ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A,
1879 lan87xx_cable_test_report_trans(detect));
1880 ethnl_cable_test_fault_length(phydev, ETHTOOL_A_CABLE_PAIR_A, length);
1881
1882 return 0;
1883
1884cd_stop:
1885 /* Stop cable diag */
1886 ret = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1887 LAN887X_START_CBL_DIAG_100,
1888 LAN887X_CBL_DIAG_STOP);
1889 if (ret < 0)
1890 return ret;
1891
1892error:
1893 /* Cable diag test failed */
1894 ret = lan887x_cd_reset(phydev, CD_TEST_DONE);
1895 if (ret < 0)
1896 return ret;
1897
1898 /* Return error in failure case */
1899 return rc;
1900}
1901
1902static int lan887x_cable_test_get_status(struct phy_device *phydev,
1903 bool *finished)
1904{
1905 int rc;
1906
1907 rc = lan887x_cable_test_chk(phydev, TEST_MODE_NORMAL);
1908 if (rc < 0) {
1909 /* Let PHY statemachine poll again */
1910 if (rc == -EAGAIN)
1911 return 0;
1912 return rc;
1913 }
1914
1915 /* Cable diag test complete */
1916 *finished = true;
1917
1918 /* Retrieve test status and cable length to fault */
1919 return lan887x_cable_test_report(phydev);
1920}
1921
1922/* Compare block to sort in ascending order */
1923static int sqi_compare(const void *a, const void *b)
1924{
1925 return *(u16 *)a - *(u16 *)b;
1926}
1927
1928static int lan887x_get_sqi_100M(struct phy_device *phydev)
1929{
1930 u16 rawtable[SQI_SAMPLES];
1931 u32 sqiavg = 0;
1932 u8 sqinum = 0;
1933 int rc, i;
1934
1935 /* Configuration of SQI 100M */
1936 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1937 LAN887X_COEFF_PWR_DN_CONFIG_100,
1938 LAN887X_COEFF_PWR_DN_CONFIG_100_V);
1939 if (rc < 0)
1940 return rc;
1941
1942 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100,
1943 LAN887X_SQI_CONFIG_100_V);
1944 if (rc < 0)
1945 return rc;
1946
1947 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_SQI_CONFIG_100);
1948 if (rc != LAN887X_SQI_CONFIG_100_V)
1949 return -EINVAL;
1950
1951 rc = phy_modify_mmd(phydev, MDIO_MMD_VEND1, LAN887X_POKE_PEEK_100,
1952 LAN887X_POKE_PEEK_100_EN,
1953 LAN887X_POKE_PEEK_100_EN);
1954 if (rc < 0)
1955 return rc;
1956
1957 /* Required before reading register
1958 * otherwise it will return high value
1959 */
1960 msleep(50);
1961
1962 /* Link check before raw readings */
1963 rc = genphy_c45_read_link(phydev);
1964 if (rc < 0)
1965 return rc;
1966
1967 if (!phydev->link)
1968 return -ENETDOWN;
1969
1970 /* Get 200 SQI raw readings */
1971 for (i = 0; i < SQI_SAMPLES; i++) {
1972 rc = phy_write_mmd(phydev, MDIO_MMD_VEND1,
1973 LAN887X_POKE_PEEK_100,
1974 LAN887X_POKE_PEEK_100_EN);
1975 if (rc < 0)
1976 return rc;
1977
1978 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1,
1979 LAN887X_SQI_MSE_100);
1980 if (rc < 0)
1981 return rc;
1982
1983 rawtable[i] = (u16)rc;
1984 }
1985
1986 /* Link check after raw readings */
1987 rc = genphy_c45_read_link(phydev);
1988 if (rc < 0)
1989 return rc;
1990
1991 if (!phydev->link)
1992 return -ENETDOWN;
1993
1994 /* Sort SQI raw readings in ascending order */
1995 sort(rawtable, SQI_SAMPLES, sizeof(u16), sqi_compare, NULL);
1996
1997 /* Keep inliers and discard outliers */
1998 for (i = SQI_INLIERS_START; i < SQI_INLIERS_END; i++)
1999 sqiavg += rawtable[i];
2000
2001 /* Handle invalid samples */
2002 if (sqiavg != 0) {
2003 /* Get SQI average */
2004 sqiavg /= SQI_INLIERS_NUM;
2005
2006 if (sqiavg < 75)
2007 sqinum = 7;
2008 else if (sqiavg < 94)
2009 sqinum = 6;
2010 else if (sqiavg < 119)
2011 sqinum = 5;
2012 else if (sqiavg < 150)
2013 sqinum = 4;
2014 else if (sqiavg < 189)
2015 sqinum = 3;
2016 else if (sqiavg < 237)
2017 sqinum = 2;
2018 else if (sqiavg < 299)
2019 sqinum = 1;
2020 else
2021 sqinum = 0;
2022 }
2023
2024 return sqinum;
2025}
2026
2027static int lan887x_get_sqi(struct phy_device *phydev)
2028{
2029 int rc, val;
2030
2031 if (phydev->speed != SPEED_1000 &&
2032 phydev->speed != SPEED_100)
2033 return -ENETDOWN;
2034
2035 if (phydev->speed == SPEED_100)
2036 return lan887x_get_sqi_100M(phydev);
2037
2038 /* Writing DCQ_COEFF_EN to trigger a SQI read */
2039 rc = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1,
2040 LAN887X_COEFF_MOD_CONFIG,
2041 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN);
2042 if (rc < 0)
2043 return rc;
2044
2045 /* Wait for DCQ done */
2046 rc = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
2047 LAN887X_COEFF_MOD_CONFIG, val, ((val &
2048 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN) !=
2049 LAN887X_COEFF_MOD_CONFIG_DCQ_COEFF_EN),
2050 10, 200, true);
2051 if (rc < 0)
2052 return rc;
2053
2054 rc = phy_read_mmd(phydev, MDIO_MMD_VEND1, LAN887X_DCQ_SQI_STATUS);
2055 if (rc < 0)
2056 return rc;
2057
2058 return FIELD_GET(T1_DCQ_SQI_MSK, rc);
2059}
2060
2061static struct phy_driver microchip_t1_phy_driver[] = {
2062 {
2063 PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX),
2064 .name = "Microchip LAN87xx T1",
2065 .flags = PHY_POLL_CABLE_TEST,
2066 .features = PHY_BASIC_T1_FEATURES,
2067 .config_init = lan87xx_config_init,
2068 .config_intr = lan87xx_phy_config_intr,
2069 .handle_interrupt = lan87xx_handle_interrupt,
2070 .suspend = genphy_suspend,
2071 .resume = genphy_resume,
2072 .config_aneg = lan87xx_config_aneg,
2073 .read_status = lan87xx_read_status,
2074 .get_sqi = lan87xx_get_sqi,
2075 .get_sqi_max = lan87xx_get_sqi_max,
2076 .cable_test_start = lan87xx_cable_test_start,
2077 .cable_test_get_status = lan87xx_cable_test_get_status,
2078 },
2079 {
2080 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X),
2081 .name = "Microchip LAN937x T1",
2082 .flags = PHY_POLL_CABLE_TEST,
2083 .features = PHY_BASIC_T1_FEATURES,
2084 .config_init = lan87xx_config_init,
2085 .config_intr = lan87xx_phy_config_intr,
2086 .handle_interrupt = lan87xx_handle_interrupt,
2087 .suspend = genphy_suspend,
2088 .resume = genphy_resume,
2089 .config_aneg = lan87xx_config_aneg,
2090 .read_status = lan87xx_read_status,
2091 .get_sqi = lan87xx_get_sqi,
2092 .get_sqi_max = lan87xx_get_sqi_max,
2093 .cable_test_start = lan87xx_cable_test_start,
2094 .cable_test_get_status = lan87xx_cable_test_get_status,
2095 },
2096 {
2097 PHY_ID_MATCH_MODEL(PHY_ID_LAN887X),
2098 .name = "Microchip LAN887x T1 PHY",
2099 .flags = PHY_POLL_CABLE_TEST,
2100 .probe = lan887x_probe,
2101 .get_features = lan887x_get_features,
2102 .config_init = lan887x_phy_init,
2103 .config_aneg = lan887x_config_aneg,
2104 .get_stats = lan887x_get_stats,
2105 .get_sset_count = lan887x_get_sset_count,
2106 .get_strings = lan887x_get_strings,
2107 .suspend = genphy_suspend,
2108 .resume = genphy_resume,
2109 .read_status = genphy_c45_read_status,
2110 .cable_test_start = lan887x_cable_test_start,
2111 .cable_test_get_status = lan887x_cable_test_get_status,
2112 .config_intr = lan887x_config_intr,
2113 .handle_interrupt = lan887x_handle_interrupt,
2114 .get_sqi = lan887x_get_sqi,
2115 .get_sqi_max = lan87xx_get_sqi_max,
2116 .set_loopback = genphy_c45_loopback,
2117 }
2118};
2119
2120module_phy_driver(microchip_t1_phy_driver);
2121
2122static struct mdio_device_id __maybe_unused microchip_t1_tbl[] = {
2123 { PHY_ID_MATCH_MODEL(PHY_ID_LAN87XX) },
2124 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X) },
2125 { PHY_ID_MATCH_MODEL(PHY_ID_LAN887X) },
2126 { }
2127};
2128
2129MODULE_DEVICE_TABLE(mdio, microchip_t1_tbl);
2130
2131MODULE_AUTHOR(DRIVER_AUTHOR);
2132MODULE_DESCRIPTION(DRIVER_DESC);
2133MODULE_LICENSE("GPL");