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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2015 Microchip Technology
4 */
5#include <linux/kernel.h>
6#include <linux/module.h>
7#include <linux/mii.h>
8#include <linux/ethtool.h>
9#include <linux/phy.h>
10#include <linux/microchipphy.h>
11#include <linux/delay.h>
12#include <linux/of.h>
13#include <dt-bindings/net/microchip-lan78xx.h>
14
15#define PHY_ID_LAN937X_TX 0x0007c190
16
17#define LAN937X_MODE_CTRL_STATUS_REG 0x11
18#define LAN937X_AUTOMDIX_EN BIT(7)
19#define LAN937X_MDI_MODE BIT(6)
20
21#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
22#define DRIVER_DESC "Microchip LAN88XX/LAN937X TX PHY driver"
23
24struct lan88xx_priv {
25 int chip_id;
26 int chip_rev;
27 __u32 wolopts;
28};
29
30static int lan88xx_read_page(struct phy_device *phydev)
31{
32 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
33}
34
35static int lan88xx_write_page(struct phy_device *phydev, int page)
36{
37 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
38}
39
40static int lan88xx_phy_config_intr(struct phy_device *phydev)
41{
42 int rc;
43
44 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
45 /* unmask all source and clear them before enable */
46 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
47 rc = phy_read(phydev, LAN88XX_INT_STS);
48 rc = phy_write(phydev, LAN88XX_INT_MASK,
49 LAN88XX_INT_MASK_MDINTPIN_EN_ |
50 LAN88XX_INT_MASK_LINK_CHANGE_);
51 } else {
52 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
53 if (rc)
54 return rc;
55
56 /* Ack interrupts after they have been disabled */
57 rc = phy_read(phydev, LAN88XX_INT_STS);
58 }
59
60 return rc < 0 ? rc : 0;
61}
62
63static irqreturn_t lan88xx_handle_interrupt(struct phy_device *phydev)
64{
65 int irq_status;
66
67 irq_status = phy_read(phydev, LAN88XX_INT_STS);
68 if (irq_status < 0) {
69 phy_error(phydev);
70 return IRQ_NONE;
71 }
72
73 if (!(irq_status & LAN88XX_INT_STS_LINK_CHANGE_))
74 return IRQ_NONE;
75
76 phy_trigger_machine(phydev);
77
78 return IRQ_HANDLED;
79}
80
81static int lan88xx_suspend(struct phy_device *phydev)
82{
83 struct lan88xx_priv *priv = phydev->priv;
84
85 /* do not power down PHY when WOL is enabled */
86 if (!priv->wolopts)
87 genphy_suspend(phydev);
88
89 return 0;
90}
91
92static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
93 u32 data)
94{
95 int val, save_page, ret = 0;
96 u16 buf;
97
98 /* Save current page */
99 save_page = phy_save_page(phydev);
100 if (save_page < 0) {
101 phydev_warn(phydev, "Failed to get current page\n");
102 goto err;
103 }
104
105 /* Switch to TR page */
106 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
107
108 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
109 (data & 0xFFFF));
110 if (ret < 0) {
111 phydev_warn(phydev, "Failed to write TR low data\n");
112 goto err;
113 }
114
115 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
116 (data & 0x00FF0000) >> 16);
117 if (ret < 0) {
118 phydev_warn(phydev, "Failed to write TR high data\n");
119 goto err;
120 }
121
122 /* Config control bits [15:13] of register */
123 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
124 buf |= 0x8000; /* Set [15] to Packet transmit */
125
126 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
127 if (ret < 0) {
128 phydev_warn(phydev, "Failed to write data in reg\n");
129 goto err;
130 }
131
132 usleep_range(1000, 2000);/* Wait for Data to be written */
133 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
134 if (!(val & 0x8000))
135 phydev_warn(phydev, "TR Register[0x%X] configuration failed\n",
136 regaddr);
137err:
138 return phy_restore_page(phydev, save_page, ret);
139}
140
141static void lan88xx_config_TR_regs(struct phy_device *phydev)
142{
143 int err;
144
145 /* Get access to Channel 0x1, Node 0xF , Register 0x01.
146 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
147 * MrvlTrFix1000Kp, MasterEnableTR bits.
148 */
149 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
150 if (err < 0)
151 phydev_warn(phydev, "Failed to Set Register[0x0F82]\n");
152
153 /* Get access to Channel b'10, Node b'1101, Register 0x06.
154 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
155 * SSTrKp1000Mas bits.
156 */
157 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
158 if (err < 0)
159 phydev_warn(phydev, "Failed to Set Register[0x168C]\n");
160
161 /* Get access to Channel b'10, Node b'1111, Register 0x11.
162 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
163 * bits
164 */
165 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
166 if (err < 0)
167 phydev_warn(phydev, "Failed to Set Register[0x17A2]\n");
168
169 /* Get access to Channel b'10, Node b'1101, Register 0x10.
170 * Write 24-bit value 0xEEFFDD to register. Setting
171 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
172 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
173 */
174 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
175 if (err < 0)
176 phydev_warn(phydev, "Failed to Set Register[0x16A0]\n");
177
178 /* Get access to Channel b'10, Node b'1101, Register 0x13.
179 * Write 24-bit value 0x071448 to register. Setting
180 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
181 */
182 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
183 if (err < 0)
184 phydev_warn(phydev, "Failed to Set Register[0x16A6]\n");
185
186 /* Get access to Channel b'10, Node b'1101, Register 0x12.
187 * Write 24-bit value 0x13132F to register. Setting
188 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
189 */
190 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
191 if (err < 0)
192 phydev_warn(phydev, "Failed to Set Register[0x16A4]\n");
193
194 /* Get access to Channel b'10, Node b'1101, Register 0x14.
195 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
196 * eee_TrKf_freeze_delay bits.
197 */
198 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
199 if (err < 0)
200 phydev_warn(phydev, "Failed to Set Register[0x16A8]\n");
201
202 /* Get access to Channel b'01, Node b'1111, Register 0x34.
203 * Write 24-bit value 0x91B06C to register. Setting
204 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
205 * FastMseSearchUpdGain1000 bits.
206 */
207 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
208 if (err < 0)
209 phydev_warn(phydev, "Failed to Set Register[0x0FE8]\n");
210
211 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
212 * Write 24-bit value 0xC0A028 to register. Setting
213 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
214 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
215 */
216 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
217 if (err < 0)
218 phydev_warn(phydev, "Failed to Set Register[0x0FFC]\n");
219
220 /* Get access to Channel b'01, Node b'1111, Register 0x35.
221 * Write 24-bit value 0x041600 to register. Setting
222 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
223 * FastMsePhChangeDelay1000 bits.
224 */
225 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
226 if (err < 0)
227 phydev_warn(phydev, "Failed to Set Register[0x0FEA]\n");
228
229 /* Get access to Channel b'10, Node b'1101, Register 0x03.
230 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
231 */
232 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
233 if (err < 0)
234 phydev_warn(phydev, "Failed to Set Register[0x1686]\n");
235}
236
237static int lan88xx_probe(struct phy_device *phydev)
238{
239 struct device *dev = &phydev->mdio.dev;
240 struct lan88xx_priv *priv;
241 u32 led_modes[4];
242 int len;
243
244 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
245 if (!priv)
246 return -ENOMEM;
247
248 priv->wolopts = 0;
249
250 len = of_property_read_variable_u32_array(dev->of_node,
251 "microchip,led-modes",
252 led_modes,
253 0,
254 ARRAY_SIZE(led_modes));
255 if (len >= 0) {
256 u32 reg = 0;
257 int i;
258
259 for (i = 0; i < len; i++) {
260 if (led_modes[i] > 15)
261 return -EINVAL;
262 reg |= led_modes[i] << (i * 4);
263 }
264 for (; i < ARRAY_SIZE(led_modes); i++)
265 reg |= LAN78XX_FORCE_LED_OFF << (i * 4);
266 (void)phy_write(phydev, LAN78XX_PHY_LED_MODE_SELECT, reg);
267 } else if (len == -EOVERFLOW) {
268 return -EINVAL;
269 }
270
271 /* these values can be used to identify internal PHY */
272 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
273 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
274
275 phydev->priv = priv;
276
277 return 0;
278}
279
280static void lan88xx_remove(struct phy_device *phydev)
281{
282 struct device *dev = &phydev->mdio.dev;
283 struct lan88xx_priv *priv = phydev->priv;
284
285 if (priv)
286 devm_kfree(dev, priv);
287}
288
289static int lan88xx_set_wol(struct phy_device *phydev,
290 struct ethtool_wolinfo *wol)
291{
292 struct lan88xx_priv *priv = phydev->priv;
293
294 priv->wolopts = wol->wolopts;
295
296 return 0;
297}
298
299static void lan88xx_set_mdix(struct phy_device *phydev)
300{
301 int buf;
302 int val;
303
304 switch (phydev->mdix_ctrl) {
305 case ETH_TP_MDI:
306 val = LAN88XX_EXT_MODE_CTRL_MDI_;
307 break;
308 case ETH_TP_MDI_X:
309 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
310 break;
311 case ETH_TP_MDI_AUTO:
312 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
313 break;
314 default:
315 return;
316 }
317
318 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
319 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
320 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
321 buf |= val;
322 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
323 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
324}
325
326static int lan88xx_config_init(struct phy_device *phydev)
327{
328 int val;
329
330 /*Zerodetect delay enable */
331 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
332 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
333 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
334
335 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
336 val);
337
338 /* Config DSP registers */
339 lan88xx_config_TR_regs(phydev);
340
341 return 0;
342}
343
344static int lan88xx_config_aneg(struct phy_device *phydev)
345{
346 lan88xx_set_mdix(phydev);
347
348 return genphy_config_aneg(phydev);
349}
350
351static void lan88xx_link_change_notify(struct phy_device *phydev)
352{
353 int temp;
354 int ret;
355
356 /* Reset PHY to ensure MII_LPA provides up-to-date information. This
357 * issue is reproducible only after parallel detection, as described
358 * in IEEE 802.3-2022, Section 28.2.3.1 ("Parallel detection function"),
359 * where the link partner does not support auto-negotiation.
360 */
361 if (phydev->state == PHY_NOLINK) {
362 ret = phy_init_hw(phydev);
363 if (ret < 0)
364 goto link_change_notify_failed;
365
366 ret = _phy_start_aneg(phydev);
367 if (ret < 0)
368 goto link_change_notify_failed;
369 }
370
371 /* At forced 100 F/H mode, chip may fail to set mode correctly
372 * when cable is switched between long(~50+m) and short one.
373 * As workaround, set to 10 before setting to 100
374 * at forced 100 F/H mode.
375 */
376 if (!phydev->autoneg && phydev->speed == 100) {
377 /* disable phy interrupt */
378 temp = phy_read(phydev, LAN88XX_INT_MASK);
379 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
380 phy_write(phydev, LAN88XX_INT_MASK, temp);
381
382 temp = phy_read(phydev, MII_BMCR);
383 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
384 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
385 temp |= BMCR_SPEED100;
386 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
387
388 /* clear pending interrupt generated while workaround */
389 temp = phy_read(phydev, LAN88XX_INT_STS);
390
391 /* enable phy interrupt back */
392 temp = phy_read(phydev, LAN88XX_INT_MASK);
393 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
394 phy_write(phydev, LAN88XX_INT_MASK, temp);
395 }
396
397 return;
398
399link_change_notify_failed:
400 phydev_err(phydev, "Link change process failed %pe\n", ERR_PTR(ret));
401}
402
403/**
404 * lan937x_tx_read_mdix_status - Read the MDIX status for the LAN937x TX PHY.
405 * @phydev: Pointer to the phy_device structure.
406 *
407 * This function reads the MDIX status of the LAN937x TX PHY and sets the
408 * mdix_ctrl and mdix fields of the phy_device structure accordingly.
409 * Note that MDIX status is not supported in AUTO mode, and will be set
410 * to invalid in such cases.
411 *
412 * Return: 0 on success, a negative error code on failure.
413 */
414static int lan937x_tx_read_mdix_status(struct phy_device *phydev)
415{
416 int ret;
417
418 ret = phy_read(phydev, LAN937X_MODE_CTRL_STATUS_REG);
419 if (ret < 0)
420 return ret;
421
422 if (ret & LAN937X_AUTOMDIX_EN) {
423 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
424 /* MDI/MDIX status is unknown */
425 phydev->mdix = ETH_TP_MDI_INVALID;
426 } else if (ret & LAN937X_MDI_MODE) {
427 phydev->mdix_ctrl = ETH_TP_MDI_X;
428 phydev->mdix = ETH_TP_MDI_X;
429 } else {
430 phydev->mdix_ctrl = ETH_TP_MDI;
431 phydev->mdix = ETH_TP_MDI;
432 }
433
434 return 0;
435}
436
437/**
438 * lan937x_tx_read_status - Read the status for the LAN937x TX PHY.
439 * @phydev: Pointer to the phy_device structure.
440 *
441 * This function reads the status of the LAN937x TX PHY and updates the
442 * phy_device structure accordingly.
443 *
444 * Return: 0 on success, a negative error code on failure.
445 */
446static int lan937x_tx_read_status(struct phy_device *phydev)
447{
448 int ret;
449
450 ret = genphy_read_status(phydev);
451 if (ret < 0)
452 return ret;
453
454 return lan937x_tx_read_mdix_status(phydev);
455}
456
457/**
458 * lan937x_tx_set_mdix - Set the MDIX mode for the LAN937x TX PHY.
459 * @phydev: Pointer to the phy_device structure.
460 *
461 * This function configures the MDIX mode of the LAN937x TX PHY based on the
462 * mdix_ctrl field of the phy_device structure. The MDIX mode can be set to
463 * MDI (straight-through), MDIX (crossover), or AUTO (auto-MDIX). If the mode
464 * is not recognized, it returns 0 without making any changes.
465 *
466 * Return: 0 on success, a negative error code on failure.
467 */
468static int lan937x_tx_set_mdix(struct phy_device *phydev)
469{
470 u16 val;
471
472 switch (phydev->mdix_ctrl) {
473 case ETH_TP_MDI:
474 val = 0;
475 break;
476 case ETH_TP_MDI_X:
477 val = LAN937X_MDI_MODE;
478 break;
479 case ETH_TP_MDI_AUTO:
480 val = LAN937X_AUTOMDIX_EN;
481 break;
482 default:
483 return 0;
484 }
485
486 return phy_modify(phydev, LAN937X_MODE_CTRL_STATUS_REG,
487 LAN937X_AUTOMDIX_EN | LAN937X_MDI_MODE, val);
488}
489
490/**
491 * lan937x_tx_config_aneg - Configure auto-negotiation and fixed modes for the
492 * LAN937x TX PHY.
493 * @phydev: Pointer to the phy_device structure.
494 *
495 * This function configures the MDIX mode for the LAN937x TX PHY and then
496 * proceeds to configure the auto-negotiation or fixed mode settings
497 * based on the phy_device structure.
498 *
499 * Return: 0 on success, a negative error code on failure.
500 */
501static int lan937x_tx_config_aneg(struct phy_device *phydev)
502{
503 int ret;
504
505 ret = lan937x_tx_set_mdix(phydev);
506 if (ret < 0)
507 return ret;
508
509 return genphy_config_aneg(phydev);
510}
511
512static struct phy_driver microchip_phy_driver[] = {
513{
514 .phy_id = 0x0007c132,
515 /* This mask (0xfffffff2) is to differentiate from
516 * LAN8742 (phy_id 0x0007c130 and 0x0007c131)
517 * and allows future phy_id revisions.
518 */
519 .phy_id_mask = 0xfffffff2,
520 .name = "Microchip LAN88xx",
521
522 /* PHY_GBIT_FEATURES */
523
524 .probe = lan88xx_probe,
525 .remove = lan88xx_remove,
526
527 .config_init = lan88xx_config_init,
528 .config_aneg = lan88xx_config_aneg,
529 .link_change_notify = lan88xx_link_change_notify,
530
531 .config_intr = lan88xx_phy_config_intr,
532 .handle_interrupt = lan88xx_handle_interrupt,
533
534 .suspend = lan88xx_suspend,
535 .resume = genphy_resume,
536 .set_wol = lan88xx_set_wol,
537 .read_page = lan88xx_read_page,
538 .write_page = lan88xx_write_page,
539},
540{
541 PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX),
542 .name = "Microchip LAN937x TX",
543 .suspend = genphy_suspend,
544 .resume = genphy_resume,
545 .config_aneg = lan937x_tx_config_aneg,
546 .read_status = lan937x_tx_read_status,
547} };
548
549module_phy_driver(microchip_phy_driver);
550
551static struct mdio_device_id __maybe_unused microchip_tbl[] = {
552 { 0x0007c132, 0xfffffff2 },
553 { PHY_ID_MATCH_MODEL(PHY_ID_LAN937X_TX) },
554 { }
555};
556
557MODULE_DEVICE_TABLE(mdio, microchip_tbl);
558
559MODULE_AUTHOR(DRIVER_AUTHOR);
560MODULE_DESCRIPTION(DRIVER_DESC);
561MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2015 Microchip Technology
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/mii.h>
20#include <linux/ethtool.h>
21#include <linux/phy.h>
22#include <linux/microchipphy.h>
23#include <linux/delay.h>
24
25#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
26#define DRIVER_DESC "Microchip LAN88XX PHY driver"
27
28struct lan88xx_priv {
29 int chip_id;
30 int chip_rev;
31 __u32 wolopts;
32};
33
34static int lan88xx_read_page(struct phy_device *phydev)
35{
36 return __phy_read(phydev, LAN88XX_EXT_PAGE_ACCESS);
37}
38
39static int lan88xx_write_page(struct phy_device *phydev, int page)
40{
41 return __phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, page);
42}
43
44static int lan88xx_phy_config_intr(struct phy_device *phydev)
45{
46 int rc;
47
48 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
49 /* unmask all source and clear them before enable */
50 rc = phy_write(phydev, LAN88XX_INT_MASK, 0x7FFF);
51 rc = phy_read(phydev, LAN88XX_INT_STS);
52 rc = phy_write(phydev, LAN88XX_INT_MASK,
53 LAN88XX_INT_MASK_MDINTPIN_EN_ |
54 LAN88XX_INT_MASK_LINK_CHANGE_);
55 } else {
56 rc = phy_write(phydev, LAN88XX_INT_MASK, 0);
57 }
58
59 return rc < 0 ? rc : 0;
60}
61
62static int lan88xx_phy_ack_interrupt(struct phy_device *phydev)
63{
64 int rc = phy_read(phydev, LAN88XX_INT_STS);
65
66 return rc < 0 ? rc : 0;
67}
68
69static int lan88xx_suspend(struct phy_device *phydev)
70{
71 struct lan88xx_priv *priv = phydev->priv;
72
73 /* do not power down PHY when WOL is enabled */
74 if (!priv->wolopts)
75 genphy_suspend(phydev);
76
77 return 0;
78}
79
80static int lan88xx_TR_reg_set(struct phy_device *phydev, u16 regaddr,
81 u32 data)
82{
83 int val, save_page, ret = 0;
84 u16 buf;
85
86 /* Save current page */
87 save_page = phy_save_page(phydev);
88 if (save_page < 0) {
89 pr_warn("Failed to get current page\n");
90 goto err;
91 }
92
93 /* Switch to TR page */
94 lan88xx_write_page(phydev, LAN88XX_EXT_PAGE_ACCESS_TR);
95
96 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_LOW_DATA,
97 (data & 0xFFFF));
98 if (ret < 0) {
99 pr_warn("Failed to write TR low data\n");
100 goto err;
101 }
102
103 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_HIGH_DATA,
104 (data & 0x00FF0000) >> 16);
105 if (ret < 0) {
106 pr_warn("Failed to write TR high data\n");
107 goto err;
108 }
109
110 /* Config control bits [15:13] of register */
111 buf = (regaddr & ~(0x3 << 13));/* Clr [14:13] to write data in reg */
112 buf |= 0x8000; /* Set [15] to Packet transmit */
113
114 ret = __phy_write(phydev, LAN88XX_EXT_PAGE_TR_CR, buf);
115 if (ret < 0) {
116 pr_warn("Failed to write data in reg\n");
117 goto err;
118 }
119
120 usleep_range(1000, 2000);/* Wait for Data to be written */
121 val = __phy_read(phydev, LAN88XX_EXT_PAGE_TR_CR);
122 if (!(val & 0x8000))
123 pr_warn("TR Register[0x%X] configuration failed\n", regaddr);
124err:
125 return phy_restore_page(phydev, save_page, ret);
126}
127
128static void lan88xx_config_TR_regs(struct phy_device *phydev)
129{
130 int err;
131
132 /* Get access to Channel 0x1, Node 0xF , Register 0x01.
133 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,
134 * MrvlTrFix1000Kp, MasterEnableTR bits.
135 */
136 err = lan88xx_TR_reg_set(phydev, 0x0F82, 0x12B00A);
137 if (err < 0)
138 pr_warn("Failed to Set Register[0x0F82]\n");
139
140 /* Get access to Channel b'10, Node b'1101, Register 0x06.
141 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,
142 * SSTrKp1000Mas bits.
143 */
144 err = lan88xx_TR_reg_set(phydev, 0x168C, 0xD2C46F);
145 if (err < 0)
146 pr_warn("Failed to Set Register[0x168C]\n");
147
148 /* Get access to Channel b'10, Node b'1111, Register 0x11.
149 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh
150 * bits
151 */
152 err = lan88xx_TR_reg_set(phydev, 0x17A2, 0x620);
153 if (err < 0)
154 pr_warn("Failed to Set Register[0x17A2]\n");
155
156 /* Get access to Channel b'10, Node b'1101, Register 0x10.
157 * Write 24-bit value 0xEEFFDD to register. Setting
158 * eee_TrKp1Long_1000, eee_TrKp2Long_1000, eee_TrKp3Long_1000,
159 * eee_TrKp1Short_1000,eee_TrKp2Short_1000, eee_TrKp3Short_1000 bits.
160 */
161 err = lan88xx_TR_reg_set(phydev, 0x16A0, 0xEEFFDD);
162 if (err < 0)
163 pr_warn("Failed to Set Register[0x16A0]\n");
164
165 /* Get access to Channel b'10, Node b'1101, Register 0x13.
166 * Write 24-bit value 0x071448 to register. Setting
167 * slv_lpi_tr_tmr_val1, slv_lpi_tr_tmr_val2 bits.
168 */
169 err = lan88xx_TR_reg_set(phydev, 0x16A6, 0x071448);
170 if (err < 0)
171 pr_warn("Failed to Set Register[0x16A6]\n");
172
173 /* Get access to Channel b'10, Node b'1101, Register 0x12.
174 * Write 24-bit value 0x13132F to register. Setting
175 * slv_sigdet_timer_val1, slv_sigdet_timer_val2 bits.
176 */
177 err = lan88xx_TR_reg_set(phydev, 0x16A4, 0x13132F);
178 if (err < 0)
179 pr_warn("Failed to Set Register[0x16A4]\n");
180
181 /* Get access to Channel b'10, Node b'1101, Register 0x14.
182 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,
183 * eee_TrKf_freeze_delay bits.
184 */
185 err = lan88xx_TR_reg_set(phydev, 0x16A8, 0x0);
186 if (err < 0)
187 pr_warn("Failed to Set Register[0x16A8]\n");
188
189 /* Get access to Channel b'01, Node b'1111, Register 0x34.
190 * Write 24-bit value 0x91B06C to register. Setting
191 * FastMseSearchThreshLong1000, FastMseSearchThreshShort1000,
192 * FastMseSearchUpdGain1000 bits.
193 */
194 err = lan88xx_TR_reg_set(phydev, 0x0FE8, 0x91B06C);
195 if (err < 0)
196 pr_warn("Failed to Set Register[0x0FE8]\n");
197
198 /* Get access to Channel b'01, Node b'1111, Register 0x3E.
199 * Write 24-bit value 0xC0A028 to register. Setting
200 * FastMseKp2ThreshLong1000, FastMseKp2ThreshShort1000,
201 * FastMseKp2UpdGain1000, FastMseKp2ExitEn1000 bits.
202 */
203 err = lan88xx_TR_reg_set(phydev, 0x0FFC, 0xC0A028);
204 if (err < 0)
205 pr_warn("Failed to Set Register[0x0FFC]\n");
206
207 /* Get access to Channel b'01, Node b'1111, Register 0x35.
208 * Write 24-bit value 0x041600 to register. Setting
209 * FastMseSearchPhShNum1000, FastMseSearchClksPerPh1000,
210 * FastMsePhChangeDelay1000 bits.
211 */
212 err = lan88xx_TR_reg_set(phydev, 0x0FEA, 0x041600);
213 if (err < 0)
214 pr_warn("Failed to Set Register[0x0FEA]\n");
215
216 /* Get access to Channel b'10, Node b'1101, Register 0x03.
217 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.
218 */
219 err = lan88xx_TR_reg_set(phydev, 0x1686, 0x000004);
220 if (err < 0)
221 pr_warn("Failed to Set Register[0x1686]\n");
222}
223
224static int lan88xx_probe(struct phy_device *phydev)
225{
226 struct device *dev = &phydev->mdio.dev;
227 struct lan88xx_priv *priv;
228
229 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
230 if (!priv)
231 return -ENOMEM;
232
233 priv->wolopts = 0;
234
235 /* these values can be used to identify internal PHY */
236 priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);
237 priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);
238
239 phydev->priv = priv;
240
241 return 0;
242}
243
244static void lan88xx_remove(struct phy_device *phydev)
245{
246 struct device *dev = &phydev->mdio.dev;
247 struct lan88xx_priv *priv = phydev->priv;
248
249 if (priv)
250 devm_kfree(dev, priv);
251}
252
253static int lan88xx_set_wol(struct phy_device *phydev,
254 struct ethtool_wolinfo *wol)
255{
256 struct lan88xx_priv *priv = phydev->priv;
257
258 priv->wolopts = wol->wolopts;
259
260 return 0;
261}
262
263static void lan88xx_set_mdix(struct phy_device *phydev)
264{
265 int buf;
266 int val;
267
268 switch (phydev->mdix_ctrl) {
269 case ETH_TP_MDI:
270 val = LAN88XX_EXT_MODE_CTRL_MDI_;
271 break;
272 case ETH_TP_MDI_X:
273 val = LAN88XX_EXT_MODE_CTRL_MDI_X_;
274 break;
275 case ETH_TP_MDI_AUTO:
276 val = LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_;
277 break;
278 default:
279 return;
280 }
281
282 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_1);
283 buf = phy_read(phydev, LAN88XX_EXT_MODE_CTRL);
284 buf &= ~LAN88XX_EXT_MODE_CTRL_MDIX_MASK_;
285 buf |= val;
286 phy_write(phydev, LAN88XX_EXT_MODE_CTRL, buf);
287 phy_write(phydev, LAN88XX_EXT_PAGE_ACCESS, LAN88XX_EXT_PAGE_SPACE_0);
288}
289
290static int lan88xx_config_init(struct phy_device *phydev)
291{
292 int val;
293
294 genphy_config_init(phydev);
295 /*Zerodetect delay enable */
296 val = phy_read_mmd(phydev, MDIO_MMD_PCS,
297 PHY_ARDENNES_MMD_DEV_3_PHY_CFG);
298 val |= PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_;
299
300 phy_write_mmd(phydev, MDIO_MMD_PCS, PHY_ARDENNES_MMD_DEV_3_PHY_CFG,
301 val);
302
303 /* Config DSP registers */
304 lan88xx_config_TR_regs(phydev);
305
306 return 0;
307}
308
309static int lan88xx_config_aneg(struct phy_device *phydev)
310{
311 lan88xx_set_mdix(phydev);
312
313 return genphy_config_aneg(phydev);
314}
315
316static struct phy_driver microchip_phy_driver[] = {
317{
318 .phy_id = 0x0007c130,
319 .phy_id_mask = 0xfffffff0,
320 .name = "Microchip LAN88xx",
321
322 .features = PHY_GBIT_FEATURES,
323 .flags = PHY_HAS_INTERRUPT,
324
325 .probe = lan88xx_probe,
326 .remove = lan88xx_remove,
327
328 .config_init = lan88xx_config_init,
329 .config_aneg = lan88xx_config_aneg,
330
331 .ack_interrupt = lan88xx_phy_ack_interrupt,
332 .config_intr = lan88xx_phy_config_intr,
333
334 .suspend = lan88xx_suspend,
335 .resume = genphy_resume,
336 .set_wol = lan88xx_set_wol,
337 .read_page = lan88xx_read_page,
338 .write_page = lan88xx_write_page,
339} };
340
341module_phy_driver(microchip_phy_driver);
342
343static struct mdio_device_id __maybe_unused microchip_tbl[] = {
344 { 0x0007c130, 0xfffffff0 },
345 { }
346};
347
348MODULE_DEVICE_TABLE(mdio, microchip_tbl);
349
350MODULE_AUTHOR(DRIVER_AUTHOR);
351MODULE_DESCRIPTION(DRIVER_DESC);
352MODULE_LICENSE("GPL");