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1/* ----------------------------------------------------------------------------
2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47-------------------------------------------------------------------------------
48Driver Notes and Issues
49-------------------------------------------------------------------------------
50
511. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
552. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
603. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
634. There is a bad slow-down problem in this driver.
64
655. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68-------------------------------------------------------------------------------
69History
70-------------------------------------------------------------------------------
71Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
9695/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
10095/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
10595/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
10995/05/10 rpao V0.07 Statistics.
11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112---------------------------------------------------------------------------- */
113
114#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
115
116#define DRV_NAME "nmclan_cs"
117
118/* ----------------------------------------------------------------------------
119Conditional Compilation Options
120---------------------------------------------------------------------------- */
121
122#define MULTI_TX 0
123#define RESET_ON_TIMEOUT 1
124#define TX_INTERRUPTABLE 1
125#define RESET_XILINX 0
126
127/* ----------------------------------------------------------------------------
128Include Files
129---------------------------------------------------------------------------- */
130
131#include <linux/module.h>
132#include <linux/kernel.h>
133#include <linux/ptrace.h>
134#include <linux/slab.h>
135#include <linux/string.h>
136#include <linux/timer.h>
137#include <linux/interrupt.h>
138#include <linux/in.h>
139#include <linux/delay.h>
140#include <linux/ethtool.h>
141#include <linux/netdevice.h>
142#include <linux/etherdevice.h>
143#include <linux/skbuff.h>
144#include <linux/if_arp.h>
145#include <linux/ioport.h>
146#include <linux/bitops.h>
147
148#include <pcmcia/cisreg.h>
149#include <pcmcia/cistpl.h>
150#include <pcmcia/ds.h>
151
152#include <linux/uaccess.h>
153#include <asm/io.h>
154
155/* ----------------------------------------------------------------------------
156Defines
157---------------------------------------------------------------------------- */
158
159#define MACE_LADRF_LEN 8
160 /* 8 bytes in Logical Address Filter */
161
162/* Loop Control Defines */
163#define MACE_MAX_IR_ITERATIONS 10
164#define MACE_MAX_RX_ITERATIONS 12
165 /*
166 TBD: Dean brought this up, and I assumed the hardware would
167 handle it:
168
169 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
170 non-zero when the isr exits. We may not get another interrupt
171 to process the remaining packets for some time.
172 */
173
174/*
175The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
176which manages the interface between the MACE and the PCMCIA bus. It
177also includes buffer management for the 32K x 8 SRAM to control up to
178four transmit and 12 receive frames at a time.
179*/
180#define AM2150_MAX_TX_FRAMES 4
181#define AM2150_MAX_RX_FRAMES 12
182
183/* Am2150 Ethernet Card I/O Mapping */
184#define AM2150_RCV 0x00
185#define AM2150_XMT 0x04
186#define AM2150_XMT_SKIP 0x09
187#define AM2150_RCV_NEXT 0x0A
188#define AM2150_RCV_FRAME_COUNT 0x0B
189#define AM2150_MACE_BANK 0x0C
190#define AM2150_MACE_BASE 0x10
191
192/* MACE Registers */
193#define MACE_RCVFIFO 0
194#define MACE_XMTFIFO 1
195#define MACE_XMTFC 2
196#define MACE_XMTFS 3
197#define MACE_XMTRC 4
198#define MACE_RCVFC 5
199#define MACE_RCVFS 6
200#define MACE_FIFOFC 7
201#define MACE_IR 8
202#define MACE_IMR 9
203#define MACE_PR 10
204#define MACE_BIUCC 11
205#define MACE_FIFOCC 12
206#define MACE_MACCC 13
207#define MACE_PLSCC 14
208#define MACE_PHYCC 15
209#define MACE_CHIPIDL 16
210#define MACE_CHIPIDH 17
211#define MACE_IAC 18
212/* Reserved */
213#define MACE_LADRF 20
214#define MACE_PADR 21
215/* Reserved */
216/* Reserved */
217#define MACE_MPC 24
218/* Reserved */
219#define MACE_RNTPC 26
220#define MACE_RCVCC 27
221/* Reserved */
222#define MACE_UTR 29
223#define MACE_RTR1 30
224#define MACE_RTR2 31
225
226/* MACE Bit Masks */
227#define MACE_XMTRC_EXDEF 0x80
228#define MACE_XMTRC_XMTRC 0x0F
229
230#define MACE_XMTFS_XMTSV 0x80
231#define MACE_XMTFS_UFLO 0x40
232#define MACE_XMTFS_LCOL 0x20
233#define MACE_XMTFS_MORE 0x10
234#define MACE_XMTFS_ONE 0x08
235#define MACE_XMTFS_DEFER 0x04
236#define MACE_XMTFS_LCAR 0x02
237#define MACE_XMTFS_RTRY 0x01
238
239#define MACE_RCVFS_RCVSTS 0xF000
240#define MACE_RCVFS_OFLO 0x8000
241#define MACE_RCVFS_CLSN 0x4000
242#define MACE_RCVFS_FRAM 0x2000
243#define MACE_RCVFS_FCS 0x1000
244
245#define MACE_FIFOFC_RCVFC 0xF0
246#define MACE_FIFOFC_XMTFC 0x0F
247
248#define MACE_IR_JAB 0x80
249#define MACE_IR_BABL 0x40
250#define MACE_IR_CERR 0x20
251#define MACE_IR_RCVCCO 0x10
252#define MACE_IR_RNTPCO 0x08
253#define MACE_IR_MPCO 0x04
254#define MACE_IR_RCVINT 0x02
255#define MACE_IR_XMTINT 0x01
256
257#define MACE_MACCC_PROM 0x80
258#define MACE_MACCC_DXMT2PD 0x40
259#define MACE_MACCC_EMBA 0x20
260#define MACE_MACCC_RESERVED 0x10
261#define MACE_MACCC_DRCVPA 0x08
262#define MACE_MACCC_DRCVBC 0x04
263#define MACE_MACCC_ENXMT 0x02
264#define MACE_MACCC_ENRCV 0x01
265
266#define MACE_PHYCC_LNKFL 0x80
267#define MACE_PHYCC_DLNKTST 0x40
268#define MACE_PHYCC_REVPOL 0x20
269#define MACE_PHYCC_DAPC 0x10
270#define MACE_PHYCC_LRT 0x08
271#define MACE_PHYCC_ASEL 0x04
272#define MACE_PHYCC_RWAKE 0x02
273#define MACE_PHYCC_AWAKE 0x01
274
275#define MACE_IAC_ADDRCHG 0x80
276#define MACE_IAC_PHYADDR 0x04
277#define MACE_IAC_LOGADDR 0x02
278
279#define MACE_UTR_RTRE 0x80
280#define MACE_UTR_RTRD 0x40
281#define MACE_UTR_RPA 0x20
282#define MACE_UTR_FCOLL 0x10
283#define MACE_UTR_RCVFCSE 0x08
284#define MACE_UTR_LOOP_INCL_MENDEC 0x06
285#define MACE_UTR_LOOP_NO_MENDEC 0x04
286#define MACE_UTR_LOOP_EXTERNAL 0x02
287#define MACE_UTR_LOOP_NONE 0x00
288#define MACE_UTR_RESERVED 0x01
289
290/* Switch MACE register bank (only 0 and 1 are valid) */
291#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
292
293#define MACE_IMR_DEFAULT \
294 (0xFF - \
295 ( \
296 MACE_IR_CERR | \
297 MACE_IR_RCVCCO | \
298 MACE_IR_RNTPCO | \
299 MACE_IR_MPCO | \
300 MACE_IR_RCVINT | \
301 MACE_IR_XMTINT \
302 ) \
303 )
304#undef MACE_IMR_DEFAULT
305#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
306
307#define TX_TIMEOUT ((400*HZ)/1000)
308
309/* ----------------------------------------------------------------------------
310Type Definitions
311---------------------------------------------------------------------------- */
312
313typedef struct _mace_statistics {
314 /* MACE_XMTFS */
315 int xmtsv;
316 int uflo;
317 int lcol;
318 int more;
319 int one;
320 int defer;
321 int lcar;
322 int rtry;
323
324 /* MACE_XMTRC */
325 int exdef;
326 int xmtrc;
327
328 /* RFS1--Receive Status (RCVSTS) */
329 int oflo;
330 int clsn;
331 int fram;
332 int fcs;
333
334 /* RFS2--Runt Packet Count (RNTPC) */
335 int rfs_rntpc;
336
337 /* RFS3--Receive Collision Count (RCVCC) */
338 int rfs_rcvcc;
339
340 /* MACE_IR */
341 int jab;
342 int babl;
343 int cerr;
344 int rcvcco;
345 int rntpco;
346 int mpco;
347
348 /* MACE_MPC */
349 int mpc;
350
351 /* MACE_RNTPC */
352 int rntpc;
353
354 /* MACE_RCVCC */
355 int rcvcc;
356} mace_statistics;
357
358typedef struct _mace_private {
359 struct pcmcia_device *p_dev;
360 mace_statistics mace_stats; /* MACE chip statistics counters */
361
362 /* restore_multicast_list() state variables */
363 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
364 int multicast_num_addrs;
365
366 char tx_free_frames; /* Number of free transmit frame buffers */
367 char tx_irq_disabled; /* MACE TX interrupt disabled */
368
369 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
370} mace_private;
371
372/* ----------------------------------------------------------------------------
373Private Global Variables
374---------------------------------------------------------------------------- */
375
376static const char *if_names[]={
377 "Auto", "10baseT", "BNC",
378};
379
380/* ----------------------------------------------------------------------------
381Parameters
382 These are the parameters that can be set during loading with
383 'insmod'.
384---------------------------------------------------------------------------- */
385
386MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
387MODULE_LICENSE("GPL");
388
389#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
390
391/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
392INT_MODULE_PARM(if_port, 0);
393
394
395/* ----------------------------------------------------------------------------
396Function Prototypes
397---------------------------------------------------------------------------- */
398
399static int nmclan_config(struct pcmcia_device *link);
400static void nmclan_release(struct pcmcia_device *link);
401
402static void nmclan_reset(struct net_device *dev);
403static int mace_config(struct net_device *dev, struct ifmap *map);
404static int mace_open(struct net_device *dev);
405static int mace_close(struct net_device *dev);
406static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
407 struct net_device *dev);
408static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue);
409static irqreturn_t mace_interrupt(int irq, void *dev_id);
410static struct net_device_stats *mace_get_stats(struct net_device *dev);
411static int mace_rx(struct net_device *dev, unsigned char RxCnt);
412static void restore_multicast_list(struct net_device *dev);
413static void set_multicast_list(struct net_device *dev);
414static const struct ethtool_ops netdev_ethtool_ops;
415
416
417static void nmclan_detach(struct pcmcia_device *p_dev);
418
419static const struct net_device_ops mace_netdev_ops = {
420 .ndo_open = mace_open,
421 .ndo_stop = mace_close,
422 .ndo_start_xmit = mace_start_xmit,
423 .ndo_tx_timeout = mace_tx_timeout,
424 .ndo_set_config = mace_config,
425 .ndo_get_stats = mace_get_stats,
426 .ndo_set_rx_mode = set_multicast_list,
427 .ndo_set_mac_address = eth_mac_addr,
428 .ndo_validate_addr = eth_validate_addr,
429};
430
431static int nmclan_probe(struct pcmcia_device *link)
432{
433 mace_private *lp;
434 struct net_device *dev;
435
436 dev_dbg(&link->dev, "nmclan_attach()\n");
437
438 /* Create new ethernet device */
439 dev = alloc_etherdev(sizeof(mace_private));
440 if (!dev)
441 return -ENOMEM;
442 lp = netdev_priv(dev);
443 lp->p_dev = link;
444 link->priv = dev;
445
446 spin_lock_init(&lp->bank_lock);
447 link->resource[0]->end = 32;
448 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
449 link->config_flags |= CONF_ENABLE_IRQ;
450 link->config_index = 1;
451 link->config_regs = PRESENT_OPTION;
452
453 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
454
455 dev->netdev_ops = &mace_netdev_ops;
456 dev->ethtool_ops = &netdev_ethtool_ops;
457 dev->watchdog_timeo = TX_TIMEOUT;
458
459 return nmclan_config(link);
460} /* nmclan_attach */
461
462static void nmclan_detach(struct pcmcia_device *link)
463{
464 struct net_device *dev = link->priv;
465
466 dev_dbg(&link->dev, "nmclan_detach\n");
467
468 unregister_netdev(dev);
469
470 nmclan_release(link);
471
472 free_netdev(dev);
473} /* nmclan_detach */
474
475/* ----------------------------------------------------------------------------
476mace_read
477 Reads a MACE register. This is bank independent; however, the
478 caller must ensure that this call is not interruptable. We are
479 assuming that during normal operation, the MACE is always in
480 bank 0.
481---------------------------------------------------------------------------- */
482static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
483{
484 int data = 0xFF;
485 unsigned long flags;
486
487 switch (reg >> 4) {
488 case 0: /* register 0-15 */
489 data = inb(ioaddr + AM2150_MACE_BASE + reg);
490 break;
491 case 1: /* register 16-31 */
492 spin_lock_irqsave(&lp->bank_lock, flags);
493 MACEBANK(1);
494 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
495 MACEBANK(0);
496 spin_unlock_irqrestore(&lp->bank_lock, flags);
497 break;
498 }
499 return data & 0xFF;
500} /* mace_read */
501
502/* ----------------------------------------------------------------------------
503mace_write
504 Writes to a MACE register. This is bank independent; however,
505 the caller must ensure that this call is not interruptable. We
506 are assuming that during normal operation, the MACE is always in
507 bank 0.
508---------------------------------------------------------------------------- */
509static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
510 int data)
511{
512 unsigned long flags;
513
514 switch (reg >> 4) {
515 case 0: /* register 0-15 */
516 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
517 break;
518 case 1: /* register 16-31 */
519 spin_lock_irqsave(&lp->bank_lock, flags);
520 MACEBANK(1);
521 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
522 MACEBANK(0);
523 spin_unlock_irqrestore(&lp->bank_lock, flags);
524 break;
525 }
526} /* mace_write */
527
528/* ----------------------------------------------------------------------------
529mace_init
530 Resets the MACE chip.
531---------------------------------------------------------------------------- */
532static int mace_init(mace_private *lp, unsigned int ioaddr,
533 const char *enet_addr)
534{
535 int i;
536 int ct = 0;
537
538 /* MACE Software reset */
539 mace_write(lp, ioaddr, MACE_BIUCC, 1);
540 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
541 /* Wait for reset bit to be cleared automatically after <= 200ns */;
542 if(++ct > 500)
543 {
544 pr_err("reset failed, card removed?\n");
545 return -1;
546 }
547 udelay(1);
548 }
549 mace_write(lp, ioaddr, MACE_BIUCC, 0);
550
551 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
552 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
553
554 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
555 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
556
557 /*
558 * Bit 2-1 PORTSEL[1-0] Port Select.
559 * 00 AUI/10Base-2
560 * 01 10Base-T
561 * 10 DAI Port (reserved in Am2150)
562 * 11 GPSI
563 * For this card, only the first two are valid.
564 * So, PLSCC should be set to
565 * 0x00 for 10Base-2
566 * 0x02 for 10Base-T
567 * Or just set ASEL in PHYCC below!
568 */
569 switch (if_port) {
570 case 1:
571 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
572 break;
573 case 2:
574 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
575 break;
576 default:
577 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
578 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
579 and the MACE device will automatically select the operating media
580 interface port. */
581 break;
582 }
583
584 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
585 /* Poll ADDRCHG bit */
586 ct = 0;
587 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
588 {
589 if(++ ct > 500)
590 {
591 pr_err("ADDRCHG timeout, card removed?\n");
592 return -1;
593 }
594 }
595 /* Set PADR register */
596 for (i = 0; i < ETH_ALEN; i++)
597 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
598
599 /* MAC Configuration Control Register should be written last */
600 /* Let set_multicast_list set this. */
601 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
602 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
603 return 0;
604} /* mace_init */
605
606static int nmclan_config(struct pcmcia_device *link)
607{
608 struct net_device *dev = link->priv;
609 mace_private *lp = netdev_priv(dev);
610 u8 *buf;
611 size_t len;
612 int i, ret;
613 unsigned int ioaddr;
614
615 dev_dbg(&link->dev, "nmclan_config\n");
616
617 link->io_lines = 5;
618 ret = pcmcia_request_io(link);
619 if (ret)
620 goto failed;
621 ret = pcmcia_request_irq(link, mace_interrupt);
622 if (ret)
623 goto failed;
624 ret = pcmcia_enable_device(link);
625 if (ret)
626 goto failed;
627
628 dev->irq = link->irq;
629 dev->base_addr = link->resource[0]->start;
630
631 ioaddr = dev->base_addr;
632
633 /* Read the ethernet address from the CIS. */
634 len = pcmcia_get_tuple(link, 0x80, &buf);
635 if (!buf || len < ETH_ALEN) {
636 kfree(buf);
637 goto failed;
638 }
639 eth_hw_addr_set(dev, buf);
640 kfree(buf);
641
642 /* Verify configuration by reading the MACE ID. */
643 {
644 char sig[2];
645
646 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
647 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
648 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
649 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
650 sig[0], sig[1]);
651 } else {
652 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
653 sig[0], sig[1]);
654 goto failed;
655 }
656 }
657
658 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
659 goto failed;
660
661 /* The if_port symbol can be set when the module is loaded */
662 if (if_port <= 2)
663 dev->if_port = if_port;
664 else
665 pr_notice("invalid if_port requested\n");
666
667 SET_NETDEV_DEV(dev, &link->dev);
668
669 i = register_netdev(dev);
670 if (i != 0) {
671 pr_notice("register_netdev() failed\n");
672 goto failed;
673 }
674
675 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
676 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
677 return 0;
678
679failed:
680 nmclan_release(link);
681 return -ENODEV;
682} /* nmclan_config */
683
684static void nmclan_release(struct pcmcia_device *link)
685{
686 dev_dbg(&link->dev, "nmclan_release\n");
687 pcmcia_disable_device(link);
688}
689
690static int nmclan_suspend(struct pcmcia_device *link)
691{
692 struct net_device *dev = link->priv;
693
694 if (link->open)
695 netif_device_detach(dev);
696
697 return 0;
698}
699
700static int nmclan_resume(struct pcmcia_device *link)
701{
702 struct net_device *dev = link->priv;
703
704 if (link->open) {
705 nmclan_reset(dev);
706 netif_device_attach(dev);
707 }
708
709 return 0;
710}
711
712
713/* ----------------------------------------------------------------------------
714nmclan_reset
715 Reset and restore all of the Xilinx and MACE registers.
716---------------------------------------------------------------------------- */
717static void nmclan_reset(struct net_device *dev)
718{
719 mace_private *lp = netdev_priv(dev);
720
721#if RESET_XILINX
722 struct pcmcia_device *link = &lp->link;
723 u8 OrigCorValue;
724
725 /* Save original COR value */
726 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
727
728 /* Reset Xilinx */
729 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
730 OrigCorValue);
731 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
732 /* Need to wait for 20 ms for PCMCIA to finish reset. */
733
734 /* Restore original COR configuration index */
735 pcmcia_write_config_byte(link, CISREG_COR,
736 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
737 /* Xilinx is now completely reset along with the MACE chip. */
738 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
739
740#endif /* #if RESET_XILINX */
741
742 /* Xilinx is now completely reset along with the MACE chip. */
743 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
744
745 /* Reinitialize the MACE chip for operation. */
746 mace_init(lp, dev->base_addr, dev->dev_addr);
747 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
748
749 /* Restore the multicast list and enable TX and RX. */
750 restore_multicast_list(dev);
751} /* nmclan_reset */
752
753/* ----------------------------------------------------------------------------
754mace_config
755 [Someone tell me what this is supposed to do? Is if_port a defined
756 standard? If so, there should be defines to indicate 1=10Base-T,
757 2=10Base-2, etc. including limited automatic detection.]
758---------------------------------------------------------------------------- */
759static int mace_config(struct net_device *dev, struct ifmap *map)
760{
761 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
762 if (map->port <= 2) {
763 WRITE_ONCE(dev->if_port, map->port);
764 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
765 } else
766 return -EINVAL;
767 }
768 return 0;
769} /* mace_config */
770
771/* ----------------------------------------------------------------------------
772mace_open
773 Open device driver.
774---------------------------------------------------------------------------- */
775static int mace_open(struct net_device *dev)
776{
777 unsigned int ioaddr = dev->base_addr;
778 mace_private *lp = netdev_priv(dev);
779 struct pcmcia_device *link = lp->p_dev;
780
781 if (!pcmcia_dev_present(link))
782 return -ENODEV;
783
784 link->open++;
785
786 MACEBANK(0);
787
788 netif_start_queue(dev);
789 nmclan_reset(dev);
790
791 return 0; /* Always succeed */
792} /* mace_open */
793
794/* ----------------------------------------------------------------------------
795mace_close
796 Closes device driver.
797---------------------------------------------------------------------------- */
798static int mace_close(struct net_device *dev)
799{
800 unsigned int ioaddr = dev->base_addr;
801 mace_private *lp = netdev_priv(dev);
802 struct pcmcia_device *link = lp->p_dev;
803
804 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
805
806 /* Mask off all interrupts from the MACE chip. */
807 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
808
809 link->open--;
810 netif_stop_queue(dev);
811
812 return 0;
813} /* mace_close */
814
815static void netdev_get_drvinfo(struct net_device *dev,
816 struct ethtool_drvinfo *info)
817{
818 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
819 snprintf(info->bus_info, sizeof(info->bus_info),
820 "PCMCIA 0x%lx", dev->base_addr);
821}
822
823static const struct ethtool_ops netdev_ethtool_ops = {
824 .get_drvinfo = netdev_get_drvinfo,
825};
826
827/* ----------------------------------------------------------------------------
828mace_start_xmit
829 This routine begins the packet transmit function. When completed,
830 it will generate a transmit interrupt.
831
832 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
833 returns 0, the "packet is now solely the responsibility of the
834 driver." If _start_xmit returns non-zero, the "transmission
835 failed, put skb back into a list."
836---------------------------------------------------------------------------- */
837
838static void mace_tx_timeout(struct net_device *dev, unsigned int txqueue)
839{
840 mace_private *lp = netdev_priv(dev);
841 struct pcmcia_device *link = lp->p_dev;
842
843 netdev_notice(dev, "transmit timed out -- ");
844#if RESET_ON_TIMEOUT
845 pr_cont("resetting card\n");
846 pcmcia_reset_card(link->socket);
847#else /* #if RESET_ON_TIMEOUT */
848 pr_cont("NOT resetting card\n");
849#endif /* #if RESET_ON_TIMEOUT */
850 netif_trans_update(dev); /* prevent tx timeout */
851 netif_wake_queue(dev);
852}
853
854static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
855 struct net_device *dev)
856{
857 mace_private *lp = netdev_priv(dev);
858 unsigned int ioaddr = dev->base_addr;
859
860 netif_stop_queue(dev);
861
862 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
863 dev->name, (long)skb->len);
864
865#if (!TX_INTERRUPTABLE)
866 /* Disable MACE TX interrupts. */
867 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
868 ioaddr + AM2150_MACE_BASE + MACE_IMR);
869 lp->tx_irq_disabled=1;
870#endif /* #if (!TX_INTERRUPTABLE) */
871
872 {
873 /* This block must not be interrupted by another transmit request!
874 mace_tx_timeout will take care of timer-based retransmissions from
875 the upper layers. The interrupt handler is guaranteed never to
876 service a transmit interrupt while we are in here.
877 */
878
879 dev->stats.tx_bytes += skb->len;
880 lp->tx_free_frames--;
881
882 /* WARNING: Write the _exact_ number of bytes written in the header! */
883 /* Put out the word header [must be an outw()] . . . */
884 outw(skb->len, ioaddr + AM2150_XMT);
885 /* . . . and the packet [may be any combination of outw() and outb()] */
886 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
887 if (skb->len & 1) {
888 /* Odd byte transfer */
889 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
890 }
891
892#if MULTI_TX
893 if (lp->tx_free_frames > 0)
894 netif_start_queue(dev);
895#endif /* #if MULTI_TX */
896 }
897
898#if (!TX_INTERRUPTABLE)
899 /* Re-enable MACE TX interrupts. */
900 lp->tx_irq_disabled=0;
901 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
902#endif /* #if (!TX_INTERRUPTABLE) */
903
904 dev_kfree_skb(skb);
905
906 return NETDEV_TX_OK;
907} /* mace_start_xmit */
908
909/* ----------------------------------------------------------------------------
910mace_interrupt
911 The interrupt handler.
912---------------------------------------------------------------------------- */
913static irqreturn_t mace_interrupt(int irq, void *dev_id)
914{
915 struct net_device *dev = (struct net_device *) dev_id;
916 mace_private *lp = netdev_priv(dev);
917 unsigned int ioaddr;
918 int status;
919 int IntrCnt = MACE_MAX_IR_ITERATIONS;
920
921 if (!dev) {
922 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
923 irq);
924 return IRQ_NONE;
925 }
926
927 ioaddr = dev->base_addr;
928
929 if (lp->tx_irq_disabled) {
930 const char *msg;
931 if (lp->tx_irq_disabled)
932 msg = "Interrupt with tx_irq_disabled";
933 else
934 msg = "Re-entering the interrupt handler";
935 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
936 msg,
937 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
938 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
939 /* WARNING: MACE_IR has been read! */
940 return IRQ_NONE;
941 }
942
943 if (!netif_device_present(dev)) {
944 netdev_dbg(dev, "interrupt from dead card\n");
945 return IRQ_NONE;
946 }
947
948 do {
949 /* WARNING: MACE_IR is a READ/CLEAR port! */
950 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
951 if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS)
952 return IRQ_NONE;
953
954 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
955
956 if (status & MACE_IR_RCVINT) {
957 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
958 }
959
960 if (status & MACE_IR_XMTINT) {
961 unsigned char fifofc;
962 unsigned char xmtrc;
963 unsigned char xmtfs;
964
965 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
966 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
967 dev->stats.tx_errors++;
968 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
969 }
970
971 /* Transmit Retry Count (XMTRC, reg 4) */
972 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
973 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
974 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
975
976 if (
977 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
978 MACE_XMTFS_XMTSV /* Transmit Status Valid */
979 ) {
980 lp->mace_stats.xmtsv++;
981
982 if (xmtfs & ~MACE_XMTFS_XMTSV) {
983 if (xmtfs & MACE_XMTFS_UFLO) {
984 /* Underflow. Indicates that the Transmit FIFO emptied before
985 the end of frame was reached. */
986 lp->mace_stats.uflo++;
987 }
988 if (xmtfs & MACE_XMTFS_LCOL) {
989 /* Late Collision */
990 lp->mace_stats.lcol++;
991 }
992 if (xmtfs & MACE_XMTFS_MORE) {
993 /* MORE than one retry was needed */
994 lp->mace_stats.more++;
995 }
996 if (xmtfs & MACE_XMTFS_ONE) {
997 /* Exactly ONE retry occurred */
998 lp->mace_stats.one++;
999 }
1000 if (xmtfs & MACE_XMTFS_DEFER) {
1001 /* Transmission was defered */
1002 lp->mace_stats.defer++;
1003 }
1004 if (xmtfs & MACE_XMTFS_LCAR) {
1005 /* Loss of carrier */
1006 lp->mace_stats.lcar++;
1007 }
1008 if (xmtfs & MACE_XMTFS_RTRY) {
1009 /* Retry error: transmit aborted after 16 attempts */
1010 lp->mace_stats.rtry++;
1011 }
1012 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1013
1014 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1015
1016 dev->stats.tx_packets++;
1017 lp->tx_free_frames++;
1018 netif_wake_queue(dev);
1019 } /* if (status & MACE_IR_XMTINT) */
1020
1021 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1022 if (status & MACE_IR_JAB) {
1023 /* Jabber Error. Excessive transmit duration (20-150ms). */
1024 lp->mace_stats.jab++;
1025 }
1026 if (status & MACE_IR_BABL) {
1027 /* Babble Error. >1518 bytes transmitted. */
1028 lp->mace_stats.babl++;
1029 }
1030 if (status & MACE_IR_CERR) {
1031 /* Collision Error. CERR indicates the absence of the
1032 Signal Quality Error Test message after a packet
1033 transmission. */
1034 lp->mace_stats.cerr++;
1035 }
1036 if (status & MACE_IR_RCVCCO) {
1037 /* Receive Collision Count Overflow; */
1038 lp->mace_stats.rcvcco++;
1039 }
1040 if (status & MACE_IR_RNTPCO) {
1041 /* Runt Packet Count Overflow */
1042 lp->mace_stats.rntpco++;
1043 }
1044 if (status & MACE_IR_MPCO) {
1045 /* Missed Packet Count Overflow */
1046 lp->mace_stats.mpco++;
1047 }
1048 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1049
1050 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1051
1052 return IRQ_HANDLED;
1053} /* mace_interrupt */
1054
1055/* ----------------------------------------------------------------------------
1056mace_rx
1057 Receives packets.
1058---------------------------------------------------------------------------- */
1059static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1060{
1061 mace_private *lp = netdev_priv(dev);
1062 unsigned int ioaddr = dev->base_addr;
1063 unsigned char rx_framecnt;
1064 unsigned short rx_status;
1065
1066 while (
1067 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1068 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1069 (RxCnt--)
1070 ) {
1071 rx_status = inw(ioaddr + AM2150_RCV);
1072
1073 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1074 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1075
1076 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1077 dev->stats.rx_errors++;
1078 if (rx_status & MACE_RCVFS_OFLO) {
1079 lp->mace_stats.oflo++;
1080 }
1081 if (rx_status & MACE_RCVFS_CLSN) {
1082 lp->mace_stats.clsn++;
1083 }
1084 if (rx_status & MACE_RCVFS_FRAM) {
1085 lp->mace_stats.fram++;
1086 }
1087 if (rx_status & MACE_RCVFS_FCS) {
1088 lp->mace_stats.fcs++;
1089 }
1090 } else {
1091 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1092 /* Auto Strip is off, always subtract 4 */
1093 struct sk_buff *skb;
1094
1095 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1096 /* runt packet count */
1097 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1098 /* rcv collision count */
1099
1100 pr_debug(" receiving packet size 0x%X rx_status"
1101 " 0x%X.\n", pkt_len, rx_status);
1102
1103 skb = netdev_alloc_skb(dev, pkt_len + 2);
1104
1105 if (skb) {
1106 skb_reserve(skb, 2);
1107 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1108 if (pkt_len & 1)
1109 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1110 skb->protocol = eth_type_trans(skb, dev);
1111
1112 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1113
1114 dev->stats.rx_packets++;
1115 dev->stats.rx_bytes += pkt_len;
1116 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1117 continue;
1118 } else {
1119 pr_debug("%s: couldn't allocate a sk_buff of size"
1120 " %d.\n", dev->name, pkt_len);
1121 dev->stats.rx_dropped++;
1122 }
1123 }
1124 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1125 } /* while */
1126
1127 return 0;
1128} /* mace_rx */
1129
1130/* ----------------------------------------------------------------------------
1131pr_linux_stats
1132---------------------------------------------------------------------------- */
1133static void pr_linux_stats(struct net_device_stats *pstats)
1134{
1135 pr_debug("pr_linux_stats\n");
1136 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1137 (long)pstats->rx_packets, (long)pstats->tx_packets);
1138 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1139 (long)pstats->rx_errors, (long)pstats->tx_errors);
1140 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1141 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1142 pr_debug(" multicast=%-7ld collisions=%ld\n",
1143 (long)pstats->multicast, (long)pstats->collisions);
1144
1145 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1146 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1147 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1148 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1149 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1150 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1151
1152 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1153 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1154 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1155 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1156 pr_debug(" tx_window_errors=%ld\n",
1157 (long)pstats->tx_window_errors);
1158} /* pr_linux_stats */
1159
1160/* ----------------------------------------------------------------------------
1161pr_mace_stats
1162---------------------------------------------------------------------------- */
1163static void pr_mace_stats(mace_statistics *pstats)
1164{
1165 pr_debug("pr_mace_stats\n");
1166
1167 pr_debug(" xmtsv=%-7d uflo=%d\n",
1168 pstats->xmtsv, pstats->uflo);
1169 pr_debug(" lcol=%-7d more=%d\n",
1170 pstats->lcol, pstats->more);
1171 pr_debug(" one=%-7d defer=%d\n",
1172 pstats->one, pstats->defer);
1173 pr_debug(" lcar=%-7d rtry=%d\n",
1174 pstats->lcar, pstats->rtry);
1175
1176 /* MACE_XMTRC */
1177 pr_debug(" exdef=%-7d xmtrc=%d\n",
1178 pstats->exdef, pstats->xmtrc);
1179
1180 /* RFS1--Receive Status (RCVSTS) */
1181 pr_debug(" oflo=%-7d clsn=%d\n",
1182 pstats->oflo, pstats->clsn);
1183 pr_debug(" fram=%-7d fcs=%d\n",
1184 pstats->fram, pstats->fcs);
1185
1186 /* RFS2--Runt Packet Count (RNTPC) */
1187 /* RFS3--Receive Collision Count (RCVCC) */
1188 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1189 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1190
1191 /* MACE_IR */
1192 pr_debug(" jab=%-7d babl=%d\n",
1193 pstats->jab, pstats->babl);
1194 pr_debug(" cerr=%-7d rcvcco=%d\n",
1195 pstats->cerr, pstats->rcvcco);
1196 pr_debug(" rntpco=%-7d mpco=%d\n",
1197 pstats->rntpco, pstats->mpco);
1198
1199 /* MACE_MPC */
1200 pr_debug(" mpc=%d\n", pstats->mpc);
1201
1202 /* MACE_RNTPC */
1203 pr_debug(" rntpc=%d\n", pstats->rntpc);
1204
1205 /* MACE_RCVCC */
1206 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1207
1208} /* pr_mace_stats */
1209
1210/* ----------------------------------------------------------------------------
1211update_stats
1212 Update statistics. We change to register window 1, so this
1213 should be run single-threaded if the device is active. This is
1214 expected to be a rare operation, and it's simpler for the rest
1215 of the driver to assume that window 0 is always valid rather
1216 than use a special window-state variable.
1217
1218 oflo & uflo should _never_ occur since it would mean the Xilinx
1219 was not able to transfer data between the MACE FIFO and the
1220 card's SRAM fast enough. If this happens, something is
1221 seriously wrong with the hardware.
1222---------------------------------------------------------------------------- */
1223static void update_stats(unsigned int ioaddr, struct net_device *dev)
1224{
1225 mace_private *lp = netdev_priv(dev);
1226
1227 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1228 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1229 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1230 /* At this point, mace_stats is fully updated for this call.
1231 We may now update the netdev stats. */
1232
1233 /* The MACE has no equivalent for netdev stats field which are commented
1234 out. */
1235
1236 /* dev->stats.multicast; */
1237 dev->stats.collisions =
1238 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1239 /* Collision: The MACE may retry sending a packet 15 times
1240 before giving up. The retry count is in XMTRC.
1241 Does each retry constitute a collision?
1242 If so, why doesn't the RCVCC record these collisions? */
1243
1244 /* detailed rx_errors: */
1245 dev->stats.rx_length_errors =
1246 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1247 /* dev->stats.rx_over_errors */
1248 dev->stats.rx_crc_errors = lp->mace_stats.fcs;
1249 dev->stats.rx_frame_errors = lp->mace_stats.fram;
1250 dev->stats.rx_fifo_errors = lp->mace_stats.oflo;
1251 dev->stats.rx_missed_errors =
1252 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1253
1254 /* detailed tx_errors */
1255 dev->stats.tx_aborted_errors = lp->mace_stats.rtry;
1256 dev->stats.tx_carrier_errors = lp->mace_stats.lcar;
1257 /* LCAR usually results from bad cabling. */
1258 dev->stats.tx_fifo_errors = lp->mace_stats.uflo;
1259 dev->stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1260 /* dev->stats.tx_window_errors; */
1261} /* update_stats */
1262
1263/* ----------------------------------------------------------------------------
1264mace_get_stats
1265 Gathers ethernet statistics from the MACE chip.
1266---------------------------------------------------------------------------- */
1267static struct net_device_stats *mace_get_stats(struct net_device *dev)
1268{
1269 mace_private *lp = netdev_priv(dev);
1270
1271 update_stats(dev->base_addr, dev);
1272
1273 pr_debug("%s: updating the statistics.\n", dev->name);
1274 pr_linux_stats(&dev->stats);
1275 pr_mace_stats(&lp->mace_stats);
1276
1277 return &dev->stats;
1278} /* net_device_stats */
1279
1280/* ----------------------------------------------------------------------------
1281updateCRC
1282 Modified from Am79C90 data sheet.
1283---------------------------------------------------------------------------- */
1284
1285#ifdef BROKEN_MULTICAST
1286
1287static void updateCRC(int *CRC, int bit)
1288{
1289 static const int poly[]={
1290 1,1,1,0, 1,1,0,1,
1291 1,0,1,1, 1,0,0,0,
1292 1,0,0,0, 0,0,1,1,
1293 0,0,1,0, 0,0,0,0
1294 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1295 CRC generator polynomial. */
1296
1297 int j;
1298
1299 /* shift CRC and control bit (CRC[32]) */
1300 for (j = 32; j > 0; j--)
1301 CRC[j] = CRC[j-1];
1302 CRC[0] = 0;
1303
1304 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1305 if (bit ^ CRC[32])
1306 for (j = 0; j < 32; j++)
1307 CRC[j] ^= poly[j];
1308} /* updateCRC */
1309
1310/* ----------------------------------------------------------------------------
1311BuildLAF
1312 Build logical address filter.
1313 Modified from Am79C90 data sheet.
1314
1315Input
1316 ladrf: logical address filter (contents initialized to 0)
1317 adr: ethernet address
1318---------------------------------------------------------------------------- */
1319static void BuildLAF(int *ladrf, int *adr)
1320{
1321 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1322
1323 int i, byte; /* temporary array indices */
1324 int hashcode; /* the output object */
1325
1326 CRC[32]=0;
1327
1328 for (byte = 0; byte < 6; byte++)
1329 for (i = 0; i < 8; i++)
1330 updateCRC(CRC, (adr[byte] >> i) & 1);
1331
1332 hashcode = 0;
1333 for (i = 0; i < 6; i++)
1334 hashcode = (hashcode << 1) + CRC[i];
1335
1336 byte = hashcode >> 3;
1337 ladrf[byte] |= (1 << (hashcode & 7));
1338
1339#ifdef PCMCIA_DEBUG
1340 if (0)
1341 printk(KERN_DEBUG " adr =%pM\n", adr);
1342 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1343 for (i = 0; i < 8; i++)
1344 pr_cont(" %02X", ladrf[i]);
1345 pr_cont("\n");
1346#endif
1347} /* BuildLAF */
1348
1349/* ----------------------------------------------------------------------------
1350restore_multicast_list
1351 Restores the multicast filter for MACE chip to the last
1352 set_multicast_list() call.
1353
1354Input
1355 multicast_num_addrs
1356 multicast_ladrf[]
1357---------------------------------------------------------------------------- */
1358static void restore_multicast_list(struct net_device *dev)
1359{
1360 mace_private *lp = netdev_priv(dev);
1361 int num_addrs = lp->multicast_num_addrs;
1362 int *ladrf = lp->multicast_ladrf;
1363 unsigned int ioaddr = dev->base_addr;
1364 int i;
1365
1366 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1367 dev->name, num_addrs);
1368
1369 if (num_addrs > 0) {
1370
1371 pr_debug("Attempt to restore multicast list detected.\n");
1372
1373 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1374 /* Poll ADDRCHG bit */
1375 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1376 ;
1377 /* Set LADRF register */
1378 for (i = 0; i < MACE_LADRF_LEN; i++)
1379 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1380
1381 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1382 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1383
1384 } else if (num_addrs < 0) {
1385
1386 /* Promiscuous mode: receive all packets */
1387 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1388 mace_write(lp, ioaddr, MACE_MACCC,
1389 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1390 );
1391
1392 } else {
1393
1394 /* Normal mode */
1395 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1396 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1397
1398 }
1399} /* restore_multicast_list */
1400
1401/* ----------------------------------------------------------------------------
1402set_multicast_list
1403 Set or clear the multicast filter for this adaptor.
1404
1405Input
1406 num_addrs == -1 Promiscuous mode, receive all packets
1407 num_addrs == 0 Normal mode, clear multicast list
1408 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1409 best-effort filtering.
1410Output
1411 multicast_num_addrs
1412 multicast_ladrf[]
1413---------------------------------------------------------------------------- */
1414
1415static void set_multicast_list(struct net_device *dev)
1416{
1417 mace_private *lp = netdev_priv(dev);
1418 int adr[ETH_ALEN] = {0}; /* Ethernet address */
1419 struct netdev_hw_addr *ha;
1420
1421#ifdef PCMCIA_DEBUG
1422 {
1423 static int old;
1424 if (netdev_mc_count(dev) != old) {
1425 old = netdev_mc_count(dev);
1426 pr_debug("%s: setting Rx mode to %d addresses.\n",
1427 dev->name, old);
1428 }
1429 }
1430#endif
1431
1432 /* Set multicast_num_addrs. */
1433 lp->multicast_num_addrs = netdev_mc_count(dev);
1434
1435 /* Set multicast_ladrf. */
1436 if (num_addrs > 0) {
1437 /* Calculate multicast logical address filter */
1438 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1439 netdev_for_each_mc_addr(ha, dev) {
1440 memcpy(adr, ha->addr, ETH_ALEN);
1441 BuildLAF(lp->multicast_ladrf, adr);
1442 }
1443 }
1444
1445 restore_multicast_list(dev);
1446
1447} /* set_multicast_list */
1448
1449#endif /* BROKEN_MULTICAST */
1450
1451static void restore_multicast_list(struct net_device *dev)
1452{
1453 unsigned int ioaddr = dev->base_addr;
1454 mace_private *lp = netdev_priv(dev);
1455
1456 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1457 lp->multicast_num_addrs);
1458
1459 if (dev->flags & IFF_PROMISC) {
1460 /* Promiscuous mode: receive all packets */
1461 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1462 mace_write(lp, ioaddr, MACE_MACCC,
1463 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1464 );
1465 } else {
1466 /* Normal mode */
1467 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1468 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1469 }
1470} /* restore_multicast_list */
1471
1472static void set_multicast_list(struct net_device *dev)
1473{
1474 mace_private *lp = netdev_priv(dev);
1475
1476#ifdef PCMCIA_DEBUG
1477 {
1478 static int old;
1479 if (netdev_mc_count(dev) != old) {
1480 old = netdev_mc_count(dev);
1481 pr_debug("%s: setting Rx mode to %d addresses.\n",
1482 dev->name, old);
1483 }
1484 }
1485#endif
1486
1487 lp->multicast_num_addrs = netdev_mc_count(dev);
1488 restore_multicast_list(dev);
1489
1490} /* set_multicast_list */
1491
1492static const struct pcmcia_device_id nmclan_ids[] = {
1493 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1494 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1495 PCMCIA_DEVICE_NULL,
1496};
1497MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1498
1499static struct pcmcia_driver nmclan_cs_driver = {
1500 .owner = THIS_MODULE,
1501 .name = "nmclan_cs",
1502 .probe = nmclan_probe,
1503 .remove = nmclan_detach,
1504 .id_table = nmclan_ids,
1505 .suspend = nmclan_suspend,
1506 .resume = nmclan_resume,
1507};
1508module_pcmcia_driver(nmclan_cs_driver);
1/* ----------------------------------------------------------------------------
2Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
3 nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
4
5 The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
6 Access Controller for Ethernet (MACE). It is essentially the Am2150
7 PCMCIA Ethernet card contained in the Am2150 Demo Kit.
8
9Written by Roger C. Pao <rpao@paonet.org>
10 Copyright 1995 Roger C. Pao
11 Linux 2.5 cleanups Copyright Red Hat 2003
12
13 This software may be used and distributed according to the terms of
14 the GNU General Public License.
15
16Ported to Linux 1.3.* network driver environment by
17 Matti Aarnio <mea@utu.fi>
18
19References
20
21 Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
22 Am79C940 (MACE) Data Sheet, 1994
23 Am79C90 (C-LANCE) Data Sheet, 1994
24 Linux PCMCIA Programmer's Guide v1.17
25 /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
26
27 Eric Mears, New Media Corporation
28 Tom Pollard, New Media Corporation
29 Dean Siasoyco, New Media Corporation
30 Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
31 Donald Becker <becker@scyld.com>
32 David Hinds <dahinds@users.sourceforge.net>
33
34 The Linux client driver is based on the 3c589_cs.c client driver by
35 David Hinds.
36
37 The Linux network driver outline is based on the 3c589_cs.c driver,
38 the 8390.c driver, and the example skeleton.c kernel code, which are
39 by Donald Becker.
40
41 The Am2150 network driver hardware interface code is based on the
42 OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
43
44 Special thanks for testing and help in debugging this driver goes
45 to Ken Lesniak.
46
47-------------------------------------------------------------------------------
48Driver Notes and Issues
49-------------------------------------------------------------------------------
50
511. Developed on a Dell 320SLi
52 PCMCIA Card Services 2.6.2
53 Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
54
552. rc.pcmcia may require loading pcmcia_core with io_speed=300:
56 'insmod pcmcia_core.o io_speed=300'.
57 This will avoid problems with fast systems which causes rx_framecnt
58 to return random values.
59
603. If hot extraction does not work for you, use 'ifconfig eth0 down'
61 before extraction.
62
634. There is a bad slow-down problem in this driver.
64
655. Future: Multicast processing. In the meantime, do _not_ compile your
66 kernel with multicast ip enabled.
67
68-------------------------------------------------------------------------------
69History
70-------------------------------------------------------------------------------
71Log: nmclan_cs.c,v
72 * 2.5.75-ac1 2003/07/11 Alan Cox <alan@lxorguk.ukuu.org.uk>
73 * Fixed hang on card eject as we probe it
74 * Cleaned up to use new style locking.
75 *
76 * Revision 0.16 1995/07/01 06:42:17 rpao
77 * Bug fix: nmclan_reset() called CardServices incorrectly.
78 *
79 * Revision 0.15 1995/05/24 08:09:47 rpao
80 * Re-implement MULTI_TX dev->tbusy handling.
81 *
82 * Revision 0.14 1995/05/23 03:19:30 rpao
83 * Added, in nmclan_config(), "tuple.Attributes = 0;".
84 * Modified MACE ID check to ignore chip revision level.
85 * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
86 *
87 * Revision 0.13 1995/05/18 05:56:34 rpao
88 * Statistics changes.
89 * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
90 * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT. Fixes driver lockup.
91 *
92 * Revision 0.12 1995/05/14 00:12:23 rpao
93 * Statistics overhaul.
94 *
95
9695/05/13 rpao V0.10a
97 Bug fix: MACE statistics counters used wrong I/O ports.
98 Bug fix: mace_interrupt() needed to allow statistics to be
99 processed without RX or TX interrupts pending.
10095/05/11 rpao V0.10
101 Multiple transmit request processing.
102 Modified statistics to use MACE counters where possible.
10395/05/10 rpao V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
104 *Released
10595/05/10 rpao V0.08
106 Bug fix: Make all non-exported functions private by using
107 static keyword.
108 Bug fix: Test IntrCnt _before_ reading MACE_IR.
10995/05/10 rpao V0.07 Statistics.
11095/05/09 rpao V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
111
112---------------------------------------------------------------------------- */
113
114#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
115
116#define DRV_NAME "nmclan_cs"
117#define DRV_VERSION "0.16"
118
119
120/* ----------------------------------------------------------------------------
121Conditional Compilation Options
122---------------------------------------------------------------------------- */
123
124#define MULTI_TX 0
125#define RESET_ON_TIMEOUT 1
126#define TX_INTERRUPTABLE 1
127#define RESET_XILINX 0
128
129/* ----------------------------------------------------------------------------
130Include Files
131---------------------------------------------------------------------------- */
132
133#include <linux/module.h>
134#include <linux/kernel.h>
135#include <linux/ptrace.h>
136#include <linux/slab.h>
137#include <linux/string.h>
138#include <linux/timer.h>
139#include <linux/interrupt.h>
140#include <linux/in.h>
141#include <linux/delay.h>
142#include <linux/ethtool.h>
143#include <linux/netdevice.h>
144#include <linux/etherdevice.h>
145#include <linux/skbuff.h>
146#include <linux/if_arp.h>
147#include <linux/ioport.h>
148#include <linux/bitops.h>
149
150#include <pcmcia/cisreg.h>
151#include <pcmcia/cistpl.h>
152#include <pcmcia/ds.h>
153
154#include <linux/uaccess.h>
155#include <asm/io.h>
156
157/* ----------------------------------------------------------------------------
158Defines
159---------------------------------------------------------------------------- */
160
161#define MACE_LADRF_LEN 8
162 /* 8 bytes in Logical Address Filter */
163
164/* Loop Control Defines */
165#define MACE_MAX_IR_ITERATIONS 10
166#define MACE_MAX_RX_ITERATIONS 12
167 /*
168 TBD: Dean brought this up, and I assumed the hardware would
169 handle it:
170
171 If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
172 non-zero when the isr exits. We may not get another interrupt
173 to process the remaining packets for some time.
174 */
175
176/*
177The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
178which manages the interface between the MACE and the PCMCIA bus. It
179also includes buffer management for the 32K x 8 SRAM to control up to
180four transmit and 12 receive frames at a time.
181*/
182#define AM2150_MAX_TX_FRAMES 4
183#define AM2150_MAX_RX_FRAMES 12
184
185/* Am2150 Ethernet Card I/O Mapping */
186#define AM2150_RCV 0x00
187#define AM2150_XMT 0x04
188#define AM2150_XMT_SKIP 0x09
189#define AM2150_RCV_NEXT 0x0A
190#define AM2150_RCV_FRAME_COUNT 0x0B
191#define AM2150_MACE_BANK 0x0C
192#define AM2150_MACE_BASE 0x10
193
194/* MACE Registers */
195#define MACE_RCVFIFO 0
196#define MACE_XMTFIFO 1
197#define MACE_XMTFC 2
198#define MACE_XMTFS 3
199#define MACE_XMTRC 4
200#define MACE_RCVFC 5
201#define MACE_RCVFS 6
202#define MACE_FIFOFC 7
203#define MACE_IR 8
204#define MACE_IMR 9
205#define MACE_PR 10
206#define MACE_BIUCC 11
207#define MACE_FIFOCC 12
208#define MACE_MACCC 13
209#define MACE_PLSCC 14
210#define MACE_PHYCC 15
211#define MACE_CHIPIDL 16
212#define MACE_CHIPIDH 17
213#define MACE_IAC 18
214/* Reserved */
215#define MACE_LADRF 20
216#define MACE_PADR 21
217/* Reserved */
218/* Reserved */
219#define MACE_MPC 24
220/* Reserved */
221#define MACE_RNTPC 26
222#define MACE_RCVCC 27
223/* Reserved */
224#define MACE_UTR 29
225#define MACE_RTR1 30
226#define MACE_RTR2 31
227
228/* MACE Bit Masks */
229#define MACE_XMTRC_EXDEF 0x80
230#define MACE_XMTRC_XMTRC 0x0F
231
232#define MACE_XMTFS_XMTSV 0x80
233#define MACE_XMTFS_UFLO 0x40
234#define MACE_XMTFS_LCOL 0x20
235#define MACE_XMTFS_MORE 0x10
236#define MACE_XMTFS_ONE 0x08
237#define MACE_XMTFS_DEFER 0x04
238#define MACE_XMTFS_LCAR 0x02
239#define MACE_XMTFS_RTRY 0x01
240
241#define MACE_RCVFS_RCVSTS 0xF000
242#define MACE_RCVFS_OFLO 0x8000
243#define MACE_RCVFS_CLSN 0x4000
244#define MACE_RCVFS_FRAM 0x2000
245#define MACE_RCVFS_FCS 0x1000
246
247#define MACE_FIFOFC_RCVFC 0xF0
248#define MACE_FIFOFC_XMTFC 0x0F
249
250#define MACE_IR_JAB 0x80
251#define MACE_IR_BABL 0x40
252#define MACE_IR_CERR 0x20
253#define MACE_IR_RCVCCO 0x10
254#define MACE_IR_RNTPCO 0x08
255#define MACE_IR_MPCO 0x04
256#define MACE_IR_RCVINT 0x02
257#define MACE_IR_XMTINT 0x01
258
259#define MACE_MACCC_PROM 0x80
260#define MACE_MACCC_DXMT2PD 0x40
261#define MACE_MACCC_EMBA 0x20
262#define MACE_MACCC_RESERVED 0x10
263#define MACE_MACCC_DRCVPA 0x08
264#define MACE_MACCC_DRCVBC 0x04
265#define MACE_MACCC_ENXMT 0x02
266#define MACE_MACCC_ENRCV 0x01
267
268#define MACE_PHYCC_LNKFL 0x80
269#define MACE_PHYCC_DLNKTST 0x40
270#define MACE_PHYCC_REVPOL 0x20
271#define MACE_PHYCC_DAPC 0x10
272#define MACE_PHYCC_LRT 0x08
273#define MACE_PHYCC_ASEL 0x04
274#define MACE_PHYCC_RWAKE 0x02
275#define MACE_PHYCC_AWAKE 0x01
276
277#define MACE_IAC_ADDRCHG 0x80
278#define MACE_IAC_PHYADDR 0x04
279#define MACE_IAC_LOGADDR 0x02
280
281#define MACE_UTR_RTRE 0x80
282#define MACE_UTR_RTRD 0x40
283#define MACE_UTR_RPA 0x20
284#define MACE_UTR_FCOLL 0x10
285#define MACE_UTR_RCVFCSE 0x08
286#define MACE_UTR_LOOP_INCL_MENDEC 0x06
287#define MACE_UTR_LOOP_NO_MENDEC 0x04
288#define MACE_UTR_LOOP_EXTERNAL 0x02
289#define MACE_UTR_LOOP_NONE 0x00
290#define MACE_UTR_RESERVED 0x01
291
292/* Switch MACE register bank (only 0 and 1 are valid) */
293#define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
294
295#define MACE_IMR_DEFAULT \
296 (0xFF - \
297 ( \
298 MACE_IR_CERR | \
299 MACE_IR_RCVCCO | \
300 MACE_IR_RNTPCO | \
301 MACE_IR_MPCO | \
302 MACE_IR_RCVINT | \
303 MACE_IR_XMTINT \
304 ) \
305 )
306#undef MACE_IMR_DEFAULT
307#define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
308
309#define TX_TIMEOUT ((400*HZ)/1000)
310
311/* ----------------------------------------------------------------------------
312Type Definitions
313---------------------------------------------------------------------------- */
314
315typedef struct _mace_statistics {
316 /* MACE_XMTFS */
317 int xmtsv;
318 int uflo;
319 int lcol;
320 int more;
321 int one;
322 int defer;
323 int lcar;
324 int rtry;
325
326 /* MACE_XMTRC */
327 int exdef;
328 int xmtrc;
329
330 /* RFS1--Receive Status (RCVSTS) */
331 int oflo;
332 int clsn;
333 int fram;
334 int fcs;
335
336 /* RFS2--Runt Packet Count (RNTPC) */
337 int rfs_rntpc;
338
339 /* RFS3--Receive Collision Count (RCVCC) */
340 int rfs_rcvcc;
341
342 /* MACE_IR */
343 int jab;
344 int babl;
345 int cerr;
346 int rcvcco;
347 int rntpco;
348 int mpco;
349
350 /* MACE_MPC */
351 int mpc;
352
353 /* MACE_RNTPC */
354 int rntpc;
355
356 /* MACE_RCVCC */
357 int rcvcc;
358} mace_statistics;
359
360typedef struct _mace_private {
361 struct pcmcia_device *p_dev;
362 mace_statistics mace_stats; /* MACE chip statistics counters */
363
364 /* restore_multicast_list() state variables */
365 int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
366 int multicast_num_addrs;
367
368 char tx_free_frames; /* Number of free transmit frame buffers */
369 char tx_irq_disabled; /* MACE TX interrupt disabled */
370
371 spinlock_t bank_lock; /* Must be held if you step off bank 0 */
372} mace_private;
373
374/* ----------------------------------------------------------------------------
375Private Global Variables
376---------------------------------------------------------------------------- */
377
378static const char *if_names[]={
379 "Auto", "10baseT", "BNC",
380};
381
382/* ----------------------------------------------------------------------------
383Parameters
384 These are the parameters that can be set during loading with
385 'insmod'.
386---------------------------------------------------------------------------- */
387
388MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
389MODULE_LICENSE("GPL");
390
391#define INT_MODULE_PARM(n, v) static int n = v; module_param(n, int, 0)
392
393/* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
394INT_MODULE_PARM(if_port, 0);
395
396
397/* ----------------------------------------------------------------------------
398Function Prototypes
399---------------------------------------------------------------------------- */
400
401static int nmclan_config(struct pcmcia_device *link);
402static void nmclan_release(struct pcmcia_device *link);
403
404static void nmclan_reset(struct net_device *dev);
405static int mace_config(struct net_device *dev, struct ifmap *map);
406static int mace_open(struct net_device *dev);
407static int mace_close(struct net_device *dev);
408static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
409 struct net_device *dev);
410static void mace_tx_timeout(struct net_device *dev);
411static irqreturn_t mace_interrupt(int irq, void *dev_id);
412static struct net_device_stats *mace_get_stats(struct net_device *dev);
413static int mace_rx(struct net_device *dev, unsigned char RxCnt);
414static void restore_multicast_list(struct net_device *dev);
415static void set_multicast_list(struct net_device *dev);
416static const struct ethtool_ops netdev_ethtool_ops;
417
418
419static void nmclan_detach(struct pcmcia_device *p_dev);
420
421static const struct net_device_ops mace_netdev_ops = {
422 .ndo_open = mace_open,
423 .ndo_stop = mace_close,
424 .ndo_start_xmit = mace_start_xmit,
425 .ndo_tx_timeout = mace_tx_timeout,
426 .ndo_set_config = mace_config,
427 .ndo_get_stats = mace_get_stats,
428 .ndo_set_rx_mode = set_multicast_list,
429 .ndo_set_mac_address = eth_mac_addr,
430 .ndo_validate_addr = eth_validate_addr,
431};
432
433static int nmclan_probe(struct pcmcia_device *link)
434{
435 mace_private *lp;
436 struct net_device *dev;
437
438 dev_dbg(&link->dev, "nmclan_attach()\n");
439
440 /* Create new ethernet device */
441 dev = alloc_etherdev(sizeof(mace_private));
442 if (!dev)
443 return -ENOMEM;
444 lp = netdev_priv(dev);
445 lp->p_dev = link;
446 link->priv = dev;
447
448 spin_lock_init(&lp->bank_lock);
449 link->resource[0]->end = 32;
450 link->resource[0]->flags |= IO_DATA_PATH_WIDTH_AUTO;
451 link->config_flags |= CONF_ENABLE_IRQ;
452 link->config_index = 1;
453 link->config_regs = PRESENT_OPTION;
454
455 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
456
457 dev->netdev_ops = &mace_netdev_ops;
458 dev->ethtool_ops = &netdev_ethtool_ops;
459 dev->watchdog_timeo = TX_TIMEOUT;
460
461 return nmclan_config(link);
462} /* nmclan_attach */
463
464static void nmclan_detach(struct pcmcia_device *link)
465{
466 struct net_device *dev = link->priv;
467
468 dev_dbg(&link->dev, "nmclan_detach\n");
469
470 unregister_netdev(dev);
471
472 nmclan_release(link);
473
474 free_netdev(dev);
475} /* nmclan_detach */
476
477/* ----------------------------------------------------------------------------
478mace_read
479 Reads a MACE register. This is bank independent; however, the
480 caller must ensure that this call is not interruptable. We are
481 assuming that during normal operation, the MACE is always in
482 bank 0.
483---------------------------------------------------------------------------- */
484static int mace_read(mace_private *lp, unsigned int ioaddr, int reg)
485{
486 int data = 0xFF;
487 unsigned long flags;
488
489 switch (reg >> 4) {
490 case 0: /* register 0-15 */
491 data = inb(ioaddr + AM2150_MACE_BASE + reg);
492 break;
493 case 1: /* register 16-31 */
494 spin_lock_irqsave(&lp->bank_lock, flags);
495 MACEBANK(1);
496 data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
497 MACEBANK(0);
498 spin_unlock_irqrestore(&lp->bank_lock, flags);
499 break;
500 }
501 return data & 0xFF;
502} /* mace_read */
503
504/* ----------------------------------------------------------------------------
505mace_write
506 Writes to a MACE register. This is bank independent; however,
507 the caller must ensure that this call is not interruptable. We
508 are assuming that during normal operation, the MACE is always in
509 bank 0.
510---------------------------------------------------------------------------- */
511static void mace_write(mace_private *lp, unsigned int ioaddr, int reg,
512 int data)
513{
514 unsigned long flags;
515
516 switch (reg >> 4) {
517 case 0: /* register 0-15 */
518 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
519 break;
520 case 1: /* register 16-31 */
521 spin_lock_irqsave(&lp->bank_lock, flags);
522 MACEBANK(1);
523 outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
524 MACEBANK(0);
525 spin_unlock_irqrestore(&lp->bank_lock, flags);
526 break;
527 }
528} /* mace_write */
529
530/* ----------------------------------------------------------------------------
531mace_init
532 Resets the MACE chip.
533---------------------------------------------------------------------------- */
534static int mace_init(mace_private *lp, unsigned int ioaddr, char *enet_addr)
535{
536 int i;
537 int ct = 0;
538
539 /* MACE Software reset */
540 mace_write(lp, ioaddr, MACE_BIUCC, 1);
541 while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
542 /* Wait for reset bit to be cleared automatically after <= 200ns */;
543 if(++ct > 500)
544 {
545 pr_err("reset failed, card removed?\n");
546 return -1;
547 }
548 udelay(1);
549 }
550 mace_write(lp, ioaddr, MACE_BIUCC, 0);
551
552 /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
553 mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
554
555 mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
556 mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
557
558 /*
559 * Bit 2-1 PORTSEL[1-0] Port Select.
560 * 00 AUI/10Base-2
561 * 01 10Base-T
562 * 10 DAI Port (reserved in Am2150)
563 * 11 GPSI
564 * For this card, only the first two are valid.
565 * So, PLSCC should be set to
566 * 0x00 for 10Base-2
567 * 0x02 for 10Base-T
568 * Or just set ASEL in PHYCC below!
569 */
570 switch (if_port) {
571 case 1:
572 mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
573 break;
574 case 2:
575 mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
576 break;
577 default:
578 mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
579 /* ASEL Auto Select. When set, the PORTSEL[1-0] bits are overridden,
580 and the MACE device will automatically select the operating media
581 interface port. */
582 break;
583 }
584
585 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
586 /* Poll ADDRCHG bit */
587 ct = 0;
588 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
589 {
590 if(++ ct > 500)
591 {
592 pr_err("ADDRCHG timeout, card removed?\n");
593 return -1;
594 }
595 }
596 /* Set PADR register */
597 for (i = 0; i < ETH_ALEN; i++)
598 mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
599
600 /* MAC Configuration Control Register should be written last */
601 /* Let set_multicast_list set this. */
602 /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
603 mace_write(lp, ioaddr, MACE_MACCC, 0x00);
604 return 0;
605} /* mace_init */
606
607static int nmclan_config(struct pcmcia_device *link)
608{
609 struct net_device *dev = link->priv;
610 mace_private *lp = netdev_priv(dev);
611 u8 *buf;
612 size_t len;
613 int i, ret;
614 unsigned int ioaddr;
615
616 dev_dbg(&link->dev, "nmclan_config\n");
617
618 link->io_lines = 5;
619 ret = pcmcia_request_io(link);
620 if (ret)
621 goto failed;
622 ret = pcmcia_request_irq(link, mace_interrupt);
623 if (ret)
624 goto failed;
625 ret = pcmcia_enable_device(link);
626 if (ret)
627 goto failed;
628
629 dev->irq = link->irq;
630 dev->base_addr = link->resource[0]->start;
631
632 ioaddr = dev->base_addr;
633
634 /* Read the ethernet address from the CIS. */
635 len = pcmcia_get_tuple(link, 0x80, &buf);
636 if (!buf || len < ETH_ALEN) {
637 kfree(buf);
638 goto failed;
639 }
640 memcpy(dev->dev_addr, buf, ETH_ALEN);
641 kfree(buf);
642
643 /* Verify configuration by reading the MACE ID. */
644 {
645 char sig[2];
646
647 sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
648 sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
649 if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
650 dev_dbg(&link->dev, "nmclan_cs configured: mace id=%x %x\n",
651 sig[0], sig[1]);
652 } else {
653 pr_notice("mace id not found: %x %x should be 0x40 0x?9\n",
654 sig[0], sig[1]);
655 return -ENODEV;
656 }
657 }
658
659 if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
660 goto failed;
661
662 /* The if_port symbol can be set when the module is loaded */
663 if (if_port <= 2)
664 dev->if_port = if_port;
665 else
666 pr_notice("invalid if_port requested\n");
667
668 SET_NETDEV_DEV(dev, &link->dev);
669
670 i = register_netdev(dev);
671 if (i != 0) {
672 pr_notice("register_netdev() failed\n");
673 goto failed;
674 }
675
676 netdev_info(dev, "nmclan: port %#3lx, irq %d, %s port, hw_addr %pM\n",
677 dev->base_addr, dev->irq, if_names[dev->if_port], dev->dev_addr);
678 return 0;
679
680failed:
681 nmclan_release(link);
682 return -ENODEV;
683} /* nmclan_config */
684
685static void nmclan_release(struct pcmcia_device *link)
686{
687 dev_dbg(&link->dev, "nmclan_release\n");
688 pcmcia_disable_device(link);
689}
690
691static int nmclan_suspend(struct pcmcia_device *link)
692{
693 struct net_device *dev = link->priv;
694
695 if (link->open)
696 netif_device_detach(dev);
697
698 return 0;
699}
700
701static int nmclan_resume(struct pcmcia_device *link)
702{
703 struct net_device *dev = link->priv;
704
705 if (link->open) {
706 nmclan_reset(dev);
707 netif_device_attach(dev);
708 }
709
710 return 0;
711}
712
713
714/* ----------------------------------------------------------------------------
715nmclan_reset
716 Reset and restore all of the Xilinx and MACE registers.
717---------------------------------------------------------------------------- */
718static void nmclan_reset(struct net_device *dev)
719{
720 mace_private *lp = netdev_priv(dev);
721
722#if RESET_XILINX
723 struct pcmcia_device *link = &lp->link;
724 u8 OrigCorValue;
725
726 /* Save original COR value */
727 pcmcia_read_config_byte(link, CISREG_COR, &OrigCorValue);
728
729 /* Reset Xilinx */
730 dev_dbg(&link->dev, "nmclan_reset: OrigCorValue=0x%x, resetting...\n",
731 OrigCorValue);
732 pcmcia_write_config_byte(link, CISREG_COR, COR_SOFT_RESET);
733 /* Need to wait for 20 ms for PCMCIA to finish reset. */
734
735 /* Restore original COR configuration index */
736 pcmcia_write_config_byte(link, CISREG_COR,
737 (COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK)));
738 /* Xilinx is now completely reset along with the MACE chip. */
739 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
740
741#endif /* #if RESET_XILINX */
742
743 /* Xilinx is now completely reset along with the MACE chip. */
744 lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
745
746 /* Reinitialize the MACE chip for operation. */
747 mace_init(lp, dev->base_addr, dev->dev_addr);
748 mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
749
750 /* Restore the multicast list and enable TX and RX. */
751 restore_multicast_list(dev);
752} /* nmclan_reset */
753
754/* ----------------------------------------------------------------------------
755mace_config
756 [Someone tell me what this is supposed to do? Is if_port a defined
757 standard? If so, there should be defines to indicate 1=10Base-T,
758 2=10Base-2, etc. including limited automatic detection.]
759---------------------------------------------------------------------------- */
760static int mace_config(struct net_device *dev, struct ifmap *map)
761{
762 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
763 if (map->port <= 2) {
764 dev->if_port = map->port;
765 netdev_info(dev, "switched to %s port\n", if_names[dev->if_port]);
766 } else
767 return -EINVAL;
768 }
769 return 0;
770} /* mace_config */
771
772/* ----------------------------------------------------------------------------
773mace_open
774 Open device driver.
775---------------------------------------------------------------------------- */
776static int mace_open(struct net_device *dev)
777{
778 unsigned int ioaddr = dev->base_addr;
779 mace_private *lp = netdev_priv(dev);
780 struct pcmcia_device *link = lp->p_dev;
781
782 if (!pcmcia_dev_present(link))
783 return -ENODEV;
784
785 link->open++;
786
787 MACEBANK(0);
788
789 netif_start_queue(dev);
790 nmclan_reset(dev);
791
792 return 0; /* Always succeed */
793} /* mace_open */
794
795/* ----------------------------------------------------------------------------
796mace_close
797 Closes device driver.
798---------------------------------------------------------------------------- */
799static int mace_close(struct net_device *dev)
800{
801 unsigned int ioaddr = dev->base_addr;
802 mace_private *lp = netdev_priv(dev);
803 struct pcmcia_device *link = lp->p_dev;
804
805 dev_dbg(&link->dev, "%s: shutting down ethercard.\n", dev->name);
806
807 /* Mask off all interrupts from the MACE chip. */
808 outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
809
810 link->open--;
811 netif_stop_queue(dev);
812
813 return 0;
814} /* mace_close */
815
816static void netdev_get_drvinfo(struct net_device *dev,
817 struct ethtool_drvinfo *info)
818{
819 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
820 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
821 snprintf(info->bus_info, sizeof(info->bus_info),
822 "PCMCIA 0x%lx", dev->base_addr);
823}
824
825static const struct ethtool_ops netdev_ethtool_ops = {
826 .get_drvinfo = netdev_get_drvinfo,
827};
828
829/* ----------------------------------------------------------------------------
830mace_start_xmit
831 This routine begins the packet transmit function. When completed,
832 it will generate a transmit interrupt.
833
834 According to /usr/src/linux/net/inet/dev.c, if _start_xmit
835 returns 0, the "packet is now solely the responsibility of the
836 driver." If _start_xmit returns non-zero, the "transmission
837 failed, put skb back into a list."
838---------------------------------------------------------------------------- */
839
840static void mace_tx_timeout(struct net_device *dev)
841{
842 mace_private *lp = netdev_priv(dev);
843 struct pcmcia_device *link = lp->p_dev;
844
845 netdev_notice(dev, "transmit timed out -- ");
846#if RESET_ON_TIMEOUT
847 pr_cont("resetting card\n");
848 pcmcia_reset_card(link->socket);
849#else /* #if RESET_ON_TIMEOUT */
850 pr_cont("NOT resetting card\n");
851#endif /* #if RESET_ON_TIMEOUT */
852 netif_trans_update(dev); /* prevent tx timeout */
853 netif_wake_queue(dev);
854}
855
856static netdev_tx_t mace_start_xmit(struct sk_buff *skb,
857 struct net_device *dev)
858{
859 mace_private *lp = netdev_priv(dev);
860 unsigned int ioaddr = dev->base_addr;
861
862 netif_stop_queue(dev);
863
864 pr_debug("%s: mace_start_xmit(length = %ld) called.\n",
865 dev->name, (long)skb->len);
866
867#if (!TX_INTERRUPTABLE)
868 /* Disable MACE TX interrupts. */
869 outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
870 ioaddr + AM2150_MACE_BASE + MACE_IMR);
871 lp->tx_irq_disabled=1;
872#endif /* #if (!TX_INTERRUPTABLE) */
873
874 {
875 /* This block must not be interrupted by another transmit request!
876 mace_tx_timeout will take care of timer-based retransmissions from
877 the upper layers. The interrupt handler is guaranteed never to
878 service a transmit interrupt while we are in here.
879 */
880
881 dev->stats.tx_bytes += skb->len;
882 lp->tx_free_frames--;
883
884 /* WARNING: Write the _exact_ number of bytes written in the header! */
885 /* Put out the word header [must be an outw()] . . . */
886 outw(skb->len, ioaddr + AM2150_XMT);
887 /* . . . and the packet [may be any combination of outw() and outb()] */
888 outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
889 if (skb->len & 1) {
890 /* Odd byte transfer */
891 outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
892 }
893
894#if MULTI_TX
895 if (lp->tx_free_frames > 0)
896 netif_start_queue(dev);
897#endif /* #if MULTI_TX */
898 }
899
900#if (!TX_INTERRUPTABLE)
901 /* Re-enable MACE TX interrupts. */
902 lp->tx_irq_disabled=0;
903 outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
904#endif /* #if (!TX_INTERRUPTABLE) */
905
906 dev_kfree_skb(skb);
907
908 return NETDEV_TX_OK;
909} /* mace_start_xmit */
910
911/* ----------------------------------------------------------------------------
912mace_interrupt
913 The interrupt handler.
914---------------------------------------------------------------------------- */
915static irqreturn_t mace_interrupt(int irq, void *dev_id)
916{
917 struct net_device *dev = (struct net_device *) dev_id;
918 mace_private *lp = netdev_priv(dev);
919 unsigned int ioaddr;
920 int status;
921 int IntrCnt = MACE_MAX_IR_ITERATIONS;
922
923 if (dev == NULL) {
924 pr_debug("mace_interrupt(): irq 0x%X for unknown device.\n",
925 irq);
926 return IRQ_NONE;
927 }
928
929 ioaddr = dev->base_addr;
930
931 if (lp->tx_irq_disabled) {
932 const char *msg;
933 if (lp->tx_irq_disabled)
934 msg = "Interrupt with tx_irq_disabled";
935 else
936 msg = "Re-entering the interrupt handler";
937 netdev_notice(dev, "%s [isr=%02X, imr=%02X]\n",
938 msg,
939 inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
940 inb(ioaddr + AM2150_MACE_BASE + MACE_IMR));
941 /* WARNING: MACE_IR has been read! */
942 return IRQ_NONE;
943 }
944
945 if (!netif_device_present(dev)) {
946 netdev_dbg(dev, "interrupt from dead card\n");
947 return IRQ_NONE;
948 }
949
950 do {
951 /* WARNING: MACE_IR is a READ/CLEAR port! */
952 status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
953 if (!(status & ~MACE_IMR_DEFAULT) && IntrCnt == MACE_MAX_IR_ITERATIONS)
954 return IRQ_NONE;
955
956 pr_debug("mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
957
958 if (status & MACE_IR_RCVINT) {
959 mace_rx(dev, MACE_MAX_RX_ITERATIONS);
960 }
961
962 if (status & MACE_IR_XMTINT) {
963 unsigned char fifofc;
964 unsigned char xmtrc;
965 unsigned char xmtfs;
966
967 fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
968 if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
969 dev->stats.tx_errors++;
970 outb(0xFF, ioaddr + AM2150_XMT_SKIP);
971 }
972
973 /* Transmit Retry Count (XMTRC, reg 4) */
974 xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
975 if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
976 lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
977
978 if (
979 (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
980 MACE_XMTFS_XMTSV /* Transmit Status Valid */
981 ) {
982 lp->mace_stats.xmtsv++;
983
984 if (xmtfs & ~MACE_XMTFS_XMTSV) {
985 if (xmtfs & MACE_XMTFS_UFLO) {
986 /* Underflow. Indicates that the Transmit FIFO emptied before
987 the end of frame was reached. */
988 lp->mace_stats.uflo++;
989 }
990 if (xmtfs & MACE_XMTFS_LCOL) {
991 /* Late Collision */
992 lp->mace_stats.lcol++;
993 }
994 if (xmtfs & MACE_XMTFS_MORE) {
995 /* MORE than one retry was needed */
996 lp->mace_stats.more++;
997 }
998 if (xmtfs & MACE_XMTFS_ONE) {
999 /* Exactly ONE retry occurred */
1000 lp->mace_stats.one++;
1001 }
1002 if (xmtfs & MACE_XMTFS_DEFER) {
1003 /* Transmission was defered */
1004 lp->mace_stats.defer++;
1005 }
1006 if (xmtfs & MACE_XMTFS_LCAR) {
1007 /* Loss of carrier */
1008 lp->mace_stats.lcar++;
1009 }
1010 if (xmtfs & MACE_XMTFS_RTRY) {
1011 /* Retry error: transmit aborted after 16 attempts */
1012 lp->mace_stats.rtry++;
1013 }
1014 } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1015
1016 } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1017
1018 dev->stats.tx_packets++;
1019 lp->tx_free_frames++;
1020 netif_wake_queue(dev);
1021 } /* if (status & MACE_IR_XMTINT) */
1022
1023 if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1024 if (status & MACE_IR_JAB) {
1025 /* Jabber Error. Excessive transmit duration (20-150ms). */
1026 lp->mace_stats.jab++;
1027 }
1028 if (status & MACE_IR_BABL) {
1029 /* Babble Error. >1518 bytes transmitted. */
1030 lp->mace_stats.babl++;
1031 }
1032 if (status & MACE_IR_CERR) {
1033 /* Collision Error. CERR indicates the absence of the
1034 Signal Quality Error Test message after a packet
1035 transmission. */
1036 lp->mace_stats.cerr++;
1037 }
1038 if (status & MACE_IR_RCVCCO) {
1039 /* Receive Collision Count Overflow; */
1040 lp->mace_stats.rcvcco++;
1041 }
1042 if (status & MACE_IR_RNTPCO) {
1043 /* Runt Packet Count Overflow */
1044 lp->mace_stats.rntpco++;
1045 }
1046 if (status & MACE_IR_MPCO) {
1047 /* Missed Packet Count Overflow */
1048 lp->mace_stats.mpco++;
1049 }
1050 } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1051
1052 } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1053
1054 return IRQ_HANDLED;
1055} /* mace_interrupt */
1056
1057/* ----------------------------------------------------------------------------
1058mace_rx
1059 Receives packets.
1060---------------------------------------------------------------------------- */
1061static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1062{
1063 mace_private *lp = netdev_priv(dev);
1064 unsigned int ioaddr = dev->base_addr;
1065 unsigned char rx_framecnt;
1066 unsigned short rx_status;
1067
1068 while (
1069 ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1070 (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1071 (RxCnt--)
1072 ) {
1073 rx_status = inw(ioaddr + AM2150_RCV);
1074
1075 pr_debug("%s: in mace_rx(), framecnt 0x%X, rx_status"
1076 " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1077
1078 if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1079 dev->stats.rx_errors++;
1080 if (rx_status & MACE_RCVFS_OFLO) {
1081 lp->mace_stats.oflo++;
1082 }
1083 if (rx_status & MACE_RCVFS_CLSN) {
1084 lp->mace_stats.clsn++;
1085 }
1086 if (rx_status & MACE_RCVFS_FRAM) {
1087 lp->mace_stats.fram++;
1088 }
1089 if (rx_status & MACE_RCVFS_FCS) {
1090 lp->mace_stats.fcs++;
1091 }
1092 } else {
1093 short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1094 /* Auto Strip is off, always subtract 4 */
1095 struct sk_buff *skb;
1096
1097 lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1098 /* runt packet count */
1099 lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1100 /* rcv collision count */
1101
1102 pr_debug(" receiving packet size 0x%X rx_status"
1103 " 0x%X.\n", pkt_len, rx_status);
1104
1105 skb = netdev_alloc_skb(dev, pkt_len + 2);
1106
1107 if (skb != NULL) {
1108 skb_reserve(skb, 2);
1109 insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1110 if (pkt_len & 1)
1111 *(skb_tail_pointer(skb) - 1) = inb(ioaddr + AM2150_RCV);
1112 skb->protocol = eth_type_trans(skb, dev);
1113
1114 netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1115
1116 dev->stats.rx_packets++;
1117 dev->stats.rx_bytes += pkt_len;
1118 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1119 continue;
1120 } else {
1121 pr_debug("%s: couldn't allocate a sk_buff of size"
1122 " %d.\n", dev->name, pkt_len);
1123 dev->stats.rx_dropped++;
1124 }
1125 }
1126 outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1127 } /* while */
1128
1129 return 0;
1130} /* mace_rx */
1131
1132/* ----------------------------------------------------------------------------
1133pr_linux_stats
1134---------------------------------------------------------------------------- */
1135static void pr_linux_stats(struct net_device_stats *pstats)
1136{
1137 pr_debug("pr_linux_stats\n");
1138 pr_debug(" rx_packets=%-7ld tx_packets=%ld\n",
1139 (long)pstats->rx_packets, (long)pstats->tx_packets);
1140 pr_debug(" rx_errors=%-7ld tx_errors=%ld\n",
1141 (long)pstats->rx_errors, (long)pstats->tx_errors);
1142 pr_debug(" rx_dropped=%-7ld tx_dropped=%ld\n",
1143 (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1144 pr_debug(" multicast=%-7ld collisions=%ld\n",
1145 (long)pstats->multicast, (long)pstats->collisions);
1146
1147 pr_debug(" rx_length_errors=%-7ld rx_over_errors=%ld\n",
1148 (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1149 pr_debug(" rx_crc_errors=%-7ld rx_frame_errors=%ld\n",
1150 (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1151 pr_debug(" rx_fifo_errors=%-7ld rx_missed_errors=%ld\n",
1152 (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1153
1154 pr_debug(" tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1155 (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1156 pr_debug(" tx_fifo_errors=%-7ld tx_heartbeat_errors=%ld\n",
1157 (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1158 pr_debug(" tx_window_errors=%ld\n",
1159 (long)pstats->tx_window_errors);
1160} /* pr_linux_stats */
1161
1162/* ----------------------------------------------------------------------------
1163pr_mace_stats
1164---------------------------------------------------------------------------- */
1165static void pr_mace_stats(mace_statistics *pstats)
1166{
1167 pr_debug("pr_mace_stats\n");
1168
1169 pr_debug(" xmtsv=%-7d uflo=%d\n",
1170 pstats->xmtsv, pstats->uflo);
1171 pr_debug(" lcol=%-7d more=%d\n",
1172 pstats->lcol, pstats->more);
1173 pr_debug(" one=%-7d defer=%d\n",
1174 pstats->one, pstats->defer);
1175 pr_debug(" lcar=%-7d rtry=%d\n",
1176 pstats->lcar, pstats->rtry);
1177
1178 /* MACE_XMTRC */
1179 pr_debug(" exdef=%-7d xmtrc=%d\n",
1180 pstats->exdef, pstats->xmtrc);
1181
1182 /* RFS1--Receive Status (RCVSTS) */
1183 pr_debug(" oflo=%-7d clsn=%d\n",
1184 pstats->oflo, pstats->clsn);
1185 pr_debug(" fram=%-7d fcs=%d\n",
1186 pstats->fram, pstats->fcs);
1187
1188 /* RFS2--Runt Packet Count (RNTPC) */
1189 /* RFS3--Receive Collision Count (RCVCC) */
1190 pr_debug(" rfs_rntpc=%-7d rfs_rcvcc=%d\n",
1191 pstats->rfs_rntpc, pstats->rfs_rcvcc);
1192
1193 /* MACE_IR */
1194 pr_debug(" jab=%-7d babl=%d\n",
1195 pstats->jab, pstats->babl);
1196 pr_debug(" cerr=%-7d rcvcco=%d\n",
1197 pstats->cerr, pstats->rcvcco);
1198 pr_debug(" rntpco=%-7d mpco=%d\n",
1199 pstats->rntpco, pstats->mpco);
1200
1201 /* MACE_MPC */
1202 pr_debug(" mpc=%d\n", pstats->mpc);
1203
1204 /* MACE_RNTPC */
1205 pr_debug(" rntpc=%d\n", pstats->rntpc);
1206
1207 /* MACE_RCVCC */
1208 pr_debug(" rcvcc=%d\n", pstats->rcvcc);
1209
1210} /* pr_mace_stats */
1211
1212/* ----------------------------------------------------------------------------
1213update_stats
1214 Update statistics. We change to register window 1, so this
1215 should be run single-threaded if the device is active. This is
1216 expected to be a rare operation, and it's simpler for the rest
1217 of the driver to assume that window 0 is always valid rather
1218 than use a special window-state variable.
1219
1220 oflo & uflo should _never_ occur since it would mean the Xilinx
1221 was not able to transfer data between the MACE FIFO and the
1222 card's SRAM fast enough. If this happens, something is
1223 seriously wrong with the hardware.
1224---------------------------------------------------------------------------- */
1225static void update_stats(unsigned int ioaddr, struct net_device *dev)
1226{
1227 mace_private *lp = netdev_priv(dev);
1228
1229 lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1230 lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1231 lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1232 /* At this point, mace_stats is fully updated for this call.
1233 We may now update the netdev stats. */
1234
1235 /* The MACE has no equivalent for netdev stats field which are commented
1236 out. */
1237
1238 /* dev->stats.multicast; */
1239 dev->stats.collisions =
1240 lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1241 /* Collision: The MACE may retry sending a packet 15 times
1242 before giving up. The retry count is in XMTRC.
1243 Does each retry constitute a collision?
1244 If so, why doesn't the RCVCC record these collisions? */
1245
1246 /* detailed rx_errors: */
1247 dev->stats.rx_length_errors =
1248 lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1249 /* dev->stats.rx_over_errors */
1250 dev->stats.rx_crc_errors = lp->mace_stats.fcs;
1251 dev->stats.rx_frame_errors = lp->mace_stats.fram;
1252 dev->stats.rx_fifo_errors = lp->mace_stats.oflo;
1253 dev->stats.rx_missed_errors =
1254 lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1255
1256 /* detailed tx_errors */
1257 dev->stats.tx_aborted_errors = lp->mace_stats.rtry;
1258 dev->stats.tx_carrier_errors = lp->mace_stats.lcar;
1259 /* LCAR usually results from bad cabling. */
1260 dev->stats.tx_fifo_errors = lp->mace_stats.uflo;
1261 dev->stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1262 /* dev->stats.tx_window_errors; */
1263} /* update_stats */
1264
1265/* ----------------------------------------------------------------------------
1266mace_get_stats
1267 Gathers ethernet statistics from the MACE chip.
1268---------------------------------------------------------------------------- */
1269static struct net_device_stats *mace_get_stats(struct net_device *dev)
1270{
1271 mace_private *lp = netdev_priv(dev);
1272
1273 update_stats(dev->base_addr, dev);
1274
1275 pr_debug("%s: updating the statistics.\n", dev->name);
1276 pr_linux_stats(&dev->stats);
1277 pr_mace_stats(&lp->mace_stats);
1278
1279 return &dev->stats;
1280} /* net_device_stats */
1281
1282/* ----------------------------------------------------------------------------
1283updateCRC
1284 Modified from Am79C90 data sheet.
1285---------------------------------------------------------------------------- */
1286
1287#ifdef BROKEN_MULTICAST
1288
1289static void updateCRC(int *CRC, int bit)
1290{
1291 static const int poly[]={
1292 1,1,1,0, 1,1,0,1,
1293 1,0,1,1, 1,0,0,0,
1294 1,0,0,0, 0,0,1,1,
1295 0,0,1,0, 0,0,0,0
1296 }; /* CRC polynomial. poly[n] = coefficient of the x**n term of the
1297 CRC generator polynomial. */
1298
1299 int j;
1300
1301 /* shift CRC and control bit (CRC[32]) */
1302 for (j = 32; j > 0; j--)
1303 CRC[j] = CRC[j-1];
1304 CRC[0] = 0;
1305
1306 /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1307 if (bit ^ CRC[32])
1308 for (j = 0; j < 32; j++)
1309 CRC[j] ^= poly[j];
1310} /* updateCRC */
1311
1312/* ----------------------------------------------------------------------------
1313BuildLAF
1314 Build logical address filter.
1315 Modified from Am79C90 data sheet.
1316
1317Input
1318 ladrf: logical address filter (contents initialized to 0)
1319 adr: ethernet address
1320---------------------------------------------------------------------------- */
1321static void BuildLAF(int *ladrf, int *adr)
1322{
1323 int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1324
1325 int i, byte; /* temporary array indices */
1326 int hashcode; /* the output object */
1327
1328 CRC[32]=0;
1329
1330 for (byte = 0; byte < 6; byte++)
1331 for (i = 0; i < 8; i++)
1332 updateCRC(CRC, (adr[byte] >> i) & 1);
1333
1334 hashcode = 0;
1335 for (i = 0; i < 6; i++)
1336 hashcode = (hashcode << 1) + CRC[i];
1337
1338 byte = hashcode >> 3;
1339 ladrf[byte] |= (1 << (hashcode & 7));
1340
1341#ifdef PCMCIA_DEBUG
1342 if (0)
1343 printk(KERN_DEBUG " adr =%pM\n", adr);
1344 printk(KERN_DEBUG " hashcode = %d(decimal), ladrf[0:63] =", hashcode);
1345 for (i = 0; i < 8; i++)
1346 pr_cont(" %02X", ladrf[i]);
1347 pr_cont("\n");
1348#endif
1349} /* BuildLAF */
1350
1351/* ----------------------------------------------------------------------------
1352restore_multicast_list
1353 Restores the multicast filter for MACE chip to the last
1354 set_multicast_list() call.
1355
1356Input
1357 multicast_num_addrs
1358 multicast_ladrf[]
1359---------------------------------------------------------------------------- */
1360static void restore_multicast_list(struct net_device *dev)
1361{
1362 mace_private *lp = netdev_priv(dev);
1363 int num_addrs = lp->multicast_num_addrs;
1364 int *ladrf = lp->multicast_ladrf;
1365 unsigned int ioaddr = dev->base_addr;
1366 int i;
1367
1368 pr_debug("%s: restoring Rx mode to %d addresses.\n",
1369 dev->name, num_addrs);
1370
1371 if (num_addrs > 0) {
1372
1373 pr_debug("Attempt to restore multicast list detected.\n");
1374
1375 mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1376 /* Poll ADDRCHG bit */
1377 while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1378 ;
1379 /* Set LADRF register */
1380 for (i = 0; i < MACE_LADRF_LEN; i++)
1381 mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1382
1383 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1384 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1385
1386 } else if (num_addrs < 0) {
1387
1388 /* Promiscuous mode: receive all packets */
1389 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1390 mace_write(lp, ioaddr, MACE_MACCC,
1391 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1392 );
1393
1394 } else {
1395
1396 /* Normal mode */
1397 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1398 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1399
1400 }
1401} /* restore_multicast_list */
1402
1403/* ----------------------------------------------------------------------------
1404set_multicast_list
1405 Set or clear the multicast filter for this adaptor.
1406
1407Input
1408 num_addrs == -1 Promiscuous mode, receive all packets
1409 num_addrs == 0 Normal mode, clear multicast list
1410 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1411 best-effort filtering.
1412Output
1413 multicast_num_addrs
1414 multicast_ladrf[]
1415---------------------------------------------------------------------------- */
1416
1417static void set_multicast_list(struct net_device *dev)
1418{
1419 mace_private *lp = netdev_priv(dev);
1420 int adr[ETH_ALEN] = {0}; /* Ethernet address */
1421 struct netdev_hw_addr *ha;
1422
1423#ifdef PCMCIA_DEBUG
1424 {
1425 static int old;
1426 if (netdev_mc_count(dev) != old) {
1427 old = netdev_mc_count(dev);
1428 pr_debug("%s: setting Rx mode to %d addresses.\n",
1429 dev->name, old);
1430 }
1431 }
1432#endif
1433
1434 /* Set multicast_num_addrs. */
1435 lp->multicast_num_addrs = netdev_mc_count(dev);
1436
1437 /* Set multicast_ladrf. */
1438 if (num_addrs > 0) {
1439 /* Calculate multicast logical address filter */
1440 memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1441 netdev_for_each_mc_addr(ha, dev) {
1442 memcpy(adr, ha->addr, ETH_ALEN);
1443 BuildLAF(lp->multicast_ladrf, adr);
1444 }
1445 }
1446
1447 restore_multicast_list(dev);
1448
1449} /* set_multicast_list */
1450
1451#endif /* BROKEN_MULTICAST */
1452
1453static void restore_multicast_list(struct net_device *dev)
1454{
1455 unsigned int ioaddr = dev->base_addr;
1456 mace_private *lp = netdev_priv(dev);
1457
1458 pr_debug("%s: restoring Rx mode to %d addresses.\n", dev->name,
1459 lp->multicast_num_addrs);
1460
1461 if (dev->flags & IFF_PROMISC) {
1462 /* Promiscuous mode: receive all packets */
1463 mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1464 mace_write(lp, ioaddr, MACE_MACCC,
1465 MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1466 );
1467 } else {
1468 /* Normal mode */
1469 mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1470 mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1471 }
1472} /* restore_multicast_list */
1473
1474static void set_multicast_list(struct net_device *dev)
1475{
1476 mace_private *lp = netdev_priv(dev);
1477
1478#ifdef PCMCIA_DEBUG
1479 {
1480 static int old;
1481 if (netdev_mc_count(dev) != old) {
1482 old = netdev_mc_count(dev);
1483 pr_debug("%s: setting Rx mode to %d addresses.\n",
1484 dev->name, old);
1485 }
1486 }
1487#endif
1488
1489 lp->multicast_num_addrs = netdev_mc_count(dev);
1490 restore_multicast_list(dev);
1491
1492} /* set_multicast_list */
1493
1494static const struct pcmcia_device_id nmclan_ids[] = {
1495 PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
1496 PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
1497 PCMCIA_DEVICE_NULL,
1498};
1499MODULE_DEVICE_TABLE(pcmcia, nmclan_ids);
1500
1501static struct pcmcia_driver nmclan_cs_driver = {
1502 .owner = THIS_MODULE,
1503 .name = "nmclan_cs",
1504 .probe = nmclan_probe,
1505 .remove = nmclan_detach,
1506 .id_table = nmclan_ids,
1507 .suspend = nmclan_suspend,
1508 .resume = nmclan_resume,
1509};
1510module_pcmcia_driver(nmclan_cs_driver);