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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 Broadcom
4 */
5
6/**
7 * DOC: VC4 CRTC module
8 *
9 * In VC4, the Pixel Valve is what most closely corresponds to the
10 * DRM's concept of a CRTC. The PV generates video timings from the
11 * encoder's clock plus its configuration. It pulls scaled pixels from
12 * the HVS at that timing, and feeds it to the encoder.
13 *
14 * However, the DRM CRTC also collects the configuration of all the
15 * DRM planes attached to it. As a result, the CRTC is also
16 * responsible for writing the display list for the HVS channel that
17 * the CRTC will use.
18 *
19 * The 2835 has 3 different pixel valves. pv0 in the audio power
20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
21 * image domain can feed either HDMI or the SDTV controller. The
22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
23 * SDTV, etc.) according to which output type is chosen in the mux.
24 *
25 * For power management, the pixel valve's registers are all clocked
26 * by the AXI clock, while the timings and FIFOs make use of the
27 * output-specific clock. Since the encoders also directly consume
28 * the CPRMAN clocks, and know what timings they need, they are the
29 * ones that set the clock.
30 */
31
32#include <linux/clk.h>
33#include <linux/component.h>
34#include <linux/of.h>
35#include <linux/platform_device.h>
36#include <linux/pm_runtime.h>
37
38#include <drm/drm_atomic.h>
39#include <drm/drm_atomic_helper.h>
40#include <drm/drm_atomic_uapi.h>
41#include <drm/drm_fb_dma_helper.h>
42#include <drm/drm_framebuffer.h>
43#include <drm/drm_drv.h>
44#include <drm/drm_print.h>
45#include <drm/drm_probe_helper.h>
46#include <drm/drm_vblank.h>
47
48#include "vc4_drv.h"
49#include "vc4_hdmi.h"
50#include "vc4_regs.h"
51
52#define HVS_FIFO_LATENCY_PIX 6
53
54#define CRTC_WRITE(offset, val) \
55 do { \
56 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
57 writel(val, vc4_crtc->regs + (offset)); \
58 } while (0)
59
60#define CRTC_READ(offset) \
61 ({ \
62 kunit_fail_current_test("Accessing a register in a unit test!\n"); \
63 readl(vc4_crtc->regs + (offset)); \
64 })
65
66static const struct debugfs_reg32 crtc_regs[] = {
67 VC4_REG32(PV_CONTROL),
68 VC4_REG32(PV_V_CONTROL),
69 VC4_REG32(PV_VSYNCD_EVEN),
70 VC4_REG32(PV_HORZA),
71 VC4_REG32(PV_HORZB),
72 VC4_REG32(PV_VERTA),
73 VC4_REG32(PV_VERTB),
74 VC4_REG32(PV_VERTA_EVEN),
75 VC4_REG32(PV_VERTB_EVEN),
76 VC4_REG32(PV_INTEN),
77 VC4_REG32(PV_INTSTAT),
78 VC4_REG32(PV_STAT),
79 VC4_REG32(PV_HACT_ACT),
80};
81
82static unsigned int
83vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel)
84{
85 struct vc4_hvs *hvs = vc4->hvs;
86 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel));
87 /* Top/base are supposed to be 4-pixel aligned, but the
88 * Raspberry Pi firmware fills the low bits (which are
89 * presumably ignored).
90 */
91 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
92 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
93
94 return top - base + 4;
95}
96
97static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc,
98 bool in_vblank_irq,
99 int *vpos, int *hpos,
100 ktime_t *stime, ktime_t *etime,
101 const struct drm_display_mode *mode)
102{
103 struct drm_device *dev = crtc->dev;
104 struct vc4_dev *vc4 = to_vc4_dev(dev);
105 struct vc4_hvs *hvs = vc4->hvs;
106 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
107 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state);
108 unsigned int channel = vc4_crtc_state->assigned_channel;
109 unsigned int cob_size;
110 u32 val;
111 int fifo_lines;
112 int vblank_lines;
113 bool ret = false;
114
115 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
116
117 /* Get optional system timestamp before query. */
118 if (stime)
119 *stime = ktime_get();
120
121 /*
122 * Read vertical scanline which is currently composed for our
123 * pixelvalve by the HVS, and also the scaler status.
124 */
125 val = HVS_READ(SCALER_DISPSTATX(channel));
126
127 /* Get optional system timestamp after query. */
128 if (etime)
129 *etime = ktime_get();
130
131 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
132
133 /* Vertical position of hvs composed scanline. */
134 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
135 *hpos = 0;
136
137 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
138 *vpos /= 2;
139
140 /* Use hpos to correct for field offset in interlaced mode. */
141 if (vc4_hvs_get_fifo_frame_count(hvs, channel) % 2)
142 *hpos += mode->crtc_htotal / 2;
143 }
144
145 cob_size = vc4_crtc_get_cob_allocation(vc4, channel);
146 /* This is the offset we need for translating hvs -> pv scanout pos. */
147 fifo_lines = cob_size / mode->crtc_hdisplay;
148
149 if (fifo_lines > 0)
150 ret = true;
151
152 /* HVS more than fifo_lines into frame for compositing? */
153 if (*vpos > fifo_lines) {
154 /*
155 * We are in active scanout and can get some meaningful results
156 * from HVS. The actual PV scanout can not trail behind more
157 * than fifo_lines as that is the fifo's capacity. Assume that
158 * in active scanout the HVS and PV work in lockstep wrt. HVS
159 * refilling the fifo and PV consuming from the fifo, ie.
160 * whenever the PV consumes and frees up a scanline in the
161 * fifo, the HVS will immediately refill it, therefore
162 * incrementing vpos. Therefore we choose HVS read position -
163 * fifo size in scanlines as a estimate of the real scanout
164 * position of the PV.
165 */
166 *vpos -= fifo_lines + 1;
167
168 return ret;
169 }
170
171 /*
172 * Less: This happens when we are in vblank and the HVS, after getting
173 * the VSTART restart signal from the PV, just started refilling its
174 * fifo with new lines from the top-most lines of the new framebuffers.
175 * The PV does not scan out in vblank, so does not remove lines from
176 * the fifo, so the fifo will be full quickly and the HVS has to pause.
177 * We can't get meaningful readings wrt. scanline position of the PV
178 * and need to make things up in a approximative but consistent way.
179 */
180 vblank_lines = mode->vtotal - mode->vdisplay;
181
182 if (in_vblank_irq) {
183 /*
184 * Assume the irq handler got called close to first
185 * line of vblank, so PV has about a full vblank
186 * scanlines to go, and as a base timestamp use the
187 * one taken at entry into vblank irq handler, so it
188 * is not affected by random delays due to lock
189 * contention on event_lock or vblank_time lock in
190 * the core.
191 */
192 *vpos = -vblank_lines;
193
194 if (stime)
195 *stime = vc4_crtc->t_vblank;
196 if (etime)
197 *etime = vc4_crtc->t_vblank;
198
199 /*
200 * If the HVS fifo is not yet full then we know for certain
201 * we are at the very beginning of vblank, as the hvs just
202 * started refilling, and the stime and etime timestamps
203 * truly correspond to start of vblank.
204 *
205 * Unfortunately there's no way to report this to upper levels
206 * and make it more useful.
207 */
208 } else {
209 /*
210 * No clue where we are inside vblank. Return a vpos of zero,
211 * which will cause calling code to just return the etime
212 * timestamp uncorrected. At least this is no worse than the
213 * standard fallback.
214 */
215 *vpos = 0;
216 }
217
218 return ret;
219}
220
221static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
222{
223 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
224 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
225 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
226 u32 fifo_len_bytes = pv_data->fifo_depth;
227
228 /*
229 * Pixels are pulled from the HVS if the number of bytes is
230 * lower than the FIFO full level.
231 *
232 * The latency of the pixel fetch mechanism is 6 pixels, so we
233 * need to convert those 6 pixels in bytes, depending on the
234 * format, and then subtract that from the length of the FIFO
235 * to make sure we never end up in a situation where the FIFO
236 * is full.
237 */
238 switch (format) {
239 case PV_CONTROL_FORMAT_DSIV_16:
240 case PV_CONTROL_FORMAT_DSIC_16:
241 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX;
242 case PV_CONTROL_FORMAT_DSIV_18:
243 return fifo_len_bytes - 14;
244 case PV_CONTROL_FORMAT_24:
245 case PV_CONTROL_FORMAT_DSIV_24:
246 default:
247 /*
248 * For some reason, the pixelvalve4 doesn't work with
249 * the usual formula and will only work with 32.
250 */
251 if (crtc_data->hvs_output == 5)
252 return 32;
253
254 /*
255 * It looks like in some situations, we will overflow
256 * the PixelValve FIFO (with the bit 10 of PV stat being
257 * set) and stall the HVS / PV, eventually resulting in
258 * a page flip timeout.
259 *
260 * Displaying the video overlay during a playback with
261 * Kodi on an RPi3 seems to be a great solution with a
262 * failure rate around 50%.
263 *
264 * Removing 1 from the FIFO full level however
265 * seems to completely remove that issue.
266 */
267 if (vc4->gen == VC4_GEN_4)
268 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
269
270 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
271 }
272}
273
274static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
275 u32 format)
276{
277 u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
278 u32 ret = 0;
279
280 ret |= VC4_SET_FIELD((level >> 6),
281 PV5_CONTROL_FIFO_LEVEL_HIGH);
282
283 return ret | VC4_SET_FIELD(level & 0x3f,
284 PV_CONTROL_FIFO_LEVEL);
285}
286
287/*
288 * Returns the encoder attached to the CRTC.
289 *
290 * VC4 can only scan out to one encoder at a time, while the DRM core
291 * allows drivers to push pixels to more than one encoder from the
292 * same CRTC.
293 */
294struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc,
295 struct drm_crtc_state *state)
296{
297 struct drm_encoder *encoder;
298
299 WARN_ON(hweight32(state->encoder_mask) > 1);
300
301 drm_for_each_encoder_mask(encoder, crtc->dev, state->encoder_mask)
302 return encoder;
303
304 return NULL;
305}
306
307static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc)
308{
309 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
310 struct drm_device *dev = crtc->dev;
311 int idx;
312
313 if (!drm_dev_enter(dev, &idx))
314 return;
315
316 /* The PV needs to be disabled before it can be flushed */
317 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN);
318 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
319
320 drm_dev_exit(idx);
321}
322
323static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_encoder *encoder,
324 struct drm_atomic_state *state)
325{
326 struct drm_device *dev = crtc->dev;
327 struct vc4_dev *vc4 = to_vc4_dev(dev);
328 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
329 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
330 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
331 struct drm_crtc_state *crtc_state = crtc->state;
332 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
333 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
334 bool is_hdmi = vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0 ||
335 vc4_encoder->type == VC4_ENCODER_TYPE_HDMI1;
336 u32 pixel_rep = ((mode->flags & DRM_MODE_FLAG_DBLCLK) && !is_hdmi) ? 2 : 1;
337 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
338 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
339 bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
340 bool is_vec = vc4_encoder->type == VC4_ENCODER_TYPE_VEC;
341 u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
342 u8 ppc = pv_data->pixels_per_clock;
343
344 u16 vert_bp = mode->crtc_vtotal - mode->crtc_vsync_end;
345 u16 vert_sync = mode->crtc_vsync_end - mode->crtc_vsync_start;
346 u16 vert_fp = mode->crtc_vsync_start - mode->crtc_vdisplay;
347
348 bool debug_dump_regs = false;
349 int idx;
350
351 if (!drm_dev_enter(dev, &idx))
352 return;
353
354 if (debug_dump_regs) {
355 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
356 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n",
357 drm_crtc_index(crtc));
358 drm_print_regset32(&p, &vc4_crtc->regset);
359 }
360
361 vc4_crtc_pixelvalve_reset(crtc);
362
363 CRTC_WRITE(PV_HORZA,
364 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc,
365 PV_HORZA_HBP) |
366 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc,
367 PV_HORZA_HSYNC));
368
369 CRTC_WRITE(PV_HORZB,
370 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc,
371 PV_HORZB_HFP) |
372 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc,
373 PV_HORZB_HACTIVE));
374
375 if (interlace) {
376 bool odd_field_first = false;
377 u32 field_delay = mode->htotal * pixel_rep / (2 * ppc);
378 u16 vert_bp_even = vert_bp;
379 u16 vert_fp_even = vert_fp;
380
381 if (is_vec) {
382 /* VEC (composite output) */
383 ++field_delay;
384 if (mode->htotal == 858) {
385 /* 525-line mode (NTSC or PAL-M) */
386 odd_field_first = true;
387 }
388 }
389
390 if (odd_field_first)
391 ++vert_fp_even;
392 else
393 ++vert_bp;
394
395 CRTC_WRITE(PV_VERTA_EVEN,
396 VC4_SET_FIELD(vert_bp_even, PV_VERTA_VBP) |
397 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
398 CRTC_WRITE(PV_VERTB_EVEN,
399 VC4_SET_FIELD(vert_fp_even, PV_VERTB_VFP) |
400 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
401
402 /* We set up first field even mode for HDMI and VEC's PAL.
403 * For NTSC, we need first field odd.
404 */
405 CRTC_WRITE(PV_V_CONTROL,
406 PV_VCONTROL_CONTINUOUS |
407 (is_dsi ? PV_VCONTROL_DSI : 0) |
408 PV_VCONTROL_INTERLACE |
409 (odd_field_first
410 ? PV_VCONTROL_ODD_FIRST
411 : VC4_SET_FIELD(field_delay,
412 PV_VCONTROL_ODD_DELAY)));
413 CRTC_WRITE(PV_VSYNCD_EVEN,
414 (odd_field_first ? field_delay : 0));
415 } else {
416 CRTC_WRITE(PV_V_CONTROL,
417 PV_VCONTROL_CONTINUOUS |
418 (is_dsi ? PV_VCONTROL_DSI : 0));
419 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
420 }
421
422 CRTC_WRITE(PV_VERTA,
423 VC4_SET_FIELD(vert_bp, PV_VERTA_VBP) |
424 VC4_SET_FIELD(vert_sync, PV_VERTA_VSYNC));
425 CRTC_WRITE(PV_VERTB,
426 VC4_SET_FIELD(vert_fp, PV_VERTB_VFP) |
427 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
428
429 if (is_dsi)
430 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
431
432 if (vc4->gen == VC4_GEN_5)
433 CRTC_WRITE(PV_MUX_CFG,
434 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP,
435 PV_MUX_CFG_RGB_PIXEL_MUX_MODE));
436
437 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR |
438 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
439 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
440 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
441 PV_CONTROL_CLR_AT_START |
442 PV_CONTROL_TRIGGER_UNDERFLOW |
443 PV_CONTROL_WAIT_HSTART |
444 VC4_SET_FIELD(vc4_encoder->clock_select,
445 PV_CONTROL_CLK_SELECT));
446
447 if (debug_dump_regs) {
448 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev);
449 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n",
450 drm_crtc_index(crtc));
451 drm_print_regset32(&p, &vc4_crtc->regset);
452 }
453
454 drm_dev_exit(idx);
455}
456
457static void require_hvs_enabled(struct drm_device *dev)
458{
459 struct vc4_dev *vc4 = to_vc4_dev(dev);
460 struct vc4_hvs *hvs = vc4->hvs;
461
462 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
463 SCALER_DISPCTRL_ENABLE);
464}
465
466static int vc4_crtc_disable(struct drm_crtc *crtc,
467 struct drm_encoder *encoder,
468 struct drm_atomic_state *state,
469 unsigned int channel)
470{
471 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
472 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
473 struct drm_device *dev = crtc->dev;
474 struct vc4_dev *vc4 = to_vc4_dev(dev);
475 int idx, ret;
476
477 if (!drm_dev_enter(dev, &idx))
478 return -ENODEV;
479
480 CRTC_WRITE(PV_V_CONTROL,
481 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
482 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
483 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
484
485 /*
486 * This delay is needed to avoid to get a pixel stuck in an
487 * unflushable FIFO between the pixelvalve and the HDMI
488 * controllers on the BCM2711.
489 *
490 * Timing is fairly sensitive here, so mdelay is the safest
491 * approach.
492 *
493 * If it was to be reworked, the stuck pixel happens on a
494 * BCM2711 when changing mode with a good probability, so a
495 * script that changes mode on a regular basis should trigger
496 * the bug after less than 10 attempts. It manifests itself with
497 * every pixels being shifted by one to the right, and thus the
498 * last pixel of a line actually being displayed as the first
499 * pixel on the next line.
500 */
501 mdelay(20);
502
503 if (vc4_encoder && vc4_encoder->post_crtc_disable)
504 vc4_encoder->post_crtc_disable(encoder, state);
505
506 vc4_crtc_pixelvalve_reset(crtc);
507 vc4_hvs_stop_channel(vc4->hvs, channel);
508
509 if (vc4_encoder && vc4_encoder->post_crtc_powerdown)
510 vc4_encoder->post_crtc_powerdown(encoder, state);
511
512 drm_dev_exit(idx);
513
514 return 0;
515}
516
517int vc4_crtc_disable_at_boot(struct drm_crtc *crtc)
518{
519 struct drm_device *drm = crtc->dev;
520 struct vc4_dev *vc4 = to_vc4_dev(drm);
521 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
522 enum vc4_encoder_type encoder_type;
523 const struct vc4_pv_data *pv_data;
524 struct drm_encoder *encoder;
525 struct vc4_hdmi *vc4_hdmi;
526 unsigned encoder_sel;
527 int channel;
528 int ret;
529
530 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
531 "brcm,bcm2711-pixelvalve2") ||
532 of_device_is_compatible(vc4_crtc->pdev->dev.of_node,
533 "brcm,bcm2711-pixelvalve4")))
534 return 0;
535
536 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN))
537 return 0;
538
539 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN))
540 return 0;
541
542 channel = vc4_hvs_get_fifo_from_output(vc4->hvs, vc4_crtc->data->hvs_output);
543 if (channel < 0)
544 return 0;
545
546 encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT);
547 if (WARN_ON(encoder_sel != 0))
548 return 0;
549
550 pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
551 encoder_type = pv_data->encoder_types[encoder_sel];
552 encoder = vc4_find_encoder_by_type(drm, encoder_type);
553 if (WARN_ON(!encoder))
554 return 0;
555
556 vc4_hdmi = encoder_to_vc4_hdmi(encoder);
557 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
558 if (ret)
559 return ret;
560
561 ret = vc4_crtc_disable(crtc, encoder, NULL, channel);
562 if (ret)
563 return ret;
564
565 /*
566 * post_crtc_powerdown will have called pm_runtime_put, so we
567 * don't need it here otherwise we'll get the reference counting
568 * wrong.
569 */
570
571 return 0;
572}
573
574void vc4_crtc_send_vblank(struct drm_crtc *crtc)
575{
576 struct drm_device *dev = crtc->dev;
577 unsigned long flags;
578
579 if (!crtc->state || !crtc->state->event)
580 return;
581
582 spin_lock_irqsave(&dev->event_lock, flags);
583 drm_crtc_send_vblank_event(crtc, crtc->state->event);
584 crtc->state->event = NULL;
585 spin_unlock_irqrestore(&dev->event_lock, flags);
586}
587
588static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
589 struct drm_atomic_state *state)
590{
591 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state,
592 crtc);
593 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state);
594 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, old_state);
595 struct drm_device *dev = crtc->dev;
596
597 drm_dbg(dev, "Disabling CRTC %s (%u) connected to Encoder %s (%u)",
598 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
599
600 require_hvs_enabled(dev);
601
602 /* Disable vblank irq handling before crtc is disabled. */
603 drm_crtc_vblank_off(crtc);
604
605 vc4_crtc_disable(crtc, encoder, state, old_vc4_state->assigned_channel);
606
607 /*
608 * Make sure we issue a vblank event after disabling the CRTC if
609 * someone was waiting it.
610 */
611 vc4_crtc_send_vblank(crtc);
612}
613
614static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
615 struct drm_atomic_state *state)
616{
617 struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state,
618 crtc);
619 struct drm_device *dev = crtc->dev;
620 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
621 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc, new_state);
622 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
623 int idx;
624
625 drm_dbg(dev, "Enabling CRTC %s (%u) connected to Encoder %s (%u)",
626 crtc->name, crtc->base.id, encoder->name, encoder->base.id);
627
628 if (!drm_dev_enter(dev, &idx))
629 return;
630
631 require_hvs_enabled(dev);
632
633 /* Enable vblank irq handling before crtc is started otherwise
634 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
635 */
636 drm_crtc_vblank_on(crtc);
637
638 vc4_hvs_atomic_enable(crtc, state);
639
640 if (vc4_encoder->pre_crtc_configure)
641 vc4_encoder->pre_crtc_configure(encoder, state);
642
643 vc4_crtc_config_pv(crtc, encoder, state);
644
645 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);
646
647 if (vc4_encoder->pre_crtc_enable)
648 vc4_encoder->pre_crtc_enable(encoder, state);
649
650 /* When feeding the transposer block the pixelvalve is unneeded and
651 * should not be enabled.
652 */
653 CRTC_WRITE(PV_V_CONTROL,
654 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
655
656 if (vc4_encoder->post_crtc_enable)
657 vc4_encoder->post_crtc_enable(encoder, state);
658
659 drm_dev_exit(idx);
660}
661
662static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
663 const struct drm_display_mode *mode)
664{
665 /* Do not allow doublescan modes from user space */
666 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
667 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
668 crtc->base.id);
669 return MODE_NO_DBLESCAN;
670 }
671
672 return MODE_OK;
673}
674
675void vc4_crtc_get_margins(struct drm_crtc_state *state,
676 unsigned int *left, unsigned int *right,
677 unsigned int *top, unsigned int *bottom)
678{
679 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
680 struct drm_connector_state *conn_state;
681 struct drm_connector *conn;
682 int i;
683
684 *left = vc4_state->margins.left;
685 *right = vc4_state->margins.right;
686 *top = vc4_state->margins.top;
687 *bottom = vc4_state->margins.bottom;
688
689 /* We have to interate over all new connector states because
690 * vc4_crtc_get_margins() might be called before
691 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state
692 * might be outdated.
693 */
694 for_each_new_connector_in_state(state->state, conn, conn_state, i) {
695 if (conn_state->crtc != state->crtc)
696 continue;
697
698 *left = conn_state->tv.margins.left;
699 *right = conn_state->tv.margins.right;
700 *top = conn_state->tv.margins.top;
701 *bottom = conn_state->tv.margins.bottom;
702 break;
703 }
704}
705
706int vc4_crtc_atomic_check(struct drm_crtc *crtc,
707 struct drm_atomic_state *state)
708{
709 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
710 crtc);
711 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state);
712 struct drm_connector *conn;
713 struct drm_connector_state *conn_state;
714 struct drm_encoder *encoder;
715 int ret, i;
716
717 ret = vc4_hvs_atomic_check(crtc, state);
718 if (ret)
719 return ret;
720
721 encoder = vc4_get_crtc_encoder(crtc, crtc_state);
722 if (encoder) {
723 const struct drm_display_mode *mode = &crtc_state->adjusted_mode;
724 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
725
726 if (vc4_encoder->type == VC4_ENCODER_TYPE_HDMI0) {
727 vc4_state->hvs_load = max(mode->clock * mode->hdisplay / mode->htotal + 8000,
728 mode->clock * 9 / 10) * 1000;
729 } else {
730 vc4_state->hvs_load = mode->clock * 1000;
731 }
732 }
733
734 for_each_new_connector_in_state(state, conn, conn_state,
735 i) {
736 if (conn_state->crtc != crtc)
737 continue;
738
739 if (memcmp(&vc4_state->margins, &conn_state->tv.margins,
740 sizeof(vc4_state->margins))) {
741 memcpy(&vc4_state->margins, &conn_state->tv.margins,
742 sizeof(vc4_state->margins));
743
744 /*
745 * Need to force the dlist entries for all planes to be
746 * updated so that the dest rectangles are changed.
747 */
748 crtc_state->zpos_changed = true;
749 }
750 break;
751 }
752
753 return 0;
754}
755
756static int vc4_enable_vblank(struct drm_crtc *crtc)
757{
758 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
759 struct drm_device *dev = crtc->dev;
760 int idx;
761
762 if (!drm_dev_enter(dev, &idx))
763 return -ENODEV;
764
765 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
766
767 drm_dev_exit(idx);
768
769 return 0;
770}
771
772static void vc4_disable_vblank(struct drm_crtc *crtc)
773{
774 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
775 struct drm_device *dev = crtc->dev;
776 int idx;
777
778 if (!drm_dev_enter(dev, &idx))
779 return;
780
781 CRTC_WRITE(PV_INTEN, 0);
782
783 drm_dev_exit(idx);
784}
785
786static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
787{
788 struct drm_crtc *crtc = &vc4_crtc->base;
789 struct drm_device *dev = crtc->dev;
790 struct vc4_dev *vc4 = to_vc4_dev(dev);
791 struct vc4_hvs *hvs = vc4->hvs;
792 u32 chan = vc4_crtc->current_hvs_channel;
793 unsigned long flags;
794
795 spin_lock_irqsave(&dev->event_lock, flags);
796 spin_lock(&vc4_crtc->irq_lock);
797 if (vc4_crtc->event &&
798 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) ||
799 vc4_crtc->feeds_txp)) {
800 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
801 vc4_crtc->event = NULL;
802 drm_crtc_vblank_put(crtc);
803
804 /* Wait for the page flip to unmask the underrun to ensure that
805 * the display list was updated by the hardware. Before that
806 * happens, the HVS will be using the previous display list with
807 * the CRTC and encoder already reconfigured, leading to
808 * underruns. This can be seen when reconfiguring the CRTC.
809 */
810 vc4_hvs_unmask_underrun(hvs, chan);
811 }
812 spin_unlock(&vc4_crtc->irq_lock);
813 spin_unlock_irqrestore(&dev->event_lock, flags);
814}
815
816void vc4_crtc_handle_vblank(struct vc4_crtc *crtc)
817{
818 crtc->t_vblank = ktime_get();
819 drm_crtc_handle_vblank(&crtc->base);
820 vc4_crtc_handle_page_flip(crtc);
821}
822
823static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
824{
825 struct vc4_crtc *vc4_crtc = data;
826 u32 stat = CRTC_READ(PV_INTSTAT);
827 irqreturn_t ret = IRQ_NONE;
828
829 if (stat & PV_INT_VFP_START) {
830 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
831 vc4_crtc_handle_vblank(vc4_crtc);
832 ret = IRQ_HANDLED;
833 }
834
835 return ret;
836}
837
838struct vc4_async_flip_state {
839 struct drm_crtc *crtc;
840 struct drm_framebuffer *fb;
841 struct drm_framebuffer *old_fb;
842 struct drm_pending_vblank_event *event;
843
844 union {
845 struct dma_fence_cb fence;
846 struct vc4_seqno_cb seqno;
847 } cb;
848};
849
850/* Called when the V3D execution for the BO being flipped to is done, so that
851 * we can actually update the plane's address to point to it.
852 */
853static void
854vc4_async_page_flip_complete(struct vc4_async_flip_state *flip_state)
855{
856 struct drm_crtc *crtc = flip_state->crtc;
857 struct drm_device *dev = crtc->dev;
858 struct drm_plane *plane = crtc->primary;
859
860 vc4_plane_async_set_fb(plane, flip_state->fb);
861 if (flip_state->event) {
862 unsigned long flags;
863
864 spin_lock_irqsave(&dev->event_lock, flags);
865 drm_crtc_send_vblank_event(crtc, flip_state->event);
866 spin_unlock_irqrestore(&dev->event_lock, flags);
867 }
868
869 drm_crtc_vblank_put(crtc);
870 drm_framebuffer_put(flip_state->fb);
871
872 if (flip_state->old_fb)
873 drm_framebuffer_put(flip_state->old_fb);
874
875 kfree(flip_state);
876}
877
878static void vc4_async_page_flip_seqno_complete(struct vc4_seqno_cb *cb)
879{
880 struct vc4_async_flip_state *flip_state =
881 container_of(cb, struct vc4_async_flip_state, cb.seqno);
882 struct vc4_bo *bo = NULL;
883
884 if (flip_state->old_fb) {
885 struct drm_gem_dma_object *dma_bo =
886 drm_fb_dma_get_gem_obj(flip_state->old_fb, 0);
887 bo = to_vc4_bo(&dma_bo->base);
888 }
889
890 vc4_async_page_flip_complete(flip_state);
891
892 /*
893 * Decrement the BO usecnt in order to keep the inc/dec
894 * calls balanced when the planes are updated through
895 * the async update path.
896 *
897 * FIXME: we should move to generic async-page-flip when
898 * it's available, so that we can get rid of this
899 * hand-made cleanup_fb() logic.
900 */
901 if (bo)
902 vc4_bo_dec_usecnt(bo);
903}
904
905static void vc4_async_page_flip_fence_complete(struct dma_fence *fence,
906 struct dma_fence_cb *cb)
907{
908 struct vc4_async_flip_state *flip_state =
909 container_of(cb, struct vc4_async_flip_state, cb.fence);
910
911 vc4_async_page_flip_complete(flip_state);
912 dma_fence_put(fence);
913}
914
915static int vc4_async_set_fence_cb(struct drm_device *dev,
916 struct vc4_async_flip_state *flip_state)
917{
918 struct drm_framebuffer *fb = flip_state->fb;
919 struct drm_gem_dma_object *dma_bo = drm_fb_dma_get_gem_obj(fb, 0);
920 struct vc4_dev *vc4 = to_vc4_dev(dev);
921 struct dma_fence *fence;
922 int ret;
923
924 if (vc4->gen == VC4_GEN_4) {
925 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
926
927 return vc4_queue_seqno_cb(dev, &flip_state->cb.seqno, bo->seqno,
928 vc4_async_page_flip_seqno_complete);
929 }
930
931 ret = dma_resv_get_singleton(dma_bo->base.resv, DMA_RESV_USAGE_READ, &fence);
932 if (ret)
933 return ret;
934
935 /* If there's no fence, complete the page flip immediately */
936 if (!fence) {
937 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
938 return 0;
939 }
940
941 /* If the fence has already been completed, complete the page flip */
942 if (dma_fence_add_callback(fence, &flip_state->cb.fence,
943 vc4_async_page_flip_fence_complete))
944 vc4_async_page_flip_fence_complete(fence, &flip_state->cb.fence);
945
946 return 0;
947}
948
949static int
950vc4_async_page_flip_common(struct drm_crtc *crtc,
951 struct drm_framebuffer *fb,
952 struct drm_pending_vblank_event *event,
953 uint32_t flags)
954{
955 struct drm_device *dev = crtc->dev;
956 struct drm_plane *plane = crtc->primary;
957 struct vc4_async_flip_state *flip_state;
958
959 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
960 if (!flip_state)
961 return -ENOMEM;
962
963 drm_framebuffer_get(fb);
964 flip_state->fb = fb;
965 flip_state->crtc = crtc;
966 flip_state->event = event;
967
968 /* Save the current FB before it's replaced by the new one in
969 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
970 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
971 * it consistent.
972 * FIXME: we should move to generic async-page-flip when it's
973 * available, so that we can get rid of this hand-made cleanup_fb()
974 * logic.
975 */
976 flip_state->old_fb = plane->state->fb;
977 if (flip_state->old_fb)
978 drm_framebuffer_get(flip_state->old_fb);
979
980 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
981
982 /* Immediately update the plane's legacy fb pointer, so that later
983 * modeset prep sees the state that will be present when the semaphore
984 * is released.
985 */
986 drm_atomic_set_fb_for_plane(plane->state, fb);
987
988 vc4_async_set_fence_cb(dev, flip_state);
989
990 /* Driver takes ownership of state on successful async commit. */
991 return 0;
992}
993
994/* Implements async (non-vblank-synced) page flips.
995 *
996 * The page flip ioctl needs to return immediately, so we grab the
997 * modeset semaphore on the pipe, and queue the address update for
998 * when V3D is done with the BO being flipped to.
999 */
1000static int vc4_async_page_flip(struct drm_crtc *crtc,
1001 struct drm_framebuffer *fb,
1002 struct drm_pending_vblank_event *event,
1003 uint32_t flags)
1004{
1005 struct drm_device *dev = crtc->dev;
1006 struct vc4_dev *vc4 = to_vc4_dev(dev);
1007 struct drm_gem_dma_object *dma_bo = drm_fb_dma_get_gem_obj(fb, 0);
1008 struct vc4_bo *bo = to_vc4_bo(&dma_bo->base);
1009 int ret;
1010
1011 if (WARN_ON_ONCE(vc4->gen > VC4_GEN_4))
1012 return -ENODEV;
1013
1014 /*
1015 * Increment the BO usecnt here, so that we never end up with an
1016 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
1017 * plane is later updated through the non-async path.
1018 *
1019 * FIXME: we should move to generic async-page-flip when
1020 * it's available, so that we can get rid of this
1021 * hand-made prepare_fb() logic.
1022 */
1023 ret = vc4_bo_inc_usecnt(bo);
1024 if (ret)
1025 return ret;
1026
1027 ret = vc4_async_page_flip_common(crtc, fb, event, flags);
1028 if (ret) {
1029 vc4_bo_dec_usecnt(bo);
1030 return ret;
1031 }
1032
1033 return 0;
1034}
1035
1036static int vc5_async_page_flip(struct drm_crtc *crtc,
1037 struct drm_framebuffer *fb,
1038 struct drm_pending_vblank_event *event,
1039 uint32_t flags)
1040{
1041 return vc4_async_page_flip_common(crtc, fb, event, flags);
1042}
1043
1044int vc4_page_flip(struct drm_crtc *crtc,
1045 struct drm_framebuffer *fb,
1046 struct drm_pending_vblank_event *event,
1047 uint32_t flags,
1048 struct drm_modeset_acquire_ctx *ctx)
1049{
1050 if (flags & DRM_MODE_PAGE_FLIP_ASYNC) {
1051 struct drm_device *dev = crtc->dev;
1052 struct vc4_dev *vc4 = to_vc4_dev(dev);
1053
1054 if (vc4->gen > VC4_GEN_4)
1055 return vc5_async_page_flip(crtc, fb, event, flags);
1056 else
1057 return vc4_async_page_flip(crtc, fb, event, flags);
1058 } else {
1059 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
1060 }
1061}
1062
1063struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
1064{
1065 struct vc4_crtc_state *vc4_state, *old_vc4_state;
1066
1067 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
1068 if (!vc4_state)
1069 return NULL;
1070
1071 old_vc4_state = to_vc4_crtc_state(crtc->state);
1072 vc4_state->margins = old_vc4_state->margins;
1073 vc4_state->assigned_channel = old_vc4_state->assigned_channel;
1074
1075 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
1076 return &vc4_state->base;
1077}
1078
1079void vc4_crtc_destroy_state(struct drm_crtc *crtc,
1080 struct drm_crtc_state *state)
1081{
1082 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
1083 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
1084
1085 if (drm_mm_node_allocated(&vc4_state->mm)) {
1086 unsigned long flags;
1087
1088 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
1089 drm_mm_remove_node(&vc4_state->mm);
1090 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
1091
1092 }
1093
1094 drm_atomic_helper_crtc_destroy_state(crtc, state);
1095}
1096
1097void vc4_crtc_reset(struct drm_crtc *crtc)
1098{
1099 struct vc4_crtc_state *vc4_crtc_state;
1100
1101 if (crtc->state)
1102 vc4_crtc_destroy_state(crtc, crtc->state);
1103
1104 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL);
1105 if (!vc4_crtc_state) {
1106 crtc->state = NULL;
1107 return;
1108 }
1109
1110 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED;
1111 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base);
1112}
1113
1114int vc4_crtc_late_register(struct drm_crtc *crtc)
1115{
1116 struct drm_device *drm = crtc->dev;
1117 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1118 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
1119
1120 vc4_debugfs_add_regset32(drm, crtc_data->debugfs_name,
1121 &vc4_crtc->regset);
1122
1123 return 0;
1124}
1125
1126static const struct drm_crtc_funcs vc4_crtc_funcs = {
1127 .set_config = drm_atomic_helper_set_config,
1128 .page_flip = vc4_page_flip,
1129 .set_property = NULL,
1130 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
1131 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
1132 .reset = vc4_crtc_reset,
1133 .atomic_duplicate_state = vc4_crtc_duplicate_state,
1134 .atomic_destroy_state = vc4_crtc_destroy_state,
1135 .enable_vblank = vc4_enable_vblank,
1136 .disable_vblank = vc4_disable_vblank,
1137 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1138 .late_register = vc4_crtc_late_register,
1139};
1140
1141static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
1142 .mode_valid = vc4_crtc_mode_valid,
1143 .atomic_check = vc4_crtc_atomic_check,
1144 .atomic_begin = vc4_hvs_atomic_begin,
1145 .atomic_flush = vc4_hvs_atomic_flush,
1146 .atomic_enable = vc4_crtc_atomic_enable,
1147 .atomic_disable = vc4_crtc_atomic_disable,
1148 .get_scanout_position = vc4_crtc_get_scanout_position,
1149};
1150
1151const struct vc4_pv_data bcm2835_pv0_data = {
1152 .base = {
1153 .name = "pixelvalve-0",
1154 .debugfs_name = "crtc0_regs",
1155 .hvs_available_channels = BIT(0),
1156 .hvs_output = 0,
1157 },
1158 .fifo_depth = 64,
1159 .pixels_per_clock = 1,
1160 .encoder_types = {
1161 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
1162 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
1163 },
1164};
1165
1166const struct vc4_pv_data bcm2835_pv1_data = {
1167 .base = {
1168 .name = "pixelvalve-1",
1169 .debugfs_name = "crtc1_regs",
1170 .hvs_available_channels = BIT(2),
1171 .hvs_output = 2,
1172 },
1173 .fifo_depth = 64,
1174 .pixels_per_clock = 1,
1175 .encoder_types = {
1176 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
1177 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
1178 },
1179};
1180
1181const struct vc4_pv_data bcm2835_pv2_data = {
1182 .base = {
1183 .name = "pixelvalve-2",
1184 .debugfs_name = "crtc2_regs",
1185 .hvs_available_channels = BIT(1),
1186 .hvs_output = 1,
1187 },
1188 .fifo_depth = 64,
1189 .pixels_per_clock = 1,
1190 .encoder_types = {
1191 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0,
1192 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1193 },
1194};
1195
1196const struct vc4_pv_data bcm2711_pv0_data = {
1197 .base = {
1198 .name = "pixelvalve-0",
1199 .debugfs_name = "crtc0_regs",
1200 .hvs_available_channels = BIT(0),
1201 .hvs_output = 0,
1202 },
1203 .fifo_depth = 64,
1204 .pixels_per_clock = 1,
1205 .encoder_types = {
1206 [0] = VC4_ENCODER_TYPE_DSI0,
1207 [1] = VC4_ENCODER_TYPE_DPI,
1208 },
1209};
1210
1211const struct vc4_pv_data bcm2711_pv1_data = {
1212 .base = {
1213 .name = "pixelvalve-1",
1214 .debugfs_name = "crtc1_regs",
1215 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1216 .hvs_output = 3,
1217 },
1218 .fifo_depth = 64,
1219 .pixels_per_clock = 1,
1220 .encoder_types = {
1221 [0] = VC4_ENCODER_TYPE_DSI1,
1222 [1] = VC4_ENCODER_TYPE_SMI,
1223 },
1224};
1225
1226const struct vc4_pv_data bcm2711_pv2_data = {
1227 .base = {
1228 .name = "pixelvalve-2",
1229 .debugfs_name = "crtc2_regs",
1230 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1231 .hvs_output = 4,
1232 },
1233 .fifo_depth = 256,
1234 .pixels_per_clock = 2,
1235 .encoder_types = {
1236 [0] = VC4_ENCODER_TYPE_HDMI0,
1237 },
1238};
1239
1240const struct vc4_pv_data bcm2711_pv3_data = {
1241 .base = {
1242 .name = "pixelvalve-3",
1243 .debugfs_name = "crtc3_regs",
1244 .hvs_available_channels = BIT(1),
1245 .hvs_output = 1,
1246 },
1247 .fifo_depth = 64,
1248 .pixels_per_clock = 1,
1249 .encoder_types = {
1250 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
1251 },
1252};
1253
1254const struct vc4_pv_data bcm2711_pv4_data = {
1255 .base = {
1256 .name = "pixelvalve-4",
1257 .debugfs_name = "crtc4_regs",
1258 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2),
1259 .hvs_output = 5,
1260 },
1261 .fifo_depth = 64,
1262 .pixels_per_clock = 2,
1263 .encoder_types = {
1264 [0] = VC4_ENCODER_TYPE_HDMI1,
1265 },
1266};
1267
1268static const struct of_device_id vc4_crtc_dt_match[] = {
1269 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data },
1270 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data },
1271 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data },
1272 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data },
1273 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data },
1274 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data },
1275 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data },
1276 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data },
1277 {}
1278};
1279
1280static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1281 struct drm_crtc *crtc)
1282{
1283 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1284 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
1285 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types;
1286 struct drm_encoder *encoder;
1287
1288 drm_for_each_encoder(encoder, drm) {
1289 struct vc4_encoder *vc4_encoder;
1290 int i;
1291
1292 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
1293 continue;
1294
1295 vc4_encoder = to_vc4_encoder(encoder);
1296 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) {
1297 if (vc4_encoder->type == encoder_types[i]) {
1298 vc4_encoder->clock_select = i;
1299 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1300 break;
1301 }
1302 }
1303 }
1304}
1305
1306/**
1307 * __vc4_crtc_init - Initializes a CRTC
1308 * @drm: DRM Device
1309 * @pdev: CRTC Platform Device
1310 * @vc4_crtc: CRTC Object to Initialize
1311 * @data: Configuration data associated with this CRTC
1312 * @primary_plane: Primary plane for CRTC
1313 * @crtc_funcs: Callbacks for the new CRTC
1314 * @crtc_helper_funcs: Helper Callbacks for the new CRTC
1315 * @feeds_txp: Is this CRTC connected to the TXP?
1316 *
1317 * Initializes our private CRTC structure. This function is mostly
1318 * relevant for KUnit testing, all other users should use
1319 * vc4_crtc_init() instead.
1320 *
1321 * Returns:
1322 * 0 on success, a negative error code on failure.
1323 */
1324int __vc4_crtc_init(struct drm_device *drm,
1325 struct platform_device *pdev,
1326 struct vc4_crtc *vc4_crtc,
1327 const struct vc4_crtc_data *data,
1328 struct drm_plane *primary_plane,
1329 const struct drm_crtc_funcs *crtc_funcs,
1330 const struct drm_crtc_helper_funcs *crtc_helper_funcs,
1331 bool feeds_txp)
1332{
1333 struct vc4_dev *vc4 = to_vc4_dev(drm);
1334 struct drm_crtc *crtc = &vc4_crtc->base;
1335 unsigned int i;
1336 int ret;
1337
1338 vc4_crtc->data = data;
1339 vc4_crtc->pdev = pdev;
1340 vc4_crtc->feeds_txp = feeds_txp;
1341 spin_lock_init(&vc4_crtc->irq_lock);
1342 ret = drmm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1343 crtc_funcs, data->name);
1344 if (ret)
1345 return ret;
1346
1347 drm_crtc_helper_add(crtc, crtc_helper_funcs);
1348
1349 if (vc4->gen == VC4_GEN_4) {
1350 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1351 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size);
1352
1353 /* We support CTM, but only for one CRTC at a time. It's therefore
1354 * implemented as private driver state in vc4_kms, not here.
1355 */
1356 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size);
1357 }
1358
1359 for (i = 0; i < crtc->gamma_size; i++) {
1360 vc4_crtc->lut_r[i] = i;
1361 vc4_crtc->lut_g[i] = i;
1362 vc4_crtc->lut_b[i] = i;
1363 }
1364
1365 return 0;
1366}
1367
1368int vc4_crtc_init(struct drm_device *drm, struct platform_device *pdev,
1369 struct vc4_crtc *vc4_crtc,
1370 const struct vc4_crtc_data *data,
1371 const struct drm_crtc_funcs *crtc_funcs,
1372 const struct drm_crtc_helper_funcs *crtc_helper_funcs,
1373 bool feeds_txp)
1374{
1375 struct drm_plane *primary_plane;
1376
1377 /* For now, we create just the primary and the legacy cursor
1378 * planes. We should be able to stack more planes on easily,
1379 * but to do that we would need to compute the bandwidth
1380 * requirement of the plane configuration, and reject ones
1381 * that will take too much.
1382 */
1383 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY, 0);
1384 if (IS_ERR(primary_plane)) {
1385 dev_err(drm->dev, "failed to construct primary plane\n");
1386 return PTR_ERR(primary_plane);
1387 }
1388
1389 return __vc4_crtc_init(drm, pdev, vc4_crtc, data, primary_plane,
1390 crtc_funcs, crtc_helper_funcs, feeds_txp);
1391}
1392
1393static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1394{
1395 struct platform_device *pdev = to_platform_device(dev);
1396 struct drm_device *drm = dev_get_drvdata(master);
1397 const struct vc4_pv_data *pv_data;
1398 struct vc4_crtc *vc4_crtc;
1399 struct drm_crtc *crtc;
1400 int ret;
1401
1402 vc4_crtc = drmm_kzalloc(drm, sizeof(*vc4_crtc), GFP_KERNEL);
1403 if (!vc4_crtc)
1404 return -ENOMEM;
1405 crtc = &vc4_crtc->base;
1406
1407 pv_data = of_device_get_match_data(dev);
1408 if (!pv_data)
1409 return -ENODEV;
1410
1411 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1412 if (IS_ERR(vc4_crtc->regs))
1413 return PTR_ERR(vc4_crtc->regs);
1414
1415 vc4_crtc->regset.base = vc4_crtc->regs;
1416 vc4_crtc->regset.regs = crtc_regs;
1417 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs);
1418
1419 ret = vc4_crtc_init(drm, pdev, vc4_crtc, &pv_data->base,
1420 &vc4_crtc_funcs, &vc4_crtc_helper_funcs,
1421 false);
1422 if (ret)
1423 return ret;
1424 vc4_set_crtc_possible_masks(drm, crtc);
1425
1426 CRTC_WRITE(PV_INTEN, 0);
1427 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1428 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1429 vc4_crtc_irq_handler,
1430 IRQF_SHARED,
1431 "vc4 crtc", vc4_crtc);
1432 if (ret)
1433 return ret;
1434
1435 platform_set_drvdata(pdev, vc4_crtc);
1436
1437 return 0;
1438}
1439
1440static void vc4_crtc_unbind(struct device *dev, struct device *master,
1441 void *data)
1442{
1443 struct platform_device *pdev = to_platform_device(dev);
1444 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1445
1446 CRTC_WRITE(PV_INTEN, 0);
1447
1448 platform_set_drvdata(pdev, NULL);
1449}
1450
1451static const struct component_ops vc4_crtc_ops = {
1452 .bind = vc4_crtc_bind,
1453 .unbind = vc4_crtc_unbind,
1454};
1455
1456static int vc4_crtc_dev_probe(struct platform_device *pdev)
1457{
1458 return component_add(&pdev->dev, &vc4_crtc_ops);
1459}
1460
1461static void vc4_crtc_dev_remove(struct platform_device *pdev)
1462{
1463 component_del(&pdev->dev, &vc4_crtc_ops);
1464}
1465
1466struct platform_driver vc4_crtc_driver = {
1467 .probe = vc4_crtc_dev_probe,
1468 .remove = vc4_crtc_dev_remove,
1469 .driver = {
1470 .name = "vc4_crtc",
1471 .of_match_table = vc4_crtc_dt_match,
1472 },
1473};
1/*
2 * Copyright (C) 2015 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/**
10 * DOC: VC4 CRTC module
11 *
12 * In VC4, the Pixel Valve is what most closely corresponds to the
13 * DRM's concept of a CRTC. The PV generates video timings from the
14 * encoder's clock plus its configuration. It pulls scaled pixels from
15 * the HVS at that timing, and feeds it to the encoder.
16 *
17 * However, the DRM CRTC also collects the configuration of all the
18 * DRM planes attached to it. As a result, the CRTC is also
19 * responsible for writing the display list for the HVS channel that
20 * the CRTC will use.
21 *
22 * The 2835 has 3 different pixel valves. pv0 in the audio power
23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the
24 * image domain can feed either HDMI or the SDTV controller. The
25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26 * SDTV, etc.) according to which output type is chosen in the mux.
27 *
28 * For power management, the pixel valve's registers are all clocked
29 * by the AXI clock, while the timings and FIFOs make use of the
30 * output-specific clock. Since the encoders also directly consume
31 * the CPRMAN clocks, and know what timings they need, they are the
32 * ones that set the clock.
33 */
34
35#include <drm/drm_atomic.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_crtc_helper.h>
38#include <linux/clk.h>
39#include <drm/drm_fb_cma_helper.h>
40#include <linux/component.h>
41#include <linux/of_device.h>
42#include "vc4_drv.h"
43#include "vc4_regs.h"
44
45struct vc4_crtc {
46 struct drm_crtc base;
47 const struct vc4_crtc_data *data;
48 void __iomem *regs;
49
50 /* Timestamp at start of vblank irq - unaffected by lock delays. */
51 ktime_t t_vblank;
52
53 /* Which HVS channel we're using for our CRTC. */
54 int channel;
55
56 u8 lut_r[256];
57 u8 lut_g[256];
58 u8 lut_b[256];
59 /* Size in pixels of the COB memory allocated to this CRTC. */
60 u32 cob_size;
61
62 struct drm_pending_vblank_event *event;
63};
64
65struct vc4_crtc_state {
66 struct drm_crtc_state base;
67 /* Dlist area for this CRTC configuration. */
68 struct drm_mm_node mm;
69};
70
71static inline struct vc4_crtc *
72to_vc4_crtc(struct drm_crtc *crtc)
73{
74 return (struct vc4_crtc *)crtc;
75}
76
77static inline struct vc4_crtc_state *
78to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
79{
80 return (struct vc4_crtc_state *)crtc_state;
81}
82
83struct vc4_crtc_data {
84 /* Which channel of the HVS this pixelvalve sources from. */
85 int hvs_channel;
86
87 enum vc4_encoder_type encoder_types[4];
88};
89
90#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
92
93#define CRTC_REG(reg) { reg, #reg }
94static const struct {
95 u32 reg;
96 const char *name;
97} crtc_regs[] = {
98 CRTC_REG(PV_CONTROL),
99 CRTC_REG(PV_V_CONTROL),
100 CRTC_REG(PV_VSYNCD_EVEN),
101 CRTC_REG(PV_HORZA),
102 CRTC_REG(PV_HORZB),
103 CRTC_REG(PV_VERTA),
104 CRTC_REG(PV_VERTB),
105 CRTC_REG(PV_VERTA_EVEN),
106 CRTC_REG(PV_VERTB_EVEN),
107 CRTC_REG(PV_INTEN),
108 CRTC_REG(PV_INTSTAT),
109 CRTC_REG(PV_STAT),
110 CRTC_REG(PV_HACT_ACT),
111};
112
113static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
114{
115 int i;
116
117 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
118 DRM_INFO("0x%04x (%s): 0x%08x\n",
119 crtc_regs[i].reg, crtc_regs[i].name,
120 CRTC_READ(crtc_regs[i].reg));
121 }
122}
123
124#ifdef CONFIG_DEBUG_FS
125int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
126{
127 struct drm_info_node *node = (struct drm_info_node *)m->private;
128 struct drm_device *dev = node->minor->dev;
129 int crtc_index = (uintptr_t)node->info_ent->data;
130 struct drm_crtc *crtc;
131 struct vc4_crtc *vc4_crtc;
132 int i;
133
134 i = 0;
135 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
136 if (i == crtc_index)
137 break;
138 i++;
139 }
140 if (!crtc)
141 return 0;
142 vc4_crtc = to_vc4_crtc(crtc);
143
144 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
145 seq_printf(m, "%s (0x%04x): 0x%08x\n",
146 crtc_regs[i].name, crtc_regs[i].reg,
147 CRTC_READ(crtc_regs[i].reg));
148 }
149
150 return 0;
151}
152#endif
153
154bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
155 bool in_vblank_irq, int *vpos, int *hpos,
156 ktime_t *stime, ktime_t *etime,
157 const struct drm_display_mode *mode)
158{
159 struct vc4_dev *vc4 = to_vc4_dev(dev);
160 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
161 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
162 u32 val;
163 int fifo_lines;
164 int vblank_lines;
165 bool ret = false;
166
167 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
168
169 /* Get optional system timestamp before query. */
170 if (stime)
171 *stime = ktime_get();
172
173 /*
174 * Read vertical scanline which is currently composed for our
175 * pixelvalve by the HVS, and also the scaler status.
176 */
177 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
178
179 /* Get optional system timestamp after query. */
180 if (etime)
181 *etime = ktime_get();
182
183 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
184
185 /* Vertical position of hvs composed scanline. */
186 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
187 *hpos = 0;
188
189 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
190 *vpos /= 2;
191
192 /* Use hpos to correct for field offset in interlaced mode. */
193 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
194 *hpos += mode->crtc_htotal / 2;
195 }
196
197 /* This is the offset we need for translating hvs -> pv scanout pos. */
198 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
199
200 if (fifo_lines > 0)
201 ret = true;
202
203 /* HVS more than fifo_lines into frame for compositing? */
204 if (*vpos > fifo_lines) {
205 /*
206 * We are in active scanout and can get some meaningful results
207 * from HVS. The actual PV scanout can not trail behind more
208 * than fifo_lines as that is the fifo's capacity. Assume that
209 * in active scanout the HVS and PV work in lockstep wrt. HVS
210 * refilling the fifo and PV consuming from the fifo, ie.
211 * whenever the PV consumes and frees up a scanline in the
212 * fifo, the HVS will immediately refill it, therefore
213 * incrementing vpos. Therefore we choose HVS read position -
214 * fifo size in scanlines as a estimate of the real scanout
215 * position of the PV.
216 */
217 *vpos -= fifo_lines + 1;
218
219 return ret;
220 }
221
222 /*
223 * Less: This happens when we are in vblank and the HVS, after getting
224 * the VSTART restart signal from the PV, just started refilling its
225 * fifo with new lines from the top-most lines of the new framebuffers.
226 * The PV does not scan out in vblank, so does not remove lines from
227 * the fifo, so the fifo will be full quickly and the HVS has to pause.
228 * We can't get meaningful readings wrt. scanline position of the PV
229 * and need to make things up in a approximative but consistent way.
230 */
231 vblank_lines = mode->vtotal - mode->vdisplay;
232
233 if (in_vblank_irq) {
234 /*
235 * Assume the irq handler got called close to first
236 * line of vblank, so PV has about a full vblank
237 * scanlines to go, and as a base timestamp use the
238 * one taken at entry into vblank irq handler, so it
239 * is not affected by random delays due to lock
240 * contention on event_lock or vblank_time lock in
241 * the core.
242 */
243 *vpos = -vblank_lines;
244
245 if (stime)
246 *stime = vc4_crtc->t_vblank;
247 if (etime)
248 *etime = vc4_crtc->t_vblank;
249
250 /*
251 * If the HVS fifo is not yet full then we know for certain
252 * we are at the very beginning of vblank, as the hvs just
253 * started refilling, and the stime and etime timestamps
254 * truly correspond to start of vblank.
255 *
256 * Unfortunately there's no way to report this to upper levels
257 * and make it more useful.
258 */
259 } else {
260 /*
261 * No clue where we are inside vblank. Return a vpos of zero,
262 * which will cause calling code to just return the etime
263 * timestamp uncorrected. At least this is no worse than the
264 * standard fallback.
265 */
266 *vpos = 0;
267 }
268
269 return ret;
270}
271
272static void vc4_crtc_destroy(struct drm_crtc *crtc)
273{
274 drm_crtc_cleanup(crtc);
275}
276
277static void
278vc4_crtc_lut_load(struct drm_crtc *crtc)
279{
280 struct drm_device *dev = crtc->dev;
281 struct vc4_dev *vc4 = to_vc4_dev(dev);
282 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
283 u32 i;
284
285 /* The LUT memory is laid out with each HVS channel in order,
286 * each of which takes 256 writes for R, 256 for G, then 256
287 * for B.
288 */
289 HVS_WRITE(SCALER_GAMADDR,
290 SCALER_GAMADDR_AUTOINC |
291 (vc4_crtc->channel * 3 * crtc->gamma_size));
292
293 for (i = 0; i < crtc->gamma_size; i++)
294 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
295 for (i = 0; i < crtc->gamma_size; i++)
296 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
297 for (i = 0; i < crtc->gamma_size; i++)
298 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
299}
300
301static int
302vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
303 uint32_t size,
304 struct drm_modeset_acquire_ctx *ctx)
305{
306 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
307 u32 i;
308
309 for (i = 0; i < size; i++) {
310 vc4_crtc->lut_r[i] = r[i] >> 8;
311 vc4_crtc->lut_g[i] = g[i] >> 8;
312 vc4_crtc->lut_b[i] = b[i] >> 8;
313 }
314
315 vc4_crtc_lut_load(crtc);
316
317 return 0;
318}
319
320static u32 vc4_get_fifo_full_level(u32 format)
321{
322 static const u32 fifo_len_bytes = 64;
323 static const u32 hvs_latency_pix = 6;
324
325 switch (format) {
326 case PV_CONTROL_FORMAT_DSIV_16:
327 case PV_CONTROL_FORMAT_DSIC_16:
328 return fifo_len_bytes - 2 * hvs_latency_pix;
329 case PV_CONTROL_FORMAT_DSIV_18:
330 return fifo_len_bytes - 14;
331 case PV_CONTROL_FORMAT_24:
332 case PV_CONTROL_FORMAT_DSIV_24:
333 default:
334 return fifo_len_bytes - 3 * hvs_latency_pix;
335 }
336}
337
338/*
339 * Returns the encoder attached to the CRTC.
340 *
341 * VC4 can only scan out to one encoder at a time, while the DRM core
342 * allows drivers to push pixels to more than one encoder from the
343 * same CRTC.
344 */
345static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
346{
347 struct drm_connector *connector;
348 struct drm_connector_list_iter conn_iter;
349
350 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
351 drm_for_each_connector_iter(connector, &conn_iter) {
352 if (connector->state->crtc == crtc) {
353 drm_connector_list_iter_end(&conn_iter);
354 return connector->encoder;
355 }
356 }
357 drm_connector_list_iter_end(&conn_iter);
358
359 return NULL;
360}
361
362static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
363{
364 struct drm_device *dev = crtc->dev;
365 struct vc4_dev *vc4 = to_vc4_dev(dev);
366 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
367 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
368 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
369 struct drm_crtc_state *state = crtc->state;
370 struct drm_display_mode *mode = &state->adjusted_mode;
371 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
372 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
373 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
374 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
375 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
376 bool debug_dump_regs = false;
377
378 if (debug_dump_regs) {
379 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
380 vc4_crtc_dump_regs(vc4_crtc);
381 }
382
383 /* Reset the PV fifo. */
384 CRTC_WRITE(PV_CONTROL, 0);
385 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
386 CRTC_WRITE(PV_CONTROL, 0);
387
388 CRTC_WRITE(PV_HORZA,
389 VC4_SET_FIELD((mode->htotal -
390 mode->hsync_end) * pixel_rep,
391 PV_HORZA_HBP) |
392 VC4_SET_FIELD((mode->hsync_end -
393 mode->hsync_start) * pixel_rep,
394 PV_HORZA_HSYNC));
395 CRTC_WRITE(PV_HORZB,
396 VC4_SET_FIELD((mode->hsync_start -
397 mode->hdisplay) * pixel_rep,
398 PV_HORZB_HFP) |
399 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
400
401 CRTC_WRITE(PV_VERTA,
402 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
403 PV_VERTA_VBP) |
404 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
405 PV_VERTA_VSYNC));
406 CRTC_WRITE(PV_VERTB,
407 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
408 PV_VERTB_VFP) |
409 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
410
411 if (interlace) {
412 CRTC_WRITE(PV_VERTA_EVEN,
413 VC4_SET_FIELD(mode->crtc_vtotal -
414 mode->crtc_vsync_end - 1,
415 PV_VERTA_VBP) |
416 VC4_SET_FIELD(mode->crtc_vsync_end -
417 mode->crtc_vsync_start,
418 PV_VERTA_VSYNC));
419 CRTC_WRITE(PV_VERTB_EVEN,
420 VC4_SET_FIELD(mode->crtc_vsync_start -
421 mode->crtc_vdisplay,
422 PV_VERTB_VFP) |
423 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
424
425 /* We set up first field even mode for HDMI. VEC's
426 * NTSC mode would want first field odd instead, once
427 * we support it (to do so, set ODD_FIRST and put the
428 * delay in VSYNCD_EVEN instead).
429 */
430 CRTC_WRITE(PV_V_CONTROL,
431 PV_VCONTROL_CONTINUOUS |
432 (is_dsi ? PV_VCONTROL_DSI : 0) |
433 PV_VCONTROL_INTERLACE |
434 VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
435 PV_VCONTROL_ODD_DELAY));
436 CRTC_WRITE(PV_VSYNCD_EVEN, 0);
437 } else {
438 CRTC_WRITE(PV_V_CONTROL,
439 PV_VCONTROL_CONTINUOUS |
440 (is_dsi ? PV_VCONTROL_DSI : 0));
441 }
442
443 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
444
445 CRTC_WRITE(PV_CONTROL,
446 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
447 VC4_SET_FIELD(vc4_get_fifo_full_level(format),
448 PV_CONTROL_FIFO_LEVEL) |
449 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
450 PV_CONTROL_CLR_AT_START |
451 PV_CONTROL_TRIGGER_UNDERFLOW |
452 PV_CONTROL_WAIT_HSTART |
453 VC4_SET_FIELD(vc4_encoder->clock_select,
454 PV_CONTROL_CLK_SELECT) |
455 PV_CONTROL_FIFO_CLR |
456 PV_CONTROL_EN);
457
458 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
459 SCALER_DISPBKGND_AUTOHS |
460 SCALER_DISPBKGND_GAMMA |
461 (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
462
463 /* Reload the LUT, since the SRAMs would have been disabled if
464 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
465 */
466 vc4_crtc_lut_load(crtc);
467
468 if (debug_dump_regs) {
469 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
470 vc4_crtc_dump_regs(vc4_crtc);
471 }
472}
473
474static void require_hvs_enabled(struct drm_device *dev)
475{
476 struct vc4_dev *vc4 = to_vc4_dev(dev);
477
478 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
479 SCALER_DISPCTRL_ENABLE);
480}
481
482static void vc4_crtc_atomic_disable(struct drm_crtc *crtc,
483 struct drm_crtc_state *old_state)
484{
485 struct drm_device *dev = crtc->dev;
486 struct vc4_dev *vc4 = to_vc4_dev(dev);
487 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
488 u32 chan = vc4_crtc->channel;
489 int ret;
490 require_hvs_enabled(dev);
491
492 /* Disable vblank irq handling before crtc is disabled. */
493 drm_crtc_vblank_off(crtc);
494
495 CRTC_WRITE(PV_V_CONTROL,
496 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
497 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
498 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
499
500 if (HVS_READ(SCALER_DISPCTRLX(chan)) &
501 SCALER_DISPCTRLX_ENABLE) {
502 HVS_WRITE(SCALER_DISPCTRLX(chan),
503 SCALER_DISPCTRLX_RESET);
504
505 /* While the docs say that reset is self-clearing, it
506 * seems it doesn't actually.
507 */
508 HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
509 }
510
511 /* Once we leave, the scaler should be disabled and its fifo empty. */
512
513 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
514
515 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
516 SCALER_DISPSTATX_MODE) !=
517 SCALER_DISPSTATX_MODE_DISABLED);
518
519 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
520 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
521 SCALER_DISPSTATX_EMPTY);
522
523 /*
524 * Make sure we issue a vblank event after disabling the CRTC if
525 * someone was waiting it.
526 */
527 if (crtc->state->event) {
528 unsigned long flags;
529
530 spin_lock_irqsave(&dev->event_lock, flags);
531 drm_crtc_send_vblank_event(crtc, crtc->state->event);
532 crtc->state->event = NULL;
533 spin_unlock_irqrestore(&dev->event_lock, flags);
534 }
535}
536
537static void vc4_crtc_update_dlist(struct drm_crtc *crtc)
538{
539 struct drm_device *dev = crtc->dev;
540 struct vc4_dev *vc4 = to_vc4_dev(dev);
541 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
542 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
543
544 if (crtc->state->event) {
545 unsigned long flags;
546
547 crtc->state->event->pipe = drm_crtc_index(crtc);
548
549 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
550
551 spin_lock_irqsave(&dev->event_lock, flags);
552 vc4_crtc->event = crtc->state->event;
553 crtc->state->event = NULL;
554
555 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
556 vc4_state->mm.start);
557
558 spin_unlock_irqrestore(&dev->event_lock, flags);
559 } else {
560 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
561 vc4_state->mm.start);
562 }
563}
564
565static void vc4_crtc_atomic_enable(struct drm_crtc *crtc,
566 struct drm_crtc_state *old_state)
567{
568 struct drm_device *dev = crtc->dev;
569 struct vc4_dev *vc4 = to_vc4_dev(dev);
570 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
571 struct drm_crtc_state *state = crtc->state;
572 struct drm_display_mode *mode = &state->adjusted_mode;
573
574 require_hvs_enabled(dev);
575
576 /* Enable vblank irq handling before crtc is started otherwise
577 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist().
578 */
579 drm_crtc_vblank_on(crtc);
580 vc4_crtc_update_dlist(crtc);
581
582 /* Turn on the scaler, which will wait for vstart to start
583 * compositing.
584 */
585 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
586 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
587 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
588 SCALER_DISPCTRLX_ENABLE);
589
590 /* Turn on the pixel valve, which will emit the vstart signal. */
591 CRTC_WRITE(PV_V_CONTROL,
592 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
593}
594
595static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc,
596 const struct drm_display_mode *mode)
597{
598 /* Do not allow doublescan modes from user space */
599 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
600 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
601 crtc->base.id);
602 return MODE_NO_DBLESCAN;
603 }
604
605 return MODE_OK;
606}
607
608static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
609 struct drm_crtc_state *state)
610{
611 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
612 struct drm_device *dev = crtc->dev;
613 struct vc4_dev *vc4 = to_vc4_dev(dev);
614 struct drm_plane *plane;
615 unsigned long flags;
616 const struct drm_plane_state *plane_state;
617 u32 dlist_count = 0;
618 int ret;
619
620 /* The pixelvalve can only feed one encoder (and encoders are
621 * 1:1 with connectors.)
622 */
623 if (hweight32(state->connector_mask) > 1)
624 return -EINVAL;
625
626 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
627 dlist_count += vc4_plane_dlist_size(plane_state);
628
629 dlist_count++; /* Account for SCALER_CTL0_END. */
630
631 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
632 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
633 dlist_count);
634 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
635 if (ret)
636 return ret;
637
638 return 0;
639}
640
641static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
642 struct drm_crtc_state *old_state)
643{
644 struct drm_device *dev = crtc->dev;
645 struct vc4_dev *vc4 = to_vc4_dev(dev);
646 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
647 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
648 struct drm_plane *plane;
649 struct vc4_plane_state *vc4_plane_state;
650 bool debug_dump_regs = false;
651 bool enable_bg_fill = false;
652 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
653 u32 __iomem *dlist_next = dlist_start;
654
655 if (debug_dump_regs) {
656 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
657 vc4_hvs_dump_state(dev);
658 }
659
660 /* Copy all the active planes' dlist contents to the hardware dlist. */
661 drm_atomic_crtc_for_each_plane(plane, crtc) {
662 /* Is this the first active plane? */
663 if (dlist_next == dlist_start) {
664 /* We need to enable background fill when a plane
665 * could be alpha blending from the background, i.e.
666 * where no other plane is underneath. It suffices to
667 * consider the first active plane here since we set
668 * needs_bg_fill such that either the first plane
669 * already needs it or all planes on top blend from
670 * the first or a lower plane.
671 */
672 vc4_plane_state = to_vc4_plane_state(plane->state);
673 enable_bg_fill = vc4_plane_state->needs_bg_fill;
674 }
675
676 dlist_next += vc4_plane_write_dlist(plane, dlist_next);
677 }
678
679 writel(SCALER_CTL0_END, dlist_next);
680 dlist_next++;
681
682 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
683
684 if (enable_bg_fill)
685 /* This sets a black background color fill, as is the case
686 * with other DRM drivers.
687 */
688 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
689 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
690 SCALER_DISPBKGND_FILL);
691
692 /* Only update DISPLIST if the CRTC was already running and is not
693 * being disabled.
694 * vc4_crtc_enable() takes care of updating the dlist just after
695 * re-enabling VBLANK interrupts and before enabling the engine.
696 * If the CRTC is being disabled, there's no point in updating this
697 * information.
698 */
699 if (crtc->state->active && old_state->active)
700 vc4_crtc_update_dlist(crtc);
701
702 if (debug_dump_regs) {
703 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
704 vc4_hvs_dump_state(dev);
705 }
706}
707
708static int vc4_enable_vblank(struct drm_crtc *crtc)
709{
710 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
711
712 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
713
714 return 0;
715}
716
717static void vc4_disable_vblank(struct drm_crtc *crtc)
718{
719 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
720
721 CRTC_WRITE(PV_INTEN, 0);
722}
723
724static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
725{
726 struct drm_crtc *crtc = &vc4_crtc->base;
727 struct drm_device *dev = crtc->dev;
728 struct vc4_dev *vc4 = to_vc4_dev(dev);
729 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
730 u32 chan = vc4_crtc->channel;
731 unsigned long flags;
732
733 spin_lock_irqsave(&dev->event_lock, flags);
734 if (vc4_crtc->event &&
735 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
736 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
737 vc4_crtc->event = NULL;
738 drm_crtc_vblank_put(crtc);
739 }
740 spin_unlock_irqrestore(&dev->event_lock, flags);
741}
742
743static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
744{
745 struct vc4_crtc *vc4_crtc = data;
746 u32 stat = CRTC_READ(PV_INTSTAT);
747 irqreturn_t ret = IRQ_NONE;
748
749 if (stat & PV_INT_VFP_START) {
750 vc4_crtc->t_vblank = ktime_get();
751 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
752 drm_crtc_handle_vblank(&vc4_crtc->base);
753 vc4_crtc_handle_page_flip(vc4_crtc);
754 ret = IRQ_HANDLED;
755 }
756
757 return ret;
758}
759
760struct vc4_async_flip_state {
761 struct drm_crtc *crtc;
762 struct drm_framebuffer *fb;
763 struct drm_framebuffer *old_fb;
764 struct drm_pending_vblank_event *event;
765
766 struct vc4_seqno_cb cb;
767};
768
769/* Called when the V3D execution for the BO being flipped to is done, so that
770 * we can actually update the plane's address to point to it.
771 */
772static void
773vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
774{
775 struct vc4_async_flip_state *flip_state =
776 container_of(cb, struct vc4_async_flip_state, cb);
777 struct drm_crtc *crtc = flip_state->crtc;
778 struct drm_device *dev = crtc->dev;
779 struct vc4_dev *vc4 = to_vc4_dev(dev);
780 struct drm_plane *plane = crtc->primary;
781
782 vc4_plane_async_set_fb(plane, flip_state->fb);
783 if (flip_state->event) {
784 unsigned long flags;
785
786 spin_lock_irqsave(&dev->event_lock, flags);
787 drm_crtc_send_vblank_event(crtc, flip_state->event);
788 spin_unlock_irqrestore(&dev->event_lock, flags);
789 }
790
791 drm_crtc_vblank_put(crtc);
792 drm_framebuffer_put(flip_state->fb);
793
794 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced
795 * when the planes are updated through the async update path.
796 * FIXME: we should move to generic async-page-flip when it's
797 * available, so that we can get rid of this hand-made cleanup_fb()
798 * logic.
799 */
800 if (flip_state->old_fb) {
801 struct drm_gem_cma_object *cma_bo;
802 struct vc4_bo *bo;
803
804 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0);
805 bo = to_vc4_bo(&cma_bo->base);
806 vc4_bo_dec_usecnt(bo);
807 drm_framebuffer_put(flip_state->old_fb);
808 }
809
810 kfree(flip_state);
811
812 up(&vc4->async_modeset);
813}
814
815/* Implements async (non-vblank-synced) page flips.
816 *
817 * The page flip ioctl needs to return immediately, so we grab the
818 * modeset semaphore on the pipe, and queue the address update for
819 * when V3D is done with the BO being flipped to.
820 */
821static int vc4_async_page_flip(struct drm_crtc *crtc,
822 struct drm_framebuffer *fb,
823 struct drm_pending_vblank_event *event,
824 uint32_t flags)
825{
826 struct drm_device *dev = crtc->dev;
827 struct vc4_dev *vc4 = to_vc4_dev(dev);
828 struct drm_plane *plane = crtc->primary;
829 int ret = 0;
830 struct vc4_async_flip_state *flip_state;
831 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
832 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
833
834 /* Increment the BO usecnt here, so that we never end up with an
835 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the
836 * plane is later updated through the non-async path.
837 * FIXME: we should move to generic async-page-flip when it's
838 * available, so that we can get rid of this hand-made prepare_fb()
839 * logic.
840 */
841 ret = vc4_bo_inc_usecnt(bo);
842 if (ret)
843 return ret;
844
845 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
846 if (!flip_state) {
847 vc4_bo_dec_usecnt(bo);
848 return -ENOMEM;
849 }
850
851 drm_framebuffer_get(fb);
852 flip_state->fb = fb;
853 flip_state->crtc = crtc;
854 flip_state->event = event;
855
856 /* Make sure all other async modesetes have landed. */
857 ret = down_interruptible(&vc4->async_modeset);
858 if (ret) {
859 drm_framebuffer_put(fb);
860 vc4_bo_dec_usecnt(bo);
861 kfree(flip_state);
862 return ret;
863 }
864
865 /* Save the current FB before it's replaced by the new one in
866 * drm_atomic_set_fb_for_plane(). We'll need the old FB in
867 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep
868 * it consistent.
869 * FIXME: we should move to generic async-page-flip when it's
870 * available, so that we can get rid of this hand-made cleanup_fb()
871 * logic.
872 */
873 flip_state->old_fb = plane->state->fb;
874 if (flip_state->old_fb)
875 drm_framebuffer_get(flip_state->old_fb);
876
877 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
878
879 /* Immediately update the plane's legacy fb pointer, so that later
880 * modeset prep sees the state that will be present when the semaphore
881 * is released.
882 */
883 drm_atomic_set_fb_for_plane(plane->state, fb);
884 plane->fb = fb;
885
886 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
887 vc4_async_page_flip_complete);
888
889 /* Driver takes ownership of state on successful async commit. */
890 return 0;
891}
892
893static int vc4_page_flip(struct drm_crtc *crtc,
894 struct drm_framebuffer *fb,
895 struct drm_pending_vblank_event *event,
896 uint32_t flags,
897 struct drm_modeset_acquire_ctx *ctx)
898{
899 if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
900 return vc4_async_page_flip(crtc, fb, event, flags);
901 else
902 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
903}
904
905static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
906{
907 struct vc4_crtc_state *vc4_state;
908
909 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
910 if (!vc4_state)
911 return NULL;
912
913 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
914 return &vc4_state->base;
915}
916
917static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
918 struct drm_crtc_state *state)
919{
920 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
921 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
922
923 if (vc4_state->mm.allocated) {
924 unsigned long flags;
925
926 spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
927 drm_mm_remove_node(&vc4_state->mm);
928 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
929
930 }
931
932 drm_atomic_helper_crtc_destroy_state(crtc, state);
933}
934
935static void
936vc4_crtc_reset(struct drm_crtc *crtc)
937{
938 if (crtc->state)
939 __drm_atomic_helper_crtc_destroy_state(crtc->state);
940
941 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
942 if (crtc->state)
943 crtc->state->crtc = crtc;
944}
945
946static const struct drm_crtc_funcs vc4_crtc_funcs = {
947 .set_config = drm_atomic_helper_set_config,
948 .destroy = vc4_crtc_destroy,
949 .page_flip = vc4_page_flip,
950 .set_property = NULL,
951 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */
952 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */
953 .reset = vc4_crtc_reset,
954 .atomic_duplicate_state = vc4_crtc_duplicate_state,
955 .atomic_destroy_state = vc4_crtc_destroy_state,
956 .gamma_set = vc4_crtc_gamma_set,
957 .enable_vblank = vc4_enable_vblank,
958 .disable_vblank = vc4_disable_vblank,
959};
960
961static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
962 .mode_set_nofb = vc4_crtc_mode_set_nofb,
963 .mode_valid = vc4_crtc_mode_valid,
964 .atomic_check = vc4_crtc_atomic_check,
965 .atomic_flush = vc4_crtc_atomic_flush,
966 .atomic_enable = vc4_crtc_atomic_enable,
967 .atomic_disable = vc4_crtc_atomic_disable,
968};
969
970static const struct vc4_crtc_data pv0_data = {
971 .hvs_channel = 0,
972 .encoder_types = {
973 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
974 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
975 },
976};
977
978static const struct vc4_crtc_data pv1_data = {
979 .hvs_channel = 2,
980 .encoder_types = {
981 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
982 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
983 },
984};
985
986static const struct vc4_crtc_data pv2_data = {
987 .hvs_channel = 1,
988 .encoder_types = {
989 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
990 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
991 },
992};
993
994static const struct of_device_id vc4_crtc_dt_match[] = {
995 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
996 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
997 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
998 {}
999};
1000
1001static void vc4_set_crtc_possible_masks(struct drm_device *drm,
1002 struct drm_crtc *crtc)
1003{
1004 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
1005 const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
1006 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
1007 struct drm_encoder *encoder;
1008
1009 drm_for_each_encoder(encoder, drm) {
1010 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
1011 int i;
1012
1013 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
1014 if (vc4_encoder->type == encoder_types[i]) {
1015 vc4_encoder->clock_select = i;
1016 encoder->possible_crtcs |= drm_crtc_mask(crtc);
1017 break;
1018 }
1019 }
1020 }
1021}
1022
1023static void
1024vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
1025{
1026 struct drm_device *drm = vc4_crtc->base.dev;
1027 struct vc4_dev *vc4 = to_vc4_dev(drm);
1028 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
1029 /* Top/base are supposed to be 4-pixel aligned, but the
1030 * Raspberry Pi firmware fills the low bits (which are
1031 * presumably ignored).
1032 */
1033 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
1034 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
1035
1036 vc4_crtc->cob_size = top - base + 4;
1037}
1038
1039static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
1040{
1041 struct platform_device *pdev = to_platform_device(dev);
1042 struct drm_device *drm = dev_get_drvdata(master);
1043 struct vc4_crtc *vc4_crtc;
1044 struct drm_crtc *crtc;
1045 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
1046 const struct of_device_id *match;
1047 int ret, i;
1048
1049 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
1050 if (!vc4_crtc)
1051 return -ENOMEM;
1052 crtc = &vc4_crtc->base;
1053
1054 match = of_match_device(vc4_crtc_dt_match, dev);
1055 if (!match)
1056 return -ENODEV;
1057 vc4_crtc->data = match->data;
1058
1059 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
1060 if (IS_ERR(vc4_crtc->regs))
1061 return PTR_ERR(vc4_crtc->regs);
1062
1063 /* For now, we create just the primary and the legacy cursor
1064 * planes. We should be able to stack more planes on easily,
1065 * but to do that we would need to compute the bandwidth
1066 * requirement of the plane configuration, and reject ones
1067 * that will take too much.
1068 */
1069 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
1070 if (IS_ERR(primary_plane)) {
1071 dev_err(dev, "failed to construct primary plane\n");
1072 ret = PTR_ERR(primary_plane);
1073 goto err;
1074 }
1075
1076 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
1077 &vc4_crtc_funcs, NULL);
1078 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
1079 primary_plane->crtc = crtc;
1080 vc4_crtc->channel = vc4_crtc->data->hvs_channel;
1081 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
1082
1083 /* Set up some arbitrary number of planes. We're not limited
1084 * by a set number of physical registers, just the space in
1085 * the HVS (16k) and how small an plane can be (28 bytes).
1086 * However, each plane we set up takes up some memory, and
1087 * increases the cost of looping over planes, which atomic
1088 * modesetting does quite a bit. As a result, we pick a
1089 * modest number of planes to expose, that should hopefully
1090 * still cover any sane usecase.
1091 */
1092 for (i = 0; i < 8; i++) {
1093 struct drm_plane *plane =
1094 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
1095
1096 if (IS_ERR(plane))
1097 continue;
1098
1099 plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1100 }
1101
1102 /* Set up the legacy cursor after overlay initialization,
1103 * since we overlay planes on the CRTC in the order they were
1104 * initialized.
1105 */
1106 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1107 if (!IS_ERR(cursor_plane)) {
1108 cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1109 cursor_plane->crtc = crtc;
1110 crtc->cursor = cursor_plane;
1111 }
1112
1113 vc4_crtc_get_cob_allocation(vc4_crtc);
1114
1115 CRTC_WRITE(PV_INTEN, 0);
1116 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1117 ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1118 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1119 if (ret)
1120 goto err_destroy_planes;
1121
1122 vc4_set_crtc_possible_masks(drm, crtc);
1123
1124 for (i = 0; i < crtc->gamma_size; i++) {
1125 vc4_crtc->lut_r[i] = i;
1126 vc4_crtc->lut_g[i] = i;
1127 vc4_crtc->lut_b[i] = i;
1128 }
1129
1130 platform_set_drvdata(pdev, vc4_crtc);
1131
1132 return 0;
1133
1134err_destroy_planes:
1135 list_for_each_entry_safe(destroy_plane, temp,
1136 &drm->mode_config.plane_list, head) {
1137 if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1138 destroy_plane->funcs->destroy(destroy_plane);
1139 }
1140err:
1141 return ret;
1142}
1143
1144static void vc4_crtc_unbind(struct device *dev, struct device *master,
1145 void *data)
1146{
1147 struct platform_device *pdev = to_platform_device(dev);
1148 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1149
1150 vc4_crtc_destroy(&vc4_crtc->base);
1151
1152 CRTC_WRITE(PV_INTEN, 0);
1153
1154 platform_set_drvdata(pdev, NULL);
1155}
1156
1157static const struct component_ops vc4_crtc_ops = {
1158 .bind = vc4_crtc_bind,
1159 .unbind = vc4_crtc_unbind,
1160};
1161
1162static int vc4_crtc_dev_probe(struct platform_device *pdev)
1163{
1164 return component_add(&pdev->dev, &vc4_crtc_ops);
1165}
1166
1167static int vc4_crtc_dev_remove(struct platform_device *pdev)
1168{
1169 component_del(&pdev->dev, &vc4_crtc_ops);
1170 return 0;
1171}
1172
1173struct platform_driver vc4_crtc_driver = {
1174 .probe = vc4_crtc_dev_probe,
1175 .remove = vc4_crtc_dev_remove,
1176 .driver = {
1177 .name = "vc4_crtc",
1178 .of_match_table = vc4_crtc_dt_match,
1179 },
1180};