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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2019 Intel Corporation.
4 */
5
6#include "i915_drv.h"
7#include "i915_utils.h"
8#include "intel_pch.h"
9
10/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
11static enum intel_pch
12intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
13{
14 switch (id) {
15 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
16 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n");
17 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5);
18 return PCH_IBX;
19 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
20 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n");
21 drm_WARN_ON(&dev_priv->drm,
22 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
23 return PCH_CPT;
24 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
25 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n");
26 drm_WARN_ON(&dev_priv->drm,
27 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
28 /* PPT is CPT compatible */
29 return PCH_CPT;
30 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
31 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n");
32 drm_WARN_ON(&dev_priv->drm,
33 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
34 drm_WARN_ON(&dev_priv->drm,
35 IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv));
36 return PCH_LPT;
37 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
38 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n");
39 drm_WARN_ON(&dev_priv->drm,
40 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
41 drm_WARN_ON(&dev_priv->drm,
42 !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv));
43 return PCH_LPT;
44 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
45 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n");
46 drm_WARN_ON(&dev_priv->drm,
47 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
48 drm_WARN_ON(&dev_priv->drm,
49 IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv));
50 /* WPT is LPT compatible */
51 return PCH_LPT;
52 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
53 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n");
54 drm_WARN_ON(&dev_priv->drm,
55 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
56 drm_WARN_ON(&dev_priv->drm,
57 !IS_HASWELL_ULT(dev_priv) && !IS_BROADWELL_ULT(dev_priv));
58 /* WPT is LPT compatible */
59 return PCH_LPT;
60 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
61 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n");
62 drm_WARN_ON(&dev_priv->drm,
63 !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
64 return PCH_SPT;
65 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
66 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n");
67 drm_WARN_ON(&dev_priv->drm,
68 !IS_SKYLAKE(dev_priv) &&
69 !IS_KABYLAKE(dev_priv) &&
70 !IS_COFFEELAKE(dev_priv) &&
71 !IS_COMETLAKE(dev_priv));
72 return PCH_SPT;
73 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
74 drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n");
75 drm_WARN_ON(&dev_priv->drm,
76 !IS_SKYLAKE(dev_priv) &&
77 !IS_KABYLAKE(dev_priv) &&
78 !IS_COFFEELAKE(dev_priv) &&
79 !IS_COMETLAKE(dev_priv));
80 /* KBP is SPT compatible */
81 return PCH_SPT;
82 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
83 drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n");
84 drm_WARN_ON(&dev_priv->drm,
85 !IS_COFFEELAKE(dev_priv) &&
86 !IS_COMETLAKE(dev_priv));
87 return PCH_CNP;
88 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
89 drm_dbg_kms(&dev_priv->drm,
90 "Found Cannon Lake LP PCH (CNP-LP)\n");
91 drm_WARN_ON(&dev_priv->drm,
92 !IS_COFFEELAKE(dev_priv) &&
93 !IS_COMETLAKE(dev_priv));
94 return PCH_CNP;
95 case INTEL_PCH_CMP_DEVICE_ID_TYPE:
96 case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
97 drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n");
98 drm_WARN_ON(&dev_priv->drm,
99 !IS_COFFEELAKE(dev_priv) &&
100 !IS_COMETLAKE(dev_priv) &&
101 !IS_ROCKETLAKE(dev_priv));
102 /* CMP is CNP compatible */
103 return PCH_CNP;
104 case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
105 drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n");
106 drm_WARN_ON(&dev_priv->drm,
107 !IS_COFFEELAKE(dev_priv) &&
108 !IS_COMETLAKE(dev_priv));
109 /* CMP-V is based on KBP, which is SPT compatible */
110 return PCH_SPT;
111 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
112 case INTEL_PCH_ICP2_DEVICE_ID_TYPE:
113 drm_dbg_kms(&dev_priv->drm, "Found Ice Lake PCH\n");
114 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
115 return PCH_ICP;
116 case INTEL_PCH_MCC_DEVICE_ID_TYPE:
117 drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
118 drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) ||
119 IS_ELKHARTLAKE(dev_priv)));
120 /* MCC is TGP compatible */
121 return PCH_TGP;
122 case INTEL_PCH_TGP_DEVICE_ID_TYPE:
123 case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
124 drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
125 drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
126 !IS_ROCKETLAKE(dev_priv) &&
127 !IS_SKYLAKE(dev_priv) &&
128 !IS_KABYLAKE(dev_priv) &&
129 !IS_COFFEELAKE(dev_priv) &&
130 !IS_COMETLAKE(dev_priv));
131 return PCH_TGP;
132 case INTEL_PCH_JSP_DEVICE_ID_TYPE:
133 drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
134 drm_WARN_ON(&dev_priv->drm, !(IS_JASPERLAKE(dev_priv) ||
135 IS_ELKHARTLAKE(dev_priv)));
136 /* JSP is ICP compatible */
137 return PCH_ICP;
138 case INTEL_PCH_ADP_DEVICE_ID_TYPE:
139 case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
140 case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
141 case INTEL_PCH_ADP4_DEVICE_ID_TYPE:
142 drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
143 drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
144 !IS_ALDERLAKE_P(dev_priv));
145 return PCH_ADP;
146 default:
147 return PCH_NONE;
148 }
149}
150
151static bool intel_is_virt_pch(unsigned short id,
152 unsigned short svendor, unsigned short sdevice)
153{
154 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
155 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
156 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
157 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
158 sdevice == PCI_SUBDEVICE_ID_QEMU));
159}
160
161static void
162intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
163 unsigned short *pch_id, enum intel_pch *pch_type)
164{
165 unsigned short id = 0;
166
167 /*
168 * In a virtualized passthrough environment we can be in a
169 * setup where the ISA bridge is not able to be passed through.
170 * In this case, a south bridge can be emulated and we have to
171 * make an educated guess as to which PCH is really there.
172 */
173
174 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
175 id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
176 else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
177 id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
178 else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
179 id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
180 else if (IS_ICELAKE(dev_priv))
181 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
182 else if (IS_COFFEELAKE(dev_priv) ||
183 IS_COMETLAKE(dev_priv))
184 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
185 else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
186 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
187 else if (IS_HASWELL_ULT(dev_priv) || IS_BROADWELL_ULT(dev_priv))
188 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
189 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
190 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
191 else if (GRAPHICS_VER(dev_priv) == 6 || IS_IVYBRIDGE(dev_priv))
192 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
193 else if (GRAPHICS_VER(dev_priv) == 5)
194 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
195
196 if (id)
197 drm_dbg_kms(&dev_priv->drm, "Assuming PCH ID %04x\n", id);
198 else
199 drm_dbg_kms(&dev_priv->drm, "Assuming no PCH\n");
200
201 *pch_type = intel_pch_type(dev_priv, id);
202
203 /* Sanity check virtual PCH id */
204 if (drm_WARN_ON(&dev_priv->drm,
205 id && *pch_type == PCH_NONE))
206 id = 0;
207
208 *pch_id = id;
209}
210
211void intel_detect_pch(struct drm_i915_private *dev_priv)
212{
213 struct pci_dev *pch = NULL;
214 unsigned short id;
215 enum intel_pch pch_type;
216
217 /*
218 * South display engine on the same PCI device: just assign the fake
219 * PCH.
220 */
221 if (DISPLAY_VER(dev_priv) >= 20) {
222 dev_priv->pch_type = PCH_LNL;
223 return;
224 } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) {
225 /*
226 * Both north display and south display are on the SoC die.
227 * The real PCH (if it even exists) is uninvolved in display.
228 */
229 dev_priv->pch_type = PCH_MTL;
230 return;
231 } else if (IS_DG2(dev_priv)) {
232 dev_priv->pch_type = PCH_DG2;
233 return;
234 } else if (IS_DG1(dev_priv)) {
235 dev_priv->pch_type = PCH_DG1;
236 return;
237 }
238
239 /*
240 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
241 * make graphics device passthrough work easy for VMM, that only
242 * need to expose ISA bridge to let driver know the real hardware
243 * underneath. This is a requirement from virtualization team.
244 *
245 * In some virtualized environments (e.g. XEN), there is irrelevant
246 * ISA bridge in the system. To work reliably, we should scan trhough
247 * all the ISA bridge devices and check for the first match, instead
248 * of only checking the first one.
249 */
250 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
251 if (pch->vendor != PCI_VENDOR_ID_INTEL)
252 continue;
253
254 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
255
256 pch_type = intel_pch_type(dev_priv, id);
257 if (pch_type != PCH_NONE) {
258 dev_priv->pch_type = pch_type;
259 dev_priv->pch_id = id;
260 break;
261 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
262 pch->subsystem_device)) {
263 intel_virt_detect_pch(dev_priv, &id, &pch_type);
264 dev_priv->pch_type = pch_type;
265 dev_priv->pch_id = id;
266 break;
267 }
268 }
269
270 /*
271 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
272 * display.
273 */
274 if (pch && !HAS_DISPLAY(dev_priv)) {
275 drm_dbg_kms(&dev_priv->drm,
276 "Display disabled, reverting to NOP PCH\n");
277 dev_priv->pch_type = PCH_NOP;
278 dev_priv->pch_id = 0;
279 } else if (!pch) {
280 if (i915_run_as_guest() && HAS_DISPLAY(dev_priv)) {
281 intel_virt_detect_pch(dev_priv, &id, &pch_type);
282 dev_priv->pch_type = pch_type;
283 dev_priv->pch_id = id;
284 } else {
285 drm_dbg_kms(&dev_priv->drm, "No PCH found.\n");
286 }
287 }
288
289 pci_dev_put(pch);
290}