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1/*
2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27/*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30
31#include <linux/delay.h>
32#include <linux/export.h>
33#include <linux/pci.h>
34
35#include <drm/drm_atomic.h>
36#include <drm/drm_atomic_helper.h>
37#include <drm/drm_crtc.h>
38#include <drm/drm_damage_helper.h>
39#include <drm/drm_format_helper.h>
40#include <drm/drm_fourcc.h>
41#include <drm/drm_gem_atomic_helper.h>
42#include <drm/drm_gem_framebuffer_helper.h>
43#include <drm/drm_gem_shmem_helper.h>
44#include <drm/drm_managed.h>
45#include <drm/drm_panic.h>
46#include <drm/drm_probe_helper.h>
47
48#include "ast_drv.h"
49#include "ast_tables.h"
50
51#define AST_LUT_SIZE 256
52
53static inline void ast_load_palette_index(struct ast_device *ast,
54 u8 index, u8 red, u8 green,
55 u8 blue)
56{
57 ast_io_write8(ast, AST_IO_VGADWR, index);
58 ast_io_read8(ast, AST_IO_VGASRI);
59 ast_io_write8(ast, AST_IO_VGAPDR, red);
60 ast_io_read8(ast, AST_IO_VGASRI);
61 ast_io_write8(ast, AST_IO_VGAPDR, green);
62 ast_io_read8(ast, AST_IO_VGASRI);
63 ast_io_write8(ast, AST_IO_VGAPDR, blue);
64 ast_io_read8(ast, AST_IO_VGASRI);
65}
66
67static void ast_crtc_set_gamma_linear(struct ast_device *ast,
68 const struct drm_format_info *format)
69{
70 int i;
71
72 switch (format->format) {
73 case DRM_FORMAT_C8: /* In this case, gamma table is used as color palette */
74 case DRM_FORMAT_RGB565:
75 case DRM_FORMAT_XRGB8888:
76 for (i = 0; i < AST_LUT_SIZE; i++)
77 ast_load_palette_index(ast, i, i, i, i);
78 break;
79 default:
80 drm_warn_once(&ast->base, "Unsupported format %p4cc for gamma correction\n",
81 &format->format);
82 break;
83 }
84}
85
86static void ast_crtc_set_gamma(struct ast_device *ast,
87 const struct drm_format_info *format,
88 struct drm_color_lut *lut)
89{
90 int i;
91
92 switch (format->format) {
93 case DRM_FORMAT_C8: /* In this case, gamma table is used as color palette */
94 case DRM_FORMAT_RGB565:
95 case DRM_FORMAT_XRGB8888:
96 for (i = 0; i < AST_LUT_SIZE; i++)
97 ast_load_palette_index(ast, i,
98 lut[i].red >> 8,
99 lut[i].green >> 8,
100 lut[i].blue >> 8);
101 break;
102 default:
103 drm_warn_once(&ast->base, "Unsupported format %p4cc for gamma correction\n",
104 &format->format);
105 break;
106 }
107}
108
109static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
110 const struct drm_display_mode *mode,
111 struct drm_display_mode *adjusted_mode,
112 struct ast_vbios_mode_info *vbios_mode)
113{
114 u32 refresh_rate_index = 0, refresh_rate;
115 const struct ast_vbios_enhtable *best = NULL;
116 u32 hborder, vborder;
117 bool check_sync;
118
119 switch (format->cpp[0] * 8) {
120 case 8:
121 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
122 break;
123 case 16:
124 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
125 break;
126 case 24:
127 case 32:
128 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
129 break;
130 default:
131 return false;
132 }
133
134 switch (mode->crtc_hdisplay) {
135 case 640:
136 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
137 break;
138 case 800:
139 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
140 break;
141 case 1024:
142 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
143 break;
144 case 1152:
145 vbios_mode->enh_table = &res_1152x864[refresh_rate_index];
146 break;
147 case 1280:
148 if (mode->crtc_vdisplay == 800)
149 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
150 else
151 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
152 break;
153 case 1360:
154 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
155 break;
156 case 1440:
157 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
158 break;
159 case 1600:
160 if (mode->crtc_vdisplay == 900)
161 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
162 else
163 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
164 break;
165 case 1680:
166 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
167 break;
168 case 1920:
169 if (mode->crtc_vdisplay == 1080)
170 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
171 else
172 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
173 break;
174 default:
175 return false;
176 }
177
178 refresh_rate = drm_mode_vrefresh(mode);
179 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
180
181 while (1) {
182 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
183
184 while (loop->refresh_rate != 0xff) {
185 if ((check_sync) &&
186 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
187 (loop->flags & PVSync)) ||
188 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
189 (loop->flags & NVSync)) ||
190 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
191 (loop->flags & PHSync)) ||
192 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
193 (loop->flags & NHSync)))) {
194 loop++;
195 continue;
196 }
197 if (loop->refresh_rate <= refresh_rate
198 && (!best || loop->refresh_rate > best->refresh_rate))
199 best = loop;
200 loop++;
201 }
202 if (best || !check_sync)
203 break;
204 check_sync = 0;
205 }
206
207 if (best)
208 vbios_mode->enh_table = best;
209
210 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
211 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
212
213 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
214 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
215 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
216 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
217 vbios_mode->enh_table->hfp;
218 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
219 vbios_mode->enh_table->hfp +
220 vbios_mode->enh_table->hsync);
221
222 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
223 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
224 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
225 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
226 vbios_mode->enh_table->vfp;
227 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
228 vbios_mode->enh_table->vfp +
229 vbios_mode->enh_table->vsync);
230
231 return true;
232}
233
234static void ast_set_vbios_color_reg(struct ast_device *ast,
235 const struct drm_format_info *format,
236 const struct ast_vbios_mode_info *vbios_mode)
237{
238 u32 color_index;
239
240 switch (format->cpp[0]) {
241 case 1:
242 color_index = VGAModeIndex - 1;
243 break;
244 case 2:
245 color_index = HiCModeIndex;
246 break;
247 case 3:
248 case 4:
249 color_index = TrueCModeIndex;
250 break;
251 default:
252 return;
253 }
254
255 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8c, (u8)((color_index & 0x0f) << 4));
256
257 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00);
258
259 if (vbios_mode->enh_table->flags & NewModeInfo) {
260 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8);
261 ast_set_index_reg(ast, AST_IO_VGACRI, 0x92, format->cpp[0] * 8);
262 }
263}
264
265static void ast_set_vbios_mode_reg(struct ast_device *ast,
266 const struct drm_display_mode *adjusted_mode,
267 const struct ast_vbios_mode_info *vbios_mode)
268{
269 u32 refresh_rate_index, mode_id;
270
271 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
272 mode_id = vbios_mode->enh_table->mode_id;
273
274 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8d, refresh_rate_index & 0xff);
275 ast_set_index_reg(ast, AST_IO_VGACRI, 0x8e, mode_id & 0xff);
276
277 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0x00);
278
279 if (vbios_mode->enh_table->flags & NewModeInfo) {
280 ast_set_index_reg(ast, AST_IO_VGACRI, 0x91, 0xa8);
281 ast_set_index_reg(ast, AST_IO_VGACRI, 0x93, adjusted_mode->clock / 1000);
282 ast_set_index_reg(ast, AST_IO_VGACRI, 0x94, adjusted_mode->crtc_hdisplay);
283 ast_set_index_reg(ast, AST_IO_VGACRI, 0x95, adjusted_mode->crtc_hdisplay >> 8);
284 ast_set_index_reg(ast, AST_IO_VGACRI, 0x96, adjusted_mode->crtc_vdisplay);
285 ast_set_index_reg(ast, AST_IO_VGACRI, 0x97, adjusted_mode->crtc_vdisplay >> 8);
286 }
287}
288
289static void ast_set_std_reg(struct ast_device *ast,
290 struct drm_display_mode *mode,
291 struct ast_vbios_mode_info *vbios_mode)
292{
293 const struct ast_vbios_stdtable *stdtable;
294 u32 i;
295 u8 jreg;
296
297 stdtable = vbios_mode->std_table;
298
299 jreg = stdtable->misc;
300 ast_io_write8(ast, AST_IO_VGAMR_W, jreg);
301
302 /* Set SEQ; except Screen Disable field */
303 ast_set_index_reg(ast, AST_IO_VGASRI, 0x00, 0x03);
304 ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0x20, stdtable->seq[0]);
305 for (i = 1; i < 4; i++) {
306 jreg = stdtable->seq[i];
307 ast_set_index_reg(ast, AST_IO_VGASRI, (i + 1), jreg);
308 }
309
310 /* Set CRTC; except base address and offset */
311 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00);
312 for (i = 0; i < 12; i++)
313 ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]);
314 for (i = 14; i < 19; i++)
315 ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]);
316 for (i = 20; i < 25; i++)
317 ast_set_index_reg(ast, AST_IO_VGACRI, i, stdtable->crtc[i]);
318
319 /* set AR */
320 jreg = ast_io_read8(ast, AST_IO_VGAIR1_R);
321 for (i = 0; i < 20; i++) {
322 jreg = stdtable->ar[i];
323 ast_io_write8(ast, AST_IO_VGAARI_W, (u8)i);
324 ast_io_write8(ast, AST_IO_VGAARI_W, jreg);
325 }
326 ast_io_write8(ast, AST_IO_VGAARI_W, 0x14);
327 ast_io_write8(ast, AST_IO_VGAARI_W, 0x00);
328
329 jreg = ast_io_read8(ast, AST_IO_VGAIR1_R);
330 ast_io_write8(ast, AST_IO_VGAARI_W, 0x20);
331
332 /* Set GR */
333 for (i = 0; i < 9; i++)
334 ast_set_index_reg(ast, AST_IO_VGAGRI, i, stdtable->gr[i]);
335}
336
337static void ast_set_crtc_reg(struct ast_device *ast,
338 struct drm_display_mode *mode,
339 struct ast_vbios_mode_info *vbios_mode)
340{
341 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
342 u16 temp, precache = 0;
343
344 if ((IS_AST_GEN6(ast) || IS_AST_GEN7(ast)) &&
345 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
346 precache = 40;
347
348 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x00);
349
350 temp = (mode->crtc_htotal >> 3) - 5;
351 if (temp & 0x100)
352 jregAC |= 0x01; /* HT D[8] */
353 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x00, 0x00, temp);
354
355 temp = (mode->crtc_hdisplay >> 3) - 1;
356 if (temp & 0x100)
357 jregAC |= 0x04; /* HDE D[8] */
358 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x01, 0x00, temp);
359
360 temp = (mode->crtc_hblank_start >> 3) - 1;
361 if (temp & 0x100)
362 jregAC |= 0x10; /* HBS D[8] */
363 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x02, 0x00, temp);
364
365 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
366 if (temp & 0x20)
367 jreg05 |= 0x80; /* HBE D[5] */
368 if (temp & 0x40)
369 jregAD |= 0x01; /* HBE D[5] */
370 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x03, 0xE0, (temp & 0x1f));
371
372 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
373 if (temp & 0x100)
374 jregAC |= 0x40; /* HRS D[5] */
375 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x04, 0x00, temp);
376
377 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
378 if (temp & 0x20)
379 jregAD |= 0x04; /* HRE D[5] */
380 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
381
382 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAC, 0x00, jregAC);
383 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAD, 0x00, jregAD);
384
385 // Workaround for HSync Time non octave pixels (1920x1080@60Hz HSync 44 pixels);
386 if (IS_AST_GEN7(ast) && (mode->crtc_vdisplay == 1080))
387 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xFC, 0xFD, 0x02);
388 else
389 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xFC, 0xFD, 0x00);
390
391 /* vert timings */
392 temp = (mode->crtc_vtotal) - 2;
393 if (temp & 0x100)
394 jreg07 |= 0x01;
395 if (temp & 0x200)
396 jreg07 |= 0x20;
397 if (temp & 0x400)
398 jregAE |= 0x01;
399 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x06, 0x00, temp);
400
401 temp = (mode->crtc_vsync_start) - 1;
402 if (temp & 0x100)
403 jreg07 |= 0x04;
404 if (temp & 0x200)
405 jreg07 |= 0x80;
406 if (temp & 0x400)
407 jregAE |= 0x08;
408 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x10, 0x00, temp);
409
410 temp = (mode->crtc_vsync_end - 1) & 0x3f;
411 if (temp & 0x10)
412 jregAE |= 0x20;
413 if (temp & 0x20)
414 jregAE |= 0x40;
415 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x70, temp & 0xf);
416
417 temp = mode->crtc_vdisplay - 1;
418 if (temp & 0x100)
419 jreg07 |= 0x02;
420 if (temp & 0x200)
421 jreg07 |= 0x40;
422 if (temp & 0x400)
423 jregAE |= 0x02;
424 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x12, 0x00, temp);
425
426 temp = mode->crtc_vblank_start - 1;
427 if (temp & 0x100)
428 jreg07 |= 0x08;
429 if (temp & 0x200)
430 jreg09 |= 0x20;
431 if (temp & 0x400)
432 jregAE |= 0x04;
433 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x15, 0x00, temp);
434
435 temp = mode->crtc_vblank_end - 1;
436 if (temp & 0x100)
437 jregAE |= 0x10;
438 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x16, 0x00, temp);
439
440 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x07, 0x00, jreg07);
441 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x09, 0xdf, jreg09);
442 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xAE, 0x00, (jregAE | 0x80));
443
444 if (precache)
445 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0x3f, 0x80);
446 else
447 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0x3f, 0x00);
448
449 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x11, 0x7f, 0x80);
450}
451
452static void ast_set_offset_reg(struct ast_device *ast,
453 struct drm_framebuffer *fb)
454{
455 u16 offset;
456
457 offset = fb->pitches[0] >> 3;
458 ast_set_index_reg(ast, AST_IO_VGACRI, 0x13, (offset & 0xff));
459 ast_set_index_reg(ast, AST_IO_VGACRI, 0xb0, (offset >> 8) & 0x3f);
460}
461
462static void ast_set_dclk_reg(struct ast_device *ast,
463 struct drm_display_mode *mode,
464 struct ast_vbios_mode_info *vbios_mode)
465{
466 const struct ast_vbios_dclk_info *clk_info;
467
468 if (IS_AST_GEN6(ast) || IS_AST_GEN7(ast))
469 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
470 else
471 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
472
473 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xc0, 0x00, clk_info->param1);
474 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xc1, 0x00, clk_info->param2);
475 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xbb, 0x0f,
476 (clk_info->param3 & 0xc0) |
477 ((clk_info->param3 & 0x3) << 4));
478}
479
480static void ast_set_color_reg(struct ast_device *ast,
481 const struct drm_format_info *format)
482{
483 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
484
485 switch (format->cpp[0] * 8) {
486 case 8:
487 jregA0 = 0x70;
488 jregA3 = 0x01;
489 jregA8 = 0x00;
490 break;
491 case 15:
492 case 16:
493 jregA0 = 0x70;
494 jregA3 = 0x04;
495 jregA8 = 0x02;
496 break;
497 case 32:
498 jregA0 = 0x70;
499 jregA3 = 0x08;
500 jregA8 = 0x02;
501 break;
502 }
503
504 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa0, 0x8f, jregA0);
505 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xf0, jregA3);
506 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa8, 0xfd, jregA8);
507}
508
509static void ast_set_crtthd_reg(struct ast_device *ast)
510{
511 /* Set Threshold */
512 if (IS_AST_GEN7(ast)) {
513 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa7, 0xe0);
514 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa6, 0xa0);
515 } else if (IS_AST_GEN6(ast) || IS_AST_GEN5(ast) || IS_AST_GEN4(ast)) {
516 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa7, 0x78);
517 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa6, 0x60);
518 } else if (IS_AST_GEN3(ast) || IS_AST_GEN2(ast)) {
519 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa7, 0x3f);
520 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa6, 0x2f);
521 } else {
522 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa7, 0x2f);
523 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa6, 0x1f);
524 }
525}
526
527static void ast_set_sync_reg(struct ast_device *ast,
528 struct drm_display_mode *mode,
529 struct ast_vbios_mode_info *vbios_mode)
530{
531 u8 jreg;
532
533 jreg = ast_io_read8(ast, AST_IO_VGAMR_R);
534 jreg &= ~0xC0;
535 if (vbios_mode->enh_table->flags & NVSync)
536 jreg |= 0x80;
537 if (vbios_mode->enh_table->flags & NHSync)
538 jreg |= 0x40;
539 ast_io_write8(ast, AST_IO_VGAMR_W, jreg);
540}
541
542static void ast_set_start_address_crt1(struct ast_device *ast,
543 unsigned int offset)
544{
545 u32 addr;
546
547 addr = offset >> 2;
548 ast_set_index_reg(ast, AST_IO_VGACRI, 0x0d, (u8)(addr & 0xff));
549 ast_set_index_reg(ast, AST_IO_VGACRI, 0x0c, (u8)((addr >> 8) & 0xff));
550 ast_set_index_reg(ast, AST_IO_VGACRI, 0xaf, (u8)((addr >> 16) & 0xff));
551
552}
553
554static void ast_wait_for_vretrace(struct ast_device *ast)
555{
556 unsigned long timeout = jiffies + HZ;
557 u8 vgair1;
558
559 do {
560 vgair1 = ast_io_read8(ast, AST_IO_VGAIR1_R);
561 } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
562}
563
564/*
565 * Planes
566 */
567
568static int ast_plane_init(struct drm_device *dev, struct ast_plane *ast_plane,
569 void __iomem *vaddr, u64 offset, unsigned long size,
570 uint32_t possible_crtcs,
571 const struct drm_plane_funcs *funcs,
572 const uint32_t *formats, unsigned int format_count,
573 const uint64_t *format_modifiers,
574 enum drm_plane_type type)
575{
576 struct drm_plane *plane = &ast_plane->base;
577
578 ast_plane->vaddr = vaddr;
579 ast_plane->offset = offset;
580 ast_plane->size = size;
581
582 return drm_universal_plane_init(dev, plane, possible_crtcs, funcs,
583 formats, format_count, format_modifiers,
584 type, NULL);
585}
586
587/*
588 * Primary plane
589 */
590
591static const uint32_t ast_primary_plane_formats[] = {
592 DRM_FORMAT_XRGB8888,
593 DRM_FORMAT_RGB565,
594 DRM_FORMAT_C8,
595};
596
597static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
598 struct drm_atomic_state *state)
599{
600 struct drm_device *dev = plane->dev;
601 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
602 struct drm_crtc_state *new_crtc_state = NULL;
603 struct ast_crtc_state *new_ast_crtc_state;
604 int ret;
605
606 if (new_plane_state->crtc)
607 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
608
609 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
610 DRM_PLANE_NO_SCALING,
611 DRM_PLANE_NO_SCALING,
612 false, true);
613 if (ret) {
614 return ret;
615 } else if (!new_plane_state->visible) {
616 if (drm_WARN_ON(dev, new_plane_state->crtc)) /* cannot legally happen */
617 return -EINVAL;
618 else
619 return 0;
620 }
621
622 new_ast_crtc_state = to_ast_crtc_state(new_crtc_state);
623
624 new_ast_crtc_state->format = new_plane_state->fb->format;
625
626 return 0;
627}
628
629static void ast_handle_damage(struct ast_plane *ast_plane, struct iosys_map *src,
630 struct drm_framebuffer *fb,
631 const struct drm_rect *clip)
632{
633 struct iosys_map dst = IOSYS_MAP_INIT_VADDR_IOMEM(ast_plane->vaddr);
634
635 iosys_map_incr(&dst, drm_fb_clip_offset(fb->pitches[0], fb->format, clip));
636 drm_fb_memcpy(&dst, fb->pitches, src, fb, clip);
637}
638
639static void ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
640 struct drm_atomic_state *state)
641{
642 struct drm_device *dev = plane->dev;
643 struct ast_device *ast = to_ast_device(dev);
644 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
645 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
646 struct drm_framebuffer *fb = plane_state->fb;
647 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
648 struct drm_framebuffer *old_fb = old_plane_state->fb;
649 struct ast_plane *ast_plane = to_ast_plane(plane);
650 struct drm_crtc *crtc = plane_state->crtc;
651 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
652 struct drm_rect damage;
653 struct drm_atomic_helper_damage_iter iter;
654
655 if (!old_fb || (fb->format != old_fb->format) || crtc_state->mode_changed) {
656 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
657 struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
658
659 ast_set_color_reg(ast, fb->format);
660 ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info);
661 }
662
663 drm_atomic_helper_damage_iter_init(&iter, old_plane_state, plane_state);
664 drm_atomic_for_each_plane_damage(&iter, &damage) {
665 ast_handle_damage(ast_plane, shadow_plane_state->data, fb, &damage);
666 }
667
668 /*
669 * Some BMCs stop scanning out the video signal after the driver
670 * reprogrammed the offset. This stalls display output for several
671 * seconds and makes the display unusable. Therefore only update
672 * the offset if it changes.
673 */
674 if (!old_fb || old_fb->pitches[0] != fb->pitches[0])
675 ast_set_offset_reg(ast, fb);
676}
677
678static void ast_primary_plane_helper_atomic_enable(struct drm_plane *plane,
679 struct drm_atomic_state *state)
680{
681 struct ast_device *ast = to_ast_device(plane->dev);
682 struct ast_plane *ast_plane = to_ast_plane(plane);
683
684 /*
685 * Some BMCs stop scanning out the video signal after the driver
686 * reprogrammed the scanout address. This stalls display
687 * output for several seconds and makes the display unusable.
688 * Therefore only reprogram the address after enabling the plane.
689 */
690 ast_set_start_address_crt1(ast, (u32)ast_plane->offset);
691}
692
693static void ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
694 struct drm_atomic_state *state)
695{
696 /*
697 * Keep this empty function to avoid calling
698 * atomic_update when disabling the plane.
699 */
700}
701
702static int ast_primary_plane_helper_get_scanout_buffer(struct drm_plane *plane,
703 struct drm_scanout_buffer *sb)
704{
705 struct ast_plane *ast_plane = to_ast_plane(plane);
706
707 if (plane->state && plane->state->fb && ast_plane->vaddr) {
708 sb->format = plane->state->fb->format;
709 sb->width = plane->state->fb->width;
710 sb->height = plane->state->fb->height;
711 sb->pitch[0] = plane->state->fb->pitches[0];
712 iosys_map_set_vaddr_iomem(&sb->map[0], ast_plane->vaddr);
713 return 0;
714 }
715 return -ENODEV;
716}
717
718static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
719 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
720 .atomic_check = ast_primary_plane_helper_atomic_check,
721 .atomic_update = ast_primary_plane_helper_atomic_update,
722 .atomic_enable = ast_primary_plane_helper_atomic_enable,
723 .atomic_disable = ast_primary_plane_helper_atomic_disable,
724 .get_scanout_buffer = ast_primary_plane_helper_get_scanout_buffer,
725};
726
727static const struct drm_plane_funcs ast_primary_plane_funcs = {
728 .update_plane = drm_atomic_helper_update_plane,
729 .disable_plane = drm_atomic_helper_disable_plane,
730 .destroy = drm_plane_cleanup,
731 DRM_GEM_SHADOW_PLANE_FUNCS,
732};
733
734static int ast_primary_plane_init(struct ast_device *ast)
735{
736 struct drm_device *dev = &ast->base;
737 struct ast_plane *ast_primary_plane = &ast->primary_plane;
738 struct drm_plane *primary_plane = &ast_primary_plane->base;
739 void __iomem *vaddr = ast->vram;
740 u64 offset = 0; /* with shmem, the primary plane is always at offset 0 */
741 unsigned long cursor_size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
742 unsigned long size = ast->vram_fb_available - cursor_size;
743 int ret;
744
745 ret = ast_plane_init(dev, ast_primary_plane, vaddr, offset, size,
746 0x01, &ast_primary_plane_funcs,
747 ast_primary_plane_formats, ARRAY_SIZE(ast_primary_plane_formats),
748 NULL, DRM_PLANE_TYPE_PRIMARY);
749 if (ret) {
750 drm_err(dev, "ast_plane_init() failed: %d\n", ret);
751 return ret;
752 }
753 drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs);
754 drm_plane_enable_fb_damage_clips(primary_plane);
755
756 return 0;
757}
758
759/*
760 * Cursor plane
761 */
762
763static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height)
764{
765 union {
766 u32 ul;
767 u8 b[4];
768 } srcdata32[2], data32;
769 union {
770 u16 us;
771 u8 b[2];
772 } data16;
773 u32 csum = 0;
774 s32 alpha_dst_delta, last_alpha_dst_delta;
775 u8 __iomem *dstxor;
776 const u8 *srcxor;
777 int i, j;
778 u32 per_pixel_copy, two_pixel_copy;
779
780 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
781 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
782
783 srcxor = src;
784 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
785 per_pixel_copy = width & 1;
786 two_pixel_copy = width >> 1;
787
788 for (j = 0; j < height; j++) {
789 for (i = 0; i < two_pixel_copy; i++) {
790 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
791 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
792 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
793 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
794 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
795 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
796
797 writel(data32.ul, dstxor);
798 csum += data32.ul;
799
800 dstxor += 4;
801 srcxor += 8;
802
803 }
804
805 for (i = 0; i < per_pixel_copy; i++) {
806 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
807 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
808 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
809 writew(data16.us, dstxor);
810 csum += (u32)data16.us;
811
812 dstxor += 2;
813 srcxor += 4;
814 }
815 dstxor += last_alpha_dst_delta;
816 }
817
818 /* write checksum + signature */
819 dst += AST_HWC_SIZE;
820 writel(csum, dst);
821 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
822 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
823 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
824 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
825}
826
827static void ast_set_cursor_base(struct ast_device *ast, u64 address)
828{
829 u8 addr0 = (address >> 3) & 0xff;
830 u8 addr1 = (address >> 11) & 0xff;
831 u8 addr2 = (address >> 19) & 0xff;
832
833 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc8, addr0);
834 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc9, addr1);
835 ast_set_index_reg(ast, AST_IO_VGACRI, 0xca, addr2);
836}
837
838static void ast_set_cursor_location(struct ast_device *ast, u16 x, u16 y,
839 u8 x_offset, u8 y_offset)
840{
841 u8 x0 = (x & 0x00ff);
842 u8 x1 = (x & 0x0f00) >> 8;
843 u8 y0 = (y & 0x00ff);
844 u8 y1 = (y & 0x0700) >> 8;
845
846 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc2, x_offset);
847 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc3, y_offset);
848 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc4, x0);
849 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc5, x1);
850 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc6, y0);
851 ast_set_index_reg(ast, AST_IO_VGACRI, 0xc7, y1);
852}
853
854static void ast_set_cursor_enabled(struct ast_device *ast, bool enabled)
855{
856 static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP |
857 AST_IO_VGACRCB_HWC_ENABLED);
858
859 u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP;
860
861 if (enabled)
862 vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED;
863
864 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xcb, mask, vgacrcb);
865}
866
867static const uint32_t ast_cursor_plane_formats[] = {
868 DRM_FORMAT_ARGB8888,
869};
870
871static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
872 struct drm_atomic_state *state)
873{
874 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
875 struct drm_framebuffer *new_fb = new_plane_state->fb;
876 struct drm_crtc_state *new_crtc_state = NULL;
877 int ret;
878
879 if (new_plane_state->crtc)
880 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc);
881
882 ret = drm_atomic_helper_check_plane_state(new_plane_state, new_crtc_state,
883 DRM_PLANE_NO_SCALING,
884 DRM_PLANE_NO_SCALING,
885 true, true);
886 if (ret || !new_plane_state->visible)
887 return ret;
888
889 if (new_fb->width > AST_MAX_HWC_WIDTH || new_fb->height > AST_MAX_HWC_HEIGHT)
890 return -EINVAL;
891
892 return 0;
893}
894
895static void ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
896 struct drm_atomic_state *state)
897{
898 struct ast_plane *ast_plane = to_ast_plane(plane);
899 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, plane);
900 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(plane_state);
901 struct drm_framebuffer *fb = plane_state->fb;
902 struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
903 struct ast_device *ast = to_ast_device(plane->dev);
904 struct iosys_map src_map = shadow_plane_state->data[0];
905 struct drm_rect damage;
906 const u8 *src = src_map.vaddr; /* TODO: Use mapping abstraction properly */
907 u64 dst_off = ast_plane->offset;
908 u8 __iomem *dst = ast_plane->vaddr; /* TODO: Use mapping abstraction properly */
909 u8 __iomem *sig = dst + AST_HWC_SIZE; /* TODO: Use mapping abstraction properly */
910 unsigned int offset_x, offset_y;
911 u16 x, y;
912 u8 x_offset, y_offset;
913
914 /*
915 * Do data transfer to hardware buffer and point the scanout
916 * engine to the offset.
917 */
918
919 if (drm_atomic_helper_damage_merged(old_plane_state, plane_state, &damage)) {
920 ast_update_cursor_image(dst, src, fb->width, fb->height);
921 ast_set_cursor_base(ast, dst_off);
922 }
923
924 /*
925 * Update location in HWC signature and registers.
926 */
927
928 writel(plane_state->crtc_x, sig + AST_HWC_SIGNATURE_X);
929 writel(plane_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
930
931 offset_x = AST_MAX_HWC_WIDTH - fb->width;
932 offset_y = AST_MAX_HWC_HEIGHT - fb->height;
933
934 if (plane_state->crtc_x < 0) {
935 x_offset = (-plane_state->crtc_x) + offset_x;
936 x = 0;
937 } else {
938 x_offset = offset_x;
939 x = plane_state->crtc_x;
940 }
941 if (plane_state->crtc_y < 0) {
942 y_offset = (-plane_state->crtc_y) + offset_y;
943 y = 0;
944 } else {
945 y_offset = offset_y;
946 y = plane_state->crtc_y;
947 }
948
949 ast_set_cursor_location(ast, x, y, x_offset, y_offset);
950
951 /* Dummy write to enable HWC and make the HW pick-up the changes. */
952 ast_set_cursor_enabled(ast, true);
953}
954
955static void ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
956 struct drm_atomic_state *state)
957{
958 struct ast_device *ast = to_ast_device(plane->dev);
959
960 ast_set_cursor_enabled(ast, false);
961}
962
963static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
964 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
965 .atomic_check = ast_cursor_plane_helper_atomic_check,
966 .atomic_update = ast_cursor_plane_helper_atomic_update,
967 .atomic_disable = ast_cursor_plane_helper_atomic_disable,
968};
969
970static const struct drm_plane_funcs ast_cursor_plane_funcs = {
971 .update_plane = drm_atomic_helper_update_plane,
972 .disable_plane = drm_atomic_helper_disable_plane,
973 .destroy = drm_plane_cleanup,
974 DRM_GEM_SHADOW_PLANE_FUNCS,
975};
976
977static int ast_cursor_plane_init(struct ast_device *ast)
978{
979 struct drm_device *dev = &ast->base;
980 struct ast_plane *ast_cursor_plane = &ast->cursor_plane;
981 struct drm_plane *cursor_plane = &ast_cursor_plane->base;
982 size_t size;
983 void __iomem *vaddr;
984 u64 offset;
985 int ret;
986
987 /*
988 * Allocate backing storage for cursors. The BOs are permanently
989 * pinned to the top end of the VRAM.
990 */
991
992 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
993
994 if (ast->vram_fb_available < size)
995 return -ENOMEM;
996
997 vaddr = ast->vram + ast->vram_fb_available - size;
998 offset = ast->vram_fb_available - size;
999
1000 ret = ast_plane_init(dev, ast_cursor_plane, vaddr, offset, size,
1001 0x01, &ast_cursor_plane_funcs,
1002 ast_cursor_plane_formats, ARRAY_SIZE(ast_cursor_plane_formats),
1003 NULL, DRM_PLANE_TYPE_CURSOR);
1004 if (ret) {
1005 drm_err(dev, "ast_plane_init() failed: %d\n", ret);
1006 return ret;
1007 }
1008 drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs);
1009 drm_plane_enable_fb_damage_clips(cursor_plane);
1010
1011 ast->vram_fb_available -= size;
1012
1013 return 0;
1014}
1015
1016/*
1017 * CRTC
1018 */
1019
1020static enum drm_mode_status
1021ast_crtc_helper_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
1022{
1023 struct ast_device *ast = to_ast_device(crtc->dev);
1024 enum drm_mode_status status;
1025 uint32_t jtemp;
1026
1027 if (ast->support_wide_screen) {
1028 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1029 return MODE_OK;
1030 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1031 return MODE_OK;
1032 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1033 return MODE_OK;
1034 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1035 return MODE_OK;
1036 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1037 return MODE_OK;
1038 if ((mode->hdisplay == 1152) && (mode->vdisplay == 864))
1039 return MODE_OK;
1040
1041 if ((ast->chip == AST2100) || // GEN2, but not AST1100 (?)
1042 (ast->chip == AST2200) || // GEN3, but not AST2150 (?)
1043 IS_AST_GEN4(ast) || IS_AST_GEN5(ast) ||
1044 IS_AST_GEN6(ast) || IS_AST_GEN7(ast)) {
1045 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1046 return MODE_OK;
1047
1048 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1049 jtemp = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 0xff);
1050 if (jtemp & 0x01)
1051 return MODE_NOMODE;
1052 else
1053 return MODE_OK;
1054 }
1055 }
1056 }
1057
1058 status = MODE_NOMODE;
1059
1060 switch (mode->hdisplay) {
1061 case 640:
1062 if (mode->vdisplay == 480)
1063 status = MODE_OK;
1064 break;
1065 case 800:
1066 if (mode->vdisplay == 600)
1067 status = MODE_OK;
1068 break;
1069 case 1024:
1070 if (mode->vdisplay == 768)
1071 status = MODE_OK;
1072 break;
1073 case 1152:
1074 if (mode->vdisplay == 864)
1075 status = MODE_OK;
1076 break;
1077 case 1280:
1078 if (mode->vdisplay == 1024)
1079 status = MODE_OK;
1080 break;
1081 case 1600:
1082 if (mode->vdisplay == 1200)
1083 status = MODE_OK;
1084 break;
1085 default:
1086 break;
1087 }
1088
1089 return status;
1090}
1091
1092static void ast_crtc_helper_mode_set_nofb(struct drm_crtc *crtc)
1093{
1094 struct drm_device *dev = crtc->dev;
1095 struct ast_device *ast = to_ast_device(dev);
1096 struct drm_crtc_state *crtc_state = crtc->state;
1097 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1098 struct ast_vbios_mode_info *vbios_mode_info =
1099 &ast_crtc_state->vbios_mode_info;
1100 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1101
1102 /*
1103 * Ensure that no scanout takes place before reprogramming mode
1104 * and format registers.
1105 *
1106 * TODO: Get vblank interrupts working and remove this line.
1107 */
1108 ast_wait_for_vretrace(ast);
1109
1110 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
1111 ast_set_index_reg(ast, AST_IO_VGACRI, 0xa1, 0x06);
1112 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
1113 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
1114 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
1115 ast_set_crtthd_reg(ast);
1116 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
1117}
1118
1119static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
1120 struct drm_atomic_state *state)
1121{
1122 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1123 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1124 struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
1125 struct drm_device *dev = crtc->dev;
1126 struct ast_crtc_state *ast_state;
1127 const struct drm_format_info *format;
1128 bool succ;
1129 int ret;
1130
1131 if (!crtc_state->enable)
1132 return 0;
1133
1134 ret = drm_atomic_helper_check_crtc_primary_plane(crtc_state);
1135 if (ret)
1136 return ret;
1137
1138 ast_state = to_ast_crtc_state(crtc_state);
1139
1140 format = ast_state->format;
1141 if (drm_WARN_ON_ONCE(dev, !format))
1142 return -EINVAL; /* BUG: We didn't set format in primary check(). */
1143
1144 /*
1145 * The gamma LUT has to be reloaded after changing the primary
1146 * plane's color format.
1147 */
1148 if (old_ast_crtc_state->format != format)
1149 crtc_state->color_mgmt_changed = true;
1150
1151 if (crtc_state->color_mgmt_changed && crtc_state->gamma_lut) {
1152 if (crtc_state->gamma_lut->length !=
1153 AST_LUT_SIZE * sizeof(struct drm_color_lut)) {
1154 drm_err(dev, "Wrong size for gamma_lut %zu\n",
1155 crtc_state->gamma_lut->length);
1156 return -EINVAL;
1157 }
1158 }
1159
1160 succ = ast_get_vbios_mode_info(format, &crtc_state->mode,
1161 &crtc_state->adjusted_mode,
1162 &ast_state->vbios_mode_info);
1163 if (!succ)
1164 return -EINVAL;
1165
1166 return 0;
1167}
1168
1169static void
1170ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
1171 struct drm_atomic_state *state)
1172{
1173 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1174 crtc);
1175 struct drm_device *dev = crtc->dev;
1176 struct ast_device *ast = to_ast_device(dev);
1177 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1178
1179 /*
1180 * The gamma LUT has to be reloaded after changing the primary
1181 * plane's color format.
1182 */
1183 if (crtc_state->enable && crtc_state->color_mgmt_changed) {
1184 if (crtc_state->gamma_lut)
1185 ast_crtc_set_gamma(ast,
1186 ast_crtc_state->format,
1187 crtc_state->gamma_lut->data);
1188 else
1189 ast_crtc_set_gamma_linear(ast, ast_crtc_state->format);
1190 }
1191}
1192
1193static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state)
1194{
1195 struct ast_device *ast = to_ast_device(crtc->dev);
1196
1197 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, 0x00);
1198 ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, 0x00);
1199}
1200
1201static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state)
1202{
1203 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
1204 struct ast_device *ast = to_ast_device(crtc->dev);
1205 u8 vgacrb6;
1206
1207 ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, AST_IO_VGASR1_SD);
1208
1209 vgacrb6 = AST_IO_VGACRB6_VSYNC_OFF |
1210 AST_IO_VGACRB6_HSYNC_OFF;
1211 ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6);
1212
1213 /*
1214 * HW cursors require the underlying primary plane and CRTC to
1215 * display a valid mode and image. This is not the case during
1216 * full modeset operations. So we temporarily disable any active
1217 * plane, including the HW cursor. Each plane's atomic_update()
1218 * helper will re-enable it if necessary.
1219 *
1220 * We only do this during *full* modesets. It does not affect
1221 * simple pageflips on the planes.
1222 */
1223 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1224}
1225
1226static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
1227 .mode_valid = ast_crtc_helper_mode_valid,
1228 .mode_set_nofb = ast_crtc_helper_mode_set_nofb,
1229 .atomic_check = ast_crtc_helper_atomic_check,
1230 .atomic_flush = ast_crtc_helper_atomic_flush,
1231 .atomic_enable = ast_crtc_helper_atomic_enable,
1232 .atomic_disable = ast_crtc_helper_atomic_disable,
1233};
1234
1235static void ast_crtc_reset(struct drm_crtc *crtc)
1236{
1237 struct ast_crtc_state *ast_state =
1238 kzalloc(sizeof(*ast_state), GFP_KERNEL);
1239
1240 if (crtc->state)
1241 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
1242
1243 if (ast_state)
1244 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
1245 else
1246 __drm_atomic_helper_crtc_reset(crtc, NULL);
1247}
1248
1249static struct drm_crtc_state *
1250ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1251{
1252 struct ast_crtc_state *new_ast_state, *ast_state;
1253 struct drm_device *dev = crtc->dev;
1254
1255 if (drm_WARN_ON(dev, !crtc->state))
1256 return NULL;
1257
1258 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
1259 if (!new_ast_state)
1260 return NULL;
1261 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
1262
1263 ast_state = to_ast_crtc_state(crtc->state);
1264
1265 new_ast_state->format = ast_state->format;
1266 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
1267 sizeof(new_ast_state->vbios_mode_info));
1268
1269 return &new_ast_state->base;
1270}
1271
1272static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1273 struct drm_crtc_state *state)
1274{
1275 struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
1276
1277 __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
1278 kfree(ast_state);
1279}
1280
1281static const struct drm_crtc_funcs ast_crtc_funcs = {
1282 .reset = ast_crtc_reset,
1283 .destroy = drm_crtc_cleanup,
1284 .set_config = drm_atomic_helper_set_config,
1285 .page_flip = drm_atomic_helper_page_flip,
1286 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
1287 .atomic_destroy_state = ast_crtc_atomic_destroy_state,
1288};
1289
1290static int ast_crtc_init(struct ast_device *ast)
1291{
1292 struct drm_device *dev = &ast->base;
1293 struct drm_crtc *crtc = &ast->crtc;
1294 int ret;
1295
1296 ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane.base,
1297 &ast->cursor_plane.base, &ast_crtc_funcs,
1298 NULL);
1299 if (ret)
1300 return ret;
1301
1302 drm_mode_crtc_set_gamma_size(crtc, AST_LUT_SIZE);
1303 drm_crtc_enable_color_mgmt(crtc, 0, false, AST_LUT_SIZE);
1304
1305 drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs);
1306
1307 return 0;
1308}
1309
1310/*
1311 * Mode config
1312 */
1313
1314static void ast_mode_config_helper_atomic_commit_tail(struct drm_atomic_state *state)
1315{
1316 struct ast_device *ast = to_ast_device(state->dev);
1317
1318 /*
1319 * Concurrent operations could possibly trigger a call to
1320 * drm_connector_helper_funcs.get_modes by trying to read the
1321 * display modes. Protect access to I/O registers by acquiring
1322 * the I/O-register lock. Released in atomic_flush().
1323 */
1324 mutex_lock(&ast->modeset_lock);
1325 drm_atomic_helper_commit_tail(state);
1326 mutex_unlock(&ast->modeset_lock);
1327}
1328
1329static const struct drm_mode_config_helper_funcs ast_mode_config_helper_funcs = {
1330 .atomic_commit_tail = ast_mode_config_helper_atomic_commit_tail,
1331};
1332
1333static enum drm_mode_status ast_mode_config_mode_valid(struct drm_device *dev,
1334 const struct drm_display_mode *mode)
1335{
1336 static const unsigned long max_bpp = 4; /* DRM_FORMAT_XRGB8888 */
1337 struct ast_device *ast = to_ast_device(dev);
1338 unsigned long fbsize, fbpages, max_fbpages;
1339
1340 max_fbpages = (ast->vram_fb_available) >> PAGE_SHIFT;
1341
1342 fbsize = mode->hdisplay * mode->vdisplay * max_bpp;
1343 fbpages = DIV_ROUND_UP(fbsize, PAGE_SIZE);
1344
1345 if (fbpages > max_fbpages)
1346 return MODE_MEM;
1347
1348 return MODE_OK;
1349}
1350
1351static const struct drm_mode_config_funcs ast_mode_config_funcs = {
1352 .fb_create = drm_gem_fb_create_with_dirty,
1353 .mode_valid = ast_mode_config_mode_valid,
1354 .atomic_check = drm_atomic_helper_check,
1355 .atomic_commit = drm_atomic_helper_commit,
1356};
1357
1358int ast_mode_config_init(struct ast_device *ast)
1359{
1360 struct drm_device *dev = &ast->base;
1361 int ret;
1362
1363 ret = drmm_mutex_init(dev, &ast->modeset_lock);
1364 if (ret)
1365 return ret;
1366
1367 ret = drmm_mode_config_init(dev);
1368 if (ret)
1369 return ret;
1370
1371 dev->mode_config.funcs = &ast_mode_config_funcs;
1372 dev->mode_config.min_width = 0;
1373 dev->mode_config.min_height = 0;
1374 dev->mode_config.preferred_depth = 24;
1375
1376 if (ast->chip == AST2100 || // GEN2, but not AST1100 (?)
1377 ast->chip == AST2200 || // GEN3, but not AST2150 (?)
1378 IS_AST_GEN7(ast) ||
1379 IS_AST_GEN6(ast) ||
1380 IS_AST_GEN5(ast) ||
1381 IS_AST_GEN4(ast)) {
1382 dev->mode_config.max_width = 1920;
1383 dev->mode_config.max_height = 2048;
1384 } else {
1385 dev->mode_config.max_width = 1600;
1386 dev->mode_config.max_height = 1200;
1387 }
1388
1389 dev->mode_config.helper_private = &ast_mode_config_helper_funcs;
1390
1391 ret = ast_primary_plane_init(ast);
1392 if (ret)
1393 return ret;
1394
1395 ret = ast_cursor_plane_init(ast);
1396 if (ret)
1397 return ret;
1398
1399 ret = ast_crtc_init(ast);
1400 if (ret)
1401 return ret;
1402
1403 switch (ast->tx_chip) {
1404 case AST_TX_NONE:
1405 ret = ast_vga_output_init(ast);
1406 break;
1407 case AST_TX_SIL164:
1408 ret = ast_sil164_output_init(ast);
1409 break;
1410 case AST_TX_DP501:
1411 ret = ast_dp501_output_init(ast);
1412 break;
1413 case AST_TX_ASTDP:
1414 ret = ast_astdp_output_init(ast);
1415 break;
1416 }
1417 if (ret)
1418 return ret;
1419
1420 drm_mode_config_reset(dev);
1421
1422 ret = drmm_kms_helper_poll_init(dev);
1423 if (ret)
1424 return ret;
1425
1426 return 0;
1427}
1/*
2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27/*
28 * Authors: Dave Airlie <airlied@redhat.com>
29 */
30#include <linux/export.h>
31#include <drm/drmP.h>
32#include <drm/drm_crtc.h>
33#include <drm/drm_crtc_helper.h>
34#include <drm/drm_plane_helper.h>
35#include "ast_drv.h"
36
37#include "ast_tables.h"
38
39static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
40static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
41static int ast_cursor_set(struct drm_crtc *crtc,
42 struct drm_file *file_priv,
43 uint32_t handle,
44 uint32_t width,
45 uint32_t height);
46static int ast_cursor_move(struct drm_crtc *crtc,
47 int x, int y);
48
49static inline void ast_load_palette_index(struct ast_private *ast,
50 u8 index, u8 red, u8 green,
51 u8 blue)
52{
53 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
54 ast_io_read8(ast, AST_IO_SEQ_PORT);
55 ast_io_write8(ast, AST_IO_DAC_DATA, red);
56 ast_io_read8(ast, AST_IO_SEQ_PORT);
57 ast_io_write8(ast, AST_IO_DAC_DATA, green);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61}
62
63static void ast_crtc_load_lut(struct drm_crtc *crtc)
64{
65 struct ast_private *ast = crtc->dev->dev_private;
66 u16 *r, *g, *b;
67 int i;
68
69 if (!crtc->enabled)
70 return;
71
72 r = crtc->gamma_store;
73 g = r + crtc->gamma_size;
74 b = g + crtc->gamma_size;
75
76 for (i = 0; i < 256; i++)
77 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
78}
79
80static bool ast_get_vbios_mode_info(struct drm_crtc *crtc, struct drm_display_mode *mode,
81 struct drm_display_mode *adjusted_mode,
82 struct ast_vbios_mode_info *vbios_mode)
83{
84 struct ast_private *ast = crtc->dev->dev_private;
85 const struct drm_framebuffer *fb = crtc->primary->fb;
86 u32 refresh_rate_index = 0, mode_id, color_index, refresh_rate;
87 const struct ast_vbios_enhtable *best = NULL;
88 u32 hborder, vborder;
89 bool check_sync;
90
91 switch (fb->format->cpp[0] * 8) {
92 case 8:
93 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
94 color_index = VGAModeIndex - 1;
95 break;
96 case 16:
97 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
98 color_index = HiCModeIndex;
99 break;
100 case 24:
101 case 32:
102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
103 color_index = TrueCModeIndex;
104 break;
105 default:
106 return false;
107 }
108
109 switch (crtc->mode.crtc_hdisplay) {
110 case 640:
111 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
112 break;
113 case 800:
114 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
115 break;
116 case 1024:
117 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
118 break;
119 case 1280:
120 if (crtc->mode.crtc_vdisplay == 800)
121 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
122 else
123 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
124 break;
125 case 1360:
126 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
127 break;
128 case 1440:
129 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
130 break;
131 case 1600:
132 if (crtc->mode.crtc_vdisplay == 900)
133 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
134 else
135 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
136 break;
137 case 1680:
138 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
139 break;
140 case 1920:
141 if (crtc->mode.crtc_vdisplay == 1080)
142 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
143 else
144 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
145 break;
146 default:
147 return false;
148 }
149
150 refresh_rate = drm_mode_vrefresh(mode);
151 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
152 do {
153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
154
155 while (loop->refresh_rate != 0xff) {
156 if ((check_sync) &&
157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
158 (loop->flags & PVSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
160 (loop->flags & NVSync)) ||
161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
162 (loop->flags & PHSync)) ||
163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
164 (loop->flags & NHSync)))) {
165 loop++;
166 continue;
167 }
168 if (loop->refresh_rate <= refresh_rate
169 && (!best || loop->refresh_rate > best->refresh_rate))
170 best = loop;
171 loop++;
172 }
173 if (best || !check_sync)
174 break;
175 check_sync = 0;
176 } while (1);
177 if (best)
178 vbios_mode->enh_table = best;
179
180 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
181 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
182
183 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
184 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
185 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
186 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
187 vbios_mode->enh_table->hfp;
188 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
189 vbios_mode->enh_table->hfp +
190 vbios_mode->enh_table->hsync);
191
192 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
193 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
194 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
195 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
196 vbios_mode->enh_table->vfp;
197 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
198 vbios_mode->enh_table->vfp +
199 vbios_mode->enh_table->vsync);
200
201 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
202 mode_id = vbios_mode->enh_table->mode_id;
203
204 if (ast->chip == AST1180) {
205 /* TODO 1180 */
206 } else {
207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0xf) << 4));
208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
209 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
210
211 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
212 if (vbios_mode->enh_table->flags & NewModeInfo) {
213 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
214 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92,
215 fb->format->cpp[0] * 8);
216 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
217 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
218 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
219
220 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
221 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
222 }
223 }
224
225 return true;
226
227
228}
229static void ast_set_std_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
230 struct ast_vbios_mode_info *vbios_mode)
231{
232 struct ast_private *ast = crtc->dev->dev_private;
233 const struct ast_vbios_stdtable *stdtable;
234 u32 i;
235 u8 jreg;
236
237 stdtable = vbios_mode->std_table;
238
239 jreg = stdtable->misc;
240 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
241
242 /* Set SEQ */
243 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
244 for (i = 0; i < 4; i++) {
245 jreg = stdtable->seq[i];
246 if (!i)
247 jreg |= 0x20;
248 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
249 }
250
251 /* Set CRTC */
252 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
253 for (i = 0; i < 25; i++)
254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
255
256 /* set AR */
257 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
258 for (i = 0; i < 20; i++) {
259 jreg = stdtable->ar[i];
260 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
261 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
262 }
263 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
264 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
265
266 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
267 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
268
269 /* Set GR */
270 for (i = 0; i < 9; i++)
271 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
272}
273
274static void ast_set_crtc_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
275 struct ast_vbios_mode_info *vbios_mode)
276{
277 struct ast_private *ast = crtc->dev->dev_private;
278 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
279 u16 temp, precache = 0;
280
281 if ((ast->chip == AST2500) &&
282 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
283 precache = 40;
284
285 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
286
287 temp = (mode->crtc_htotal >> 3) - 5;
288 if (temp & 0x100)
289 jregAC |= 0x01; /* HT D[8] */
290 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
291
292 temp = (mode->crtc_hdisplay >> 3) - 1;
293 if (temp & 0x100)
294 jregAC |= 0x04; /* HDE D[8] */
295 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
296
297 temp = (mode->crtc_hblank_start >> 3) - 1;
298 if (temp & 0x100)
299 jregAC |= 0x10; /* HBS D[8] */
300 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
301
302 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
303 if (temp & 0x20)
304 jreg05 |= 0x80; /* HBE D[5] */
305 if (temp & 0x40)
306 jregAD |= 0x01; /* HBE D[5] */
307 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
308
309 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
310 if (temp & 0x100)
311 jregAC |= 0x40; /* HRS D[5] */
312 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
313
314 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
315 if (temp & 0x20)
316 jregAD |= 0x04; /* HRE D[5] */
317 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
318
319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
320 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
321
322 /* vert timings */
323 temp = (mode->crtc_vtotal) - 2;
324 if (temp & 0x100)
325 jreg07 |= 0x01;
326 if (temp & 0x200)
327 jreg07 |= 0x20;
328 if (temp & 0x400)
329 jregAE |= 0x01;
330 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
331
332 temp = (mode->crtc_vsync_start) - 1;
333 if (temp & 0x100)
334 jreg07 |= 0x04;
335 if (temp & 0x200)
336 jreg07 |= 0x80;
337 if (temp & 0x400)
338 jregAE |= 0x08;
339 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
340
341 temp = (mode->crtc_vsync_end - 1) & 0x3f;
342 if (temp & 0x10)
343 jregAE |= 0x20;
344 if (temp & 0x20)
345 jregAE |= 0x40;
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
347
348 temp = mode->crtc_vdisplay - 1;
349 if (temp & 0x100)
350 jreg07 |= 0x02;
351 if (temp & 0x200)
352 jreg07 |= 0x40;
353 if (temp & 0x400)
354 jregAE |= 0x02;
355 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
356
357 temp = mode->crtc_vblank_start - 1;
358 if (temp & 0x100)
359 jreg07 |= 0x08;
360 if (temp & 0x200)
361 jreg09 |= 0x20;
362 if (temp & 0x400)
363 jregAE |= 0x04;
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
365
366 temp = mode->crtc_vblank_end - 1;
367 if (temp & 0x100)
368 jregAE |= 0x10;
369 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
370
371 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
372 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
374
375 if (precache)
376 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
377 else
378 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
379
380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
381}
382
383static void ast_set_offset_reg(struct drm_crtc *crtc)
384{
385 struct ast_private *ast = crtc->dev->dev_private;
386 const struct drm_framebuffer *fb = crtc->primary->fb;
387
388 u16 offset;
389
390 offset = fb->pitches[0] >> 3;
391 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
392 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
393}
394
395static void ast_set_dclk_reg(struct drm_device *dev, struct drm_display_mode *mode,
396 struct ast_vbios_mode_info *vbios_mode)
397{
398 struct ast_private *ast = dev->dev_private;
399 const struct ast_vbios_dclk_info *clk_info;
400
401 if (ast->chip == AST2500)
402 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
403 else
404 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
405
406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
408 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
409 (clk_info->param3 & 0xc0) |
410 ((clk_info->param3 & 0x3) << 4));
411}
412
413static void ast_set_ext_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
414 struct ast_vbios_mode_info *vbios_mode)
415{
416 struct ast_private *ast = crtc->dev->dev_private;
417 const struct drm_framebuffer *fb = crtc->primary->fb;
418 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
419
420 switch (fb->format->cpp[0] * 8) {
421 case 8:
422 jregA0 = 0x70;
423 jregA3 = 0x01;
424 jregA8 = 0x00;
425 break;
426 case 15:
427 case 16:
428 jregA0 = 0x70;
429 jregA3 = 0x04;
430 jregA8 = 0x02;
431 break;
432 case 32:
433 jregA0 = 0x70;
434 jregA3 = 0x08;
435 jregA8 = 0x02;
436 break;
437 }
438
439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
441 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
442
443 /* Set Threshold */
444 if (ast->chip == AST2300 || ast->chip == AST2400 ||
445 ast->chip == AST2500) {
446 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
447 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
448 } else if (ast->chip == AST2100 ||
449 ast->chip == AST1100 ||
450 ast->chip == AST2200 ||
451 ast->chip == AST2150) {
452 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
453 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
454 } else {
455 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
456 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
457 }
458}
459
460static void ast_set_sync_reg(struct drm_device *dev, struct drm_display_mode *mode,
461 struct ast_vbios_mode_info *vbios_mode)
462{
463 struct ast_private *ast = dev->dev_private;
464 u8 jreg;
465
466 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
467 jreg &= ~0xC0;
468 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
469 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
470 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
471}
472
473static bool ast_set_dac_reg(struct drm_crtc *crtc, struct drm_display_mode *mode,
474 struct ast_vbios_mode_info *vbios_mode)
475{
476 const struct drm_framebuffer *fb = crtc->primary->fb;
477
478 switch (fb->format->cpp[0] * 8) {
479 case 8:
480 break;
481 default:
482 return false;
483 }
484 return true;
485}
486
487static void ast_set_start_address_crt1(struct drm_crtc *crtc, unsigned offset)
488{
489 struct ast_private *ast = crtc->dev->dev_private;
490 u32 addr;
491
492 addr = offset >> 2;
493 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
494 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
495 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
496
497}
498
499static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
500{
501 struct ast_private *ast = crtc->dev->dev_private;
502
503 if (ast->chip == AST1180)
504 return;
505
506 switch (mode) {
507 case DRM_MODE_DPMS_ON:
508 case DRM_MODE_DPMS_STANDBY:
509 case DRM_MODE_DPMS_SUSPEND:
510 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
511 if (ast->tx_chip_type == AST_TX_DP501)
512 ast_set_dp501_video_output(crtc->dev, 1);
513 ast_crtc_load_lut(crtc);
514 break;
515 case DRM_MODE_DPMS_OFF:
516 if (ast->tx_chip_type == AST_TX_DP501)
517 ast_set_dp501_video_output(crtc->dev, 0);
518 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
519 break;
520 }
521}
522
523/* ast is different - we will force move buffers out of VRAM */
524static int ast_crtc_do_set_base(struct drm_crtc *crtc,
525 struct drm_framebuffer *fb,
526 int x, int y, int atomic)
527{
528 struct ast_private *ast = crtc->dev->dev_private;
529 struct drm_gem_object *obj;
530 struct ast_framebuffer *ast_fb;
531 struct ast_bo *bo;
532 int ret;
533 u64 gpu_addr;
534
535 /* push the previous fb to system ram */
536 if (!atomic && fb) {
537 ast_fb = to_ast_framebuffer(fb);
538 obj = ast_fb->obj;
539 bo = gem_to_ast_bo(obj);
540 ret = ast_bo_reserve(bo, false);
541 if (ret)
542 return ret;
543 ast_bo_push_sysram(bo);
544 ast_bo_unreserve(bo);
545 }
546
547 ast_fb = to_ast_framebuffer(crtc->primary->fb);
548 obj = ast_fb->obj;
549 bo = gem_to_ast_bo(obj);
550
551 ret = ast_bo_reserve(bo, false);
552 if (ret)
553 return ret;
554
555 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
556 if (ret) {
557 ast_bo_unreserve(bo);
558 return ret;
559 }
560
561 if (&ast->fbdev->afb == ast_fb) {
562 /* if pushing console in kmap it */
563 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
564 if (ret)
565 DRM_ERROR("failed to kmap fbcon\n");
566 else
567 ast_fbdev_set_base(ast, gpu_addr);
568 }
569 ast_bo_unreserve(bo);
570
571 ast_set_start_address_crt1(crtc, (u32)gpu_addr);
572
573 return 0;
574}
575
576static int ast_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
577 struct drm_framebuffer *old_fb)
578{
579 return ast_crtc_do_set_base(crtc, old_fb, x, y, 0);
580}
581
582static int ast_crtc_mode_set(struct drm_crtc *crtc,
583 struct drm_display_mode *mode,
584 struct drm_display_mode *adjusted_mode,
585 int x, int y,
586 struct drm_framebuffer *old_fb)
587{
588 struct drm_device *dev = crtc->dev;
589 struct ast_private *ast = crtc->dev->dev_private;
590 struct ast_vbios_mode_info vbios_mode;
591 bool ret;
592 if (ast->chip == AST1180) {
593 DRM_ERROR("AST 1180 modesetting not supported\n");
594 return -EINVAL;
595 }
596
597 ret = ast_get_vbios_mode_info(crtc, mode, adjusted_mode, &vbios_mode);
598 if (ret == false)
599 return -EINVAL;
600 ast_open_key(ast);
601
602 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x04);
603
604 ast_set_std_reg(crtc, adjusted_mode, &vbios_mode);
605 ast_set_crtc_reg(crtc, adjusted_mode, &vbios_mode);
606 ast_set_offset_reg(crtc);
607 ast_set_dclk_reg(dev, adjusted_mode, &vbios_mode);
608 ast_set_ext_reg(crtc, adjusted_mode, &vbios_mode);
609 ast_set_sync_reg(dev, adjusted_mode, &vbios_mode);
610 ast_set_dac_reg(crtc, adjusted_mode, &vbios_mode);
611
612 ast_crtc_mode_set_base(crtc, x, y, old_fb);
613
614 return 0;
615}
616
617static void ast_crtc_disable(struct drm_crtc *crtc)
618{
619 int ret;
620
621 DRM_DEBUG_KMS("\n");
622 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
623 if (crtc->primary->fb) {
624 struct ast_framebuffer *ast_fb = to_ast_framebuffer(crtc->primary->fb);
625 struct drm_gem_object *obj = ast_fb->obj;
626 struct ast_bo *bo = gem_to_ast_bo(obj);
627
628 ret = ast_bo_reserve(bo, false);
629 if (ret)
630 return;
631
632 ast_bo_push_sysram(bo);
633 ast_bo_unreserve(bo);
634 }
635 crtc->primary->fb = NULL;
636}
637
638static void ast_crtc_prepare(struct drm_crtc *crtc)
639{
640
641}
642
643static void ast_crtc_commit(struct drm_crtc *crtc)
644{
645 struct ast_private *ast = crtc->dev->dev_private;
646 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
647 ast_crtc_load_lut(crtc);
648}
649
650
651static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
652 .dpms = ast_crtc_dpms,
653 .mode_set = ast_crtc_mode_set,
654 .mode_set_base = ast_crtc_mode_set_base,
655 .disable = ast_crtc_disable,
656 .prepare = ast_crtc_prepare,
657 .commit = ast_crtc_commit,
658
659};
660
661static void ast_crtc_reset(struct drm_crtc *crtc)
662{
663
664}
665
666static int ast_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
667 u16 *blue, uint32_t size,
668 struct drm_modeset_acquire_ctx *ctx)
669{
670 ast_crtc_load_lut(crtc);
671
672 return 0;
673}
674
675
676static void ast_crtc_destroy(struct drm_crtc *crtc)
677{
678 drm_crtc_cleanup(crtc);
679 kfree(crtc);
680}
681
682static const struct drm_crtc_funcs ast_crtc_funcs = {
683 .cursor_set = ast_cursor_set,
684 .cursor_move = ast_cursor_move,
685 .reset = ast_crtc_reset,
686 .set_config = drm_crtc_helper_set_config,
687 .gamma_set = ast_crtc_gamma_set,
688 .destroy = ast_crtc_destroy,
689};
690
691static int ast_crtc_init(struct drm_device *dev)
692{
693 struct ast_crtc *crtc;
694
695 crtc = kzalloc(sizeof(struct ast_crtc), GFP_KERNEL);
696 if (!crtc)
697 return -ENOMEM;
698
699 drm_crtc_init(dev, &crtc->base, &ast_crtc_funcs);
700 drm_mode_crtc_set_gamma_size(&crtc->base, 256);
701 drm_crtc_helper_add(&crtc->base, &ast_crtc_helper_funcs);
702 return 0;
703}
704
705static void ast_encoder_destroy(struct drm_encoder *encoder)
706{
707 drm_encoder_cleanup(encoder);
708 kfree(encoder);
709}
710
711
712static struct drm_encoder *ast_best_single_encoder(struct drm_connector *connector)
713{
714 int enc_id = connector->encoder_ids[0];
715 /* pick the encoder ids */
716 if (enc_id)
717 return drm_encoder_find(connector->dev, NULL, enc_id);
718 return NULL;
719}
720
721
722static const struct drm_encoder_funcs ast_enc_funcs = {
723 .destroy = ast_encoder_destroy,
724};
725
726static void ast_encoder_dpms(struct drm_encoder *encoder, int mode)
727{
728
729}
730
731static void ast_encoder_mode_set(struct drm_encoder *encoder,
732 struct drm_display_mode *mode,
733 struct drm_display_mode *adjusted_mode)
734{
735}
736
737static void ast_encoder_prepare(struct drm_encoder *encoder)
738{
739
740}
741
742static void ast_encoder_commit(struct drm_encoder *encoder)
743{
744
745}
746
747
748static const struct drm_encoder_helper_funcs ast_enc_helper_funcs = {
749 .dpms = ast_encoder_dpms,
750 .prepare = ast_encoder_prepare,
751 .commit = ast_encoder_commit,
752 .mode_set = ast_encoder_mode_set,
753};
754
755static int ast_encoder_init(struct drm_device *dev)
756{
757 struct ast_encoder *ast_encoder;
758
759 ast_encoder = kzalloc(sizeof(struct ast_encoder), GFP_KERNEL);
760 if (!ast_encoder)
761 return -ENOMEM;
762
763 drm_encoder_init(dev, &ast_encoder->base, &ast_enc_funcs,
764 DRM_MODE_ENCODER_DAC, NULL);
765 drm_encoder_helper_add(&ast_encoder->base, &ast_enc_helper_funcs);
766
767 ast_encoder->base.possible_crtcs = 1;
768 return 0;
769}
770
771static int ast_get_modes(struct drm_connector *connector)
772{
773 struct ast_connector *ast_connector = to_ast_connector(connector);
774 struct ast_private *ast = connector->dev->dev_private;
775 struct edid *edid;
776 int ret;
777 bool flags = false;
778 if (ast->tx_chip_type == AST_TX_DP501) {
779 ast->dp501_maxclk = 0xff;
780 edid = kmalloc(128, GFP_KERNEL);
781 if (!edid)
782 return -ENOMEM;
783
784 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
785 if (flags)
786 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
787 else
788 kfree(edid);
789 }
790 if (!flags)
791 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
792 if (edid) {
793 drm_mode_connector_update_edid_property(&ast_connector->base, edid);
794 ret = drm_add_edid_modes(connector, edid);
795 kfree(edid);
796 return ret;
797 } else
798 drm_mode_connector_update_edid_property(&ast_connector->base, NULL);
799 return 0;
800}
801
802static int ast_mode_valid(struct drm_connector *connector,
803 struct drm_display_mode *mode)
804{
805 struct ast_private *ast = connector->dev->dev_private;
806 int flags = MODE_NOMODE;
807 uint32_t jtemp;
808
809 if (ast->support_wide_screen) {
810 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
811 return MODE_OK;
812 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
813 return MODE_OK;
814 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
815 return MODE_OK;
816 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
817 return MODE_OK;
818 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
819 return MODE_OK;
820
821 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
822 (ast->chip == AST2300) || (ast->chip == AST2400) ||
823 (ast->chip == AST2500) || (ast->chip == AST1180)) {
824 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
825 return MODE_OK;
826
827 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
828 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
829 if (jtemp & 0x01)
830 return MODE_NOMODE;
831 else
832 return MODE_OK;
833 }
834 }
835 }
836 switch (mode->hdisplay) {
837 case 640:
838 if (mode->vdisplay == 480) flags = MODE_OK;
839 break;
840 case 800:
841 if (mode->vdisplay == 600) flags = MODE_OK;
842 break;
843 case 1024:
844 if (mode->vdisplay == 768) flags = MODE_OK;
845 break;
846 case 1280:
847 if (mode->vdisplay == 1024) flags = MODE_OK;
848 break;
849 case 1600:
850 if (mode->vdisplay == 1200) flags = MODE_OK;
851 break;
852 default:
853 return flags;
854 }
855
856 return flags;
857}
858
859static void ast_connector_destroy(struct drm_connector *connector)
860{
861 struct ast_connector *ast_connector = to_ast_connector(connector);
862 ast_i2c_destroy(ast_connector->i2c);
863 drm_connector_unregister(connector);
864 drm_connector_cleanup(connector);
865 kfree(connector);
866}
867
868static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
869 .mode_valid = ast_mode_valid,
870 .get_modes = ast_get_modes,
871 .best_encoder = ast_best_single_encoder,
872};
873
874static const struct drm_connector_funcs ast_connector_funcs = {
875 .dpms = drm_helper_connector_dpms,
876 .fill_modes = drm_helper_probe_single_connector_modes,
877 .destroy = ast_connector_destroy,
878};
879
880static int ast_connector_init(struct drm_device *dev)
881{
882 struct ast_connector *ast_connector;
883 struct drm_connector *connector;
884 struct drm_encoder *encoder;
885
886 ast_connector = kzalloc(sizeof(struct ast_connector), GFP_KERNEL);
887 if (!ast_connector)
888 return -ENOMEM;
889
890 connector = &ast_connector->base;
891 drm_connector_init(dev, connector, &ast_connector_funcs, DRM_MODE_CONNECTOR_VGA);
892
893 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
894
895 connector->interlace_allowed = 0;
896 connector->doublescan_allowed = 0;
897
898 drm_connector_register(connector);
899
900 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
901
902 encoder = list_first_entry(&dev->mode_config.encoder_list, struct drm_encoder, head);
903 drm_mode_connector_attach_encoder(connector, encoder);
904
905 ast_connector->i2c = ast_i2c_create(dev);
906 if (!ast_connector->i2c)
907 DRM_ERROR("failed to add ddc bus for connector\n");
908
909 return 0;
910}
911
912/* allocate cursor cache and pin at start of VRAM */
913static int ast_cursor_init(struct drm_device *dev)
914{
915 struct ast_private *ast = dev->dev_private;
916 int size;
917 int ret;
918 struct drm_gem_object *obj;
919 struct ast_bo *bo;
920 uint64_t gpu_addr;
921
922 size = (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE) * AST_DEFAULT_HWC_NUM;
923
924 ret = ast_gem_create(dev, size, true, &obj);
925 if (ret)
926 return ret;
927 bo = gem_to_ast_bo(obj);
928 ret = ast_bo_reserve(bo, false);
929 if (unlikely(ret != 0))
930 goto fail;
931
932 ret = ast_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
933 ast_bo_unreserve(bo);
934 if (ret)
935 goto fail;
936
937 /* kmap the object */
938 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &ast->cache_kmap);
939 if (ret)
940 goto fail;
941
942 ast->cursor_cache = obj;
943 ast->cursor_cache_gpu_addr = gpu_addr;
944 DRM_DEBUG_KMS("pinned cursor cache at %llx\n", ast->cursor_cache_gpu_addr);
945 return 0;
946fail:
947 return ret;
948}
949
950static void ast_cursor_fini(struct drm_device *dev)
951{
952 struct ast_private *ast = dev->dev_private;
953 ttm_bo_kunmap(&ast->cache_kmap);
954 drm_gem_object_put_unlocked(ast->cursor_cache);
955}
956
957int ast_mode_init(struct drm_device *dev)
958{
959 ast_cursor_init(dev);
960 ast_crtc_init(dev);
961 ast_encoder_init(dev);
962 ast_connector_init(dev);
963 return 0;
964}
965
966void ast_mode_fini(struct drm_device *dev)
967{
968 ast_cursor_fini(dev);
969}
970
971static int get_clock(void *i2c_priv)
972{
973 struct ast_i2c_chan *i2c = i2c_priv;
974 struct ast_private *ast = i2c->dev->dev_private;
975 uint32_t val;
976
977 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4;
978 return val & 1 ? 1 : 0;
979}
980
981static int get_data(void *i2c_priv)
982{
983 struct ast_i2c_chan *i2c = i2c_priv;
984 struct ast_private *ast = i2c->dev->dev_private;
985 uint32_t val;
986
987 val = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5;
988 return val & 1 ? 1 : 0;
989}
990
991static void set_clock(void *i2c_priv, int clock)
992{
993 struct ast_i2c_chan *i2c = i2c_priv;
994 struct ast_private *ast = i2c->dev->dev_private;
995 int i;
996 u8 ujcrb7, jtemp;
997
998 for (i = 0; i < 0x10000; i++) {
999 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1000 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfe, ujcrb7);
1001 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1002 if (ujcrb7 == jtemp)
1003 break;
1004 }
1005}
1006
1007static void set_data(void *i2c_priv, int data)
1008{
1009 struct ast_i2c_chan *i2c = i2c_priv;
1010 struct ast_private *ast = i2c->dev->dev_private;
1011 int i;
1012 u8 ujcrb7, jtemp;
1013
1014 for (i = 0; i < 0x10000; i++) {
1015 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1016 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xfb, ujcrb7);
1017 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1018 if (ujcrb7 == jtemp)
1019 break;
1020 }
1021}
1022
1023static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1024{
1025 struct ast_i2c_chan *i2c;
1026 int ret;
1027
1028 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1029 if (!i2c)
1030 return NULL;
1031
1032 i2c->adapter.owner = THIS_MODULE;
1033 i2c->adapter.class = I2C_CLASS_DDC;
1034 i2c->adapter.dev.parent = &dev->pdev->dev;
1035 i2c->dev = dev;
1036 i2c_set_adapdata(&i2c->adapter, i2c);
1037 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1038 "AST i2c bit bus");
1039 i2c->adapter.algo_data = &i2c->bit;
1040
1041 i2c->bit.udelay = 20;
1042 i2c->bit.timeout = 2;
1043 i2c->bit.data = i2c;
1044 i2c->bit.setsda = set_data;
1045 i2c->bit.setscl = set_clock;
1046 i2c->bit.getsda = get_data;
1047 i2c->bit.getscl = get_clock;
1048 ret = i2c_bit_add_bus(&i2c->adapter);
1049 if (ret) {
1050 DRM_ERROR("Failed to register bit i2c\n");
1051 goto out_free;
1052 }
1053
1054 return i2c;
1055out_free:
1056 kfree(i2c);
1057 return NULL;
1058}
1059
1060static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1061{
1062 if (!i2c)
1063 return;
1064 i2c_del_adapter(&i2c->adapter);
1065 kfree(i2c);
1066}
1067
1068static void ast_show_cursor(struct drm_crtc *crtc)
1069{
1070 struct ast_private *ast = crtc->dev->dev_private;
1071 u8 jreg;
1072
1073 jreg = 0x2;
1074 /* enable ARGB cursor */
1075 jreg |= 1;
1076 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, jreg);
1077}
1078
1079static void ast_hide_cursor(struct drm_crtc *crtc)
1080{
1081 struct ast_private *ast = crtc->dev->dev_private;
1082 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, 0xfc, 0x00);
1083}
1084
1085static u32 copy_cursor_image(u8 *src, u8 *dst, int width, int height)
1086{
1087 union {
1088 u32 ul;
1089 u8 b[4];
1090 } srcdata32[2], data32;
1091 union {
1092 u16 us;
1093 u8 b[2];
1094 } data16;
1095 u32 csum = 0;
1096 s32 alpha_dst_delta, last_alpha_dst_delta;
1097 u8 *srcxor, *dstxor;
1098 int i, j;
1099 u32 per_pixel_copy, two_pixel_copy;
1100
1101 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
1102 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
1103
1104 srcxor = src;
1105 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
1106 per_pixel_copy = width & 1;
1107 two_pixel_copy = width >> 1;
1108
1109 for (j = 0; j < height; j++) {
1110 for (i = 0; i < two_pixel_copy; i++) {
1111 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1112 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
1113 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1114 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1115 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
1116 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
1117
1118 writel(data32.ul, dstxor);
1119 csum += data32.ul;
1120
1121 dstxor += 4;
1122 srcxor += 8;
1123
1124 }
1125
1126 for (i = 0; i < per_pixel_copy; i++) {
1127 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
1128 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
1129 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
1130 writew(data16.us, dstxor);
1131 csum += (u32)data16.us;
1132
1133 dstxor += 2;
1134 srcxor += 4;
1135 }
1136 dstxor += last_alpha_dst_delta;
1137 }
1138 return csum;
1139}
1140
1141static int ast_cursor_set(struct drm_crtc *crtc,
1142 struct drm_file *file_priv,
1143 uint32_t handle,
1144 uint32_t width,
1145 uint32_t height)
1146{
1147 struct ast_private *ast = crtc->dev->dev_private;
1148 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1149 struct drm_gem_object *obj;
1150 struct ast_bo *bo;
1151 uint64_t gpu_addr;
1152 u32 csum;
1153 int ret;
1154 struct ttm_bo_kmap_obj uobj_map;
1155 u8 *src, *dst;
1156 bool src_isiomem, dst_isiomem;
1157 if (!handle) {
1158 ast_hide_cursor(crtc);
1159 return 0;
1160 }
1161
1162 if (width > AST_MAX_HWC_WIDTH || height > AST_MAX_HWC_HEIGHT)
1163 return -EINVAL;
1164
1165 obj = drm_gem_object_lookup(file_priv, handle);
1166 if (!obj) {
1167 DRM_ERROR("Cannot find cursor object %x for crtc\n", handle);
1168 return -ENOENT;
1169 }
1170 bo = gem_to_ast_bo(obj);
1171
1172 ret = ast_bo_reserve(bo, false);
1173 if (ret)
1174 goto fail;
1175
1176 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &uobj_map);
1177
1178 src = ttm_kmap_obj_virtual(&uobj_map, &src_isiomem);
1179 dst = ttm_kmap_obj_virtual(&ast->cache_kmap, &dst_isiomem);
1180
1181 if (src_isiomem == true)
1182 DRM_ERROR("src cursor bo should be in main memory\n");
1183 if (dst_isiomem == false)
1184 DRM_ERROR("dst bo should be in VRAM\n");
1185
1186 dst += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1187
1188 /* do data transfer to cursor cache */
1189 csum = copy_cursor_image(src, dst, width, height);
1190
1191 /* write checksum + signature */
1192 ttm_bo_kunmap(&uobj_map);
1193 ast_bo_unreserve(bo);
1194 {
1195 u8 *dst = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1196 writel(csum, dst);
1197 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
1198 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
1199 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
1200 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
1201
1202 /* set pattern offset */
1203 gpu_addr = ast->cursor_cache_gpu_addr;
1204 gpu_addr += (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor;
1205 gpu_addr >>= 3;
1206 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, gpu_addr & 0xff);
1207 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, (gpu_addr >> 8) & 0xff);
1208 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, (gpu_addr >> 16) & 0xff);
1209 }
1210 ast_crtc->cursor_width = width;
1211 ast_crtc->cursor_height = height;
1212 ast_crtc->offset_x = AST_MAX_HWC_WIDTH - width;
1213 ast_crtc->offset_y = AST_MAX_HWC_WIDTH - height;
1214
1215 ast->next_cursor = (ast->next_cursor + 1) % AST_DEFAULT_HWC_NUM;
1216
1217 ast_show_cursor(crtc);
1218
1219 drm_gem_object_put_unlocked(obj);
1220 return 0;
1221fail:
1222 drm_gem_object_put_unlocked(obj);
1223 return ret;
1224}
1225
1226static int ast_cursor_move(struct drm_crtc *crtc,
1227 int x, int y)
1228{
1229 struct ast_crtc *ast_crtc = to_ast_crtc(crtc);
1230 struct ast_private *ast = crtc->dev->dev_private;
1231 int x_offset, y_offset;
1232 u8 *sig;
1233
1234 sig = (u8 *)ast->cache_kmap.virtual + (AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE)*ast->next_cursor + AST_HWC_SIZE;
1235 writel(x, sig + AST_HWC_SIGNATURE_X);
1236 writel(y, sig + AST_HWC_SIGNATURE_Y);
1237
1238 x_offset = ast_crtc->offset_x;
1239 y_offset = ast_crtc->offset_y;
1240 if (x < 0) {
1241 x_offset = (-x) + ast_crtc->offset_x;
1242 x = 0;
1243 }
1244
1245 if (y < 0) {
1246 y_offset = (-y) + ast_crtc->offset_y;
1247 y = 0;
1248 }
1249 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
1250 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
1251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, (x & 0xff));
1252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, ((x >> 8) & 0x0f));
1253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, (y & 0xff));
1254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, ((y >> 8) & 0x07));
1255
1256 /* dummy write to fire HWC */
1257 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xCB, 0xFF, 0x00);
1258
1259 return 0;
1260}