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1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_0.h"
26
27#include "nbio/nbio_7_0_default.h"
28#include "nbio/nbio_7_0_offset.h"
29#include "nbio/nbio_7_0_sh_mask.h"
30#include "nbio/nbio_7_0_smn.h"
31#include "vega10_enum.h"
32#include <uapi/linux/kfd_ioctl.h>
33
34#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
35
36static void nbio_v7_0_remap_hdp_registers(struct amdgpu_device *adev)
37{
38 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
39 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
40 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
41 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
42}
43
44static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
45{
46 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
47
48 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
49 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
50
51 return tmp;
52}
53
54static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
55{
56 if (enable)
57 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
58 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
59 else
60 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
61}
62
63static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
64{
65 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
66}
67
68static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
69 bool use_doorbell, int doorbell_index, int doorbell_size)
70{
71 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
72 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
73
74 u32 doorbell_range = RREG32(reg);
75
76 if (use_doorbell) {
77 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
78 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
79 } else
80 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
81
82 WREG32(reg, doorbell_range);
83}
84
85static void nbio_v7_0_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
86 int doorbell_index, int instance)
87{
88 u32 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
89
90 u32 doorbell_range = RREG32(reg);
91
92 if (use_doorbell) {
93 doorbell_range = REG_SET_FIELD(doorbell_range,
94 BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
95 doorbell_index);
96 doorbell_range = REG_SET_FIELD(doorbell_range,
97 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
98 } else
99 doorbell_range = REG_SET_FIELD(doorbell_range,
100 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
101
102 WREG32(reg, doorbell_range);
103}
104
105static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
106 bool enable)
107{
108 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
109}
110
111static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
112 bool enable)
113{
114
115}
116
117static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
118 bool use_doorbell, int doorbell_index)
119{
120 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE);
121
122 if (use_doorbell) {
123 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
124 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
125 } else
126 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
127
128 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
129}
130
131static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
132{
133 uint32_t data;
134
135 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
136 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
137
138 return data;
139}
140
141static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
142 uint32_t data)
143{
144 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
145 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
146}
147
148static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
149 bool enable)
150{
151 uint32_t def, data;
152
153 /* NBIF_MGCG_CTRL_LCLK */
154 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
155
156 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
157 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
158 else
159 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
160
161 if (def != data)
162 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
163
164 /* SYSHUB_MGCG_CTRL_SOCCLK */
165 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
166
167 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
168 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
169 else
170 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
171
172 if (def != data)
173 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
174
175 /* SYSHUB_MGCG_CTRL_SHUBCLK */
176 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
177
178 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
179 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
180 else
181 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
182
183 if (def != data)
184 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
185}
186
187static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
188 bool enable)
189{
190 uint32_t def, data;
191
192 def = data = RREG32_PCIE(smnPCIE_CNTL2);
193 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
194 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
195 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
196 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
197 } else {
198 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
199 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
200 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
201 }
202
203 if (def != data)
204 WREG32_PCIE(smnPCIE_CNTL2, data);
205}
206
207static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
208 u64 *flags)
209{
210 int data;
211
212 /* AMD_CG_SUPPORT_BIF_MGCG */
213 data = RREG32_PCIE(smnCPM_CONTROL);
214 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
215 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
216
217 /* AMD_CG_SUPPORT_BIF_LS */
218 data = RREG32_PCIE(smnPCIE_CNTL2);
219 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
220 *flags |= AMD_CG_SUPPORT_BIF_LS;
221}
222
223static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
224{
225 u32 interrupt_cntl;
226
227 /* setup interrupt control */
228 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
229 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
230 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
231 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
232 */
233 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
234 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
235 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
236 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
237}
238
239static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
240{
241 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
242}
243
244static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
245{
246 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
247}
248
249static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
250{
251 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
252}
253
254static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
255{
256 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
257}
258
259const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
260 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
261 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
262 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
263 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
264 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
265 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
266 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
267 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
268 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
269 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
270 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
271 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
272};
273
274#define regRCC_DEV0_EPF6_STRAP4 0xd304
275#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX 5
276
277static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
278{
279 uint32_t data;
280
281 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) {
282 case IP_VERSION(2, 5, 0):
283 data = RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4) & ~BIT(23);
284 WREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF6_STRAP4, data);
285 break;
286 }
287}
288
289#define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
290
291static void nbio_v7_0_set_reg_remap(struct amdgpu_device *adev)
292{
293 if (!amdgpu_sriov_vf(adev) && (PAGE_SIZE <= 4096)) {
294 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
295 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
296 } else {
297 adev->rmmio_remap.reg_offset =
298 SOC15_REG_OFFSET(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
299 adev->rmmio_remap.bus_addr = 0;
300 }
301}
302
303const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
304 .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
305 .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
306 .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
307 .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
308 .get_rev_id = nbio_v7_0_get_rev_id,
309 .mc_access_enable = nbio_v7_0_mc_access_enable,
310 .get_memsize = nbio_v7_0_get_memsize,
311 .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
312 .vcn_doorbell_range = nbio_v7_0_vcn_doorbell_range,
313 .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
314 .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
315 .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
316 .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
317 .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
318 .get_clockgating_state = nbio_v7_0_get_clockgating_state,
319 .ih_control = nbio_v7_0_ih_control,
320 .init_registers = nbio_v7_0_init_registers,
321 .remap_hdp_registers = nbio_v7_0_remap_hdp_registers,
322 .set_reg_remap = nbio_v7_0_set_reg_remap,
323};
1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_0.h"
26
27#include "nbio/nbio_7_0_default.h"
28#include "nbio/nbio_7_0_offset.h"
29#include "nbio/nbio_7_0_sh_mask.h"
30#include "vega10_enum.h"
31
32#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
33
34#define smnCPM_CONTROL 0x11180460
35#define smnPCIE_CNTL2 0x11180070
36
37static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
38{
39 u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
40
41 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
42 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
43
44 return tmp;
45}
46
47static void nbio_v7_0_mc_access_enable(struct amdgpu_device *adev, bool enable)
48{
49 if (enable)
50 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
51 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
52 else
53 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
54}
55
56static void nbio_v7_0_hdp_flush(struct amdgpu_device *adev,
57 struct amdgpu_ring *ring)
58{
59 if (!ring || !ring->funcs->emit_wreg)
60 WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL, 0);
61 else
62 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
63 NBIO, 0, mmHDP_MEM_COHERENCY_FLUSH_CNTL), 0);
64}
65
66static u32 nbio_v7_0_get_memsize(struct amdgpu_device *adev)
67{
68 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
69}
70
71static void nbio_v7_0_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
72 bool use_doorbell, int doorbell_index)
73{
74 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
75 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA1_DOORBELL_RANGE);
76
77 u32 doorbell_range = RREG32(reg);
78
79 if (use_doorbell) {
80 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
81 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 2);
82 } else
83 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
84
85 WREG32(reg, doorbell_range);
86}
87
88static void nbio_v7_0_enable_doorbell_aperture(struct amdgpu_device *adev,
89 bool enable)
90{
91 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
92}
93
94static void nbio_v7_0_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
95 bool enable)
96{
97
98}
99
100static void nbio_v7_0_ih_doorbell_range(struct amdgpu_device *adev,
101 bool use_doorbell, int doorbell_index)
102{
103 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
104
105 if (use_doorbell) {
106 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
107 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 2);
108 } else
109 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
110
111 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
112}
113
114static uint32_t nbio_7_0_read_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset)
115{
116 uint32_t data;
117
118 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
119 data = RREG32_SOC15(NBIO, 0, mmSYSHUB_DATA);
120
121 return data;
122}
123
124static void nbio_7_0_write_syshub_ind_mmr(struct amdgpu_device *adev, uint32_t offset,
125 uint32_t data)
126{
127 WREG32_SOC15(NBIO, 0, mmSYSHUB_INDEX, offset);
128 WREG32_SOC15(NBIO, 0, mmSYSHUB_DATA, data);
129}
130
131static void nbio_v7_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
132 bool enable)
133{
134 uint32_t def, data;
135
136 /* NBIF_MGCG_CTRL_LCLK */
137 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
138
139 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
140 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
141 else
142 data &= ~NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK;
143
144 if (def != data)
145 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
146
147 /* SYSHUB_MGCG_CTRL_SOCCLK */
148 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK);
149
150 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
151 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
152 else
153 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK;
154
155 if (def != data)
156 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SOCCLK, data);
157
158 /* SYSHUB_MGCG_CTRL_SHUBCLK */
159 def = data = nbio_7_0_read_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK);
160
161 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG))
162 data |= SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
163 else
164 data &= ~SYSHUB_MMREG_DIRECT_SYSHUB_MGCG_CTRL_SHUBCLK__SYSHUB_MGCG_EN_SHUBCLK_MASK;
165
166 if (def != data)
167 nbio_7_0_write_syshub_ind_mmr(adev, ixSYSHUB_MMREG_IND_SYSHUB_MGCG_CTRL_SHUBCLK, data);
168}
169
170static void nbio_v7_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
171 bool enable)
172{
173 uint32_t def, data;
174
175 def = data = RREG32_PCIE(smnPCIE_CNTL2);
176 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
177 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
178 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
179 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
180 } else {
181 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
182 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
183 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
184 }
185
186 if (def != data)
187 WREG32_PCIE(smnPCIE_CNTL2, data);
188}
189
190static void nbio_v7_0_get_clockgating_state(struct amdgpu_device *adev,
191 u32 *flags)
192{
193 int data;
194
195 /* AMD_CG_SUPPORT_BIF_MGCG */
196 data = RREG32_PCIE(smnCPM_CONTROL);
197 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
198 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
199
200 /* AMD_CG_SUPPORT_BIF_LS */
201 data = RREG32_PCIE(smnPCIE_CNTL2);
202 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
203 *flags |= AMD_CG_SUPPORT_BIF_LS;
204}
205
206static void nbio_v7_0_ih_control(struct amdgpu_device *adev)
207{
208 u32 interrupt_cntl;
209
210 /* setup interrupt control */
211 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
212 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
213 /* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
214 * INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
215 */
216 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
217 /* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
218 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
219 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
220}
221
222static u32 nbio_v7_0_get_hdp_flush_req_offset(struct amdgpu_device *adev)
223{
224 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
225}
226
227static u32 nbio_v7_0_get_hdp_flush_done_offset(struct amdgpu_device *adev)
228{
229 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
230}
231
232static u32 nbio_v7_0_get_pcie_index_offset(struct amdgpu_device *adev)
233{
234 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
235}
236
237static u32 nbio_v7_0_get_pcie_data_offset(struct amdgpu_device *adev)
238{
239 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
240}
241
242const struct nbio_hdp_flush_reg nbio_v7_0_hdp_flush_reg = {
243 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
244 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
245 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
246 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
247 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
248 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
249 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
250 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
251 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
252 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
253 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
254 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
255};
256
257static void nbio_v7_0_detect_hw_virt(struct amdgpu_device *adev)
258{
259 if (is_virtual_machine()) /* passthrough mode exclus sriov mod */
260 adev->virt.caps |= AMDGPU_PASSTHROUGH_MODE;
261}
262
263static void nbio_v7_0_init_registers(struct amdgpu_device *adev)
264{
265
266}
267
268const struct amdgpu_nbio_funcs nbio_v7_0_funcs = {
269 .hdp_flush_reg = &nbio_v7_0_hdp_flush_reg,
270 .get_hdp_flush_req_offset = nbio_v7_0_get_hdp_flush_req_offset,
271 .get_hdp_flush_done_offset = nbio_v7_0_get_hdp_flush_done_offset,
272 .get_pcie_index_offset = nbio_v7_0_get_pcie_index_offset,
273 .get_pcie_data_offset = nbio_v7_0_get_pcie_data_offset,
274 .get_rev_id = nbio_v7_0_get_rev_id,
275 .mc_access_enable = nbio_v7_0_mc_access_enable,
276 .hdp_flush = nbio_v7_0_hdp_flush,
277 .get_memsize = nbio_v7_0_get_memsize,
278 .sdma_doorbell_range = nbio_v7_0_sdma_doorbell_range,
279 .enable_doorbell_aperture = nbio_v7_0_enable_doorbell_aperture,
280 .enable_doorbell_selfring_aperture = nbio_v7_0_enable_doorbell_selfring_aperture,
281 .ih_doorbell_range = nbio_v7_0_ih_doorbell_range,
282 .update_medium_grain_clock_gating = nbio_v7_0_update_medium_grain_clock_gating,
283 .update_medium_grain_light_sleep = nbio_v7_0_update_medium_grain_light_sleep,
284 .get_clockgating_state = nbio_v7_0_get_clockgating_state,
285 .ih_control = nbio_v7_0_ih_control,
286 .init_registers = nbio_v7_0_init_registers,
287 .detect_hw_virt = nbio_v7_0_detect_hw_virt,
288};