Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * linux/drivers/gpio/gpio-mb86s7x.c
4 *
5 * Copyright (C) 2015 Fujitsu Semiconductor Limited
6 * Copyright (C) 2015 Linaro Ltd.
7 */
8
9#include <linux/acpi.h>
10#include <linux/io.h>
11#include <linux/init.h>
12#include <linux/clk.h>
13#include <linux/mod_devicetable.h>
14#include <linux/module.h>
15#include <linux/err.h>
16#include <linux/errno.h>
17#include <linux/ioport.h>
18#include <linux/gpio/driver.h>
19#include <linux/platform_device.h>
20#include <linux/spinlock.h>
21#include <linux/slab.h>
22
23#include "gpiolib-acpi.h"
24
25/*
26 * Only first 8bits of a register correspond to each pin,
27 * so there are 4 registers for 32 pins.
28 */
29#define PDR(x) (0x0 + x / 8 * 4)
30#define DDR(x) (0x10 + x / 8 * 4)
31#define PFR(x) (0x20 + x / 8 * 4)
32
33#define OFFSET(x) BIT((x) % 8)
34
35struct mb86s70_gpio_chip {
36 struct gpio_chip gc;
37 void __iomem *base;
38 spinlock_t lock;
39};
40
41static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
42{
43 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
44 unsigned long flags;
45 u32 val;
46
47 spin_lock_irqsave(&gchip->lock, flags);
48
49 val = readl(gchip->base + PFR(gpio));
50 val &= ~OFFSET(gpio);
51 writel(val, gchip->base + PFR(gpio));
52
53 spin_unlock_irqrestore(&gchip->lock, flags);
54
55 return 0;
56}
57
58static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
59{
60 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
61 unsigned long flags;
62 u32 val;
63
64 spin_lock_irqsave(&gchip->lock, flags);
65
66 val = readl(gchip->base + PFR(gpio));
67 val |= OFFSET(gpio);
68 writel(val, gchip->base + PFR(gpio));
69
70 spin_unlock_irqrestore(&gchip->lock, flags);
71}
72
73static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
74{
75 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
76 unsigned long flags;
77 unsigned char val;
78
79 spin_lock_irqsave(&gchip->lock, flags);
80
81 val = readl(gchip->base + DDR(gpio));
82 val &= ~OFFSET(gpio);
83 writel(val, gchip->base + DDR(gpio));
84
85 spin_unlock_irqrestore(&gchip->lock, flags);
86
87 return 0;
88}
89
90static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
91 unsigned gpio, int value)
92{
93 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
94 unsigned long flags;
95 unsigned char val;
96
97 spin_lock_irqsave(&gchip->lock, flags);
98
99 val = readl(gchip->base + PDR(gpio));
100 if (value)
101 val |= OFFSET(gpio);
102 else
103 val &= ~OFFSET(gpio);
104 writel(val, gchip->base + PDR(gpio));
105
106 val = readl(gchip->base + DDR(gpio));
107 val |= OFFSET(gpio);
108 writel(val, gchip->base + DDR(gpio));
109
110 spin_unlock_irqrestore(&gchip->lock, flags);
111
112 return 0;
113}
114
115static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
116{
117 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
118
119 return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
120}
121
122static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
123{
124 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
125 unsigned long flags;
126 unsigned char val;
127
128 spin_lock_irqsave(&gchip->lock, flags);
129
130 val = readl(gchip->base + PDR(gpio));
131 if (value)
132 val |= OFFSET(gpio);
133 else
134 val &= ~OFFSET(gpio);
135 writel(val, gchip->base + PDR(gpio));
136
137 spin_unlock_irqrestore(&gchip->lock, flags);
138}
139
140static int mb86s70_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
141{
142 int irq, index;
143
144 for (index = 0;; index++) {
145 irq = platform_get_irq(to_platform_device(gc->parent), index);
146 if (irq < 0)
147 return irq;
148 if (irq_get_irq_data(irq)->hwirq == offset)
149 return irq;
150 }
151 return -EINVAL;
152}
153
154static int mb86s70_gpio_probe(struct platform_device *pdev)
155{
156 struct mb86s70_gpio_chip *gchip;
157 struct clk *clk;
158 int ret;
159
160 gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
161 if (gchip == NULL)
162 return -ENOMEM;
163
164 platform_set_drvdata(pdev, gchip);
165
166 gchip->base = devm_platform_ioremap_resource(pdev, 0);
167 if (IS_ERR(gchip->base))
168 return PTR_ERR(gchip->base);
169
170 clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
171 if (IS_ERR(clk))
172 return PTR_ERR(clk);
173
174 spin_lock_init(&gchip->lock);
175
176 gchip->gc.direction_output = mb86s70_gpio_direction_output;
177 gchip->gc.direction_input = mb86s70_gpio_direction_input;
178 gchip->gc.request = mb86s70_gpio_request;
179 gchip->gc.free = mb86s70_gpio_free;
180 gchip->gc.get = mb86s70_gpio_get;
181 gchip->gc.set = mb86s70_gpio_set;
182 gchip->gc.to_irq = mb86s70_gpio_to_irq;
183 gchip->gc.label = dev_name(&pdev->dev);
184 gchip->gc.ngpio = 32;
185 gchip->gc.owner = THIS_MODULE;
186 gchip->gc.parent = &pdev->dev;
187 gchip->gc.base = -1;
188
189 ret = gpiochip_add_data(&gchip->gc, gchip);
190 if (ret)
191 return dev_err_probe(&pdev->dev, ret,
192 "couldn't register gpio driver\n");
193
194 acpi_gpiochip_request_interrupts(&gchip->gc);
195
196 return 0;
197}
198
199static void mb86s70_gpio_remove(struct platform_device *pdev)
200{
201 struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);
202
203 acpi_gpiochip_free_interrupts(&gchip->gc);
204 gpiochip_remove(&gchip->gc);
205}
206
207static const struct of_device_id mb86s70_gpio_dt_ids[] = {
208 { .compatible = "fujitsu,mb86s70-gpio" },
209 { /* sentinel */ }
210};
211MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);
212
213#ifdef CONFIG_ACPI
214static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = {
215 { "SCX0007" },
216 { /* sentinel */ }
217};
218MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids);
219#endif
220
221static struct platform_driver mb86s70_gpio_driver = {
222 .driver = {
223 .name = "mb86s70-gpio",
224 .of_match_table = mb86s70_gpio_dt_ids,
225 .acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids),
226 },
227 .probe = mb86s70_gpio_probe,
228 .remove = mb86s70_gpio_remove,
229};
230module_platform_driver(mb86s70_gpio_driver);
231
232MODULE_DESCRIPTION("MB86S7x GPIO Driver");
233MODULE_ALIAS("platform:mb86s70-gpio");
234MODULE_LICENSE("GPL");
1/*
2 * linux/drivers/gpio/gpio-mb86s7x.c
3 *
4 * Copyright (C) 2015 Fujitsu Semiconductor Limited
5 * Copyright (C) 2015 Linaro Ltd.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation, version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/io.h>
18#include <linux/init.h>
19#include <linux/clk.h>
20#include <linux/module.h>
21#include <linux/err.h>
22#include <linux/errno.h>
23#include <linux/ioport.h>
24#include <linux/of_device.h>
25#include <linux/gpio/driver.h>
26#include <linux/platform_device.h>
27#include <linux/spinlock.h>
28#include <linux/slab.h>
29
30/*
31 * Only first 8bits of a register correspond to each pin,
32 * so there are 4 registers for 32 pins.
33 */
34#define PDR(x) (0x0 + x / 8 * 4)
35#define DDR(x) (0x10 + x / 8 * 4)
36#define PFR(x) (0x20 + x / 8 * 4)
37
38#define OFFSET(x) BIT((x) % 8)
39
40struct mb86s70_gpio_chip {
41 struct gpio_chip gc;
42 void __iomem *base;
43 struct clk *clk;
44 spinlock_t lock;
45};
46
47static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio)
48{
49 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
50 unsigned long flags;
51 u32 val;
52
53 spin_lock_irqsave(&gchip->lock, flags);
54
55 val = readl(gchip->base + PFR(gpio));
56 val &= ~OFFSET(gpio);
57 writel(val, gchip->base + PFR(gpio));
58
59 spin_unlock_irqrestore(&gchip->lock, flags);
60
61 return 0;
62}
63
64static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio)
65{
66 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
67 unsigned long flags;
68 u32 val;
69
70 spin_lock_irqsave(&gchip->lock, flags);
71
72 val = readl(gchip->base + PFR(gpio));
73 val |= OFFSET(gpio);
74 writel(val, gchip->base + PFR(gpio));
75
76 spin_unlock_irqrestore(&gchip->lock, flags);
77}
78
79static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
80{
81 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
82 unsigned long flags;
83 unsigned char val;
84
85 spin_lock_irqsave(&gchip->lock, flags);
86
87 val = readl(gchip->base + DDR(gpio));
88 val &= ~OFFSET(gpio);
89 writel(val, gchip->base + DDR(gpio));
90
91 spin_unlock_irqrestore(&gchip->lock, flags);
92
93 return 0;
94}
95
96static int mb86s70_gpio_direction_output(struct gpio_chip *gc,
97 unsigned gpio, int value)
98{
99 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
100 unsigned long flags;
101 unsigned char val;
102
103 spin_lock_irqsave(&gchip->lock, flags);
104
105 val = readl(gchip->base + PDR(gpio));
106 if (value)
107 val |= OFFSET(gpio);
108 else
109 val &= ~OFFSET(gpio);
110 writel(val, gchip->base + PDR(gpio));
111
112 val = readl(gchip->base + DDR(gpio));
113 val |= OFFSET(gpio);
114 writel(val, gchip->base + DDR(gpio));
115
116 spin_unlock_irqrestore(&gchip->lock, flags);
117
118 return 0;
119}
120
121static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio)
122{
123 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
124
125 return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio));
126}
127
128static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value)
129{
130 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc);
131 unsigned long flags;
132 unsigned char val;
133
134 spin_lock_irqsave(&gchip->lock, flags);
135
136 val = readl(gchip->base + PDR(gpio));
137 if (value)
138 val |= OFFSET(gpio);
139 else
140 val &= ~OFFSET(gpio);
141 writel(val, gchip->base + PDR(gpio));
142
143 spin_unlock_irqrestore(&gchip->lock, flags);
144}
145
146static int mb86s70_gpio_probe(struct platform_device *pdev)
147{
148 struct mb86s70_gpio_chip *gchip;
149 struct resource *res;
150 int ret;
151
152 gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL);
153 if (gchip == NULL)
154 return -ENOMEM;
155
156 platform_set_drvdata(pdev, gchip);
157
158 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
159 gchip->base = devm_ioremap_resource(&pdev->dev, res);
160 if (IS_ERR(gchip->base))
161 return PTR_ERR(gchip->base);
162
163 gchip->clk = devm_clk_get(&pdev->dev, NULL);
164 if (IS_ERR(gchip->clk))
165 return PTR_ERR(gchip->clk);
166
167 ret = clk_prepare_enable(gchip->clk);
168 if (ret)
169 return ret;
170
171 spin_lock_init(&gchip->lock);
172
173 gchip->gc.direction_output = mb86s70_gpio_direction_output;
174 gchip->gc.direction_input = mb86s70_gpio_direction_input;
175 gchip->gc.request = mb86s70_gpio_request;
176 gchip->gc.free = mb86s70_gpio_free;
177 gchip->gc.get = mb86s70_gpio_get;
178 gchip->gc.set = mb86s70_gpio_set;
179 gchip->gc.label = dev_name(&pdev->dev);
180 gchip->gc.ngpio = 32;
181 gchip->gc.owner = THIS_MODULE;
182 gchip->gc.parent = &pdev->dev;
183 gchip->gc.base = -1;
184
185 ret = gpiochip_add_data(&gchip->gc, gchip);
186 if (ret) {
187 dev_err(&pdev->dev, "couldn't register gpio driver\n");
188 clk_disable_unprepare(gchip->clk);
189 }
190
191 return ret;
192}
193
194static int mb86s70_gpio_remove(struct platform_device *pdev)
195{
196 struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev);
197
198 gpiochip_remove(&gchip->gc);
199 clk_disable_unprepare(gchip->clk);
200
201 return 0;
202}
203
204static const struct of_device_id mb86s70_gpio_dt_ids[] = {
205 { .compatible = "fujitsu,mb86s70-gpio" },
206 { /* sentinel */ }
207};
208MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids);
209
210static struct platform_driver mb86s70_gpio_driver = {
211 .driver = {
212 .name = "mb86s70-gpio",
213 .of_match_table = mb86s70_gpio_dt_ids,
214 },
215 .probe = mb86s70_gpio_probe,
216 .remove = mb86s70_gpio_remove,
217};
218module_platform_driver(mb86s70_gpio_driver);
219
220MODULE_DESCRIPTION("MB86S7x GPIO Driver");
221MODULE_ALIAS("platform:mb86s70-gpio");
222MODULE_LICENSE("GPL");