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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2013 Freescale Semiconductor, Inc.
4 * Copyright 2021 NXP
5 *
6 * clock driver for Freescale QorIQ SoCs.
7 */
8
9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12#include <linux/cleanup.h>
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/clkdev.h>
16#include <linux/fsl/guts.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of_address.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/slab.h>
24
25#define PLL_DIV1 0
26#define PLL_DIV2 1
27#define PLL_DIV3 2
28#define PLL_DIV4 3
29
30#define PLATFORM_PLL 0
31#define CGA_PLL1 1
32#define CGA_PLL2 2
33#define CGA_PLL3 3
34#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
35#define CGB_PLL1 4
36#define CGB_PLL2 5
37#define MAX_PLL_DIV 32
38
39struct clockgen_pll_div {
40 struct clk *clk;
41 char name[32];
42};
43
44struct clockgen_pll {
45 struct clockgen_pll_div div[MAX_PLL_DIV];
46};
47
48#define CLKSEL_VALID 1
49#define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
50
51struct clockgen_sourceinfo {
52 u32 flags; /* CLKSEL_xxx */
53 int pll; /* CGx_PLLn */
54 int div; /* PLL_DIVn */
55};
56
57#define NUM_MUX_PARENTS 16
58
59struct clockgen_muxinfo {
60 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
61};
62
63#define NUM_HWACCEL 5
64#define NUM_CMUX 8
65
66struct clockgen;
67
68/*
69 * cmux freq must be >= platform pll.
70 * If not set, cmux freq must be >= platform pll/2
71 */
72#define CG_CMUX_GE_PLAT 1
73
74#define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
75#define CG_VER3 4 /* version 3 cg: reg layout different */
76#define CG_LITTLE_ENDIAN 8
77
78struct clockgen_chipinfo {
79 const char *compat, *guts_compat;
80 const struct clockgen_muxinfo *cmux_groups[2];
81 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
82 void (*init_periph)(struct clockgen *cg);
83 int cmux_to_group[NUM_CMUX + 1]; /* array should be -1 terminated */
84 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
85 u32 flags; /* CG_xxx */
86};
87
88struct clockgen {
89 struct device_node *node;
90 void __iomem *regs;
91 struct clockgen_chipinfo info; /* mutable copy */
92 struct clk *sysclk, *coreclk;
93 struct clockgen_pll pll[6];
94 struct clk *cmux[NUM_CMUX];
95 struct clk *hwaccel[NUM_HWACCEL];
96 struct clk *fman[2];
97 struct ccsr_guts __iomem *guts;
98};
99
100static struct clockgen clockgen;
101static bool add_cpufreq_dev __initdata;
102
103static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
104{
105 if (cg->info.flags & CG_LITTLE_ENDIAN)
106 iowrite32(val, reg);
107 else
108 iowrite32be(val, reg);
109}
110
111static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
112{
113 u32 val;
114
115 if (cg->info.flags & CG_LITTLE_ENDIAN)
116 val = ioread32(reg);
117 else
118 val = ioread32be(reg);
119
120 return val;
121}
122
123static const struct clockgen_muxinfo p2041_cmux_grp1 = {
124 {
125 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
126 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
127 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
128 }
129};
130
131static const struct clockgen_muxinfo p2041_cmux_grp2 = {
132 {
133 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
134 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
135 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
136 }
137};
138
139static const struct clockgen_muxinfo p5020_cmux_grp1 = {
140 {
141 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
142 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
143 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
144 }
145};
146
147static const struct clockgen_muxinfo p5020_cmux_grp2 = {
148 {
149 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
150 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
151 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
152 }
153};
154
155static const struct clockgen_muxinfo p5040_cmux_grp1 = {
156 {
157 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
158 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
159 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
160 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
161 }
162};
163
164static const struct clockgen_muxinfo p5040_cmux_grp2 = {
165 {
166 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
167 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
168 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
169 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
170 }
171};
172
173static const struct clockgen_muxinfo p4080_cmux_grp1 = {
174 {
175 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
176 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
177 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
178 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
179 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
180 }
181};
182
183static const struct clockgen_muxinfo p4080_cmux_grp2 = {
184 {
185 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
186 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
187 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
188 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
189 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
190 }
191};
192
193static const struct clockgen_muxinfo t1023_cmux = {
194 {
195 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
196 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
197 }
198};
199
200static const struct clockgen_muxinfo t1040_cmux = {
201 {
202 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
203 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
204 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
205 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
206 }
207};
208
209
210static const struct clockgen_muxinfo clockgen2_cmux_cga = {
211 {
212 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
213 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
214 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
215 {},
216 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
217 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
218 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
219 {},
220 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
221 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
222 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
223 },
224};
225
226static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
227 {
228 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
229 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
230 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
231 {},
232 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
233 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
234 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
235 },
236};
237
238static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
239 {
240 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
241 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
242 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
243 {},
244 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
245 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
246 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
247 },
248};
249
250static const struct clockgen_muxinfo ls1021a_cmux = {
251 {
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
253 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
254 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
255 }
256};
257
258static const struct clockgen_muxinfo ls1028a_hwa1 = {
259 {
260 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
262 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
263 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
264 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
265 {},
266 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
267 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
268 },
269};
270
271static const struct clockgen_muxinfo ls1028a_hwa2 = {
272 {
273 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
274 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
275 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
276 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
277 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
278 {},
279 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
280 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
281 },
282};
283
284static const struct clockgen_muxinfo ls1028a_hwa3 = {
285 {
286 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
288 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
289 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
290 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
291 {},
292 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
293 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
294 },
295};
296
297static const struct clockgen_muxinfo ls1028a_hwa4 = {
298 {
299 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
300 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
301 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
302 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
303 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
304 {},
305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
306 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
307 },
308};
309
310static const struct clockgen_muxinfo ls1043a_hwa1 = {
311 {
312 {},
313 {},
314 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
315 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
316 {},
317 {},
318 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
319 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
320 },
321};
322
323static const struct clockgen_muxinfo ls1043a_hwa2 = {
324 {
325 {},
326 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
327 {},
328 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
329 },
330};
331
332static const struct clockgen_muxinfo ls1046a_hwa1 = {
333 {
334 {},
335 {},
336 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
337 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
338 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
339 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
340 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
341 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
342 },
343};
344
345static const struct clockgen_muxinfo ls1046a_hwa2 = {
346 {
347 {},
348 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
349 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
350 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
351 {},
352 {},
353 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
354 },
355};
356
357static const struct clockgen_muxinfo ls1088a_hwa1 = {
358 {
359 {},
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
361 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
362 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
363 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
364 {},
365 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
366 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
367 },
368};
369
370static const struct clockgen_muxinfo ls1088a_hwa2 = {
371 {
372 {},
373 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
374 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
375 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
376 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
377 {},
378 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
379 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
380 },
381};
382
383static const struct clockgen_muxinfo ls1012a_cmux = {
384 {
385 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
386 {},
387 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
388 }
389};
390
391static const struct clockgen_muxinfo t1023_hwa1 = {
392 {
393 {},
394 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
395 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
396 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
397 },
398};
399
400static const struct clockgen_muxinfo t1023_hwa2 = {
401 {
402 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
403 },
404};
405
406static const struct clockgen_muxinfo t2080_hwa1 = {
407 {
408 {},
409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
410 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
411 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
412 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
413 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
414 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
415 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
416 },
417};
418
419static const struct clockgen_muxinfo t2080_hwa2 = {
420 {
421 {},
422 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
423 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
424 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
425 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
426 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
427 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
428 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
429 },
430};
431
432static const struct clockgen_muxinfo t4240_hwa1 = {
433 {
434 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
436 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
437 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
438 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
439 {},
440 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
441 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
442 },
443};
444
445static const struct clockgen_muxinfo t4240_hwa4 = {
446 {
447 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
448 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
449 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
450 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
451 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
452 },
453};
454
455static const struct clockgen_muxinfo t4240_hwa5 = {
456 {
457 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
458 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
459 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
460 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
461 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
462 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
463 },
464};
465
466#define RCWSR7_FM1_CLK_SEL 0x40000000
467#define RCWSR7_FM2_CLK_SEL 0x20000000
468#define RCWSR7_HWA_ASYNC_DIV 0x04000000
469
470static void __init p2041_init_periph(struct clockgen *cg)
471{
472 u32 reg;
473
474 reg = ioread32be(&cg->guts->rcwsr[7]);
475
476 if (reg & RCWSR7_FM1_CLK_SEL)
477 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
478 else
479 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
480}
481
482static void __init p4080_init_periph(struct clockgen *cg)
483{
484 u32 reg;
485
486 reg = ioread32be(&cg->guts->rcwsr[7]);
487
488 if (reg & RCWSR7_FM1_CLK_SEL)
489 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
490 else
491 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
492
493 if (reg & RCWSR7_FM2_CLK_SEL)
494 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
495 else
496 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
497}
498
499static void __init p5020_init_periph(struct clockgen *cg)
500{
501 u32 reg;
502 int div = PLL_DIV2;
503
504 reg = ioread32be(&cg->guts->rcwsr[7]);
505 if (reg & RCWSR7_HWA_ASYNC_DIV)
506 div = PLL_DIV4;
507
508 if (reg & RCWSR7_FM1_CLK_SEL)
509 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
510 else
511 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
512}
513
514static void __init p5040_init_periph(struct clockgen *cg)
515{
516 u32 reg;
517 int div = PLL_DIV2;
518
519 reg = ioread32be(&cg->guts->rcwsr[7]);
520 if (reg & RCWSR7_HWA_ASYNC_DIV)
521 div = PLL_DIV4;
522
523 if (reg & RCWSR7_FM1_CLK_SEL)
524 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
525 else
526 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
527
528 if (reg & RCWSR7_FM2_CLK_SEL)
529 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
530 else
531 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
532}
533
534static void __init t1023_init_periph(struct clockgen *cg)
535{
536 cg->fman[0] = cg->hwaccel[1];
537}
538
539static void __init t1040_init_periph(struct clockgen *cg)
540{
541 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
542}
543
544static void __init t2080_init_periph(struct clockgen *cg)
545{
546 cg->fman[0] = cg->hwaccel[0];
547}
548
549static void __init t4240_init_periph(struct clockgen *cg)
550{
551 cg->fman[0] = cg->hwaccel[3];
552 cg->fman[1] = cg->hwaccel[4];
553}
554
555static const struct clockgen_chipinfo chipinfo[] = {
556 {
557 .compat = "fsl,b4420-clockgen",
558 .guts_compat = "fsl,b4860-device-config",
559 .init_periph = t2080_init_periph,
560 .cmux_groups = {
561 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
562 },
563 .hwaccel = {
564 &t2080_hwa1
565 },
566 .cmux_to_group = {
567 0, 1, 1, 1, -1
568 },
569 .pll_mask = BIT(PLATFORM_PLL) |
570 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
571 BIT(CGB_PLL1) | BIT(CGB_PLL2),
572 .flags = CG_PLL_8BIT,
573 },
574 {
575 .compat = "fsl,b4860-clockgen",
576 .guts_compat = "fsl,b4860-device-config",
577 .init_periph = t2080_init_periph,
578 .cmux_groups = {
579 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
580 },
581 .hwaccel = {
582 &t2080_hwa1
583 },
584 .cmux_to_group = {
585 0, 1, 1, 1, -1
586 },
587 .pll_mask = BIT(PLATFORM_PLL) |
588 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
589 BIT(CGB_PLL1) | BIT(CGB_PLL2),
590 .flags = CG_PLL_8BIT,
591 },
592 {
593 .compat = "fsl,ls1021a-clockgen",
594 .cmux_groups = {
595 &ls1021a_cmux
596 },
597 .cmux_to_group = {
598 0, -1
599 },
600 .pll_mask = BIT(PLATFORM_PLL) |
601 BIT(CGA_PLL1) | BIT(CGA_PLL2),
602 },
603 {
604 .compat = "fsl,ls1028a-clockgen",
605 .cmux_groups = {
606 &clockgen2_cmux_cga12
607 },
608 .hwaccel = {
609 &ls1028a_hwa1, &ls1028a_hwa2,
610 &ls1028a_hwa3, &ls1028a_hwa4
611 },
612 .cmux_to_group = {
613 0, 0, 0, 0, -1
614 },
615 .pll_mask = BIT(PLATFORM_PLL) |
616 BIT(CGA_PLL1) | BIT(CGA_PLL2),
617 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
618 },
619 {
620 .compat = "fsl,ls1043a-clockgen",
621 .init_periph = t2080_init_periph,
622 .cmux_groups = {
623 &t1040_cmux
624 },
625 .hwaccel = {
626 &ls1043a_hwa1, &ls1043a_hwa2
627 },
628 .cmux_to_group = {
629 0, -1
630 },
631 .pll_mask = BIT(PLATFORM_PLL) |
632 BIT(CGA_PLL1) | BIT(CGA_PLL2),
633 .flags = CG_PLL_8BIT,
634 },
635 {
636 .compat = "fsl,ls1046a-clockgen",
637 .init_periph = t2080_init_periph,
638 .cmux_groups = {
639 &t1040_cmux
640 },
641 .hwaccel = {
642 &ls1046a_hwa1, &ls1046a_hwa2
643 },
644 .cmux_to_group = {
645 0, -1
646 },
647 .pll_mask = BIT(PLATFORM_PLL) |
648 BIT(CGA_PLL1) | BIT(CGA_PLL2),
649 .flags = CG_PLL_8BIT,
650 },
651 {
652 .compat = "fsl,ls1088a-clockgen",
653 .cmux_groups = {
654 &clockgen2_cmux_cga12
655 },
656 .hwaccel = {
657 &ls1088a_hwa1, &ls1088a_hwa2
658 },
659 .cmux_to_group = {
660 0, 0, -1
661 },
662 .pll_mask = BIT(PLATFORM_PLL) |
663 BIT(CGA_PLL1) | BIT(CGA_PLL2),
664 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
665 },
666 {
667 .compat = "fsl,ls1012a-clockgen",
668 .cmux_groups = {
669 &ls1012a_cmux
670 },
671 .cmux_to_group = {
672 0, -1
673 },
674 .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
675 },
676 {
677 .compat = "fsl,ls2080a-clockgen",
678 .cmux_groups = {
679 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
680 },
681 .cmux_to_group = {
682 0, 0, 1, 1, -1
683 },
684 .pll_mask = BIT(PLATFORM_PLL) |
685 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
686 BIT(CGB_PLL1) | BIT(CGB_PLL2),
687 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
688 },
689 {
690 .compat = "fsl,lx2160a-clockgen",
691 .cmux_groups = {
692 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
693 },
694 .cmux_to_group = {
695 0, 0, 0, 0, 1, 1, 1, 1, -1
696 },
697 .pll_mask = BIT(PLATFORM_PLL) |
698 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
699 BIT(CGB_PLL1) | BIT(CGB_PLL2),
700 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
701 },
702 {
703 .compat = "fsl,p2041-clockgen",
704 .guts_compat = "fsl,qoriq-device-config-1.0",
705 .init_periph = p2041_init_periph,
706 .cmux_groups = {
707 &p2041_cmux_grp1, &p2041_cmux_grp2
708 },
709 .cmux_to_group = {
710 0, 0, 1, 1, -1
711 },
712 .pll_mask = BIT(PLATFORM_PLL) |
713 BIT(CGA_PLL1) | BIT(CGA_PLL2),
714 },
715 {
716 .compat = "fsl,p3041-clockgen",
717 .guts_compat = "fsl,qoriq-device-config-1.0",
718 .init_periph = p2041_init_periph,
719 .cmux_groups = {
720 &p2041_cmux_grp1, &p2041_cmux_grp2
721 },
722 .cmux_to_group = {
723 0, 0, 1, 1, -1
724 },
725 .pll_mask = BIT(PLATFORM_PLL) |
726 BIT(CGA_PLL1) | BIT(CGA_PLL2),
727 },
728 {
729 .compat = "fsl,p4080-clockgen",
730 .guts_compat = "fsl,qoriq-device-config-1.0",
731 .init_periph = p4080_init_periph,
732 .cmux_groups = {
733 &p4080_cmux_grp1, &p4080_cmux_grp2
734 },
735 .cmux_to_group = {
736 0, 0, 0, 0, 1, 1, 1, 1, -1
737 },
738 .pll_mask = BIT(PLATFORM_PLL) |
739 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
740 BIT(CGA_PLL3) | BIT(CGA_PLL4),
741 },
742 {
743 .compat = "fsl,p5020-clockgen",
744 .guts_compat = "fsl,qoriq-device-config-1.0",
745 .init_periph = p5020_init_periph,
746 .cmux_groups = {
747 &p5020_cmux_grp1, &p5020_cmux_grp2
748 },
749 .cmux_to_group = {
750 0, 1, -1
751 },
752 .pll_mask = BIT(PLATFORM_PLL) |
753 BIT(CGA_PLL1) | BIT(CGA_PLL2),
754 },
755 {
756 .compat = "fsl,p5040-clockgen",
757 .guts_compat = "fsl,p5040-device-config",
758 .init_periph = p5040_init_periph,
759 .cmux_groups = {
760 &p5040_cmux_grp1, &p5040_cmux_grp2
761 },
762 .cmux_to_group = {
763 0, 0, 1, 1, -1
764 },
765 .pll_mask = BIT(PLATFORM_PLL) |
766 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),
767 },
768 {
769 .compat = "fsl,t1023-clockgen",
770 .guts_compat = "fsl,t1023-device-config",
771 .init_periph = t1023_init_periph,
772 .cmux_groups = {
773 &t1023_cmux
774 },
775 .hwaccel = {
776 &t1023_hwa1, &t1023_hwa2
777 },
778 .cmux_to_group = {
779 0, 0, -1
780 },
781 .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
782 .flags = CG_PLL_8BIT,
783 },
784 {
785 .compat = "fsl,t1040-clockgen",
786 .guts_compat = "fsl,t1040-device-config",
787 .init_periph = t1040_init_periph,
788 .cmux_groups = {
789 &t1040_cmux
790 },
791 .cmux_to_group = {
792 0, 0, 0, 0, -1
793 },
794 .pll_mask = BIT(PLATFORM_PLL) |
795 BIT(CGA_PLL1) | BIT(CGA_PLL2),
796 .flags = CG_PLL_8BIT,
797 },
798 {
799 .compat = "fsl,t2080-clockgen",
800 .guts_compat = "fsl,t2080-device-config",
801 .init_periph = t2080_init_periph,
802 .cmux_groups = {
803 &clockgen2_cmux_cga12
804 },
805 .hwaccel = {
806 &t2080_hwa1, &t2080_hwa2
807 },
808 .cmux_to_group = {
809 0, -1
810 },
811 .pll_mask = BIT(PLATFORM_PLL) |
812 BIT(CGA_PLL1) | BIT(CGA_PLL2),
813 .flags = CG_PLL_8BIT,
814 },
815 {
816 .compat = "fsl,t4240-clockgen",
817 .guts_compat = "fsl,t4240-device-config",
818 .init_periph = t4240_init_periph,
819 .cmux_groups = {
820 &clockgen2_cmux_cga, &clockgen2_cmux_cgb
821 },
822 .hwaccel = {
823 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
824 },
825 .cmux_to_group = {
826 0, 0, 1, -1
827 },
828 .pll_mask = BIT(PLATFORM_PLL) |
829 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
830 BIT(CGB_PLL1) | BIT(CGB_PLL2),
831 .flags = CG_PLL_8BIT,
832 },
833 {},
834};
835
836struct mux_hwclock {
837 struct clk_hw hw;
838 struct clockgen *cg;
839 const struct clockgen_muxinfo *info;
840 u32 __iomem *reg;
841 u8 parent_to_clksel[NUM_MUX_PARENTS];
842 s8 clksel_to_parent[NUM_MUX_PARENTS];
843 int num_parents;
844};
845
846#define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
847#define CLKSEL_MASK 0x78000000
848#define CLKSEL_SHIFT 27
849
850static int mux_set_parent(struct clk_hw *hw, u8 idx)
851{
852 struct mux_hwclock *hwc = to_mux_hwclock(hw);
853 u32 clksel;
854
855 if (idx >= hwc->num_parents)
856 return -EINVAL;
857
858 clksel = hwc->parent_to_clksel[idx];
859 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
860
861 return 0;
862}
863
864static u8 mux_get_parent(struct clk_hw *hw)
865{
866 struct mux_hwclock *hwc = to_mux_hwclock(hw);
867 u32 clksel;
868 s8 ret;
869
870 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
871
872 ret = hwc->clksel_to_parent[clksel];
873 if (ret < 0) {
874 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
875 return 0;
876 }
877
878 return ret;
879}
880
881static const struct clk_ops cmux_ops = {
882 .determine_rate = clk_hw_determine_rate_no_reparent,
883 .get_parent = mux_get_parent,
884 .set_parent = mux_set_parent,
885};
886
887/*
888 * Don't allow setting for now, as the clock options haven't been
889 * sanitized for additional restrictions.
890 */
891static const struct clk_ops hwaccel_ops = {
892 .get_parent = mux_get_parent,
893};
894
895static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
896 struct mux_hwclock *hwc,
897 int idx)
898{
899 int pll, div;
900
901 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
902 return NULL;
903
904 pll = hwc->info->clksel[idx].pll;
905 div = hwc->info->clksel[idx].div;
906
907 return &cg->pll[pll].div[div];
908}
909
910static struct clk * __init create_mux_common(struct clockgen *cg,
911 struct mux_hwclock *hwc,
912 const struct clk_ops *ops,
913 unsigned long min_rate,
914 unsigned long max_rate,
915 unsigned long pct80_rate,
916 const char *fmt, int idx)
917{
918 struct clk_init_data init = {};
919 struct clk *clk;
920 const struct clockgen_pll_div *div;
921 const char *parent_names[NUM_MUX_PARENTS];
922 char name[32];
923 int i, j;
924
925 snprintf(name, sizeof(name), fmt, idx);
926
927 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
928 unsigned long rate;
929
930 hwc->clksel_to_parent[i] = -1;
931
932 div = get_pll_div(cg, hwc, i);
933 if (!div)
934 continue;
935
936 rate = clk_get_rate(div->clk);
937
938 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
939 rate > pct80_rate)
940 continue;
941 if (rate < min_rate)
942 continue;
943 if (rate > max_rate)
944 continue;
945
946 parent_names[j] = div->name;
947 hwc->parent_to_clksel[j] = i;
948 hwc->clksel_to_parent[i] = j;
949 j++;
950 }
951
952 init.name = name;
953 init.ops = ops;
954 init.parent_names = parent_names;
955 init.num_parents = hwc->num_parents = j;
956 init.flags = 0;
957 hwc->hw.init = &init;
958 hwc->cg = cg;
959
960 clk = clk_register(NULL, &hwc->hw);
961 if (IS_ERR(clk)) {
962 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
963 PTR_ERR(clk));
964 kfree(hwc);
965 return NULL;
966 }
967
968 return clk;
969}
970
971static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
972{
973 struct mux_hwclock *hwc;
974 const struct clockgen_pll_div *div;
975 unsigned long plat_rate, min_rate;
976 u64 max_rate, pct80_rate;
977 u32 clksel;
978
979 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
980 if (!hwc)
981 return NULL;
982
983 if (cg->info.flags & CG_VER3)
984 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
985 else
986 hwc->reg = cg->regs + 0x20 * idx;
987
988 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
989
990 /*
991 * Find the rate for the default clksel, and treat it as the
992 * maximum rated core frequency. If this is an incorrect
993 * assumption, certain clock options (possibly including the
994 * default clksel) may be inappropriately excluded on certain
995 * chips.
996 */
997 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
998 div = get_pll_div(cg, hwc, clksel);
999 if (!div) {
1000 kfree(hwc);
1001 return NULL;
1002 }
1003
1004 max_rate = clk_get_rate(div->clk);
1005 pct80_rate = max_rate * 8;
1006 do_div(pct80_rate, 10);
1007
1008 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
1009
1010 if (cg->info.flags & CG_CMUX_GE_PLAT)
1011 min_rate = plat_rate;
1012 else
1013 min_rate = plat_rate / 2;
1014
1015 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
1016 pct80_rate, "cg-cmux%d", idx);
1017}
1018
1019static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
1020{
1021 struct mux_hwclock *hwc;
1022
1023 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
1024 if (!hwc)
1025 return NULL;
1026
1027 hwc->reg = cg->regs + 0x20 * idx + 0x10;
1028 hwc->info = cg->info.hwaccel[idx];
1029
1030 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
1031 "cg-hwaccel%d", idx);
1032}
1033
1034static void __init create_muxes(struct clockgen *cg)
1035{
1036 int i;
1037
1038 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
1039 if (cg->info.cmux_to_group[i] < 0)
1040 break;
1041 if (cg->info.cmux_to_group[i] >=
1042 ARRAY_SIZE(cg->info.cmux_groups)) {
1043 WARN_ON_ONCE(1);
1044 continue;
1045 }
1046
1047 cg->cmux[i] = create_one_cmux(cg, i);
1048 }
1049
1050 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
1051 if (!cg->info.hwaccel[i])
1052 continue;
1053
1054 cg->hwaccel[i] = create_one_hwaccel(cg, i);
1055 }
1056}
1057
1058static void __init _clockgen_init(struct device_node *np, bool legacy);
1059
1060/*
1061 * Legacy nodes may get probed before the parent clockgen node.
1062 * It is assumed that device trees with legacy nodes will not
1063 * contain a "clocks" property -- otherwise the input clocks may
1064 * not be initialized at this point.
1065 */
1066static void __init legacy_init_clockgen(struct device_node *np)
1067{
1068 if (!clockgen.node) {
1069 struct device_node *parent_np __free(device_node) = of_get_parent(np);
1070 _clockgen_init(parent_np, true);
1071 }
1072}
1073
1074/* Legacy node */
1075static void __init core_mux_init(struct device_node *np)
1076{
1077 struct clk *clk;
1078 struct resource res;
1079 int idx, rc;
1080
1081 legacy_init_clockgen(np);
1082
1083 if (of_address_to_resource(np, 0, &res))
1084 return;
1085
1086 idx = (res.start & 0xf0) >> 5;
1087 clk = clockgen.cmux[idx];
1088
1089 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
1090 if (rc) {
1091 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1092 __func__, np, rc);
1093 return;
1094 }
1095}
1096
1097static struct clk __init
1098*sysclk_from_fixed(struct device_node *node, const char *name)
1099{
1100 u32 rate;
1101
1102 if (of_property_read_u32(node, "clock-frequency", &rate))
1103 return ERR_PTR(-ENODEV);
1104
1105 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
1106}
1107
1108static struct clk __init *input_clock(const char *name, struct clk *clk)
1109{
1110 const char *input_name;
1111
1112 /* Register the input clock under the desired name. */
1113 input_name = __clk_get_name(clk);
1114 clk = clk_register_fixed_factor(NULL, name, input_name,
1115 0, 1, 1);
1116 if (IS_ERR(clk))
1117 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
1118 PTR_ERR(clk));
1119
1120 return clk;
1121}
1122
1123static struct clk __init *input_clock_by_name(const char *name,
1124 const char *dtname)
1125{
1126 struct clk *clk;
1127
1128 clk = of_clk_get_by_name(clockgen.node, dtname);
1129 if (IS_ERR(clk))
1130 return clk;
1131
1132 return input_clock(name, clk);
1133}
1134
1135static struct clk __init *input_clock_by_index(const char *name, int idx)
1136{
1137 struct clk *clk;
1138
1139 clk = of_clk_get(clockgen.node, 0);
1140 if (IS_ERR(clk))
1141 return clk;
1142
1143 return input_clock(name, clk);
1144}
1145
1146static struct clk * __init create_sysclk(const char *name)
1147{
1148 struct device_node *sysclk;
1149 struct clk *clk;
1150
1151 clk = sysclk_from_fixed(clockgen.node, name);
1152 if (!IS_ERR(clk))
1153 return clk;
1154
1155 clk = input_clock_by_name(name, "sysclk");
1156 if (!IS_ERR(clk))
1157 return clk;
1158
1159 clk = input_clock_by_index(name, 0);
1160 if (!IS_ERR(clk))
1161 return clk;
1162
1163 sysclk = of_get_child_by_name(clockgen.node, "sysclk");
1164 if (sysclk) {
1165 clk = sysclk_from_fixed(sysclk, name);
1166 of_node_put(sysclk);
1167 if (!IS_ERR(clk))
1168 return clk;
1169 }
1170
1171 pr_err("%s: No input sysclk\n", __func__);
1172 return NULL;
1173}
1174
1175static struct clk * __init create_coreclk(const char *name)
1176{
1177 struct clk *clk;
1178
1179 clk = input_clock_by_name(name, "coreclk");
1180 if (!IS_ERR(clk))
1181 return clk;
1182
1183 /*
1184 * This indicates a mix of legacy nodes with the new coreclk
1185 * mechanism, which should never happen. If this error occurs,
1186 * don't use the wrong input clock just because coreclk isn't
1187 * ready yet.
1188 */
1189 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
1190 return clk;
1191
1192 return NULL;
1193}
1194
1195/* Legacy node */
1196static void __init sysclk_init(struct device_node *node)
1197{
1198 struct clk *clk;
1199
1200 legacy_init_clockgen(node);
1201
1202 clk = clockgen.sysclk;
1203 if (clk)
1204 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1205}
1206
1207#define PLL_KILL BIT(31)
1208
1209static void __init create_one_pll(struct clockgen *cg, int idx)
1210{
1211 u32 __iomem *reg;
1212 u32 mult;
1213 struct clockgen_pll *pll = &cg->pll[idx];
1214 const char *input = "cg-sysclk";
1215 int i;
1216
1217 if (!(cg->info.pll_mask & (1 << idx)))
1218 return;
1219
1220 if (cg->coreclk && idx != PLATFORM_PLL) {
1221 if (IS_ERR(cg->coreclk))
1222 return;
1223
1224 input = "cg-coreclk";
1225 }
1226
1227 if (cg->info.flags & CG_VER3) {
1228 switch (idx) {
1229 case PLATFORM_PLL:
1230 reg = cg->regs + 0x60080;
1231 break;
1232 case CGA_PLL1:
1233 reg = cg->regs + 0x80;
1234 break;
1235 case CGA_PLL2:
1236 reg = cg->regs + 0xa0;
1237 break;
1238 case CGB_PLL1:
1239 reg = cg->regs + 0x10080;
1240 break;
1241 case CGB_PLL2:
1242 reg = cg->regs + 0x100a0;
1243 break;
1244 default:
1245 WARN_ONCE(1, "index %d\n", idx);
1246 return;
1247 }
1248 } else {
1249 if (idx == PLATFORM_PLL)
1250 reg = cg->regs + 0xc00;
1251 else
1252 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1253 }
1254
1255 /* Get the multiple of PLL */
1256 mult = cg_in(cg, reg);
1257
1258 /* Check if this PLL is disabled */
1259 if (mult & PLL_KILL) {
1260 pr_debug("%s(): pll %p disabled\n", __func__, reg);
1261 return;
1262 }
1263
1264 if ((cg->info.flags & CG_VER3) ||
1265 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1266 mult = (mult & GENMASK(8, 1)) >> 1;
1267 else
1268 mult = (mult & GENMASK(6, 1)) >> 1;
1269
1270 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
1271 struct clk *clk;
1272 int ret;
1273
1274 /*
1275 * For platform PLL, there are MAX_PLL_DIV divider clocks.
1276 * For core PLL, there are 4 divider clocks at most.
1277 */
1278 if (idx != PLATFORM_PLL && i >= 4)
1279 break;
1280
1281 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
1282 "cg-pll%d-div%d", idx, i + 1);
1283
1284 clk = clk_register_fixed_factor(NULL,
1285 pll->div[i].name, input, 0, mult, i + 1);
1286 if (IS_ERR(clk)) {
1287 pr_err("%s: %s: register failed %ld\n",
1288 __func__, pll->div[i].name, PTR_ERR(clk));
1289 continue;
1290 }
1291
1292 pll->div[i].clk = clk;
1293 ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
1294 if (ret != 0)
1295 pr_err("%s: %s: register to lookup table failed %d\n",
1296 __func__, pll->div[i].name, ret);
1297
1298 }
1299}
1300
1301static void __init create_plls(struct clockgen *cg)
1302{
1303 int i;
1304
1305 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1306 create_one_pll(cg, i);
1307}
1308
1309static void __init legacy_pll_init(struct device_node *np, int idx)
1310{
1311 struct clockgen_pll *pll;
1312 struct clk_onecell_data *onecell_data;
1313 struct clk **subclks;
1314 int count, rc;
1315
1316 legacy_init_clockgen(np);
1317
1318 pll = &clockgen.pll[idx];
1319 count = of_property_count_strings(np, "clock-output-names");
1320
1321 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
1322 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
1323 if (!subclks)
1324 return;
1325
1326 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
1327 if (!onecell_data)
1328 goto err_clks;
1329
1330 if (count <= 3) {
1331 subclks[0] = pll->div[0].clk;
1332 subclks[1] = pll->div[1].clk;
1333 subclks[2] = pll->div[3].clk;
1334 } else {
1335 subclks[0] = pll->div[0].clk;
1336 subclks[1] = pll->div[1].clk;
1337 subclks[2] = pll->div[2].clk;
1338 subclks[3] = pll->div[3].clk;
1339 }
1340
1341 onecell_data->clks = subclks;
1342 onecell_data->clk_num = count;
1343
1344 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1345 if (rc) {
1346 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1347 __func__, np, rc);
1348 goto err_cell;
1349 }
1350
1351 return;
1352err_cell:
1353 kfree(onecell_data);
1354err_clks:
1355 kfree(subclks);
1356}
1357
1358/* Legacy node */
1359static void __init pltfrm_pll_init(struct device_node *np)
1360{
1361 legacy_pll_init(np, PLATFORM_PLL);
1362}
1363
1364/* Legacy node */
1365static void __init core_pll_init(struct device_node *np)
1366{
1367 struct resource res;
1368 int idx;
1369
1370 if (of_address_to_resource(np, 0, &res))
1371 return;
1372
1373 if ((res.start & 0xfff) == 0xc00) {
1374 /*
1375 * ls1021a devtree labels the platform PLL
1376 * with the core PLL compatible
1377 */
1378 pltfrm_pll_init(np);
1379 } else {
1380 idx = (res.start & 0xf0) >> 5;
1381 legacy_pll_init(np, CGA_PLL1 + idx);
1382 }
1383}
1384
1385static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
1386{
1387 struct clockgen *cg = data;
1388 struct clk *clk;
1389 struct clockgen_pll *pll;
1390 u32 type, idx;
1391
1392 if (clkspec->args_count < 2) {
1393 pr_err("%s: insufficient phandle args\n", __func__);
1394 return ERR_PTR(-EINVAL);
1395 }
1396
1397 type = clkspec->args[0];
1398 idx = clkspec->args[1];
1399
1400 switch (type) {
1401 case QORIQ_CLK_SYSCLK:
1402 if (idx != 0)
1403 goto bad_args;
1404 clk = cg->sysclk;
1405 break;
1406 case QORIQ_CLK_CMUX:
1407 if (idx >= ARRAY_SIZE(cg->cmux))
1408 goto bad_args;
1409 clk = cg->cmux[idx];
1410 break;
1411 case QORIQ_CLK_HWACCEL:
1412 if (idx >= ARRAY_SIZE(cg->hwaccel))
1413 goto bad_args;
1414 clk = cg->hwaccel[idx];
1415 break;
1416 case QORIQ_CLK_FMAN:
1417 if (idx >= ARRAY_SIZE(cg->fman))
1418 goto bad_args;
1419 clk = cg->fman[idx];
1420 break;
1421 case QORIQ_CLK_PLATFORM_PLL:
1422 pll = &cg->pll[PLATFORM_PLL];
1423 if (idx >= ARRAY_SIZE(pll->div))
1424 goto bad_args;
1425 clk = pll->div[idx].clk;
1426 break;
1427 case QORIQ_CLK_CORECLK:
1428 if (idx != 0)
1429 goto bad_args;
1430 clk = cg->coreclk;
1431 if (IS_ERR(clk))
1432 clk = NULL;
1433 break;
1434 default:
1435 goto bad_args;
1436 }
1437
1438 if (!clk)
1439 return ERR_PTR(-ENOENT);
1440 return clk;
1441
1442bad_args:
1443 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
1444 return ERR_PTR(-EINVAL);
1445}
1446
1447#ifdef CONFIG_PPC
1448#include <asm/mpc85xx.h>
1449
1450static const u32 a4510_svrs[] __initconst = {
1451 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
1452 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
1453 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
1454 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
1455 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
1456 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
1457 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
1458 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
1459 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
1460 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
1461 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
1462 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
1463 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
1464};
1465
1466#define SVR_SECURITY 0x80000 /* The Security (E) bit */
1467
1468static bool __init has_erratum_a4510(void)
1469{
1470 u32 svr = mfspr(SPRN_SVR);
1471 int i;
1472
1473 svr &= ~SVR_SECURITY;
1474
1475 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
1476 if (svr == a4510_svrs[i])
1477 return true;
1478 }
1479
1480 return false;
1481}
1482#else
1483static bool __init has_erratum_a4510(void)
1484{
1485 return false;
1486}
1487#endif
1488
1489static void __init _clockgen_init(struct device_node *np, bool legacy)
1490{
1491 int i, ret;
1492 bool is_old_ls1021a = false;
1493
1494 /* May have already been called by a legacy probe */
1495 if (clockgen.node)
1496 return;
1497
1498 clockgen.node = np;
1499 clockgen.regs = of_iomap(np, 0);
1500 if (!clockgen.regs &&
1501 of_device_is_compatible(of_root, "fsl,ls1021a")) {
1502 /* Compatibility hack for old, broken device trees */
1503 clockgen.regs = ioremap(0x1ee1000, 0x1000);
1504 is_old_ls1021a = true;
1505 }
1506 if (!clockgen.regs) {
1507 pr_err("%s(): %pOFn: of_iomap() failed\n", __func__, np);
1508 return;
1509 }
1510
1511 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
1512 if (of_device_is_compatible(np, chipinfo[i].compat))
1513 break;
1514 if (is_old_ls1021a &&
1515 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
1516 break;
1517 }
1518
1519 if (i == ARRAY_SIZE(chipinfo)) {
1520 pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
1521 goto err;
1522 }
1523 clockgen.info = chipinfo[i];
1524
1525 if (clockgen.info.guts_compat) {
1526 struct device_node *guts;
1527
1528 guts = of_find_compatible_node(NULL, NULL,
1529 clockgen.info.guts_compat);
1530 if (guts) {
1531 clockgen.guts = of_iomap(guts, 0);
1532 if (!clockgen.guts) {
1533 pr_err("%s: Couldn't map %pOF regs\n", __func__,
1534 guts);
1535 }
1536 of_node_put(guts);
1537 }
1538
1539 }
1540
1541 if (has_erratum_a4510())
1542 clockgen.info.flags |= CG_CMUX_GE_PLAT;
1543
1544 clockgen.sysclk = create_sysclk("cg-sysclk");
1545 clockgen.coreclk = create_coreclk("cg-coreclk");
1546 create_plls(&clockgen);
1547 create_muxes(&clockgen);
1548
1549 if (clockgen.info.init_periph)
1550 clockgen.info.init_periph(&clockgen);
1551
1552 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1553 if (ret) {
1554 pr_err("%s: Couldn't register clk provider for node %pOFn: %d\n",
1555 __func__, np, ret);
1556 }
1557
1558 /* Don't create cpufreq device for legacy clockgen blocks */
1559 add_cpufreq_dev = !legacy;
1560
1561 return;
1562err:
1563 iounmap(clockgen.regs);
1564 clockgen.regs = NULL;
1565}
1566
1567static void __init clockgen_init(struct device_node *np)
1568{
1569 _clockgen_init(np, false);
1570}
1571
1572static int __init clockgen_cpufreq_init(void)
1573{
1574 struct platform_device *pdev;
1575
1576 if (add_cpufreq_dev) {
1577 pdev = platform_device_register_simple("qoriq-cpufreq", -1,
1578 NULL, 0);
1579 if (IS_ERR(pdev))
1580 pr_err("Couldn't register qoriq-cpufreq err=%ld\n",
1581 PTR_ERR(pdev));
1582 }
1583 return 0;
1584}
1585device_initcall(clockgen_cpufreq_init);
1586
1587CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1588CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1589CLK_OF_DECLARE(qoriq_clockgen_b4420, "fsl,b4420-clockgen", clockgen_init);
1590CLK_OF_DECLARE(qoriq_clockgen_b4860, "fsl,b4860-clockgen", clockgen_init);
1591CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1592CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1593CLK_OF_DECLARE(qoriq_clockgen_ls1028a, "fsl,ls1028a-clockgen", clockgen_init);
1594CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1595CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1596CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1597CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1598CLK_OF_DECLARE(qoriq_clockgen_lx2160a, "fsl,lx2160a-clockgen", clockgen_init);
1599CLK_OF_DECLARE(qoriq_clockgen_p2041, "fsl,p2041-clockgen", clockgen_init);
1600CLK_OF_DECLARE(qoriq_clockgen_p3041, "fsl,p3041-clockgen", clockgen_init);
1601CLK_OF_DECLARE(qoriq_clockgen_p4080, "fsl,p4080-clockgen", clockgen_init);
1602CLK_OF_DECLARE(qoriq_clockgen_p5020, "fsl,p5020-clockgen", clockgen_init);
1603CLK_OF_DECLARE(qoriq_clockgen_p5040, "fsl,p5040-clockgen", clockgen_init);
1604CLK_OF_DECLARE(qoriq_clockgen_t1023, "fsl,t1023-clockgen", clockgen_init);
1605CLK_OF_DECLARE(qoriq_clockgen_t1040, "fsl,t1040-clockgen", clockgen_init);
1606CLK_OF_DECLARE(qoriq_clockgen_t2080, "fsl,t2080-clockgen", clockgen_init);
1607CLK_OF_DECLARE(qoriq_clockgen_t4240, "fsl,t4240-clockgen", clockgen_init);
1608
1609/* Legacy nodes */
1610CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1611CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1612CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1613CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1614CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1615CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1616CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1617CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);
1/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * clock driver for Freescale QorIQ SoCs.
9 */
10
11#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12
13#include <linux/clk.h>
14#include <linux/clk-provider.h>
15#include <linux/clkdev.h>
16#include <linux/fsl/guts.h>
17#include <linux/io.h>
18#include <linux/kernel.h>
19#include <linux/module.h>
20#include <linux/of_address.h>
21#include <linux/of_platform.h>
22#include <linux/of.h>
23#include <linux/slab.h>
24
25#define PLL_DIV1 0
26#define PLL_DIV2 1
27#define PLL_DIV3 2
28#define PLL_DIV4 3
29
30#define PLATFORM_PLL 0
31#define CGA_PLL1 1
32#define CGA_PLL2 2
33#define CGA_PLL3 3
34#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
35#define CGB_PLL1 4
36#define CGB_PLL2 5
37
38struct clockgen_pll_div {
39 struct clk *clk;
40 char name[32];
41};
42
43struct clockgen_pll {
44 struct clockgen_pll_div div[8];
45};
46
47#define CLKSEL_VALID 1
48#define CLKSEL_80PCT 2 /* Only allowed if PLL <= 80% of max cpu freq */
49
50struct clockgen_sourceinfo {
51 u32 flags; /* CLKSEL_xxx */
52 int pll; /* CGx_PLLn */
53 int div; /* PLL_DIVn */
54};
55
56#define NUM_MUX_PARENTS 16
57
58struct clockgen_muxinfo {
59 struct clockgen_sourceinfo clksel[NUM_MUX_PARENTS];
60};
61
62#define NUM_HWACCEL 5
63#define NUM_CMUX 8
64
65struct clockgen;
66
67/*
68 * cmux freq must be >= platform pll.
69 * If not set, cmux freq must be >= platform pll/2
70 */
71#define CG_CMUX_GE_PLAT 1
72
73#define CG_PLL_8BIT 2 /* PLLCnGSR[CFG] is 8 bits, not 6 */
74#define CG_VER3 4 /* version 3 cg: reg layout different */
75#define CG_LITTLE_ENDIAN 8
76
77struct clockgen_chipinfo {
78 const char *compat, *guts_compat;
79 const struct clockgen_muxinfo *cmux_groups[2];
80 const struct clockgen_muxinfo *hwaccel[NUM_HWACCEL];
81 void (*init_periph)(struct clockgen *cg);
82 int cmux_to_group[NUM_CMUX]; /* -1 terminates if fewer than NUM_CMUX */
83 u32 pll_mask; /* 1 << n bit set if PLL n is valid */
84 u32 flags; /* CG_xxx */
85};
86
87struct clockgen {
88 struct device_node *node;
89 void __iomem *regs;
90 struct clockgen_chipinfo info; /* mutable copy */
91 struct clk *sysclk, *coreclk;
92 struct clockgen_pll pll[6];
93 struct clk *cmux[NUM_CMUX];
94 struct clk *hwaccel[NUM_HWACCEL];
95 struct clk *fman[2];
96 struct ccsr_guts __iomem *guts;
97};
98
99static struct clockgen clockgen;
100
101static void cg_out(struct clockgen *cg, u32 val, u32 __iomem *reg)
102{
103 if (cg->info.flags & CG_LITTLE_ENDIAN)
104 iowrite32(val, reg);
105 else
106 iowrite32be(val, reg);
107}
108
109static u32 cg_in(struct clockgen *cg, u32 __iomem *reg)
110{
111 u32 val;
112
113 if (cg->info.flags & CG_LITTLE_ENDIAN)
114 val = ioread32(reg);
115 else
116 val = ioread32be(reg);
117
118 return val;
119}
120
121static const struct clockgen_muxinfo p2041_cmux_grp1 = {
122 {
123 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
124 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
125 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
126 }
127};
128
129static const struct clockgen_muxinfo p2041_cmux_grp2 = {
130 {
131 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
132 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
133 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
134 }
135};
136
137static const struct clockgen_muxinfo p5020_cmux_grp1 = {
138 {
139 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
140 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
141 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
142 }
143};
144
145static const struct clockgen_muxinfo p5020_cmux_grp2 = {
146 {
147 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
148 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
149 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
150 }
151};
152
153static const struct clockgen_muxinfo p5040_cmux_grp1 = {
154 {
155 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
156 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
157 [4] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV1 },
158 [5] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL2, PLL_DIV2 },
159 }
160};
161
162static const struct clockgen_muxinfo p5040_cmux_grp2 = {
163 {
164 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
165 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
166 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
167 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
168 }
169};
170
171static const struct clockgen_muxinfo p4080_cmux_grp1 = {
172 {
173 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
174 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
175 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
176 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
177 [8] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL3, PLL_DIV1 },
178 }
179};
180
181static const struct clockgen_muxinfo p4080_cmux_grp2 = {
182 {
183 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
184 [8] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
185 [9] = { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
186 [12] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV1 },
187 [13] = { CLKSEL_VALID, CGA_PLL4, PLL_DIV2 },
188 }
189};
190
191static const struct clockgen_muxinfo t1023_cmux = {
192 {
193 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
194 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
195 }
196};
197
198static const struct clockgen_muxinfo t1040_cmux = {
199 {
200 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
201 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
202 [4] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
203 [5] = { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
204 }
205};
206
207
208static const struct clockgen_muxinfo clockgen2_cmux_cga = {
209 {
210 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
212 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
213 {},
214 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
215 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
216 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
217 {},
218 { CLKSEL_VALID, CGA_PLL3, PLL_DIV1 },
219 { CLKSEL_VALID, CGA_PLL3, PLL_DIV2 },
220 { CLKSEL_VALID, CGA_PLL3, PLL_DIV4 },
221 },
222};
223
224static const struct clockgen_muxinfo clockgen2_cmux_cga12 = {
225 {
226 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
228 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
229 {},
230 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
231 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
232 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
233 },
234};
235
236static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
237 {
238 { CLKSEL_VALID, CGB_PLL1, PLL_DIV1 },
239 { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
240 { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
241 {},
242 { CLKSEL_VALID, CGB_PLL2, PLL_DIV1 },
243 { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
244 { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
245 },
246};
247
248static const struct clockgen_muxinfo ls1043a_hwa1 = {
249 {
250 {},
251 {},
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
253 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
254 {},
255 {},
256 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
257 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
258 },
259};
260
261static const struct clockgen_muxinfo ls1043a_hwa2 = {
262 {
263 {},
264 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
265 {},
266 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
267 },
268};
269
270static const struct clockgen_muxinfo ls1046a_hwa1 = {
271 {
272 {},
273 {},
274 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
275 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
276 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
277 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
278 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
279 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
280 },
281};
282
283static const struct clockgen_muxinfo ls1046a_hwa2 = {
284 {
285 {},
286 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
287 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
288 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
289 {},
290 {},
291 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
292 },
293};
294
295static const struct clockgen_muxinfo ls1012a_cmux = {
296 {
297 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
298 {},
299 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
300 }
301};
302
303static const struct clockgen_muxinfo t1023_hwa1 = {
304 {
305 {},
306 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
307 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
308 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
309 },
310};
311
312static const struct clockgen_muxinfo t1023_hwa2 = {
313 {
314 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
315 },
316};
317
318static const struct clockgen_muxinfo t2080_hwa1 = {
319 {
320 {},
321 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
322 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
323 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
324 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
325 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
326 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
327 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
328 },
329};
330
331static const struct clockgen_muxinfo t2080_hwa2 = {
332 {
333 {},
334 { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
335 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
336 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
337 { CLKSEL_VALID, CGA_PLL2, PLL_DIV4 },
338 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
339 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
340 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
341 },
342};
343
344static const struct clockgen_muxinfo t4240_hwa1 = {
345 {
346 { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV2 },
347 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
348 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
349 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
350 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
351 {},
352 { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
353 { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
354 },
355};
356
357static const struct clockgen_muxinfo t4240_hwa4 = {
358 {
359 [2] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
360 [3] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
361 [4] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV4 },
362 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
363 [6] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
364 },
365};
366
367static const struct clockgen_muxinfo t4240_hwa5 = {
368 {
369 [2] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV2 },
370 [3] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV3 },
371 [4] = { CLKSEL_VALID, CGB_PLL2, PLL_DIV4 },
372 [5] = { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 },
373 [6] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV2 },
374 [7] = { CLKSEL_VALID, CGB_PLL1, PLL_DIV3 },
375 },
376};
377
378#define RCWSR7_FM1_CLK_SEL 0x40000000
379#define RCWSR7_FM2_CLK_SEL 0x20000000
380#define RCWSR7_HWA_ASYNC_DIV 0x04000000
381
382static void __init p2041_init_periph(struct clockgen *cg)
383{
384 u32 reg;
385
386 reg = ioread32be(&cg->guts->rcwsr[7]);
387
388 if (reg & RCWSR7_FM1_CLK_SEL)
389 cg->fman[0] = cg->pll[CGA_PLL2].div[PLL_DIV2].clk;
390 else
391 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
392}
393
394static void __init p4080_init_periph(struct clockgen *cg)
395{
396 u32 reg;
397
398 reg = ioread32be(&cg->guts->rcwsr[7]);
399
400 if (reg & RCWSR7_FM1_CLK_SEL)
401 cg->fman[0] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
402 else
403 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
404
405 if (reg & RCWSR7_FM2_CLK_SEL)
406 cg->fman[1] = cg->pll[CGA_PLL3].div[PLL_DIV2].clk;
407 else
408 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
409}
410
411static void __init p5020_init_periph(struct clockgen *cg)
412{
413 u32 reg;
414 int div = PLL_DIV2;
415
416 reg = ioread32be(&cg->guts->rcwsr[7]);
417 if (reg & RCWSR7_HWA_ASYNC_DIV)
418 div = PLL_DIV4;
419
420 if (reg & RCWSR7_FM1_CLK_SEL)
421 cg->fman[0] = cg->pll[CGA_PLL2].div[div].clk;
422 else
423 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
424}
425
426static void __init p5040_init_periph(struct clockgen *cg)
427{
428 u32 reg;
429 int div = PLL_DIV2;
430
431 reg = ioread32be(&cg->guts->rcwsr[7]);
432 if (reg & RCWSR7_HWA_ASYNC_DIV)
433 div = PLL_DIV4;
434
435 if (reg & RCWSR7_FM1_CLK_SEL)
436 cg->fman[0] = cg->pll[CGA_PLL3].div[div].clk;
437 else
438 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
439
440 if (reg & RCWSR7_FM2_CLK_SEL)
441 cg->fman[1] = cg->pll[CGA_PLL3].div[div].clk;
442 else
443 cg->fman[1] = cg->pll[PLATFORM_PLL].div[PLL_DIV2].clk;
444}
445
446static void __init t1023_init_periph(struct clockgen *cg)
447{
448 cg->fman[0] = cg->hwaccel[1];
449}
450
451static void __init t1040_init_periph(struct clockgen *cg)
452{
453 cg->fman[0] = cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk;
454}
455
456static void __init t2080_init_periph(struct clockgen *cg)
457{
458 cg->fman[0] = cg->hwaccel[0];
459}
460
461static void __init t4240_init_periph(struct clockgen *cg)
462{
463 cg->fman[0] = cg->hwaccel[3];
464 cg->fman[1] = cg->hwaccel[4];
465}
466
467static const struct clockgen_chipinfo chipinfo[] = {
468 {
469 .compat = "fsl,b4420-clockgen",
470 .guts_compat = "fsl,b4860-device-config",
471 .init_periph = t2080_init_periph,
472 .cmux_groups = {
473 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
474 },
475 .hwaccel = {
476 &t2080_hwa1
477 },
478 .cmux_to_group = {
479 0, 1, 1, 1, -1
480 },
481 .pll_mask = 0x3f,
482 .flags = CG_PLL_8BIT,
483 },
484 {
485 .compat = "fsl,b4860-clockgen",
486 .guts_compat = "fsl,b4860-device-config",
487 .init_periph = t2080_init_periph,
488 .cmux_groups = {
489 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
490 },
491 .hwaccel = {
492 &t2080_hwa1
493 },
494 .cmux_to_group = {
495 0, 1, 1, 1, -1
496 },
497 .pll_mask = 0x3f,
498 .flags = CG_PLL_8BIT,
499 },
500 {
501 .compat = "fsl,ls1021a-clockgen",
502 .cmux_groups = {
503 &t1023_cmux
504 },
505 .cmux_to_group = {
506 0, -1
507 },
508 .pll_mask = 0x03,
509 },
510 {
511 .compat = "fsl,ls1043a-clockgen",
512 .init_periph = t2080_init_periph,
513 .cmux_groups = {
514 &t1040_cmux
515 },
516 .hwaccel = {
517 &ls1043a_hwa1, &ls1043a_hwa2
518 },
519 .cmux_to_group = {
520 0, -1
521 },
522 .pll_mask = 0x07,
523 .flags = CG_PLL_8BIT,
524 },
525 {
526 .compat = "fsl,ls1046a-clockgen",
527 .init_periph = t2080_init_periph,
528 .cmux_groups = {
529 &t1040_cmux
530 },
531 .hwaccel = {
532 &ls1046a_hwa1, &ls1046a_hwa2
533 },
534 .cmux_to_group = {
535 0, -1
536 },
537 .pll_mask = 0x07,
538 .flags = CG_PLL_8BIT,
539 },
540 {
541 .compat = "fsl,ls1088a-clockgen",
542 .cmux_groups = {
543 &clockgen2_cmux_cga12
544 },
545 .cmux_to_group = {
546 0, 0, -1
547 },
548 .pll_mask = 0x07,
549 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
550 },
551 {
552 .compat = "fsl,ls1012a-clockgen",
553 .cmux_groups = {
554 &ls1012a_cmux
555 },
556 .cmux_to_group = {
557 0, -1
558 },
559 .pll_mask = 0x03,
560 },
561 {
562 .compat = "fsl,ls2080a-clockgen",
563 .cmux_groups = {
564 &clockgen2_cmux_cga12, &clockgen2_cmux_cgb
565 },
566 .cmux_to_group = {
567 0, 0, 1, 1, -1
568 },
569 .pll_mask = 0x37,
570 .flags = CG_VER3 | CG_LITTLE_ENDIAN,
571 },
572 {
573 .compat = "fsl,p2041-clockgen",
574 .guts_compat = "fsl,qoriq-device-config-1.0",
575 .init_periph = p2041_init_periph,
576 .cmux_groups = {
577 &p2041_cmux_grp1, &p2041_cmux_grp2
578 },
579 .cmux_to_group = {
580 0, 0, 1, 1, -1
581 },
582 .pll_mask = 0x07,
583 },
584 {
585 .compat = "fsl,p3041-clockgen",
586 .guts_compat = "fsl,qoriq-device-config-1.0",
587 .init_periph = p2041_init_periph,
588 .cmux_groups = {
589 &p2041_cmux_grp1, &p2041_cmux_grp2
590 },
591 .cmux_to_group = {
592 0, 0, 1, 1, -1
593 },
594 .pll_mask = 0x07,
595 },
596 {
597 .compat = "fsl,p4080-clockgen",
598 .guts_compat = "fsl,qoriq-device-config-1.0",
599 .init_periph = p4080_init_periph,
600 .cmux_groups = {
601 &p4080_cmux_grp1, &p4080_cmux_grp2
602 },
603 .cmux_to_group = {
604 0, 0, 0, 0, 1, 1, 1, 1
605 },
606 .pll_mask = 0x1f,
607 },
608 {
609 .compat = "fsl,p5020-clockgen",
610 .guts_compat = "fsl,qoriq-device-config-1.0",
611 .init_periph = p5020_init_periph,
612 .cmux_groups = {
613 &p2041_cmux_grp1, &p2041_cmux_grp2
614 },
615 .cmux_to_group = {
616 0, 1, -1
617 },
618 .pll_mask = 0x07,
619 },
620 {
621 .compat = "fsl,p5040-clockgen",
622 .guts_compat = "fsl,p5040-device-config",
623 .init_periph = p5040_init_periph,
624 .cmux_groups = {
625 &p5040_cmux_grp1, &p5040_cmux_grp2
626 },
627 .cmux_to_group = {
628 0, 0, 1, 1, -1
629 },
630 .pll_mask = 0x0f,
631 },
632 {
633 .compat = "fsl,t1023-clockgen",
634 .guts_compat = "fsl,t1023-device-config",
635 .init_periph = t1023_init_periph,
636 .cmux_groups = {
637 &t1023_cmux
638 },
639 .hwaccel = {
640 &t1023_hwa1, &t1023_hwa2
641 },
642 .cmux_to_group = {
643 0, 0, -1
644 },
645 .pll_mask = 0x03,
646 .flags = CG_PLL_8BIT,
647 },
648 {
649 .compat = "fsl,t1040-clockgen",
650 .guts_compat = "fsl,t1040-device-config",
651 .init_periph = t1040_init_periph,
652 .cmux_groups = {
653 &t1040_cmux
654 },
655 .cmux_to_group = {
656 0, 0, 0, 0, -1
657 },
658 .pll_mask = 0x07,
659 .flags = CG_PLL_8BIT,
660 },
661 {
662 .compat = "fsl,t2080-clockgen",
663 .guts_compat = "fsl,t2080-device-config",
664 .init_periph = t2080_init_periph,
665 .cmux_groups = {
666 &clockgen2_cmux_cga12
667 },
668 .hwaccel = {
669 &t2080_hwa1, &t2080_hwa2
670 },
671 .cmux_to_group = {
672 0, -1
673 },
674 .pll_mask = 0x07,
675 .flags = CG_PLL_8BIT,
676 },
677 {
678 .compat = "fsl,t4240-clockgen",
679 .guts_compat = "fsl,t4240-device-config",
680 .init_periph = t4240_init_periph,
681 .cmux_groups = {
682 &clockgen2_cmux_cga, &clockgen2_cmux_cgb
683 },
684 .hwaccel = {
685 &t4240_hwa1, NULL, NULL, &t4240_hwa4, &t4240_hwa5
686 },
687 .cmux_to_group = {
688 0, 0, 1, -1
689 },
690 .pll_mask = 0x3f,
691 .flags = CG_PLL_8BIT,
692 },
693 {},
694};
695
696struct mux_hwclock {
697 struct clk_hw hw;
698 struct clockgen *cg;
699 const struct clockgen_muxinfo *info;
700 u32 __iomem *reg;
701 u8 parent_to_clksel[NUM_MUX_PARENTS];
702 s8 clksel_to_parent[NUM_MUX_PARENTS];
703 int num_parents;
704};
705
706#define to_mux_hwclock(p) container_of(p, struct mux_hwclock, hw)
707#define CLKSEL_MASK 0x78000000
708#define CLKSEL_SHIFT 27
709
710static int mux_set_parent(struct clk_hw *hw, u8 idx)
711{
712 struct mux_hwclock *hwc = to_mux_hwclock(hw);
713 u32 clksel;
714
715 if (idx >= hwc->num_parents)
716 return -EINVAL;
717
718 clksel = hwc->parent_to_clksel[idx];
719 cg_out(hwc->cg, (clksel << CLKSEL_SHIFT) & CLKSEL_MASK, hwc->reg);
720
721 return 0;
722}
723
724static u8 mux_get_parent(struct clk_hw *hw)
725{
726 struct mux_hwclock *hwc = to_mux_hwclock(hw);
727 u32 clksel;
728 s8 ret;
729
730 clksel = (cg_in(hwc->cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
731
732 ret = hwc->clksel_to_parent[clksel];
733 if (ret < 0) {
734 pr_err("%s: mux at %p has bad clksel\n", __func__, hwc->reg);
735 return 0;
736 }
737
738 return ret;
739}
740
741static const struct clk_ops cmux_ops = {
742 .get_parent = mux_get_parent,
743 .set_parent = mux_set_parent,
744};
745
746/*
747 * Don't allow setting for now, as the clock options haven't been
748 * sanitized for additional restrictions.
749 */
750static const struct clk_ops hwaccel_ops = {
751 .get_parent = mux_get_parent,
752};
753
754static const struct clockgen_pll_div *get_pll_div(struct clockgen *cg,
755 struct mux_hwclock *hwc,
756 int idx)
757{
758 int pll, div;
759
760 if (!(hwc->info->clksel[idx].flags & CLKSEL_VALID))
761 return NULL;
762
763 pll = hwc->info->clksel[idx].pll;
764 div = hwc->info->clksel[idx].div;
765
766 return &cg->pll[pll].div[div];
767}
768
769static struct clk * __init create_mux_common(struct clockgen *cg,
770 struct mux_hwclock *hwc,
771 const struct clk_ops *ops,
772 unsigned long min_rate,
773 unsigned long max_rate,
774 unsigned long pct80_rate,
775 const char *fmt, int idx)
776{
777 struct clk_init_data init = {};
778 struct clk *clk;
779 const struct clockgen_pll_div *div;
780 const char *parent_names[NUM_MUX_PARENTS];
781 char name[32];
782 int i, j;
783
784 snprintf(name, sizeof(name), fmt, idx);
785
786 for (i = 0, j = 0; i < NUM_MUX_PARENTS; i++) {
787 unsigned long rate;
788
789 hwc->clksel_to_parent[i] = -1;
790
791 div = get_pll_div(cg, hwc, i);
792 if (!div)
793 continue;
794
795 rate = clk_get_rate(div->clk);
796
797 if (hwc->info->clksel[i].flags & CLKSEL_80PCT &&
798 rate > pct80_rate)
799 continue;
800 if (rate < min_rate)
801 continue;
802 if (rate > max_rate)
803 continue;
804
805 parent_names[j] = div->name;
806 hwc->parent_to_clksel[j] = i;
807 hwc->clksel_to_parent[i] = j;
808 j++;
809 }
810
811 init.name = name;
812 init.ops = ops;
813 init.parent_names = parent_names;
814 init.num_parents = hwc->num_parents = j;
815 init.flags = 0;
816 hwc->hw.init = &init;
817 hwc->cg = cg;
818
819 clk = clk_register(NULL, &hwc->hw);
820 if (IS_ERR(clk)) {
821 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
822 PTR_ERR(clk));
823 kfree(hwc);
824 return NULL;
825 }
826
827 return clk;
828}
829
830static struct clk * __init create_one_cmux(struct clockgen *cg, int idx)
831{
832 struct mux_hwclock *hwc;
833 const struct clockgen_pll_div *div;
834 unsigned long plat_rate, min_rate;
835 u64 max_rate, pct80_rate;
836 u32 clksel;
837
838 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
839 if (!hwc)
840 return NULL;
841
842 if (cg->info.flags & CG_VER3)
843 hwc->reg = cg->regs + 0x70000 + 0x20 * idx;
844 else
845 hwc->reg = cg->regs + 0x20 * idx;
846
847 hwc->info = cg->info.cmux_groups[cg->info.cmux_to_group[idx]];
848
849 /*
850 * Find the rate for the default clksel, and treat it as the
851 * maximum rated core frequency. If this is an incorrect
852 * assumption, certain clock options (possibly including the
853 * default clksel) may be inappropriately excluded on certain
854 * chips.
855 */
856 clksel = (cg_in(cg, hwc->reg) & CLKSEL_MASK) >> CLKSEL_SHIFT;
857 div = get_pll_div(cg, hwc, clksel);
858 if (!div) {
859 kfree(hwc);
860 return NULL;
861 }
862
863 max_rate = clk_get_rate(div->clk);
864 pct80_rate = max_rate * 8;
865 do_div(pct80_rate, 10);
866
867 plat_rate = clk_get_rate(cg->pll[PLATFORM_PLL].div[PLL_DIV1].clk);
868
869 if (cg->info.flags & CG_CMUX_GE_PLAT)
870 min_rate = plat_rate;
871 else
872 min_rate = plat_rate / 2;
873
874 return create_mux_common(cg, hwc, &cmux_ops, min_rate, max_rate,
875 pct80_rate, "cg-cmux%d", idx);
876}
877
878static struct clk * __init create_one_hwaccel(struct clockgen *cg, int idx)
879{
880 struct mux_hwclock *hwc;
881
882 hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
883 if (!hwc)
884 return NULL;
885
886 hwc->reg = cg->regs + 0x20 * idx + 0x10;
887 hwc->info = cg->info.hwaccel[idx];
888
889 return create_mux_common(cg, hwc, &hwaccel_ops, 0, ULONG_MAX, 0,
890 "cg-hwaccel%d", idx);
891}
892
893static void __init create_muxes(struct clockgen *cg)
894{
895 int i;
896
897 for (i = 0; i < ARRAY_SIZE(cg->cmux); i++) {
898 if (cg->info.cmux_to_group[i] < 0)
899 break;
900 if (cg->info.cmux_to_group[i] >=
901 ARRAY_SIZE(cg->info.cmux_groups)) {
902 WARN_ON_ONCE(1);
903 continue;
904 }
905
906 cg->cmux[i] = create_one_cmux(cg, i);
907 }
908
909 for (i = 0; i < ARRAY_SIZE(cg->hwaccel); i++) {
910 if (!cg->info.hwaccel[i])
911 continue;
912
913 cg->hwaccel[i] = create_one_hwaccel(cg, i);
914 }
915}
916
917static void __init clockgen_init(struct device_node *np);
918
919/*
920 * Legacy nodes may get probed before the parent clockgen node.
921 * It is assumed that device trees with legacy nodes will not
922 * contain a "clocks" property -- otherwise the input clocks may
923 * not be initialized at this point.
924 */
925static void __init legacy_init_clockgen(struct device_node *np)
926{
927 if (!clockgen.node)
928 clockgen_init(of_get_parent(np));
929}
930
931/* Legacy node */
932static void __init core_mux_init(struct device_node *np)
933{
934 struct clk *clk;
935 struct resource res;
936 int idx, rc;
937
938 legacy_init_clockgen(np);
939
940 if (of_address_to_resource(np, 0, &res))
941 return;
942
943 idx = (res.start & 0xf0) >> 5;
944 clk = clockgen.cmux[idx];
945
946 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
947 if (rc) {
948 pr_err("%s: Couldn't register clk provider for node %s: %d\n",
949 __func__, np->name, rc);
950 return;
951 }
952}
953
954static struct clk __init
955*sysclk_from_fixed(struct device_node *node, const char *name)
956{
957 u32 rate;
958
959 if (of_property_read_u32(node, "clock-frequency", &rate))
960 return ERR_PTR(-ENODEV);
961
962 return clk_register_fixed_rate(NULL, name, NULL, 0, rate);
963}
964
965static struct clk __init *input_clock(const char *name, struct clk *clk)
966{
967 const char *input_name;
968
969 /* Register the input clock under the desired name. */
970 input_name = __clk_get_name(clk);
971 clk = clk_register_fixed_factor(NULL, name, input_name,
972 0, 1, 1);
973 if (IS_ERR(clk))
974 pr_err("%s: Couldn't register %s: %ld\n", __func__, name,
975 PTR_ERR(clk));
976
977 return clk;
978}
979
980static struct clk __init *input_clock_by_name(const char *name,
981 const char *dtname)
982{
983 struct clk *clk;
984
985 clk = of_clk_get_by_name(clockgen.node, dtname);
986 if (IS_ERR(clk))
987 return clk;
988
989 return input_clock(name, clk);
990}
991
992static struct clk __init *input_clock_by_index(const char *name, int idx)
993{
994 struct clk *clk;
995
996 clk = of_clk_get(clockgen.node, 0);
997 if (IS_ERR(clk))
998 return clk;
999
1000 return input_clock(name, clk);
1001}
1002
1003static struct clk * __init create_sysclk(const char *name)
1004{
1005 struct device_node *sysclk;
1006 struct clk *clk;
1007
1008 clk = sysclk_from_fixed(clockgen.node, name);
1009 if (!IS_ERR(clk))
1010 return clk;
1011
1012 clk = input_clock_by_name(name, "sysclk");
1013 if (!IS_ERR(clk))
1014 return clk;
1015
1016 clk = input_clock_by_index(name, 0);
1017 if (!IS_ERR(clk))
1018 return clk;
1019
1020 sysclk = of_get_child_by_name(clockgen.node, "sysclk");
1021 if (sysclk) {
1022 clk = sysclk_from_fixed(sysclk, name);
1023 if (!IS_ERR(clk))
1024 return clk;
1025 }
1026
1027 pr_err("%s: No input sysclk\n", __func__);
1028 return NULL;
1029}
1030
1031static struct clk * __init create_coreclk(const char *name)
1032{
1033 struct clk *clk;
1034
1035 clk = input_clock_by_name(name, "coreclk");
1036 if (!IS_ERR(clk))
1037 return clk;
1038
1039 /*
1040 * This indicates a mix of legacy nodes with the new coreclk
1041 * mechanism, which should never happen. If this error occurs,
1042 * don't use the wrong input clock just because coreclk isn't
1043 * ready yet.
1044 */
1045 if (WARN_ON(PTR_ERR(clk) == -EPROBE_DEFER))
1046 return clk;
1047
1048 return NULL;
1049}
1050
1051/* Legacy node */
1052static void __init sysclk_init(struct device_node *node)
1053{
1054 struct clk *clk;
1055
1056 legacy_init_clockgen(node);
1057
1058 clk = clockgen.sysclk;
1059 if (clk)
1060 of_clk_add_provider(node, of_clk_src_simple_get, clk);
1061}
1062
1063#define PLL_KILL BIT(31)
1064
1065static void __init create_one_pll(struct clockgen *cg, int idx)
1066{
1067 u32 __iomem *reg;
1068 u32 mult;
1069 struct clockgen_pll *pll = &cg->pll[idx];
1070 const char *input = "cg-sysclk";
1071 int i;
1072
1073 if (!(cg->info.pll_mask & (1 << idx)))
1074 return;
1075
1076 if (cg->coreclk && idx != PLATFORM_PLL) {
1077 if (IS_ERR(cg->coreclk))
1078 return;
1079
1080 input = "cg-coreclk";
1081 }
1082
1083 if (cg->info.flags & CG_VER3) {
1084 switch (idx) {
1085 case PLATFORM_PLL:
1086 reg = cg->regs + 0x60080;
1087 break;
1088 case CGA_PLL1:
1089 reg = cg->regs + 0x80;
1090 break;
1091 case CGA_PLL2:
1092 reg = cg->regs + 0xa0;
1093 break;
1094 case CGB_PLL1:
1095 reg = cg->regs + 0x10080;
1096 break;
1097 case CGB_PLL2:
1098 reg = cg->regs + 0x100a0;
1099 break;
1100 default:
1101 WARN_ONCE(1, "index %d\n", idx);
1102 return;
1103 }
1104 } else {
1105 if (idx == PLATFORM_PLL)
1106 reg = cg->regs + 0xc00;
1107 else
1108 reg = cg->regs + 0x800 + 0x20 * (idx - 1);
1109 }
1110
1111 /* Get the multiple of PLL */
1112 mult = cg_in(cg, reg);
1113
1114 /* Check if this PLL is disabled */
1115 if (mult & PLL_KILL) {
1116 pr_debug("%s(): pll %p disabled\n", __func__, reg);
1117 return;
1118 }
1119
1120 if ((cg->info.flags & CG_VER3) ||
1121 ((cg->info.flags & CG_PLL_8BIT) && idx != PLATFORM_PLL))
1122 mult = (mult & GENMASK(8, 1)) >> 1;
1123 else
1124 mult = (mult & GENMASK(6, 1)) >> 1;
1125
1126 for (i = 0; i < ARRAY_SIZE(pll->div); i++) {
1127 struct clk *clk;
1128 int ret;
1129
1130 /*
1131 * For platform PLL, there are 8 divider clocks.
1132 * For core PLL, there are 4 divider clocks at most.
1133 */
1134 if (idx != PLATFORM_PLL && i >= 4)
1135 break;
1136
1137 snprintf(pll->div[i].name, sizeof(pll->div[i].name),
1138 "cg-pll%d-div%d", idx, i + 1);
1139
1140 clk = clk_register_fixed_factor(NULL,
1141 pll->div[i].name, input, 0, mult, i + 1);
1142 if (IS_ERR(clk)) {
1143 pr_err("%s: %s: register failed %ld\n",
1144 __func__, pll->div[i].name, PTR_ERR(clk));
1145 continue;
1146 }
1147
1148 pll->div[i].clk = clk;
1149 ret = clk_register_clkdev(clk, pll->div[i].name, NULL);
1150 if (ret != 0)
1151 pr_err("%s: %s: register to lookup table failed %ld\n",
1152 __func__, pll->div[i].name, PTR_ERR(clk));
1153
1154 }
1155}
1156
1157static void __init create_plls(struct clockgen *cg)
1158{
1159 int i;
1160
1161 for (i = 0; i < ARRAY_SIZE(cg->pll); i++)
1162 create_one_pll(cg, i);
1163}
1164
1165static void __init legacy_pll_init(struct device_node *np, int idx)
1166{
1167 struct clockgen_pll *pll;
1168 struct clk_onecell_data *onecell_data;
1169 struct clk **subclks;
1170 int count, rc;
1171
1172 legacy_init_clockgen(np);
1173
1174 pll = &clockgen.pll[idx];
1175 count = of_property_count_strings(np, "clock-output-names");
1176
1177 BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
1178 subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
1179 if (!subclks)
1180 return;
1181
1182 onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
1183 if (!onecell_data)
1184 goto err_clks;
1185
1186 if (count <= 3) {
1187 subclks[0] = pll->div[0].clk;
1188 subclks[1] = pll->div[1].clk;
1189 subclks[2] = pll->div[3].clk;
1190 } else {
1191 subclks[0] = pll->div[0].clk;
1192 subclks[1] = pll->div[1].clk;
1193 subclks[2] = pll->div[2].clk;
1194 subclks[3] = pll->div[3].clk;
1195 }
1196
1197 onecell_data->clks = subclks;
1198 onecell_data->clk_num = count;
1199
1200 rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
1201 if (rc) {
1202 pr_err("%s: Couldn't register clk provider for node %s: %d\n",
1203 __func__, np->name, rc);
1204 goto err_cell;
1205 }
1206
1207 return;
1208err_cell:
1209 kfree(onecell_data);
1210err_clks:
1211 kfree(subclks);
1212}
1213
1214/* Legacy node */
1215static void __init pltfrm_pll_init(struct device_node *np)
1216{
1217 legacy_pll_init(np, PLATFORM_PLL);
1218}
1219
1220/* Legacy node */
1221static void __init core_pll_init(struct device_node *np)
1222{
1223 struct resource res;
1224 int idx;
1225
1226 if (of_address_to_resource(np, 0, &res))
1227 return;
1228
1229 if ((res.start & 0xfff) == 0xc00) {
1230 /*
1231 * ls1021a devtree labels the platform PLL
1232 * with the core PLL compatible
1233 */
1234 pltfrm_pll_init(np);
1235 } else {
1236 idx = (res.start & 0xf0) >> 5;
1237 legacy_pll_init(np, CGA_PLL1 + idx);
1238 }
1239}
1240
1241static struct clk *clockgen_clk_get(struct of_phandle_args *clkspec, void *data)
1242{
1243 struct clockgen *cg = data;
1244 struct clk *clk;
1245 struct clockgen_pll *pll;
1246 u32 type, idx;
1247
1248 if (clkspec->args_count < 2) {
1249 pr_err("%s: insufficient phandle args\n", __func__);
1250 return ERR_PTR(-EINVAL);
1251 }
1252
1253 type = clkspec->args[0];
1254 idx = clkspec->args[1];
1255
1256 switch (type) {
1257 case 0:
1258 if (idx != 0)
1259 goto bad_args;
1260 clk = cg->sysclk;
1261 break;
1262 case 1:
1263 if (idx >= ARRAY_SIZE(cg->cmux))
1264 goto bad_args;
1265 clk = cg->cmux[idx];
1266 break;
1267 case 2:
1268 if (idx >= ARRAY_SIZE(cg->hwaccel))
1269 goto bad_args;
1270 clk = cg->hwaccel[idx];
1271 break;
1272 case 3:
1273 if (idx >= ARRAY_SIZE(cg->fman))
1274 goto bad_args;
1275 clk = cg->fman[idx];
1276 break;
1277 case 4:
1278 pll = &cg->pll[PLATFORM_PLL];
1279 if (idx >= ARRAY_SIZE(pll->div))
1280 goto bad_args;
1281 clk = pll->div[idx].clk;
1282 break;
1283 case 5:
1284 if (idx != 0)
1285 goto bad_args;
1286 clk = cg->coreclk;
1287 if (IS_ERR(clk))
1288 clk = NULL;
1289 break;
1290 default:
1291 goto bad_args;
1292 }
1293
1294 if (!clk)
1295 return ERR_PTR(-ENOENT);
1296 return clk;
1297
1298bad_args:
1299 pr_err("%s: Bad phandle args %u %u\n", __func__, type, idx);
1300 return ERR_PTR(-EINVAL);
1301}
1302
1303#ifdef CONFIG_PPC
1304#include <asm/mpc85xx.h>
1305
1306static const u32 a4510_svrs[] __initconst = {
1307 (SVR_P2040 << 8) | 0x10, /* P2040 1.0 */
1308 (SVR_P2040 << 8) | 0x11, /* P2040 1.1 */
1309 (SVR_P2041 << 8) | 0x10, /* P2041 1.0 */
1310 (SVR_P2041 << 8) | 0x11, /* P2041 1.1 */
1311 (SVR_P3041 << 8) | 0x10, /* P3041 1.0 */
1312 (SVR_P3041 << 8) | 0x11, /* P3041 1.1 */
1313 (SVR_P4040 << 8) | 0x20, /* P4040 2.0 */
1314 (SVR_P4080 << 8) | 0x20, /* P4080 2.0 */
1315 (SVR_P5010 << 8) | 0x10, /* P5010 1.0 */
1316 (SVR_P5010 << 8) | 0x20, /* P5010 2.0 */
1317 (SVR_P5020 << 8) | 0x10, /* P5020 1.0 */
1318 (SVR_P5021 << 8) | 0x10, /* P5021 1.0 */
1319 (SVR_P5040 << 8) | 0x10, /* P5040 1.0 */
1320};
1321
1322#define SVR_SECURITY 0x80000 /* The Security (E) bit */
1323
1324static bool __init has_erratum_a4510(void)
1325{
1326 u32 svr = mfspr(SPRN_SVR);
1327 int i;
1328
1329 svr &= ~SVR_SECURITY;
1330
1331 for (i = 0; i < ARRAY_SIZE(a4510_svrs); i++) {
1332 if (svr == a4510_svrs[i])
1333 return true;
1334 }
1335
1336 return false;
1337}
1338#else
1339static bool __init has_erratum_a4510(void)
1340{
1341 return false;
1342}
1343#endif
1344
1345static void __init clockgen_init(struct device_node *np)
1346{
1347 int i, ret;
1348 bool is_old_ls1021a = false;
1349
1350 /* May have already been called by a legacy probe */
1351 if (clockgen.node)
1352 return;
1353
1354 clockgen.node = np;
1355 clockgen.regs = of_iomap(np, 0);
1356 if (!clockgen.regs &&
1357 of_device_is_compatible(of_root, "fsl,ls1021a")) {
1358 /* Compatibility hack for old, broken device trees */
1359 clockgen.regs = ioremap(0x1ee1000, 0x1000);
1360 is_old_ls1021a = true;
1361 }
1362 if (!clockgen.regs) {
1363 pr_err("%s(): %s: of_iomap() failed\n", __func__, np->name);
1364 return;
1365 }
1366
1367 for (i = 0; i < ARRAY_SIZE(chipinfo); i++) {
1368 if (of_device_is_compatible(np, chipinfo[i].compat))
1369 break;
1370 if (is_old_ls1021a &&
1371 !strcmp(chipinfo[i].compat, "fsl,ls1021a-clockgen"))
1372 break;
1373 }
1374
1375 if (i == ARRAY_SIZE(chipinfo)) {
1376 pr_err("%s: unknown clockgen node %pOF\n", __func__, np);
1377 goto err;
1378 }
1379 clockgen.info = chipinfo[i];
1380
1381 if (clockgen.info.guts_compat) {
1382 struct device_node *guts;
1383
1384 guts = of_find_compatible_node(NULL, NULL,
1385 clockgen.info.guts_compat);
1386 if (guts) {
1387 clockgen.guts = of_iomap(guts, 0);
1388 if (!clockgen.guts) {
1389 pr_err("%s: Couldn't map %pOF regs\n", __func__,
1390 guts);
1391 }
1392 }
1393
1394 }
1395
1396 if (has_erratum_a4510())
1397 clockgen.info.flags |= CG_CMUX_GE_PLAT;
1398
1399 clockgen.sysclk = create_sysclk("cg-sysclk");
1400 clockgen.coreclk = create_coreclk("cg-coreclk");
1401 create_plls(&clockgen);
1402 create_muxes(&clockgen);
1403
1404 if (clockgen.info.init_periph)
1405 clockgen.info.init_periph(&clockgen);
1406
1407 ret = of_clk_add_provider(np, clockgen_clk_get, &clockgen);
1408 if (ret) {
1409 pr_err("%s: Couldn't register clk provider for node %s: %d\n",
1410 __func__, np->name, ret);
1411 }
1412
1413 return;
1414err:
1415 iounmap(clockgen.regs);
1416 clockgen.regs = NULL;
1417}
1418
1419CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
1420CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
1421CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init);
1422CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
1423CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
1424CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init);
1425CLK_OF_DECLARE(qoriq_clockgen_ls1088a, "fsl,ls1088a-clockgen", clockgen_init);
1426CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
1427
1428/* Legacy nodes */
1429CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init);
1430CLK_OF_DECLARE(qoriq_sysclk_2, "fsl,qoriq-sysclk-2.0", sysclk_init);
1431CLK_OF_DECLARE(qoriq_core_pll_1, "fsl,qoriq-core-pll-1.0", core_pll_init);
1432CLK_OF_DECLARE(qoriq_core_pll_2, "fsl,qoriq-core-pll-2.0", core_pll_init);
1433CLK_OF_DECLARE(qoriq_core_mux_1, "fsl,qoriq-core-mux-1.0", core_mux_init);
1434CLK_OF_DECLARE(qoriq_core_mux_2, "fsl,qoriq-core-mux-2.0", core_mux_init);
1435CLK_OF_DECLARE(qoriq_pltfrm_pll_1, "fsl,qoriq-platform-pll-1.0", pltfrm_pll_init);
1436CLK_OF_DECLARE(qoriq_pltfrm_pll_2, "fsl,qoriq-platform-pll-2.0", pltfrm_pll_init);