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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
6 *
7 * Simple multiplexer clock implementation
8 */
9
10#include <linux/clk-provider.h>
11#include <linux/device.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/io.h>
15#include <linux/err.h>
16
17/*
18 * DOC: basic adjustable multiplexer clock that cannot gate
19 *
20 * Traits of this clock:
21 * prepare - clk_prepare only ensures that parents are prepared
22 * enable - clk_enable only ensures that parents are enabled
23 * rate - rate is only affected by parent switching. No clk_set_rate support
24 * parent - parent is adjustable through clk_set_parent
25 */
26
27static inline u32 clk_mux_readl(struct clk_mux *mux)
28{
29 if (mux->flags & CLK_MUX_BIG_ENDIAN)
30 return ioread32be(mux->reg);
31
32 return readl(mux->reg);
33}
34
35static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
36{
37 if (mux->flags & CLK_MUX_BIG_ENDIAN)
38 iowrite32be(val, mux->reg);
39 else
40 writel(val, mux->reg);
41}
42
43int clk_mux_val_to_index(struct clk_hw *hw, const u32 *table, unsigned int flags,
44 unsigned int val)
45{
46 int num_parents = clk_hw_get_num_parents(hw);
47
48 if (table) {
49 int i;
50
51 for (i = 0; i < num_parents; i++)
52 if (table[i] == val)
53 return i;
54 return -EINVAL;
55 }
56
57 if (val && (flags & CLK_MUX_INDEX_BIT))
58 val = ffs(val) - 1;
59
60 if (val && (flags & CLK_MUX_INDEX_ONE))
61 val--;
62
63 if (val >= num_parents)
64 return -EINVAL;
65
66 return val;
67}
68EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
69
70unsigned int clk_mux_index_to_val(const u32 *table, unsigned int flags, u8 index)
71{
72 unsigned int val = index;
73
74 if (table) {
75 val = table[index];
76 } else {
77 if (flags & CLK_MUX_INDEX_BIT)
78 val = 1 << index;
79
80 if (flags & CLK_MUX_INDEX_ONE)
81 val++;
82 }
83
84 return val;
85}
86EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
87
88static u8 clk_mux_get_parent(struct clk_hw *hw)
89{
90 struct clk_mux *mux = to_clk_mux(hw);
91 u32 val;
92
93 val = clk_mux_readl(mux) >> mux->shift;
94 val &= mux->mask;
95
96 return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
97}
98
99static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
100{
101 struct clk_mux *mux = to_clk_mux(hw);
102 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
103 unsigned long flags = 0;
104 u32 reg;
105
106 if (mux->lock)
107 spin_lock_irqsave(mux->lock, flags);
108 else
109 __acquire(mux->lock);
110
111 if (mux->flags & CLK_MUX_HIWORD_MASK) {
112 reg = mux->mask << (mux->shift + 16);
113 } else {
114 reg = clk_mux_readl(mux);
115 reg &= ~(mux->mask << mux->shift);
116 }
117 val = val << mux->shift;
118 reg |= val;
119 clk_mux_writel(mux, reg);
120
121 if (mux->lock)
122 spin_unlock_irqrestore(mux->lock, flags);
123 else
124 __release(mux->lock);
125
126 return 0;
127}
128
129static int clk_mux_determine_rate(struct clk_hw *hw,
130 struct clk_rate_request *req)
131{
132 struct clk_mux *mux = to_clk_mux(hw);
133
134 return clk_mux_determine_rate_flags(hw, req, mux->flags);
135}
136
137const struct clk_ops clk_mux_ops = {
138 .get_parent = clk_mux_get_parent,
139 .set_parent = clk_mux_set_parent,
140 .determine_rate = clk_mux_determine_rate,
141};
142EXPORT_SYMBOL_GPL(clk_mux_ops);
143
144const struct clk_ops clk_mux_ro_ops = {
145 .get_parent = clk_mux_get_parent,
146};
147EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
148
149struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
150 const char *name, u8 num_parents,
151 const char * const *parent_names,
152 const struct clk_hw **parent_hws,
153 const struct clk_parent_data *parent_data,
154 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
155 u8 clk_mux_flags, const u32 *table, spinlock_t *lock)
156{
157 struct clk_mux *mux;
158 struct clk_hw *hw;
159 struct clk_init_data init = {};
160 int ret = -EINVAL;
161
162 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
163 u8 width = fls(mask) - ffs(mask) + 1;
164
165 if (width + shift > 16) {
166 pr_err("mux value exceeds LOWORD field\n");
167 return ERR_PTR(-EINVAL);
168 }
169 }
170
171 /* allocate the mux */
172 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
173 if (!mux)
174 return ERR_PTR(-ENOMEM);
175
176 init.name = name;
177 if (clk_mux_flags & CLK_MUX_READ_ONLY)
178 init.ops = &clk_mux_ro_ops;
179 else
180 init.ops = &clk_mux_ops;
181 init.flags = flags;
182 init.parent_names = parent_names;
183 init.parent_data = parent_data;
184 init.parent_hws = parent_hws;
185 init.num_parents = num_parents;
186
187 /* struct clk_mux assignments */
188 mux->reg = reg;
189 mux->shift = shift;
190 mux->mask = mask;
191 mux->flags = clk_mux_flags;
192 mux->lock = lock;
193 mux->table = table;
194 mux->hw.init = &init;
195
196 hw = &mux->hw;
197 if (dev || !np)
198 ret = clk_hw_register(dev, hw);
199 else if (np)
200 ret = of_clk_hw_register(np, hw);
201 if (ret) {
202 kfree(mux);
203 hw = ERR_PTR(ret);
204 }
205
206 return hw;
207}
208EXPORT_SYMBOL_GPL(__clk_hw_register_mux);
209
210static void devm_clk_hw_release_mux(struct device *dev, void *res)
211{
212 clk_hw_unregister_mux(*(struct clk_hw **)res);
213}
214
215struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
216 const char *name, u8 num_parents,
217 const char * const *parent_names,
218 const struct clk_hw **parent_hws,
219 const struct clk_parent_data *parent_data,
220 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
221 u8 clk_mux_flags, const u32 *table, spinlock_t *lock)
222{
223 struct clk_hw **ptr, *hw;
224
225 ptr = devres_alloc(devm_clk_hw_release_mux, sizeof(*ptr), GFP_KERNEL);
226 if (!ptr)
227 return ERR_PTR(-ENOMEM);
228
229 hw = __clk_hw_register_mux(dev, np, name, num_parents, parent_names, parent_hws,
230 parent_data, flags, reg, shift, mask,
231 clk_mux_flags, table, lock);
232
233 if (!IS_ERR(hw)) {
234 *ptr = hw;
235 devres_add(dev, ptr);
236 } else {
237 devres_free(ptr);
238 }
239
240 return hw;
241}
242EXPORT_SYMBOL_GPL(__devm_clk_hw_register_mux);
243
244struct clk *clk_register_mux_table(struct device *dev, const char *name,
245 const char * const *parent_names, u8 num_parents,
246 unsigned long flags, void __iomem *reg, u8 shift, u32 mask,
247 u8 clk_mux_flags, const u32 *table, spinlock_t *lock)
248{
249 struct clk_hw *hw;
250
251 hw = clk_hw_register_mux_table(dev, name, parent_names,
252 num_parents, flags, reg, shift, mask,
253 clk_mux_flags, table, lock);
254 if (IS_ERR(hw))
255 return ERR_CAST(hw);
256 return hw->clk;
257}
258EXPORT_SYMBOL_GPL(clk_register_mux_table);
259
260void clk_unregister_mux(struct clk *clk)
261{
262 struct clk_mux *mux;
263 struct clk_hw *hw;
264
265 hw = __clk_get_hw(clk);
266 if (!hw)
267 return;
268
269 mux = to_clk_mux(hw);
270
271 clk_unregister(clk);
272 kfree(mux);
273}
274EXPORT_SYMBOL_GPL(clk_unregister_mux);
275
276void clk_hw_unregister_mux(struct clk_hw *hw)
277{
278 struct clk_mux *mux;
279
280 mux = to_clk_mux(hw);
281
282 clk_hw_unregister(hw);
283 kfree(mux);
284}
285EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);
1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 * Copyright (C) 2011 Richard Zhao, Linaro <richard.zhao@linaro.org>
4 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Simple multiplexer clock implementation
11 */
12
13#include <linux/clk-provider.h>
14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/io.h>
17#include <linux/err.h>
18
19/*
20 * DOC: basic adjustable multiplexer clock that cannot gate
21 *
22 * Traits of this clock:
23 * prepare - clk_prepare only ensures that parents are prepared
24 * enable - clk_enable only ensures that parents are enabled
25 * rate - rate is only affected by parent switching. No clk_set_rate support
26 * parent - parent is adjustable through clk_set_parent
27 */
28
29int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,
30 unsigned int val)
31{
32 int num_parents = clk_hw_get_num_parents(hw);
33
34 if (table) {
35 int i;
36
37 for (i = 0; i < num_parents; i++)
38 if (table[i] == val)
39 return i;
40 return -EINVAL;
41 }
42
43 if (val && (flags & CLK_MUX_INDEX_BIT))
44 val = ffs(val) - 1;
45
46 if (val && (flags & CLK_MUX_INDEX_ONE))
47 val--;
48
49 if (val >= num_parents)
50 return -EINVAL;
51
52 return val;
53}
54EXPORT_SYMBOL_GPL(clk_mux_val_to_index);
55
56unsigned int clk_mux_index_to_val(u32 *table, unsigned int flags, u8 index)
57{
58 unsigned int val = index;
59
60 if (table) {
61 val = table[index];
62 } else {
63 if (flags & CLK_MUX_INDEX_BIT)
64 val = 1 << index;
65
66 if (flags & CLK_MUX_INDEX_ONE)
67 val++;
68 }
69
70 return val;
71}
72EXPORT_SYMBOL_GPL(clk_mux_index_to_val);
73
74static u8 clk_mux_get_parent(struct clk_hw *hw)
75{
76 struct clk_mux *mux = to_clk_mux(hw);
77 u32 val;
78
79 val = clk_readl(mux->reg) >> mux->shift;
80 val &= mux->mask;
81
82 return clk_mux_val_to_index(hw, mux->table, mux->flags, val);
83}
84
85static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
86{
87 struct clk_mux *mux = to_clk_mux(hw);
88 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
89 unsigned long flags = 0;
90 u32 reg;
91
92 if (mux->lock)
93 spin_lock_irqsave(mux->lock, flags);
94 else
95 __acquire(mux->lock);
96
97 if (mux->flags & CLK_MUX_HIWORD_MASK) {
98 reg = mux->mask << (mux->shift + 16);
99 } else {
100 reg = clk_readl(mux->reg);
101 reg &= ~(mux->mask << mux->shift);
102 }
103 val = val << mux->shift;
104 reg |= val;
105 clk_writel(reg, mux->reg);
106
107 if (mux->lock)
108 spin_unlock_irqrestore(mux->lock, flags);
109 else
110 __release(mux->lock);
111
112 return 0;
113}
114
115static int clk_mux_determine_rate(struct clk_hw *hw,
116 struct clk_rate_request *req)
117{
118 struct clk_mux *mux = to_clk_mux(hw);
119
120 return clk_mux_determine_rate_flags(hw, req, mux->flags);
121}
122
123const struct clk_ops clk_mux_ops = {
124 .get_parent = clk_mux_get_parent,
125 .set_parent = clk_mux_set_parent,
126 .determine_rate = clk_mux_determine_rate,
127};
128EXPORT_SYMBOL_GPL(clk_mux_ops);
129
130const struct clk_ops clk_mux_ro_ops = {
131 .get_parent = clk_mux_get_parent,
132};
133EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
134
135struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
136 const char * const *parent_names, u8 num_parents,
137 unsigned long flags,
138 void __iomem *reg, u8 shift, u32 mask,
139 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
140{
141 struct clk_mux *mux;
142 struct clk_hw *hw;
143 struct clk_init_data init;
144 u8 width = 0;
145 int ret;
146
147 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
148 width = fls(mask) - ffs(mask) + 1;
149 if (width + shift > 16) {
150 pr_err("mux value exceeds LOWORD field\n");
151 return ERR_PTR(-EINVAL);
152 }
153 }
154
155 /* allocate the mux */
156 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
157 if (!mux)
158 return ERR_PTR(-ENOMEM);
159
160 init.name = name;
161 if (clk_mux_flags & CLK_MUX_READ_ONLY)
162 init.ops = &clk_mux_ro_ops;
163 else
164 init.ops = &clk_mux_ops;
165 init.flags = flags | CLK_IS_BASIC;
166 init.parent_names = parent_names;
167 init.num_parents = num_parents;
168
169 /* struct clk_mux assignments */
170 mux->reg = reg;
171 mux->shift = shift;
172 mux->mask = mask;
173 mux->flags = clk_mux_flags;
174 mux->lock = lock;
175 mux->table = table;
176 mux->hw.init = &init;
177
178 hw = &mux->hw;
179 ret = clk_hw_register(dev, hw);
180 if (ret) {
181 kfree(mux);
182 hw = ERR_PTR(ret);
183 }
184
185 return hw;
186}
187EXPORT_SYMBOL_GPL(clk_hw_register_mux_table);
188
189struct clk *clk_register_mux_table(struct device *dev, const char *name,
190 const char * const *parent_names, u8 num_parents,
191 unsigned long flags,
192 void __iomem *reg, u8 shift, u32 mask,
193 u8 clk_mux_flags, u32 *table, spinlock_t *lock)
194{
195 struct clk_hw *hw;
196
197 hw = clk_hw_register_mux_table(dev, name, parent_names, num_parents,
198 flags, reg, shift, mask, clk_mux_flags,
199 table, lock);
200 if (IS_ERR(hw))
201 return ERR_CAST(hw);
202 return hw->clk;
203}
204EXPORT_SYMBOL_GPL(clk_register_mux_table);
205
206struct clk *clk_register_mux(struct device *dev, const char *name,
207 const char * const *parent_names, u8 num_parents,
208 unsigned long flags,
209 void __iomem *reg, u8 shift, u8 width,
210 u8 clk_mux_flags, spinlock_t *lock)
211{
212 u32 mask = BIT(width) - 1;
213
214 return clk_register_mux_table(dev, name, parent_names, num_parents,
215 flags, reg, shift, mask, clk_mux_flags,
216 NULL, lock);
217}
218EXPORT_SYMBOL_GPL(clk_register_mux);
219
220struct clk_hw *clk_hw_register_mux(struct device *dev, const char *name,
221 const char * const *parent_names, u8 num_parents,
222 unsigned long flags,
223 void __iomem *reg, u8 shift, u8 width,
224 u8 clk_mux_flags, spinlock_t *lock)
225{
226 u32 mask = BIT(width) - 1;
227
228 return clk_hw_register_mux_table(dev, name, parent_names, num_parents,
229 flags, reg, shift, mask, clk_mux_flags,
230 NULL, lock);
231}
232EXPORT_SYMBOL_GPL(clk_hw_register_mux);
233
234void clk_unregister_mux(struct clk *clk)
235{
236 struct clk_mux *mux;
237 struct clk_hw *hw;
238
239 hw = __clk_get_hw(clk);
240 if (!hw)
241 return;
242
243 mux = to_clk_mux(hw);
244
245 clk_unregister(clk);
246 kfree(mux);
247}
248EXPORT_SYMBOL_GPL(clk_unregister_mux);
249
250void clk_hw_unregister_mux(struct clk_hw *hw)
251{
252 struct clk_mux *mux;
253
254 mux = to_clk_mux(hw);
255
256 clk_hw_unregister(hw);
257 kfree(mux);
258}
259EXPORT_SYMBOL_GPL(clk_hw_unregister_mux);