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1/*
2 * Copyright (C) 2016 NXP Semiconductors.
3 * Author: Fabio Estevam <fabio.estevam@nxp.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
29 * conditions:
30 *
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
33 *
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44/dts-v1/;
45
46#include <dt-bindings/input/input.h>
47#include "imx7s.dtsi"
48
49/ {
50 model = "Warp i.MX7 Board";
51 compatible = "warp,imx7s-warp", "fsl,imx7s";
52
53 memory@80000000 {
54 reg = <0x80000000 0x20000000>;
55 };
56
57 gpio-keys {
58 compatible = "gpio-keys";
59 pinctrl-0 = <&pinctrl_gpio>;
60 autorepeat;
61
62 back {
63 label = "Back";
64 gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
65 linux,code = <KEY_BACK>;
66 wakeup-source;
67 };
68 };
69
70 reg_brcm: regulator-brcm {
71 compatible = "regulator-fixed";
72 enable-active-high;
73 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
74 pinctrl-names = "default";
75 pinctrl-0 = <&pinctrl_brcm_reg>;
76 regulator-name = "brcm_reg";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 startup-delay-us = <200000>;
80 };
81
82 reg_bt: regulator-bt {
83 compatible = "regulator-fixed";
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_bt_reg>;
86 enable-active-high;
87 gpio = <&gpio5 17 GPIO_ACTIVE_HIGH>;
88 regulator-name = "bt_reg";
89 regulator-min-microvolt = <3300000>;
90 regulator-max-microvolt = <3300000>;
91 regulator-always-on;
92 };
93
94 sound {
95 compatible = "simple-audio-card";
96 simple-audio-card,name = "imx7-sgtl5000";
97 simple-audio-card,format = "i2s";
98 simple-audio-card,bitclock-master = <&dailink_master>;
99 simple-audio-card,frame-master = <&dailink_master>;
100 simple-audio-card,cpu {
101 sound-dai = <&sai1>;
102 };
103
104 dailink_master: simple-audio-card,codec {
105 sound-dai = <&codec>;
106 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
107 };
108 };
109};
110
111&clks {
112 assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
113 assigned-clock-rates = <884736000>;
114};
115
116&cpu0 {
117 arm-supply = <&sw1a_reg>;
118};
119
120&i2c1 {
121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_i2c1>;
123 status = "okay";
124
125 pmic: pfuze3000@8 {
126 compatible = "fsl,pfuze3000";
127 reg = <0x08>;
128
129 regulators {
130 sw1a_reg: sw1a {
131 regulator-min-microvolt = <700000>;
132 regulator-max-microvolt = <1475000>;
133 regulator-boot-on;
134 regulator-always-on;
135 regulator-ramp-delay = <6250>;
136 };
137
138 /* use sw1c_reg to align with pfuze100/pfuze200 */
139 sw1c_reg: sw1b {
140 regulator-min-microvolt = <700000>;
141 regulator-max-microvolt = <1475000>;
142 regulator-boot-on;
143 regulator-always-on;
144 regulator-ramp-delay = <6250>;
145 };
146
147 sw2_reg: sw2 {
148 regulator-min-microvolt = <1500000>;
149 regulator-max-microvolt = <1850000>;
150 regulator-boot-on;
151 regulator-always-on;
152 };
153
154 sw3a_reg: sw3 {
155 regulator-min-microvolt = <900000>;
156 regulator-max-microvolt = <1650000>;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 swbst_reg: swbst {
162 regulator-min-microvolt = <5000000>;
163 regulator-max-microvolt = <5150000>;
164 };
165
166 snvs_reg: vsnvs {
167 regulator-min-microvolt = <1000000>;
168 regulator-max-microvolt = <3000000>;
169 regulator-boot-on;
170 regulator-always-on;
171 };
172
173 vref_reg: vrefddr {
174 regulator-boot-on;
175 regulator-always-on;
176 };
177
178 vgen1_reg: vldo1 {
179 regulator-min-microvolt = <1800000>;
180 regulator-max-microvolt = <3300000>;
181 regulator-always-on;
182 };
183
184 vgen2_reg: vldo2 {
185 regulator-min-microvolt = <800000>;
186 regulator-max-microvolt = <1550000>;
187 };
188
189 vgen3_reg: vccsd {
190 regulator-min-microvolt = <2850000>;
191 regulator-max-microvolt = <3300000>;
192 regulator-always-on;
193 };
194
195 vgen4_reg: v33 {
196 regulator-min-microvolt = <2850000>;
197 regulator-max-microvolt = <3300000>;
198 regulator-always-on;
199 };
200
201 vgen5_reg: vldo3 {
202 regulator-min-microvolt = <1800000>;
203 regulator-max-microvolt = <3300000>;
204 regulator-always-on;
205 };
206
207 vgen6_reg: vldo4 {
208 regulator-min-microvolt = <1800000>;
209 regulator-max-microvolt = <3300000>;
210 regulator-always-on;
211 };
212 };
213 };
214};
215
216&i2c2 {
217 clock-frequency = <100000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_i2c2>;
220 status = "okay";
221};
222
223&i2c4 {
224 clock-frequency = <100000>;
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_i2c4>;
227 status = "okay";
228
229 codec: sgtl5000@a {
230 #sound-dai-cells = <0>;
231 reg = <0x0a>;
232 compatible = "fsl,sgtl5000";
233 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&pinctrl_sai1_mclk>;
236 VDDA-supply = <&vgen4_reg>;
237 VDDIO-supply = <&vgen4_reg>;
238 VDDD-supply = <&vgen2_reg>;
239 };
240
241 mpl3115@60 {
242 compatible = "fsl,mpl3115";
243 reg = <0x60>;
244 };
245};
246
247&sai1 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_sai1>;
250 assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
251 <&clks IMX7D_SAI1_ROOT_CLK>;
252 assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
253 assigned-clock-rates = <0>, <36864000>;
254 status = "okay";
255};
256
257&uart1 {
258 pinctrl-names = "default";
259 pinctrl-0 = <&pinctrl_uart1>;
260 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
261 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
262 status = "okay";
263};
264
265&uart3 {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_uart3>;
268 assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
269 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
270 uart-has-rtscts;
271 status = "okay";
272};
273
274&uart6 {
275 pinctrl-names = "default";
276 pinctrl-0 = <&pinctrl_uart6>;
277 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
278 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
279 fsl,dte-mode;
280 status = "okay";
281};
282
283&usbotg1 {
284 dr_mode = "peripheral";
285 status = "okay";
286};
287
288&usdhc1 {
289 pinctrl-names = "default";
290 pinctrl-0 = <&pinctrl_usdhc1>;
291 bus-width = <4>;
292 keep-power-in-suspend;
293 no-1-8-v;
294 non-removable;
295 vmmc-supply = <®_brcm>;
296 status = "okay";
297};
298
299&usdhc3 {
300 pinctrl-names = "default", "state_100mhz", "state_200mhz";
301 pinctrl-0 = <&pinctrl_usdhc3>;
302 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
303 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
304 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
305 assigned-clock-rates = <400000000>;
306 bus-width = <8>;
307 no-1-8-v;
308 fsl,tuning-step = <2>;
309 non-removable;
310 status = "okay";
311};
312
313&wdog1 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_wdog>;
316 fsl,ext-reset-output;
317 status = "okay";
318};
319
320&iomuxc {
321 pinctrl_brcm_reg: brcmreggrp {
322 fsl,pins = <
323 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
324 >;
325 };
326
327 pinctrl_bt_reg: btreggrp {
328 fsl,pins = <
329 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
330 >;
331 };
332
333 pinctrl_gpio: gpiogrp {
334 fsl,pins = <
335 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
336 >;
337 };
338
339 pinctrl_i2c1: i2c1grp {
340 fsl,pins = <
341 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
342 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
343 >;
344 };
345
346 pinctrl_i2c2: i2c2grp {
347 fsl,pins = <
348 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
349 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
350 >;
351 };
352
353 pinctrl_i2c4: i2c4grp {
354 fsl,pins = <
355 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
356 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
357 >;
358 };
359
360 pinctrl_sai1: sai1grp {
361 fsl,pins = <
362 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
363 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
364 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
365 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
366 >;
367 };
368
369 pinctrl_sai1_mclk: sai1mclkgrp {
370 fsl,pins = <
371 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
372 >;
373 };
374
375 pinctrl_uart1: uart1grp {
376 fsl,pins = <
377 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
378 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
379 >;
380 };
381
382 pinctrl_uart3: uart3grp {
383 fsl,pins = <
384 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
385 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
386 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
387 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
388 >;
389 };
390
391 pinctrl_uart6: uart6grp {
392 fsl,pins = <
393 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
394 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
395 >;
396 };
397
398 pinctrl_usdhc1: usdhc1grp {
399 fsl,pins = <
400 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
401 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
402 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
403 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
404 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
405 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
406 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
407 >;
408 };
409
410 pinctrl_usdhc3: usdhc3grp {
411 fsl,pins = <
412 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
413 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
414 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
415 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
416 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
417 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
418 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
419 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
420 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
421 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
422 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
423 >;
424 };
425
426 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
427 fsl,pins = <
428 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
429 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
430 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
431 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
432 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
433 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
434 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
435 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
436 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
437 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
438 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
439 >;
440 };
441
442 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
443 fsl,pins = <
444 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
445 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
446 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
447 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
448 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
449 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
450 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
451 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
452 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
453 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
454 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
455 >;
456 };
457};
458
459&iomuxc_lpsr {
460 pinctrl_wdog: wdoggrp {
461 fsl,pins = <
462 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
463 >;
464 };
465};