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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
   5 * Copyright (c) 2023, Linaro Limited
   6 */
   7
   8#include <linux/module.h>
   9#include <linux/slab.h>
  10#include <linux/platform_device.h>
  11#include <linux/device.h>
  12#include <linux/delay.h>
  13#include <linux/gpio/consumer.h>
  14#include <linux/kernel.h>
  15#include <linux/pm_runtime.h>
  16#include <linux/component.h>
  17#include <sound/tlv.h>
  18#include <linux/of_gpio.h>
  19#include <linux/of_graph.h>
  20#include <linux/of.h>
  21#include <sound/jack.h>
  22#include <sound/pcm.h>
  23#include <sound/pcm_params.h>
  24#include <linux/regmap.h>
  25#include <sound/soc.h>
  26#include <sound/soc-dapm.h>
  27#include <linux/regulator/consumer.h>
  28#include <linux/usb/typec_mux.h>
  29#include <linux/usb/typec_altmode.h>
  30
  31#include "wcd-clsh-v2.h"
  32#include "wcd-mbhc-v2.h"
  33#include "wcd939x.h"
  34
  35#define WCD939X_MAX_MICBIAS		(4)
  36#define WCD939X_MAX_SUPPLY		(4)
  37#define WCD939X_MBHC_MAX_BUTTONS	(8)
  38#define TX_ADC_MAX			(4)
  39#define WCD_MBHC_HS_V_MAX		1600
  40
  41enum {
  42	WCD939X_VERSION_1_0 = 0,
  43	WCD939X_VERSION_1_1,
  44	WCD939X_VERSION_2_0,
  45};
  46
  47#define WCD939X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  48			    SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  49			    SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\
  50			    SNDRV_PCM_RATE_384000)
  51/* Fractional Rates */
  52#define WCD939X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  53				 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_352800)
  54#define WCD939X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
  55			 SNDRV_PCM_FMTBIT_S24_LE |\
  56			 SNDRV_PCM_FMTBIT_S24_3LE |\
  57			 SNDRV_PCM_FMTBIT_S32_LE)
  58
  59/* Convert from vout ctl to micbias voltage in mV */
  60#define WCD_VOUT_CTL_TO_MICB(v)		(1000 + (v) * 50)
  61#define SWR_CLK_RATE_0P6MHZ		(600000)
  62#define SWR_CLK_RATE_1P2MHZ		(1200000)
  63#define SWR_CLK_RATE_2P4MHZ		(2400000)
  64#define SWR_CLK_RATE_4P8MHZ		(4800000)
  65#define SWR_CLK_RATE_9P6MHZ		(9600000)
  66#define SWR_CLK_RATE_11P2896MHZ		(1128960)
  67
  68#define ADC_MODE_VAL_HIFI		0x01
  69#define ADC_MODE_VAL_LO_HIF		0x02
  70#define ADC_MODE_VAL_NORMAL		0x03
  71#define ADC_MODE_VAL_LP			0x05
  72#define ADC_MODE_VAL_ULP1		0x09
  73#define ADC_MODE_VAL_ULP2		0x0B
  74
  75/* Z value defined in milliohm */
  76#define WCD939X_ZDET_VAL_32		(32000)
  77#define WCD939X_ZDET_VAL_400		(400000)
  78#define WCD939X_ZDET_VAL_1200		(1200000)
  79#define WCD939X_ZDET_VAL_100K		(100000000)
  80
  81/* Z floating defined in ohms */
  82#define WCD939X_ZDET_FLOATING_IMPEDANCE	(0x0FFFFFFE)
  83#define WCD939X_ZDET_NUM_MEASUREMENTS	(900)
  84#define WCD939X_MBHC_GET_C1(c)		(((c) & 0xC000) >> 14)
  85#define WCD939X_MBHC_GET_X1(x)		((x) & 0x3FFF)
  86
  87/* Z value compared in milliOhm */
  88#define WCD939X_ANA_MBHC_ZDET_CONST	(1018 * 1024)
  89
  90enum {
  91	WCD9390 = 0,
  92	WCD9395 = 5,
  93};
  94
  95enum {
  96	/* INTR_CTRL_INT_MASK_0 */
  97	WCD939X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
  98	WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET,
  99	WCD939X_IRQ_MBHC_ELECT_INS_REM_DET,
 100	WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
 101	WCD939X_IRQ_MBHC_SW_DET,
 102	WCD939X_IRQ_HPHR_OCP_INT,
 103	WCD939X_IRQ_HPHR_CNP_INT,
 104	WCD939X_IRQ_HPHL_OCP_INT,
 105
 106	/* INTR_CTRL_INT_MASK_1 */
 107	WCD939X_IRQ_HPHL_CNP_INT,
 108	WCD939X_IRQ_EAR_CNP_INT,
 109	WCD939X_IRQ_EAR_SCD_INT,
 110	WCD939X_IRQ_HPHL_PDM_WD_INT,
 111	WCD939X_IRQ_HPHR_PDM_WD_INT,
 112	WCD939X_IRQ_EAR_PDM_WD_INT,
 113
 114	/* INTR_CTRL_INT_MASK_2 */
 115	WCD939X_IRQ_MBHC_MOISTURE_INT,
 116	WCD939X_IRQ_HPHL_SURGE_DET_INT,
 117	WCD939X_IRQ_HPHR_SURGE_DET_INT,
 118	WCD939X_NUM_IRQS,
 119};
 120
 121enum {
 122	MICB_BIAS_DISABLE = 0,
 123	MICB_BIAS_ENABLE,
 124	MICB_BIAS_PULL_UP,
 125	MICB_BIAS_PULL_DOWN,
 126};
 127
 128enum {
 129	WCD_ADC1 = 0,
 130	WCD_ADC2,
 131	WCD_ADC3,
 132	WCD_ADC4,
 133	HPH_PA_DELAY,
 134};
 135
 136enum {
 137	ADC_MODE_INVALID = 0,
 138	ADC_MODE_HIFI,
 139	ADC_MODE_LO_HIF,
 140	ADC_MODE_NORMAL,
 141	ADC_MODE_LP,
 142	ADC_MODE_ULP1,
 143	ADC_MODE_ULP2,
 144};
 145
 146enum {
 147	AIF1_PB = 0,
 148	AIF1_CAP,
 149	NUM_CODEC_DAIS,
 150};
 151
 152static u8 tx_mode_bit[] = {
 153	[ADC_MODE_INVALID] = 0x00,
 154	[ADC_MODE_HIFI] = 0x01,
 155	[ADC_MODE_LO_HIF] = 0x02,
 156	[ADC_MODE_NORMAL] = 0x04,
 157	[ADC_MODE_LP] = 0x08,
 158	[ADC_MODE_ULP1] = 0x10,
 159	[ADC_MODE_ULP2] = 0x20,
 160};
 161
 162struct zdet_param {
 163	u16 ldo_ctl;
 164	u16 noff;
 165	u16 nshift;
 166	u16 btn5;
 167	u16 btn6;
 168	u16 btn7;
 169};
 170
 171struct wcd939x_priv {
 172	struct sdw_slave *tx_sdw_dev;
 173	struct wcd939x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
 174	struct device *txdev;
 175	struct device *rxdev;
 176	struct device_node *rxnode, *txnode;
 177	struct regmap *regmap;
 178	struct snd_soc_component *component;
 179	/* micb setup lock */
 180	struct mutex micb_lock;
 181	/* typec handling */
 182	bool typec_analog_mux;
 183#if IS_ENABLED(CONFIG_TYPEC)
 184	enum typec_orientation typec_orientation;
 185	unsigned long typec_mode;
 186	struct typec_switch *typec_switch;
 187#endif /* CONFIG_TYPEC */
 188	/* mbhc module */
 189	struct wcd_mbhc *wcd_mbhc;
 190	struct wcd_mbhc_config mbhc_cfg;
 191	struct wcd_mbhc_intr intr_ids;
 192	struct wcd_clsh_ctrl *clsh_info;
 193	struct irq_domain *virq;
 194	struct regmap_irq_chip *wcd_regmap_irq_chip;
 195	struct regmap_irq_chip_data *irq_chip;
 196	struct regulator_bulk_data supplies[WCD939X_MAX_SUPPLY];
 197	struct snd_soc_jack *jack;
 198	unsigned long status_mask;
 199	s32 micb_ref[WCD939X_MAX_MICBIAS];
 200	s32 pullup_ref[WCD939X_MAX_MICBIAS];
 201	u32 hph_mode;
 202	u32 tx_mode[TX_ADC_MAX];
 203	int variant;
 204	int reset_gpio;
 205	u32 micb1_mv;
 206	u32 micb2_mv;
 207	u32 micb3_mv;
 208	u32 micb4_mv;
 209	int hphr_pdm_wd_int;
 210	int hphl_pdm_wd_int;
 211	int ear_pdm_wd_int;
 212	bool comp1_enable;
 213	bool comp2_enable;
 214	bool ldoh;
 215};
 216
 217static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
 218static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
 219static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
 220
 221static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
 222	WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD939X_ANA_MBHC_MECH, 0x80),
 223	WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD939X_ANA_MBHC_MECH, 0x40),
 224	WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD939X_ANA_MBHC_MECH, 0x20),
 225	WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
 226	WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD939X_ANA_MBHC_ELECT, 0x08),
 227	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT, 0x1F),
 228	WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD939X_ANA_MBHC_MECH, 0x04),
 229	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x10),
 230	WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD939X_ANA_MBHC_MECH, 0x08),
 231	WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD939X_ANA_MBHC_MECH, 0x01),
 232	WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD939X_ANA_MBHC_ELECT, 0x06),
 233	WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD939X_ANA_MBHC_ELECT, 0x80),
 234	WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD939X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
 235	WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD939X_MBHC_NEW_CTL_1, 0x03),
 236	WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD939X_MBHC_NEW_CTL_2, 0x03),
 237	WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x08),
 238	WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
 239	WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x20),
 240	WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x80),
 241	WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x40),
 242	WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD939X_HPH_OCP_CTL, 0x10),
 243	WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0x07),
 244	WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD939X_ANA_MBHC_ELECT, 0x70),
 245	WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD939X_ANA_MBHC_RESULT_3, 0xFF),
 246	WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD939X_ANA_MICB2, 0xC0),
 247	WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD939X_HPH_CNP_WG_TIME, 0xFF),
 248	WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD939X_ANA_HPH, 0x40),
 249	WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD939X_ANA_HPH, 0x80),
 250	WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD939X_ANA_HPH, 0xC0),
 251	WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD939X_ANA_MBHC_RESULT_3, 0x10),
 252	WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD939X_MBHC_CTL_BCS, 0x02),
 253	WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x01),
 254	WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD939X_MBHC_NEW_CTL_2, 0x70),
 255	WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD939X_MBHC_NEW_FSM_STATUS, 0x20),
 256	WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD939X_HPH_PA_CTL2, 0x40),
 257	WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD939X_HPH_PA_CTL2, 0x10),
 258	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD939X_HPH_L_TEST, 0x01),
 259	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD939X_HPH_R_TEST, 0x01),
 260	WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x80),
 261	WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD939X_DIGITAL_INTR_STATUS_0, 0x20),
 262	WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD939X_MBHC_NEW_CTL_1, 0x08),
 263	WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD939X_MBHC_NEW_FSM_STATUS, 0x40),
 264	WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD939X_MBHC_NEW_FSM_STATUS, 0x80),
 265	WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD939X_MBHC_NEW_ADC_RESULT, 0xFF),
 266	WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD939X_ANA_MICB2, 0x3F),
 267	WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD939X_MBHC_NEW_CTL_1, 0x10),
 268	WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD939X_MBHC_NEW_CTL_1, 0x04),
 269	WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD939X_ANA_MBHC_ZDET, 0x02),
 270};
 271
 272static const struct regmap_irq wcd939x_irqs[WCD939X_NUM_IRQS] = {
 273	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
 274	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
 275	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
 276	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
 277	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_SW_DET, 0, 0x10),
 278	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_OCP_INT, 0, 0x20),
 279	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_CNP_INT, 0, 0x40),
 280	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_OCP_INT, 0, 0x80),
 281	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_CNP_INT, 1, 0x01),
 282	REGMAP_IRQ_REG(WCD939X_IRQ_EAR_CNP_INT, 1, 0x02),
 283	REGMAP_IRQ_REG(WCD939X_IRQ_EAR_SCD_INT, 1, 0x04),
 284	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
 285	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
 286	REGMAP_IRQ_REG(WCD939X_IRQ_EAR_PDM_WD_INT, 1, 0x80),
 287	REGMAP_IRQ_REG(WCD939X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
 288	REGMAP_IRQ_REG(WCD939X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
 289	REGMAP_IRQ_REG(WCD939X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
 290};
 291
 292static const struct regmap_irq_chip wcd939x_regmap_irq_chip = {
 293	.name = "wcd939x",
 294	.irqs = wcd939x_irqs,
 295	.num_irqs = ARRAY_SIZE(wcd939x_irqs),
 296	.num_regs = 3,
 297	.status_base = WCD939X_DIGITAL_INTR_STATUS_0,
 298	.mask_base = WCD939X_DIGITAL_INTR_MASK_0,
 299	.ack_base = WCD939X_DIGITAL_INTR_CLEAR_0,
 300	.use_ack = 1,
 301	.runtime_pm = true,
 302	.irq_drv_data = NULL,
 303};
 304
 305static int wcd939x_get_clk_rate(int mode)
 306{
 307	int rate;
 308
 309	switch (mode) {
 310	case ADC_MODE_ULP2:
 311		rate = SWR_CLK_RATE_0P6MHZ;
 312		break;
 313	case ADC_MODE_ULP1:
 314		rate = SWR_CLK_RATE_1P2MHZ;
 315		break;
 316	case ADC_MODE_LP:
 317		rate = SWR_CLK_RATE_4P8MHZ;
 318		break;
 319	case ADC_MODE_NORMAL:
 320	case ADC_MODE_LO_HIF:
 321	case ADC_MODE_HIFI:
 322	case ADC_MODE_INVALID:
 323	default:
 324		rate = SWR_CLK_RATE_9P6MHZ;
 325		break;
 326	}
 327
 328	return rate;
 329}
 330
 331static int wcd939x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
 332{
 333	u8 mask = (bank ? 0xF0 : 0x0F);
 334	u8 val = 0;
 335
 336	switch (rate) {
 337	case SWR_CLK_RATE_0P6MHZ:
 338		val = 6;
 339		break;
 340	case SWR_CLK_RATE_1P2MHZ:
 341		val = 5;
 342		break;
 343	case SWR_CLK_RATE_2P4MHZ:
 344		val = 3;
 345		break;
 346	case SWR_CLK_RATE_4P8MHZ:
 347		val = 1;
 348		break;
 349	case SWR_CLK_RATE_9P6MHZ:
 350	default:
 351		val = 0;
 352		break;
 353	}
 354
 355	snd_soc_component_write_field(component, WCD939X_DIGITAL_SWR_TX_CLK_RATE, mask, val);
 356
 357	return 0;
 358}
 359
 360static int wcd939x_io_init(struct snd_soc_component *component)
 361{
 362	snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
 363				      WCD939X_BIAS_ANALOG_BIAS_EN, true);
 364	snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
 365				      WCD939X_BIAS_PRECHRG_EN, true);
 366
 367	/* 10 msec delay as per HW requirement */
 368	usleep_range(10000, 10010);
 369	snd_soc_component_write_field(component, WCD939X_ANA_BIAS,
 370				      WCD939X_BIAS_PRECHRG_EN, false);
 371
 372	snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
 373				      WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x15);
 374	snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
 375				      WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x15);
 376	snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
 377				      WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
 378
 379	snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
 380				      WCD939X_FE_ICTRL_STG2CASC_ULP_ICTRL_SCBIAS_ULP0P6M, 1);
 381	snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2CASC_ULP,
 382				      WCD939X_FE_ICTRL_STG2CASC_ULP_VALUE, 4);
 383
 384	snd_soc_component_write_field(component, WCD939X_TX_COM_NEW_INT_FE_ICTRL_STG2MAIN_ULP,
 385				      WCD939X_FE_ICTRL_STG2MAIN_ULP_VALUE, 8);
 386
 387	snd_soc_component_write_field(component, WCD939X_MICB1_TEST_CTL_1,
 388				      WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 389	snd_soc_component_write_field(component, WCD939X_MICB2_TEST_CTL_1,
 390				      WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 391	snd_soc_component_write_field(component, WCD939X_MICB3_TEST_CTL_1,
 392				      WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 393	snd_soc_component_write_field(component, WCD939X_MICB4_TEST_CTL_1,
 394				      WCD939X_TEST_CTL_1_NOISE_FILT_RES_VAL, 7);
 395	snd_soc_component_write_field(component, WCD939X_TX_3_4_TEST_BLK_EN2,
 396				      WCD939X_TEST_BLK_EN2_TXFE2_MBHC_CLKRST_EN, false);
 397
 398	snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
 399				      WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
 400	snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
 401				      WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
 402
 403	snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
 404				      WCD939X_OCP_CTL_OCP_FSM_EN, true);
 405	snd_soc_component_write_field(component, WCD939X_HPH_OCP_CTL,
 406				      WCD939X_OCP_CTL_SCD_OP_EN, true);
 407
 408	snd_soc_component_write(component, WCD939X_E_CFG0,
 409				WCD939X_CFG0_IDLE_STEREO |
 410				WCD939X_CFG0_AUTO_DISABLE_ANC);
 411
 412	return 0;
 413}
 414
 415static int wcd939x_sdw_connect_port(const struct wcd939x_sdw_ch_info *ch_info,
 416				    struct sdw_port_config *port_config,
 417				    u8 enable)
 418{
 419	u8 ch_mask, port_num;
 420
 421	port_num = ch_info->port_num;
 422	ch_mask = ch_info->ch_mask;
 423
 424	port_config->num = port_num;
 425
 426	if (enable)
 427		port_config->ch_mask |= ch_mask;
 428	else
 429		port_config->ch_mask &= ~ch_mask;
 430
 431	return 0;
 432}
 433
 434static int wcd939x_connect_port(struct wcd939x_sdw_priv *wcd, u8 port_num, u8 ch_id, u8 enable)
 435{
 436	return wcd939x_sdw_connect_port(&wcd->ch_info[ch_id],
 437					&wcd->port_config[port_num - 1],
 438					enable);
 439}
 440
 441static int wcd939x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
 442				      struct snd_kcontrol *kcontrol,
 443				      int event)
 444{
 445	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 446
 447	switch (event) {
 448	case SND_SOC_DAPM_PRE_PMU:
 449		snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 450					      WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, true);
 451
 452		/* Analog path clock controls */
 453		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 454					      WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, true);
 455		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 456					      WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
 457					      true);
 458		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 459					      WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
 460					      true);
 461
 462		/* Digital path clock controls */
 463		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 464					      WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, true);
 465		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 466					      WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, true);
 467		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 468					      WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, true);
 469		break;
 470	case SND_SOC_DAPM_POST_PMD:
 471		snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 472					      WCD939X_RX_SUPPLIES_VNEG_EN, false);
 473		snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 474					      WCD939X_RX_SUPPLIES_VPOS_EN, false);
 475
 476		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 477					      WCD939X_CDC_DIG_CLK_CTL_RXD2_CLK_EN, false);
 478		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 479					      WCD939X_CDC_DIG_CLK_CTL_RXD1_CLK_EN, false);
 480		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
 481					      WCD939X_CDC_DIG_CLK_CTL_RXD0_CLK_EN, false);
 482
 483		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 484					      WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV4_CLK_EN,
 485					      false);
 486		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 487					      WCD939X_CDC_ANA_CLK_CTL_ANA_RX_DIV2_CLK_EN,
 488					      false);
 489		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
 490					      WCD939X_CDC_ANA_CLK_CTL_ANA_RX_CLK_EN, false);
 491
 492		snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 493					      WCD939X_RX_SUPPLIES_RX_BIAS_ENABLE, false);
 494
 495		break;
 496	}
 497
 498	return 0;
 499}
 500
 501static int wcd939x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
 502					struct snd_kcontrol *kcontrol,
 503					int event)
 504{
 505	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 506	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 507
 508	switch (event) {
 509	case SND_SOC_DAPM_PRE_PMU:
 510		snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
 511					      WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
 512					      false);
 513
 514		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 515					      WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, true);
 516		break;
 517	case SND_SOC_DAPM_POST_PMU:
 518		snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
 519					      WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 0x1d);
 520		if (wcd939x->comp1_enable) {
 521			snd_soc_component_write_field(component,
 522						      WCD939X_DIGITAL_CDC_COMP_CTL_0,
 523						      WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
 524						      true);
 525			/* 5msec compander delay as per HW requirement */
 526			if (!wcd939x->comp2_enable ||
 527			    snd_soc_component_read_field(component,
 528							 WCD939X_DIGITAL_CDC_COMP_CTL_0,
 529							 WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN))
 530				usleep_range(5000, 5010);
 531
 532			snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 533						      WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
 534						      false);
 535		} else {
 536			snd_soc_component_write_field(component,
 537						      WCD939X_DIGITAL_CDC_COMP_CTL_0,
 538						      WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN,
 539						      false);
 540			snd_soc_component_write_field(component, WCD939X_HPH_L_EN,
 541						      WCD939X_L_EN_GAIN_SOURCE_SEL, true);
 542		}
 543		break;
 544	case SND_SOC_DAPM_POST_PMD:
 545		snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_L,
 546					      WCD939X_RDAC_HD2_CTL_L_HD2_RES_DIV_CTL_L, 1);
 547		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 548					      WCD939X_CDC_HPH_GAIN_CTL_HPHL_RX_EN, false);
 549		break;
 550	}
 551
 552	return 0;
 553}
 554
 555static int wcd939x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
 556					struct snd_kcontrol *kcontrol,
 557					int event)
 558{
 559	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 560	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 561
 562	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
 563		w->name, event);
 564
 565	switch (event) {
 566	case SND_SOC_DAPM_PRE_PMU:
 567		snd_soc_component_write_field(component, WCD939X_HPH_RDAC_CLK_CTL1,
 568					      WCD939X_RDAC_CLK_CTL1_OPAMP_CHOP_CLK_EN,
 569					      false);
 570
 571		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 572					      WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, true);
 573		break;
 574	case SND_SOC_DAPM_POST_PMU:
 575		snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
 576					      WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 0x1d);
 577		if (wcd939x->comp2_enable) {
 578			snd_soc_component_write_field(component,
 579						      WCD939X_DIGITAL_CDC_COMP_CTL_0,
 580						      WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
 581						      true);
 582			/* 5msec compander delay as per HW requirement */
 583			if (!wcd939x->comp1_enable ||
 584			    snd_soc_component_read_field(component,
 585							 WCD939X_DIGITAL_CDC_COMP_CTL_0,
 586							 WCD939X_CDC_COMP_CTL_0_HPHL_COMP_EN))
 587				usleep_range(5000, 5010);
 588			snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 589						      WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN,
 590						      false);
 591		} else {
 592			snd_soc_component_write_field(component,
 593						      WCD939X_DIGITAL_CDC_COMP_CTL_0,
 594						      WCD939X_CDC_COMP_CTL_0_HPHR_COMP_EN,
 595						      false);
 596			snd_soc_component_write_field(component, WCD939X_HPH_R_EN,
 597						      WCD939X_R_EN_GAIN_SOURCE_SEL, true);
 598		}
 599		break;
 600	case SND_SOC_DAPM_POST_PMD:
 601		snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_RDAC_HD2_CTL_R,
 602					      WCD939X_RDAC_HD2_CTL_R_HD2_RES_DIV_CTL_R, 1);
 603		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_HPH_GAIN_CTL,
 604					      WCD939X_CDC_HPH_GAIN_CTL_HPHR_RX_EN, false);
 605		break;
 606	}
 607
 608	return 0;
 609}
 610
 611static int wcd939x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
 612				       struct snd_kcontrol *kcontrol,
 613				       int event)
 614{
 615	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 616	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 617
 618	switch (event) {
 619	case SND_SOC_DAPM_PRE_PMU:
 620		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_EAR_GAIN_CTL,
 621					      WCD939X_CDC_EAR_GAIN_CTL_EAR_EN, true);
 622
 623		snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
 624					      WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, false);
 625
 626		/* 5 msec delay as per HW requirement */
 627		usleep_range(5000, 5010);
 628		wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
 629					WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
 630
 631		snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
 632					      WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
 633		break;
 634	case SND_SOC_DAPM_POST_PMD:
 635		snd_soc_component_write_field(component, WCD939X_EAR_DAC_CON,
 636					      WCD939X_DAC_CON_DAC_SAMPLE_EDGE_SEL, true);
 637		break;
 638	}
 639
 640	return 0;
 641}
 642
 643static int wcd939x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
 644					struct snd_kcontrol *kcontrol,
 645					int event)
 646{
 647	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 648	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 649	int hph_mode = wcd939x->hph_mode;
 650
 651	switch (event) {
 652	case SND_SOC_DAPM_PRE_PMU:
 653		if (wcd939x->ldoh)
 654			snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 655						      WCD939X_MODE_LDOH_EN, true);
 656
 657		wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
 658					WCD_CLSH_STATE_HPHR, hph_mode);
 659		wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
 660
 661		if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
 662			snd_soc_component_write_field(component,
 663					WCD939X_HPH_REFBUFF_LP_CTL,
 664					WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS, true);
 665		if (hph_mode == CLS_H_LOHIFI)
 666			snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 667						       WCD939X_HPH_PWR_LEVEL, 0);
 668
 669		snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
 670					      WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
 671		snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 672					      WCD939X_HPH_HPHR_REF_ENABLE, true);
 673
 674		if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
 675						 WCD939X_HPH_HPHL_REF_ENABLE))
 676			usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
 677
 678		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 679		snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
 680					      WCD939X_PDM_WD_CTL1_PDM_WD_EN, 3);
 681		break;
 682	case SND_SOC_DAPM_POST_PMU:
 683		/*
 684		 * 7ms sleep is required if compander is enabled as per
 685		 * HW requirement. If compander is disabled, then
 686		 * 20ms delay is required.
 687		 */
 688		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 689			if (!wcd939x->comp2_enable)
 690				usleep_range(20000, 20100);
 691			else
 692				usleep_range(7000, 7100);
 693
 694			if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
 695			    hph_mode == CLS_H_ULP)
 696				snd_soc_component_write_field(component,
 697						WCD939X_HPH_REFBUFF_LP_CTL,
 698						WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
 699						false);
 700			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 701		}
 702		snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 703					      WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
 704		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
 705		    hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
 706			snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 707						      WCD939X_RX_SUPPLIES_REGULATOR_MODE,
 708						      true);
 709
 710		enable_irq(wcd939x->hphr_pdm_wd_int);
 711		break;
 712	case SND_SOC_DAPM_PRE_PMD:
 713		disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
 714		/*
 715		 * 7ms sleep is required if compander is enabled as per
 716		 * HW requirement. If compander is disabled, then
 717		 * 20ms delay is required.
 718		 */
 719		if (!wcd939x->comp2_enable)
 720			usleep_range(20000, 20100);
 721		else
 722			usleep_range(7000, 7100);
 723
 724		snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 725					      WCD939X_HPH_HPHR_ENABLE, false);
 726
 727		wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
 728				      WCD_EVENT_PRE_HPHR_PA_OFF);
 729		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 730		break;
 731	case SND_SOC_DAPM_POST_PMD:
 732		/*
 733		 * 7ms sleep is required if compander is enabled as per
 734		 * HW requirement. If compander is disabled, then
 735		 * 20ms delay is required.
 736		 */
 737		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 738			if (!wcd939x->comp2_enable)
 739				usleep_range(20000, 20100);
 740			else
 741				usleep_range(7000, 7100);
 742			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 743		}
 744		wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
 745				      WCD_EVENT_POST_HPHR_PA_OFF);
 746
 747		snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 748					      WCD939X_HPH_HPHR_REF_ENABLE, false);
 749		snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL1,
 750					      WCD939X_PDM_WD_CTL1_PDM_WD_EN, 0);
 751
 752		wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
 753					WCD_CLSH_STATE_HPHR, hph_mode);
 754		if (wcd939x->ldoh)
 755			snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 756						      WCD939X_MODE_LDOH_EN, false);
 757		break;
 758	}
 759
 760	return 0;
 761}
 762
 763static int wcd939x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
 764					struct snd_kcontrol *kcontrol,
 765					int event)
 766{
 767	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 768	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 769	int hph_mode = wcd939x->hph_mode;
 770
 771	dev_dbg(component->dev, "%s wname: %s event: %d\n", __func__,
 772		w->name, event);
 773
 774	switch (event) {
 775	case SND_SOC_DAPM_PRE_PMU:
 776		if (wcd939x->ldoh)
 777			snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 778						      WCD939X_MODE_LDOH_EN, true);
 779		wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
 780					WCD_CLSH_STATE_HPHL, hph_mode);
 781		wcd_clsh_set_hph_mode(wcd939x->clsh_info, CLS_H_HIFI);
 782
 783		if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI || hph_mode == CLS_H_ULP)
 784			snd_soc_component_write_field(component,
 785						WCD939X_HPH_REFBUFF_LP_CTL,
 786						WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
 787						true);
 788		if (hph_mode == CLS_H_LOHIFI)
 789			snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 790						       WCD939X_HPH_PWR_LEVEL, 0);
 791
 792		snd_soc_component_write_field(component, WCD939X_FLYBACK_VNEG_CTRL_4,
 793					      WCD939X_VNEG_CTRL_4_ILIM_SEL, 0xd);
 794		snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 795					      WCD939X_HPH_HPHL_REF_ENABLE, true);
 796
 797		if (snd_soc_component_read_field(component, WCD939X_ANA_HPH,
 798						 WCD939X_HPH_HPHR_REF_ENABLE))
 799			usleep_range(2500, 2600); /* 2.5msec delay as per HW requirement */
 800
 801		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 802		snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 803					      WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
 804		break;
 805	case SND_SOC_DAPM_POST_PMU:
 806		/*
 807		 * 7ms sleep is required if compander is enabled as per
 808		 * HW requirement. If compander is disabled, then
 809		 * 20ms delay is required.
 810		 */
 811		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 812			if (!wcd939x->comp1_enable)
 813				usleep_range(20000, 20100);
 814			else
 815				usleep_range(7000, 7100);
 816			if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
 817			    hph_mode == CLS_H_ULP)
 818				snd_soc_component_write_field(component,
 819						WCD939X_HPH_REFBUFF_LP_CTL,
 820						WCD939X_REFBUFF_LP_CTL_PREREF_FILT_BYPASS,
 821						false);
 822			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 823		}
 824		snd_soc_component_write_field(component, WCD939X_HPH_NEW_INT_TIMER1,
 825					      WCD939X_TIMER1_AUTOCHOP_TIMER_CTL_EN, true);
 826		if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
 827		    hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
 828			snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 829						      WCD939X_RX_SUPPLIES_REGULATOR_MODE,
 830						      true);
 831		enable_irq(wcd939x->hphl_pdm_wd_int);
 832		break;
 833	case SND_SOC_DAPM_PRE_PMD:
 834		disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
 835		/*
 836		 * 7ms sleep is required if compander is enabled as per
 837		 * HW requirement. If compander is disabled, then
 838		 * 20ms delay is required.
 839		 */
 840		if (!wcd939x->comp1_enable)
 841			usleep_range(20000, 20100);
 842		else
 843			usleep_range(7000, 7100);
 844
 845		snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 846					      WCD939X_HPH_HPHL_ENABLE, false);
 847
 848		wcd_mbhc_event_notify(wcd939x->wcd_mbhc, WCD_EVENT_PRE_HPHL_PA_OFF);
 849		set_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 850		break;
 851	case SND_SOC_DAPM_POST_PMD:
 852		/*
 853		 * 7ms sleep is required if compander is enabled as per
 854		 * HW requirement. If compander is disabled, then
 855		 * 20ms delay is required.
 856		 */
 857		if (test_bit(HPH_PA_DELAY, &wcd939x->status_mask)) {
 858			if (!wcd939x->comp1_enable)
 859				usleep_range(21000, 21100);
 860			else
 861				usleep_range(7000, 7100);
 862			clear_bit(HPH_PA_DELAY, &wcd939x->status_mask);
 863		}
 864		wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
 865				      WCD_EVENT_POST_HPHL_PA_OFF);
 866		snd_soc_component_write_field(component, WCD939X_ANA_HPH,
 867					      WCD939X_HPH_HPHL_REF_ENABLE, false);
 868		snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 869					      WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
 870		wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
 871					WCD_CLSH_STATE_HPHL, hph_mode);
 872		if (wcd939x->ldoh)
 873			snd_soc_component_write_field(component, WCD939X_LDOH_MODE,
 874						      WCD939X_MODE_LDOH_EN, false);
 875		break;
 876	}
 877
 878	return 0;
 879}
 880
 881static int wcd939x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
 882				       struct snd_kcontrol *kcontrol, int event)
 883{
 884	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 885	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
 886
 887	switch (event) {
 888	case SND_SOC_DAPM_PRE_PMU:
 889		/* Enable watchdog interrupt for HPHL */
 890		snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 891					      WCD939X_PDM_WD_CTL0_PDM_WD_EN, 3);
 892		/* For EAR, use CLASS_AB regulator mode */
 893		snd_soc_component_write_field(component, WCD939X_ANA_RX_SUPPLIES,
 894					      WCD939X_RX_SUPPLIES_REGULATOR_MODE, true);
 895		snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
 896					      WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG, true);
 897		break;
 898	case SND_SOC_DAPM_POST_PMU:
 899		/* 6 msec delay as per HW requirement */
 900		usleep_range(6000, 6010);
 901		enable_irq(wcd939x->ear_pdm_wd_int);
 902		break;
 903	case SND_SOC_DAPM_PRE_PMD:
 904		disable_irq_nosync(wcd939x->ear_pdm_wd_int);
 905		break;
 906	case SND_SOC_DAPM_POST_PMD:
 907		snd_soc_component_write_field(component, WCD939X_ANA_EAR_COMPANDER_CTL,
 908					      WCD939X_EAR_COMPANDER_CTL_GAIN_OVRD_REG,
 909					      false);
 910		/* 7 msec delay as per HW requirement */
 911		usleep_range(7000, 7010);
 912		snd_soc_component_write_field(component, WCD939X_DIGITAL_PDM_WD_CTL0,
 913					      WCD939X_PDM_WD_CTL0_PDM_WD_EN, 0);
 914		wcd_clsh_ctrl_set_state(wcd939x->clsh_info, WCD_CLSH_EVENT_POST_PA,
 915					WCD_CLSH_STATE_EAR, CLS_AB_HIFI);
 916		break;
 917	}
 918
 919	return 0;
 920}
 921
 922/* TX Controls */
 923
 924static int wcd939x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
 925				     struct snd_kcontrol *kcontrol,
 926				     int event)
 927{
 928	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
 929	u16 dmic_clk_reg, dmic_clk_en_reg;
 930	u8 dmic_clk_en_mask;
 931	u8 dmic_ctl_mask;
 932	u8 dmic_clk_mask;
 933
 934	switch (w->shift) {
 935	case 0:
 936	case 1:
 937		dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
 938		dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC1_CTL;
 939		dmic_clk_en_mask = WCD939X_CDC_DMIC1_CTL_DMIC_CLK_EN;
 940		dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC1_RATE;
 941		dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC1_IN_SEL;
 942		break;
 943	case 2:
 944	case 3:
 945		dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_1_2;
 946		dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC2_CTL;
 947		dmic_clk_en_mask = WCD939X_CDC_DMIC2_CTL_DMIC_CLK_EN;
 948		dmic_clk_mask = WCD939X_CDC_DMIC_RATE_1_2_DMIC2_RATE;
 949		dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC3_IN_SEL;
 950		break;
 951	case 4:
 952	case 5:
 953		dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
 954		dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC3_CTL;
 955		dmic_clk_en_mask = WCD939X_CDC_DMIC3_CTL_DMIC_CLK_EN;
 956		dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC3_RATE;
 957		dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC4_IN_SEL;
 958		break;
 959	case 6:
 960	case 7:
 961		dmic_clk_reg = WCD939X_DIGITAL_CDC_DMIC_RATE_3_4;
 962		dmic_clk_en_reg = WCD939X_DIGITAL_CDC_DMIC4_CTL;
 963		dmic_clk_en_mask = WCD939X_CDC_DMIC4_CTL_DMIC_CLK_EN;
 964		dmic_clk_mask = WCD939X_CDC_DMIC_RATE_3_4_DMIC4_RATE;
 965		dmic_ctl_mask = WCD939X_CDC_AMIC_CTL_AMIC5_IN_SEL;
 966		break;
 967	default:
 968		dev_err(component->dev, "%s: Invalid DMIC Selection\n", __func__);
 969		return -EINVAL;
 970	}
 971
 972	switch (event) {
 973	case SND_SOC_DAPM_PRE_PMU:
 974		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
 975					      dmic_ctl_mask, false);
 976		/* 250us sleep as per HW requirement */
 977		usleep_range(250, 260);
 978		if (w->shift == 2)
 979			snd_soc_component_write_field(component,
 980						      WCD939X_DIGITAL_CDC_DMIC2_CTL,
 981						      WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
 982						      true);
 983		/* Setting DMIC clock rate to 2.4MHz */
 984		snd_soc_component_write_field(component, dmic_clk_reg,
 985					      dmic_clk_mask, 3);
 986		snd_soc_component_write_field(component, dmic_clk_en_reg,
 987					      dmic_clk_en_mask, true);
 988		/* enable clock scaling */
 989		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
 990					      WCD939X_CDC_DMIC_CTL_CLK_SCALE_EN, true);
 991		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_DMIC_CTL,
 992					      WCD939X_CDC_DMIC_CTL_DMIC_DIV_BAK_EN, true);
 993		break;
 994	case SND_SOC_DAPM_POST_PMD:
 995		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_AMIC_CTL,
 996					      dmic_ctl_mask, 1);
 997		if (w->shift == 2)
 998			snd_soc_component_write_field(component,
 999						      WCD939X_DIGITAL_CDC_DMIC2_CTL,
1000						      WCD939X_CDC_DMIC2_CTL_DMIC_LEFT_EN,
1001						      false);
1002		snd_soc_component_write_field(component, dmic_clk_en_reg,
1003					      dmic_clk_en_mask, 0);
1004		break;
1005	}
1006	return 0;
1007}
1008
1009static int wcd939x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
1010			       struct snd_kcontrol *kcontrol, int event)
1011{
1012	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1013	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1014	int bank;
1015	int rate;
1016
1017	bank = wcd939x_swr_get_current_bank(wcd939x->sdw_priv[AIF1_CAP]->sdev);
1018
1019	switch (event) {
1020	case SND_SOC_DAPM_PRE_PMU:
1021		if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1022			int mode = 0;
1023
1024			if (test_bit(WCD_ADC1, &wcd939x->status_mask))
1025				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC1]];
1026			if (test_bit(WCD_ADC2, &wcd939x->status_mask))
1027				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC2]];
1028			if (test_bit(WCD_ADC3, &wcd939x->status_mask))
1029				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC3]];
1030			if (test_bit(WCD_ADC4, &wcd939x->status_mask))
1031				mode |= tx_mode_bit[wcd939x->tx_mode[WCD_ADC4]];
1032
1033			if (mode)
1034				rate = wcd939x_get_clk_rate(ffs(mode) - 1);
1035			else
1036				rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1037			wcd939x_set_swr_clk_rate(component, rate, bank);
1038			wcd939x_set_swr_clk_rate(component, rate, !bank);
1039		}
1040		break;
1041	case SND_SOC_DAPM_POST_PMD:
1042		if (strnstr(w->name, "ADC", sizeof("ADC"))) {
1043			rate = wcd939x_get_clk_rate(ADC_MODE_INVALID);
1044			wcd939x_set_swr_clk_rate(component, rate, !bank);
1045			wcd939x_set_swr_clk_rate(component, rate, bank);
1046		}
1047		break;
1048	}
1049
1050	return 0;
1051}
1052
1053static int wcd939x_get_adc_mode(int val)
1054{
1055	int ret = 0;
1056
1057	switch (val) {
1058	case ADC_MODE_INVALID:
1059		ret = ADC_MODE_VAL_NORMAL;
1060		break;
1061	case ADC_MODE_HIFI:
1062		ret = ADC_MODE_VAL_HIFI;
1063		break;
1064	case ADC_MODE_LO_HIF:
1065		ret = ADC_MODE_VAL_LO_HIF;
1066		break;
1067	case ADC_MODE_NORMAL:
1068		ret = ADC_MODE_VAL_NORMAL;
1069		break;
1070	case ADC_MODE_LP:
1071		ret = ADC_MODE_VAL_LP;
1072		break;
1073	case ADC_MODE_ULP1:
1074		ret = ADC_MODE_VAL_ULP1;
1075		break;
1076	case ADC_MODE_ULP2:
1077		ret = ADC_MODE_VAL_ULP2;
1078		break;
1079	default:
1080		ret = -EINVAL;
1081		break;
1082	}
1083	return ret;
1084}
1085
1086static int wcd939x_codec_enable_adc(struct snd_soc_dapm_widget *w,
1087				    struct snd_kcontrol *kcontrol, int event)
1088{
1089	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1090	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1091
1092	switch (event) {
1093	case SND_SOC_DAPM_PRE_PMU:
1094		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1095					      WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN, true);
1096		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1097					      WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1098					      true);
1099		set_bit(w->shift, &wcd939x->status_mask);
1100		break;
1101	case SND_SOC_DAPM_POST_PMD:
1102		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1103					      WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1104					      false);
1105		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1106					      WCD939X_CDC_ANA_CLK_CTL_ANA_TX_CLK_EN,
1107					      false);
1108		clear_bit(w->shift, &wcd939x->status_mask);
1109		break;
1110	}
1111
1112	return 0;
1113}
1114
1115static void wcd939x_tx_channel_config(struct snd_soc_component *component,
1116				      int channel, bool init)
1117{
1118	int reg, mask;
1119
1120	switch (channel) {
1121	case 0:
1122		reg = WCD939X_ANA_TX_CH2;
1123		mask = WCD939X_TX_CH2_HPF1_INIT;
1124		break;
1125	case 1:
1126		reg = WCD939X_ANA_TX_CH2;
1127		mask = WCD939X_TX_CH2_HPF2_INIT;
1128		break;
1129	case 2:
1130		reg = WCD939X_ANA_TX_CH4;
1131		mask = WCD939X_TX_CH4_HPF3_INIT;
1132		break;
1133	case 3:
1134		reg = WCD939X_ANA_TX_CH4;
1135		mask = WCD939X_TX_CH4_HPF4_INIT;
1136		break;
1137	default:
1138		return;
1139	}
1140
1141	snd_soc_component_write_field(component, reg, mask, init);
1142}
1143
1144static int wcd939x_adc_enable_req(struct snd_soc_dapm_widget *w,
1145				  struct snd_kcontrol *kcontrol, int event)
1146{
1147	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1148	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1149	int mode;
1150
1151	switch (event) {
1152	case SND_SOC_DAPM_PRE_PMU:
1153		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1154					      WCD939X_CDC_REQ_CTL_FS_RATE_4P8, true);
1155		snd_soc_component_write_field(component, WCD939X_DIGITAL_CDC_REQ_CTL,
1156					      WCD939X_CDC_REQ_CTL_NO_NOTCH, false);
1157
1158		wcd939x_tx_channel_config(component, w->shift, true);
1159		mode = wcd939x_get_adc_mode(wcd939x->tx_mode[w->shift]);
1160		if (mode < 0) {
1161			dev_info(component->dev, "Invalid ADC mode\n");
1162			return -EINVAL;
1163		}
1164
1165		switch (w->shift) {
1166		case 0:
1167			snd_soc_component_write_field(component,
1168						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1169						      WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1170						      mode);
1171			snd_soc_component_write_field(component,
1172						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1173						      WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1174						      true);
1175			break;
1176		case 1:
1177			snd_soc_component_write_field(component,
1178						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1179						      WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1180						      mode);
1181			snd_soc_component_write_field(component,
1182						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1183						      WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1184						      true);
1185			break;
1186		case 2:
1187			snd_soc_component_write_field(component,
1188						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1189						      WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1190						      mode);
1191			snd_soc_component_write_field(component,
1192						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1193						      WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1194						      true);
1195			break;
1196		case 3:
1197			snd_soc_component_write_field(component,
1198						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1199						      WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1200						      mode);
1201			snd_soc_component_write_field(component,
1202						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1203						      WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1204						      true);
1205			break;
1206		default:
1207			break;
1208		}
1209
1210		wcd939x_tx_channel_config(component, w->shift, false);
1211		break;
1212	case SND_SOC_DAPM_POST_PMD:
1213		switch (w->shift) {
1214		case 0:
1215			snd_soc_component_write_field(component,
1216						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1217						      WCD939X_CDC_TX_ANA_MODE_0_1_TXD0_MODE,
1218						      false);
1219			snd_soc_component_write_field(component,
1220						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1221						      WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN,
1222						      false);
1223			break;
1224		case 1:
1225			snd_soc_component_write_field(component,
1226						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_0_1,
1227						      WCD939X_CDC_TX_ANA_MODE_0_1_TXD1_MODE,
1228						      false);
1229			snd_soc_component_write_field(component,
1230						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1231						      WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN,
1232						      false);
1233			break;
1234		case 2:
1235			snd_soc_component_write_field(component,
1236						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1237						      WCD939X_CDC_TX_ANA_MODE_2_3_TXD2_MODE,
1238						      false);
1239			snd_soc_component_write_field(component,
1240						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1241						      WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN,
1242						      false);
1243			break;
1244		case 3:
1245			snd_soc_component_write_field(component,
1246						      WCD939X_DIGITAL_CDC_TX_ANA_MODE_2_3,
1247						      WCD939X_CDC_TX_ANA_MODE_2_3_TXD3_MODE,
1248						      false);
1249			snd_soc_component_write_field(component,
1250						      WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1251						      WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN,
1252						      false);
1253			break;
1254		default:
1255			break;
1256		}
1257		break;
1258	}
1259
1260	return 0;
1261}
1262
1263static int wcd939x_micbias_control(struct snd_soc_component *component,
1264				   int micb_num, int req, bool is_dapm)
1265{
1266	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1267	int micb_index = micb_num - 1;
1268	u16 micb_reg;
1269
1270	switch (micb_num) {
1271	case MIC_BIAS_1:
1272		micb_reg = WCD939X_ANA_MICB1;
1273		break;
1274	case MIC_BIAS_2:
1275		micb_reg = WCD939X_ANA_MICB2;
1276		break;
1277	case MIC_BIAS_3:
1278		micb_reg = WCD939X_ANA_MICB3;
1279		break;
1280	case MIC_BIAS_4:
1281		micb_reg = WCD939X_ANA_MICB4;
1282		break;
1283	default:
1284		dev_err(component->dev, "%s: Invalid micbias number: %d\n",
1285			__func__, micb_num);
1286		return -EINVAL;
1287	}
1288
1289	switch (req) {
1290	case MICB_PULLUP_ENABLE:
1291		wcd939x->pullup_ref[micb_index]++;
1292		if (wcd939x->pullup_ref[micb_index] == 1 &&
1293		    wcd939x->micb_ref[micb_index] == 0)
1294			snd_soc_component_write_field(component, micb_reg,
1295						      WCD939X_MICB_ENABLE,
1296						      MICB_BIAS_PULL_UP);
1297		break;
1298	case MICB_PULLUP_DISABLE:
1299		if (wcd939x->pullup_ref[micb_index] > 0)
1300			wcd939x->pullup_ref[micb_index]--;
1301		if (wcd939x->pullup_ref[micb_index] == 0 &&
1302		    wcd939x->micb_ref[micb_index] == 0)
1303			snd_soc_component_write_field(component, micb_reg,
1304						      WCD939X_MICB_ENABLE,
1305						      MICB_BIAS_DISABLE);
1306		break;
1307	case MICB_ENABLE:
1308		wcd939x->micb_ref[micb_index]++;
1309		if (wcd939x->micb_ref[micb_index] == 1) {
1310			snd_soc_component_write_field(component,
1311						WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1312						WCD939X_CDC_DIG_CLK_CTL_TXD3_CLK_EN, true);
1313			snd_soc_component_write_field(component,
1314						WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1315						WCD939X_CDC_DIG_CLK_CTL_TXD2_CLK_EN, true);
1316			snd_soc_component_write_field(component,
1317						WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1318						WCD939X_CDC_DIG_CLK_CTL_TXD1_CLK_EN, true);
1319			snd_soc_component_write_field(component,
1320						WCD939X_DIGITAL_CDC_DIG_CLK_CTL,
1321						WCD939X_CDC_DIG_CLK_CTL_TXD0_CLK_EN, true);
1322			snd_soc_component_write_field(component,
1323						WCD939X_DIGITAL_CDC_ANA_CLK_CTL,
1324						WCD939X_CDC_ANA_CLK_CTL_ANA_TX_DIV2_CLK_EN,
1325						true);
1326			snd_soc_component_write_field(component,
1327						WCD939X_DIGITAL_CDC_ANA_TX_CLK_CTL,
1328						WCD939X_CDC_ANA_TX_CLK_CTL_ANA_TXSCBIAS_CLK_EN,
1329						true);
1330			snd_soc_component_write_field(component,
1331						WCD939X_MICB1_TEST_CTL_2,
1332						WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1333			snd_soc_component_write_field(component,
1334						WCD939X_MICB2_TEST_CTL_2,
1335						WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1336			snd_soc_component_write_field(component,
1337						WCD939X_MICB3_TEST_CTL_2,
1338						WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1339			snd_soc_component_write_field(component,
1340						WCD939X_MICB4_TEST_CTL_2,
1341						WCD939X_TEST_CTL_2_IBIAS_LDO_DRIVER, true);
1342			snd_soc_component_write_field(component, micb_reg,
1343						      WCD939X_MICB_ENABLE,
1344						      MICB_BIAS_ENABLE);
1345			if (micb_num == MIC_BIAS_2)
1346				wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1347						      WCD_EVENT_POST_MICBIAS_2_ON);
1348		}
1349		if (micb_num == MIC_BIAS_2 && is_dapm)
1350			wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1351					      WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
1352		break;
1353	case MICB_DISABLE:
1354		if (wcd939x->micb_ref[micb_index] > 0)
1355			wcd939x->micb_ref[micb_index]--;
1356
1357		if (wcd939x->micb_ref[micb_index] == 0 &&
1358		    wcd939x->pullup_ref[micb_index] > 0)
1359			snd_soc_component_write_field(component, micb_reg,
1360						      WCD939X_MICB_ENABLE,
1361						      MICB_BIAS_PULL_UP);
1362		else if (wcd939x->micb_ref[micb_index] == 0 &&
1363			 wcd939x->pullup_ref[micb_index] == 0) {
1364			if (micb_num  == MIC_BIAS_2)
1365				wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1366						      WCD_EVENT_PRE_MICBIAS_2_OFF);
1367
1368			snd_soc_component_write_field(component, micb_reg,
1369						      WCD939X_MICB_ENABLE,
1370						      MICB_BIAS_DISABLE);
1371			if (micb_num  == MIC_BIAS_2)
1372				wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1373						      WCD_EVENT_POST_MICBIAS_2_OFF);
1374		}
1375		if (is_dapm && micb_num  == MIC_BIAS_2)
1376			wcd_mbhc_event_notify(wcd939x->wcd_mbhc,
1377					      WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
1378		break;
1379	}
1380
1381	return 0;
1382}
1383
1384static int wcd939x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
1385					struct snd_kcontrol *kcontrol,
1386					int event)
1387{
1388	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1389	int micb_num = w->shift;
1390
1391	switch (event) {
1392	case SND_SOC_DAPM_PRE_PMU:
1393		wcd939x_micbias_control(component, micb_num, MICB_ENABLE, true);
1394		break;
1395	case SND_SOC_DAPM_POST_PMU:
1396		/* 1 msec delay as per HW requirement */
1397		usleep_range(1000, 1100);
1398		break;
1399	case SND_SOC_DAPM_POST_PMD:
1400		wcd939x_micbias_control(component, micb_num, MICB_DISABLE, true);
1401		break;
1402	}
1403
1404	return 0;
1405}
1406
1407static int wcd939x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
1408					       struct snd_kcontrol *kcontrol,
1409					       int event)
1410{
1411	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1412	int micb_num = w->shift;
1413
1414	switch (event) {
1415	case SND_SOC_DAPM_PRE_PMU:
1416		wcd939x_micbias_control(component, micb_num,
1417					MICB_PULLUP_ENABLE, true);
1418		break;
1419	case SND_SOC_DAPM_POST_PMU:
1420		/* 1 msec delay as per HW requirement */
1421		usleep_range(1000, 1100);
1422		break;
1423	case SND_SOC_DAPM_POST_PMD:
1424		wcd939x_micbias_control(component, micb_num,
1425					MICB_PULLUP_DISABLE, true);
1426		break;
1427	}
1428
1429	return 0;
1430}
1431
1432static int wcd939x_tx_mode_get(struct snd_kcontrol *kcontrol,
1433			       struct snd_ctl_elem_value *ucontrol)
1434{
1435	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1436	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1437	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1438	int path = e->shift_l;
1439
1440	ucontrol->value.enumerated.item[0] = wcd939x->tx_mode[path];
1441
1442	return 0;
1443}
1444
1445static int wcd939x_tx_mode_put(struct snd_kcontrol *kcontrol,
1446			       struct snd_ctl_elem_value *ucontrol)
1447{
1448	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1449	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1450	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1451	int path = e->shift_l;
1452
1453	if (wcd939x->tx_mode[path] == ucontrol->value.enumerated.item[0])
1454		return 0;
1455
1456	wcd939x->tx_mode[path] = ucontrol->value.enumerated.item[0];
1457
1458	return 1;
1459}
1460
1461/* RX Controls */
1462
1463static int wcd939x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
1464				   struct snd_ctl_elem_value *ucontrol)
1465{
1466	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1467	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1468
1469	ucontrol->value.integer.value[0] = wcd939x->hph_mode;
1470
1471	return 0;
1472}
1473
1474static int wcd939x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
1475				   struct snd_ctl_elem_value *ucontrol)
1476{
1477	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1478	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1479	u32 mode_val;
1480
1481	mode_val = ucontrol->value.enumerated.item[0];
1482
1483	if (mode_val == wcd939x->hph_mode)
1484		return 0;
1485
1486	if (wcd939x->variant == WCD9390) {
1487		switch (mode_val) {
1488		case CLS_H_NORMAL:
1489		case CLS_H_LP:
1490		case CLS_AB:
1491		case CLS_H_LOHIFI:
1492		case CLS_H_ULP:
1493		case CLS_AB_LP:
1494		case CLS_AB_LOHIFI:
1495			wcd939x->hph_mode = mode_val;
1496			return 1;
1497		}
1498	} else {
1499		switch (mode_val) {
1500		case CLS_H_NORMAL:
1501		case CLS_H_HIFI:
1502		case CLS_H_LP:
1503		case CLS_AB:
1504		case CLS_H_LOHIFI:
1505		case CLS_H_ULP:
1506		case CLS_AB_HIFI:
1507		case CLS_AB_LP:
1508		case CLS_AB_LOHIFI:
1509			wcd939x->hph_mode = mode_val;
1510			return 1;
1511		}
1512	}
1513
1514	dev_dbg(component->dev, "%s: Invalid HPH Mode\n", __func__);
1515	return -EINVAL;
1516}
1517
1518static int wcd939x_get_compander(struct snd_kcontrol *kcontrol,
1519				 struct snd_ctl_elem_value *ucontrol)
1520{
1521	struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1522	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1523	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1524
1525	if (mc->shift)
1526		ucontrol->value.integer.value[0] = wcd939x->comp2_enable ? 1 : 0;
1527	else
1528		ucontrol->value.integer.value[0] = wcd939x->comp1_enable ? 1 : 0;
1529
1530	return 0;
1531}
1532
1533static int wcd939x_set_compander(struct snd_kcontrol *kcontrol,
1534				 struct snd_ctl_elem_value *ucontrol)
1535{
1536	struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
1537	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1538	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1539	struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[AIF1_PB];
1540	bool value = !!ucontrol->value.integer.value[0];
1541	int portidx = wcd->ch_info[mc->reg].port_num;
1542
1543	if (mc->shift)
1544		wcd939x->comp2_enable = value;
1545	else
1546		wcd939x->comp1_enable = value;
1547
1548	if (value)
1549		wcd939x_connect_port(wcd, portidx, mc->reg, true);
1550	else
1551		wcd939x_connect_port(wcd, portidx, mc->reg, false);
1552
1553	return 1;
1554}
1555
1556static int wcd939x_ldoh_get(struct snd_kcontrol *kcontrol,
1557			    struct snd_ctl_elem_value *ucontrol)
1558{
1559	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1560	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1561
1562	ucontrol->value.integer.value[0] = wcd939x->ldoh ? 1 : 0;
1563
1564	return 0;
1565}
1566
1567static int wcd939x_ldoh_put(struct snd_kcontrol *kcontrol,
1568			    struct snd_ctl_elem_value *ucontrol)
1569{
1570	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1571	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1572
1573	if (wcd939x->ldoh == !!ucontrol->value.integer.value[0])
1574		return 0;
1575
1576	wcd939x->ldoh = !!ucontrol->value.integer.value[0];
1577
1578	return 1;
1579}
1580
1581static const char * const tx_mode_mux_text_wcd9390[] = {
1582	"ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1583};
1584
1585static const struct soc_enum tx0_mode_mux_enum_wcd9390 =
1586	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1587			tx_mode_mux_text_wcd9390);
1588
1589static const struct soc_enum tx1_mode_mux_enum_wcd9390 =
1590	SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1591			tx_mode_mux_text_wcd9390);
1592
1593static const struct soc_enum tx2_mode_mux_enum_wcd9390 =
1594	SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1595			tx_mode_mux_text_wcd9390);
1596
1597static const struct soc_enum tx3_mode_mux_enum_wcd9390 =
1598	SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9390),
1599			tx_mode_mux_text_wcd9390);
1600
1601static const char * const tx_mode_mux_text[] = {
1602	"ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
1603	"ADC_ULP1", "ADC_ULP2",
1604};
1605
1606static const struct soc_enum tx0_mode_mux_enum =
1607	SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
1608			tx_mode_mux_text);
1609
1610static const struct soc_enum tx1_mode_mux_enum =
1611	SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
1612			tx_mode_mux_text);
1613
1614static const struct soc_enum tx2_mode_mux_enum =
1615	SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
1616			tx_mode_mux_text);
1617
1618static const struct soc_enum tx3_mode_mux_enum =
1619	SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
1620			tx_mode_mux_text);
1621
1622static const char * const rx_hph_mode_mux_text_wcd9390[] = {
1623	"CLS_H_NORMAL", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
1624	"CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
1625	"CLS_AB_LOHIFI",
1626};
1627
1628static const struct soc_enum rx_hph_mode_mux_enum_wcd9390 =
1629	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9390),
1630			    rx_hph_mode_mux_text_wcd9390);
1631
1632static const char * const rx_hph_mode_mux_text[] = {
1633	"CLS_H_NORMAL", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
1634	"CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
1635};
1636
1637static const struct soc_enum rx_hph_mode_mux_enum =
1638	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
1639			    rx_hph_mode_mux_text);
1640
1641static const struct snd_kcontrol_new wcd9390_snd_controls[] = {
1642	SOC_SINGLE_TLV("EAR_PA Volume", WCD939X_ANA_EAR_COMPANDER_CTL,
1643		       2, 0x10, 0, ear_pa_gain),
1644
1645	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9390,
1646		     wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1647
1648	SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum_wcd9390,
1649		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1650	SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum_wcd9390,
1651		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1652	SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum_wcd9390,
1653		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1654	SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum_wcd9390,
1655		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1656};
1657
1658static const struct snd_kcontrol_new wcd9395_snd_controls[] = {
1659	SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
1660		     wcd939x_rx_hph_mode_get, wcd939x_rx_hph_mode_put),
1661
1662	SOC_ENUM_EXT("TX0 MODE", tx0_mode_mux_enum,
1663		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1664	SOC_ENUM_EXT("TX1 MODE", tx1_mode_mux_enum,
1665		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1666	SOC_ENUM_EXT("TX2 MODE", tx2_mode_mux_enum,
1667		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1668	SOC_ENUM_EXT("TX3 MODE", tx3_mode_mux_enum,
1669		     wcd939x_tx_mode_get, wcd939x_tx_mode_put),
1670};
1671
1672static const struct snd_kcontrol_new adc1_switch[] = {
1673	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1674};
1675
1676static const struct snd_kcontrol_new adc2_switch[] = {
1677	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1678};
1679
1680static const struct snd_kcontrol_new adc3_switch[] = {
1681	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1682};
1683
1684static const struct snd_kcontrol_new adc4_switch[] = {
1685	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1686};
1687
1688static const struct snd_kcontrol_new dmic1_switch[] = {
1689	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1690};
1691
1692static const struct snd_kcontrol_new dmic2_switch[] = {
1693	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1694};
1695
1696static const struct snd_kcontrol_new dmic3_switch[] = {
1697	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1698};
1699
1700static const struct snd_kcontrol_new dmic4_switch[] = {
1701	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1702};
1703
1704static const struct snd_kcontrol_new dmic5_switch[] = {
1705	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1706};
1707
1708static const struct snd_kcontrol_new dmic6_switch[] = {
1709	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1710};
1711
1712static const struct snd_kcontrol_new dmic7_switch[] = {
1713	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1714};
1715
1716static const struct snd_kcontrol_new dmic8_switch[] = {
1717	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1718};
1719
1720static const struct snd_kcontrol_new ear_rdac_switch[] = {
1721	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1722};
1723
1724static const struct snd_kcontrol_new hphl_rdac_switch[] = {
1725	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1726};
1727
1728static const struct snd_kcontrol_new hphr_rdac_switch[] = {
1729	SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
1730};
1731
1732static const char * const adc1_mux_text[] = {
1733	"CH1_AMIC_DISABLE", "CH1_AMIC1", "CH1_AMIC2", "CH1_AMIC3", "CH1_AMIC4", "CH1_AMIC5"
1734};
1735
1736static const struct soc_enum adc1_enum =
1737	SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 0,
1738			ARRAY_SIZE(adc1_mux_text), adc1_mux_text);
1739
1740static const struct snd_kcontrol_new tx_adc1_mux =
1741	SOC_DAPM_ENUM("ADC1 MUX Mux", adc1_enum);
1742
1743static const char * const adc2_mux_text[] = {
1744	"CH2_AMIC_DISABLE", "CH2_AMIC1", "CH2_AMIC2", "CH2_AMIC3", "CH2_AMIC4", "CH2_AMIC5"
1745};
1746
1747static const struct soc_enum adc2_enum =
1748	SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH12_MUX, 3,
1749			ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
1750
1751static const struct snd_kcontrol_new tx_adc2_mux =
1752	SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
1753
1754static const char * const adc3_mux_text[] = {
1755	"CH3_AMIC_DISABLE", "CH3_AMIC1", "CH3_AMIC3", "CH3_AMIC4", "CH3_AMIC5"
1756};
1757
1758static const struct soc_enum adc3_enum =
1759	SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 0,
1760			ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
1761
1762static const struct snd_kcontrol_new tx_adc3_mux =
1763	SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
1764
1765static const char * const adc4_mux_text[] = {
1766	"CH4_AMIC_DISABLE", "CH4_AMIC1", "CH4_AMIC3", "CH4_AMIC4", "CH4_AMIC5"
1767};
1768
1769static const struct soc_enum adc4_enum =
1770	SOC_ENUM_SINGLE(WCD939X_TX_NEW_CH34_MUX, 3,
1771			ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
1772
1773static const struct snd_kcontrol_new tx_adc4_mux =
1774	SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
1775
1776static const char * const rdac3_mux_text[] = {
1777	"RX3", "RX1"
1778};
1779
1780static const struct soc_enum rdac3_enum =
1781	SOC_ENUM_SINGLE(WCD939X_DIGITAL_CDC_EAR_PATH_CTL, 0,
1782			ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
1783
1784static const struct snd_kcontrol_new rx_rdac3_mux =
1785	SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
1786
1787static int wcd939x_get_swr_port(struct snd_kcontrol *kcontrol,
1788				struct snd_ctl_elem_value *ucontrol)
1789{
1790	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1791	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1792	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1793	struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1794	unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1795
1796	ucontrol->value.integer.value[0] = wcd->port_enable[portidx] ? 1 : 0;
1797
1798	return 0;
1799}
1800
1801static const char *version_to_str(u32 version)
1802{
1803	switch (version) {
1804	case WCD939X_VERSION_1_0:
1805		return __stringify(WCD939X_1_0);
1806	case WCD939X_VERSION_1_1:
1807		return __stringify(WCD939X_1_1);
1808	case WCD939X_VERSION_2_0:
1809		return __stringify(WCD939X_2_0);
1810	}
1811	return NULL;
1812}
1813
1814static int wcd939x_set_swr_port(struct snd_kcontrol *kcontrol,
1815				struct snd_ctl_elem_value *ucontrol)
1816{
1817	struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
1818	struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
1819	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(comp);
1820	struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[mixer->shift];
1821	unsigned int portidx = wcd->ch_info[mixer->reg].port_num;
1822
1823	wcd->port_enable[portidx] = !!ucontrol->value.integer.value[0];
1824
1825	wcd939x_connect_port(wcd, portidx, mixer->reg, wcd->port_enable[portidx]);
1826
1827	return 1;
1828}
1829
1830/* MBHC Related */
1831
1832static void wcd939x_mbhc_clk_setup(struct snd_soc_component *component,
1833				   bool enable)
1834{
1835	snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_1,
1836				      WCD939X_CTL_1_RCO_EN, enable);
1837}
1838
1839static void wcd939x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
1840					   bool enable)
1841{
1842	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
1843				      WCD939X_MBHC_ELECT_BIAS_EN, enable);
1844}
1845
1846static void wcd939x_mbhc_program_btn_thr(struct snd_soc_component *component,
1847					 int *btn_low, int *btn_high,
1848					 int num_btn, bool is_micbias)
1849{
1850	int i, vth;
1851
1852	if (num_btn > WCD_MBHC_DEF_BUTTONS) {
1853		dev_err(component->dev, "%s: invalid number of buttons: %d\n",
1854			__func__, num_btn);
1855		return;
1856	}
1857
1858	for (i = 0; i < num_btn; i++) {
1859		vth = (btn_high[i] * 2) / 25;
1860		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_BTN0 + i,
1861					      WCD939X_MBHC_BTN0_VTH, vth);
1862		dev_dbg(component->dev, "%s: btn_high[%d]: %d, vth: %d\n",
1863			__func__, i, btn_high[i], vth);
1864	}
1865}
1866
1867static bool wcd939x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
1868{
1869	if (micb_num == MIC_BIAS_2) {
1870		u8 val;
1871
1872		val = FIELD_GET(WCD939X_MICB_ENABLE,
1873				snd_soc_component_read(component, WCD939X_ANA_MICB2));
1874		if (val == MICB_BIAS_ENABLE)
1875			return true;
1876	}
1877
1878	return false;
1879}
1880
1881static void wcd939x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
1882					       int pull_up_cur)
1883{
1884	/* Default pull up current to 2uA */
1885	if (pull_up_cur > HS_PULLUP_I_OFF ||
1886	    pull_up_cur < HS_PULLUP_I_3P0_UA ||
1887	    pull_up_cur == HS_PULLUP_I_DEFAULT)
1888		pull_up_cur = HS_PULLUP_I_2P0_UA;
1889
1890	dev_dbg(component->dev, "%s: HS pull up current:%d\n",
1891		__func__, pull_up_cur);
1892
1893	snd_soc_component_write_field(component, WCD939X_MBHC_NEW_INT_MECH_DET_CURRENT,
1894				      WCD939X_MECH_DET_CURRENT_HSDET_PULLUP_CTL, pull_up_cur);
1895}
1896
1897static int wcd939x_mbhc_request_micbias(struct snd_soc_component *component,
1898					int micb_num, int req)
1899{
1900	return wcd939x_micbias_control(component, micb_num, req, false);
1901}
1902
1903static void wcd939x_mbhc_micb_ramp_control(struct snd_soc_component *component,
1904					   bool enable)
1905{
1906	if (enable) {
1907		snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1908					      WCD939X_MICB2_RAMP_SHIFT_CTL, 3);
1909		snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1910					      WCD939X_MICB2_RAMP_RAMP_ENABLE, true);
1911	} else {
1912		snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1913					      WCD939X_MICB2_RAMP_RAMP_ENABLE, false);
1914		snd_soc_component_write_field(component, WCD939X_ANA_MICB2_RAMP,
1915					      WCD939X_MICB2_RAMP_SHIFT_CTL, 0);
1916	}
1917}
1918
1919static int wcd939x_get_micb_vout_ctl_val(u32 micb_mv)
1920{
1921	/* min micbias voltage is 1V and maximum is 2.85V */
1922	if (micb_mv < 1000 || micb_mv > 2850) {
1923		pr_err("%s: unsupported micbias voltage\n", __func__);
1924		return -EINVAL;
1925	}
1926
1927	return (micb_mv - 1000) / 50;
1928}
1929
1930static int wcd939x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
1931					    int req_volt, int micb_num)
1932{
1933	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
1934	unsigned int micb_reg, cur_vout_ctl, micb_en;
1935	int req_vout_ctl;
1936	int ret = 0;
1937
1938	switch (micb_num) {
1939	case MIC_BIAS_1:
1940		micb_reg = WCD939X_ANA_MICB1;
1941		break;
1942	case MIC_BIAS_2:
1943		micb_reg = WCD939X_ANA_MICB2;
1944		break;
1945	case MIC_BIAS_3:
1946		micb_reg = WCD939X_ANA_MICB3;
1947		break;
1948	case MIC_BIAS_4:
1949		micb_reg = WCD939X_ANA_MICB4;
1950		break;
1951	default:
1952		return -EINVAL;
1953	}
1954	mutex_lock(&wcd939x->micb_lock);
1955
1956	/*
1957	 * If requested micbias voltage is same as current micbias
1958	 * voltage, then just return. Otherwise, adjust voltage as
1959	 * per requested value. If micbias is already enabled, then
1960	 * to avoid slow micbias ramp-up or down enable pull-up
1961	 * momentarily, change the micbias value and then re-enable
1962	 * micbias.
1963	 */
1964	micb_en = snd_soc_component_read_field(component, micb_reg,
1965					       WCD939X_MICB_ENABLE);
1966	cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
1967						    WCD939X_MICB_VOUT_CTL);
1968
1969	req_vout_ctl = wcd939x_get_micb_vout_ctl_val(req_volt);
1970	if (req_vout_ctl < 0) {
1971		ret = req_vout_ctl;
1972		goto exit;
1973	}
1974
1975	if (cur_vout_ctl == req_vout_ctl) {
1976		ret = 0;
1977		goto exit;
1978	}
1979
1980	dev_dbg(component->dev, "%s: micb_num: %d, cur_mv: %d, req_mv: %d, micb_en: %d\n",
1981		__func__, micb_num, WCD_VOUT_CTL_TO_MICB(cur_vout_ctl),
1982		 req_volt, micb_en);
1983
1984	if (micb_en == MICB_BIAS_ENABLE)
1985		snd_soc_component_write_field(component, micb_reg,
1986					      WCD939X_MICB_ENABLE,
1987					      MICB_BIAS_PULL_DOWN);
1988
1989	snd_soc_component_write_field(component, micb_reg,
1990				      WCD939X_MICB_VOUT_CTL, req_vout_ctl);
1991
1992	if (micb_en == MICB_BIAS_ENABLE) {
1993		snd_soc_component_write_field(component, micb_reg,
1994					      WCD939X_MICB_ENABLE,
1995					      MICB_BIAS_ENABLE);
1996		/*
1997		 * Add 2ms delay as per HW requirement after enabling
1998		 * micbias
1999		 */
2000		usleep_range(2000, 2100);
2001	}
2002
2003exit:
2004	mutex_unlock(&wcd939x->micb_lock);
2005	return ret;
2006}
2007
2008static int wcd939x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2009						int micb_num, bool req_en)
2010{
2011	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2012	int micb_mv;
2013
2014	if (micb_num != MIC_BIAS_2)
2015		return -EINVAL;
2016	/*
2017	 * If device tree micbias level is already above the minimum
2018	 * voltage needed to detect threshold microphone, then do
2019	 * not change the micbias, just return.
2020	 */
2021	if (wcd939x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2022		return 0;
2023
2024	micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd939x->micb2_mv;
2025
2026	return wcd939x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2027}
2028
2029/* Selected by WCD939X_MBHC_GET_C1() */
2030static const s16 wcd939x_wcd_mbhc_d1_a[4] = {
2031	0, 30, 30, 6
2032};
2033
2034/* Selected by zdet_param.noff */
2035static const int wcd939x_mbhc_mincode_param[] = {
2036	3277, 1639, 820, 410, 205, 103, 52, 26
2037};
2038
2039static const struct zdet_param wcd939x_mbhc_zdet_param = {
2040	.ldo_ctl = 4,
2041	.noff = 0,
2042	.nshift = 6,
2043	.btn5 = 0x18,
2044	.btn6 = 0x60,
2045	.btn7 = 0x78,
2046};
2047
2048static void wcd939x_mbhc_get_result_params(struct snd_soc_component *component,
2049					   int32_t *zdet)
2050{
2051	const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2052	s32 x1, d1, denom;
2053	int val;
2054	s16 c1;
2055	int i;
2056
2057	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2058				      WCD939X_MBHC_ZDET_ZDET_CHG_EN, true);
2059	for (i = 0; i < WCD939X_ZDET_NUM_MEASUREMENTS; i++) {
2060		val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2061						   WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2062		if (val & BIT(7))
2063			break;
2064	}
2065	val = val << 8;
2066	val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2067					    WCD939X_MBHC_RESULT_1_Z_RESULT_LSB);
2068	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2069				      WCD939X_MBHC_ZDET_ZDET_CHG_EN, false);
2070	x1 = WCD939X_MBHC_GET_X1(val);
2071	c1 = WCD939X_MBHC_GET_C1(val);
2072
2073	/* If ramp is not complete, give additional 5ms */
2074	if (c1 < 2 && x1)
2075		mdelay(5);
2076
2077	if (!c1 || !x1) {
2078		dev_dbg(component->dev,
2079			"%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2080			__func__, c1, x1);
2081		goto ramp_down;
2082	}
2083
2084	d1 = wcd939x_wcd_mbhc_d1_a[c1];
2085	denom = (x1 * d1) - (1 << (14 - zdet_param->noff));
2086	if (denom > 0)
2087		*zdet = (WCD939X_ANA_MBHC_ZDET_CONST * 1000) / denom;
2088	else if (x1 <  wcd939x_mbhc_mincode_param[zdet_param->noff])
2089		*zdet = WCD939X_ZDET_FLOATING_IMPEDANCE;
2090
2091	dev_dbg(component->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%d(milliOhm)\n",
2092		__func__, d1, c1, x1, *zdet);
2093ramp_down:
2094	i = 0;
2095	while (x1) {
2096		val = snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_1,
2097						   WCD939X_MBHC_RESULT_1_Z_RESULT_LSB) << 8;
2098		val |= snd_soc_component_read_field(component, WCD939X_ANA_MBHC_RESULT_2,
2099						    WCD939X_MBHC_RESULT_2_Z_RESULT_MSB);
2100		x1 = WCD939X_MBHC_GET_X1(val);
2101		i++;
2102		if (i == WCD939X_ZDET_NUM_MEASUREMENTS)
2103			break;
2104	}
2105}
2106
2107static void wcd939x_mbhc_zdet_ramp(struct snd_soc_component *component,
2108				   s32 *zl, int32_t *zr)
2109{
2110	const struct zdet_param *zdet_param = &wcd939x_mbhc_zdet_param;
2111	s32 zdet = 0;
2112
2113	snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2114				      WCD939X_ZDET_ANA_CTL_MAXV_CTL, zdet_param->ldo_ctl);
2115	snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN5, WCD939X_MBHC_BTN5_VTH,
2116				      zdet_param->btn5);
2117	snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN6, WCD939X_MBHC_BTN6_VTH,
2118				      zdet_param->btn6);
2119	snd_soc_component_update_bits(component, WCD939X_ANA_MBHC_BTN7, WCD939X_MBHC_BTN7_VTH,
2120				      zdet_param->btn7);
2121	snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL,
2122				      WCD939X_ZDET_ANA_CTL_RANGE_CTL, zdet_param->noff);
2123	snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2124				      WCD939X_ZDET_RAMP_CTL_TIME_CTL, zdet_param->nshift);
2125	snd_soc_component_write_field(component, WCD939X_MBHC_NEW_ZDET_RAMP_CTL,
2126				      WCD939X_ZDET_RAMP_CTL_ACC1_MIN_CTL, 6); /*acc1_min_63 */
2127
2128	if (!zl)
2129		goto z_right;
2130
2131	/* Start impedance measurement for HPH_L */
2132	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2133				      WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, true);
2134	dev_dbg(component->dev, "%s: ramp for HPH_L, noff = %d\n",
2135		__func__, zdet_param->noff);
2136	wcd939x_mbhc_get_result_params(component, &zdet);
2137	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2138				      WCD939X_MBHC_ZDET_ZDET_L_MEAS_EN, false);
2139
2140	*zl = zdet;
2141
2142z_right:
2143	if (!zr)
2144		return;
2145
2146	/* Start impedance measurement for HPH_R */
2147	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2148				      WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, true);
2149	dev_dbg(component->dev, "%s: ramp for HPH_R, noff = %d\n",
2150		__func__, zdet_param->noff);
2151	wcd939x_mbhc_get_result_params(component, &zdet);
2152	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ZDET,
2153				      WCD939X_MBHC_ZDET_ZDET_R_MEAS_EN, false);
2154
2155	*zr = zdet;
2156}
2157
2158static void wcd939x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2159				       s32 *z_val, int flag_l_r)
2160{
2161	int q1_cal;
2162	s16 q1;
2163
2164	q1 = snd_soc_component_read(component, WCD939X_DIGITAL_EFUSE_REG_21 + flag_l_r);
2165	if (q1 & BIT(7))
2166		q1_cal = (10000 - ((q1 & GENMASK(6, 0)) * 10));
2167	else
2168		q1_cal = (10000 + (q1 * 10));
2169
2170	if (q1_cal > 0)
2171		*z_val = ((*z_val) * 10000) / q1_cal;
2172}
2173
2174static void wcd939x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2175					    u32 *zl, uint32_t *zr)
2176{
2177	struct wcd939x_priv *wcd939x = dev_get_drvdata(component->dev);
2178	unsigned int reg0, reg1, reg2, reg3, reg4;
2179	int z_mono, z_diff1, z_diff2;
2180	bool is_fsm_disable = false;
2181	s32 z1l, z1r, z1ls;
2182
2183	reg0 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN5);
2184	reg1 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN6);
2185	reg2 = snd_soc_component_read(component, WCD939X_ANA_MBHC_BTN7);
2186	reg3 = snd_soc_component_read(component, WCD939X_MBHC_CTL_CLK);
2187	reg4 = snd_soc_component_read(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL);
2188
2189	if (snd_soc_component_read_field(component, WCD939X_ANA_MBHC_ELECT,
2190					 WCD939X_MBHC_ELECT_FSM_EN)) {
2191		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2192					      WCD939X_MBHC_ELECT_FSM_EN, false);
2193		is_fsm_disable = true;
2194	}
2195
2196	/* For NO-jack, disable L_DET_EN before Z-det measurements */
2197	if (wcd939x->mbhc_cfg.hphl_swh)
2198		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2199					      WCD939X_MBHC_MECH_L_DET_EN, false);
2200
2201	/* Turn off 100k pull down on HPHL */
2202	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2203				      WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND,
2204				      false);
2205
2206	/*
2207	 * Disable surge protection before impedance detection.
2208	 * This is done to give correct value for high impedance.
2209	 */
2210	snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2211				      WCD939X_EN_EN_SURGE_PROTECTION_HPHR, false);
2212	snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2213				      WCD939X_EN_EN_SURGE_PROTECTION_HPHL, false);
2214
2215	/* 1ms delay needed after disable surge protection */
2216	usleep_range(1000, 1010);
2217
2218	/* First get impedance on Left */
2219	wcd939x_mbhc_zdet_ramp(component, &z1l, NULL);
2220	if (z1l == WCD939X_ZDET_FLOATING_IMPEDANCE || z1l > WCD939X_ZDET_VAL_100K) {
2221		*zl = WCD939X_ZDET_FLOATING_IMPEDANCE;
2222	} else {
2223		*zl = z1l / 1000;
2224		wcd939x_wcd_mbhc_qfuse_cal(component, zl, 0);
2225	}
2226	dev_dbg(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2227		__func__, *zl);
2228
2229	/* Start of right impedance ramp and calculation */
2230	wcd939x_mbhc_zdet_ramp(component, NULL, &z1r);
2231	if (z1r == WCD939X_ZDET_FLOATING_IMPEDANCE || z1r > WCD939X_ZDET_VAL_100K) {
2232		*zr = WCD939X_ZDET_FLOATING_IMPEDANCE;
2233	} else {
2234		*zr = z1r / 1000;
2235		wcd939x_wcd_mbhc_qfuse_cal(component, zr, 1);
2236	}
2237	dev_dbg(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2238		__func__, *zr);
2239
2240	/* Mono/stereo detection */
2241	if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE &&
2242	    *zr == WCD939X_ZDET_FLOATING_IMPEDANCE) {
2243		dev_dbg(component->dev,
2244			"%s: plug type is invalid or extension cable\n",
2245			__func__);
2246		goto zdet_complete;
2247	}
2248
2249	if (*zl == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2250	    *zr == WCD939X_ZDET_FLOATING_IMPEDANCE ||
2251	    (*zl < WCD_MONO_HS_MIN_THR && *zr > WCD_MONO_HS_MIN_THR) ||
2252	    (*zl > WCD_MONO_HS_MIN_THR && *zr < WCD_MONO_HS_MIN_THR)) {
2253		dev_dbg(component->dev,
2254			"%s: Mono plug type with one ch floating or shorted to GND\n",
2255			__func__);
2256		wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2257		goto zdet_complete;
2258	}
2259
2260	snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2261				      WCD939X_R_ATEST_HPH_GND_OVR, true);
2262	snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2263				      WCD939X_PA_CTL2_HPHPA_GND_R, true);
2264	wcd939x_mbhc_zdet_ramp(component, &z1ls, NULL);
2265	snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2266				      WCD939X_PA_CTL2_HPHPA_GND_R, false);
2267	snd_soc_component_write_field(component, WCD939X_HPH_R_ATEST,
2268				      WCD939X_R_ATEST_HPH_GND_OVR, false);
2269
2270	z1ls /= 1000;
2271	wcd939x_wcd_mbhc_qfuse_cal(component, &z1ls, 0);
2272
2273	/* Parallel of left Z and 9 ohm pull down resistor */
2274	z_mono = (*zl * 9) / (*zl + 9);
2275	z_diff1 = z1ls > z_mono ? z1ls - z_mono : z_mono - z1ls;
2276	z_diff2 = *zl > z1ls ? *zl - z1ls : z1ls - *zl;
2277	if ((z_diff1 * (*zl + z1ls)) > (z_diff2 * (z1ls + z_mono))) {
2278		dev_dbg(component->dev, "%s: stereo plug type detected\n",
2279			__func__);
2280		wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_STEREO);
2281	} else {
2282		dev_dbg(component->dev, "%s: MONO plug type detected\n",
2283			__func__);
2284		wcd_mbhc_set_hph_type(wcd939x->wcd_mbhc, WCD_MBHC_HPH_MONO);
2285	}
2286
2287	/* Enable surge protection again after impedance detection */
2288	snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2289				      WCD939X_EN_EN_SURGE_PROTECTION_HPHR, true);
2290	snd_soc_component_write_field(component, WCD939X_HPH_SURGE_EN,
2291				      WCD939X_EN_EN_SURGE_PROTECTION_HPHL, true);
2292
2293zdet_complete:
2294	snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN5, reg0);
2295	snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN6, reg1);
2296	snd_soc_component_write(component, WCD939X_ANA_MBHC_BTN7, reg2);
2297
2298	/* Turn on 100k pull down on HPHL */
2299	snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2300				      WCD939X_MBHC_MECH_SW_HPH_L_P_100K_TO_GND, true);
2301
2302	/* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2303	if (wcd939x->mbhc_cfg.hphl_swh)
2304		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2305					      WCD939X_MBHC_MECH_L_DET_EN, true);
2306
2307	snd_soc_component_write(component, WCD939X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2308	snd_soc_component_write(component, WCD939X_MBHC_CTL_CLK, reg3);
2309
2310	if (is_fsm_disable)
2311		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_ELECT,
2312					      WCD939X_MBHC_ELECT_FSM_EN, true);
2313}
2314
2315static void wcd939x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2316				      bool enable)
2317{
2318	if (enable) {
2319		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2320					      WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2321					      true);
2322		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2323					      WCD939X_MBHC_MECH_GND_DET_EN, true);
2324	} else {
2325		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2326					      WCD939X_MBHC_MECH_GND_DET_EN, false);
2327		snd_soc_component_write_field(component, WCD939X_ANA_MBHC_MECH,
2328					      WCD939X_MBHC_MECH_MECH_HS_G_PULLUP_COMP_EN,
2329					      false);
2330	}
2331}
2332
2333static void wcd939x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2334					    bool enable)
2335{
2336	snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2337				      WCD939X_PA_CTL2_HPHPA_GND_R, enable);
2338	snd_soc_component_write_field(component, WCD939X_HPH_PA_CTL2,
2339				      WCD939X_PA_CTL2_HPHPA_GND_L, enable);
2340}
2341
2342static void wcd939x_mbhc_moisture_config(struct snd_soc_component *component)
2343{
2344	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2345
2346	if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2347		snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2348					      WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2349		return;
2350	}
2351
2352	/* Do not enable moisture detection if jack type is NC */
2353	if (!wcd939x->mbhc_cfg.hphl_swh) {
2354		dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2355			__func__);
2356		snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2357					      WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2358		return;
2359	}
2360
2361	snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2362				      WCD939X_CTL_2_M_RTH_CTL, wcd939x->mbhc_cfg.moist_rref);
2363}
2364
2365static void wcd939x_mbhc_moisture_detect_en(struct snd_soc_component *component, bool enable)
2366{
2367	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2368
2369	if (enable)
2370		snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2371					      WCD939X_CTL_2_M_RTH_CTL,
2372					      wcd939x->mbhc_cfg.moist_rref);
2373	else
2374		snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2375					      WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2376}
2377
2378static bool wcd939x_mbhc_get_moisture_status(struct snd_soc_component *component)
2379{
2380	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2381	bool ret = false;
2382
2383	if (wcd939x->mbhc_cfg.moist_rref == R_OFF || wcd939x->typec_analog_mux) {
2384		snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2385					      WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2386		goto done;
2387	}
2388
2389	/* Do not enable moisture detection if jack type is NC */
2390	if (!wcd939x->mbhc_cfg.hphl_swh) {
2391		dev_dbg(component->dev, "%s: disable moisture detection for NC\n",
2392			__func__);
2393		snd_soc_component_write_field(component, WCD939X_MBHC_NEW_CTL_2,
2394					      WCD939X_CTL_2_M_RTH_CTL, R_OFF);
2395		goto done;
2396	}
2397
2398	/*
2399	 * If moisture_en is already enabled, then skip to plug type
2400	 * detection.
2401	 */
2402	if (snd_soc_component_read_field(component, WCD939X_MBHC_NEW_CTL_2,
2403					 WCD939X_CTL_2_M_RTH_CTL))
2404		goto done;
2405
2406	wcd939x_mbhc_moisture_detect_en(component, true);
2407
2408	/* Read moisture comparator status, invert of status bit */
2409	ret = !snd_soc_component_read_field(component, WCD939X_MBHC_NEW_FSM_STATUS,
2410					    WCD939X_FSM_STATUS_HS_M_COMP_STATUS);
2411done:
2412	return ret;
2413}
2414
2415static void wcd939x_mbhc_moisture_polling_ctrl(struct snd_soc_component *component,
2416					       bool enable)
2417{
2418	snd_soc_component_write_field(component,
2419				      WCD939X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,
2420				      WCD939X_MOISTURE_DET_POLLING_CTRL_MOIST_EN_POLLING,
2421				      enable);
2422}
2423
2424static const struct wcd_mbhc_cb mbhc_cb = {
2425	.clk_setup = wcd939x_mbhc_clk_setup,
2426	.mbhc_bias = wcd939x_mbhc_mbhc_bias_control,
2427	.set_btn_thr = wcd939x_mbhc_program_btn_thr,
2428	.micbias_enable_status = wcd939x_mbhc_micb_en_status,
2429	.hph_pull_up_control_v2 = wcd939x_mbhc_hph_l_pull_up_control,
2430	.mbhc_micbias_control = wcd939x_mbhc_request_micbias,
2431	.mbhc_micb_ramp_control = wcd939x_mbhc_micb_ramp_control,
2432	.mbhc_micb_ctrl_thr_mic = wcd939x_mbhc_micb_ctrl_threshold_mic,
2433	.compute_impedance = wcd939x_wcd_mbhc_calc_impedance,
2434	.mbhc_gnd_det_ctrl = wcd939x_mbhc_gnd_det_ctrl,
2435	.hph_pull_down_ctrl = wcd939x_mbhc_hph_pull_down_ctrl,
2436	.mbhc_moisture_config = wcd939x_mbhc_moisture_config,
2437	.mbhc_get_moisture_status = wcd939x_mbhc_get_moisture_status,
2438	.mbhc_moisture_polling_ctrl = wcd939x_mbhc_moisture_polling_ctrl,
2439	.mbhc_moisture_detect_en = wcd939x_mbhc_moisture_detect_en,
2440};
2441
2442static int wcd939x_get_hph_type(struct snd_kcontrol *kcontrol,
2443				struct snd_ctl_elem_value *ucontrol)
2444{
2445	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2446	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2447
2448	ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd939x->wcd_mbhc);
2449
2450	return 0;
2451}
2452
2453static int wcd939x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2454				     struct snd_ctl_elem_value *ucontrol)
2455{
2456	struct soc_mixer_control *mc = (struct soc_mixer_control *)(kcontrol->private_value);
2457	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2458	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2459	bool hphr = mc->shift;
2460	u32 zl, zr;
2461
2462	wcd_mbhc_get_impedance(wcd939x->wcd_mbhc, &zl, &zr);
2463	dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2464	ucontrol->value.integer.value[0] = hphr ? zr : zl;
2465
2466	return 0;
2467}
2468
2469static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2470	SOC_SINGLE_EXT("HPH Type", 0, 0, UINT_MAX, 0,
2471		       wcd939x_get_hph_type, NULL),
2472};
2473
2474static const struct snd_kcontrol_new impedance_detect_controls[] = {
2475	SOC_SINGLE_EXT("HPHL Impedance", 0, 0, UINT_MAX, 0,
2476		       wcd939x_hph_impedance_get, NULL),
2477	SOC_SINGLE_EXT("HPHR Impedance", 0, 1, UINT_MAX, 0,
2478		       wcd939x_hph_impedance_get, NULL),
2479};
2480
2481static int wcd939x_mbhc_init(struct snd_soc_component *component)
2482{
2483	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2484	struct wcd_mbhc_intr *intr_ids = &wcd939x->intr_ids;
2485
2486	intr_ids->mbhc_sw_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2487						     WCD939X_IRQ_MBHC_SW_DET);
2488	intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2489							    WCD939X_IRQ_MBHC_BUTTON_PRESS_DET);
2490	intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2491							      WCD939X_IRQ_MBHC_BUTTON_RELEASE_DET);
2492	intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2493							 WCD939X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
2494	intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(wcd939x->irq_chip,
2495							 WCD939X_IRQ_MBHC_ELECT_INS_REM_DET);
2496	intr_ids->hph_left_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2497						     WCD939X_IRQ_HPHL_OCP_INT);
2498	intr_ids->hph_right_ocp = regmap_irq_get_virq(wcd939x->irq_chip,
2499						      WCD939X_IRQ_HPHR_OCP_INT);
2500
2501	wcd939x->wcd_mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
2502	if (IS_ERR(wcd939x->wcd_mbhc))
2503		return PTR_ERR(wcd939x->wcd_mbhc);
2504
2505	snd_soc_add_component_controls(component, impedance_detect_controls,
2506				       ARRAY_SIZE(impedance_detect_controls));
2507	snd_soc_add_component_controls(component, hph_type_detect_controls,
2508				       ARRAY_SIZE(hph_type_detect_controls));
2509
2510	return 0;
2511}
2512
2513static void wcd939x_mbhc_deinit(struct snd_soc_component *component)
2514{
2515	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2516
2517	wcd_mbhc_deinit(wcd939x->wcd_mbhc);
2518}
2519
2520/* END MBHC */
2521
2522static const struct snd_kcontrol_new wcd939x_snd_controls[] = {
2523	/* RX Path */
2524	SOC_SINGLE_EXT("HPHL_COMP Switch", WCD939X_COMP_L, 0, 1, 0,
2525		       wcd939x_get_compander, wcd939x_set_compander),
2526	SOC_SINGLE_EXT("HPHR_COMP Switch", WCD939X_COMP_R, 1, 1, 0,
2527		       wcd939x_get_compander, wcd939x_set_compander),
2528	SOC_SINGLE_EXT("HPHL Switch", WCD939X_HPH_L, 0, 1, 0,
2529		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2530	SOC_SINGLE_EXT("HPHR Switch", WCD939X_HPH_R, 0, 1, 0,
2531		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2532	SOC_SINGLE_EXT("CLSH Switch", WCD939X_CLSH, 0, 1, 0,
2533		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2534	SOC_SINGLE_EXT("LO Switch", WCD939X_LO, 0, 1, 0,
2535		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2536	SOC_SINGLE_EXT("DSD_L Switch", WCD939X_DSD_L, 0, 1, 0,
2537		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2538	SOC_SINGLE_EXT("DSD_R Switch", WCD939X_DSD_R, 0, 1, 0,
2539		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2540	SOC_SINGLE_TLV("HPHL Volume", WCD939X_HPH_L_EN, 0, 20, 1, line_gain),
2541	SOC_SINGLE_TLV("HPHR Volume", WCD939X_HPH_R_EN, 0, 20, 1, line_gain),
2542	SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2543		       wcd939x_ldoh_get, wcd939x_ldoh_put),
2544
2545	/* TX Path */
2546	SOC_SINGLE_EXT("ADC1 Switch", WCD939X_ADC1, 1, 1, 0,
2547		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2548	SOC_SINGLE_EXT("ADC2 Switch", WCD939X_ADC2, 1, 1, 0,
2549		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2550	SOC_SINGLE_EXT("ADC3 Switch", WCD939X_ADC3, 1, 1, 0,
2551		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2552	SOC_SINGLE_EXT("ADC4 Switch", WCD939X_ADC4, 1, 1, 0,
2553		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2554	SOC_SINGLE_EXT("DMIC0 Switch", WCD939X_DMIC0, 1, 1, 0,
2555		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2556	SOC_SINGLE_EXT("DMIC1 Switch", WCD939X_DMIC1, 1, 1, 0,
2557		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2558	SOC_SINGLE_EXT("MBHC Switch", WCD939X_MBHC, 1, 1, 0,
2559		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2560	SOC_SINGLE_EXT("DMIC2 Switch", WCD939X_DMIC2, 1, 1, 0,
2561		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2562	SOC_SINGLE_EXT("DMIC3 Switch", WCD939X_DMIC3, 1, 1, 0,
2563		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2564	SOC_SINGLE_EXT("DMIC4 Switch", WCD939X_DMIC4, 1, 1, 0,
2565		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2566	SOC_SINGLE_EXT("DMIC5 Switch", WCD939X_DMIC5, 1, 1, 0,
2567		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2568	SOC_SINGLE_EXT("DMIC6 Switch", WCD939X_DMIC6, 1, 1, 0,
2569		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2570	SOC_SINGLE_EXT("DMIC7 Switch", WCD939X_DMIC7, 1, 1, 0,
2571		       wcd939x_get_swr_port, wcd939x_set_swr_port),
2572	SOC_SINGLE_TLV("ADC1 Volume", WCD939X_ANA_TX_CH1, 0, 20, 0,
2573		       analog_gain),
2574	SOC_SINGLE_TLV("ADC2 Volume", WCD939X_ANA_TX_CH2, 0, 20, 0,
2575		       analog_gain),
2576	SOC_SINGLE_TLV("ADC3 Volume", WCD939X_ANA_TX_CH3, 0, 20, 0,
2577		       analog_gain),
2578	SOC_SINGLE_TLV("ADC4 Volume", WCD939X_ANA_TX_CH4, 0, 20, 0,
2579		       analog_gain),
2580};
2581
2582static const struct snd_soc_dapm_widget wcd939x_dapm_widgets[] = {
2583	/*input widgets*/
2584	SND_SOC_DAPM_INPUT("AMIC1"),
2585	SND_SOC_DAPM_INPUT("AMIC2"),
2586	SND_SOC_DAPM_INPUT("AMIC3"),
2587	SND_SOC_DAPM_INPUT("AMIC4"),
2588	SND_SOC_DAPM_INPUT("AMIC5"),
2589
2590	SND_SOC_DAPM_MIC("Analog Mic1", NULL),
2591	SND_SOC_DAPM_MIC("Analog Mic2", NULL),
2592	SND_SOC_DAPM_MIC("Analog Mic3", NULL),
2593	SND_SOC_DAPM_MIC("Analog Mic4", NULL),
2594	SND_SOC_DAPM_MIC("Analog Mic5", NULL),
2595
2596	/* TX widgets */
2597	SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2598			   wcd939x_codec_enable_adc,
2599			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2600	SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2601			   wcd939x_codec_enable_adc,
2602			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2603	SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2604			   wcd939x_codec_enable_adc,
2605			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2606	SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
2607			   wcd939x_codec_enable_adc,
2608			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2609	SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2610			   wcd939x_codec_enable_dmic,
2611			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2612	SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2613			   wcd939x_codec_enable_dmic,
2614			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2615	SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2616			   wcd939x_codec_enable_dmic,
2617			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2618	SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2619			   wcd939x_codec_enable_dmic,
2620			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2621	SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2622			   wcd939x_codec_enable_dmic,
2623			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2624	SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2625			   wcd939x_codec_enable_dmic,
2626			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2627	SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
2628			   wcd939x_codec_enable_dmic,
2629			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2630	SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
2631			   wcd939x_codec_enable_dmic,
2632			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2633
2634	SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0, NULL, 0,
2635			     wcd939x_adc_enable_req,
2636			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2637	SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0, NULL, 0,
2638			     wcd939x_adc_enable_req,
2639			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2640	SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0, NULL, 0,
2641			     wcd939x_adc_enable_req,
2642			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2643	SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
2644			     wcd939x_adc_enable_req,
2645			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2646
2647	SND_SOC_DAPM_MUX("ADC1 MUX", SND_SOC_NOPM, 0, 0, &tx_adc1_mux),
2648	SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2649	SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
2650	SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
2651
2652	/* tx mixers */
2653	SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0,
2654			     adc1_switch, ARRAY_SIZE(adc1_switch), wcd939x_tx_swr_ctrl,
2655			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2656	SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0,
2657			     adc2_switch, ARRAY_SIZE(adc2_switch), wcd939x_tx_swr_ctrl,
2658			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2659	SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0,
2660			     adc3_switch, ARRAY_SIZE(adc3_switch), wcd939x_tx_swr_ctrl,
2661			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2662	SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0,
2663			     adc4_switch, ARRAY_SIZE(adc4_switch), wcd939x_tx_swr_ctrl,
2664			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2665	SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0,
2666			     dmic1_switch, ARRAY_SIZE(dmic1_switch), wcd939x_tx_swr_ctrl,
2667			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2668	SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0,
2669			     dmic2_switch, ARRAY_SIZE(dmic2_switch), wcd939x_tx_swr_ctrl,
2670			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2671	SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0,
2672			     dmic3_switch, ARRAY_SIZE(dmic3_switch), wcd939x_tx_swr_ctrl,
2673			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2674	SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0,
2675			     dmic4_switch, ARRAY_SIZE(dmic4_switch), wcd939x_tx_swr_ctrl,
2676			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2677	SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0,
2678			     dmic5_switch, ARRAY_SIZE(dmic5_switch), wcd939x_tx_swr_ctrl,
2679			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2680	SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0,
2681			     dmic6_switch, ARRAY_SIZE(dmic6_switch), wcd939x_tx_swr_ctrl,
2682			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2683	SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0,
2684			     dmic7_switch, ARRAY_SIZE(dmic7_switch), wcd939x_tx_swr_ctrl,
2685			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2686	SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0,
2687			     dmic8_switch, ARRAY_SIZE(dmic8_switch), wcd939x_tx_swr_ctrl,
2688			     SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2689
2690	/* micbias widgets */
2691	SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2692			    wcd939x_codec_enable_micbias,
2693			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2694			    SND_SOC_DAPM_POST_PMD),
2695	SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2696			    wcd939x_codec_enable_micbias,
2697			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2698			    SND_SOC_DAPM_POST_PMD),
2699	SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2700			    wcd939x_codec_enable_micbias,
2701			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2702			    SND_SOC_DAPM_POST_PMD),
2703	SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2704			    wcd939x_codec_enable_micbias,
2705			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2706			    SND_SOC_DAPM_POST_PMD),
2707
2708	/* micbias pull up widgets */
2709	SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
2710			    wcd939x_codec_enable_micbias_pullup,
2711			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2712			    SND_SOC_DAPM_POST_PMD),
2713	SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
2714			    wcd939x_codec_enable_micbias_pullup,
2715			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2716			    SND_SOC_DAPM_POST_PMD),
2717	SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
2718			    wcd939x_codec_enable_micbias_pullup,
2719			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2720			    SND_SOC_DAPM_POST_PMD),
2721	SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
2722			    wcd939x_codec_enable_micbias_pullup,
2723			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2724			    SND_SOC_DAPM_POST_PMD),
2725
2726	/* output widgets tx */
2727	SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
2728	SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
2729	SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
2730	SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
2731	SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
2732	SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
2733	SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
2734	SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
2735	SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
2736	SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
2737	SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
2738	SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
2739
2740	SND_SOC_DAPM_INPUT("IN1_HPHL"),
2741	SND_SOC_DAPM_INPUT("IN2_HPHR"),
2742	SND_SOC_DAPM_INPUT("IN3_EAR"),
2743
2744	/* rx widgets */
2745	SND_SOC_DAPM_PGA_E("EAR PGA", WCD939X_ANA_EAR, 7, 0, NULL, 0,
2746			   wcd939x_codec_enable_ear_pa,
2747			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2748			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2749	SND_SOC_DAPM_PGA_E("HPHL PGA", WCD939X_ANA_HPH, 7, 0, NULL, 0,
2750			   wcd939x_codec_enable_hphl_pa,
2751			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2752			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2753	SND_SOC_DAPM_PGA_E("HPHR PGA", WCD939X_ANA_HPH, 6, 0, NULL, 0,
2754			   wcd939x_codec_enable_hphr_pa,
2755			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2756			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2757
2758	SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
2759			   wcd939x_codec_hphl_dac_event,
2760			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2761			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2762	SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
2763			   wcd939x_codec_hphr_dac_event,
2764			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2765			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2766	SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
2767			   wcd939x_codec_ear_dac_event,
2768			   SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2769			   SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
2770
2771	SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
2772
2773	SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
2774	SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
2775			    wcd939x_codec_enable_rxclk,
2776			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
2777			    SND_SOC_DAPM_POST_PMD),
2778
2779	SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
2780
2781	SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2782	SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2783	SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
2784
2785	/* rx mixer widgets */
2786	SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
2787			   ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
2788	SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
2789			   hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
2790	SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
2791			   hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
2792
2793	/* output widgets rx */
2794	SND_SOC_DAPM_OUTPUT("EAR"),
2795	SND_SOC_DAPM_OUTPUT("HPHL"),
2796	SND_SOC_DAPM_OUTPUT("HPHR"),
2797};
2798
2799static const struct snd_soc_dapm_route wcd939x_audio_map[] = {
2800	/* TX Path */
2801	{"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
2802	{"ADC1_MIXER", "Switch", "ADC1 REQ"},
2803	{"ADC1 REQ", NULL, "ADC1"},
2804	{"ADC1", NULL, "ADC1 MUX"},
2805	{"ADC1 MUX", "CH1_AMIC1", "AMIC1"},
2806	{"ADC1 MUX", "CH1_AMIC2", "AMIC2"},
2807	{"ADC1 MUX", "CH1_AMIC3", "AMIC3"},
2808	{"ADC1 MUX", "CH1_AMIC4", "AMIC4"},
2809	{"ADC1 MUX", "CH1_AMIC5", "AMIC5"},
2810
2811	{"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
2812	{"ADC2_MIXER", "Switch", "ADC2 REQ"},
2813	{"ADC2 REQ", NULL, "ADC2"},
2814	{"ADC2", NULL, "ADC2 MUX"},
2815	{"ADC2 MUX", "CH2_AMIC1", "AMIC1"},
2816	{"ADC2 MUX", "CH2_AMIC2", "AMIC2"},
2817	{"ADC2 MUX", "CH2_AMIC3", "AMIC3"},
2818	{"ADC2 MUX", "CH2_AMIC4", "AMIC4"},
2819	{"ADC2 MUX", "CH2_AMIC5", "AMIC5"},
2820
2821	{"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
2822	{"ADC3_MIXER", "Switch", "ADC3 REQ"},
2823	{"ADC3 REQ", NULL, "ADC3"},
2824	{"ADC3", NULL, "ADC3 MUX"},
2825	{"ADC3 MUX", "CH3_AMIC1", "AMIC1"},
2826	{"ADC3 MUX", "CH3_AMIC3", "AMIC3"},
2827	{"ADC3 MUX", "CH3_AMIC4", "AMIC4"},
2828	{"ADC3 MUX", "CH3_AMIC5", "AMIC5"},
2829
2830	{"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
2831	{"ADC4_MIXER", "Switch", "ADC4 REQ"},
2832	{"ADC4 REQ", NULL, "ADC4"},
2833	{"ADC4", NULL, "ADC4 MUX"},
2834	{"ADC4 MUX", "CH4_AMIC1", "AMIC1"},
2835	{"ADC4 MUX", "CH4_AMIC3", "AMIC3"},
2836	{"ADC4 MUX", "CH4_AMIC4", "AMIC4"},
2837	{"ADC4 MUX", "CH4_AMIC5", "AMIC5"},
2838
2839	{"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
2840	{"DMIC1_MIXER", "Switch", "DMIC1"},
2841
2842	{"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
2843	{"DMIC2_MIXER", "Switch", "DMIC2"},
2844
2845	{"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
2846	{"DMIC3_MIXER", "Switch", "DMIC3"},
2847
2848	{"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
2849	{"DMIC4_MIXER", "Switch", "DMIC4"},
2850
2851	{"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
2852	{"DMIC5_MIXER", "Switch", "DMIC5"},
2853
2854	{"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
2855	{"DMIC6_MIXER", "Switch", "DMIC6"},
2856
2857	{"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
2858	{"DMIC7_MIXER", "Switch", "DMIC7"},
2859
2860	{"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
2861	{"DMIC8_MIXER", "Switch", "DMIC8"},
2862
2863	/* RX Path */
2864	{"IN1_HPHL", NULL, "VDD_BUCK"},
2865	{"IN1_HPHL", NULL, "CLS_H_PORT"},
2866
2867	{"RX1", NULL, "IN1_HPHL"},
2868	{"RX1", NULL, "RXCLK"},
2869	{"RDAC1", NULL, "RX1"},
2870	{"HPHL_RDAC", "Switch", "RDAC1"},
2871	{"HPHL PGA", NULL, "HPHL_RDAC"},
2872	{"HPHL", NULL, "HPHL PGA"},
2873
2874	{"IN2_HPHR", NULL, "VDD_BUCK"},
2875	{"IN2_HPHR", NULL, "CLS_H_PORT"},
2876	{"RX2", NULL, "IN2_HPHR"},
2877	{"RDAC2", NULL, "RX2"},
2878	{"RX2", NULL, "RXCLK"},
2879	{"HPHR_RDAC", "Switch", "RDAC2"},
2880	{"HPHR PGA", NULL, "HPHR_RDAC"},
2881	{"HPHR", NULL, "HPHR PGA"},
2882
2883	{"IN3_EAR", NULL, "VDD_BUCK"},
2884	{"RX3", NULL, "IN3_EAR"},
2885	{"RX3", NULL, "RXCLK"},
2886
2887	{"RDAC3_MUX", "RX3", "RX3"},
2888	{"RDAC3_MUX", "RX1", "RX1"},
2889	{"RDAC3", NULL, "RDAC3_MUX"},
2890	{"EAR_RDAC", "Switch", "RDAC3"},
2891	{"EAR PGA", NULL, "EAR_RDAC"},
2892	{"EAR", NULL, "EAR PGA"},
2893};
2894
2895static int wcd939x_set_micbias_data(struct wcd939x_priv *wcd939x)
2896{
2897	int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2898
2899	/* set micbias voltage */
2900	vout_ctl_1 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb1_mv);
2901	vout_ctl_2 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb2_mv);
2902	vout_ctl_3 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb3_mv);
2903	vout_ctl_4 = wcd939x_get_micb_vout_ctl_val(wcd939x->micb4_mv);
2904	if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
2905		return -EINVAL;
2906
2907	regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB1,
2908			   WCD939X_MICB_VOUT_CTL, vout_ctl_1);
2909	regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB2,
2910			   WCD939X_MICB_VOUT_CTL, vout_ctl_2);
2911	regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB3,
2912			   WCD939X_MICB_VOUT_CTL, vout_ctl_3);
2913	regmap_update_bits(wcd939x->regmap, WCD939X_ANA_MICB4,
2914			   WCD939X_MICB_VOUT_CTL, vout_ctl_4);
2915
2916	return 0;
2917}
2918
2919static irqreturn_t wcd939x_wd_handle_irq(int irq, void *data)
2920{
2921	/*
2922	 * HPHR/HPHL/EAR Watchdog interrupt threaded handler
2923	 *
2924	 * Watchdog interrupts are expected to be enabled when switching
2925	 * on the HPHL/R and EAR RX PGA in order to make sure the interrupts
2926	 * are acked by the regmap_irq handler to allow PDM sync.
2927	 * We could leave those interrupts masked but we would not have
2928	 * any valid way to enable/disable them without violating irq layers.
2929	 *
2930	 * The HPHR/HPHL/EAR Watchdog interrupts are handled
2931	 * by regmap_irq, so requesting a threaded handler is the
2932	 * safest way to be able to ack those interrupts without
2933	 * colliding with the regmap_irq setup.
2934	 */
2935
2936	return IRQ_HANDLED;
2937}
2938
2939/*
2940 * Setup a virtual interrupt domain to hook regmap_irq
2941 * The root domain will have a single interrupt which mapping
2942 * will trigger the regmap_irq handler.
2943 *
2944 * root:
2945 *   wcd_irq_chip
2946 *     [0] wcd939x_regmap_irq_chip
2947 *       [0] MBHC_BUTTON_PRESS_DET
2948 *       [1] MBHC_BUTTON_RELEASE_DET
2949 *       ...
2950 *       [16] HPHR_SURGE_DET_INT
2951 *
2952 * Interrupt trigger:
2953 *   soundwire_interrupt_callback()
2954 *   \-handle_nested_irq(0)
2955 *     \- regmap_irq_thread()
2956 *         \- handle_nested_irq(i)
2957 */
2958static const struct irq_chip wcd_irq_chip = {
2959	.name = "WCD939x",
2960};
2961
2962static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
2963			    irq_hw_number_t hw)
2964{
2965	irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
2966	irq_set_nested_thread(virq, 1);
2967	irq_set_noprobe(virq);
2968
2969	return 0;
2970}
2971
2972static const struct irq_domain_ops wcd_domain_ops = {
2973	.map = wcd_irq_chip_map,
2974};
2975
2976static int wcd939x_irq_init(struct wcd939x_priv *wcd, struct device *dev)
2977{
2978	wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
2979	if (!(wcd->virq)) {
2980		dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
2981		return -EINVAL;
2982	}
2983
2984	return devm_regmap_add_irq_chip(dev, wcd->regmap,
2985					irq_create_mapping(wcd->virq, 0),
2986					IRQF_ONESHOT, 0, &wcd939x_regmap_irq_chip,
2987					&wcd->irq_chip);
2988}
2989
2990static int wcd939x_soc_codec_probe(struct snd_soc_component *component)
2991{
2992	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
2993	struct sdw_slave *tx_sdw_dev = wcd939x->tx_sdw_dev;
2994	struct device *dev = component->dev;
2995	unsigned long time_left;
2996	int ret, i;
2997
2998	time_left = wait_for_completion_timeout(&tx_sdw_dev->initialization_complete,
2999						msecs_to_jiffies(2000));
3000	if (!time_left) {
3001		dev_err(dev, "soundwire device init timeout\n");
3002		return -ETIMEDOUT;
3003	}
3004
3005	snd_soc_component_init_regmap(component, wcd939x->regmap);
3006
3007	ret = pm_runtime_resume_and_get(dev);
3008	if (ret < 0)
3009		return ret;
3010
3011	wcd939x->variant = snd_soc_component_read_field(component,
3012							WCD939X_DIGITAL_EFUSE_REG_0,
3013							WCD939X_EFUSE_REG_0_WCD939X_ID);
3014
3015	wcd939x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD939X);
3016	if (IS_ERR(wcd939x->clsh_info)) {
3017		pm_runtime_put(dev);
3018		return PTR_ERR(wcd939x->clsh_info);
3019	}
3020
3021	wcd939x_io_init(component);
3022
3023	/* Set all interrupts as edge triggered */
3024	for (i = 0; i < wcd939x_regmap_irq_chip.num_regs; i++)
3025		regmap_write(wcd939x->regmap,
3026			     (WCD939X_DIGITAL_INTR_LEVEL_0 + i), 0);
3027
3028	pm_runtime_put(dev);
3029
3030	/* Request for watchdog interrupt */
3031	wcd939x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3032						       WCD939X_IRQ_HPHR_PDM_WD_INT);
3033	wcd939x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3034						       WCD939X_IRQ_HPHL_PDM_WD_INT);
3035	wcd939x->ear_pdm_wd_int = regmap_irq_get_virq(wcd939x->irq_chip,
3036						      WCD939X_IRQ_EAR_PDM_WD_INT);
3037
3038	ret = request_threaded_irq(wcd939x->hphr_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3039				   IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3040				   "HPHR PDM WD INT", wcd939x);
3041	if (ret) {
3042		dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
3043		goto err_free_clsh_ctrl;
3044	}
3045
3046	ret = request_threaded_irq(wcd939x->hphl_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3047				   IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3048				   "HPHL PDM WD INT", wcd939x);
3049	if (ret) {
3050		dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
3051		goto err_free_hphr_pdm_wd_int;
3052	}
3053
3054	ret = request_threaded_irq(wcd939x->ear_pdm_wd_int, NULL, wcd939x_wd_handle_irq,
3055				   IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3056				   "AUX PDM WD INT", wcd939x);
3057	if (ret) {
3058		dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
3059		goto err_free_hphl_pdm_wd_int;
3060	}
3061
3062	/* Disable watchdog interrupt for HPH and AUX */
3063	disable_irq_nosync(wcd939x->hphr_pdm_wd_int);
3064	disable_irq_nosync(wcd939x->hphl_pdm_wd_int);
3065	disable_irq_nosync(wcd939x->ear_pdm_wd_int);
3066
3067	switch (wcd939x->variant) {
3068	case WCD9390:
3069		ret = snd_soc_add_component_controls(component, wcd9390_snd_controls,
3070						     ARRAY_SIZE(wcd9390_snd_controls));
3071		if (ret < 0) {
3072			dev_err(component->dev,
3073				"%s: Failed to add snd ctrls for variant: %d\n",
3074				__func__, wcd939x->variant);
3075			goto err_free_ear_pdm_wd_int;
3076		}
3077		break;
3078	case WCD9395:
3079		ret = snd_soc_add_component_controls(component, wcd9395_snd_controls,
3080						     ARRAY_SIZE(wcd9395_snd_controls));
3081		if (ret < 0) {
3082			dev_err(component->dev,
3083				"%s: Failed to add snd ctrls for variant: %d\n",
3084				__func__, wcd939x->variant);
3085			goto err_free_ear_pdm_wd_int;
3086		}
3087		break;
3088	default:
3089		break;
3090	}
3091
3092	ret = wcd939x_mbhc_init(component);
3093	if (ret) {
3094		dev_err(component->dev,  "mbhc initialization failed\n");
3095		goto err_free_ear_pdm_wd_int;
3096	}
3097
3098	return 0;
3099
3100err_free_ear_pdm_wd_int:
3101	free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3102err_free_hphl_pdm_wd_int:
3103	free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3104err_free_hphr_pdm_wd_int:
3105	free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3106err_free_clsh_ctrl:
3107	wcd_clsh_ctrl_free(wcd939x->clsh_info);
3108
3109	return ret;
3110}
3111
3112static void wcd939x_soc_codec_remove(struct snd_soc_component *component)
3113{
3114	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3115
3116	wcd939x_mbhc_deinit(component);
3117
3118	free_irq(wcd939x->ear_pdm_wd_int, wcd939x);
3119	free_irq(wcd939x->hphl_pdm_wd_int, wcd939x);
3120	free_irq(wcd939x->hphr_pdm_wd_int, wcd939x);
3121
3122	wcd_clsh_ctrl_free(wcd939x->clsh_info);
3123}
3124
3125static int wcd939x_codec_set_jack(struct snd_soc_component *comp,
3126				  struct snd_soc_jack *jack, void *data)
3127{
3128	struct wcd939x_priv *wcd = dev_get_drvdata(comp->dev);
3129
3130	if (jack)
3131		return wcd_mbhc_start(wcd->wcd_mbhc, &wcd->mbhc_cfg, jack);
3132
3133	wcd_mbhc_stop(wcd->wcd_mbhc);
3134
3135	return 0;
3136}
3137
3138static const struct snd_soc_component_driver soc_codec_dev_wcd939x = {
3139	.name = "wcd939x_codec",
3140	.probe = wcd939x_soc_codec_probe,
3141	.remove = wcd939x_soc_codec_remove,
3142	.controls = wcd939x_snd_controls,
3143	.num_controls = ARRAY_SIZE(wcd939x_snd_controls),
3144	.dapm_widgets = wcd939x_dapm_widgets,
3145	.num_dapm_widgets = ARRAY_SIZE(wcd939x_dapm_widgets),
3146	.dapm_routes = wcd939x_audio_map,
3147	.num_dapm_routes = ARRAY_SIZE(wcd939x_audio_map),
3148	.set_jack = wcd939x_codec_set_jack,
3149	.endianness = 1,
3150};
3151
3152#if IS_ENABLED(CONFIG_TYPEC)
3153/* Get USB-C plug orientation to provide swap event for MBHC */
3154static int wcd939x_typec_switch_set(struct typec_switch_dev *sw,
3155				    enum typec_orientation orientation)
3156{
3157	struct wcd939x_priv *wcd939x = typec_switch_get_drvdata(sw);
3158
3159	wcd939x->typec_orientation = orientation;
3160
3161	return 0;
3162}
3163
3164static int wcd939x_typec_mux_set(struct typec_mux_dev *mux,
3165				 struct typec_mux_state *state)
3166{
3167	struct wcd939x_priv *wcd939x = typec_mux_get_drvdata(mux);
3168	unsigned int previous_mode = wcd939x->typec_mode;
3169
3170	if (!wcd939x->wcd_mbhc)
3171		return -EINVAL;
3172
3173	if (wcd939x->typec_mode != state->mode) {
3174		wcd939x->typec_mode = state->mode;
3175
3176		if (wcd939x->typec_mode == TYPEC_MODE_AUDIO)
3177			return wcd_mbhc_typec_report_plug(wcd939x->wcd_mbhc);
3178		else if (previous_mode == TYPEC_MODE_AUDIO)
3179			return wcd_mbhc_typec_report_unplug(wcd939x->wcd_mbhc);
3180	}
3181
3182	return 0;
3183}
3184#endif /* CONFIG_TYPEC */
3185
3186static void wcd939x_dt_parse_micbias_info(struct device *dev, struct wcd939x_priv *wcd)
3187{
3188	struct device_node *np = dev->of_node;
3189	u32 prop_val = 0;
3190	int rc = 0;
3191
3192	rc = of_property_read_u32(np, "qcom,micbias1-microvolt",  &prop_val);
3193	if (!rc)
3194		wcd->micb1_mv = prop_val / 1000;
3195	else
3196		dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
3197
3198	rc = of_property_read_u32(np, "qcom,micbias2-microvolt",  &prop_val);
3199	if (!rc)
3200		wcd->micb2_mv = prop_val / 1000;
3201	else
3202		dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
3203
3204	rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
3205	if (!rc)
3206		wcd->micb3_mv = prop_val / 1000;
3207	else
3208		dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
3209
3210	rc = of_property_read_u32(np, "qcom,micbias4-microvolt",  &prop_val);
3211	if (!rc)
3212		wcd->micb4_mv = prop_val / 1000;
3213	else
3214		dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
3215}
3216
3217#if IS_ENABLED(CONFIG_TYPEC)
3218static bool wcd939x_swap_gnd_mic(struct snd_soc_component *component, bool active)
3219{
3220	struct wcd939x_priv *wcd939x = snd_soc_component_get_drvdata(component);
3221
3222	if (!wcd939x->typec_analog_mux || !wcd939x->typec_switch)
3223		return false;
3224
3225	/* Report inversion via Type Switch of USBSS */
3226	typec_switch_set(wcd939x->typec_switch,
3227			 wcd939x->typec_orientation == TYPEC_ORIENTATION_REVERSE ?
3228				TYPEC_ORIENTATION_NORMAL : TYPEC_ORIENTATION_REVERSE);
3229
3230	return true;
3231}
3232#endif /* CONFIG_TYPEC */
3233
3234static int wcd939x_populate_dt_data(struct wcd939x_priv *wcd939x, struct device *dev)
3235{
3236	struct wcd_mbhc_config *cfg = &wcd939x->mbhc_cfg;
3237#if IS_ENABLED(CONFIG_TYPEC)
3238	struct device_node *np;
3239#endif /* CONFIG_TYPEC */
3240	int ret;
3241
3242	wcd939x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
3243	if (wcd939x->reset_gpio < 0)
3244		return dev_err_probe(dev, wcd939x->reset_gpio,
3245				     "Failed to get reset gpio\n");
3246
3247	wcd939x->supplies[0].supply = "vdd-rxtx";
3248	wcd939x->supplies[1].supply = "vdd-io";
3249	wcd939x->supplies[2].supply = "vdd-buck";
3250	wcd939x->supplies[3].supply = "vdd-mic-bias";
3251
3252	ret = regulator_bulk_get(dev, WCD939X_MAX_SUPPLY, wcd939x->supplies);
3253	if (ret)
3254		return dev_err_probe(dev, ret, "Failed to get supplies\n");
3255
3256	ret = regulator_bulk_enable(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3257	if (ret) {
3258		regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3259		return dev_err_probe(dev, ret, "Failed to enable supplies\n");
3260	}
3261
3262	wcd939x_dt_parse_micbias_info(dev, wcd939x);
3263
3264	cfg->mbhc_micbias = MIC_BIAS_2;
3265	cfg->anc_micbias = MIC_BIAS_2;
3266	cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
3267	cfg->num_btn = WCD939X_MBHC_MAX_BUTTONS;
3268	cfg->micb_mv = wcd939x->micb2_mv;
3269	cfg->linein_th = 5000;
3270	cfg->hs_thr = 1700;
3271	cfg->hph_thr = 50;
3272
3273	wcd_dt_parse_mbhc_data(dev, cfg);
3274
3275#if IS_ENABLED(CONFIG_TYPEC)
3276	/*
3277	 * Is node has a port and a valid remote endpoint
3278	 * consider HP lines are connected to the USBSS part
3279	 */
3280	np = of_graph_get_remote_node(dev->of_node, 0, 0);
3281	if (np) {
3282		wcd939x->typec_analog_mux = true;
3283		cfg->typec_analog_mux = true;
3284		cfg->swap_gnd_mic = wcd939x_swap_gnd_mic;
3285	}
3286#endif /* CONFIG_TYPEC */
3287
3288	return 0;
3289}
3290
3291static int wcd939x_reset(struct wcd939x_priv *wcd939x)
3292{
3293	gpio_direction_output(wcd939x->reset_gpio, 0);
3294	/* 20us sleep required after pulling the reset gpio to LOW */
3295	usleep_range(20, 30);
3296	gpio_set_value(wcd939x->reset_gpio, 1);
3297	/* 20us sleep required after pulling the reset gpio to HIGH */
3298	usleep_range(20, 30);
3299
3300	return 0;
3301}
3302
3303static int wcd939x_codec_hw_params(struct snd_pcm_substream *substream,
3304				   struct snd_pcm_hw_params *params,
3305				struct snd_soc_dai *dai)
3306{
3307	struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3308	struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3309
3310	return wcd939x_sdw_hw_params(wcd, substream, params, dai);
3311}
3312
3313static int wcd939x_codec_free(struct snd_pcm_substream *substream,
3314			      struct snd_soc_dai *dai)
3315{
3316	struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3317	struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3318
3319	return wcd939x_sdw_free(wcd, substream, dai);
3320}
3321
3322static int wcd939x_codec_set_sdw_stream(struct snd_soc_dai *dai,
3323					void *stream, int direction)
3324{
3325	struct wcd939x_priv *wcd939x = dev_get_drvdata(dai->dev);
3326	struct wcd939x_sdw_priv *wcd = wcd939x->sdw_priv[dai->id];
3327
3328	return wcd939x_sdw_set_sdw_stream(wcd, dai, stream, direction);
3329}
3330
3331static const struct snd_soc_dai_ops wcd939x_sdw_dai_ops = {
3332	.hw_params = wcd939x_codec_hw_params,
3333	.hw_free = wcd939x_codec_free,
3334	.set_stream = wcd939x_codec_set_sdw_stream,
3335};
3336
3337static struct snd_soc_dai_driver wcd939x_dais[] = {
3338	[0] = {
3339		.name = "wcd939x-sdw-rx",
3340		.playback = {
3341			.stream_name = "WCD AIF1 Playback",
3342			.rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3343			.formats = WCD939X_FORMATS,
3344			.rate_max = 384000,
3345			.rate_min = 8000,
3346			.channels_min = 1,
3347			.channels_max = 2,
3348		},
3349		.ops = &wcd939x_sdw_dai_ops,
3350	},
3351	[1] = {
3352		.name = "wcd939x-sdw-tx",
3353		.capture = {
3354			.stream_name = "WCD AIF1 Capture",
3355			.rates = WCD939X_RATES_MASK | WCD939X_FRAC_RATES_MASK,
3356			.formats = WCD939X_FORMATS,
3357			.rate_min = 8000,
3358			.rate_max = 384000,
3359			.channels_min = 1,
3360			.channels_max = 4,
3361		},
3362		.ops = &wcd939x_sdw_dai_ops,
3363	},
3364};
3365
3366static int wcd939x_bind(struct device *dev)
3367{
3368	struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3369	unsigned int version, id1, status1;
3370	int ret;
3371
3372#if IS_ENABLED(CONFIG_TYPEC)
3373	/*
3374	 * Get USBSS type-c switch to send gnd/mic swap events
3375	 * typec_switch is fetched now to avoid a probe deadlock since
3376	 * the USBSS depends on the typec_mux register in wcd939x_probe()
3377	 */
3378	if (wcd939x->typec_analog_mux) {
3379		wcd939x->typec_switch = fwnode_typec_switch_get(dev->fwnode);
3380		if (IS_ERR(wcd939x->typec_switch))
3381			return dev_err_probe(dev, PTR_ERR(wcd939x->typec_switch),
3382					     "failed to acquire orientation-switch\n");
3383	}
3384#endif /* CONFIG_TYPEC */
3385
3386	ret = component_bind_all(dev, wcd939x);
3387	if (ret) {
3388		dev_err(dev, "%s: Slave bind failed, ret = %d\n",
3389			__func__, ret);
3390		goto err_put_typec_switch;
3391	}
3392
3393	wcd939x->rxdev = wcd939x_sdw_device_get(wcd939x->rxnode);
3394	if (!wcd939x->rxdev) {
3395		dev_err(dev, "could not find slave with matching of node\n");
3396		ret = -EINVAL;
3397		goto err_unbind;
3398	}
3399	wcd939x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd939x->rxdev);
3400	wcd939x->sdw_priv[AIF1_PB]->wcd939x = wcd939x;
3401
3402	wcd939x->txdev = wcd939x_sdw_device_get(wcd939x->txnode);
3403	if (!wcd939x->txdev) {
3404		dev_err(dev, "could not find txslave with matching of node\n");
3405		ret = -EINVAL;
3406		goto err_put_rxdev;
3407	}
3408	wcd939x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd939x->txdev);
3409	wcd939x->sdw_priv[AIF1_CAP]->wcd939x = wcd939x;
3410	wcd939x->tx_sdw_dev = dev_to_sdw_dev(wcd939x->txdev);
3411
3412	/*
3413	 * As TX is main CSR reg interface, which should not be suspended first.
3414	 * explicitly add the dependency link
3415	 */
3416	if (!device_link_add(wcd939x->rxdev, wcd939x->txdev, DL_FLAG_STATELESS |
3417			    DL_FLAG_PM_RUNTIME)) {
3418		dev_err(dev, "could not devlink tx and rx\n");
3419		ret = -EINVAL;
3420		goto err_put_txdev;
3421	}
3422
3423	if (!device_link_add(dev, wcd939x->txdev, DL_FLAG_STATELESS |
3424					DL_FLAG_PM_RUNTIME)) {
3425		dev_err(dev, "could not devlink wcd and tx\n");
3426		ret = -EINVAL;
3427		goto err_remove_rxtx_link;
3428	}
3429
3430	if (!device_link_add(dev, wcd939x->rxdev, DL_FLAG_STATELESS |
3431					DL_FLAG_PM_RUNTIME)) {
3432		dev_err(dev, "could not devlink wcd and rx\n");
3433		ret = -EINVAL;
3434		goto err_remove_tx_link;
3435	}
3436
3437	/* Get regmap from TX SoundWire device */
3438	wcd939x->regmap = wcd939x_swr_get_regmap(wcd939x->sdw_priv[AIF1_CAP]);
3439	if (IS_ERR(wcd939x->regmap)) {
3440		dev_err(dev, "could not get TX device regmap\n");
3441		ret = PTR_ERR(wcd939x->regmap);
3442		goto err_remove_rx_link;
3443	}
3444
3445	ret = wcd939x_irq_init(wcd939x, dev);
3446	if (ret) {
3447		dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
3448		goto err_remove_rx_link;
3449	}
3450
3451	wcd939x->sdw_priv[AIF1_PB]->slave_irq = wcd939x->virq;
3452	wcd939x->sdw_priv[AIF1_CAP]->slave_irq = wcd939x->virq;
3453
3454	ret = wcd939x_set_micbias_data(wcd939x);
3455	if (ret < 0) {
3456		dev_err(dev, "%s: bad micbias pdata\n", __func__);
3457		goto err_remove_rx_link;
3458	}
3459
3460	/* Check WCD9395 version */
3461	regmap_read(wcd939x->regmap, WCD939X_DIGITAL_CHIP_ID1, &id1);
3462	regmap_read(wcd939x->regmap, WCD939X_EAR_STATUS_REG_1, &status1);
3463
3464	if (id1 == 0)
3465		version = ((status1 & 0x3) ? WCD939X_VERSION_1_1 : WCD939X_VERSION_1_0);
3466	else
3467		version = WCD939X_VERSION_2_0;
3468
3469	dev_dbg(dev, "wcd939x version: %s\n", version_to_str(version));
3470
3471	ret = snd_soc_register_component(dev, &soc_codec_dev_wcd939x,
3472					 wcd939x_dais, ARRAY_SIZE(wcd939x_dais));
3473	if (ret) {
3474		dev_err(dev, "%s: Codec registration failed\n",
3475			__func__);
3476		goto err_remove_rx_link;
3477	}
3478
3479	return 0;
3480
3481err_remove_rx_link:
3482	device_link_remove(dev, wcd939x->rxdev);
3483err_remove_tx_link:
3484	device_link_remove(dev, wcd939x->txdev);
3485err_remove_rxtx_link:
3486	device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3487err_put_txdev:
3488	put_device(wcd939x->txdev);
3489err_put_rxdev:
3490	put_device(wcd939x->rxdev);
3491err_unbind:
3492	component_unbind_all(dev, wcd939x);
3493err_put_typec_switch:
3494#if IS_ENABLED(CONFIG_TYPEC)
3495	if (wcd939x->typec_analog_mux)
3496		typec_switch_put(wcd939x->typec_switch);
3497#endif /* CONFIG_TYPEC */
3498
3499	return ret;
3500}
3501
3502static void wcd939x_unbind(struct device *dev)
3503{
3504	struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3505
3506	snd_soc_unregister_component(dev);
3507	device_link_remove(dev, wcd939x->txdev);
3508	device_link_remove(dev, wcd939x->rxdev);
3509	device_link_remove(wcd939x->rxdev, wcd939x->txdev);
3510	put_device(wcd939x->txdev);
3511	put_device(wcd939x->rxdev);
3512	component_unbind_all(dev, wcd939x);
3513}
3514
3515static const struct component_master_ops wcd939x_comp_ops = {
3516	.bind   = wcd939x_bind,
3517	.unbind = wcd939x_unbind,
3518};
3519
3520static void __maybe_unused wcd939x_typec_mux_unregister(void *data)
3521{
3522	struct typec_mux_dev *typec_mux = data;
3523
3524	typec_mux_unregister(typec_mux);
3525}
3526
3527static void __maybe_unused wcd939x_typec_switch_unregister(void *data)
3528{
3529	struct typec_switch_dev *typec_sw = data;
3530
3531	typec_switch_unregister(typec_sw);
3532}
3533
3534static int wcd939x_add_typec(struct wcd939x_priv *wcd939x, struct device *dev)
3535{
3536#if IS_ENABLED(CONFIG_TYPEC)
3537	int ret;
3538	struct typec_mux_dev *typec_mux;
3539	struct typec_switch_dev *typec_sw;
3540	struct typec_mux_desc mux_desc = {
3541		.drvdata = wcd939x,
3542		.fwnode = dev_fwnode(dev),
3543		.set = wcd939x_typec_mux_set,
3544	};
3545	struct typec_switch_desc sw_desc = {
3546		.drvdata = wcd939x,
3547		.fwnode = dev_fwnode(dev),
3548		.set = wcd939x_typec_switch_set,
3549	};
3550
3551	/*
3552	 * Is USBSS is used to mux analog lines,
3553	 * register a typec mux/switch to get typec events
3554	 */
3555	if (!wcd939x->typec_analog_mux)
3556		return 0;
3557
3558	typec_mux = typec_mux_register(dev, &mux_desc);
3559	if (IS_ERR(typec_mux))
3560		return dev_err_probe(dev, PTR_ERR(typec_mux),
3561				     "failed to register typec mux\n");
3562
3563	ret = devm_add_action_or_reset(dev, wcd939x_typec_mux_unregister,
3564				       typec_mux);
3565	if (ret)
3566		return ret;
3567
3568	typec_sw = typec_switch_register(dev, &sw_desc);
3569	if (IS_ERR(typec_sw))
3570		return dev_err_probe(dev, PTR_ERR(typec_sw),
3571				     "failed to register typec switch\n");
3572
3573	ret = devm_add_action_or_reset(dev, wcd939x_typec_switch_unregister,
3574				       typec_sw);
3575	if (ret)
3576		return ret;
3577#endif
3578
3579	return 0;
3580}
3581
3582static int wcd939x_add_slave_components(struct wcd939x_priv *wcd939x,
3583					struct device *dev,
3584					struct component_match **matchptr)
3585{
3586	struct device_node *np = dev->of_node;
3587
3588	wcd939x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
3589	if (!wcd939x->rxnode) {
3590		dev_err(dev, "%s: Rx-device node not defined\n", __func__);
3591		return -ENODEV;
3592	}
3593
3594	of_node_get(wcd939x->rxnode);
3595	component_match_add_release(dev, matchptr, component_release_of,
3596				    component_compare_of, wcd939x->rxnode);
3597
3598	wcd939x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
3599	if (!wcd939x->txnode) {
3600		dev_err(dev, "%s: Tx-device node not defined\n", __func__);
3601		return -ENODEV;
3602	}
3603	of_node_get(wcd939x->txnode);
3604	component_match_add_release(dev, matchptr, component_release_of,
3605				    component_compare_of, wcd939x->txnode);
3606	return 0;
3607}
3608
3609static int wcd939x_probe(struct platform_device *pdev)
3610{
3611	struct component_match *match = NULL;
3612	struct wcd939x_priv *wcd939x = NULL;
3613	struct device *dev = &pdev->dev;
3614	int ret;
3615
3616	wcd939x = devm_kzalloc(dev, sizeof(struct wcd939x_priv),
3617			       GFP_KERNEL);
3618	if (!wcd939x)
3619		return -ENOMEM;
3620
3621	dev_set_drvdata(dev, wcd939x);
3622	mutex_init(&wcd939x->micb_lock);
3623
3624	ret = wcd939x_populate_dt_data(wcd939x, dev);
3625	if (ret) {
3626		dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
3627		return -EINVAL;
3628	}
3629
3630	ret = wcd939x_add_typec(wcd939x, dev);
3631	if (ret)
3632		goto err_disable_regulators;
3633
3634	ret = wcd939x_add_slave_components(wcd939x, dev, &match);
3635	if (ret)
3636		goto err_disable_regulators;
3637
3638	wcd939x_reset(wcd939x);
3639
3640	ret = component_master_add_with_match(dev, &wcd939x_comp_ops, match);
3641	if (ret)
3642		goto err_disable_regulators;
3643
3644	pm_runtime_set_autosuspend_delay(dev, 1000);
3645	pm_runtime_use_autosuspend(dev);
3646	pm_runtime_mark_last_busy(dev);
3647	pm_runtime_set_active(dev);
3648	pm_runtime_enable(dev);
3649	pm_runtime_idle(dev);
3650
3651	return 0;
3652
3653err_disable_regulators:
3654	regulator_bulk_disable(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3655	regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3656
3657	return ret;
3658}
3659
3660static void wcd939x_remove(struct platform_device *pdev)
3661{
3662	struct device *dev = &pdev->dev;
3663	struct wcd939x_priv *wcd939x = dev_get_drvdata(dev);
3664
3665	component_master_del(dev, &wcd939x_comp_ops);
3666
3667	pm_runtime_disable(dev);
3668	pm_runtime_set_suspended(dev);
3669	pm_runtime_dont_use_autosuspend(dev);
3670
3671	regulator_bulk_disable(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3672	regulator_bulk_free(WCD939X_MAX_SUPPLY, wcd939x->supplies);
3673}
3674
3675#if defined(CONFIG_OF)
3676static const struct of_device_id wcd939x_dt_match[] = {
3677	{ .compatible = "qcom,wcd9390-codec" },
3678	{ .compatible = "qcom,wcd9395-codec" },
3679	{}
3680};
3681MODULE_DEVICE_TABLE(of, wcd939x_dt_match);
3682#endif
3683
3684static struct platform_driver wcd939x_codec_driver = {
3685	.probe = wcd939x_probe,
3686	.remove = wcd939x_remove,
3687	.driver = {
3688		.name = "wcd939x_codec",
3689		.of_match_table = of_match_ptr(wcd939x_dt_match),
3690		.suppress_bind_attrs = true,
3691	},
3692};
3693
3694module_platform_driver(wcd939x_codec_driver);
3695MODULE_DESCRIPTION("WCD939X Codec driver");
3696MODULE_LICENSE("GPL");