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1// SPDX-License-Identifier: GPL-2.0
2// Copyright (c) 2019, Linaro Limited
3
4#include <linux/cleanup.h>
5#include <linux/clk.h>
6#include <linux/clk-provider.h>
7#include <linux/interrupt.h>
8#include <linux/kernel.h>
9#include <linux/mfd/wcd934x/registers.h>
10#include <linux/mfd/wcd934x/wcd934x.h>
11#include <linux/module.h>
12#include <linux/mutex.h>
13#include <linux/of_clk.h>
14#include <linux/of.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/slimbus.h>
19#include <sound/pcm_params.h>
20#include <sound/soc.h>
21#include <sound/soc-dapm.h>
22#include <sound/tlv.h>
23#include "wcd-clsh-v2.h"
24#include "wcd-mbhc-v2.h"
25
26#define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
27 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
28 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
29/* Fractional Rates */
30#define WCD934X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
31 SNDRV_PCM_RATE_176400)
32#define WCD934X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
33 SNDRV_PCM_FMTBIT_S24_LE)
34
35/* slave port water mark level
36 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
37 */
38#define SLAVE_PORT_WATER_MARK_6BYTES 0
39#define SLAVE_PORT_WATER_MARK_9BYTES 1
40#define SLAVE_PORT_WATER_MARK_12BYTES 2
41#define SLAVE_PORT_WATER_MARK_15BYTES 3
42#define SLAVE_PORT_WATER_MARK_SHIFT 1
43#define SLAVE_PORT_ENABLE 1
44#define SLAVE_PORT_DISABLE 0
45#define WCD934X_SLIM_WATER_MARK_VAL \
46 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
47 (SLAVE_PORT_ENABLE))
48
49#define WCD934X_SLIM_NUM_PORT_REG 3
50#define WCD934X_SLIM_PGD_PORT_INT_TX_EN0 (WCD934X_SLIM_PGD_PORT_INT_EN0 + 2)
51#define WCD934X_SLIM_IRQ_OVERFLOW BIT(0)
52#define WCD934X_SLIM_IRQ_UNDERFLOW BIT(1)
53#define WCD934X_SLIM_IRQ_PORT_CLOSED BIT(2)
54
55#define WCD934X_MCLK_CLK_12P288MHZ 12288000
56#define WCD934X_MCLK_CLK_9P6MHZ 9600000
57
58/* Only valid for 9.6 MHz mclk */
59#define WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ 2400000
60#define WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ 4800000
61
62/* Only valid for 12.288 MHz mclk */
63#define WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ 4096000
64
65#define WCD934X_DMIC_CLK_DIV_2 0x0
66#define WCD934X_DMIC_CLK_DIV_3 0x1
67#define WCD934X_DMIC_CLK_DIV_4 0x2
68#define WCD934X_DMIC_CLK_DIV_6 0x3
69#define WCD934X_DMIC_CLK_DIV_8 0x4
70#define WCD934X_DMIC_CLK_DIV_16 0x5
71#define WCD934X_DMIC_CLK_DRIVE_DEFAULT 0x02
72
73#define TX_HPF_CUT_OFF_FREQ_MASK 0x60
74#define CF_MIN_3DB_4HZ 0x0
75#define CF_MIN_3DB_75HZ 0x1
76#define CF_MIN_3DB_150HZ 0x2
77
78#define WCD934X_RX_START 16
79#define WCD934X_NUM_INTERPOLATORS 9
80#define WCD934X_RX_PATH_CTL_OFFSET 20
81#define WCD934X_MAX_VALID_ADC_MUX 13
82#define WCD934X_INVALID_ADC_MUX 9
83
84#define WCD934X_SLIM_RX_CH(p) \
85 {.port = p + WCD934X_RX_START, .shift = p,}
86
87#define WCD934X_SLIM_TX_CH(p) \
88 {.port = p, .shift = p,}
89
90/* Feature masks to distinguish codec version */
91#define DSD_DISABLED_MASK 0
92#define SLNQ_DISABLED_MASK 1
93
94#define DSD_DISABLED BIT(DSD_DISABLED_MASK)
95#define SLNQ_DISABLED BIT(SLNQ_DISABLED_MASK)
96
97/* As fine version info cannot be retrieved before wcd probe.
98 * Define three coarse versions for possible future use before wcd probe.
99 */
100#define WCD_VERSION_WCD9340_1_0 0x400
101#define WCD_VERSION_WCD9341_1_0 0x410
102#define WCD_VERSION_WCD9340_1_1 0x401
103#define WCD_VERSION_WCD9341_1_1 0x411
104#define WCD934X_AMIC_PWR_LEVEL_LP 0
105#define WCD934X_AMIC_PWR_LEVEL_DEFAULT 1
106#define WCD934X_AMIC_PWR_LEVEL_HP 2
107#define WCD934X_AMIC_PWR_LEVEL_HYBRID 3
108#define WCD934X_AMIC_PWR_LVL_MASK 0x60
109#define WCD934X_AMIC_PWR_LVL_SHIFT 0x5
110
111#define WCD934X_DEC_PWR_LVL_MASK 0x06
112#define WCD934X_DEC_PWR_LVL_LP 0x02
113#define WCD934X_DEC_PWR_LVL_HP 0x04
114#define WCD934X_DEC_PWR_LVL_DF 0x00
115#define WCD934X_DEC_PWR_LVL_HYBRID WCD934X_DEC_PWR_LVL_DF
116
117#define WCD934X_DEF_MICBIAS_MV 1800
118#define WCD934X_MAX_MICBIAS_MV 2850
119
120#define WCD_IIR_FILTER_SIZE (sizeof(u32) * BAND_MAX)
121
122#define WCD_IIR_FILTER_CTL(xname, iidx, bidx) \
123{ \
124 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
125 .info = wcd934x_iir_filter_info, \
126 .get = wcd934x_get_iir_band_audio_mixer, \
127 .put = wcd934x_put_iir_band_audio_mixer, \
128 .private_value = (unsigned long)&(struct wcd_iir_filter_ctl) { \
129 .iir_idx = iidx, \
130 .band_idx = bidx, \
131 .bytes_ext = {.max = WCD_IIR_FILTER_SIZE, }, \
132 } \
133}
134
135/* Z value defined in milliohm */
136#define WCD934X_ZDET_VAL_32 32000
137#define WCD934X_ZDET_VAL_400 400000
138#define WCD934X_ZDET_VAL_1200 1200000
139#define WCD934X_ZDET_VAL_100K 100000000
140/* Z floating defined in ohms */
141#define WCD934X_ZDET_FLOATING_IMPEDANCE 0x0FFFFFFE
142
143#define WCD934X_ZDET_NUM_MEASUREMENTS 900
144#define WCD934X_MBHC_GET_C1(c) ((c & 0xC000) >> 14)
145#define WCD934X_MBHC_GET_X1(x) (x & 0x3FFF)
146/* Z value compared in milliOhm */
147#define WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
148#define WCD934X_MBHC_ZDET_CONST (86 * 16384)
149#define WCD934X_MBHC_MOISTURE_RREF R_24_KOHM
150#define WCD934X_MBHC_MAX_BUTTONS (8)
151#define WCD_MBHC_HS_V_MAX 1600
152
153#define WCD934X_INTERPOLATOR_PATH(id) \
154 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
155 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
156 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
157 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
158 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
159 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
160 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
161 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
162 {"RX INT" #id "_1 MIX1 INP0", "IIR0", "IIR0"}, \
163 {"RX INT" #id "_1 MIX1 INP0", "IIR1", "IIR1"}, \
164 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
165 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
166 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
167 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
168 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
169 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
170 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
171 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
172 {"RX INT" #id "_1 MIX1 INP1", "IIR0", "IIR0"}, \
173 {"RX INT" #id "_1 MIX1 INP1", "IIR1", "IIR1"}, \
174 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
175 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
176 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
177 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
178 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
179 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
180 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
181 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
182 {"RX INT" #id "_1 MIX1 INP2", "IIR0", "IIR0"}, \
183 {"RX INT" #id "_1 MIX1 INP2", "IIR1", "IIR1"}, \
184 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
185 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
186 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
187 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
188 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
189 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
190 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
191 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
192 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
193 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
194 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
195 {"RX INT" #id "_2 MUX", NULL, "INT" #id "_CLK"}, \
196 {"RX INT" #id "_2 MUX", NULL, "DSMDEM" #id "_CLK"}, \
197 {"RX INT" #id "_2 INTERP", NULL, "RX INT" #id "_2 MUX"}, \
198 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 INTERP"}, \
199 {"RX INT" #id "_1 INTERP", NULL, "RX INT" #id "_1 MIX1"}, \
200 {"RX INT" #id "_1 INTERP", NULL, "INT" #id "_CLK"}, \
201 {"RX INT" #id "_1 INTERP", NULL, "DSMDEM" #id "_CLK"}, \
202 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 INTERP"}
203
204#define WCD934X_INTERPOLATOR_MIX2(id) \
205 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
206 {"RX INT" #id " MIX2", NULL, "RX INT" #id " MIX2 INP"}
207
208#define WCD934X_SLIM_RX_AIF_PATH(id) \
209 {"SLIM RX"#id" MUX", "AIF1_PB", "AIF1 PB"}, \
210 {"SLIM RX"#id" MUX", "AIF2_PB", "AIF2 PB"}, \
211 {"SLIM RX"#id" MUX", "AIF3_PB", "AIF3 PB"}, \
212 {"SLIM RX"#id" MUX", "AIF4_PB", "AIF4 PB"}, \
213 {"SLIM RX"#id, NULL, "SLIM RX"#id" MUX"}
214
215#define WCD934X_ADC_MUX(id) \
216 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id }, \
217 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id }, \
218 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
219 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
220 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
221 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
222 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
223 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
224 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
225 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
226 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
227 {"AMIC MUX" #id, "ADC4", "ADC4"}
228
229#define WCD934X_IIR_INP_MUX(id) \
230 {"IIR" #id, NULL, "IIR" #id " INP0 MUX"}, \
231 {"IIR" #id " INP0 MUX", "DEC0", "ADC MUX0"}, \
232 {"IIR" #id " INP0 MUX", "DEC1", "ADC MUX1"}, \
233 {"IIR" #id " INP0 MUX", "DEC2", "ADC MUX2"}, \
234 {"IIR" #id " INP0 MUX", "DEC3", "ADC MUX3"}, \
235 {"IIR" #id " INP0 MUX", "DEC4", "ADC MUX4"}, \
236 {"IIR" #id " INP0 MUX", "DEC5", "ADC MUX5"}, \
237 {"IIR" #id " INP0 MUX", "DEC6", "ADC MUX6"}, \
238 {"IIR" #id " INP0 MUX", "DEC7", "ADC MUX7"}, \
239 {"IIR" #id " INP0 MUX", "DEC8", "ADC MUX8"}, \
240 {"IIR" #id " INP0 MUX", "RX0", "SLIM RX0"}, \
241 {"IIR" #id " INP0 MUX", "RX1", "SLIM RX1"}, \
242 {"IIR" #id " INP0 MUX", "RX2", "SLIM RX2"}, \
243 {"IIR" #id " INP0 MUX", "RX3", "SLIM RX3"}, \
244 {"IIR" #id " INP0 MUX", "RX4", "SLIM RX4"}, \
245 {"IIR" #id " INP0 MUX", "RX5", "SLIM RX5"}, \
246 {"IIR" #id " INP0 MUX", "RX6", "SLIM RX6"}, \
247 {"IIR" #id " INP0 MUX", "RX7", "SLIM RX7"}, \
248 {"IIR" #id, NULL, "IIR" #id " INP1 MUX"}, \
249 {"IIR" #id " INP1 MUX", "DEC0", "ADC MUX0"}, \
250 {"IIR" #id " INP1 MUX", "DEC1", "ADC MUX1"}, \
251 {"IIR" #id " INP1 MUX", "DEC2", "ADC MUX2"}, \
252 {"IIR" #id " INP1 MUX", "DEC3", "ADC MUX3"}, \
253 {"IIR" #id " INP1 MUX", "DEC4", "ADC MUX4"}, \
254 {"IIR" #id " INP1 MUX", "DEC5", "ADC MUX5"}, \
255 {"IIR" #id " INP1 MUX", "DEC6", "ADC MUX6"}, \
256 {"IIR" #id " INP1 MUX", "DEC7", "ADC MUX7"}, \
257 {"IIR" #id " INP1 MUX", "DEC8", "ADC MUX8"}, \
258 {"IIR" #id " INP1 MUX", "RX0", "SLIM RX0"}, \
259 {"IIR" #id " INP1 MUX", "RX1", "SLIM RX1"}, \
260 {"IIR" #id " INP1 MUX", "RX2", "SLIM RX2"}, \
261 {"IIR" #id " INP1 MUX", "RX3", "SLIM RX3"}, \
262 {"IIR" #id " INP1 MUX", "RX4", "SLIM RX4"}, \
263 {"IIR" #id " INP1 MUX", "RX5", "SLIM RX5"}, \
264 {"IIR" #id " INP1 MUX", "RX6", "SLIM RX6"}, \
265 {"IIR" #id " INP1 MUX", "RX7", "SLIM RX7"}, \
266 {"IIR" #id, NULL, "IIR" #id " INP2 MUX"}, \
267 {"IIR" #id " INP2 MUX", "DEC0", "ADC MUX0"}, \
268 {"IIR" #id " INP2 MUX", "DEC1", "ADC MUX1"}, \
269 {"IIR" #id " INP2 MUX", "DEC2", "ADC MUX2"}, \
270 {"IIR" #id " INP2 MUX", "DEC3", "ADC MUX3"}, \
271 {"IIR" #id " INP2 MUX", "DEC4", "ADC MUX4"}, \
272 {"IIR" #id " INP2 MUX", "DEC5", "ADC MUX5"}, \
273 {"IIR" #id " INP2 MUX", "DEC6", "ADC MUX6"}, \
274 {"IIR" #id " INP2 MUX", "DEC7", "ADC MUX7"}, \
275 {"IIR" #id " INP2 MUX", "DEC8", "ADC MUX8"}, \
276 {"IIR" #id " INP2 MUX", "RX0", "SLIM RX0"}, \
277 {"IIR" #id " INP2 MUX", "RX1", "SLIM RX1"}, \
278 {"IIR" #id " INP2 MUX", "RX2", "SLIM RX2"}, \
279 {"IIR" #id " INP2 MUX", "RX3", "SLIM RX3"}, \
280 {"IIR" #id " INP2 MUX", "RX4", "SLIM RX4"}, \
281 {"IIR" #id " INP2 MUX", "RX5", "SLIM RX5"}, \
282 {"IIR" #id " INP2 MUX", "RX6", "SLIM RX6"}, \
283 {"IIR" #id " INP2 MUX", "RX7", "SLIM RX7"}, \
284 {"IIR" #id, NULL, "IIR" #id " INP3 MUX"}, \
285 {"IIR" #id " INP3 MUX", "DEC0", "ADC MUX0"}, \
286 {"IIR" #id " INP3 MUX", "DEC1", "ADC MUX1"}, \
287 {"IIR" #id " INP3 MUX", "DEC2", "ADC MUX2"}, \
288 {"IIR" #id " INP3 MUX", "DEC3", "ADC MUX3"}, \
289 {"IIR" #id " INP3 MUX", "DEC4", "ADC MUX4"}, \
290 {"IIR" #id " INP3 MUX", "DEC5", "ADC MUX5"}, \
291 {"IIR" #id " INP3 MUX", "DEC6", "ADC MUX6"}, \
292 {"IIR" #id " INP3 MUX", "DEC7", "ADC MUX7"}, \
293 {"IIR" #id " INP3 MUX", "DEC8", "ADC MUX8"}, \
294 {"IIR" #id " INP3 MUX", "RX0", "SLIM RX0"}, \
295 {"IIR" #id " INP3 MUX", "RX1", "SLIM RX1"}, \
296 {"IIR" #id " INP3 MUX", "RX2", "SLIM RX2"}, \
297 {"IIR" #id " INP3 MUX", "RX3", "SLIM RX3"}, \
298 {"IIR" #id " INP3 MUX", "RX4", "SLIM RX4"}, \
299 {"IIR" #id " INP3 MUX", "RX5", "SLIM RX5"}, \
300 {"IIR" #id " INP3 MUX", "RX6", "SLIM RX6"}, \
301 {"IIR" #id " INP3 MUX", "RX7", "SLIM RX7"}
302
303#define WCD934X_SLIM_TX_AIF_PATH(id) \
304 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
305 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
306 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id }, \
307 {"SLIM TX" #id, NULL, "CDC_IF TX" #id " MUX"}
308
309#define WCD934X_MAX_MICBIAS MIC_BIAS_4
310
311enum {
312 SIDO_SOURCE_INTERNAL,
313 SIDO_SOURCE_RCO_BG,
314};
315
316enum {
317 INTERP_EAR = 0,
318 INTERP_HPHL,
319 INTERP_HPHR,
320 INTERP_LO1,
321 INTERP_LO2,
322 INTERP_LO3_NA, /* LO3 not avalible in Tavil */
323 INTERP_LO4_NA,
324 INTERP_SPKR1, /*INT7 WSA Speakers via soundwire */
325 INTERP_SPKR2, /*INT8 WSA Speakers via soundwire */
326 INTERP_MAX,
327};
328
329enum {
330 WCD934X_RX0 = 0,
331 WCD934X_RX1,
332 WCD934X_RX2,
333 WCD934X_RX3,
334 WCD934X_RX4,
335 WCD934X_RX5,
336 WCD934X_RX6,
337 WCD934X_RX7,
338 WCD934X_RX8,
339 WCD934X_RX9,
340 WCD934X_RX10,
341 WCD934X_RX11,
342 WCD934X_RX12,
343 WCD934X_RX_MAX,
344};
345
346enum {
347 WCD934X_TX0 = 0,
348 WCD934X_TX1,
349 WCD934X_TX2,
350 WCD934X_TX3,
351 WCD934X_TX4,
352 WCD934X_TX5,
353 WCD934X_TX6,
354 WCD934X_TX7,
355 WCD934X_TX8,
356 WCD934X_TX9,
357 WCD934X_TX10,
358 WCD934X_TX11,
359 WCD934X_TX12,
360 WCD934X_TX13,
361 WCD934X_TX14,
362 WCD934X_TX15,
363 WCD934X_TX_MAX,
364};
365
366struct wcd934x_slim_ch {
367 u32 ch_num;
368 u16 port;
369 u16 shift;
370 struct list_head list;
371};
372
373static const struct wcd934x_slim_ch wcd934x_tx_chs[WCD934X_TX_MAX] = {
374 WCD934X_SLIM_TX_CH(0),
375 WCD934X_SLIM_TX_CH(1),
376 WCD934X_SLIM_TX_CH(2),
377 WCD934X_SLIM_TX_CH(3),
378 WCD934X_SLIM_TX_CH(4),
379 WCD934X_SLIM_TX_CH(5),
380 WCD934X_SLIM_TX_CH(6),
381 WCD934X_SLIM_TX_CH(7),
382 WCD934X_SLIM_TX_CH(8),
383 WCD934X_SLIM_TX_CH(9),
384 WCD934X_SLIM_TX_CH(10),
385 WCD934X_SLIM_TX_CH(11),
386 WCD934X_SLIM_TX_CH(12),
387 WCD934X_SLIM_TX_CH(13),
388 WCD934X_SLIM_TX_CH(14),
389 WCD934X_SLIM_TX_CH(15),
390};
391
392static const struct wcd934x_slim_ch wcd934x_rx_chs[WCD934X_RX_MAX] = {
393 WCD934X_SLIM_RX_CH(0), /* 16 */
394 WCD934X_SLIM_RX_CH(1), /* 17 */
395 WCD934X_SLIM_RX_CH(2),
396 WCD934X_SLIM_RX_CH(3),
397 WCD934X_SLIM_RX_CH(4),
398 WCD934X_SLIM_RX_CH(5),
399 WCD934X_SLIM_RX_CH(6),
400 WCD934X_SLIM_RX_CH(7),
401 WCD934X_SLIM_RX_CH(8),
402 WCD934X_SLIM_RX_CH(9),
403 WCD934X_SLIM_RX_CH(10),
404 WCD934X_SLIM_RX_CH(11),
405 WCD934X_SLIM_RX_CH(12),
406};
407
408/* Codec supports 2 IIR filters */
409enum {
410 IIR0 = 0,
411 IIR1,
412 IIR_MAX,
413};
414
415/* Each IIR has 5 Filter Stages */
416enum {
417 BAND1 = 0,
418 BAND2,
419 BAND3,
420 BAND4,
421 BAND5,
422 BAND_MAX,
423};
424
425enum {
426 COMPANDER_1, /* HPH_L */
427 COMPANDER_2, /* HPH_R */
428 COMPANDER_3, /* LO1_DIFF */
429 COMPANDER_4, /* LO2_DIFF */
430 COMPANDER_5, /* LO3_SE - not used in Tavil */
431 COMPANDER_6, /* LO4_SE - not used in Tavil */
432 COMPANDER_7, /* SWR SPK CH1 */
433 COMPANDER_8, /* SWR SPK CH2 */
434 COMPANDER_MAX,
435};
436
437enum {
438 AIF1_PB = 0,
439 AIF1_CAP,
440 AIF2_PB,
441 AIF2_CAP,
442 AIF3_PB,
443 AIF3_CAP,
444 AIF4_PB,
445 AIF4_VIFEED,
446 AIF4_MAD_TX,
447 NUM_CODEC_DAIS,
448};
449
450enum {
451 INTn_1_INP_SEL_ZERO = 0,
452 INTn_1_INP_SEL_DEC0,
453 INTn_1_INP_SEL_DEC1,
454 INTn_1_INP_SEL_IIR0,
455 INTn_1_INP_SEL_IIR1,
456 INTn_1_INP_SEL_RX0,
457 INTn_1_INP_SEL_RX1,
458 INTn_1_INP_SEL_RX2,
459 INTn_1_INP_SEL_RX3,
460 INTn_1_INP_SEL_RX4,
461 INTn_1_INP_SEL_RX5,
462 INTn_1_INP_SEL_RX6,
463 INTn_1_INP_SEL_RX7,
464};
465
466enum {
467 INTn_2_INP_SEL_ZERO = 0,
468 INTn_2_INP_SEL_RX0,
469 INTn_2_INP_SEL_RX1,
470 INTn_2_INP_SEL_RX2,
471 INTn_2_INP_SEL_RX3,
472 INTn_2_INP_SEL_RX4,
473 INTn_2_INP_SEL_RX5,
474 INTn_2_INP_SEL_RX6,
475 INTn_2_INP_SEL_RX7,
476 INTn_2_INP_SEL_PROXIMITY,
477};
478
479struct interp_sample_rate {
480 int sample_rate;
481 int rate_val;
482};
483
484static const struct interp_sample_rate sr_val_tbl[] = {
485 {8000, 0x0},
486 {16000, 0x1},
487 {32000, 0x3},
488 {48000, 0x4},
489 {96000, 0x5},
490 {192000, 0x6},
491 {384000, 0x7},
492 {44100, 0x9},
493 {88200, 0xA},
494 {176400, 0xB},
495 {352800, 0xC},
496};
497
498struct wcd934x_mbhc_zdet_param {
499 u16 ldo_ctl;
500 u16 noff;
501 u16 nshift;
502 u16 btn5;
503 u16 btn6;
504 u16 btn7;
505};
506
507struct wcd_slim_codec_dai_data {
508 struct list_head slim_ch_list;
509 struct slim_stream_config sconfig;
510 struct slim_stream_runtime *sruntime;
511};
512
513static const struct regmap_range_cfg wcd934x_ifc_ranges[] = {
514 {
515 .name = "WCD9335-IFC-DEV",
516 .range_min = 0x0,
517 .range_max = 0xffff,
518 .selector_reg = 0x800,
519 .selector_mask = 0xfff,
520 .selector_shift = 0,
521 .window_start = 0x800,
522 .window_len = 0x400,
523 },
524};
525
526static const struct regmap_config wcd934x_ifc_regmap_config = {
527 .reg_bits = 16,
528 .val_bits = 8,
529 .max_register = 0xffff,
530 .ranges = wcd934x_ifc_ranges,
531 .num_ranges = ARRAY_SIZE(wcd934x_ifc_ranges),
532};
533
534struct wcd934x_codec {
535 struct device *dev;
536 struct clk_hw hw;
537 struct clk *extclk;
538 struct regmap *regmap;
539 struct regmap *if_regmap;
540 struct slim_device *sdev;
541 struct slim_device *sidev;
542 struct wcd_clsh_ctrl *clsh_ctrl;
543 struct snd_soc_component *component;
544 struct wcd934x_slim_ch rx_chs[WCD934X_RX_MAX];
545 struct wcd934x_slim_ch tx_chs[WCD934X_TX_MAX];
546 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
547 int rate;
548 u32 version;
549 u32 hph_mode;
550 int num_rx_port;
551 int num_tx_port;
552 u32 tx_port_value[WCD934X_TX_MAX];
553 u32 rx_port_value[WCD934X_RX_MAX];
554 int sido_input_src;
555 int dmic_0_1_clk_cnt;
556 int dmic_2_3_clk_cnt;
557 int dmic_4_5_clk_cnt;
558 int dmic_sample_rate;
559 int comp_enabled[COMPANDER_MAX];
560 int sysclk_users;
561 struct mutex sysclk_mutex;
562 /* mbhc module */
563 struct wcd_mbhc *mbhc;
564 struct wcd_mbhc_config mbhc_cfg;
565 struct wcd_mbhc_intr intr_ids;
566 bool mbhc_started;
567 struct mutex micb_lock;
568 u32 micb_ref[WCD934X_MAX_MICBIAS];
569 u32 pullup_ref[WCD934X_MAX_MICBIAS];
570 u32 micb2_mv;
571};
572
573#define to_wcd934x_codec(_hw) container_of(_hw, struct wcd934x_codec, hw)
574
575struct wcd_iir_filter_ctl {
576 unsigned int iir_idx;
577 unsigned int band_idx;
578 struct soc_bytes_ext bytes_ext;
579};
580
581static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
582static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
583static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
584static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
585
586/* Cutoff frequency for high pass filter */
587static const char * const cf_text[] = {
588 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
589};
590
591static const char * const rx_cf_text[] = {
592 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
593 "CF_NEG_3DB_0P48HZ"
594};
595
596static const char * const rx_hph_mode_mux_text[] = {
597 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
598 "Class-H Hi-Fi Low Power"
599};
600
601static const char *const slim_rx_mux_text[] = {
602 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
603};
604
605static const char * const rx_int0_7_mix_mux_text[] = {
606 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
607 "RX6", "RX7", "PROXIMITY"
608};
609
610static const char * const rx_int_mix_mux_text[] = {
611 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
612 "RX6", "RX7"
613};
614
615static const char * const rx_prim_mix_text[] = {
616 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
617 "RX3", "RX4", "RX5", "RX6", "RX7"
618};
619
620static const char * const rx_sidetone_mix_text[] = {
621 "ZERO", "SRC0", "SRC1", "SRC_SUM"
622};
623
624static const char * const iir_inp_mux_text[] = {
625 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4", "DEC5", "DEC6",
626 "DEC7", "DEC8", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5", "RX6", "RX7"
627};
628
629static const char * const rx_int_dem_inp_mux_text[] = {
630 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
631};
632
633static const char * const rx_int0_1_interp_mux_text[] = {
634 "ZERO", "RX INT0_1 MIX1",
635};
636
637static const char * const rx_int1_1_interp_mux_text[] = {
638 "ZERO", "RX INT1_1 MIX1",
639};
640
641static const char * const rx_int2_1_interp_mux_text[] = {
642 "ZERO", "RX INT2_1 MIX1",
643};
644
645static const char * const rx_int3_1_interp_mux_text[] = {
646 "ZERO", "RX INT3_1 MIX1",
647};
648
649static const char * const rx_int4_1_interp_mux_text[] = {
650 "ZERO", "RX INT4_1 MIX1",
651};
652
653static const char * const rx_int7_1_interp_mux_text[] = {
654 "ZERO", "RX INT7_1 MIX1",
655};
656
657static const char * const rx_int8_1_interp_mux_text[] = {
658 "ZERO", "RX INT8_1 MIX1",
659};
660
661static const char * const rx_int0_2_interp_mux_text[] = {
662 "ZERO", "RX INT0_2 MUX",
663};
664
665static const char * const rx_int1_2_interp_mux_text[] = {
666 "ZERO", "RX INT1_2 MUX",
667};
668
669static const char * const rx_int2_2_interp_mux_text[] = {
670 "ZERO", "RX INT2_2 MUX",
671};
672
673static const char * const rx_int3_2_interp_mux_text[] = {
674 "ZERO", "RX INT3_2 MUX",
675};
676
677static const char * const rx_int4_2_interp_mux_text[] = {
678 "ZERO", "RX INT4_2 MUX",
679};
680
681static const char * const rx_int7_2_interp_mux_text[] = {
682 "ZERO", "RX INT7_2 MUX",
683};
684
685static const char * const rx_int8_2_interp_mux_text[] = {
686 "ZERO", "RX INT8_2 MUX",
687};
688
689static const char * const dmic_mux_text[] = {
690 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5"
691};
692
693static const char * const amic_mux_text[] = {
694 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4"
695};
696
697static const char * const amic4_5_sel_text[] = {
698 "AMIC4", "AMIC5"
699};
700
701static const char * const adc_mux_text[] = {
702 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
703};
704
705static const char * const cdc_if_tx0_mux_text[] = {
706 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
707};
708
709static const char * const cdc_if_tx1_mux_text[] = {
710 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
711};
712
713static const char * const cdc_if_tx2_mux_text[] = {
714 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
715};
716
717static const char * const cdc_if_tx3_mux_text[] = {
718 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
719};
720
721static const char * const cdc_if_tx4_mux_text[] = {
722 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
723};
724
725static const char * const cdc_if_tx5_mux_text[] = {
726 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
727};
728
729static const char * const cdc_if_tx6_mux_text[] = {
730 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
731};
732
733static const char * const cdc_if_tx7_mux_text[] = {
734 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
735};
736
737static const char * const cdc_if_tx8_mux_text[] = {
738 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
739};
740
741static const char * const cdc_if_tx9_mux_text[] = {
742 "ZERO", "DEC7", "DEC7_192"
743};
744
745static const char * const cdc_if_tx10_mux_text[] = {
746 "ZERO", "DEC6", "DEC6_192"
747};
748
749static const char * const cdc_if_tx11_mux_text[] = {
750 "DEC_0_5", "DEC_9_12", "MAD_AUDIO", "MAD_BRDCST"
751};
752
753static const char * const cdc_if_tx11_inp1_mux_text[] = {
754 "ZERO", "DEC0", "DEC1", "DEC2", "DEC3", "DEC4",
755 "DEC5", "RX_MIX_TX5", "DEC9_10", "DEC11_12"
756};
757
758static const char * const cdc_if_tx13_mux_text[] = {
759 "CDC_DEC_5", "MAD_BRDCST"
760};
761
762static const char * const cdc_if_tx13_inp1_mux_text[] = {
763 "ZERO", "DEC5", "DEC5_192"
764};
765
766static const struct soc_enum cf_dec0_enum =
767 SOC_ENUM_SINGLE(WCD934X_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
768
769static const struct soc_enum cf_dec1_enum =
770 SOC_ENUM_SINGLE(WCD934X_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
771
772static const struct soc_enum cf_dec2_enum =
773 SOC_ENUM_SINGLE(WCD934X_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
774
775static const struct soc_enum cf_dec3_enum =
776 SOC_ENUM_SINGLE(WCD934X_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
777
778static const struct soc_enum cf_dec4_enum =
779 SOC_ENUM_SINGLE(WCD934X_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
780
781static const struct soc_enum cf_dec5_enum =
782 SOC_ENUM_SINGLE(WCD934X_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
783
784static const struct soc_enum cf_dec6_enum =
785 SOC_ENUM_SINGLE(WCD934X_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
786
787static const struct soc_enum cf_dec7_enum =
788 SOC_ENUM_SINGLE(WCD934X_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
789
790static const struct soc_enum cf_dec8_enum =
791 SOC_ENUM_SINGLE(WCD934X_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
792
793static const struct soc_enum cf_int0_1_enum =
794 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
795
796static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD934X_CDC_RX0_RX_PATH_MIX_CFG, 2,
797 rx_cf_text);
798
799static const struct soc_enum cf_int1_1_enum =
800 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
801
802static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD934X_CDC_RX1_RX_PATH_MIX_CFG, 2,
803 rx_cf_text);
804
805static const struct soc_enum cf_int2_1_enum =
806 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
807
808static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD934X_CDC_RX2_RX_PATH_MIX_CFG, 2,
809 rx_cf_text);
810
811static const struct soc_enum cf_int3_1_enum =
812 SOC_ENUM_SINGLE(WCD934X_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
813
814static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD934X_CDC_RX3_RX_PATH_MIX_CFG, 2,
815 rx_cf_text);
816
817static const struct soc_enum cf_int4_1_enum =
818 SOC_ENUM_SINGLE(WCD934X_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
819
820static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD934X_CDC_RX4_RX_PATH_MIX_CFG, 2,
821 rx_cf_text);
822
823static const struct soc_enum cf_int7_1_enum =
824 SOC_ENUM_SINGLE(WCD934X_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
825
826static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD934X_CDC_RX7_RX_PATH_MIX_CFG, 2,
827 rx_cf_text);
828
829static const struct soc_enum cf_int8_1_enum =
830 SOC_ENUM_SINGLE(WCD934X_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
831
832static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD934X_CDC_RX8_RX_PATH_MIX_CFG, 2,
833 rx_cf_text);
834
835static const struct soc_enum rx_hph_mode_mux_enum =
836 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
837 rx_hph_mode_mux_text);
838
839static const struct soc_enum slim_rx_mux_enum =
840 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
841
842static const struct soc_enum rx_int0_2_mux_chain_enum =
843 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
844 rx_int0_7_mix_mux_text);
845
846static const struct soc_enum rx_int1_2_mux_chain_enum =
847 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
848 rx_int_mix_mux_text);
849
850static const struct soc_enum rx_int2_2_mux_chain_enum =
851 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
852 rx_int_mix_mux_text);
853
854static const struct soc_enum rx_int3_2_mux_chain_enum =
855 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
856 rx_int_mix_mux_text);
857
858static const struct soc_enum rx_int4_2_mux_chain_enum =
859 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
860 rx_int_mix_mux_text);
861
862static const struct soc_enum rx_int7_2_mux_chain_enum =
863 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
864 rx_int0_7_mix_mux_text);
865
866static const struct soc_enum rx_int8_2_mux_chain_enum =
867 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
868 rx_int_mix_mux_text);
869
870static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
871 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
872 rx_prim_mix_text);
873
874static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
875 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
876 rx_prim_mix_text);
877
878static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
879 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
880 rx_prim_mix_text);
881
882static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
883 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
884 rx_prim_mix_text);
885
886static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
887 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
888 rx_prim_mix_text);
889
890static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
891 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
892 rx_prim_mix_text);
893
894static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
895 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
896 rx_prim_mix_text);
897
898static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
899 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
900 rx_prim_mix_text);
901
902static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
903 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
904 rx_prim_mix_text);
905
906static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
907 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
908 rx_prim_mix_text);
909
910static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
911 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
912 rx_prim_mix_text);
913
914static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
915 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
916 rx_prim_mix_text);
917
918static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
919 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
920 rx_prim_mix_text);
921
922static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
923 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
924 rx_prim_mix_text);
925
926static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
927 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
928 rx_prim_mix_text);
929
930static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
931 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
932 rx_prim_mix_text);
933
934static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
935 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
936 rx_prim_mix_text);
937
938static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
939 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
940 rx_prim_mix_text);
941
942static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
943 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
944 rx_prim_mix_text);
945
946static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
947 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
948 rx_prim_mix_text);
949
950static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
951 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
952 rx_prim_mix_text);
953
954static const struct soc_enum rx_int0_mix2_inp_mux_enum =
955 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 0, 4,
956 rx_sidetone_mix_text);
957
958static const struct soc_enum rx_int1_mix2_inp_mux_enum =
959 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 2, 4,
960 rx_sidetone_mix_text);
961
962static const struct soc_enum rx_int2_mix2_inp_mux_enum =
963 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 4, 4,
964 rx_sidetone_mix_text);
965
966static const struct soc_enum rx_int3_mix2_inp_mux_enum =
967 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0, 6, 4,
968 rx_sidetone_mix_text);
969
970static const struct soc_enum rx_int4_mix2_inp_mux_enum =
971 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 0, 4,
972 rx_sidetone_mix_text);
973
974static const struct soc_enum rx_int7_mix2_inp_mux_enum =
975 SOC_ENUM_SINGLE(WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1, 2, 4,
976 rx_sidetone_mix_text);
977
978static const struct soc_enum iir0_inp0_mux_enum =
979 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,
980 0, 18, iir_inp_mux_text);
981
982static const struct soc_enum iir0_inp1_mux_enum =
983 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,
984 0, 18, iir_inp_mux_text);
985
986static const struct soc_enum iir0_inp2_mux_enum =
987 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,
988 0, 18, iir_inp_mux_text);
989
990static const struct soc_enum iir0_inp3_mux_enum =
991 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,
992 0, 18, iir_inp_mux_text);
993
994static const struct soc_enum iir1_inp0_mux_enum =
995 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,
996 0, 18, iir_inp_mux_text);
997
998static const struct soc_enum iir1_inp1_mux_enum =
999 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,
1000 0, 18, iir_inp_mux_text);
1001
1002static const struct soc_enum iir1_inp2_mux_enum =
1003 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,
1004 0, 18, iir_inp_mux_text);
1005
1006static const struct soc_enum iir1_inp3_mux_enum =
1007 SOC_ENUM_SINGLE(WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,
1008 0, 18, iir_inp_mux_text);
1009
1010static const struct soc_enum rx_int0_dem_inp_mux_enum =
1011 SOC_ENUM_SINGLE(WCD934X_CDC_RX0_RX_PATH_SEC0, 0,
1012 ARRAY_SIZE(rx_int_dem_inp_mux_text),
1013 rx_int_dem_inp_mux_text);
1014
1015static const struct soc_enum rx_int1_dem_inp_mux_enum =
1016 SOC_ENUM_SINGLE(WCD934X_CDC_RX1_RX_PATH_SEC0, 0,
1017 ARRAY_SIZE(rx_int_dem_inp_mux_text),
1018 rx_int_dem_inp_mux_text);
1019
1020static const struct soc_enum rx_int2_dem_inp_mux_enum =
1021 SOC_ENUM_SINGLE(WCD934X_CDC_RX2_RX_PATH_SEC0, 0,
1022 ARRAY_SIZE(rx_int_dem_inp_mux_text),
1023 rx_int_dem_inp_mux_text);
1024
1025static const struct soc_enum tx_adc_mux0_enum =
1026 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0,
1027 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1028static const struct soc_enum tx_adc_mux1_enum =
1029 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0,
1030 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1031static const struct soc_enum tx_adc_mux2_enum =
1032 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0,
1033 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1034static const struct soc_enum tx_adc_mux3_enum =
1035 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0,
1036 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1037static const struct soc_enum tx_adc_mux4_enum =
1038 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 2,
1039 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1040static const struct soc_enum tx_adc_mux5_enum =
1041 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 2,
1042 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1043static const struct soc_enum tx_adc_mux6_enum =
1044 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 2,
1045 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1046static const struct soc_enum tx_adc_mux7_enum =
1047 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 2,
1048 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1049static const struct soc_enum tx_adc_mux8_enum =
1050 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 4,
1051 ARRAY_SIZE(adc_mux_text), adc_mux_text);
1052
1053static const struct soc_enum rx_int0_1_interp_mux_enum =
1054 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1055 rx_int0_1_interp_mux_text);
1056
1057static const struct soc_enum rx_int1_1_interp_mux_enum =
1058 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1059 rx_int1_1_interp_mux_text);
1060
1061static const struct soc_enum rx_int2_1_interp_mux_enum =
1062 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2,
1063 rx_int2_1_interp_mux_text);
1064
1065static const struct soc_enum rx_int3_1_interp_mux_enum =
1066 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_1_interp_mux_text);
1067
1068static const struct soc_enum rx_int4_1_interp_mux_enum =
1069 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_1_interp_mux_text);
1070
1071static const struct soc_enum rx_int7_1_interp_mux_enum =
1072 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_1_interp_mux_text);
1073
1074static const struct soc_enum rx_int8_1_interp_mux_enum =
1075 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_1_interp_mux_text);
1076
1077static const struct soc_enum rx_int0_2_interp_mux_enum =
1078 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int0_2_interp_mux_text);
1079
1080static const struct soc_enum rx_int1_2_interp_mux_enum =
1081 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int1_2_interp_mux_text);
1082
1083static const struct soc_enum rx_int2_2_interp_mux_enum =
1084 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int2_2_interp_mux_text);
1085
1086static const struct soc_enum rx_int3_2_interp_mux_enum =
1087 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int3_2_interp_mux_text);
1088
1089static const struct soc_enum rx_int4_2_interp_mux_enum =
1090 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int4_2_interp_mux_text);
1091
1092static const struct soc_enum rx_int7_2_interp_mux_enum =
1093 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int7_2_interp_mux_text);
1094
1095static const struct soc_enum rx_int8_2_interp_mux_enum =
1096 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, 2, rx_int8_2_interp_mux_text);
1097
1098static const struct soc_enum tx_dmic_mux0_enum =
1099 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 7,
1100 dmic_mux_text);
1101
1102static const struct soc_enum tx_dmic_mux1_enum =
1103 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 7,
1104 dmic_mux_text);
1105
1106static const struct soc_enum tx_dmic_mux2_enum =
1107 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 7,
1108 dmic_mux_text);
1109
1110static const struct soc_enum tx_dmic_mux3_enum =
1111 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 7,
1112 dmic_mux_text);
1113
1114static const struct soc_enum tx_dmic_mux4_enum =
1115 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
1116 dmic_mux_text);
1117
1118static const struct soc_enum tx_dmic_mux5_enum =
1119 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
1120 dmic_mux_text);
1121
1122static const struct soc_enum tx_dmic_mux6_enum =
1123 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
1124 dmic_mux_text);
1125
1126static const struct soc_enum tx_dmic_mux7_enum =
1127 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
1128 dmic_mux_text);
1129
1130static const struct soc_enum tx_dmic_mux8_enum =
1131 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
1132 dmic_mux_text);
1133
1134static const struct soc_enum tx_amic_mux0_enum =
1135 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 5,
1136 amic_mux_text);
1137static const struct soc_enum tx_amic_mux1_enum =
1138 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 5,
1139 amic_mux_text);
1140static const struct soc_enum tx_amic_mux2_enum =
1141 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 5,
1142 amic_mux_text);
1143static const struct soc_enum tx_amic_mux3_enum =
1144 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 5,
1145 amic_mux_text);
1146static const struct soc_enum tx_amic_mux4_enum =
1147 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 5,
1148 amic_mux_text);
1149static const struct soc_enum tx_amic_mux5_enum =
1150 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 5,
1151 amic_mux_text);
1152static const struct soc_enum tx_amic_mux6_enum =
1153 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 5,
1154 amic_mux_text);
1155static const struct soc_enum tx_amic_mux7_enum =
1156 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 5,
1157 amic_mux_text);
1158static const struct soc_enum tx_amic_mux8_enum =
1159 SOC_ENUM_SINGLE(WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 5,
1160 amic_mux_text);
1161
1162static const struct soc_enum tx_amic4_5_enum =
1163 SOC_ENUM_SINGLE(WCD934X_TX_NEW_AMIC_4_5_SEL, 7, 2, amic4_5_sel_text);
1164
1165static const struct soc_enum cdc_if_tx0_mux_enum =
1166 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 0,
1167 ARRAY_SIZE(cdc_if_tx0_mux_text), cdc_if_tx0_mux_text);
1168static const struct soc_enum cdc_if_tx1_mux_enum =
1169 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 2,
1170 ARRAY_SIZE(cdc_if_tx1_mux_text), cdc_if_tx1_mux_text);
1171static const struct soc_enum cdc_if_tx2_mux_enum =
1172 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 4,
1173 ARRAY_SIZE(cdc_if_tx2_mux_text), cdc_if_tx2_mux_text);
1174static const struct soc_enum cdc_if_tx3_mux_enum =
1175 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0, 6,
1176 ARRAY_SIZE(cdc_if_tx3_mux_text), cdc_if_tx3_mux_text);
1177static const struct soc_enum cdc_if_tx4_mux_enum =
1178 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 0,
1179 ARRAY_SIZE(cdc_if_tx4_mux_text), cdc_if_tx4_mux_text);
1180static const struct soc_enum cdc_if_tx5_mux_enum =
1181 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 2,
1182 ARRAY_SIZE(cdc_if_tx5_mux_text), cdc_if_tx5_mux_text);
1183static const struct soc_enum cdc_if_tx6_mux_enum =
1184 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 4,
1185 ARRAY_SIZE(cdc_if_tx6_mux_text), cdc_if_tx6_mux_text);
1186static const struct soc_enum cdc_if_tx7_mux_enum =
1187 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1, 6,
1188 ARRAY_SIZE(cdc_if_tx7_mux_text), cdc_if_tx7_mux_text);
1189static const struct soc_enum cdc_if_tx8_mux_enum =
1190 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 0,
1191 ARRAY_SIZE(cdc_if_tx8_mux_text), cdc_if_tx8_mux_text);
1192static const struct soc_enum cdc_if_tx9_mux_enum =
1193 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 2,
1194 ARRAY_SIZE(cdc_if_tx9_mux_text), cdc_if_tx9_mux_text);
1195static const struct soc_enum cdc_if_tx10_mux_enum =
1196 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2, 4,
1197 ARRAY_SIZE(cdc_if_tx10_mux_text), cdc_if_tx10_mux_text);
1198static const struct soc_enum cdc_if_tx11_inp1_mux_enum =
1199 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 0,
1200 ARRAY_SIZE(cdc_if_tx11_inp1_mux_text),
1201 cdc_if_tx11_inp1_mux_text);
1202static const struct soc_enum cdc_if_tx11_mux_enum =
1203 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX11_INP_CFG, 0,
1204 ARRAY_SIZE(cdc_if_tx11_mux_text), cdc_if_tx11_mux_text);
1205static const struct soc_enum cdc_if_tx13_inp1_mux_enum =
1206 SOC_ENUM_SINGLE(WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3, 4,
1207 ARRAY_SIZE(cdc_if_tx13_inp1_mux_text),
1208 cdc_if_tx13_inp1_mux_text);
1209static const struct soc_enum cdc_if_tx13_mux_enum =
1210 SOC_ENUM_SINGLE(WCD934X_DATA_HUB_SB_TX13_INP_CFG, 0,
1211 ARRAY_SIZE(cdc_if_tx13_mux_text), cdc_if_tx13_mux_text);
1212
1213static const struct wcd_mbhc_field wcd_mbhc_fields[WCD_MBHC_REG_FUNC_MAX] = {
1214 WCD_MBHC_FIELD(WCD_MBHC_L_DET_EN, WCD934X_ANA_MBHC_MECH, 0x80),
1215 WCD_MBHC_FIELD(WCD_MBHC_GND_DET_EN, WCD934X_ANA_MBHC_MECH, 0x40),
1216 WCD_MBHC_FIELD(WCD_MBHC_MECH_DETECTION_TYPE, WCD934X_ANA_MBHC_MECH, 0x20),
1217 WCD_MBHC_FIELD(WCD_MBHC_MIC_CLAMP_CTL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x30),
1218 WCD_MBHC_FIELD(WCD_MBHC_ELECT_DETECTION_TYPE, WCD934X_ANA_MBHC_ELECT, 0x08),
1219 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_CTRL, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0xC0),
1220 WCD_MBHC_FIELD(WCD_MBHC_HS_L_DET_PULL_UP_COMP_CTRL, WCD934X_ANA_MBHC_MECH, 0x04),
1221 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x10),
1222 WCD_MBHC_FIELD(WCD_MBHC_GND_PLUG_TYPE, WCD934X_ANA_MBHC_MECH, 0x08),
1223 WCD_MBHC_FIELD(WCD_MBHC_SW_HPH_LP_100K_TO_GND, WCD934X_ANA_MBHC_MECH, 0x01),
1224 WCD_MBHC_FIELD(WCD_MBHC_ELECT_SCHMT_ISRC, WCD934X_ANA_MBHC_ELECT, 0x06),
1225 WCD_MBHC_FIELD(WCD_MBHC_FSM_EN, WCD934X_ANA_MBHC_ELECT, 0x80),
1226 WCD_MBHC_FIELD(WCD_MBHC_INSREM_DBNC, WCD934X_MBHC_NEW_PLUG_DETECT_CTL, 0x0F),
1227 WCD_MBHC_FIELD(WCD_MBHC_BTN_DBNC, WCD934X_MBHC_NEW_CTL_1, 0x03),
1228 WCD_MBHC_FIELD(WCD_MBHC_HS_VREF, WCD934X_MBHC_NEW_CTL_2, 0x03),
1229 WCD_MBHC_FIELD(WCD_MBHC_HS_COMP_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x08),
1230 WCD_MBHC_FIELD(WCD_MBHC_IN2P_CLAMP_STATE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1231 WCD_MBHC_FIELD(WCD_MBHC_MIC_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x20),
1232 WCD_MBHC_FIELD(WCD_MBHC_HPHL_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x80),
1233 WCD_MBHC_FIELD(WCD_MBHC_HPHR_SCHMT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x40),
1234 WCD_MBHC_FIELD(WCD_MBHC_OCP_FSM_EN, WCD934X_HPH_OCP_CTL, 0x10),
1235 WCD_MBHC_FIELD(WCD_MBHC_BTN_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0x07),
1236 WCD_MBHC_FIELD(WCD_MBHC_BTN_ISRC_CTL, WCD934X_ANA_MBHC_ELECT, 0x70),
1237 WCD_MBHC_FIELD(WCD_MBHC_ELECT_RESULT, WCD934X_ANA_MBHC_RESULT_3, 0xFF),
1238 WCD_MBHC_FIELD(WCD_MBHC_MICB_CTRL, WCD934X_ANA_MICB2, 0xC0),
1239 WCD_MBHC_FIELD(WCD_MBHC_HPH_CNP_WG_TIME, WCD934X_HPH_CNP_WG_TIME, 0xFF),
1240 WCD_MBHC_FIELD(WCD_MBHC_HPHR_PA_EN, WCD934X_ANA_HPH, 0x40),
1241 WCD_MBHC_FIELD(WCD_MBHC_HPHL_PA_EN, WCD934X_ANA_HPH, 0x80),
1242 WCD_MBHC_FIELD(WCD_MBHC_HPH_PA_EN, WCD934X_ANA_HPH, 0xC0),
1243 WCD_MBHC_FIELD(WCD_MBHC_SWCH_LEVEL_REMOVE, WCD934X_ANA_MBHC_RESULT_3, 0x10),
1244 WCD_MBHC_FIELD(WCD_MBHC_ANC_DET_EN, WCD934X_MBHC_CTL_BCS, 0x02),
1245 WCD_MBHC_FIELD(WCD_MBHC_FSM_STATUS, WCD934X_MBHC_STATUS_SPARE_1, 0x01),
1246 WCD_MBHC_FIELD(WCD_MBHC_MUX_CTL, WCD934X_MBHC_NEW_CTL_2, 0x70),
1247 WCD_MBHC_FIELD(WCD_MBHC_MOISTURE_STATUS, WCD934X_MBHC_NEW_FSM_STATUS, 0x20),
1248 WCD_MBHC_FIELD(WCD_MBHC_HPHR_GND, WCD934X_HPH_PA_CTL2, 0x40),
1249 WCD_MBHC_FIELD(WCD_MBHC_HPHL_GND, WCD934X_HPH_PA_CTL2, 0x10),
1250 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_DET_EN, WCD934X_HPH_L_TEST, 0x01),
1251 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_DET_EN, WCD934X_HPH_R_TEST, 0x01),
1252 WCD_MBHC_FIELD(WCD_MBHC_HPHL_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x04),
1253 WCD_MBHC_FIELD(WCD_MBHC_HPHR_OCP_STATUS, WCD934X_INTR_PIN1_STATUS0, 0x08),
1254 WCD_MBHC_FIELD(WCD_MBHC_ADC_EN, WCD934X_MBHC_NEW_CTL_1, 0x08),
1255 WCD_MBHC_FIELD(WCD_MBHC_ADC_COMPLETE, WCD934X_MBHC_NEW_FSM_STATUS, 0x40),
1256 WCD_MBHC_FIELD(WCD_MBHC_ADC_TIMEOUT, WCD934X_MBHC_NEW_FSM_STATUS, 0x80),
1257 WCD_MBHC_FIELD(WCD_MBHC_ADC_RESULT, WCD934X_MBHC_NEW_ADC_RESULT, 0xFF),
1258 WCD_MBHC_FIELD(WCD_MBHC_MICB2_VOUT, WCD934X_ANA_MICB2, 0x3F),
1259 WCD_MBHC_FIELD(WCD_MBHC_ADC_MODE, WCD934X_MBHC_NEW_CTL_1, 0x10),
1260 WCD_MBHC_FIELD(WCD_MBHC_DETECTION_DONE, WCD934X_MBHC_NEW_CTL_1, 0x04),
1261 WCD_MBHC_FIELD(WCD_MBHC_ELECT_ISRC_EN, WCD934X_ANA_MBHC_ZDET, 0x02),
1262};
1263
1264static int wcd934x_set_sido_input_src(struct wcd934x_codec *wcd, int sido_src)
1265{
1266 if (sido_src == wcd->sido_input_src)
1267 return 0;
1268
1269 if (sido_src == SIDO_SOURCE_RCO_BG) {
1270 regmap_update_bits(wcd->regmap, WCD934X_ANA_RCO,
1271 WCD934X_ANA_RCO_BG_EN_MASK,
1272 WCD934X_ANA_RCO_BG_ENABLE);
1273 usleep_range(100, 110);
1274 }
1275 wcd->sido_input_src = sido_src;
1276
1277 return 0;
1278}
1279
1280static int wcd934x_enable_ana_bias_and_sysclk(struct wcd934x_codec *wcd)
1281{
1282 mutex_lock(&wcd->sysclk_mutex);
1283
1284 if (++wcd->sysclk_users != 1) {
1285 mutex_unlock(&wcd->sysclk_mutex);
1286 return 0;
1287 }
1288 mutex_unlock(&wcd->sysclk_mutex);
1289
1290 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1291 WCD934X_ANA_BIAS_EN_MASK,
1292 WCD934X_ANA_BIAS_EN);
1293 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1294 WCD934X_ANA_PRECHRG_EN_MASK,
1295 WCD934X_ANA_PRECHRG_EN);
1296 /*
1297 * 1ms delay is required after pre-charge is enabled
1298 * as per HW requirement
1299 */
1300 usleep_range(1000, 1100);
1301 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1302 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1303 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1304 WCD934X_ANA_PRECHRG_MODE_MASK, 0);
1305
1306 /*
1307 * In data clock contrl register is changed
1308 * to CLK_SYS_MCLK_PRG
1309 */
1310
1311 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1312 WCD934X_EXT_CLK_BUF_EN_MASK,
1313 WCD934X_EXT_CLK_BUF_EN);
1314 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1315 WCD934X_EXT_CLK_DIV_RATIO_MASK,
1316 WCD934X_EXT_CLK_DIV_BY_2);
1317 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1318 WCD934X_MCLK_SRC_MASK,
1319 WCD934X_MCLK_SRC_EXT_CLK);
1320 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1321 WCD934X_MCLK_EN_MASK, WCD934X_MCLK_EN);
1322 regmap_update_bits(wcd->regmap,
1323 WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
1324 WCD934X_CDC_FS_MCLK_CNT_EN_MASK,
1325 WCD934X_CDC_FS_MCLK_CNT_ENABLE);
1326 regmap_update_bits(wcd->regmap,
1327 WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,
1328 WCD934X_MCLK_EN_MASK,
1329 WCD934X_MCLK_EN);
1330 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_GATE,
1331 WCD934X_CODEC_RPM_CLK_GATE_MASK, 0x0);
1332 /*
1333 * 10us sleep is required after clock is enabled
1334 * as per HW requirement
1335 */
1336 usleep_range(10, 15);
1337
1338 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1339
1340 return 0;
1341}
1342
1343static int wcd934x_disable_ana_bias_and_syclk(struct wcd934x_codec *wcd)
1344{
1345 mutex_lock(&wcd->sysclk_mutex);
1346 if (--wcd->sysclk_users != 0) {
1347 mutex_unlock(&wcd->sysclk_mutex);
1348 return 0;
1349 }
1350 mutex_unlock(&wcd->sysclk_mutex);
1351
1352 regmap_update_bits(wcd->regmap, WCD934X_CLK_SYS_MCLK_PRG,
1353 WCD934X_EXT_CLK_BUF_EN_MASK |
1354 WCD934X_MCLK_EN_MASK, 0x0);
1355 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1356 WCD934X_ANA_BIAS_EN_MASK, 0);
1357 regmap_update_bits(wcd->regmap, WCD934X_ANA_BIAS,
1358 WCD934X_ANA_PRECHRG_EN_MASK, 0);
1359
1360 return 0;
1361}
1362
1363static int __wcd934x_cdc_mclk_enable(struct wcd934x_codec *wcd, bool enable)
1364{
1365 int ret = 0;
1366
1367 if (enable) {
1368 ret = clk_prepare_enable(wcd->extclk);
1369
1370 if (ret) {
1371 dev_err(wcd->dev, "%s: ext clk enable failed\n",
1372 __func__);
1373 return ret;
1374 }
1375 ret = wcd934x_enable_ana_bias_and_sysclk(wcd);
1376 } else {
1377 int val;
1378
1379 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1380 &val);
1381
1382 /* Don't disable clock if soundwire using it.*/
1383 if (val & WCD934X_CDC_SWR_CLK_EN_MASK)
1384 return 0;
1385
1386 wcd934x_disable_ana_bias_and_syclk(wcd);
1387 clk_disable_unprepare(wcd->extclk);
1388 }
1389
1390 return ret;
1391}
1392
1393static int wcd934x_codec_enable_mclk(struct snd_soc_dapm_widget *w,
1394 struct snd_kcontrol *kc, int event)
1395{
1396 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
1397 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1398
1399 switch (event) {
1400 case SND_SOC_DAPM_PRE_PMU:
1401 return __wcd934x_cdc_mclk_enable(wcd, true);
1402 case SND_SOC_DAPM_POST_PMD:
1403 return __wcd934x_cdc_mclk_enable(wcd, false);
1404 }
1405
1406 return 0;
1407}
1408
1409static int wcd934x_get_version(struct wcd934x_codec *wcd)
1410{
1411 int val1, val2, ver, ret;
1412 struct regmap *regmap;
1413 u16 id_minor;
1414 u32 version_mask = 0;
1415
1416 regmap = wcd->regmap;
1417 ver = 0;
1418
1419 ret = regmap_bulk_read(regmap, WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,
1420 (u8 *)&id_minor, sizeof(u16));
1421
1422 if (ret)
1423 return ret;
1424
1425 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14, &val1);
1426 regmap_read(regmap, WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15, &val2);
1427
1428 version_mask |= (!!((u8)val1 & 0x80)) << DSD_DISABLED_MASK;
1429 version_mask |= (!!((u8)val2 & 0x01)) << SLNQ_DISABLED_MASK;
1430
1431 switch (version_mask) {
1432 case DSD_DISABLED | SLNQ_DISABLED:
1433 if (id_minor == 0)
1434 ver = WCD_VERSION_WCD9340_1_0;
1435 else if (id_minor == 0x01)
1436 ver = WCD_VERSION_WCD9340_1_1;
1437 break;
1438 case SLNQ_DISABLED:
1439 if (id_minor == 0)
1440 ver = WCD_VERSION_WCD9341_1_0;
1441 else if (id_minor == 0x01)
1442 ver = WCD_VERSION_WCD9341_1_1;
1443 break;
1444 }
1445
1446 wcd->version = ver;
1447 dev_info(wcd->dev, "WCD934X Minor:0x%x Version:0x%x\n", id_minor, ver);
1448
1449 return 0;
1450}
1451
1452static void wcd934x_enable_efuse_sensing(struct wcd934x_codec *wcd)
1453{
1454 int rc, val;
1455
1456 __wcd934x_cdc_mclk_enable(wcd, true);
1457
1458 regmap_update_bits(wcd->regmap,
1459 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1460 WCD934X_EFUSE_SENSE_STATE_MASK,
1461 WCD934X_EFUSE_SENSE_STATE_DEF);
1462 regmap_update_bits(wcd->regmap,
1463 WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,
1464 WCD934X_EFUSE_SENSE_EN_MASK,
1465 WCD934X_EFUSE_SENSE_ENABLE);
1466 /*
1467 * 5ms sleep required after enabling efuse control
1468 * before checking the status.
1469 */
1470 usleep_range(5000, 5500);
1471 wcd934x_set_sido_input_src(wcd, SIDO_SOURCE_RCO_BG);
1472
1473 rc = regmap_read(wcd->regmap,
1474 WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS, &val);
1475 if (rc || (!(val & 0x01)))
1476 WARN(1, "%s: Efuse sense is not complete val=%x, ret=%d\n",
1477 __func__, val, rc);
1478
1479 __wcd934x_cdc_mclk_enable(wcd, false);
1480}
1481
1482static int wcd934x_swrm_clock(struct wcd934x_codec *wcd, bool enable)
1483{
1484 if (enable) {
1485 __wcd934x_cdc_mclk_enable(wcd, true);
1486 regmap_update_bits(wcd->regmap,
1487 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1488 WCD934X_CDC_SWR_CLK_EN_MASK,
1489 WCD934X_CDC_SWR_CLK_ENABLE);
1490 } else {
1491 regmap_update_bits(wcd->regmap,
1492 WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,
1493 WCD934X_CDC_SWR_CLK_EN_MASK, 0);
1494 __wcd934x_cdc_mclk_enable(wcd, false);
1495 }
1496
1497 return 0;
1498}
1499
1500static int wcd934x_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1501 u8 rate_val, u32 rate)
1502{
1503 struct snd_soc_component *comp = dai->component;
1504 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
1505 struct wcd934x_slim_ch *ch;
1506 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1507 int inp, j;
1508
1509 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1510 inp = ch->shift + INTn_1_INP_SEL_RX0;
1511 /*
1512 * Loop through all interpolator MUX inputs and find out
1513 * to which interpolator input, the slim rx port
1514 * is connected
1515 */
1516 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1517 /* Interpolators 5 and 6 are not aviliable in Tavil */
1518 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1519 continue;
1520
1521 cfg0 = snd_soc_component_read(comp,
1522 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1523 cfg1 = snd_soc_component_read(comp,
1524 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1525
1526 inp0_sel = cfg0 &
1527 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1528 inp1_sel = (cfg0 >> 4) &
1529 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1530 inp2_sel = (cfg1 >> 4) &
1531 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1532
1533 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1534 (inp2_sel == inp)) {
1535 /* rate is in Hz */
1536 /*
1537 * Ear and speaker primary path does not support
1538 * native sample rates
1539 */
1540 if ((j == INTERP_EAR || j == INTERP_SPKR1 ||
1541 j == INTERP_SPKR2) && rate == 44100)
1542 dev_err(wcd->dev,
1543 "Cannot set 44.1KHz on INT%d\n",
1544 j);
1545 else
1546 snd_soc_component_update_bits(comp,
1547 WCD934X_CDC_RX_PATH_CTL(j),
1548 WCD934X_CDC_MIX_PCM_RATE_MASK,
1549 rate_val);
1550 }
1551 }
1552 }
1553
1554 return 0;
1555}
1556
1557static int wcd934x_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1558 int rate_val, u32 rate)
1559{
1560 struct snd_soc_component *component = dai->component;
1561 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
1562 struct wcd934x_slim_ch *ch;
1563 int val, j;
1564
1565 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1566 for (j = 0; j < WCD934X_NUM_INTERPOLATORS; j++) {
1567 /* Interpolators 5 and 6 are not aviliable in Tavil */
1568 if (j == INTERP_LO3_NA || j == INTERP_LO4_NA)
1569 continue;
1570 val = snd_soc_component_read(component,
1571 WCD934X_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1572 WCD934X_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1573
1574 if (val == (ch->shift + INTn_2_INP_SEL_RX0)) {
1575 /*
1576 * Ear mix path supports only 48, 96, 192,
1577 * 384KHz only
1578 */
1579 if ((j == INTERP_EAR) &&
1580 (rate_val < 0x4 ||
1581 rate_val > 0x7)) {
1582 dev_err(component->dev,
1583 "Invalid rate for AIF_PB DAI(%d)\n",
1584 dai->id);
1585 return -EINVAL;
1586 }
1587
1588 snd_soc_component_update_bits(component,
1589 WCD934X_CDC_RX_PATH_MIX_CTL(j),
1590 WCD934X_CDC_MIX_PCM_RATE_MASK,
1591 rate_val);
1592 }
1593 }
1594 }
1595
1596 return 0;
1597}
1598
1599static int wcd934x_set_interpolator_rate(struct snd_soc_dai *dai,
1600 u32 sample_rate)
1601{
1602 int rate_val = 0;
1603 int i, ret;
1604
1605 for (i = 0; i < ARRAY_SIZE(sr_val_tbl); i++) {
1606 if (sample_rate == sr_val_tbl[i].sample_rate) {
1607 rate_val = sr_val_tbl[i].rate_val;
1608 break;
1609 }
1610 }
1611 if ((i == ARRAY_SIZE(sr_val_tbl)) || (rate_val < 0)) {
1612 dev_err(dai->dev, "Unsupported sample rate: %d\n", sample_rate);
1613 return -EINVAL;
1614 }
1615
1616 ret = wcd934x_set_prim_interpolator_rate(dai, (u8)rate_val,
1617 sample_rate);
1618 if (ret)
1619 return ret;
1620 ret = wcd934x_set_mix_interpolator_rate(dai, (u8)rate_val,
1621 sample_rate);
1622
1623 return ret;
1624}
1625
1626static int wcd934x_set_decimator_rate(struct snd_soc_dai *dai,
1627 u8 rate_val, u32 rate)
1628{
1629 struct snd_soc_component *comp = dai->component;
1630 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
1631 u8 shift = 0, shift_val = 0, tx_mux_sel;
1632 struct wcd934x_slim_ch *ch;
1633 int tx_port, tx_port_reg;
1634 int decimator = -1;
1635
1636 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1637 tx_port = ch->port;
1638 /* Find the SB TX MUX input - which decimator is connected */
1639 switch (tx_port) {
1640 case 0 ... 3:
1641 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0;
1642 shift = (tx_port << 1);
1643 shift_val = 0x03;
1644 break;
1645 case 4 ... 7:
1646 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1;
1647 shift = ((tx_port - 4) << 1);
1648 shift_val = 0x03;
1649 break;
1650 case 8 ... 10:
1651 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2;
1652 shift = ((tx_port - 8) << 1);
1653 shift_val = 0x03;
1654 break;
1655 case 11:
1656 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1657 shift = 0;
1658 shift_val = 0x0F;
1659 break;
1660 case 13:
1661 tx_port_reg = WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3;
1662 shift = 4;
1663 shift_val = 0x03;
1664 break;
1665 default:
1666 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1667 tx_port, dai->id);
1668 return -EINVAL;
1669 }
1670
1671 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1672 (shift_val << shift);
1673
1674 tx_mux_sel = tx_mux_sel >> shift;
1675 switch (tx_port) {
1676 case 0 ... 8:
1677 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1678 decimator = tx_port;
1679 break;
1680 case 9 ... 10:
1681 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1682 decimator = ((tx_port == 9) ? 7 : 6);
1683 break;
1684 case 11:
1685 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1686 decimator = tx_mux_sel - 1;
1687 break;
1688 case 13:
1689 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1690 decimator = 5;
1691 break;
1692 default:
1693 dev_err(wcd->dev, "ERROR: Invalid tx_port: %d\n",
1694 tx_port);
1695 return -EINVAL;
1696 }
1697
1698 snd_soc_component_update_bits(comp,
1699 WCD934X_CDC_TX_PATH_CTL(decimator),
1700 WCD934X_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1701 rate_val);
1702 }
1703
1704 return 0;
1705}
1706
1707static int wcd934x_slim_set_hw_params(struct wcd934x_codec *wcd,
1708 struct wcd_slim_codec_dai_data *dai_data,
1709 int direction)
1710{
1711 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1712 struct slim_stream_config *cfg = &dai_data->sconfig;
1713 struct wcd934x_slim_ch *ch;
1714 u16 payload = 0;
1715 int ret, i;
1716
1717 cfg->ch_count = 0;
1718 cfg->direction = direction;
1719 cfg->port_mask = 0;
1720
1721 /* Configure slave interface device */
1722 list_for_each_entry(ch, slim_ch_list, list) {
1723 cfg->ch_count++;
1724 payload |= 1 << ch->shift;
1725 cfg->port_mask |= BIT(ch->port);
1726 }
1727
1728 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1729 if (!cfg->chs)
1730 return -ENOMEM;
1731
1732 i = 0;
1733 list_for_each_entry(ch, slim_ch_list, list) {
1734 cfg->chs[i++] = ch->ch_num;
1735 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1736 /* write to interface device */
1737 ret = regmap_write(wcd->if_regmap,
1738 WCD934X_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1739 payload);
1740
1741 if (ret < 0)
1742 goto err;
1743
1744 /* configure the slave port for water mark and enable*/
1745 ret = regmap_write(wcd->if_regmap,
1746 WCD934X_SLIM_PGD_RX_PORT_CFG(ch->port),
1747 WCD934X_SLIM_WATER_MARK_VAL);
1748 if (ret < 0)
1749 goto err;
1750 } else {
1751 ret = regmap_write(wcd->if_regmap,
1752 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1753 payload & 0x00FF);
1754 if (ret < 0)
1755 goto err;
1756
1757 /* ports 8,9 */
1758 ret = regmap_write(wcd->if_regmap,
1759 WCD934X_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1760 (payload & 0xFF00) >> 8);
1761 if (ret < 0)
1762 goto err;
1763
1764 /* configure the slave port for water mark and enable*/
1765 ret = regmap_write(wcd->if_regmap,
1766 WCD934X_SLIM_PGD_TX_PORT_CFG(ch->port),
1767 WCD934X_SLIM_WATER_MARK_VAL);
1768
1769 if (ret < 0)
1770 goto err;
1771 }
1772 }
1773
1774 dai_data->sruntime = slim_stream_allocate(wcd->sdev, "WCD934x-SLIM");
1775
1776 return 0;
1777
1778err:
1779 dev_err(wcd->dev, "Error Setting slim hw params\n");
1780 kfree(cfg->chs);
1781 cfg->chs = NULL;
1782
1783 return ret;
1784}
1785
1786static int wcd934x_hw_params(struct snd_pcm_substream *substream,
1787 struct snd_pcm_hw_params *params,
1788 struct snd_soc_dai *dai)
1789{
1790 struct wcd934x_codec *wcd;
1791 int ret, tx_fs_rate = 0;
1792
1793 wcd = snd_soc_component_get_drvdata(dai->component);
1794
1795 switch (substream->stream) {
1796 case SNDRV_PCM_STREAM_PLAYBACK:
1797 ret = wcd934x_set_interpolator_rate(dai, params_rate(params));
1798 if (ret) {
1799 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1800 params_rate(params));
1801 return ret;
1802 }
1803 switch (params_width(params)) {
1804 case 16 ... 24:
1805 wcd->dai[dai->id].sconfig.bps = params_width(params);
1806 break;
1807 default:
1808 dev_err(wcd->dev, "Invalid format 0x%x\n",
1809 params_width(params));
1810 return -EINVAL;
1811 }
1812 break;
1813
1814 case SNDRV_PCM_STREAM_CAPTURE:
1815 switch (params_rate(params)) {
1816 case 8000:
1817 tx_fs_rate = 0;
1818 break;
1819 case 16000:
1820 tx_fs_rate = 1;
1821 break;
1822 case 32000:
1823 tx_fs_rate = 3;
1824 break;
1825 case 48000:
1826 tx_fs_rate = 4;
1827 break;
1828 case 96000:
1829 tx_fs_rate = 5;
1830 break;
1831 case 192000:
1832 tx_fs_rate = 6;
1833 break;
1834 case 384000:
1835 tx_fs_rate = 7;
1836 break;
1837 default:
1838 dev_err(wcd->dev, "Invalid TX sample rate: %d\n",
1839 params_rate(params));
1840 return -EINVAL;
1841
1842 }
1843
1844 ret = wcd934x_set_decimator_rate(dai, tx_fs_rate,
1845 params_rate(params));
1846 if (ret < 0) {
1847 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1848 return ret;
1849 }
1850 switch (params_width(params)) {
1851 case 16 ... 32:
1852 wcd->dai[dai->id].sconfig.bps = params_width(params);
1853 break;
1854 default:
1855 dev_err(wcd->dev, "Invalid format 0x%x\n",
1856 params_width(params));
1857 return -EINVAL;
1858 }
1859 break;
1860 default:
1861 dev_err(wcd->dev, "Invalid stream type %d\n",
1862 substream->stream);
1863 return -EINVAL;
1864 }
1865
1866 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1867
1868 return wcd934x_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1869}
1870
1871static int wcd934x_hw_free(struct snd_pcm_substream *substream,
1872 struct snd_soc_dai *dai)
1873{
1874 struct wcd_slim_codec_dai_data *dai_data;
1875 struct wcd934x_codec *wcd;
1876
1877 wcd = snd_soc_component_get_drvdata(dai->component);
1878
1879 dai_data = &wcd->dai[dai->id];
1880
1881 kfree(dai_data->sconfig.chs);
1882
1883 return 0;
1884}
1885
1886static int wcd934x_trigger(struct snd_pcm_substream *substream, int cmd,
1887 struct snd_soc_dai *dai)
1888{
1889 struct wcd_slim_codec_dai_data *dai_data;
1890 struct wcd934x_codec *wcd;
1891 struct slim_stream_config *cfg;
1892
1893 wcd = snd_soc_component_get_drvdata(dai->component);
1894
1895 dai_data = &wcd->dai[dai->id];
1896
1897 switch (cmd) {
1898 case SNDRV_PCM_TRIGGER_START:
1899 case SNDRV_PCM_TRIGGER_RESUME:
1900 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1901 cfg = &dai_data->sconfig;
1902 slim_stream_prepare(dai_data->sruntime, cfg);
1903 slim_stream_enable(dai_data->sruntime);
1904 break;
1905 case SNDRV_PCM_TRIGGER_STOP:
1906 case SNDRV_PCM_TRIGGER_SUSPEND:
1907 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1908 slim_stream_disable(dai_data->sruntime);
1909 slim_stream_unprepare(dai_data->sruntime);
1910 break;
1911 default:
1912 break;
1913 }
1914
1915 return 0;
1916}
1917
1918static int wcd934x_set_channel_map(struct snd_soc_dai *dai,
1919 unsigned int tx_num,
1920 const unsigned int *tx_slot,
1921 unsigned int rx_num,
1922 const unsigned int *rx_slot)
1923{
1924 struct wcd934x_codec *wcd;
1925 int i;
1926
1927 wcd = snd_soc_component_get_drvdata(dai->component);
1928
1929 if (tx_num > WCD934X_TX_MAX || rx_num > WCD934X_RX_MAX) {
1930 dev_err(wcd->dev, "Invalid tx %d or rx %d channel count\n",
1931 tx_num, rx_num);
1932 return -EINVAL;
1933 }
1934
1935 if (!tx_slot || !rx_slot) {
1936 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1937 tx_slot, rx_slot);
1938 return -EINVAL;
1939 }
1940
1941 wcd->num_rx_port = rx_num;
1942 for (i = 0; i < rx_num; i++) {
1943 wcd->rx_chs[i].ch_num = rx_slot[i];
1944 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
1945 }
1946
1947 wcd->num_tx_port = tx_num;
1948 for (i = 0; i < tx_num; i++) {
1949 wcd->tx_chs[i].ch_num = tx_slot[i];
1950 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
1951 }
1952
1953 return 0;
1954}
1955
1956static int wcd934x_get_channel_map(const struct snd_soc_dai *dai,
1957 unsigned int *tx_num, unsigned int *tx_slot,
1958 unsigned int *rx_num, unsigned int *rx_slot)
1959{
1960 struct wcd934x_slim_ch *ch;
1961 struct wcd934x_codec *wcd;
1962 int i = 0;
1963
1964 wcd = snd_soc_component_get_drvdata(dai->component);
1965
1966 switch (dai->id) {
1967 case AIF1_PB:
1968 case AIF2_PB:
1969 case AIF3_PB:
1970 case AIF4_PB:
1971 if (!rx_slot || !rx_num) {
1972 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
1973 rx_slot, rx_num);
1974 return -EINVAL;
1975 }
1976
1977 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1978 rx_slot[i++] = ch->ch_num;
1979
1980 *rx_num = i;
1981 break;
1982 case AIF1_CAP:
1983 case AIF2_CAP:
1984 case AIF3_CAP:
1985 if (!tx_slot || !tx_num) {
1986 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
1987 tx_slot, tx_num);
1988 return -EINVAL;
1989 }
1990
1991 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
1992 tx_slot[i++] = ch->ch_num;
1993
1994 *tx_num = i;
1995 break;
1996 default:
1997 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
1998 break;
1999 }
2000
2001 return 0;
2002}
2003
2004static const struct snd_soc_dai_ops wcd934x_dai_ops = {
2005 .hw_params = wcd934x_hw_params,
2006 .hw_free = wcd934x_hw_free,
2007 .trigger = wcd934x_trigger,
2008 .set_channel_map = wcd934x_set_channel_map,
2009 .get_channel_map = wcd934x_get_channel_map,
2010};
2011
2012static struct snd_soc_dai_driver wcd934x_slim_dais[] = {
2013 [0] = {
2014 .name = "wcd934x_rx1",
2015 .id = AIF1_PB,
2016 .playback = {
2017 .stream_name = "AIF1 Playback",
2018 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2019 .formats = WCD934X_FORMATS_S16_S24_LE,
2020 .rate_max = 192000,
2021 .rate_min = 8000,
2022 .channels_min = 1,
2023 .channels_max = 2,
2024 },
2025 .ops = &wcd934x_dai_ops,
2026 },
2027 [1] = {
2028 .name = "wcd934x_tx1",
2029 .id = AIF1_CAP,
2030 .capture = {
2031 .stream_name = "AIF1 Capture",
2032 .rates = WCD934X_RATES_MASK,
2033 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2034 .rate_min = 8000,
2035 .rate_max = 192000,
2036 .channels_min = 1,
2037 .channels_max = 4,
2038 },
2039 .ops = &wcd934x_dai_ops,
2040 },
2041 [2] = {
2042 .name = "wcd934x_rx2",
2043 .id = AIF2_PB,
2044 .playback = {
2045 .stream_name = "AIF2 Playback",
2046 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2047 .formats = WCD934X_FORMATS_S16_S24_LE,
2048 .rate_min = 8000,
2049 .rate_max = 192000,
2050 .channels_min = 1,
2051 .channels_max = 2,
2052 },
2053 .ops = &wcd934x_dai_ops,
2054 },
2055 [3] = {
2056 .name = "wcd934x_tx2",
2057 .id = AIF2_CAP,
2058 .capture = {
2059 .stream_name = "AIF2 Capture",
2060 .rates = WCD934X_RATES_MASK,
2061 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2062 .rate_min = 8000,
2063 .rate_max = 192000,
2064 .channels_min = 1,
2065 .channels_max = 4,
2066 },
2067 .ops = &wcd934x_dai_ops,
2068 },
2069 [4] = {
2070 .name = "wcd934x_rx3",
2071 .id = AIF3_PB,
2072 .playback = {
2073 .stream_name = "AIF3 Playback",
2074 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2075 .formats = WCD934X_FORMATS_S16_S24_LE,
2076 .rate_min = 8000,
2077 .rate_max = 192000,
2078 .channels_min = 1,
2079 .channels_max = 2,
2080 },
2081 .ops = &wcd934x_dai_ops,
2082 },
2083 [5] = {
2084 .name = "wcd934x_tx3",
2085 .id = AIF3_CAP,
2086 .capture = {
2087 .stream_name = "AIF3 Capture",
2088 .rates = WCD934X_RATES_MASK,
2089 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2090 .rate_min = 8000,
2091 .rate_max = 192000,
2092 .channels_min = 1,
2093 .channels_max = 4,
2094 },
2095 .ops = &wcd934x_dai_ops,
2096 },
2097 [6] = {
2098 .name = "wcd934x_rx4",
2099 .id = AIF4_PB,
2100 .playback = {
2101 .stream_name = "AIF4 Playback",
2102 .rates = WCD934X_RATES_MASK | WCD934X_FRAC_RATES_MASK,
2103 .formats = WCD934X_FORMATS_S16_S24_LE,
2104 .rate_min = 8000,
2105 .rate_max = 192000,
2106 .channels_min = 1,
2107 .channels_max = 2,
2108 },
2109 .ops = &wcd934x_dai_ops,
2110 },
2111};
2112
2113static int swclk_gate_enable(struct clk_hw *hw)
2114{
2115 return wcd934x_swrm_clock(to_wcd934x_codec(hw), true);
2116}
2117
2118static void swclk_gate_disable(struct clk_hw *hw)
2119{
2120 wcd934x_swrm_clock(to_wcd934x_codec(hw), false);
2121}
2122
2123static int swclk_gate_is_enabled(struct clk_hw *hw)
2124{
2125 struct wcd934x_codec *wcd = to_wcd934x_codec(hw);
2126 int ret, val;
2127
2128 regmap_read(wcd->regmap, WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL, &val);
2129 ret = val & WCD934X_CDC_SWR_CLK_EN_MASK;
2130
2131 return ret;
2132}
2133
2134static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2135 unsigned long parent_rate)
2136{
2137 return parent_rate / 2;
2138}
2139
2140static const struct clk_ops swclk_gate_ops = {
2141 .prepare = swclk_gate_enable,
2142 .unprepare = swclk_gate_disable,
2143 .is_enabled = swclk_gate_is_enabled,
2144 .recalc_rate = swclk_recalc_rate,
2145
2146};
2147
2148static struct clk *wcd934x_register_mclk_output(struct wcd934x_codec *wcd)
2149{
2150 struct clk *parent = wcd->extclk;
2151 struct device *dev = wcd->dev;
2152 struct device_node *np = dev->parent->of_node;
2153 const char *parent_clk_name = NULL;
2154 const char *clk_name = "mclk";
2155 struct clk_hw *hw;
2156 struct clk_init_data init;
2157 int ret;
2158
2159 if (of_property_read_u32(np, "clock-frequency", &wcd->rate))
2160 return NULL;
2161
2162 parent_clk_name = __clk_get_name(parent);
2163
2164 of_property_read_string(np, "clock-output-names", &clk_name);
2165
2166 init.name = clk_name;
2167 init.ops = &swclk_gate_ops;
2168 init.flags = 0;
2169 init.parent_names = &parent_clk_name;
2170 init.num_parents = 1;
2171 wcd->hw.init = &init;
2172
2173 hw = &wcd->hw;
2174 ret = devm_clk_hw_register(wcd->dev->parent, hw);
2175 if (ret)
2176 return ERR_PTR(ret);
2177
2178 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2179 if (ret)
2180 return ERR_PTR(ret);
2181
2182 return NULL;
2183}
2184
2185static int wcd934x_get_micbias_val(struct device *dev, const char *micbias,
2186 u32 *micb_mv)
2187{
2188 int mv;
2189
2190 if (of_property_read_u32(dev->parent->of_node, micbias, &mv)) {
2191 dev_err(dev, "%s value not found, using default\n", micbias);
2192 mv = WCD934X_DEF_MICBIAS_MV;
2193 } else {
2194 /* convert it to milli volts */
2195 mv = mv/1000;
2196 }
2197
2198 if (mv < 1000 || mv > 2850) {
2199 dev_err(dev, "%s value not in valid range, using default\n",
2200 micbias);
2201 mv = WCD934X_DEF_MICBIAS_MV;
2202 }
2203
2204 if (micb_mv)
2205 *micb_mv = mv;
2206
2207 return (mv - 1000) / 50;
2208}
2209
2210static int wcd934x_init_dmic(struct snd_soc_component *comp)
2211{
2212 int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
2213 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
2214 u32 def_dmic_rate, dmic_clk_drv;
2215
2216 vout_ctl_1 = wcd934x_get_micbias_val(comp->dev,
2217 "qcom,micbias1-microvolt", NULL);
2218 vout_ctl_2 = wcd934x_get_micbias_val(comp->dev,
2219 "qcom,micbias2-microvolt",
2220 &wcd->micb2_mv);
2221 vout_ctl_3 = wcd934x_get_micbias_val(comp->dev,
2222 "qcom,micbias3-microvolt", NULL);
2223 vout_ctl_4 = wcd934x_get_micbias_val(comp->dev,
2224 "qcom,micbias4-microvolt", NULL);
2225
2226 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB1,
2227 WCD934X_MICB_VAL_MASK, vout_ctl_1);
2228 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB2,
2229 WCD934X_MICB_VAL_MASK, vout_ctl_2);
2230 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB3,
2231 WCD934X_MICB_VAL_MASK, vout_ctl_3);
2232 snd_soc_component_update_bits(comp, WCD934X_ANA_MICB4,
2233 WCD934X_MICB_VAL_MASK, vout_ctl_4);
2234
2235 if (wcd->rate == WCD934X_MCLK_CLK_9P6MHZ)
2236 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
2237 else
2238 def_dmic_rate = WCD9XXX_DMIC_SAMPLE_RATE_4P096MHZ;
2239
2240 wcd->dmic_sample_rate = def_dmic_rate;
2241
2242 dmic_clk_drv = 0;
2243 snd_soc_component_update_bits(comp, WCD934X_TEST_DEBUG_PAD_DRVCTL_0,
2244 0x0C, dmic_clk_drv << 2);
2245
2246 return 0;
2247}
2248
2249static void wcd934x_hw_init(struct wcd934x_codec *wcd)
2250{
2251 struct regmap *rm = wcd->regmap;
2252
2253 /* set SPKR rate to FS_2P4_3P072 */
2254 regmap_update_bits(rm, WCD934X_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08);
2255 regmap_update_bits(rm, WCD934X_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08);
2256
2257 /* Take DMICs out of reset */
2258 regmap_update_bits(rm, WCD934X_CPE_SS_DMIC_CFG, 0x80, 0x00);
2259}
2260
2261static int wcd934x_comp_init(struct snd_soc_component *component)
2262{
2263 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2264
2265 wcd934x_hw_init(wcd);
2266 wcd934x_enable_efuse_sensing(wcd);
2267 wcd934x_get_version(wcd);
2268
2269 return 0;
2270}
2271
2272static irqreturn_t wcd934x_slim_irq_handler(int irq, void *data)
2273{
2274 struct wcd934x_codec *wcd = data;
2275 unsigned long status = 0;
2276 int i, j, port_id;
2277 unsigned int val, int_val = 0;
2278 irqreturn_t ret = IRQ_NONE;
2279 bool tx;
2280 unsigned short reg = 0;
2281
2282 for (i = WCD934X_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
2283 i <= WCD934X_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
2284 regmap_read(wcd->if_regmap, i, &val);
2285 status |= ((u32)val << (8 * j));
2286 }
2287
2288 for_each_set_bit(j, &status, 32) {
2289 tx = false;
2290 port_id = j;
2291
2292 if (j >= 16) {
2293 tx = true;
2294 port_id = j - 16;
2295 }
2296
2297 regmap_read(wcd->if_regmap,
2298 WCD934X_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
2299 if (val) {
2300 if (!tx)
2301 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2302 (port_id / 8);
2303 else
2304 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2305 (port_id / 8);
2306 regmap_read(wcd->if_regmap, reg, &int_val);
2307 }
2308
2309 if (val & WCD934X_SLIM_IRQ_OVERFLOW)
2310 dev_err_ratelimited(wcd->dev,
2311 "overflow error on %s port %d, value %x\n",
2312 (tx ? "TX" : "RX"), port_id, val);
2313
2314 if (val & WCD934X_SLIM_IRQ_UNDERFLOW)
2315 dev_err_ratelimited(wcd->dev,
2316 "underflow error on %s port %d, value %x\n",
2317 (tx ? "TX" : "RX"), port_id, val);
2318
2319 if ((val & WCD934X_SLIM_IRQ_OVERFLOW) ||
2320 (val & WCD934X_SLIM_IRQ_UNDERFLOW)) {
2321 if (!tx)
2322 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 +
2323 (port_id / 8);
2324 else
2325 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 +
2326 (port_id / 8);
2327 regmap_read(
2328 wcd->if_regmap, reg, &int_val);
2329 if (int_val & (1 << (port_id % 8))) {
2330 int_val = int_val ^ (1 << (port_id % 8));
2331 regmap_write(wcd->if_regmap,
2332 reg, int_val);
2333 }
2334 }
2335
2336 if (val & WCD934X_SLIM_IRQ_PORT_CLOSED)
2337 dev_err_ratelimited(wcd->dev,
2338 "Port Closed %s port %d, value %x\n",
2339 (tx ? "TX" : "RX"), port_id, val);
2340
2341 regmap_write(wcd->if_regmap,
2342 WCD934X_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
2343 BIT(j % 8));
2344 ret = IRQ_HANDLED;
2345 }
2346
2347 return ret;
2348}
2349
2350static void wcd934x_mbhc_clk_setup(struct snd_soc_component *component,
2351 bool enable)
2352{
2353 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_CTL_1,
2354 WCD934X_MBHC_CTL_RCO_EN_MASK, enable);
2355}
2356
2357static void wcd934x_mbhc_mbhc_bias_control(struct snd_soc_component *component,
2358 bool enable)
2359{
2360 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_ELECT,
2361 WCD934X_ANA_MBHC_BIAS_EN, enable);
2362}
2363
2364static void wcd934x_mbhc_program_btn_thr(struct snd_soc_component *component,
2365 int *btn_low, int *btn_high,
2366 int num_btn, bool is_micbias)
2367{
2368 int i, vth;
2369
2370 if (num_btn > WCD_MBHC_DEF_BUTTONS) {
2371 dev_err(component->dev, "%s: invalid number of buttons: %d\n",
2372 __func__, num_btn);
2373 return;
2374 }
2375
2376 for (i = 0; i < num_btn; i++) {
2377 vth = ((btn_high[i] * 2) / 25) & 0x3F;
2378 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_BTN0 + i,
2379 WCD934X_MBHC_BTN_VTH_MASK, vth);
2380 }
2381}
2382
2383static bool wcd934x_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
2384{
2385 u8 val;
2386
2387 if (micb_num == MIC_BIAS_2) {
2388 val = snd_soc_component_read_field(component, WCD934X_ANA_MICB2,
2389 WCD934X_ANA_MICB2_ENABLE_MASK);
2390 if (val == WCD934X_MICB_ENABLE)
2391 return true;
2392 }
2393 return false;
2394}
2395
2396static void wcd934x_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
2397 enum mbhc_hs_pullup_iref pull_up_cur)
2398{
2399 /* Default pull up current to 2uA */
2400 if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA ||
2401 pull_up_cur == I_DEFAULT)
2402 pull_up_cur = I_2P0_UA;
2403
2404
2405 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_PLUG_DETECT_CTL,
2406 WCD934X_HSDET_PULLUP_C_MASK, pull_up_cur);
2407}
2408
2409static int wcd934x_micbias_control(struct snd_soc_component *component,
2410 int micb_num, int req, bool is_dapm)
2411{
2412 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2413 int micb_index = micb_num - 1;
2414 u16 micb_reg;
2415
2416 switch (micb_num) {
2417 case MIC_BIAS_1:
2418 micb_reg = WCD934X_ANA_MICB1;
2419 break;
2420 case MIC_BIAS_2:
2421 micb_reg = WCD934X_ANA_MICB2;
2422 break;
2423 case MIC_BIAS_3:
2424 micb_reg = WCD934X_ANA_MICB3;
2425 break;
2426 case MIC_BIAS_4:
2427 micb_reg = WCD934X_ANA_MICB4;
2428 break;
2429 default:
2430 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2431 __func__, micb_num);
2432 return -EINVAL;
2433 }
2434 mutex_lock(&wcd934x->micb_lock);
2435
2436 switch (req) {
2437 case MICB_PULLUP_ENABLE:
2438 wcd934x->pullup_ref[micb_index]++;
2439 if ((wcd934x->pullup_ref[micb_index] == 1) &&
2440 (wcd934x->micb_ref[micb_index] == 0))
2441 snd_soc_component_write_field(component, micb_reg,
2442 WCD934X_ANA_MICB_EN_MASK,
2443 WCD934X_MICB_PULL_UP);
2444 break;
2445 case MICB_PULLUP_DISABLE:
2446 if (wcd934x->pullup_ref[micb_index] > 0)
2447 wcd934x->pullup_ref[micb_index]--;
2448
2449 if ((wcd934x->pullup_ref[micb_index] == 0) &&
2450 (wcd934x->micb_ref[micb_index] == 0))
2451 snd_soc_component_write_field(component, micb_reg,
2452 WCD934X_ANA_MICB_EN_MASK, 0);
2453 break;
2454 case MICB_ENABLE:
2455 wcd934x->micb_ref[micb_index]++;
2456 if (wcd934x->micb_ref[micb_index] == 1) {
2457 snd_soc_component_write_field(component, micb_reg,
2458 WCD934X_ANA_MICB_EN_MASK,
2459 WCD934X_MICB_ENABLE);
2460 if (micb_num == MIC_BIAS_2)
2461 wcd_mbhc_event_notify(wcd934x->mbhc,
2462 WCD_EVENT_POST_MICBIAS_2_ON);
2463 }
2464
2465 if (micb_num == MIC_BIAS_2 && is_dapm)
2466 wcd_mbhc_event_notify(wcd934x->mbhc,
2467 WCD_EVENT_POST_DAPM_MICBIAS_2_ON);
2468 break;
2469 case MICB_DISABLE:
2470 if (wcd934x->micb_ref[micb_index] > 0)
2471 wcd934x->micb_ref[micb_index]--;
2472
2473 if ((wcd934x->micb_ref[micb_index] == 0) &&
2474 (wcd934x->pullup_ref[micb_index] > 0))
2475 snd_soc_component_write_field(component, micb_reg,
2476 WCD934X_ANA_MICB_EN_MASK,
2477 WCD934X_MICB_PULL_UP);
2478 else if ((wcd934x->micb_ref[micb_index] == 0) &&
2479 (wcd934x->pullup_ref[micb_index] == 0)) {
2480 if (micb_num == MIC_BIAS_2)
2481 wcd_mbhc_event_notify(wcd934x->mbhc,
2482 WCD_EVENT_PRE_MICBIAS_2_OFF);
2483
2484 snd_soc_component_write_field(component, micb_reg,
2485 WCD934X_ANA_MICB_EN_MASK, 0);
2486 if (micb_num == MIC_BIAS_2)
2487 wcd_mbhc_event_notify(wcd934x->mbhc,
2488 WCD_EVENT_POST_MICBIAS_2_OFF);
2489 }
2490 if (is_dapm && micb_num == MIC_BIAS_2)
2491 wcd_mbhc_event_notify(wcd934x->mbhc,
2492 WCD_EVENT_POST_DAPM_MICBIAS_2_OFF);
2493 break;
2494 }
2495
2496 mutex_unlock(&wcd934x->micb_lock);
2497
2498 return 0;
2499}
2500
2501static int wcd934x_mbhc_request_micbias(struct snd_soc_component *component,
2502 int micb_num, int req)
2503{
2504 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
2505 int ret;
2506
2507 if (req == MICB_ENABLE)
2508 __wcd934x_cdc_mclk_enable(wcd, true);
2509
2510 ret = wcd934x_micbias_control(component, micb_num, req, false);
2511
2512 if (req == MICB_DISABLE)
2513 __wcd934x_cdc_mclk_enable(wcd, false);
2514
2515 return ret;
2516}
2517
2518static void wcd934x_mbhc_micb_ramp_control(struct snd_soc_component *component,
2519 bool enable)
2520{
2521 if (enable) {
2522 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2523 WCD934X_RAMP_SHIFT_CTRL_MASK, 0x3);
2524 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2525 WCD934X_RAMP_EN_MASK, 1);
2526 } else {
2527 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2528 WCD934X_RAMP_EN_MASK, 0);
2529 snd_soc_component_write_field(component, WCD934X_ANA_MICB2_RAMP,
2530 WCD934X_RAMP_SHIFT_CTRL_MASK, 0);
2531 }
2532}
2533
2534static int wcd934x_get_micb_vout_ctl_val(u32 micb_mv)
2535{
2536 /* min micbias voltage is 1V and maximum is 2.85V */
2537 if (micb_mv < 1000 || micb_mv > 2850)
2538 return -EINVAL;
2539
2540 return (micb_mv - 1000) / 50;
2541}
2542
2543static int wcd934x_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
2544 int req_volt, int micb_num)
2545{
2546 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2547 int cur_vout_ctl, req_vout_ctl, micb_reg, micb_en, ret = 0;
2548
2549 switch (micb_num) {
2550 case MIC_BIAS_1:
2551 micb_reg = WCD934X_ANA_MICB1;
2552 break;
2553 case MIC_BIAS_2:
2554 micb_reg = WCD934X_ANA_MICB2;
2555 break;
2556 case MIC_BIAS_3:
2557 micb_reg = WCD934X_ANA_MICB3;
2558 break;
2559 case MIC_BIAS_4:
2560 micb_reg = WCD934X_ANA_MICB4;
2561 break;
2562 default:
2563 return -EINVAL;
2564 }
2565 mutex_lock(&wcd934x->micb_lock);
2566 /*
2567 * If requested micbias voltage is same as current micbias
2568 * voltage, then just return. Otherwise, adjust voltage as
2569 * per requested value. If micbias is already enabled, then
2570 * to avoid slow micbias ramp-up or down enable pull-up
2571 * momentarily, change the micbias value and then re-enable
2572 * micbias.
2573 */
2574 micb_en = snd_soc_component_read_field(component, micb_reg,
2575 WCD934X_ANA_MICB_EN_MASK);
2576 cur_vout_ctl = snd_soc_component_read_field(component, micb_reg,
2577 WCD934X_MICB_VAL_MASK);
2578
2579 req_vout_ctl = wcd934x_get_micb_vout_ctl_val(req_volt);
2580 if (req_vout_ctl < 0) {
2581 ret = -EINVAL;
2582 goto exit;
2583 }
2584
2585 if (cur_vout_ctl == req_vout_ctl) {
2586 ret = 0;
2587 goto exit;
2588 }
2589
2590 if (micb_en == WCD934X_MICB_ENABLE)
2591 snd_soc_component_write_field(component, micb_reg,
2592 WCD934X_ANA_MICB_EN_MASK,
2593 WCD934X_MICB_PULL_UP);
2594
2595 snd_soc_component_write_field(component, micb_reg,
2596 WCD934X_MICB_VAL_MASK,
2597 req_vout_ctl);
2598
2599 if (micb_en == WCD934X_MICB_ENABLE) {
2600 snd_soc_component_write_field(component, micb_reg,
2601 WCD934X_ANA_MICB_EN_MASK,
2602 WCD934X_MICB_ENABLE);
2603 /*
2604 * Add 2ms delay as per HW requirement after enabling
2605 * micbias
2606 */
2607 usleep_range(2000, 2100);
2608 }
2609exit:
2610 mutex_unlock(&wcd934x->micb_lock);
2611 return ret;
2612}
2613
2614static int wcd934x_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
2615 int micb_num, bool req_en)
2616{
2617 struct wcd934x_codec *wcd934x = snd_soc_component_get_drvdata(component);
2618 int rc, micb_mv;
2619
2620 if (micb_num != MIC_BIAS_2)
2621 return -EINVAL;
2622 /*
2623 * If device tree micbias level is already above the minimum
2624 * voltage needed to detect threshold microphone, then do
2625 * not change the micbias, just return.
2626 */
2627 if (wcd934x->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
2628 return 0;
2629
2630 micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : wcd934x->micb2_mv;
2631
2632 rc = wcd934x_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
2633
2634 return rc;
2635}
2636
2637static void wcd934x_mbhc_get_result_params(struct wcd934x_codec *wcd934x,
2638 s16 *d1_a, u16 noff,
2639 int32_t *zdet)
2640{
2641 int i;
2642 int val, val1;
2643 s16 c1;
2644 s32 x1, d1;
2645 int32_t denom;
2646 static const int minCode_param[] = {
2647 3277, 1639, 820, 410, 205, 103, 52, 26
2648 };
2649
2650 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x20);
2651 for (i = 0; i < WCD934X_ZDET_NUM_MEASUREMENTS; i++) {
2652 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val);
2653 if (val & 0x80)
2654 break;
2655 }
2656 val = val << 0x8;
2657 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val1);
2658 val |= val1;
2659 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x20, 0x00);
2660 x1 = WCD934X_MBHC_GET_X1(val);
2661 c1 = WCD934X_MBHC_GET_C1(val);
2662 /* If ramp is not complete, give additional 5ms */
2663 if ((c1 < 2) && x1)
2664 usleep_range(5000, 5050);
2665
2666 if (!c1 || !x1) {
2667 dev_err(wcd934x->dev, "%s: Impedance detect ramp error, c1=%d, x1=0x%x\n",
2668 __func__, c1, x1);
2669 goto ramp_down;
2670 }
2671 d1 = d1_a[c1];
2672 denom = (x1 * d1) - (1 << (14 - noff));
2673 if (denom > 0)
2674 *zdet = (WCD934X_MBHC_ZDET_CONST * 1000) / denom;
2675 else if (x1 < minCode_param[noff])
2676 *zdet = WCD934X_ZDET_FLOATING_IMPEDANCE;
2677
2678 dev_dbg(wcd934x->dev, "%s: d1=%d, c1=%d, x1=0x%x, z_val=%di (milliohm)\n",
2679 __func__, d1, c1, x1, *zdet);
2680ramp_down:
2681 i = 0;
2682
2683 while (x1) {
2684 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_1, &val);
2685 regmap_read(wcd934x->regmap, WCD934X_ANA_MBHC_RESULT_2, &val1);
2686 val = val << 0x08;
2687 val |= val1;
2688 x1 = WCD934X_MBHC_GET_X1(val);
2689 i++;
2690 if (i == WCD934X_ZDET_NUM_MEASUREMENTS)
2691 break;
2692 }
2693}
2694
2695static void wcd934x_mbhc_zdet_ramp(struct snd_soc_component *component,
2696 struct wcd934x_mbhc_zdet_param *zdet_param,
2697 int32_t *zl, int32_t *zr, s16 *d1_a)
2698{
2699 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2700 int32_t zdet = 0;
2701
2702 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2703 WCD934X_ZDET_MAXV_CTL_MASK, zdet_param->ldo_ctl);
2704 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN5,
2705 WCD934X_VTH_MASK, zdet_param->btn5);
2706 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN6,
2707 WCD934X_VTH_MASK, zdet_param->btn6);
2708 snd_soc_component_update_bits(component, WCD934X_ANA_MBHC_BTN7,
2709 WCD934X_VTH_MASK, zdet_param->btn7);
2710 snd_soc_component_write_field(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL,
2711 WCD934X_ZDET_RANGE_CTL_MASK, zdet_param->noff);
2712 snd_soc_component_update_bits(component, WCD934X_MBHC_NEW_ZDET_RAMP_CTL,
2713 0x0F, zdet_param->nshift);
2714
2715 if (!zl)
2716 goto z_right;
2717 /* Start impedance measurement for HPH_L */
2718 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x80);
2719 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2720 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x80, 0x00);
2721
2722 *zl = zdet;
2723
2724z_right:
2725 if (!zr)
2726 return;
2727 /* Start impedance measurement for HPH_R */
2728 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x40);
2729 wcd934x_mbhc_get_result_params(wcd934x, d1_a, zdet_param->noff, &zdet);
2730 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ZDET, 0x40, 0x00);
2731
2732 *zr = zdet;
2733}
2734
2735static void wcd934x_wcd_mbhc_qfuse_cal(struct snd_soc_component *component,
2736 int32_t *z_val, int flag_l_r)
2737{
2738 s16 q1;
2739 int q1_cal;
2740
2741 if (*z_val < (WCD934X_ZDET_VAL_400/1000))
2742 q1 = snd_soc_component_read(component,
2743 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1 + (2 * flag_l_r));
2744 else
2745 q1 = snd_soc_component_read(component,
2746 WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2 + (2 * flag_l_r));
2747 if (q1 & 0x80)
2748 q1_cal = (10000 - ((q1 & 0x7F) * 25));
2749 else
2750 q1_cal = (10000 + (q1 * 25));
2751 if (q1_cal > 0)
2752 *z_val = ((*z_val) * 10000) / q1_cal;
2753}
2754
2755static void wcd934x_wcd_mbhc_calc_impedance(struct snd_soc_component *component,
2756 uint32_t *zl, uint32_t *zr)
2757{
2758 struct wcd934x_codec *wcd934x = dev_get_drvdata(component->dev);
2759 s16 reg0, reg1, reg2, reg3, reg4;
2760 int32_t z1L, z1R, z1Ls;
2761 int zMono, z_diff1, z_diff2;
2762 bool is_fsm_disable = false;
2763 struct wcd934x_mbhc_zdet_param zdet_param[] = {
2764 {4, 0, 4, 0x08, 0x14, 0x18}, /* < 32ohm */
2765 {2, 0, 3, 0x18, 0x7C, 0x90}, /* 32ohm < Z < 400ohm */
2766 {1, 4, 5, 0x18, 0x7C, 0x90}, /* 400ohm < Z < 1200ohm */
2767 {1, 6, 7, 0x18, 0x7C, 0x90}, /* >1200ohm */
2768 };
2769 struct wcd934x_mbhc_zdet_param *zdet_param_ptr = NULL;
2770 s16 d1_a[][4] = {
2771 {0, 30, 90, 30},
2772 {0, 30, 30, 5},
2773 {0, 30, 30, 5},
2774 {0, 30, 30, 5},
2775 };
2776 s16 *d1 = NULL;
2777
2778 reg0 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN5);
2779 reg1 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN6);
2780 reg2 = snd_soc_component_read(component, WCD934X_ANA_MBHC_BTN7);
2781 reg3 = snd_soc_component_read(component, WCD934X_MBHC_CTL_CLK);
2782 reg4 = snd_soc_component_read(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL);
2783
2784 if (snd_soc_component_read(component, WCD934X_ANA_MBHC_ELECT) & 0x80) {
2785 is_fsm_disable = true;
2786 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00);
2787 }
2788
2789 /* For NO-jack, disable L_DET_EN before Z-det measurements */
2790 if (wcd934x->mbhc_cfg.hphl_swh)
2791 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x00);
2792
2793 /* Turn off 100k pull down on HPHL */
2794 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x00);
2795
2796 /* First get impedance on Left */
2797 d1 = d1_a[1];
2798 zdet_param_ptr = &zdet_param[1];
2799 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2800
2801 if (!WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1L))
2802 goto left_ch_impedance;
2803
2804 /* Second ramp for left ch */
2805 if (z1L < WCD934X_ZDET_VAL_32) {
2806 zdet_param_ptr = &zdet_param[0];
2807 d1 = d1_a[0];
2808 } else if ((z1L > WCD934X_ZDET_VAL_400) &&
2809 (z1L <= WCD934X_ZDET_VAL_1200)) {
2810 zdet_param_ptr = &zdet_param[2];
2811 d1 = d1_a[2];
2812 } else if (z1L > WCD934X_ZDET_VAL_1200) {
2813 zdet_param_ptr = &zdet_param[3];
2814 d1 = d1_a[3];
2815 }
2816 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, &z1L, NULL, d1);
2817
2818left_ch_impedance:
2819 if ((z1L == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2820 (z1L > WCD934X_ZDET_VAL_100K)) {
2821 *zl = WCD934X_ZDET_FLOATING_IMPEDANCE;
2822 zdet_param_ptr = &zdet_param[1];
2823 d1 = d1_a[1];
2824 } else {
2825 *zl = z1L/1000;
2826 wcd934x_wcd_mbhc_qfuse_cal(component, zl, 0);
2827 }
2828 dev_info(component->dev, "%s: impedance on HPH_L = %d(ohms)\n",
2829 __func__, *zl);
2830
2831 /* Start of right impedance ramp and calculation */
2832 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2833 if (WCD934X_MBHC_IS_SECOND_RAMP_REQUIRED(z1R)) {
2834 if (((z1R > WCD934X_ZDET_VAL_1200) &&
2835 (zdet_param_ptr->noff == 0x6)) ||
2836 ((*zl) != WCD934X_ZDET_FLOATING_IMPEDANCE))
2837 goto right_ch_impedance;
2838 /* Second ramp for right ch */
2839 if (z1R < WCD934X_ZDET_VAL_32) {
2840 zdet_param_ptr = &zdet_param[0];
2841 d1 = d1_a[0];
2842 } else if ((z1R > WCD934X_ZDET_VAL_400) &&
2843 (z1R <= WCD934X_ZDET_VAL_1200)) {
2844 zdet_param_ptr = &zdet_param[2];
2845 d1 = d1_a[2];
2846 } else if (z1R > WCD934X_ZDET_VAL_1200) {
2847 zdet_param_ptr = &zdet_param[3];
2848 d1 = d1_a[3];
2849 }
2850 wcd934x_mbhc_zdet_ramp(component, zdet_param_ptr, NULL, &z1R, d1);
2851 }
2852right_ch_impedance:
2853 if ((z1R == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2854 (z1R > WCD934X_ZDET_VAL_100K)) {
2855 *zr = WCD934X_ZDET_FLOATING_IMPEDANCE;
2856 } else {
2857 *zr = z1R/1000;
2858 wcd934x_wcd_mbhc_qfuse_cal(component, zr, 1);
2859 }
2860 dev_err(component->dev, "%s: impedance on HPH_R = %d(ohms)\n",
2861 __func__, *zr);
2862
2863 /* Mono/stereo detection */
2864 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) &&
2865 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE)) {
2866 dev_dbg(component->dev,
2867 "%s: plug type is invalid or extension cable\n",
2868 __func__);
2869 goto zdet_complete;
2870 }
2871 if ((*zl == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2872 (*zr == WCD934X_ZDET_FLOATING_IMPEDANCE) ||
2873 ((*zl < WCD_MONO_HS_MIN_THR) && (*zr > WCD_MONO_HS_MIN_THR)) ||
2874 ((*zl > WCD_MONO_HS_MIN_THR) && (*zr < WCD_MONO_HS_MIN_THR))) {
2875 dev_dbg(component->dev,
2876 "%s: Mono plug type with one ch floating or shorted to GND\n",
2877 __func__);
2878 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2879 goto zdet_complete;
2880 }
2881 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2882 WCD934X_HPHPA_GND_OVR_MASK, 1);
2883 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2884 WCD934X_HPHPA_GND_R_MASK, 1);
2885 if (*zl < (WCD934X_ZDET_VAL_32/1000))
2886 wcd934x_mbhc_zdet_ramp(component, &zdet_param[0], &z1Ls, NULL, d1);
2887 else
2888 wcd934x_mbhc_zdet_ramp(component, &zdet_param[1], &z1Ls, NULL, d1);
2889 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2890 WCD934X_HPHPA_GND_R_MASK, 0);
2891 snd_soc_component_write_field(component, WCD934X_HPH_R_ATEST,
2892 WCD934X_HPHPA_GND_OVR_MASK, 0);
2893 z1Ls /= 1000;
2894 wcd934x_wcd_mbhc_qfuse_cal(component, &z1Ls, 0);
2895 /* Parallel of left Z and 9 ohm pull down resistor */
2896 zMono = ((*zl) * 9) / ((*zl) + 9);
2897 z_diff1 = (z1Ls > zMono) ? (z1Ls - zMono) : (zMono - z1Ls);
2898 z_diff2 = ((*zl) > z1Ls) ? ((*zl) - z1Ls) : (z1Ls - (*zl));
2899 if ((z_diff1 * (*zl + z1Ls)) > (z_diff2 * (z1Ls + zMono))) {
2900 dev_err(component->dev, "%s: stereo plug type detected\n",
2901 __func__);
2902 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_STEREO);
2903 } else {
2904 dev_err(component->dev, "%s: MONO plug type detected\n",
2905 __func__);
2906 wcd_mbhc_set_hph_type(wcd934x->mbhc, WCD_MBHC_HPH_MONO);
2907 }
2908
2909zdet_complete:
2910 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN5, reg0);
2911 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN6, reg1);
2912 snd_soc_component_write(component, WCD934X_ANA_MBHC_BTN7, reg2);
2913 /* Turn on 100k pull down on HPHL */
2914 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x01, 0x01);
2915
2916 /* For NO-jack, re-enable L_DET_EN after Z-det measurements */
2917 if (wcd934x->mbhc_cfg.hphl_swh)
2918 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_MECH, 0x80, 0x80);
2919
2920 snd_soc_component_write(component, WCD934X_MBHC_NEW_ZDET_ANA_CTL, reg4);
2921 snd_soc_component_write(component, WCD934X_MBHC_CTL_CLK, reg3);
2922 if (is_fsm_disable)
2923 regmap_update_bits(wcd934x->regmap, WCD934X_ANA_MBHC_ELECT, 0x80, 0x80);
2924}
2925
2926static void wcd934x_mbhc_gnd_det_ctrl(struct snd_soc_component *component,
2927 bool enable)
2928{
2929 if (enable) {
2930 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2931 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 1);
2932 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2933 WCD934X_MBHC_GND_DET_EN_MASK, 1);
2934 } else {
2935 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2936 WCD934X_MBHC_GND_DET_EN_MASK, 0);
2937 snd_soc_component_write_field(component, WCD934X_ANA_MBHC_MECH,
2938 WCD934X_MBHC_HSG_PULLUP_COMP_EN, 0);
2939 }
2940}
2941
2942static void wcd934x_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component,
2943 bool enable)
2944{
2945 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2946 WCD934X_HPHPA_GND_R_MASK, enable);
2947 snd_soc_component_write_field(component, WCD934X_HPH_PA_CTL2,
2948 WCD934X_HPHPA_GND_L_MASK, enable);
2949}
2950
2951static const struct wcd_mbhc_cb mbhc_cb = {
2952 .clk_setup = wcd934x_mbhc_clk_setup,
2953 .mbhc_bias = wcd934x_mbhc_mbhc_bias_control,
2954 .set_btn_thr = wcd934x_mbhc_program_btn_thr,
2955 .micbias_enable_status = wcd934x_mbhc_micb_en_status,
2956 .hph_pull_up_control = wcd934x_mbhc_hph_l_pull_up_control,
2957 .mbhc_micbias_control = wcd934x_mbhc_request_micbias,
2958 .mbhc_micb_ramp_control = wcd934x_mbhc_micb_ramp_control,
2959 .mbhc_micb_ctrl_thr_mic = wcd934x_mbhc_micb_ctrl_threshold_mic,
2960 .compute_impedance = wcd934x_wcd_mbhc_calc_impedance,
2961 .mbhc_gnd_det_ctrl = wcd934x_mbhc_gnd_det_ctrl,
2962 .hph_pull_down_ctrl = wcd934x_mbhc_hph_pull_down_ctrl,
2963};
2964
2965static int wcd934x_get_hph_type(struct snd_kcontrol *kcontrol,
2966 struct snd_ctl_elem_value *ucontrol)
2967{
2968 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2969 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2970
2971 ucontrol->value.integer.value[0] = wcd_mbhc_get_hph_type(wcd->mbhc);
2972
2973 return 0;
2974}
2975
2976static int wcd934x_hph_impedance_get(struct snd_kcontrol *kcontrol,
2977 struct snd_ctl_elem_value *ucontrol)
2978{
2979 uint32_t zl, zr;
2980 bool hphr;
2981 struct soc_mixer_control *mc;
2982 struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2983 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
2984
2985 mc = (struct soc_mixer_control *)(kcontrol->private_value);
2986 hphr = mc->shift;
2987 wcd_mbhc_get_impedance(wcd->mbhc, &zl, &zr);
2988 dev_dbg(component->dev, "%s: zl=%u(ohms), zr=%u(ohms)\n", __func__, zl, zr);
2989 ucontrol->value.integer.value[0] = hphr ? zr : zl;
2990
2991 return 0;
2992}
2993static const struct snd_kcontrol_new hph_type_detect_controls[] = {
2994 SOC_SINGLE_EXT("HPH Type", 0, 0, WCD_MBHC_HPH_STEREO, 0,
2995 wcd934x_get_hph_type, NULL),
2996};
2997
2998static const struct snd_kcontrol_new impedance_detect_controls[] = {
2999 SOC_SINGLE_EXT("HPHL Impedance", 0, 0, INT_MAX, 0,
3000 wcd934x_hph_impedance_get, NULL),
3001 SOC_SINGLE_EXT("HPHR Impedance", 0, 1, INT_MAX, 0,
3002 wcd934x_hph_impedance_get, NULL),
3003};
3004
3005static int wcd934x_mbhc_init(struct snd_soc_component *component)
3006{
3007 struct wcd934x_ddata *data = dev_get_drvdata(component->dev->parent);
3008 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3009 struct wcd_mbhc_intr *intr_ids = &wcd->intr_ids;
3010
3011 intr_ids->mbhc_sw_intr = regmap_irq_get_virq(data->irq_data,
3012 WCD934X_IRQ_MBHC_SW_DET);
3013 intr_ids->mbhc_btn_press_intr = regmap_irq_get_virq(data->irq_data,
3014 WCD934X_IRQ_MBHC_BUTTON_PRESS_DET);
3015 intr_ids->mbhc_btn_release_intr = regmap_irq_get_virq(data->irq_data,
3016 WCD934X_IRQ_MBHC_BUTTON_RELEASE_DET);
3017 intr_ids->mbhc_hs_ins_intr = regmap_irq_get_virq(data->irq_data,
3018 WCD934X_IRQ_MBHC_ELECT_INS_REM_LEG_DET);
3019 intr_ids->mbhc_hs_rem_intr = regmap_irq_get_virq(data->irq_data,
3020 WCD934X_IRQ_MBHC_ELECT_INS_REM_DET);
3021 intr_ids->hph_left_ocp = regmap_irq_get_virq(data->irq_data,
3022 WCD934X_IRQ_HPH_PA_OCPL_FAULT);
3023 intr_ids->hph_right_ocp = regmap_irq_get_virq(data->irq_data,
3024 WCD934X_IRQ_HPH_PA_OCPR_FAULT);
3025
3026 wcd->mbhc = wcd_mbhc_init(component, &mbhc_cb, intr_ids, wcd_mbhc_fields, true);
3027 if (IS_ERR(wcd->mbhc)) {
3028 wcd->mbhc = NULL;
3029 return -EINVAL;
3030 }
3031
3032 snd_soc_add_component_controls(component, impedance_detect_controls,
3033 ARRAY_SIZE(impedance_detect_controls));
3034 snd_soc_add_component_controls(component, hph_type_detect_controls,
3035 ARRAY_SIZE(hph_type_detect_controls));
3036
3037 return 0;
3038}
3039
3040static void wcd934x_mbhc_deinit(struct snd_soc_component *component)
3041{
3042 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(component);
3043
3044 if (!wcd->mbhc)
3045 return;
3046
3047 wcd_mbhc_deinit(wcd->mbhc);
3048}
3049
3050static int wcd934x_comp_probe(struct snd_soc_component *component)
3051{
3052 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3053 int i;
3054
3055 snd_soc_component_init_regmap(component, wcd->regmap);
3056 wcd->component = component;
3057
3058 /* Class-H Init*/
3059 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, wcd->version);
3060 if (IS_ERR(wcd->clsh_ctrl))
3061 return PTR_ERR(wcd->clsh_ctrl);
3062
3063 /* Default HPH Mode to Class-H Low HiFi */
3064 wcd->hph_mode = CLS_H_LOHIFI;
3065
3066 wcd934x_comp_init(component);
3067
3068 for (i = 0; i < NUM_CODEC_DAIS; i++)
3069 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
3070
3071 wcd934x_init_dmic(component);
3072
3073 if (wcd934x_mbhc_init(component))
3074 dev_err(component->dev, "Failed to Initialize MBHC\n");
3075
3076 return 0;
3077}
3078
3079static void wcd934x_comp_remove(struct snd_soc_component *comp)
3080{
3081 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3082
3083 wcd934x_mbhc_deinit(comp);
3084 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
3085}
3086
3087static int wcd934x_comp_set_sysclk(struct snd_soc_component *comp,
3088 int clk_id, int source,
3089 unsigned int freq, int dir)
3090{
3091 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
3092 int val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ;
3093
3094 wcd->rate = freq;
3095
3096 if (wcd->rate == WCD934X_MCLK_CLK_12P288MHZ)
3097 val = WCD934X_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ;
3098
3099 snd_soc_component_update_bits(comp, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
3100 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
3101 val);
3102
3103 return clk_set_rate(wcd->extclk, freq);
3104}
3105
3106static uint32_t get_iir_band_coeff(struct snd_soc_component *component,
3107 int iir_idx, int band_idx, int coeff_idx)
3108{
3109 u32 value = 0;
3110 int reg, b2_reg;
3111
3112 /* Address does not automatically update if reading */
3113 reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3114 b2_reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3115
3116 snd_soc_component_write(component, reg,
3117 ((band_idx * BAND_MAX + coeff_idx) *
3118 sizeof(uint32_t)) & 0x7F);
3119
3120 value |= snd_soc_component_read(component, b2_reg);
3121 snd_soc_component_write(component, reg,
3122 ((band_idx * BAND_MAX + coeff_idx)
3123 * sizeof(uint32_t) + 1) & 0x7F);
3124
3125 value |= (snd_soc_component_read(component, b2_reg) << 8);
3126 snd_soc_component_write(component, reg,
3127 ((band_idx * BAND_MAX + coeff_idx)
3128 * sizeof(uint32_t) + 2) & 0x7F);
3129
3130 value |= (snd_soc_component_read(component, b2_reg) << 16);
3131 snd_soc_component_write(component, reg,
3132 ((band_idx * BAND_MAX + coeff_idx)
3133 * sizeof(uint32_t) + 3) & 0x7F);
3134
3135 /* Mask bits top 2 bits since they are reserved */
3136 value |= (snd_soc_component_read(component, b2_reg) << 24);
3137 return value;
3138}
3139
3140static void set_iir_band_coeff(struct snd_soc_component *component,
3141 int iir_idx, int band_idx, uint32_t value)
3142{
3143 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL + 16 * iir_idx;
3144
3145 snd_soc_component_write(component, reg, (value & 0xFF));
3146 snd_soc_component_write(component, reg, (value >> 8) & 0xFF);
3147 snd_soc_component_write(component, reg, (value >> 16) & 0xFF);
3148 /* Mask top 2 bits, 7-8 are reserved */
3149 snd_soc_component_write(component, reg, (value >> 24) & 0x3F);
3150}
3151
3152static int wcd934x_put_iir_band_audio_mixer(
3153 struct snd_kcontrol *kcontrol,
3154 struct snd_ctl_elem_value *ucontrol)
3155{
3156 struct snd_soc_component *component =
3157 snd_soc_kcontrol_component(kcontrol);
3158 struct wcd_iir_filter_ctl *ctl =
3159 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3160 struct soc_bytes_ext *params = &ctl->bytes_ext;
3161 int iir_idx = ctl->iir_idx;
3162 int band_idx = ctl->band_idx;
3163 u32 coeff[BAND_MAX];
3164 int reg = WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL + 16 * iir_idx;
3165
3166 memcpy(&coeff[0], ucontrol->value.bytes.data, params->max);
3167
3168 /* Mask top bit it is reserved */
3169 /* Updates addr automatically for each B2 write */
3170 snd_soc_component_write(component, reg, (band_idx * BAND_MAX *
3171 sizeof(uint32_t)) & 0x7F);
3172
3173 set_iir_band_coeff(component, iir_idx, band_idx, coeff[0]);
3174 set_iir_band_coeff(component, iir_idx, band_idx, coeff[1]);
3175 set_iir_band_coeff(component, iir_idx, band_idx, coeff[2]);
3176 set_iir_band_coeff(component, iir_idx, band_idx, coeff[3]);
3177 set_iir_band_coeff(component, iir_idx, band_idx, coeff[4]);
3178
3179 return 0;
3180}
3181
3182static int wcd934x_get_iir_band_audio_mixer(struct snd_kcontrol *kcontrol,
3183 struct snd_ctl_elem_value *ucontrol)
3184{
3185 struct snd_soc_component *component =
3186 snd_soc_kcontrol_component(kcontrol);
3187 struct wcd_iir_filter_ctl *ctl =
3188 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3189 struct soc_bytes_ext *params = &ctl->bytes_ext;
3190 int iir_idx = ctl->iir_idx;
3191 int band_idx = ctl->band_idx;
3192 u32 coeff[BAND_MAX];
3193
3194 coeff[0] = get_iir_band_coeff(component, iir_idx, band_idx, 0);
3195 coeff[1] = get_iir_band_coeff(component, iir_idx, band_idx, 1);
3196 coeff[2] = get_iir_band_coeff(component, iir_idx, band_idx, 2);
3197 coeff[3] = get_iir_band_coeff(component, iir_idx, band_idx, 3);
3198 coeff[4] = get_iir_band_coeff(component, iir_idx, band_idx, 4);
3199
3200 memcpy(ucontrol->value.bytes.data, &coeff[0], params->max);
3201
3202 return 0;
3203}
3204
3205static int wcd934x_iir_filter_info(struct snd_kcontrol *kcontrol,
3206 struct snd_ctl_elem_info *ucontrol)
3207{
3208 struct wcd_iir_filter_ctl *ctl =
3209 (struct wcd_iir_filter_ctl *)kcontrol->private_value;
3210 struct soc_bytes_ext *params = &ctl->bytes_ext;
3211
3212 ucontrol->type = SNDRV_CTL_ELEM_TYPE_BYTES;
3213 ucontrol->count = params->max;
3214
3215 return 0;
3216}
3217
3218static int wcd934x_compander_get(struct snd_kcontrol *kc,
3219 struct snd_ctl_elem_value *ucontrol)
3220{
3221 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3222 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3223 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3224
3225 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
3226
3227 return 0;
3228}
3229
3230static int wcd934x_compander_set(struct snd_kcontrol *kc,
3231 struct snd_ctl_elem_value *ucontrol)
3232{
3233 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3234 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3235 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
3236 int value = ucontrol->value.integer.value[0];
3237 int sel;
3238
3239 if (wcd->comp_enabled[comp] == value)
3240 return 0;
3241
3242 wcd->comp_enabled[comp] = value;
3243 sel = value ? WCD934X_HPH_GAIN_SRC_SEL_COMPANDER :
3244 WCD934X_HPH_GAIN_SRC_SEL_REGISTER;
3245
3246 /* Any specific register configuration for compander */
3247 switch (comp) {
3248 case COMPANDER_1:
3249 /* Set Gain Source Select based on compander enable/disable */
3250 snd_soc_component_update_bits(component, WCD934X_HPH_L_EN,
3251 WCD934X_HPH_GAIN_SRC_SEL_MASK,
3252 sel);
3253 break;
3254 case COMPANDER_2:
3255 snd_soc_component_update_bits(component, WCD934X_HPH_R_EN,
3256 WCD934X_HPH_GAIN_SRC_SEL_MASK,
3257 sel);
3258 break;
3259 case COMPANDER_3:
3260 case COMPANDER_4:
3261 case COMPANDER_7:
3262 case COMPANDER_8:
3263 break;
3264 default:
3265 return 0;
3266 }
3267
3268 return 1;
3269}
3270
3271static int wcd934x_rx_hph_mode_get(struct snd_kcontrol *kc,
3272 struct snd_ctl_elem_value *ucontrol)
3273{
3274 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3275 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3276
3277 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
3278
3279 return 0;
3280}
3281
3282static int wcd934x_rx_hph_mode_put(struct snd_kcontrol *kc,
3283 struct snd_ctl_elem_value *ucontrol)
3284{
3285 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
3286 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
3287 u32 mode_val;
3288
3289 mode_val = ucontrol->value.enumerated.item[0];
3290
3291 if (mode_val == wcd->hph_mode)
3292 return 0;
3293
3294 if (mode_val == 0) {
3295 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
3296 mode_val = CLS_H_LOHIFI;
3297 }
3298 wcd->hph_mode = mode_val;
3299
3300 return 1;
3301}
3302
3303static int slim_rx_mux_get(struct snd_kcontrol *kc,
3304 struct snd_ctl_elem_value *ucontrol)
3305{
3306 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3307 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3308 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3309
3310 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[w->shift];
3311
3312 return 0;
3313}
3314
3315static int slim_rx_mux_to_dai_id(int mux)
3316{
3317 int aif_id;
3318
3319 switch (mux) {
3320 case 1:
3321 aif_id = AIF1_PB;
3322 break;
3323 case 2:
3324 aif_id = AIF2_PB;
3325 break;
3326 case 3:
3327 aif_id = AIF3_PB;
3328 break;
3329 case 4:
3330 aif_id = AIF4_PB;
3331 break;
3332 default:
3333 aif_id = -1;
3334 break;
3335 }
3336
3337 return aif_id;
3338}
3339
3340static int slim_rx_mux_put(struct snd_kcontrol *kc,
3341 struct snd_ctl_elem_value *ucontrol)
3342{
3343 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
3344 struct wcd934x_codec *wcd = dev_get_drvdata(w->dapm->dev);
3345 struct soc_enum *e = (struct soc_enum *)kc->private_value;
3346 struct snd_soc_dapm_update *update = NULL;
3347 struct wcd934x_slim_ch *ch, *c;
3348 u32 port_id = w->shift;
3349 bool found = false;
3350 int mux_idx;
3351 int prev_mux_idx = wcd->rx_port_value[port_id];
3352 int aif_id;
3353
3354 mux_idx = ucontrol->value.enumerated.item[0];
3355
3356 if (mux_idx == prev_mux_idx)
3357 return 0;
3358
3359 switch(mux_idx) {
3360 case 0:
3361 aif_id = slim_rx_mux_to_dai_id(prev_mux_idx);
3362 if (aif_id < 0)
3363 return 0;
3364
3365 list_for_each_entry_safe(ch, c, &wcd->dai[aif_id].slim_ch_list, list) {
3366 if (ch->port == port_id + WCD934X_RX_START) {
3367 found = true;
3368 list_del_init(&ch->list);
3369 break;
3370 }
3371 }
3372 if (!found)
3373 return 0;
3374
3375 break;
3376 case 1 ... 4:
3377 aif_id = slim_rx_mux_to_dai_id(mux_idx);
3378 if (aif_id < 0)
3379 return 0;
3380
3381 if (list_empty(&wcd->rx_chs[port_id].list)) {
3382 list_add_tail(&wcd->rx_chs[port_id].list,
3383 &wcd->dai[aif_id].slim_ch_list);
3384 } else {
3385 dev_err(wcd->dev ,"SLIM_RX%d PORT is busy\n", port_id);
3386 return 0;
3387 }
3388 break;
3389
3390 default:
3391 dev_err(wcd->dev, "Unknown AIF %d\n", mux_idx);
3392 goto err;
3393 }
3394
3395 wcd->rx_port_value[port_id] = mux_idx;
3396 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
3397 e, update);
3398
3399 return 1;
3400err:
3401 return -EINVAL;
3402}
3403
3404static int wcd934x_int_dem_inp_mux_put(struct snd_kcontrol *kc,
3405 struct snd_ctl_elem_value *ucontrol)
3406{
3407 struct soc_enum *e = (struct soc_enum *)kc->private_value;
3408 struct snd_soc_component *component;
3409 int reg, val;
3410
3411 component = snd_soc_dapm_kcontrol_component(kc);
3412 val = ucontrol->value.enumerated.item[0];
3413 if (e->reg == WCD934X_CDC_RX0_RX_PATH_SEC0)
3414 reg = WCD934X_CDC_RX0_RX_PATH_CFG0;
3415 else if (e->reg == WCD934X_CDC_RX1_RX_PATH_SEC0)
3416 reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
3417 else if (e->reg == WCD934X_CDC_RX2_RX_PATH_SEC0)
3418 reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
3419 else
3420 return -EINVAL;
3421
3422 /* Set Look Ahead Delay */
3423 if (val)
3424 snd_soc_component_update_bits(component, reg,
3425 WCD934X_RX_DLY_ZN_EN_MASK,
3426 WCD934X_RX_DLY_ZN_ENABLE);
3427 else
3428 snd_soc_component_update_bits(component, reg,
3429 WCD934X_RX_DLY_ZN_EN_MASK,
3430 WCD934X_RX_DLY_ZN_DISABLE);
3431
3432 return snd_soc_dapm_put_enum_double(kc, ucontrol);
3433}
3434
3435static int wcd934x_dec_enum_put(struct snd_kcontrol *kcontrol,
3436 struct snd_ctl_elem_value *ucontrol)
3437{
3438 struct snd_soc_component *comp;
3439 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
3440 unsigned int val;
3441 u16 mic_sel_reg = 0;
3442 u8 mic_sel;
3443
3444 comp = snd_soc_dapm_kcontrol_component(kcontrol);
3445
3446 val = ucontrol->value.enumerated.item[0];
3447 if (val > e->items - 1)
3448 return -EINVAL;
3449
3450 switch (e->reg) {
3451 case WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
3452 if (e->shift_l == 0)
3453 mic_sel_reg = WCD934X_CDC_TX0_TX_PATH_CFG0;
3454 else if (e->shift_l == 2)
3455 mic_sel_reg = WCD934X_CDC_TX4_TX_PATH_CFG0;
3456 else if (e->shift_l == 4)
3457 mic_sel_reg = WCD934X_CDC_TX8_TX_PATH_CFG0;
3458 break;
3459 case WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
3460 if (e->shift_l == 0)
3461 mic_sel_reg = WCD934X_CDC_TX1_TX_PATH_CFG0;
3462 else if (e->shift_l == 2)
3463 mic_sel_reg = WCD934X_CDC_TX5_TX_PATH_CFG0;
3464 break;
3465 case WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
3466 if (e->shift_l == 0)
3467 mic_sel_reg = WCD934X_CDC_TX2_TX_PATH_CFG0;
3468 else if (e->shift_l == 2)
3469 mic_sel_reg = WCD934X_CDC_TX6_TX_PATH_CFG0;
3470 break;
3471 case WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
3472 if (e->shift_l == 0)
3473 mic_sel_reg = WCD934X_CDC_TX3_TX_PATH_CFG0;
3474 else if (e->shift_l == 2)
3475 mic_sel_reg = WCD934X_CDC_TX7_TX_PATH_CFG0;
3476 break;
3477 default:
3478 dev_err(comp->dev, "%s: e->reg: 0x%x not expected\n",
3479 __func__, e->reg);
3480 return -EINVAL;
3481 }
3482
3483 /* ADC: 0, DMIC: 1 */
3484 mic_sel = val ? 0x0 : 0x1;
3485 if (mic_sel_reg)
3486 snd_soc_component_update_bits(comp, mic_sel_reg, BIT(7),
3487 mic_sel << 7);
3488
3489 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
3490}
3491
3492static const struct snd_kcontrol_new rx_int0_2_mux =
3493 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
3494
3495static const struct snd_kcontrol_new rx_int1_2_mux =
3496 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
3497
3498static const struct snd_kcontrol_new rx_int2_2_mux =
3499 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
3500
3501static const struct snd_kcontrol_new rx_int3_2_mux =
3502 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
3503
3504static const struct snd_kcontrol_new rx_int4_2_mux =
3505 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
3506
3507static const struct snd_kcontrol_new rx_int7_2_mux =
3508 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
3509
3510static const struct snd_kcontrol_new rx_int8_2_mux =
3511 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
3512
3513static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
3514 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
3515
3516static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
3517 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
3518
3519static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
3520 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
3521
3522static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
3523 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
3524
3525static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
3526 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
3527
3528static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
3529 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
3530
3531static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
3532 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
3533
3534static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
3535 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
3536
3537static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
3538 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
3539
3540static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
3541 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
3542
3543static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
3544 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
3545
3546static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
3547 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
3548
3549static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
3550 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
3551
3552static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
3553 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
3554
3555static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
3556 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
3557
3558static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
3559 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
3560
3561static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
3562 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
3563
3564static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
3565 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
3566
3567static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
3568 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
3569
3570static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
3571 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
3572
3573static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
3574 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
3575
3576static const struct snd_kcontrol_new rx_int0_mix2_inp_mux =
3577 SOC_DAPM_ENUM("RX INT0 MIX2 INP Mux", rx_int0_mix2_inp_mux_enum);
3578
3579static const struct snd_kcontrol_new rx_int1_mix2_inp_mux =
3580 SOC_DAPM_ENUM("RX INT1 MIX2 INP Mux", rx_int1_mix2_inp_mux_enum);
3581
3582static const struct snd_kcontrol_new rx_int2_mix2_inp_mux =
3583 SOC_DAPM_ENUM("RX INT2 MIX2 INP Mux", rx_int2_mix2_inp_mux_enum);
3584
3585static const struct snd_kcontrol_new rx_int3_mix2_inp_mux =
3586 SOC_DAPM_ENUM("RX INT3 MIX2 INP Mux", rx_int3_mix2_inp_mux_enum);
3587
3588static const struct snd_kcontrol_new rx_int4_mix2_inp_mux =
3589 SOC_DAPM_ENUM("RX INT4 MIX2 INP Mux", rx_int4_mix2_inp_mux_enum);
3590
3591static const struct snd_kcontrol_new rx_int7_mix2_inp_mux =
3592 SOC_DAPM_ENUM("RX INT7 MIX2 INP Mux", rx_int7_mix2_inp_mux_enum);
3593
3594static const struct snd_kcontrol_new iir0_inp0_mux =
3595 SOC_DAPM_ENUM("IIR0 INP0 Mux", iir0_inp0_mux_enum);
3596static const struct snd_kcontrol_new iir0_inp1_mux =
3597 SOC_DAPM_ENUM("IIR0 INP1 Mux", iir0_inp1_mux_enum);
3598static const struct snd_kcontrol_new iir0_inp2_mux =
3599 SOC_DAPM_ENUM("IIR0 INP2 Mux", iir0_inp2_mux_enum);
3600static const struct snd_kcontrol_new iir0_inp3_mux =
3601 SOC_DAPM_ENUM("IIR0 INP3 Mux", iir0_inp3_mux_enum);
3602
3603static const struct snd_kcontrol_new iir1_inp0_mux =
3604 SOC_DAPM_ENUM("IIR1 INP0 Mux", iir1_inp0_mux_enum);
3605static const struct snd_kcontrol_new iir1_inp1_mux =
3606 SOC_DAPM_ENUM("IIR1 INP1 Mux", iir1_inp1_mux_enum);
3607static const struct snd_kcontrol_new iir1_inp2_mux =
3608 SOC_DAPM_ENUM("IIR1 INP2 Mux", iir1_inp2_mux_enum);
3609static const struct snd_kcontrol_new iir1_inp3_mux =
3610 SOC_DAPM_ENUM("IIR1 INP3 Mux", iir1_inp3_mux_enum);
3611
3612static const struct snd_kcontrol_new slim_rx_mux[WCD934X_RX_MAX] = {
3613 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
3614 slim_rx_mux_get, slim_rx_mux_put),
3615 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
3616 slim_rx_mux_get, slim_rx_mux_put),
3617 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
3618 slim_rx_mux_get, slim_rx_mux_put),
3619 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
3620 slim_rx_mux_get, slim_rx_mux_put),
3621 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
3622 slim_rx_mux_get, slim_rx_mux_put),
3623 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
3624 slim_rx_mux_get, slim_rx_mux_put),
3625 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
3626 slim_rx_mux_get, slim_rx_mux_put),
3627 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
3628 slim_rx_mux_get, slim_rx_mux_put),
3629};
3630
3631static const struct snd_kcontrol_new rx_int1_asrc_switch[] = {
3632 SOC_DAPM_SINGLE("HPHL Switch", SND_SOC_NOPM, 0, 1, 0),
3633};
3634
3635static const struct snd_kcontrol_new rx_int2_asrc_switch[] = {
3636 SOC_DAPM_SINGLE("HPHR Switch", SND_SOC_NOPM, 0, 1, 0),
3637};
3638
3639static const struct snd_kcontrol_new rx_int3_asrc_switch[] = {
3640 SOC_DAPM_SINGLE("LO1 Switch", SND_SOC_NOPM, 0, 1, 0),
3641};
3642
3643static const struct snd_kcontrol_new rx_int4_asrc_switch[] = {
3644 SOC_DAPM_SINGLE("LO2 Switch", SND_SOC_NOPM, 0, 1, 0),
3645};
3646
3647static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
3648 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
3649 snd_soc_dapm_get_enum_double,
3650 wcd934x_int_dem_inp_mux_put);
3651
3652static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
3653 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
3654 snd_soc_dapm_get_enum_double,
3655 wcd934x_int_dem_inp_mux_put);
3656
3657static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
3658 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
3659 snd_soc_dapm_get_enum_double,
3660 wcd934x_int_dem_inp_mux_put);
3661
3662static const struct snd_kcontrol_new rx_int0_1_interp_mux =
3663 SOC_DAPM_ENUM("RX INT0_1 INTERP Mux", rx_int0_1_interp_mux_enum);
3664
3665static const struct snd_kcontrol_new rx_int1_1_interp_mux =
3666 SOC_DAPM_ENUM("RX INT1_1 INTERP Mux", rx_int1_1_interp_mux_enum);
3667
3668static const struct snd_kcontrol_new rx_int2_1_interp_mux =
3669 SOC_DAPM_ENUM("RX INT2_1 INTERP Mux", rx_int2_1_interp_mux_enum);
3670
3671static const struct snd_kcontrol_new rx_int3_1_interp_mux =
3672 SOC_DAPM_ENUM("RX INT3_1 INTERP Mux", rx_int3_1_interp_mux_enum);
3673
3674static const struct snd_kcontrol_new rx_int4_1_interp_mux =
3675 SOC_DAPM_ENUM("RX INT4_1 INTERP Mux", rx_int4_1_interp_mux_enum);
3676
3677static const struct snd_kcontrol_new rx_int7_1_interp_mux =
3678 SOC_DAPM_ENUM("RX INT7_1 INTERP Mux", rx_int7_1_interp_mux_enum);
3679
3680static const struct snd_kcontrol_new rx_int8_1_interp_mux =
3681 SOC_DAPM_ENUM("RX INT8_1 INTERP Mux", rx_int8_1_interp_mux_enum);
3682
3683static const struct snd_kcontrol_new rx_int0_2_interp_mux =
3684 SOC_DAPM_ENUM("RX INT0_2 INTERP Mux", rx_int0_2_interp_mux_enum);
3685
3686static const struct snd_kcontrol_new rx_int1_2_interp_mux =
3687 SOC_DAPM_ENUM("RX INT1_2 INTERP Mux", rx_int1_2_interp_mux_enum);
3688
3689static const struct snd_kcontrol_new rx_int2_2_interp_mux =
3690 SOC_DAPM_ENUM("RX INT2_2 INTERP Mux", rx_int2_2_interp_mux_enum);
3691
3692static const struct snd_kcontrol_new rx_int3_2_interp_mux =
3693 SOC_DAPM_ENUM("RX INT3_2 INTERP Mux", rx_int3_2_interp_mux_enum);
3694
3695static const struct snd_kcontrol_new rx_int4_2_interp_mux =
3696 SOC_DAPM_ENUM("RX INT4_2 INTERP Mux", rx_int4_2_interp_mux_enum);
3697
3698static const struct snd_kcontrol_new rx_int7_2_interp_mux =
3699 SOC_DAPM_ENUM("RX INT7_2 INTERP Mux", rx_int7_2_interp_mux_enum);
3700
3701static const struct snd_kcontrol_new rx_int8_2_interp_mux =
3702 SOC_DAPM_ENUM("RX INT8_2 INTERP Mux", rx_int8_2_interp_mux_enum);
3703
3704static const struct snd_kcontrol_new tx_dmic_mux0 =
3705 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
3706
3707static const struct snd_kcontrol_new tx_dmic_mux1 =
3708 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
3709
3710static const struct snd_kcontrol_new tx_dmic_mux2 =
3711 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
3712
3713static const struct snd_kcontrol_new tx_dmic_mux3 =
3714 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
3715
3716static const struct snd_kcontrol_new tx_dmic_mux4 =
3717 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
3718
3719static const struct snd_kcontrol_new tx_dmic_mux5 =
3720 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
3721
3722static const struct snd_kcontrol_new tx_dmic_mux6 =
3723 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
3724
3725static const struct snd_kcontrol_new tx_dmic_mux7 =
3726 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
3727
3728static const struct snd_kcontrol_new tx_dmic_mux8 =
3729 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
3730
3731static const struct snd_kcontrol_new tx_amic_mux0 =
3732 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
3733
3734static const struct snd_kcontrol_new tx_amic_mux1 =
3735 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
3736
3737static const struct snd_kcontrol_new tx_amic_mux2 =
3738 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
3739
3740static const struct snd_kcontrol_new tx_amic_mux3 =
3741 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
3742
3743static const struct snd_kcontrol_new tx_amic_mux4 =
3744 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
3745
3746static const struct snd_kcontrol_new tx_amic_mux5 =
3747 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
3748
3749static const struct snd_kcontrol_new tx_amic_mux6 =
3750 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
3751
3752static const struct snd_kcontrol_new tx_amic_mux7 =
3753 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
3754
3755static const struct snd_kcontrol_new tx_amic_mux8 =
3756 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
3757
3758static const struct snd_kcontrol_new tx_amic4_5 =
3759 SOC_DAPM_ENUM("AMIC4_5 SEL Mux", tx_amic4_5_enum);
3760
3761static const struct snd_kcontrol_new tx_adc_mux0_mux =
3762 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_enum,
3763 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3764static const struct snd_kcontrol_new tx_adc_mux1_mux =
3765 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_enum,
3766 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3767static const struct snd_kcontrol_new tx_adc_mux2_mux =
3768 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_enum,
3769 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3770static const struct snd_kcontrol_new tx_adc_mux3_mux =
3771 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_enum,
3772 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3773static const struct snd_kcontrol_new tx_adc_mux4_mux =
3774 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_enum,
3775 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3776static const struct snd_kcontrol_new tx_adc_mux5_mux =
3777 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_enum,
3778 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3779static const struct snd_kcontrol_new tx_adc_mux6_mux =
3780 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_enum,
3781 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3782static const struct snd_kcontrol_new tx_adc_mux7_mux =
3783 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_enum,
3784 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3785static const struct snd_kcontrol_new tx_adc_mux8_mux =
3786 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_enum,
3787 snd_soc_dapm_get_enum_double, wcd934x_dec_enum_put);
3788
3789static const struct snd_kcontrol_new cdc_if_tx0_mux =
3790 SOC_DAPM_ENUM("CDC_IF TX0 MUX Mux", cdc_if_tx0_mux_enum);
3791static const struct snd_kcontrol_new cdc_if_tx1_mux =
3792 SOC_DAPM_ENUM("CDC_IF TX1 MUX Mux", cdc_if_tx1_mux_enum);
3793static const struct snd_kcontrol_new cdc_if_tx2_mux =
3794 SOC_DAPM_ENUM("CDC_IF TX2 MUX Mux", cdc_if_tx2_mux_enum);
3795static const struct snd_kcontrol_new cdc_if_tx3_mux =
3796 SOC_DAPM_ENUM("CDC_IF TX3 MUX Mux", cdc_if_tx3_mux_enum);
3797static const struct snd_kcontrol_new cdc_if_tx4_mux =
3798 SOC_DAPM_ENUM("CDC_IF TX4 MUX Mux", cdc_if_tx4_mux_enum);
3799static const struct snd_kcontrol_new cdc_if_tx5_mux =
3800 SOC_DAPM_ENUM("CDC_IF TX5 MUX Mux", cdc_if_tx5_mux_enum);
3801static const struct snd_kcontrol_new cdc_if_tx6_mux =
3802 SOC_DAPM_ENUM("CDC_IF TX6 MUX Mux", cdc_if_tx6_mux_enum);
3803static const struct snd_kcontrol_new cdc_if_tx7_mux =
3804 SOC_DAPM_ENUM("CDC_IF TX7 MUX Mux", cdc_if_tx7_mux_enum);
3805static const struct snd_kcontrol_new cdc_if_tx8_mux =
3806 SOC_DAPM_ENUM("CDC_IF TX8 MUX Mux", cdc_if_tx8_mux_enum);
3807static const struct snd_kcontrol_new cdc_if_tx9_mux =
3808 SOC_DAPM_ENUM("CDC_IF TX9 MUX Mux", cdc_if_tx9_mux_enum);
3809static const struct snd_kcontrol_new cdc_if_tx10_mux =
3810 SOC_DAPM_ENUM("CDC_IF TX10 MUX Mux", cdc_if_tx10_mux_enum);
3811static const struct snd_kcontrol_new cdc_if_tx11_mux =
3812 SOC_DAPM_ENUM("CDC_IF TX11 MUX Mux", cdc_if_tx11_mux_enum);
3813static const struct snd_kcontrol_new cdc_if_tx11_inp1_mux =
3814 SOC_DAPM_ENUM("CDC_IF TX11 INP1 MUX Mux", cdc_if_tx11_inp1_mux_enum);
3815static const struct snd_kcontrol_new cdc_if_tx13_mux =
3816 SOC_DAPM_ENUM("CDC_IF TX13 MUX Mux", cdc_if_tx13_mux_enum);
3817static const struct snd_kcontrol_new cdc_if_tx13_inp1_mux =
3818 SOC_DAPM_ENUM("CDC_IF TX13 INP1 MUX Mux", cdc_if_tx13_inp1_mux_enum);
3819
3820static int slim_tx_mixer_get(struct snd_kcontrol *kc,
3821 struct snd_ctl_elem_value *ucontrol)
3822{
3823 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
3824 struct wcd934x_codec *wcd = dev_get_drvdata(dapm->dev);
3825 struct soc_mixer_control *mixer =
3826 (struct soc_mixer_control *)kc->private_value;
3827 int port_id = mixer->shift;
3828
3829 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id];
3830
3831 return 0;
3832}
3833
3834static int slim_tx_mixer_put(struct snd_kcontrol *kc,
3835 struct snd_ctl_elem_value *ucontrol)
3836{
3837 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
3838 struct wcd934x_codec *wcd = dev_get_drvdata(widget->dapm->dev);
3839 struct snd_soc_dapm_update *update = NULL;
3840 struct soc_mixer_control *mixer =
3841 (struct soc_mixer_control *)kc->private_value;
3842 int enable = ucontrol->value.integer.value[0];
3843 struct wcd934x_slim_ch *ch, *c;
3844 int dai_id = widget->shift;
3845 int port_id = mixer->shift;
3846
3847 /* only add to the list if value not set */
3848 if (enable == wcd->tx_port_value[port_id])
3849 return 0;
3850
3851 if (enable) {
3852 if (list_empty(&wcd->tx_chs[port_id].list)) {
3853 list_add_tail(&wcd->tx_chs[port_id].list,
3854 &wcd->dai[dai_id].slim_ch_list);
3855 } else {
3856 dev_err(wcd->dev ,"SLIM_TX%d PORT is busy\n", port_id);
3857 return 0;
3858 }
3859 } else {
3860 bool found = false;
3861
3862 list_for_each_entry_safe(ch, c, &wcd->dai[dai_id].slim_ch_list, list) {
3863 if (ch->port == port_id) {
3864 found = true;
3865 list_del_init(&wcd->tx_chs[port_id].list);
3866 break;
3867 }
3868 }
3869 if (!found)
3870 return 0;
3871 }
3872
3873 wcd->tx_port_value[port_id] = enable;
3874 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
3875
3876 return 1;
3877}
3878
3879static const struct snd_kcontrol_new aif1_slim_cap_mixer[] = {
3880 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3881 slim_tx_mixer_get, slim_tx_mixer_put),
3882 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3883 slim_tx_mixer_get, slim_tx_mixer_put),
3884 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3885 slim_tx_mixer_get, slim_tx_mixer_put),
3886 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3887 slim_tx_mixer_get, slim_tx_mixer_put),
3888 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3889 slim_tx_mixer_get, slim_tx_mixer_put),
3890 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3891 slim_tx_mixer_get, slim_tx_mixer_put),
3892 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3893 slim_tx_mixer_get, slim_tx_mixer_put),
3894 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3895 slim_tx_mixer_get, slim_tx_mixer_put),
3896 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3897 slim_tx_mixer_get, slim_tx_mixer_put),
3898 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3899 slim_tx_mixer_get, slim_tx_mixer_put),
3900 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3901 slim_tx_mixer_get, slim_tx_mixer_put),
3902 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3903 slim_tx_mixer_get, slim_tx_mixer_put),
3904 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3905 slim_tx_mixer_get, slim_tx_mixer_put),
3906};
3907
3908static const struct snd_kcontrol_new aif2_slim_cap_mixer[] = {
3909 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3910 slim_tx_mixer_get, slim_tx_mixer_put),
3911 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3912 slim_tx_mixer_get, slim_tx_mixer_put),
3913 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3914 slim_tx_mixer_get, slim_tx_mixer_put),
3915 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3916 slim_tx_mixer_get, slim_tx_mixer_put),
3917 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3918 slim_tx_mixer_get, slim_tx_mixer_put),
3919 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3920 slim_tx_mixer_get, slim_tx_mixer_put),
3921 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3922 slim_tx_mixer_get, slim_tx_mixer_put),
3923 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3924 slim_tx_mixer_get, slim_tx_mixer_put),
3925 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3926 slim_tx_mixer_get, slim_tx_mixer_put),
3927 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3928 slim_tx_mixer_get, slim_tx_mixer_put),
3929 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3930 slim_tx_mixer_get, slim_tx_mixer_put),
3931 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3932 slim_tx_mixer_get, slim_tx_mixer_put),
3933 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3934 slim_tx_mixer_get, slim_tx_mixer_put),
3935};
3936
3937static const struct snd_kcontrol_new aif3_slim_cap_mixer[] = {
3938 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD934X_TX0, 1, 0,
3939 slim_tx_mixer_get, slim_tx_mixer_put),
3940 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD934X_TX1, 1, 0,
3941 slim_tx_mixer_get, slim_tx_mixer_put),
3942 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD934X_TX2, 1, 0,
3943 slim_tx_mixer_get, slim_tx_mixer_put),
3944 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD934X_TX3, 1, 0,
3945 slim_tx_mixer_get, slim_tx_mixer_put),
3946 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD934X_TX4, 1, 0,
3947 slim_tx_mixer_get, slim_tx_mixer_put),
3948 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD934X_TX5, 1, 0,
3949 slim_tx_mixer_get, slim_tx_mixer_put),
3950 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD934X_TX6, 1, 0,
3951 slim_tx_mixer_get, slim_tx_mixer_put),
3952 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD934X_TX7, 1, 0,
3953 slim_tx_mixer_get, slim_tx_mixer_put),
3954 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD934X_TX8, 1, 0,
3955 slim_tx_mixer_get, slim_tx_mixer_put),
3956 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD934X_TX9, 1, 0,
3957 slim_tx_mixer_get, slim_tx_mixer_put),
3958 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD934X_TX10, 1, 0,
3959 slim_tx_mixer_get, slim_tx_mixer_put),
3960 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD934X_TX11, 1, 0,
3961 slim_tx_mixer_get, slim_tx_mixer_put),
3962 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD934X_TX13, 1, 0,
3963 slim_tx_mixer_get, slim_tx_mixer_put),
3964};
3965
3966static const struct snd_kcontrol_new wcd934x_snd_controls[] = {
3967 /* Gain Controls */
3968 SOC_SINGLE_TLV("EAR PA Volume", WCD934X_ANA_EAR, 4, 4, 1, ear_pa_gain),
3969 SOC_SINGLE_TLV("HPHL Volume", WCD934X_HPH_L_EN, 0, 24, 1, line_gain),
3970 SOC_SINGLE_TLV("HPHR Volume", WCD934X_HPH_R_EN, 0, 24, 1, line_gain),
3971 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD934X_DIFF_LO_LO1_COMPANDER,
3972 3, 16, 1, line_gain),
3973 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD934X_DIFF_LO_LO2_COMPANDER,
3974 3, 16, 1, line_gain),
3975
3976 SOC_SINGLE_TLV("ADC1 Volume", WCD934X_ANA_AMIC1, 0, 20, 0, analog_gain),
3977 SOC_SINGLE_TLV("ADC2 Volume", WCD934X_ANA_AMIC2, 0, 20, 0, analog_gain),
3978 SOC_SINGLE_TLV("ADC3 Volume", WCD934X_ANA_AMIC3, 0, 20, 0, analog_gain),
3979 SOC_SINGLE_TLV("ADC4 Volume", WCD934X_ANA_AMIC4, 0, 20, 0, analog_gain),
3980
3981 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL,
3982 -84, 40, digital_gain), /* -84dB min - 40dB max */
3983 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL,
3984 -84, 40, digital_gain),
3985 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL,
3986 -84, 40, digital_gain),
3987 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL,
3988 -84, 40, digital_gain),
3989 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL,
3990 -84, 40, digital_gain),
3991 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD934X_CDC_RX7_RX_VOL_CTL,
3992 -84, 40, digital_gain),
3993 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD934X_CDC_RX8_RX_VOL_CTL,
3994 -84, 40, digital_gain),
3995 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume",
3996 WCD934X_CDC_RX0_RX_VOL_MIX_CTL,
3997 -84, 40, digital_gain),
3998 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume",
3999 WCD934X_CDC_RX1_RX_VOL_MIX_CTL,
4000 -84, 40, digital_gain),
4001 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume",
4002 WCD934X_CDC_RX2_RX_VOL_MIX_CTL,
4003 -84, 40, digital_gain),
4004 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume",
4005 WCD934X_CDC_RX3_RX_VOL_MIX_CTL,
4006 -84, 40, digital_gain),
4007 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume",
4008 WCD934X_CDC_RX4_RX_VOL_MIX_CTL,
4009 -84, 40, digital_gain),
4010 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume",
4011 WCD934X_CDC_RX7_RX_VOL_MIX_CTL,
4012 -84, 40, digital_gain),
4013 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume",
4014 WCD934X_CDC_RX8_RX_VOL_MIX_CTL,
4015 -84, 40, digital_gain),
4016
4017 SOC_SINGLE_S8_TLV("DEC0 Volume", WCD934X_CDC_TX0_TX_VOL_CTL,
4018 -84, 40, digital_gain),
4019 SOC_SINGLE_S8_TLV("DEC1 Volume", WCD934X_CDC_TX1_TX_VOL_CTL,
4020 -84, 40, digital_gain),
4021 SOC_SINGLE_S8_TLV("DEC2 Volume", WCD934X_CDC_TX2_TX_VOL_CTL,
4022 -84, 40, digital_gain),
4023 SOC_SINGLE_S8_TLV("DEC3 Volume", WCD934X_CDC_TX3_TX_VOL_CTL,
4024 -84, 40, digital_gain),
4025 SOC_SINGLE_S8_TLV("DEC4 Volume", WCD934X_CDC_TX4_TX_VOL_CTL,
4026 -84, 40, digital_gain),
4027 SOC_SINGLE_S8_TLV("DEC5 Volume", WCD934X_CDC_TX5_TX_VOL_CTL,
4028 -84, 40, digital_gain),
4029 SOC_SINGLE_S8_TLV("DEC6 Volume", WCD934X_CDC_TX6_TX_VOL_CTL,
4030 -84, 40, digital_gain),
4031 SOC_SINGLE_S8_TLV("DEC7 Volume", WCD934X_CDC_TX7_TX_VOL_CTL,
4032 -84, 40, digital_gain),
4033 SOC_SINGLE_S8_TLV("DEC8 Volume", WCD934X_CDC_TX8_TX_VOL_CTL,
4034 -84, 40, digital_gain),
4035
4036 SOC_SINGLE_S8_TLV("IIR0 INP0 Volume",
4037 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL, -84, 40,
4038 digital_gain),
4039 SOC_SINGLE_S8_TLV("IIR0 INP1 Volume",
4040 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL, -84, 40,
4041 digital_gain),
4042 SOC_SINGLE_S8_TLV("IIR0 INP2 Volume",
4043 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL, -84, 40,
4044 digital_gain),
4045 SOC_SINGLE_S8_TLV("IIR0 INP3 Volume",
4046 WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL, -84, 40,
4047 digital_gain),
4048 SOC_SINGLE_S8_TLV("IIR1 INP0 Volume",
4049 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL, -84, 40,
4050 digital_gain),
4051 SOC_SINGLE_S8_TLV("IIR1 INP1 Volume",
4052 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL, -84, 40,
4053 digital_gain),
4054 SOC_SINGLE_S8_TLV("IIR1 INP2 Volume",
4055 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL, -84, 40,
4056 digital_gain),
4057 SOC_SINGLE_S8_TLV("IIR1 INP3 Volume",
4058 WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL, -84, 40,
4059 digital_gain),
4060
4061 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
4062 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
4063 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
4064 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
4065 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
4066 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
4067 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
4068 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
4069 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
4070
4071 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
4072 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
4073 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
4074 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
4075 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
4076 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
4077 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
4078 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
4079 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
4080 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
4081 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
4082 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
4083 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
4084 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
4085
4086 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
4087 wcd934x_rx_hph_mode_get, wcd934x_rx_hph_mode_put),
4088
4089 SOC_SINGLE("IIR1 Band1 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4090 0, 1, 0),
4091 SOC_SINGLE("IIR1 Band2 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4092 1, 1, 0),
4093 SOC_SINGLE("IIR1 Band3 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4094 2, 1, 0),
4095 SOC_SINGLE("IIR1 Band4 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4096 3, 1, 0),
4097 SOC_SINGLE("IIR1 Band5 Switch", WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,
4098 4, 1, 0),
4099 SOC_SINGLE("IIR2 Band1 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4100 0, 1, 0),
4101 SOC_SINGLE("IIR2 Band2 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4102 1, 1, 0),
4103 SOC_SINGLE("IIR2 Band3 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4104 2, 1, 0),
4105 SOC_SINGLE("IIR2 Band4 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4106 3, 1, 0),
4107 SOC_SINGLE("IIR2 Band5 Switch", WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,
4108 4, 1, 0),
4109 WCD_IIR_FILTER_CTL("IIR0 Band1", IIR0, BAND1),
4110 WCD_IIR_FILTER_CTL("IIR0 Band2", IIR0, BAND2),
4111 WCD_IIR_FILTER_CTL("IIR0 Band3", IIR0, BAND3),
4112 WCD_IIR_FILTER_CTL("IIR0 Band4", IIR0, BAND4),
4113 WCD_IIR_FILTER_CTL("IIR0 Band5", IIR0, BAND5),
4114
4115 WCD_IIR_FILTER_CTL("IIR1 Band1", IIR1, BAND1),
4116 WCD_IIR_FILTER_CTL("IIR1 Band2", IIR1, BAND2),
4117 WCD_IIR_FILTER_CTL("IIR1 Band3", IIR1, BAND3),
4118 WCD_IIR_FILTER_CTL("IIR1 Band4", IIR1, BAND4),
4119 WCD_IIR_FILTER_CTL("IIR1 Band5", IIR1, BAND5),
4120
4121 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
4122 wcd934x_compander_get, wcd934x_compander_set),
4123 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
4124 wcd934x_compander_get, wcd934x_compander_set),
4125 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
4126 wcd934x_compander_get, wcd934x_compander_set),
4127 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
4128 wcd934x_compander_get, wcd934x_compander_set),
4129 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
4130 wcd934x_compander_get, wcd934x_compander_set),
4131 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
4132 wcd934x_compander_get, wcd934x_compander_set),
4133};
4134
4135static void wcd934x_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
4136 struct snd_soc_component *component)
4137{
4138 int port_num = 0;
4139 unsigned short reg = 0;
4140 unsigned int val = 0;
4141 struct wcd934x_codec *wcd = dev_get_drvdata(component->dev);
4142 struct wcd934x_slim_ch *ch;
4143
4144 list_for_each_entry(ch, &dai->slim_ch_list, list) {
4145 if (ch->port >= WCD934X_RX_START) {
4146 port_num = ch->port - WCD934X_RX_START;
4147 reg = WCD934X_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
4148 } else {
4149 port_num = ch->port;
4150 reg = WCD934X_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
4151 }
4152
4153 regmap_read(wcd->if_regmap, reg, &val);
4154 if (!(val & BIT(port_num % 8)))
4155 regmap_write(wcd->if_regmap, reg,
4156 val | BIT(port_num % 8));
4157 }
4158}
4159
4160static int wcd934x_codec_enable_slim(struct snd_soc_dapm_widget *w,
4161 struct snd_kcontrol *kc, int event)
4162{
4163 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4164 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4165 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
4166
4167 switch (event) {
4168 case SND_SOC_DAPM_POST_PMU:
4169 wcd934x_codec_enable_int_port(dai, comp);
4170 break;
4171 }
4172
4173 return 0;
4174}
4175
4176static void wcd934x_codec_hd2_control(struct snd_soc_component *component,
4177 u16 interp_idx, int event)
4178{
4179 u16 hd2_scale_reg;
4180 u16 hd2_enable_reg = 0;
4181
4182 switch (interp_idx) {
4183 case INTERP_HPHL:
4184 hd2_scale_reg = WCD934X_CDC_RX1_RX_PATH_SEC3;
4185 hd2_enable_reg = WCD934X_CDC_RX1_RX_PATH_CFG0;
4186 break;
4187 case INTERP_HPHR:
4188 hd2_scale_reg = WCD934X_CDC_RX2_RX_PATH_SEC3;
4189 hd2_enable_reg = WCD934X_CDC_RX2_RX_PATH_CFG0;
4190 break;
4191 default:
4192 return;
4193 }
4194
4195 if (SND_SOC_DAPM_EVENT_ON(event)) {
4196 snd_soc_component_update_bits(component, hd2_scale_reg,
4197 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4198 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P3125);
4199 snd_soc_component_update_bits(component, hd2_enable_reg,
4200 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4201 WCD934X_CDC_RX_PATH_CFG_HD2_ENABLE);
4202 }
4203
4204 if (SND_SOC_DAPM_EVENT_OFF(event)) {
4205 snd_soc_component_update_bits(component, hd2_enable_reg,
4206 WCD934X_CDC_RX_PATH_CFG_HD2_EN_MASK,
4207 WCD934X_CDC_RX_PATH_CFG_HD2_DISABLE);
4208 snd_soc_component_update_bits(component, hd2_scale_reg,
4209 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
4210 WCD934X_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
4211 }
4212}
4213
4214static void wcd934x_codec_hphdelay_lutbypass(struct snd_soc_component *comp,
4215 u16 interp_idx, int event)
4216{
4217 u8 hph_dly_mask;
4218 u16 hph_lut_bypass_reg = 0;
4219
4220 switch (interp_idx) {
4221 case INTERP_HPHL:
4222 hph_dly_mask = 1;
4223 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHL_COMP_LUT;
4224 break;
4225 case INTERP_HPHR:
4226 hph_dly_mask = 2;
4227 hph_lut_bypass_reg = WCD934X_CDC_TOP_HPHR_COMP_LUT;
4228 break;
4229 default:
4230 return;
4231 }
4232
4233 if (SND_SOC_DAPM_EVENT_ON(event)) {
4234 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4235 hph_dly_mask, 0x0);
4236 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4237 WCD934X_HPH_LUT_BYPASS_MASK,
4238 WCD934X_HPH_LUT_BYPASS_ENABLE);
4239 }
4240
4241 if (SND_SOC_DAPM_EVENT_OFF(event)) {
4242 snd_soc_component_update_bits(comp, WCD934X_CDC_CLSH_TEST0,
4243 hph_dly_mask, hph_dly_mask);
4244 snd_soc_component_update_bits(comp, hph_lut_bypass_reg,
4245 WCD934X_HPH_LUT_BYPASS_MASK,
4246 WCD934X_HPH_LUT_BYPASS_DISABLE);
4247 }
4248}
4249
4250static int wcd934x_config_compander(struct snd_soc_component *comp,
4251 int interp_n, int event)
4252{
4253 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4254 int compander;
4255 u16 comp_ctl0_reg, rx_path_cfg0_reg;
4256
4257 /* EAR does not have compander */
4258 if (!interp_n)
4259 return 0;
4260
4261 compander = interp_n - 1;
4262 if (!wcd->comp_enabled[compander])
4263 return 0;
4264
4265 comp_ctl0_reg = WCD934X_CDC_COMPANDER1_CTL0 + (compander * 8);
4266 rx_path_cfg0_reg = WCD934X_CDC_RX1_RX_PATH_CFG0 + (compander * 20);
4267
4268 switch (event) {
4269 case SND_SOC_DAPM_PRE_PMU:
4270 /* Enable Compander Clock */
4271 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4272 WCD934X_COMP_CLK_EN_MASK,
4273 WCD934X_COMP_CLK_ENABLE);
4274 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4275 WCD934X_COMP_SOFT_RST_MASK,
4276 WCD934X_COMP_SOFT_RST_ENABLE);
4277 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4278 WCD934X_COMP_SOFT_RST_MASK,
4279 WCD934X_COMP_SOFT_RST_DISABLE);
4280 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4281 WCD934X_HPH_CMP_EN_MASK,
4282 WCD934X_HPH_CMP_ENABLE);
4283 break;
4284 case SND_SOC_DAPM_POST_PMD:
4285 snd_soc_component_update_bits(comp, rx_path_cfg0_reg,
4286 WCD934X_HPH_CMP_EN_MASK,
4287 WCD934X_HPH_CMP_DISABLE);
4288 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4289 WCD934X_COMP_HALT_MASK,
4290 WCD934X_COMP_HALT);
4291 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4292 WCD934X_COMP_SOFT_RST_MASK,
4293 WCD934X_COMP_SOFT_RST_ENABLE);
4294 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4295 WCD934X_COMP_SOFT_RST_MASK,
4296 WCD934X_COMP_SOFT_RST_DISABLE);
4297 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4298 WCD934X_COMP_CLK_EN_MASK, 0x0);
4299 snd_soc_component_update_bits(comp, comp_ctl0_reg,
4300 WCD934X_COMP_SOFT_RST_MASK, 0x0);
4301 break;
4302 }
4303
4304 return 0;
4305}
4306
4307static int wcd934x_codec_enable_interp_clk(struct snd_soc_dapm_widget *w,
4308 struct snd_kcontrol *kc, int event)
4309{
4310 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4311 int interp_idx = w->shift;
4312 u16 main_reg = WCD934X_CDC_RX0_RX_PATH_CTL + (interp_idx * 20);
4313
4314 switch (event) {
4315 case SND_SOC_DAPM_PRE_PMU:
4316 /* Clk enable */
4317 snd_soc_component_update_bits(comp, main_reg,
4318 WCD934X_RX_CLK_EN_MASK,
4319 WCD934X_RX_CLK_ENABLE);
4320 wcd934x_codec_hd2_control(comp, interp_idx, event);
4321 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4322 wcd934x_config_compander(comp, interp_idx, event);
4323 break;
4324 case SND_SOC_DAPM_POST_PMD:
4325 wcd934x_config_compander(comp, interp_idx, event);
4326 wcd934x_codec_hphdelay_lutbypass(comp, interp_idx, event);
4327 wcd934x_codec_hd2_control(comp, interp_idx, event);
4328 /* Clk Disable */
4329 snd_soc_component_update_bits(comp, main_reg,
4330 WCD934X_RX_CLK_EN_MASK, 0);
4331 /* Reset enable and disable */
4332 snd_soc_component_update_bits(comp, main_reg,
4333 WCD934X_RX_RESET_MASK,
4334 WCD934X_RX_RESET_ENABLE);
4335 snd_soc_component_update_bits(comp, main_reg,
4336 WCD934X_RX_RESET_MASK,
4337 WCD934X_RX_RESET_DISABLE);
4338 /* Reset rate to 48K*/
4339 snd_soc_component_update_bits(comp, main_reg,
4340 WCD934X_RX_PCM_RATE_MASK,
4341 WCD934X_RX_PCM_RATE_F_48K);
4342 break;
4343 }
4344
4345 return 0;
4346}
4347
4348static int wcd934x_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
4349 struct snd_kcontrol *kc, int event)
4350{
4351 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4352 int offset_val = 0;
4353 u16 gain_reg, mix_reg;
4354 int val = 0;
4355
4356 gain_reg = WCD934X_CDC_RX0_RX_VOL_MIX_CTL +
4357 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4358 mix_reg = WCD934X_CDC_RX0_RX_PATH_MIX_CTL +
4359 (w->shift * WCD934X_RX_PATH_CTL_OFFSET);
4360
4361 switch (event) {
4362 case SND_SOC_DAPM_PRE_PMU:
4363 /* Clk enable */
4364 snd_soc_component_update_bits(comp, mix_reg,
4365 WCD934X_CDC_RX_MIX_CLK_EN_MASK,
4366 WCD934X_CDC_RX_MIX_CLK_ENABLE);
4367 break;
4368
4369 case SND_SOC_DAPM_POST_PMU:
4370 val = snd_soc_component_read(comp, gain_reg);
4371 val += offset_val;
4372 snd_soc_component_write(comp, gain_reg, val);
4373 break;
4374 }
4375
4376 return 0;
4377}
4378
4379static int wcd934x_codec_set_iir_gain(struct snd_soc_dapm_widget *w,
4380 struct snd_kcontrol *kcontrol, int event)
4381{
4382 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4383 int reg = w->reg;
4384
4385 switch (event) {
4386 case SND_SOC_DAPM_POST_PMU:
4387 /* B1 GAIN */
4388 snd_soc_component_write(comp, reg,
4389 snd_soc_component_read(comp, reg));
4390 /* B2 GAIN */
4391 reg++;
4392 snd_soc_component_write(comp, reg,
4393 snd_soc_component_read(comp, reg));
4394 /* B3 GAIN */
4395 reg++;
4396 snd_soc_component_write(comp, reg,
4397 snd_soc_component_read(comp, reg));
4398 /* B4 GAIN */
4399 reg++;
4400 snd_soc_component_write(comp, reg,
4401 snd_soc_component_read(comp, reg));
4402 /* B5 GAIN */
4403 reg++;
4404 snd_soc_component_write(comp, reg,
4405 snd_soc_component_read(comp, reg));
4406 break;
4407 default:
4408 break;
4409 }
4410 return 0;
4411}
4412
4413static int wcd934x_codec_enable_main_path(struct snd_soc_dapm_widget *w,
4414 struct snd_kcontrol *kcontrol,
4415 int event)
4416{
4417 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4418 u16 gain_reg;
4419
4420 gain_reg = WCD934X_CDC_RX0_RX_VOL_CTL + (w->shift *
4421 WCD934X_RX_PATH_CTL_OFFSET);
4422
4423 switch (event) {
4424 case SND_SOC_DAPM_POST_PMU:
4425 snd_soc_component_write(comp, gain_reg,
4426 snd_soc_component_read(comp, gain_reg));
4427 break;
4428 }
4429
4430 return 0;
4431}
4432
4433static int wcd934x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
4434 struct snd_kcontrol *kc, int event)
4435{
4436 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4437 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4438
4439 switch (event) {
4440 case SND_SOC_DAPM_PRE_PMU:
4441 /* Disable AutoChop timer during power up */
4442 snd_soc_component_update_bits(comp,
4443 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4444 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4445 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4446 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4447
4448 break;
4449 case SND_SOC_DAPM_POST_PMD:
4450 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4451 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
4452 break;
4453 }
4454
4455 return 0;
4456}
4457
4458static int wcd934x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
4459 struct snd_kcontrol *kcontrol,
4460 int event)
4461{
4462 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4463 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4464 int hph_mode = wcd->hph_mode;
4465 u8 dem_inp;
4466
4467 switch (event) {
4468 case SND_SOC_DAPM_PRE_PMU:
4469 /* Read DEM INP Select */
4470 dem_inp = snd_soc_component_read(comp,
4471 WCD934X_CDC_RX1_RX_PATH_SEC0) & 0x03;
4472
4473 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4474 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4475 return -EINVAL;
4476 }
4477 if (hph_mode != CLS_H_LP)
4478 /* Ripple freq control enable */
4479 snd_soc_component_update_bits(comp,
4480 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4481 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4482 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4483 /* Disable AutoChop timer during power up */
4484 snd_soc_component_update_bits(comp,
4485 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4486 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4487 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4488 WCD_CLSH_STATE_HPHL, hph_mode);
4489
4490 break;
4491 case SND_SOC_DAPM_POST_PMD:
4492 /* 1000us required as per HW requirement */
4493 usleep_range(1000, 1100);
4494 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4495 WCD_CLSH_STATE_HPHL, hph_mode);
4496 if (hph_mode != CLS_H_LP)
4497 /* Ripple freq control disable */
4498 snd_soc_component_update_bits(comp,
4499 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4500 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4501
4502 break;
4503 default:
4504 break;
4505 }
4506
4507 return 0;
4508}
4509
4510static int wcd934x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
4511 struct snd_kcontrol *kcontrol,
4512 int event)
4513{
4514 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4515 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4516 int hph_mode = wcd->hph_mode;
4517 u8 dem_inp;
4518
4519 switch (event) {
4520 case SND_SOC_DAPM_PRE_PMU:
4521 dem_inp = snd_soc_component_read(comp,
4522 WCD934X_CDC_RX2_RX_PATH_SEC0) & 0x03;
4523 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
4524 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
4525 return -EINVAL;
4526 }
4527 if (hph_mode != CLS_H_LP)
4528 /* Ripple freq control enable */
4529 snd_soc_component_update_bits(comp,
4530 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4531 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK,
4532 WCD934X_SIDO_RIPPLE_FREQ_ENABLE);
4533 /* Disable AutoChop timer during power up */
4534 snd_soc_component_update_bits(comp,
4535 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4536 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK, 0x0);
4537 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4538 WCD_CLSH_STATE_HPHR,
4539 hph_mode);
4540 break;
4541 case SND_SOC_DAPM_POST_PMD:
4542 /* 1000us required as per HW requirement */
4543 usleep_range(1000, 1100);
4544
4545 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4546 WCD_CLSH_STATE_HPHR, hph_mode);
4547 if (hph_mode != CLS_H_LP)
4548 /* Ripple freq control disable */
4549 snd_soc_component_update_bits(comp,
4550 WCD934X_SIDO_NEW_VOUT_D_FREQ2,
4551 WCD934X_SIDO_RIPPLE_FREQ_EN_MASK, 0x0);
4552 break;
4553 default:
4554 break;
4555 }
4556
4557 return 0;
4558}
4559
4560static int wcd934x_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
4561 struct snd_kcontrol *kc, int event)
4562{
4563 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4564 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4565
4566 switch (event) {
4567 case SND_SOC_DAPM_PRE_PMU:
4568 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
4569 WCD_CLSH_STATE_LO, CLS_AB);
4570 break;
4571 case SND_SOC_DAPM_POST_PMD:
4572 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
4573 WCD_CLSH_STATE_LO, CLS_AB);
4574 break;
4575 }
4576
4577 return 0;
4578}
4579
4580static int wcd934x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
4581 struct snd_kcontrol *kcontrol,
4582 int event)
4583{
4584 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4585 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4586
4587 switch (event) {
4588 case SND_SOC_DAPM_POST_PMU:
4589 /*
4590 * 7ms sleep is required after PA is enabled as per
4591 * HW requirement. If compander is disabled, then
4592 * 20ms delay is needed.
4593 */
4594 usleep_range(20000, 20100);
4595
4596 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4597 WCD934X_HPH_OCP_DET_MASK,
4598 WCD934X_HPH_OCP_DET_ENABLE);
4599 /* Remove Mute on primary path */
4600 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4601 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4602 0);
4603 /* Enable GM3 boost */
4604 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4605 WCD934X_HPH_GM3_BOOST_EN_MASK,
4606 WCD934X_HPH_GM3_BOOST_ENABLE);
4607 /* Enable AutoChop timer at the end of power up */
4608 snd_soc_component_update_bits(comp,
4609 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4610 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4611 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4612 /* Remove mix path mute */
4613 snd_soc_component_update_bits(comp,
4614 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4615 WCD934X_CDC_RX_PGA_MUTE_EN_MASK, 0x00);
4616 break;
4617 case SND_SOC_DAPM_PRE_PMD:
4618 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4619 /* Enable DSD Mute before PA disable */
4620 snd_soc_component_update_bits(comp, WCD934X_HPH_L_TEST,
4621 WCD934X_HPH_OCP_DET_MASK,
4622 WCD934X_HPH_OCP_DET_DISABLE);
4623 snd_soc_component_update_bits(comp, WCD934X_CDC_RX1_RX_PATH_CTL,
4624 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4625 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4626 snd_soc_component_update_bits(comp,
4627 WCD934X_CDC_RX1_RX_PATH_MIX_CTL,
4628 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4629 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4630 break;
4631 case SND_SOC_DAPM_POST_PMD:
4632 /*
4633 * 5ms sleep is required after PA disable. If compander is
4634 * disabled, then 20ms delay is needed after PA disable.
4635 */
4636 usleep_range(20000, 20100);
4637 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHL_PA_OFF);
4638 break;
4639 }
4640
4641 return 0;
4642}
4643
4644static int wcd934x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
4645 struct snd_kcontrol *kcontrol,
4646 int event)
4647{
4648 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4649 struct wcd934x_codec *wcd = snd_soc_component_get_drvdata(comp);
4650
4651 switch (event) {
4652 case SND_SOC_DAPM_POST_PMU:
4653 /*
4654 * 7ms sleep is required after PA is enabled as per
4655 * HW requirement. If compander is disabled, then
4656 * 20ms delay is needed.
4657 */
4658 usleep_range(20000, 20100);
4659 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4660 WCD934X_HPH_OCP_DET_MASK,
4661 WCD934X_HPH_OCP_DET_ENABLE);
4662 /* Remove mute */
4663 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4664 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4665 0);
4666 /* Enable GM3 boost */
4667 snd_soc_component_update_bits(comp, WCD934X_HPH_CNP_WG_CTL,
4668 WCD934X_HPH_GM3_BOOST_EN_MASK,
4669 WCD934X_HPH_GM3_BOOST_ENABLE);
4670 /* Enable AutoChop timer at the end of power up */
4671 snd_soc_component_update_bits(comp,
4672 WCD934X_HPH_NEW_INT_HPH_TIMER1,
4673 WCD934X_HPH_AUTOCHOP_TIMER_EN_MASK,
4674 WCD934X_HPH_AUTOCHOP_TIMER_ENABLE);
4675 /* Remove mix path mute if it is enabled */
4676 if ((snd_soc_component_read(comp,
4677 WCD934X_CDC_RX2_RX_PATH_MIX_CTL)) & 0x10)
4678 snd_soc_component_update_bits(comp,
4679 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4680 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4681 WCD934X_CDC_RX_PGA_MUTE_DISABLE);
4682 break;
4683 case SND_SOC_DAPM_PRE_PMD:
4684 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_PRE_HPHR_PA_OFF);
4685 snd_soc_component_update_bits(comp, WCD934X_HPH_R_TEST,
4686 WCD934X_HPH_OCP_DET_MASK,
4687 WCD934X_HPH_OCP_DET_DISABLE);
4688 snd_soc_component_update_bits(comp, WCD934X_CDC_RX2_RX_PATH_CTL,
4689 WCD934X_RX_PATH_PGA_MUTE_EN_MASK,
4690 WCD934X_RX_PATH_PGA_MUTE_ENABLE);
4691 snd_soc_component_update_bits(comp,
4692 WCD934X_CDC_RX2_RX_PATH_MIX_CTL,
4693 WCD934X_CDC_RX_PGA_MUTE_EN_MASK,
4694 WCD934X_CDC_RX_PGA_MUTE_ENABLE);
4695 break;
4696 case SND_SOC_DAPM_POST_PMD:
4697 /*
4698 * 5ms sleep is required after PA disable. If compander is
4699 * disabled, then 20ms delay is needed after PA disable.
4700 */
4701 usleep_range(20000, 20100);
4702 wcd_mbhc_event_notify(wcd->mbhc, WCD_EVENT_POST_HPHR_PA_OFF);
4703 break;
4704 }
4705
4706 return 0;
4707}
4708
4709static u32 wcd934x_get_dmic_sample_rate(struct snd_soc_component *comp,
4710 unsigned int dmic,
4711 struct wcd934x_codec *wcd)
4712{
4713 u8 tx_stream_fs;
4714 u8 adc_mux_index = 0, adc_mux_sel = 0;
4715 bool dec_found = false;
4716 u16 adc_mux_ctl_reg, tx_fs_reg;
4717 u32 dmic_fs;
4718
4719 while (!dec_found && adc_mux_index < WCD934X_MAX_VALID_ADC_MUX) {
4720 if (adc_mux_index < 4) {
4721 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4722 (adc_mux_index * 2);
4723 } else if (adc_mux_index < WCD934X_INVALID_ADC_MUX) {
4724 adc_mux_ctl_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4725 adc_mux_index - 4;
4726 } else if (adc_mux_index == WCD934X_INVALID_ADC_MUX) {
4727 ++adc_mux_index;
4728 continue;
4729 }
4730 adc_mux_sel = ((snd_soc_component_read(comp, adc_mux_ctl_reg)
4731 & 0xF8) >> 3) - 1;
4732
4733 if (adc_mux_sel == dmic) {
4734 dec_found = true;
4735 break;
4736 }
4737
4738 ++adc_mux_index;
4739 }
4740
4741 if (dec_found && adc_mux_index <= 8) {
4742 tx_fs_reg = WCD934X_CDC_TX0_TX_PATH_CTL + (16 * adc_mux_index);
4743 tx_stream_fs = snd_soc_component_read(comp, tx_fs_reg) & 0x0F;
4744 if (tx_stream_fs <= 4)
4745 dmic_fs = min(wcd->dmic_sample_rate, WCD9XXX_DMIC_SAMPLE_RATE_2P4MHZ);
4746 else
4747 dmic_fs = WCD9XXX_DMIC_SAMPLE_RATE_4P8MHZ;
4748 } else {
4749 dmic_fs = wcd->dmic_sample_rate;
4750 }
4751
4752 return dmic_fs;
4753}
4754
4755static u8 wcd934x_get_dmic_clk_val(struct snd_soc_component *comp,
4756 u32 mclk_rate, u32 dmic_clk_rate)
4757{
4758 u32 div_factor;
4759 u8 dmic_ctl_val;
4760
4761 /* Default value to return in case of error */
4762 if (mclk_rate == WCD934X_MCLK_CLK_9P6MHZ)
4763 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4764 else
4765 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4766
4767 if (dmic_clk_rate == 0) {
4768 dev_err(comp->dev,
4769 "%s: dmic_sample_rate cannot be 0\n",
4770 __func__);
4771 goto done;
4772 }
4773
4774 div_factor = mclk_rate / dmic_clk_rate;
4775 switch (div_factor) {
4776 case 2:
4777 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_2;
4778 break;
4779 case 3:
4780 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_3;
4781 break;
4782 case 4:
4783 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_4;
4784 break;
4785 case 6:
4786 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_6;
4787 break;
4788 case 8:
4789 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_8;
4790 break;
4791 case 16:
4792 dmic_ctl_val = WCD934X_DMIC_CLK_DIV_16;
4793 break;
4794 default:
4795 dev_err(comp->dev,
4796 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
4797 __func__, div_factor, mclk_rate, dmic_clk_rate);
4798 break;
4799 }
4800
4801done:
4802 return dmic_ctl_val;
4803}
4804
4805static int wcd934x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
4806 struct snd_kcontrol *kcontrol, int event)
4807{
4808 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4809 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
4810 u8 dmic_clk_en = 0x01;
4811 u16 dmic_clk_reg;
4812 s32 *dmic_clk_cnt;
4813 u8 dmic_rate_val, dmic_rate_shift = 1;
4814 unsigned int dmic;
4815 u32 dmic_sample_rate;
4816 int ret;
4817 char *wname;
4818
4819 wname = strpbrk(w->name, "012345");
4820 if (!wname) {
4821 dev_err(comp->dev, "%s: widget not found\n", __func__);
4822 return -EINVAL;
4823 }
4824
4825 ret = kstrtouint(wname, 10, &dmic);
4826 if (ret < 0) {
4827 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
4828 __func__);
4829 return -EINVAL;
4830 }
4831
4832 switch (dmic) {
4833 case 0:
4834 case 1:
4835 dmic_clk_cnt = &wcd->dmic_0_1_clk_cnt;
4836 dmic_clk_reg = WCD934X_CPE_SS_DMIC0_CTL;
4837 break;
4838 case 2:
4839 case 3:
4840 dmic_clk_cnt = &wcd->dmic_2_3_clk_cnt;
4841 dmic_clk_reg = WCD934X_CPE_SS_DMIC1_CTL;
4842 break;
4843 case 4:
4844 case 5:
4845 dmic_clk_cnt = &wcd->dmic_4_5_clk_cnt;
4846 dmic_clk_reg = WCD934X_CPE_SS_DMIC2_CTL;
4847 break;
4848 default:
4849 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
4850 __func__);
4851 return -EINVAL;
4852 }
4853
4854 switch (event) {
4855 case SND_SOC_DAPM_PRE_PMU:
4856 dmic_sample_rate = wcd934x_get_dmic_sample_rate(comp, dmic,
4857 wcd);
4858 dmic_rate_val = wcd934x_get_dmic_clk_val(comp, wcd->rate,
4859 dmic_sample_rate);
4860 (*dmic_clk_cnt)++;
4861 if (*dmic_clk_cnt == 1) {
4862 dmic_rate_val = dmic_rate_val << dmic_rate_shift;
4863 snd_soc_component_update_bits(comp, dmic_clk_reg,
4864 WCD934X_DMIC_RATE_MASK,
4865 dmic_rate_val);
4866 snd_soc_component_update_bits(comp, dmic_clk_reg,
4867 dmic_clk_en, dmic_clk_en);
4868 }
4869
4870 break;
4871 case SND_SOC_DAPM_POST_PMD:
4872 (*dmic_clk_cnt)--;
4873 if (*dmic_clk_cnt == 0)
4874 snd_soc_component_update_bits(comp, dmic_clk_reg,
4875 dmic_clk_en, 0);
4876 break;
4877 }
4878
4879 return 0;
4880}
4881
4882static int wcd934x_codec_find_amic_input(struct snd_soc_component *comp,
4883 int adc_mux_n)
4884{
4885 u16 mask, shift, adc_mux_in_reg;
4886 u16 amic_mux_sel_reg;
4887 bool is_amic;
4888
4889 if (adc_mux_n < 0 || adc_mux_n > WCD934X_MAX_VALID_ADC_MUX ||
4890 adc_mux_n == WCD934X_INVALID_ADC_MUX)
4891 return 0;
4892
4893 if (adc_mux_n < 3) {
4894 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4895 adc_mux_n;
4896 mask = 0x03;
4897 shift = 0;
4898 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4899 2 * adc_mux_n;
4900 } else if (adc_mux_n < 4) {
4901 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4902 mask = 0x03;
4903 shift = 0;
4904 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0 +
4905 2 * adc_mux_n;
4906 } else if (adc_mux_n < 7) {
4907 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4908 (adc_mux_n - 4);
4909 mask = 0x0C;
4910 shift = 2;
4911 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4912 adc_mux_n - 4;
4913 } else if (adc_mux_n < 8) {
4914 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4915 mask = 0x0C;
4916 shift = 2;
4917 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4918 adc_mux_n - 4;
4919 } else if (adc_mux_n < 12) {
4920 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1 +
4921 ((adc_mux_n == 8) ? (adc_mux_n - 8) :
4922 (adc_mux_n - 9));
4923 mask = 0x30;
4924 shift = 4;
4925 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4926 adc_mux_n - 4;
4927 } else if (adc_mux_n < 13) {
4928 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1;
4929 mask = 0x30;
4930 shift = 4;
4931 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4932 adc_mux_n - 4;
4933 } else {
4934 adc_mux_in_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1;
4935 mask = 0xC0;
4936 shift = 6;
4937 amic_mux_sel_reg = WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0 +
4938 adc_mux_n - 4;
4939 }
4940
4941 is_amic = (((snd_soc_component_read(comp, adc_mux_in_reg)
4942 & mask) >> shift) == 1);
4943 if (!is_amic)
4944 return 0;
4945
4946 return snd_soc_component_read(comp, amic_mux_sel_reg) & 0x07;
4947}
4948
4949static u16 wcd934x_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
4950 int amic)
4951{
4952 u16 pwr_level_reg = 0;
4953
4954 switch (amic) {
4955 case 1:
4956 case 2:
4957 pwr_level_reg = WCD934X_ANA_AMIC1;
4958 break;
4959
4960 case 3:
4961 case 4:
4962 pwr_level_reg = WCD934X_ANA_AMIC3;
4963 break;
4964 default:
4965 break;
4966 }
4967
4968 return pwr_level_reg;
4969}
4970
4971static int wcd934x_codec_enable_dec(struct snd_soc_dapm_widget *w,
4972 struct snd_kcontrol *kcontrol, int event)
4973{
4974 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4975 unsigned int decimator;
4976 char *dec_adc_mux_name = NULL;
4977 char *widget_name;
4978 int ret = 0, amic_n;
4979 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
4980 u16 tx_gain_ctl_reg;
4981 char *dec;
4982 u8 hpf_coff_freq;
4983
4984 char *wname __free(kfree) = kstrndup(w->name, 15, GFP_KERNEL);
4985 if (!wname)
4986 return -ENOMEM;
4987
4988 widget_name = wname;
4989 dec_adc_mux_name = strsep(&widget_name, " ");
4990 if (!dec_adc_mux_name) {
4991 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
4992 __func__, w->name);
4993 return -EINVAL;
4994 }
4995 dec_adc_mux_name = widget_name;
4996
4997 dec = strpbrk(dec_adc_mux_name, "012345678");
4998 if (!dec) {
4999 dev_err(comp->dev, "%s: decimator index not found\n",
5000 __func__);
5001 return -EINVAL;
5002 }
5003
5004 ret = kstrtouint(dec, 10, &decimator);
5005 if (ret < 0) {
5006 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
5007 __func__, wname);
5008 return -EINVAL;
5009 }
5010
5011 tx_vol_ctl_reg = WCD934X_CDC_TX0_TX_PATH_CTL + 16 * decimator;
5012 hpf_gate_reg = WCD934X_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
5013 dec_cfg_reg = WCD934X_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
5014 tx_gain_ctl_reg = WCD934X_CDC_TX0_TX_VOL_CTL + 16 * decimator;
5015
5016 switch (event) {
5017 case SND_SOC_DAPM_PRE_PMU:
5018 amic_n = wcd934x_codec_find_amic_input(comp, decimator);
5019 if (amic_n)
5020 pwr_level_reg = wcd934x_codec_get_amic_pwlvl_reg(comp,
5021 amic_n);
5022
5023 if (!pwr_level_reg)
5024 break;
5025
5026 switch ((snd_soc_component_read(comp, pwr_level_reg) &
5027 WCD934X_AMIC_PWR_LVL_MASK) >>
5028 WCD934X_AMIC_PWR_LVL_SHIFT) {
5029 case WCD934X_AMIC_PWR_LEVEL_LP:
5030 snd_soc_component_update_bits(comp, dec_cfg_reg,
5031 WCD934X_DEC_PWR_LVL_MASK,
5032 WCD934X_DEC_PWR_LVL_LP);
5033 break;
5034 case WCD934X_AMIC_PWR_LEVEL_HP:
5035 snd_soc_component_update_bits(comp, dec_cfg_reg,
5036 WCD934X_DEC_PWR_LVL_MASK,
5037 WCD934X_DEC_PWR_LVL_HP);
5038 break;
5039 case WCD934X_AMIC_PWR_LEVEL_DEFAULT:
5040 case WCD934X_AMIC_PWR_LEVEL_HYBRID:
5041 default:
5042 snd_soc_component_update_bits(comp, dec_cfg_reg,
5043 WCD934X_DEC_PWR_LVL_MASK,
5044 WCD934X_DEC_PWR_LVL_DF);
5045 break;
5046 }
5047 break;
5048 case SND_SOC_DAPM_POST_PMU:
5049 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5050 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5051 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5052 snd_soc_component_update_bits(comp, dec_cfg_reg,
5053 TX_HPF_CUT_OFF_FREQ_MASK,
5054 CF_MIN_3DB_150HZ << 5);
5055 snd_soc_component_update_bits(comp, hpf_gate_reg,
5056 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5057 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5058 /*
5059 * Minimum 1 clk cycle delay is required as per
5060 * HW spec.
5061 */
5062 usleep_range(1000, 1010);
5063 snd_soc_component_update_bits(comp, hpf_gate_reg,
5064 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5065 0);
5066 }
5067 /* apply gain after decimator is enabled */
5068 snd_soc_component_write(comp, tx_gain_ctl_reg,
5069 snd_soc_component_read(comp,
5070 tx_gain_ctl_reg));
5071 break;
5072 case SND_SOC_DAPM_PRE_PMD:
5073 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
5074 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
5075
5076 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
5077 snd_soc_component_update_bits(comp, dec_cfg_reg,
5078 TX_HPF_CUT_OFF_FREQ_MASK,
5079 hpf_coff_freq << 5);
5080 snd_soc_component_update_bits(comp, hpf_gate_reg,
5081 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5082 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ);
5083 /*
5084 * Minimum 1 clk cycle delay is required as per
5085 * HW spec.
5086 */
5087 usleep_range(1000, 1010);
5088 snd_soc_component_update_bits(comp, hpf_gate_reg,
5089 WCD934X_HPH_CUTOFF_FREQ_CHANGE_REQ_MASK,
5090 0);
5091 }
5092 break;
5093 case SND_SOC_DAPM_POST_PMD:
5094 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
5095 0x10, 0x00);
5096 snd_soc_component_update_bits(comp, dec_cfg_reg,
5097 WCD934X_DEC_PWR_LVL_MASK,
5098 WCD934X_DEC_PWR_LVL_DF);
5099 break;
5100 }
5101
5102 return ret;
5103}
5104
5105static void wcd934x_codec_set_tx_hold(struct snd_soc_component *comp,
5106 u16 amic_reg, bool set)
5107{
5108 u8 mask = 0x20;
5109 u8 val;
5110
5111 if (amic_reg == WCD934X_ANA_AMIC1 ||
5112 amic_reg == WCD934X_ANA_AMIC3)
5113 mask = 0x40;
5114
5115 val = set ? mask : 0x00;
5116
5117 switch (amic_reg) {
5118 case WCD934X_ANA_AMIC1:
5119 case WCD934X_ANA_AMIC2:
5120 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC2,
5121 mask, val);
5122 break;
5123 case WCD934X_ANA_AMIC3:
5124 case WCD934X_ANA_AMIC4:
5125 snd_soc_component_update_bits(comp, WCD934X_ANA_AMIC4,
5126 mask, val);
5127 break;
5128 default:
5129 break;
5130 }
5131}
5132
5133static int wcd934x_codec_enable_adc(struct snd_soc_dapm_widget *w,
5134 struct snd_kcontrol *kcontrol, int event)
5135{
5136 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
5137
5138 switch (event) {
5139 case SND_SOC_DAPM_PRE_PMU:
5140 wcd934x_codec_set_tx_hold(comp, w->reg, true);
5141 break;
5142 default:
5143 break;
5144 }
5145
5146 return 0;
5147}
5148
5149static int wcd934x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
5150 struct snd_kcontrol *kcontrol,
5151 int event)
5152{
5153 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
5154 int micb_num = w->shift;
5155
5156 switch (event) {
5157 case SND_SOC_DAPM_PRE_PMU:
5158 wcd934x_micbias_control(component, micb_num, MICB_ENABLE, true);
5159 break;
5160 case SND_SOC_DAPM_POST_PMU:
5161 /* 1 msec delay as per HW requirement */
5162 usleep_range(1000, 1100);
5163 break;
5164 case SND_SOC_DAPM_POST_PMD:
5165 wcd934x_micbias_control(component, micb_num, MICB_DISABLE, true);
5166 break;
5167 }
5168
5169 return 0;
5170}
5171
5172static const struct snd_soc_dapm_widget wcd934x_dapm_widgets[] = {
5173 /* Analog Outputs */
5174 SND_SOC_DAPM_OUTPUT("EAR"),
5175 SND_SOC_DAPM_OUTPUT("HPHL"),
5176 SND_SOC_DAPM_OUTPUT("HPHR"),
5177 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
5178 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
5179 SND_SOC_DAPM_OUTPUT("SPK1 OUT"),
5180 SND_SOC_DAPM_OUTPUT("SPK2 OUT"),
5181 SND_SOC_DAPM_OUTPUT("ANC EAR"),
5182 SND_SOC_DAPM_OUTPUT("ANC HPHL"),
5183 SND_SOC_DAPM_OUTPUT("ANC HPHR"),
5184 SND_SOC_DAPM_OUTPUT("WDMA3_OUT"),
5185 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT1"),
5186 SND_SOC_DAPM_OUTPUT("MAD_CPE_OUT2"),
5187 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
5188 AIF1_PB, 0, wcd934x_codec_enable_slim,
5189 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5190 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
5191 AIF2_PB, 0, wcd934x_codec_enable_slim,
5192 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5193 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
5194 AIF3_PB, 0, wcd934x_codec_enable_slim,
5195 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5196 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
5197 AIF4_PB, 0, wcd934x_codec_enable_slim,
5198 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5199
5200 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD934X_RX0, 0,
5201 &slim_rx_mux[WCD934X_RX0]),
5202 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD934X_RX1, 0,
5203 &slim_rx_mux[WCD934X_RX1]),
5204 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD934X_RX2, 0,
5205 &slim_rx_mux[WCD934X_RX2]),
5206 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD934X_RX3, 0,
5207 &slim_rx_mux[WCD934X_RX3]),
5208 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD934X_RX4, 0,
5209 &slim_rx_mux[WCD934X_RX4]),
5210 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD934X_RX5, 0,
5211 &slim_rx_mux[WCD934X_RX5]),
5212 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD934X_RX6, 0,
5213 &slim_rx_mux[WCD934X_RX6]),
5214 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD934X_RX7, 0,
5215 &slim_rx_mux[WCD934X_RX7]),
5216
5217 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5218 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5219 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5220 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5221 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5222 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5223 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5224 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5225
5226 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_EAR, 0,
5227 &rx_int0_2_mux, wcd934x_codec_enable_mix_path,
5228 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5229 SND_SOC_DAPM_POST_PMD),
5230 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
5231 &rx_int1_2_mux, wcd934x_codec_enable_mix_path,
5232 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5233 SND_SOC_DAPM_POST_PMD),
5234 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", SND_SOC_NOPM, INTERP_HPHR, 0,
5235 &rx_int2_2_mux, wcd934x_codec_enable_mix_path,
5236 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5237 SND_SOC_DAPM_POST_PMD),
5238 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", SND_SOC_NOPM, INTERP_LO1, 0,
5239 &rx_int3_2_mux, wcd934x_codec_enable_mix_path,
5240 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5241 SND_SOC_DAPM_POST_PMD),
5242 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", SND_SOC_NOPM, INTERP_LO2, 0,
5243 &rx_int4_2_mux, wcd934x_codec_enable_mix_path,
5244 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5245 SND_SOC_DAPM_POST_PMD),
5246 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", SND_SOC_NOPM, INTERP_SPKR1, 0,
5247 &rx_int7_2_mux, wcd934x_codec_enable_mix_path,
5248 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5249 SND_SOC_DAPM_POST_PMD),
5250 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", SND_SOC_NOPM, INTERP_SPKR2, 0,
5251 &rx_int8_2_mux, wcd934x_codec_enable_mix_path,
5252 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5253 SND_SOC_DAPM_POST_PMD),
5254
5255 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5256 &rx_int0_1_mix_inp0_mux),
5257 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5258 &rx_int0_1_mix_inp1_mux),
5259 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5260 &rx_int0_1_mix_inp2_mux),
5261 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5262 &rx_int1_1_mix_inp0_mux),
5263 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5264 &rx_int1_1_mix_inp1_mux),
5265 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5266 &rx_int1_1_mix_inp2_mux),
5267 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5268 &rx_int2_1_mix_inp0_mux),
5269 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5270 &rx_int2_1_mix_inp1_mux),
5271 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5272 &rx_int2_1_mix_inp2_mux),
5273 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5274 &rx_int3_1_mix_inp0_mux),
5275 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5276 &rx_int3_1_mix_inp1_mux),
5277 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5278 &rx_int3_1_mix_inp2_mux),
5279 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5280 &rx_int4_1_mix_inp0_mux),
5281 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5282 &rx_int4_1_mix_inp1_mux),
5283 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5284 &rx_int4_1_mix_inp2_mux),
5285 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5286 &rx_int7_1_mix_inp0_mux),
5287 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5288 &rx_int7_1_mix_inp1_mux),
5289 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5290 &rx_int7_1_mix_inp2_mux),
5291 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
5292 &rx_int8_1_mix_inp0_mux),
5293 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
5294 &rx_int8_1_mix_inp1_mux),
5295 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
5296 &rx_int8_1_mix_inp2_mux),
5297 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5298 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5299 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5300 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0,
5301 rx_int1_asrc_switch,
5302 ARRAY_SIZE(rx_int1_asrc_switch)),
5303 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5304 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0,
5305 rx_int2_asrc_switch,
5306 ARRAY_SIZE(rx_int2_asrc_switch)),
5307 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5308 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0,
5309 rx_int3_asrc_switch,
5310 ARRAY_SIZE(rx_int3_asrc_switch)),
5311 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5312 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0,
5313 rx_int4_asrc_switch,
5314 ARRAY_SIZE(rx_int4_asrc_switch)),
5315 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5316 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5317 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5318 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
5319 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5320 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5321 SND_SOC_DAPM_MIXER("RX INT1 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5322 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5323 SND_SOC_DAPM_MIXER("RX INT2 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5324 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5325 SND_SOC_DAPM_MIXER("RX INT3 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5326 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5327 SND_SOC_DAPM_MIXER("RX INT4 MIX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5328
5329 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5330 SND_SOC_DAPM_MIXER_E("RX INT7 CHAIN", SND_SOC_NOPM, 0, 0,
5331 NULL, 0, NULL, 0),
5332 SND_SOC_DAPM_MIXER_E("RX INT8 CHAIN", SND_SOC_NOPM, 0, 0,
5333 NULL, 0, NULL, 0),
5334 SND_SOC_DAPM_MUX_E("RX INT0 MIX2 INP", WCD934X_CDC_RX0_RX_PATH_CFG0, 4,
5335 0, &rx_int0_mix2_inp_mux, NULL,
5336 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5337 SND_SOC_DAPM_MUX_E("RX INT1 MIX2 INP", WCD934X_CDC_RX1_RX_PATH_CFG0, 4,
5338 0, &rx_int1_mix2_inp_mux, NULL,
5339 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5340 SND_SOC_DAPM_MUX_E("RX INT2 MIX2 INP", WCD934X_CDC_RX2_RX_PATH_CFG0, 4,
5341 0, &rx_int2_mix2_inp_mux, NULL,
5342 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5343 SND_SOC_DAPM_MUX_E("RX INT3 MIX2 INP", WCD934X_CDC_RX3_RX_PATH_CFG0, 4,
5344 0, &rx_int3_mix2_inp_mux, NULL,
5345 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5346 SND_SOC_DAPM_MUX_E("RX INT4 MIX2 INP", WCD934X_CDC_RX4_RX_PATH_CFG0, 4,
5347 0, &rx_int4_mix2_inp_mux, NULL,
5348 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5349 SND_SOC_DAPM_MUX_E("RX INT7 MIX2 INP", WCD934X_CDC_RX7_RX_PATH_CFG0, 4,
5350 0, &rx_int7_mix2_inp_mux, NULL,
5351 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5352
5353 SND_SOC_DAPM_MUX("IIR0 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp0_mux),
5354 SND_SOC_DAPM_MUX("IIR0 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp1_mux),
5355 SND_SOC_DAPM_MUX("IIR0 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp2_mux),
5356 SND_SOC_DAPM_MUX("IIR0 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir0_inp3_mux),
5357 SND_SOC_DAPM_MUX("IIR1 INP0 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp0_mux),
5358 SND_SOC_DAPM_MUX("IIR1 INP1 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp1_mux),
5359 SND_SOC_DAPM_MUX("IIR1 INP2 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp2_mux),
5360 SND_SOC_DAPM_MUX("IIR1 INP3 MUX", SND_SOC_NOPM, 0, 0, &iir1_inp3_mux),
5361
5362 SND_SOC_DAPM_PGA_E("IIR0", WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,
5363 0, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5364 SND_SOC_DAPM_POST_PMU),
5365 SND_SOC_DAPM_PGA_E("IIR1", WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,
5366 1, 0, NULL, 0, wcd934x_codec_set_iir_gain,
5367 SND_SOC_DAPM_POST_PMU),
5368 SND_SOC_DAPM_MIXER("SRC0", WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,
5369 4, 0, NULL, 0),
5370 SND_SOC_DAPM_MIXER("SRC1", WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,
5371 4, 0, NULL, 0),
5372 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
5373 &rx_int0_dem_inp_mux),
5374 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
5375 &rx_int1_dem_inp_mux),
5376 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
5377 &rx_int2_dem_inp_mux),
5378
5379 SND_SOC_DAPM_MUX_E("RX INT0_1 INTERP", SND_SOC_NOPM, INTERP_EAR, 0,
5380 &rx_int0_1_interp_mux,
5381 wcd934x_codec_enable_main_path,
5382 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5383 SND_SOC_DAPM_POST_PMD),
5384 SND_SOC_DAPM_MUX_E("RX INT1_1 INTERP", SND_SOC_NOPM, INTERP_HPHL, 0,
5385 &rx_int1_1_interp_mux,
5386 wcd934x_codec_enable_main_path,
5387 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5388 SND_SOC_DAPM_POST_PMD),
5389 SND_SOC_DAPM_MUX_E("RX INT2_1 INTERP", SND_SOC_NOPM, INTERP_HPHR, 0,
5390 &rx_int2_1_interp_mux,
5391 wcd934x_codec_enable_main_path,
5392 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5393 SND_SOC_DAPM_POST_PMD),
5394 SND_SOC_DAPM_MUX_E("RX INT3_1 INTERP", SND_SOC_NOPM, INTERP_LO1, 0,
5395 &rx_int3_1_interp_mux,
5396 wcd934x_codec_enable_main_path,
5397 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5398 SND_SOC_DAPM_POST_PMD),
5399 SND_SOC_DAPM_MUX_E("RX INT4_1 INTERP", SND_SOC_NOPM, INTERP_LO2, 0,
5400 &rx_int4_1_interp_mux,
5401 wcd934x_codec_enable_main_path,
5402 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5403 SND_SOC_DAPM_POST_PMD),
5404 SND_SOC_DAPM_MUX_E("RX INT7_1 INTERP", SND_SOC_NOPM, INTERP_SPKR1, 0,
5405 &rx_int7_1_interp_mux,
5406 wcd934x_codec_enable_main_path,
5407 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5408 SND_SOC_DAPM_POST_PMD),
5409 SND_SOC_DAPM_MUX_E("RX INT8_1 INTERP", SND_SOC_NOPM, INTERP_SPKR2, 0,
5410 &rx_int8_1_interp_mux,
5411 wcd934x_codec_enable_main_path,
5412 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5413 SND_SOC_DAPM_POST_PMD),
5414
5415 SND_SOC_DAPM_MUX("RX INT0_2 INTERP", SND_SOC_NOPM, 0, 0,
5416 &rx_int0_2_interp_mux),
5417 SND_SOC_DAPM_MUX("RX INT1_2 INTERP", SND_SOC_NOPM, 0, 0,
5418 &rx_int1_2_interp_mux),
5419 SND_SOC_DAPM_MUX("RX INT2_2 INTERP", SND_SOC_NOPM, 0, 0,
5420 &rx_int2_2_interp_mux),
5421 SND_SOC_DAPM_MUX("RX INT3_2 INTERP", SND_SOC_NOPM, 0, 0,
5422 &rx_int3_2_interp_mux),
5423 SND_SOC_DAPM_MUX("RX INT4_2 INTERP", SND_SOC_NOPM, 0, 0,
5424 &rx_int4_2_interp_mux),
5425 SND_SOC_DAPM_MUX("RX INT7_2 INTERP", SND_SOC_NOPM, 0, 0,
5426 &rx_int7_2_interp_mux),
5427 SND_SOC_DAPM_MUX("RX INT8_2 INTERP", SND_SOC_NOPM, 0, 0,
5428 &rx_int8_2_interp_mux),
5429 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
5430 0, 0, wcd934x_codec_ear_dac_event,
5431 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5432 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5433 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD934X_ANA_HPH,
5434 5, 0, wcd934x_codec_hphl_dac_event,
5435 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5436 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5437 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD934X_ANA_HPH,
5438 4, 0, wcd934x_codec_hphr_dac_event,
5439 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5440 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5441 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
5442 0, 0, wcd934x_codec_lineout_dac_event,
5443 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5444 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
5445 0, 0, wcd934x_codec_lineout_dac_event,
5446 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5447 SND_SOC_DAPM_PGA_E("EAR PA", WCD934X_ANA_EAR, 7, 0, NULL, 0, NULL, 0),
5448 SND_SOC_DAPM_PGA_E("HPHL PA", WCD934X_ANA_HPH, 7, 0, NULL, 0,
5449 wcd934x_codec_enable_hphl_pa,
5450 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5451 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5452 SND_SOC_DAPM_PGA_E("HPHR PA", WCD934X_ANA_HPH, 6, 0, NULL, 0,
5453 wcd934x_codec_enable_hphr_pa,
5454 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5455 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5456 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD934X_ANA_LO_1_2, 7, 0, NULL, 0,
5457 NULL, 0),
5458 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD934X_ANA_LO_1_2, 6, 0, NULL, 0,
5459 NULL, 0),
5460 SND_SOC_DAPM_SUPPLY("RX_BIAS", WCD934X_ANA_RX_SUPPLIES, 0, 0, NULL,
5461 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5462 SND_SOC_DAPM_SUPPLY("SBOOST0", WCD934X_CDC_RX7_RX_PATH_CFG1,
5463 0, 0, NULL, 0),
5464 SND_SOC_DAPM_SUPPLY("SBOOST0_CLK", WCD934X_CDC_BOOST0_BOOST_PATH_CTL,
5465 0, 0, NULL, 0),
5466 SND_SOC_DAPM_SUPPLY("SBOOST1", WCD934X_CDC_RX8_RX_PATH_CFG1,
5467 0, 0, NULL, 0),
5468 SND_SOC_DAPM_SUPPLY("SBOOST1_CLK", WCD934X_CDC_BOOST1_BOOST_PATH_CTL,
5469 0, 0, NULL, 0),
5470 SND_SOC_DAPM_SUPPLY("INT0_CLK", SND_SOC_NOPM, INTERP_EAR, 0,
5471 wcd934x_codec_enable_interp_clk,
5472 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5473 SND_SOC_DAPM_SUPPLY("INT1_CLK", SND_SOC_NOPM, INTERP_HPHL, 0,
5474 wcd934x_codec_enable_interp_clk,
5475 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5476 SND_SOC_DAPM_SUPPLY("INT2_CLK", SND_SOC_NOPM, INTERP_HPHR, 0,
5477 wcd934x_codec_enable_interp_clk,
5478 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5479 SND_SOC_DAPM_SUPPLY("INT3_CLK", SND_SOC_NOPM, INTERP_LO1, 0,
5480 wcd934x_codec_enable_interp_clk,
5481 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5482 SND_SOC_DAPM_SUPPLY("INT4_CLK", SND_SOC_NOPM, INTERP_LO2, 0,
5483 wcd934x_codec_enable_interp_clk,
5484 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5485 SND_SOC_DAPM_SUPPLY("INT7_CLK", SND_SOC_NOPM, INTERP_SPKR1, 0,
5486 wcd934x_codec_enable_interp_clk,
5487 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5488 SND_SOC_DAPM_SUPPLY("INT8_CLK", SND_SOC_NOPM, INTERP_SPKR2, 0,
5489 wcd934x_codec_enable_interp_clk,
5490 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5491 SND_SOC_DAPM_SUPPLY("DSMDEM0_CLK", WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,
5492 0, 0, NULL, 0),
5493 SND_SOC_DAPM_SUPPLY("DSMDEM1_CLK", WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,
5494 0, 0, NULL, 0),
5495 SND_SOC_DAPM_SUPPLY("DSMDEM2_CLK", WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,
5496 0, 0, NULL, 0),
5497 SND_SOC_DAPM_SUPPLY("DSMDEM3_CLK", WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,
5498 0, 0, NULL, 0),
5499 SND_SOC_DAPM_SUPPLY("DSMDEM4_CLK", WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,
5500 0, 0, NULL, 0),
5501 SND_SOC_DAPM_SUPPLY("DSMDEM7_CLK", WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,
5502 0, 0, NULL, 0),
5503 SND_SOC_DAPM_SUPPLY("DSMDEM8_CLK", WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,
5504 0, 0, NULL, 0),
5505 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
5506 wcd934x_codec_enable_mclk,
5507 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5508
5509 /* TX */
5510 SND_SOC_DAPM_INPUT("AMIC1"),
5511 SND_SOC_DAPM_INPUT("AMIC2"),
5512 SND_SOC_DAPM_INPUT("AMIC3"),
5513 SND_SOC_DAPM_INPUT("AMIC4"),
5514 SND_SOC_DAPM_INPUT("AMIC5"),
5515 SND_SOC_DAPM_INPUT("DMIC0 Pin"),
5516 SND_SOC_DAPM_INPUT("DMIC1 Pin"),
5517 SND_SOC_DAPM_INPUT("DMIC2 Pin"),
5518 SND_SOC_DAPM_INPUT("DMIC3 Pin"),
5519 SND_SOC_DAPM_INPUT("DMIC4 Pin"),
5520 SND_SOC_DAPM_INPUT("DMIC5 Pin"),
5521
5522 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
5523 AIF1_CAP, 0, wcd934x_codec_enable_slim,
5524 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5525 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
5526 AIF2_CAP, 0, wcd934x_codec_enable_slim,
5527 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5528 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
5529 AIF3_CAP, 0, wcd934x_codec_enable_slim,
5530 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5531
5532 SND_SOC_DAPM_MIXER("SLIM TX0", SND_SOC_NOPM, 0, 0, NULL, 0),
5533 SND_SOC_DAPM_MIXER("SLIM TX1", SND_SOC_NOPM, 0, 0, NULL, 0),
5534 SND_SOC_DAPM_MIXER("SLIM TX2", SND_SOC_NOPM, 0, 0, NULL, 0),
5535 SND_SOC_DAPM_MIXER("SLIM TX3", SND_SOC_NOPM, 0, 0, NULL, 0),
5536 SND_SOC_DAPM_MIXER("SLIM TX4", SND_SOC_NOPM, 0, 0, NULL, 0),
5537 SND_SOC_DAPM_MIXER("SLIM TX5", SND_SOC_NOPM, 0, 0, NULL, 0),
5538 SND_SOC_DAPM_MIXER("SLIM TX6", SND_SOC_NOPM, 0, 0, NULL, 0),
5539 SND_SOC_DAPM_MIXER("SLIM TX7", SND_SOC_NOPM, 0, 0, NULL, 0),
5540 SND_SOC_DAPM_MIXER("SLIM TX8", SND_SOC_NOPM, 0, 0, NULL, 0),
5541 SND_SOC_DAPM_MIXER("SLIM TX9", SND_SOC_NOPM, 0, 0, NULL, 0),
5542 SND_SOC_DAPM_MIXER("SLIM TX10", SND_SOC_NOPM, 0, 0, NULL, 0),
5543 SND_SOC_DAPM_MIXER("SLIM TX11", SND_SOC_NOPM, 0, 0, NULL, 0),
5544 SND_SOC_DAPM_MIXER("SLIM TX13", SND_SOC_NOPM, 0, 0, NULL, 0),
5545
5546 /* Digital Mic Inputs */
5547 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
5548 wcd934x_codec_enable_dmic,
5549 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5550 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
5551 wcd934x_codec_enable_dmic,
5552 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5553 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
5554 wcd934x_codec_enable_dmic,
5555 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5556 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
5557 wcd934x_codec_enable_dmic,
5558 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5559 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
5560 wcd934x_codec_enable_dmic,
5561 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5562 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
5563 wcd934x_codec_enable_dmic,
5564 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
5565 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_dmic_mux0),
5566 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_dmic_mux1),
5567 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_dmic_mux2),
5568 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_dmic_mux3),
5569 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_dmic_mux4),
5570 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_dmic_mux5),
5571 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_dmic_mux6),
5572 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_dmic_mux7),
5573 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_dmic_mux8),
5574 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_amic_mux0),
5575 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_amic_mux1),
5576 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_amic_mux2),
5577 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_amic_mux3),
5578 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_amic_mux4),
5579 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_amic_mux5),
5580 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_amic_mux6),
5581 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_amic_mux7),
5582 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0, &tx_amic_mux8),
5583 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD934X_CDC_TX0_TX_PATH_CTL, 5, 0,
5584 &tx_adc_mux0_mux, wcd934x_codec_enable_dec,
5585 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5586 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5587 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD934X_CDC_TX1_TX_PATH_CTL, 5, 0,
5588 &tx_adc_mux1_mux, wcd934x_codec_enable_dec,
5589 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5590 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5591 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD934X_CDC_TX2_TX_PATH_CTL, 5, 0,
5592 &tx_adc_mux2_mux, wcd934x_codec_enable_dec,
5593 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5594 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5595 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD934X_CDC_TX3_TX_PATH_CTL, 5, 0,
5596 &tx_adc_mux3_mux, wcd934x_codec_enable_dec,
5597 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5598 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5599 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD934X_CDC_TX4_TX_PATH_CTL, 5, 0,
5600 &tx_adc_mux4_mux, wcd934x_codec_enable_dec,
5601 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5602 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5603 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD934X_CDC_TX5_TX_PATH_CTL, 5, 0,
5604 &tx_adc_mux5_mux, wcd934x_codec_enable_dec,
5605 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5606 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5607 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD934X_CDC_TX6_TX_PATH_CTL, 5, 0,
5608 &tx_adc_mux6_mux, wcd934x_codec_enable_dec,
5609 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5610 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5611 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD934X_CDC_TX7_TX_PATH_CTL, 5, 0,
5612 &tx_adc_mux7_mux, wcd934x_codec_enable_dec,
5613 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5614 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5615 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD934X_CDC_TX8_TX_PATH_CTL, 5, 0,
5616 &tx_adc_mux8_mux, wcd934x_codec_enable_dec,
5617 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
5618 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
5619 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD934X_ANA_AMIC1, 7, 0,
5620 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5621 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD934X_ANA_AMIC2, 7, 0,
5622 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5623 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD934X_ANA_AMIC3, 7, 0,
5624 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5625 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD934X_ANA_AMIC4, 7, 0,
5626 wcd934x_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
5627 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
5628 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5629 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5630 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
5631 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5632 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5633 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
5634 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5635 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5636 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
5637 wcd934x_codec_enable_micbias, SND_SOC_DAPM_PRE_PMU |
5638 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
5639
5640 SND_SOC_DAPM_MUX("AMIC4_5 SEL", SND_SOC_NOPM, 0, 0, &tx_amic4_5),
5641 SND_SOC_DAPM_MUX("CDC_IF TX0 MUX", SND_SOC_NOPM, WCD934X_TX0, 0,
5642 &cdc_if_tx0_mux),
5643 SND_SOC_DAPM_MUX("CDC_IF TX1 MUX", SND_SOC_NOPM, WCD934X_TX1, 0,
5644 &cdc_if_tx1_mux),
5645 SND_SOC_DAPM_MUX("CDC_IF TX2 MUX", SND_SOC_NOPM, WCD934X_TX2, 0,
5646 &cdc_if_tx2_mux),
5647 SND_SOC_DAPM_MUX("CDC_IF TX3 MUX", SND_SOC_NOPM, WCD934X_TX3, 0,
5648 &cdc_if_tx3_mux),
5649 SND_SOC_DAPM_MUX("CDC_IF TX4 MUX", SND_SOC_NOPM, WCD934X_TX4, 0,
5650 &cdc_if_tx4_mux),
5651 SND_SOC_DAPM_MUX("CDC_IF TX5 MUX", SND_SOC_NOPM, WCD934X_TX5, 0,
5652 &cdc_if_tx5_mux),
5653 SND_SOC_DAPM_MUX("CDC_IF TX6 MUX", SND_SOC_NOPM, WCD934X_TX6, 0,
5654 &cdc_if_tx6_mux),
5655 SND_SOC_DAPM_MUX("CDC_IF TX7 MUX", SND_SOC_NOPM, WCD934X_TX7, 0,
5656 &cdc_if_tx7_mux),
5657 SND_SOC_DAPM_MUX("CDC_IF TX8 MUX", SND_SOC_NOPM, WCD934X_TX8, 0,
5658 &cdc_if_tx8_mux),
5659 SND_SOC_DAPM_MUX("CDC_IF TX9 MUX", SND_SOC_NOPM, WCD934X_TX9, 0,
5660 &cdc_if_tx9_mux),
5661 SND_SOC_DAPM_MUX("CDC_IF TX10 MUX", SND_SOC_NOPM, WCD934X_TX10, 0,
5662 &cdc_if_tx10_mux),
5663 SND_SOC_DAPM_MUX("CDC_IF TX11 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5664 &cdc_if_tx11_mux),
5665 SND_SOC_DAPM_MUX("CDC_IF TX11 INP1 MUX", SND_SOC_NOPM, WCD934X_TX11, 0,
5666 &cdc_if_tx11_inp1_mux),
5667 SND_SOC_DAPM_MUX("CDC_IF TX13 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5668 &cdc_if_tx13_mux),
5669 SND_SOC_DAPM_MUX("CDC_IF TX13 INP1 MUX", SND_SOC_NOPM, WCD934X_TX13, 0,
5670 &cdc_if_tx13_inp1_mux),
5671 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
5672 aif1_slim_cap_mixer,
5673 ARRAY_SIZE(aif1_slim_cap_mixer)),
5674 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
5675 aif2_slim_cap_mixer,
5676 ARRAY_SIZE(aif2_slim_cap_mixer)),
5677 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
5678 aif3_slim_cap_mixer,
5679 ARRAY_SIZE(aif3_slim_cap_mixer)),
5680};
5681
5682static const struct snd_soc_dapm_route wcd934x_audio_map[] = {
5683 /* RX0-RX7 */
5684 WCD934X_SLIM_RX_AIF_PATH(0),
5685 WCD934X_SLIM_RX_AIF_PATH(1),
5686 WCD934X_SLIM_RX_AIF_PATH(2),
5687 WCD934X_SLIM_RX_AIF_PATH(3),
5688 WCD934X_SLIM_RX_AIF_PATH(4),
5689 WCD934X_SLIM_RX_AIF_PATH(5),
5690 WCD934X_SLIM_RX_AIF_PATH(6),
5691 WCD934X_SLIM_RX_AIF_PATH(7),
5692
5693 /* RX0 Ear out */
5694 WCD934X_INTERPOLATOR_PATH(0),
5695 WCD934X_INTERPOLATOR_MIX2(0),
5696 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 MIX2"},
5697 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
5698 {"RX INT0 DAC", NULL, "RX_BIAS"},
5699 {"EAR PA", NULL, "RX INT0 DAC"},
5700 {"EAR", NULL, "EAR PA"},
5701
5702 /* RX1 Headphone left */
5703 WCD934X_INTERPOLATOR_PATH(1),
5704 WCD934X_INTERPOLATOR_MIX2(1),
5705 {"RX INT1 MIX3", NULL, "RX INT1 MIX2"},
5706 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 MIX3"},
5707 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
5708 {"RX INT1 DAC", NULL, "RX_BIAS"},
5709 {"HPHL PA", NULL, "RX INT1 DAC"},
5710 {"HPHL", NULL, "HPHL PA"},
5711
5712 /* RX2 Headphone right */
5713 WCD934X_INTERPOLATOR_PATH(2),
5714 WCD934X_INTERPOLATOR_MIX2(2),
5715 {"RX INT2 MIX3", NULL, "RX INT2 MIX2"},
5716 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 MIX3"},
5717 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
5718 {"RX INT2 DAC", NULL, "RX_BIAS"},
5719 {"HPHR PA", NULL, "RX INT2 DAC"},
5720 {"HPHR", NULL, "HPHR PA"},
5721
5722 /* RX3 HIFi LineOut1 */
5723 WCD934X_INTERPOLATOR_PATH(3),
5724 WCD934X_INTERPOLATOR_MIX2(3),
5725 {"RX INT3 MIX3", NULL, "RX INT3 MIX2"},
5726 {"RX INT3 DAC", NULL, "RX INT3 MIX3"},
5727 {"RX INT3 DAC", NULL, "RX_BIAS"},
5728 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
5729 {"LINEOUT1", NULL, "LINEOUT1 PA"},
5730
5731 /* RX4 HIFi LineOut2 */
5732 WCD934X_INTERPOLATOR_PATH(4),
5733 WCD934X_INTERPOLATOR_MIX2(4),
5734 {"RX INT4 MIX3", NULL, "RX INT4 MIX2"},
5735 {"RX INT4 DAC", NULL, "RX INT4 MIX3"},
5736 {"RX INT4 DAC", NULL, "RX_BIAS"},
5737 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
5738 {"LINEOUT2", NULL, "LINEOUT2 PA"},
5739
5740 /* RX7 Speaker Left Out PA */
5741 WCD934X_INTERPOLATOR_PATH(7),
5742 WCD934X_INTERPOLATOR_MIX2(7),
5743 {"RX INT7 CHAIN", NULL, "RX INT7 MIX2"},
5744 {"RX INT7 CHAIN", NULL, "RX_BIAS"},
5745 {"RX INT7 CHAIN", NULL, "SBOOST0"},
5746 {"RX INT7 CHAIN", NULL, "SBOOST0_CLK"},
5747 {"SPK1 OUT", NULL, "RX INT7 CHAIN"},
5748
5749 /* RX8 Speaker Right Out PA */
5750 WCD934X_INTERPOLATOR_PATH(8),
5751 {"RX INT8 CHAIN", NULL, "RX INT8 SEC MIX"},
5752 {"RX INT8 CHAIN", NULL, "RX_BIAS"},
5753 {"RX INT8 CHAIN", NULL, "SBOOST1"},
5754 {"RX INT8 CHAIN", NULL, "SBOOST1_CLK"},
5755 {"SPK2 OUT", NULL, "RX INT8 CHAIN"},
5756
5757 /* Tx */
5758 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
5759 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
5760 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
5761
5762 WCD934X_SLIM_TX_AIF_PATH(0),
5763 WCD934X_SLIM_TX_AIF_PATH(1),
5764 WCD934X_SLIM_TX_AIF_PATH(2),
5765 WCD934X_SLIM_TX_AIF_PATH(3),
5766 WCD934X_SLIM_TX_AIF_PATH(4),
5767 WCD934X_SLIM_TX_AIF_PATH(5),
5768 WCD934X_SLIM_TX_AIF_PATH(6),
5769 WCD934X_SLIM_TX_AIF_PATH(7),
5770 WCD934X_SLIM_TX_AIF_PATH(8),
5771
5772 WCD934X_ADC_MUX(0),
5773 WCD934X_ADC_MUX(1),
5774 WCD934X_ADC_MUX(2),
5775 WCD934X_ADC_MUX(3),
5776 WCD934X_ADC_MUX(4),
5777 WCD934X_ADC_MUX(5),
5778 WCD934X_ADC_MUX(6),
5779 WCD934X_ADC_MUX(7),
5780 WCD934X_ADC_MUX(8),
5781
5782 {"CDC_IF TX0 MUX", "DEC0", "ADC MUX0"},
5783 {"CDC_IF TX1 MUX", "DEC1", "ADC MUX1"},
5784 {"CDC_IF TX2 MUX", "DEC2", "ADC MUX2"},
5785 {"CDC_IF TX3 MUX", "DEC3", "ADC MUX3"},
5786 {"CDC_IF TX4 MUX", "DEC4", "ADC MUX4"},
5787 {"CDC_IF TX5 MUX", "DEC5", "ADC MUX5"},
5788 {"CDC_IF TX6 MUX", "DEC6", "ADC MUX6"},
5789 {"CDC_IF TX7 MUX", "DEC7", "ADC MUX7"},
5790 {"CDC_IF TX8 MUX", "DEC8", "ADC MUX8"},
5791
5792 {"AMIC4_5 SEL", "AMIC4", "AMIC4"},
5793 {"AMIC4_5 SEL", "AMIC5", "AMIC5"},
5794
5795 { "DMIC0", NULL, "DMIC0 Pin" },
5796 { "DMIC1", NULL, "DMIC1 Pin" },
5797 { "DMIC2", NULL, "DMIC2 Pin" },
5798 { "DMIC3", NULL, "DMIC3 Pin" },
5799 { "DMIC4", NULL, "DMIC4 Pin" },
5800 { "DMIC5", NULL, "DMIC5 Pin" },
5801
5802 {"ADC1", NULL, "AMIC1"},
5803 {"ADC2", NULL, "AMIC2"},
5804 {"ADC3", NULL, "AMIC3"},
5805 {"ADC4", NULL, "AMIC4_5 SEL"},
5806
5807 WCD934X_IIR_INP_MUX(0),
5808 WCD934X_IIR_INP_MUX(1),
5809
5810 {"SRC0", NULL, "IIR0"},
5811 {"SRC1", NULL, "IIR1"},
5812};
5813
5814static int wcd934x_codec_set_jack(struct snd_soc_component *comp,
5815 struct snd_soc_jack *jack, void *data)
5816{
5817 struct wcd934x_codec *wcd = dev_get_drvdata(comp->dev);
5818 int ret = 0;
5819
5820 if (!wcd->mbhc)
5821 return -ENOTSUPP;
5822
5823 if (jack && !wcd->mbhc_started) {
5824 ret = wcd_mbhc_start(wcd->mbhc, &wcd->mbhc_cfg, jack);
5825 wcd->mbhc_started = true;
5826 } else if (wcd->mbhc_started) {
5827 wcd_mbhc_stop(wcd->mbhc);
5828 wcd->mbhc_started = false;
5829 }
5830
5831 return ret;
5832}
5833
5834static const struct snd_soc_component_driver wcd934x_component_drv = {
5835 .probe = wcd934x_comp_probe,
5836 .remove = wcd934x_comp_remove,
5837 .set_sysclk = wcd934x_comp_set_sysclk,
5838 .controls = wcd934x_snd_controls,
5839 .num_controls = ARRAY_SIZE(wcd934x_snd_controls),
5840 .dapm_widgets = wcd934x_dapm_widgets,
5841 .num_dapm_widgets = ARRAY_SIZE(wcd934x_dapm_widgets),
5842 .dapm_routes = wcd934x_audio_map,
5843 .num_dapm_routes = ARRAY_SIZE(wcd934x_audio_map),
5844 .set_jack = wcd934x_codec_set_jack,
5845 .endianness = 1,
5846};
5847
5848static int wcd934x_codec_parse_data(struct wcd934x_codec *wcd)
5849{
5850 struct device *dev = &wcd->sdev->dev;
5851 struct wcd_mbhc_config *cfg = &wcd->mbhc_cfg;
5852 struct device_node *ifc_dev_np;
5853
5854 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5855 if (!ifc_dev_np)
5856 return dev_err_probe(dev, -EINVAL, "No Interface device found\n");
5857
5858 wcd->sidev = of_slim_get_device(wcd->sdev->ctrl, ifc_dev_np);
5859 of_node_put(ifc_dev_np);
5860 if (!wcd->sidev)
5861 return dev_err_probe(dev, -EINVAL, "Unable to get SLIM Interface device\n");
5862
5863 slim_get_logical_addr(wcd->sidev);
5864 wcd->if_regmap = regmap_init_slimbus(wcd->sidev,
5865 &wcd934x_ifc_regmap_config);
5866 if (IS_ERR(wcd->if_regmap))
5867 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5868 "Failed to allocate ifc register map\n");
5869
5870 of_property_read_u32(dev->parent->of_node, "qcom,dmic-sample-rate",
5871 &wcd->dmic_sample_rate);
5872
5873 cfg->mbhc_micbias = MIC_BIAS_2;
5874 cfg->anc_micbias = MIC_BIAS_2;
5875 cfg->v_hs_max = WCD_MBHC_HS_V_MAX;
5876 cfg->num_btn = WCD934X_MBHC_MAX_BUTTONS;
5877 cfg->micb_mv = wcd->micb2_mv;
5878 cfg->linein_th = 5000;
5879 cfg->hs_thr = 1700;
5880 cfg->hph_thr = 50;
5881
5882 wcd_dt_parse_mbhc_data(dev, cfg);
5883
5884
5885 return 0;
5886}
5887
5888static int wcd934x_codec_probe(struct platform_device *pdev)
5889{
5890 struct device *dev = &pdev->dev;
5891 struct wcd934x_ddata *data = dev_get_drvdata(dev->parent);
5892 struct wcd934x_codec *wcd;
5893 int ret, irq;
5894
5895 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5896 if (!wcd)
5897 return -ENOMEM;
5898
5899 wcd->dev = dev;
5900 wcd->regmap = data->regmap;
5901 wcd->extclk = data->extclk;
5902 wcd->sdev = to_slim_device(data->dev);
5903 mutex_init(&wcd->sysclk_mutex);
5904 mutex_init(&wcd->micb_lock);
5905
5906 ret = wcd934x_codec_parse_data(wcd);
5907 if (ret)
5908 return ret;
5909
5910 /* set default rate 9P6MHz */
5911 regmap_update_bits(wcd->regmap, WCD934X_CODEC_RPM_CLK_MCLK_CFG,
5912 WCD934X_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
5913 WCD934X_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
5914 memcpy(wcd->rx_chs, wcd934x_rx_chs, sizeof(wcd934x_rx_chs));
5915 memcpy(wcd->tx_chs, wcd934x_tx_chs, sizeof(wcd934x_tx_chs));
5916
5917 irq = regmap_irq_get_virq(data->irq_data, WCD934X_IRQ_SLIMBUS);
5918 if (irq < 0)
5919 return dev_err_probe(wcd->dev, irq, "Failed to get SLIM IRQ\n");
5920
5921 ret = devm_request_threaded_irq(dev, irq, NULL,
5922 wcd934x_slim_irq_handler,
5923 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
5924 "slim", wcd);
5925 if (ret)
5926 return dev_err_probe(dev, ret, "Failed to request slimbus irq\n");
5927
5928 wcd934x_register_mclk_output(wcd);
5929 platform_set_drvdata(pdev, wcd);
5930
5931 return devm_snd_soc_register_component(dev, &wcd934x_component_drv,
5932 wcd934x_slim_dais,
5933 ARRAY_SIZE(wcd934x_slim_dais));
5934}
5935
5936static const struct platform_device_id wcd934x_driver_id[] = {
5937 {
5938 .name = "wcd934x-codec",
5939 },
5940 {},
5941};
5942MODULE_DEVICE_TABLE(platform, wcd934x_driver_id);
5943
5944static struct platform_driver wcd934x_codec_driver = {
5945 .probe = &wcd934x_codec_probe,
5946 .id_table = wcd934x_driver_id,
5947 .driver = {
5948 .name = "wcd934x-codec",
5949 }
5950};
5951
5952module_platform_driver(wcd934x_codec_driver);
5953MODULE_DESCRIPTION("WCD934x codec driver");
5954MODULE_LICENSE("GPL v2");