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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Nuvoton NAU8825 audio codec driver
4 *
5 * Copyright 2015 Google Chromium project.
6 * Author: Anatol Pomozov <anatol@chromium.org>
7 * Copyright 2015 Nuvoton Technology Corp.
8 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
9 */
10
11#include <linux/module.h>
12#include <linux/delay.h>
13#include <linux/init.h>
14#include <linux/int_log.h>
15#include <linux/i2c.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
19#include <linux/acpi.h>
20#include <linux/math64.h>
21#include <linux/semaphore.h>
22
23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/jack.h>
30
31
32#include "nau8825.h"
33
34
35#define NUVOTON_CODEC_DAI "nau8825-hifi"
36
37#define NAU_FREF_MAX 13500000
38#define NAU_FVCO_MAX 124000000
39#define NAU_FVCO_MIN 90000000
40
41/* cross talk suppression detection */
42#define GAIN_AUGMENT 22500
43#define SIDETONE_BASE 207000
44
45/* the maximum frequency of CLK_ADC and CLK_DAC */
46#define CLK_DA_AD_MAX 6144000
47
48static int nau8825_configure_sysclk(struct nau8825 *nau8825,
49 int clk_id, unsigned int freq);
50static bool nau8825_is_jack_inserted(struct regmap *regmap);
51
52struct nau8825_fll {
53 int mclk_src;
54 int ratio;
55 int fll_frac;
56 int fll_frac_num;
57 int fll_int;
58 int clk_ref_div;
59};
60
61struct nau8825_fll_attr {
62 unsigned int param;
63 unsigned int val;
64};
65
66/* scaling for mclk from sysclk_src output */
67static const struct nau8825_fll_attr mclk_src_scaling[] = {
68 { 1, 0x0 },
69 { 2, 0x2 },
70 { 4, 0x3 },
71 { 8, 0x4 },
72 { 16, 0x5 },
73 { 32, 0x6 },
74 { 3, 0x7 },
75 { 6, 0xa },
76 { 12, 0xb },
77 { 24, 0xc },
78 { 48, 0xd },
79 { 96, 0xe },
80 { 5, 0xf },
81};
82
83/* ratio for input clk freq */
84static const struct nau8825_fll_attr fll_ratio[] = {
85 { 512000, 0x01 },
86 { 256000, 0x02 },
87 { 128000, 0x04 },
88 { 64000, 0x08 },
89 { 32000, 0x10 },
90 { 8000, 0x20 },
91 { 4000, 0x40 },
92};
93
94static const struct nau8825_fll_attr fll_pre_scalar[] = {
95 { 1, 0x0 },
96 { 2, 0x1 },
97 { 4, 0x2 },
98 { 8, 0x3 },
99};
100
101/* over sampling rate */
102struct nau8825_osr_attr {
103 unsigned int osr;
104 unsigned int clk_src;
105};
106
107static const struct nau8825_osr_attr osr_dac_sel[] = {
108 { 64, 2 }, /* OSR 64, SRC 1/4 */
109 { 256, 0 }, /* OSR 256, SRC 1 */
110 { 128, 1 }, /* OSR 128, SRC 1/2 */
111 { 0, 0 },
112 { 32, 3 }, /* OSR 32, SRC 1/8 */
113};
114
115static const struct nau8825_osr_attr osr_adc_sel[] = {
116 { 32, 3 }, /* OSR 32, SRC 1/8 */
117 { 64, 2 }, /* OSR 64, SRC 1/4 */
118 { 128, 1 }, /* OSR 128, SRC 1/2 */
119 { 256, 0 }, /* OSR 256, SRC 1 */
120};
121
122static const struct reg_default nau8825_reg_defaults[] = {
123 { NAU8825_REG_ENA_CTRL, 0x00ff },
124 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
125 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
126 { NAU8825_REG_FLL1, 0x0 },
127 { NAU8825_REG_FLL2, 0x3126 },
128 { NAU8825_REG_FLL3, 0x0008 },
129 { NAU8825_REG_FLL4, 0x0010 },
130 { NAU8825_REG_FLL5, 0x0 },
131 { NAU8825_REG_FLL6, 0x6000 },
132 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
133 { NAU8825_REG_HSD_CTRL, 0x000c },
134 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
135 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
136 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
137 { NAU8825_REG_SAR_CTRL, 0x0015 },
138 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
139 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
140 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
141 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
142 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
143 { NAU8825_REG_GPIO34_CTRL, 0x0 },
144 { NAU8825_REG_GPIO12_CTRL, 0x0 },
145 { NAU8825_REG_TDM_CTRL, 0x0 },
146 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
147 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
148 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
149 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
150 { NAU8825_REG_BIQ_CTRL, 0x0 },
151 { NAU8825_REG_BIQ_COF1, 0x0 },
152 { NAU8825_REG_BIQ_COF2, 0x0 },
153 { NAU8825_REG_BIQ_COF3, 0x0 },
154 { NAU8825_REG_BIQ_COF4, 0x0 },
155 { NAU8825_REG_BIQ_COF5, 0x0 },
156 { NAU8825_REG_BIQ_COF6, 0x0 },
157 { NAU8825_REG_BIQ_COF7, 0x0 },
158 { NAU8825_REG_BIQ_COF8, 0x0 },
159 { NAU8825_REG_BIQ_COF9, 0x0 },
160 { NAU8825_REG_BIQ_COF10, 0x0 },
161 { NAU8825_REG_ADC_RATE, 0x0010 },
162 { NAU8825_REG_DAC_CTRL1, 0x0001 },
163 { NAU8825_REG_DAC_CTRL2, 0x0 },
164 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
165 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
166 { NAU8825_REG_MUTE_CTRL, 0x0 },
167 { NAU8825_REG_HSVOL_CTRL, 0x0 },
168 { NAU8825_REG_DACL_CTRL, 0x02cf },
169 { NAU8825_REG_DACR_CTRL, 0x00cf },
170 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
171 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
172 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
173 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
174 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
175 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
176 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
177 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
178 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
179 { NAU8825_REG_CLASSG_CTRL, 0x0 },
180 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
181 { NAU8825_REG_MISC_CTRL, 0x0 },
182 { NAU8825_REG_FLL2_LOWER, 0x0 },
183 { NAU8825_REG_FLL2_UPPER, 0x0 },
184 { NAU8825_REG_BIAS_ADJ, 0x0 },
185 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
186 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
187 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
188 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
189 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
190 { NAU8825_REG_RDAC, 0x0008 },
191 { NAU8825_REG_MIC_BIAS, 0x0006 },
192 { NAU8825_REG_BOOST, 0x0 },
193 { NAU8825_REG_FEPGA, 0x0 },
194 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
195 { NAU8825_REG_CHARGE_PUMP, 0x0 },
196};
197
198/* register backup table when cross talk detection */
199static struct reg_default nau8825_xtalk_baktab[] = {
200 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
201 { NAU8825_REG_HSVOL_CTRL, 0 },
202 { NAU8825_REG_DACL_CTRL, 0x00cf },
203 { NAU8825_REG_DACR_CTRL, 0x02cf },
204};
205
206/* The regmap patch for Rev C */
207static const struct reg_sequence nau8825_regmap_patch[] = {
208 { NAU8825_REG_FLL2, 0x0000 },
209 { NAU8825_REG_FLL4, 0x8010 },
210 { NAU8825_REG_FLL_VCO_RSV, 0x0bc0 },
211 { NAU8825_REG_INTERRUPT_MASK, 0x0800 },
212 { NAU8825_REG_DACL_CTRL, 0x00cf },
213 { NAU8825_REG_DACR_CTRL, 0x02cf },
214 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0400 },
215 { NAU8825_REG_FLL2_LOWER, 0x26e9 },
216 { NAU8825_REG_FLL2_UPPER, 0x0031 },
217 { NAU8825_REG_ANALOG_CONTROL_2, 0x0020 },
218 { NAU8825_REG_ANALOG_ADC_2, 0x0220 },
219 { NAU8825_REG_MIC_BIAS, 0x0046 },
220};
221
222/**
223 * nau8825_sema_acquire - acquire the semaphore of nau88l25
224 * @nau8825: component to register the codec private data with
225 * @timeout: how long in jiffies to wait before failure or zero to wait
226 * until release
227 *
228 * Attempts to acquire the semaphore with number of jiffies. If no more
229 * tasks are allowed to acquire the semaphore, calling this function will
230 * put the task to sleep. If the semaphore is not released within the
231 * specified number of jiffies, this function returns.
232 * If the semaphore is not released within the specified number of jiffies,
233 * this function returns -ETIME. If the sleep is interrupted by a signal,
234 * this function will return -EINTR. It returns 0 if the semaphore was
235 * acquired successfully.
236 *
237 * Acquires the semaphore without jiffies. Try to acquire the semaphore
238 * atomically. Returns 0 if the semaphore has been acquired successfully
239 * or 1 if it cannot be acquired.
240 */
241static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
242{
243 int ret;
244
245 if (timeout) {
246 ret = down_timeout(&nau8825->xtalk_sem, timeout);
247 if (ret < 0)
248 dev_warn(nau8825->dev, "Acquire semaphore timeout\n");
249 } else {
250 ret = down_trylock(&nau8825->xtalk_sem);
251 if (ret)
252 dev_warn(nau8825->dev, "Acquire semaphore fail\n");
253 }
254
255 return ret;
256}
257
258/**
259 * nau8825_sema_release - release the semaphore of nau88l25
260 * @nau8825: component to register the codec private data with
261 *
262 * Release the semaphore which may be called from any context and
263 * even by tasks which have never called down().
264 */
265static inline void nau8825_sema_release(struct nau8825 *nau8825)
266{
267 up(&nau8825->xtalk_sem);
268}
269
270/**
271 * nau8825_sema_reset - reset the semaphore for nau88l25
272 * @nau8825: component to register the codec private data with
273 *
274 * Reset the counter of the semaphore. Call this function to restart
275 * a new round task management.
276 */
277static inline void nau8825_sema_reset(struct nau8825 *nau8825)
278{
279 nau8825->xtalk_sem.count = 1;
280}
281
282/**
283 * nau8825_hpvol_ramp - Ramp up the headphone volume change gradually to target level.
284 *
285 * @nau8825: component to register the codec private data with
286 * @vol_from: the volume to start up
287 * @vol_to: the target volume
288 * @step: the volume span to move on
289 *
290 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
291 * If the volume changes sharp, there is a pop noise heard in headphone. We
292 * provide the function to ramp up the volume up or down by delaying 10ms
293 * per step.
294 */
295static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
296 unsigned int vol_from, unsigned int vol_to, unsigned int step)
297{
298 unsigned int value, volume, ramp_up, from, to;
299
300 if (vol_from == vol_to || step == 0) {
301 return;
302 } else if (vol_from < vol_to) {
303 ramp_up = true;
304 from = vol_from;
305 to = vol_to;
306 } else {
307 ramp_up = false;
308 from = vol_to;
309 to = vol_from;
310 }
311 /* only handle volume from 0dB to minimum -54dB */
312 if (to > NAU8825_HP_VOL_MIN)
313 to = NAU8825_HP_VOL_MIN;
314
315 for (volume = from; volume < to; volume += step) {
316 if (ramp_up)
317 value = volume;
318 else
319 value = to - volume + from;
320 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
321 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
322 (value << NAU8825_HPL_VOL_SFT) | value);
323 usleep_range(10000, 10500);
324 }
325 if (ramp_up)
326 value = to;
327 else
328 value = from;
329 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
330 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
331 (value << NAU8825_HPL_VOL_SFT) | value);
332}
333
334/**
335 * nau8825_intlog10_dec3 - Computes log10 of a value, rounding the result to 3 decimal places.
336 * @value: input for log10
337 *
338 * return log10(value) * 1000
339 */
340static u32 nau8825_intlog10_dec3(u32 value)
341{
342 return intlog10(value) / ((1 << 24) / 1000);
343}
344
345/**
346 * nau8825_xtalk_sidetone - computes cross talk suppression sidetone gain.
347 *
348 * @sig_org: orignal signal level
349 * @sig_cros: cross talk signal level
350 *
351 * The orignal and cross talk signal vlues need to be characterized.
352 * Once these values have been characterized, this sidetone value
353 * can be converted to decibel with the equation below.
354 * sidetone = 20 * log (original signal level / crosstalk signal level)
355 *
356 * return cross talk sidetone gain
357 */
358static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
359{
360 u32 gain, sidetone;
361
362 if (WARN_ON(sig_org == 0 || sig_cros == 0))
363 return 0;
364
365 sig_org = nau8825_intlog10_dec3(sig_org);
366 sig_cros = nau8825_intlog10_dec3(sig_cros);
367 if (sig_org >= sig_cros)
368 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
369 else
370 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
371 sidetone = SIDETONE_BASE - gain * 2;
372 sidetone /= 1000;
373
374 return sidetone;
375}
376
377static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
378{
379 int index;
380
381 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
382 if (nau8825_xtalk_baktab[index].reg == reg)
383 return index;
384 return -EINVAL;
385}
386
387static void nau8825_xtalk_backup(struct nau8825 *nau8825)
388{
389 int i;
390
391 if (nau8825->xtalk_baktab_initialized)
392 return;
393
394 /* Backup some register values to backup table */
395 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
396 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
397 &nau8825_xtalk_baktab[i].def);
398
399 nau8825->xtalk_baktab_initialized = true;
400}
401
402static void nau8825_xtalk_restore(struct nau8825 *nau8825, bool cause_cancel)
403{
404 int i, volume;
405
406 if (!nau8825->xtalk_baktab_initialized)
407 return;
408
409 /* Restore register values from backup table; When the driver restores
410 * the headphone volume in XTALK_DONE state, it needs recover to
411 * original level gradually with 3dB per step for less pop noise.
412 * Otherwise, the restore should do ASAP.
413 */
414 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
415 if (!cause_cancel && nau8825_xtalk_baktab[i].reg ==
416 NAU8825_REG_HSVOL_CTRL) {
417 /* Ramping up the volume change to reduce pop noise */
418 volume = nau8825_xtalk_baktab[i].def &
419 NAU8825_HPR_VOL_MASK;
420 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
421 continue;
422 }
423 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
424 nau8825_xtalk_baktab[i].def);
425 }
426
427 nau8825->xtalk_baktab_initialized = false;
428}
429
430static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
431{
432 /* Enable power of DAC path */
433 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
434 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
435 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
436 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
437 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
438 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
439 /* Prevent startup click by letting charge pump to ramp up and
440 * change bump enable
441 */
442 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
443 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
444 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
445 /* Enable clock sync of DAC and DAC clock */
446 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
447 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
448 NAU8825_RDAC_FS_BCLK_ENB,
449 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
450 /* Power up output driver with 2 stage */
451 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
452 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
453 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
454 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
455 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
456 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
457 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
458 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
459 /* HP outputs not shouted to ground */
460 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
461 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
462 /* Enable HP boost driver */
463 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
464 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
465 /* Enable class G compare path to supply 1.8V or 0.9V. */
466 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
467 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
468 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
469}
470
471static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
472{
473 /* Power up left ADC and raise 5dB than Vmid for Vref */
474 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
475 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
476 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
477}
478
479static void nau8825_xtalk_clock(struct nau8825 *nau8825)
480{
481 /* Recover FLL default value */
482 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
483 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
484 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
485 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
486 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
487 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
488 /* Enable internal VCO clock for detection signal generated */
489 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
490 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
491 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
492 NAU8825_DCO_EN);
493 /* Given specific clock frequency of internal clock to
494 * generate signal.
495 */
496 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
497 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
498 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
499 NAU8825_FLL_RATIO_MASK, 0x10);
500}
501
502static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
503{
504 int volume, index;
505
506 /* Backup those registers changed by cross talk detection */
507 nau8825_xtalk_backup(nau8825);
508 /* Config IIS as master to output signal by codec */
509 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
510 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
511 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
512 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
513 /* Ramp up headphone volume to 0dB to get better performance and
514 * avoid pop noise in headphone.
515 */
516 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
517 if (index != -EINVAL) {
518 volume = nau8825_xtalk_baktab[index].def &
519 NAU8825_HPR_VOL_MASK;
520 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
521 }
522 nau8825_xtalk_clock(nau8825);
523 nau8825_xtalk_prepare_dac(nau8825);
524 nau8825_xtalk_prepare_adc(nau8825);
525 /* Config channel path and digital gain */
526 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
527 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
528 NAU8825_DACL_CH_SEL_L | 0xab);
529 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
530 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
531 NAU8825_DACR_CH_SEL_R | 0xab);
532 /* Config cross talk parameters and generate the 23Hz sine wave with
533 * 1/16 full scale of signal level for impedance measurement.
534 */
535 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
536 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
537 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
538 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
539 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
540 /* RMS intrruption enable */
541 regmap_update_bits(nau8825->regmap,
542 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
543 /* Power up left and right DAC */
544 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
545 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
546 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
547 else
548 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
549 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
550 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
551}
552
553static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
554{
555 /* Disable HP boost driver */
556 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
557 NAU8825_HP_BOOST_DIS, 0);
558 /* HP outputs shouted to ground */
559 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
560 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
561 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
562 /* Power down left and right DAC */
563 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
564 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
565 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
566 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
567 else
568 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
569 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
570
571 /* Enable the TESTDAC and disable L/R HP impedance */
572 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
573 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
574 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
575 /* Power down output driver with 2 stage */
576 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
577 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
578 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
579 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
580 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
581 /* Disable clock sync of DAC and DAC clock */
582 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
583 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
584 /* Disable charge pump ramp up function and change bump */
585 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
586 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
587 /* Disable power of DAC path */
588 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
589 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
590 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
591 if (!nau8825->irq)
592 regmap_update_bits(nau8825->regmap,
593 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
594}
595
596static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
597{
598 /* Power down left ADC and restore voltage to Vmid */
599 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
600 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
601}
602
603static void nau8825_xtalk_clean(struct nau8825 *nau8825, bool cause_cancel)
604{
605 /* Enable internal VCO needed for interruptions */
606 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
607 nau8825_xtalk_clean_dac(nau8825);
608 nau8825_xtalk_clean_adc(nau8825);
609 /* Clear cross talk parameters and disable */
610 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
611 /* RMS intrruption disable */
612 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
613 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
614 /* Recover default value for IIS */
615 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
616 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
617 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
618 /* Restore value of specific register for cross talk */
619 nau8825_xtalk_restore(nau8825, cause_cancel);
620}
621
622static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
623{
624 /* Apply ADC volume for better cross talk performance */
625 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
626 NAU8825_ADC_DIG_VOL_MASK, vol);
627 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
628 * Do it before sending signal in order to erase pop noise.
629 */
630 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
631 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
632 NAU8825_BIAS_TESTDACL_EN);
633 switch (nau8825->xtalk_state) {
634 case NAU8825_XTALK_HPR_R2L:
635 /* Enable right headphone impedance */
636 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
637 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
638 NAU8825_BIAS_HPR_IMP);
639 break;
640 case NAU8825_XTALK_HPL_R2L:
641 /* Enable left headphone impedance */
642 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
643 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
644 NAU8825_BIAS_HPL_IMP);
645 break;
646 default:
647 break;
648 }
649 msleep(100);
650 /* Impedance measurement mode enable */
651 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
652 NAU8825_IMM_EN, NAU8825_IMM_EN);
653}
654
655static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
656{
657 /* Impedance measurement mode disable */
658 regmap_update_bits(nau8825->regmap,
659 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
660}
661
662/* The cross talk measurement function can reduce cross talk across the
663 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
664 * level to determine what cross talk reduction gain is. This system works by
665 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
666 * the PGA. The output of the PGA is then connected to an internal current
667 * sense which measures the attenuated 23Hz signal and passing the output to
668 * an ADC which converts the measurement to a binary code. With two separated
669 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
670 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
671 * Thus, the measurement function has four states to complete whole sequence.
672 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
673 * IMM stat to make JKR1(HPR) impedance measure.
674 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
675 * to HPL IMM state to make JKTIP(HPL) impedance measure.
676 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
677 * transfer to IMM state to determine suppression sidetone gain.
678 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
679 * and cross talk signal level. Apply this gain and then restore codec
680 * configuration. Then transfer to Done state for ending.
681 */
682static void nau8825_xtalk_measure(struct nau8825 *nau8825)
683{
684 u32 sidetone;
685
686 switch (nau8825->xtalk_state) {
687 case NAU8825_XTALK_PREPARE:
688 /* In prepare state, set up clock, intrruption, DAC path, ADC
689 * path and cross talk detection parameters for preparation.
690 */
691 nau8825_xtalk_prepare(nau8825);
692 msleep(280);
693 /* Trigger right headphone impedance detection */
694 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
695 nau8825_xtalk_imm_start(nau8825, 0x00d2);
696 break;
697 case NAU8825_XTALK_HPR_R2L:
698 /* In right headphone IMM state, read out right headphone
699 * impedance measure result, and then start up left side.
700 */
701 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
702 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
703 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
704 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
705 /* Disable then re-enable IMM mode to update */
706 nau8825_xtalk_imm_stop(nau8825);
707 /* Trigger left headphone impedance detection */
708 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
709 nau8825_xtalk_imm_start(nau8825, 0x00ff);
710 break;
711 case NAU8825_XTALK_HPL_R2L:
712 /* In left headphone IMM state, read out left headphone
713 * impedance measure result, and delay some time to wait
714 * detection sine wave output finish. Then, we can calculate
715 * the cross talk suppresstion side tone according to the L/R
716 * headphone imedance.
717 */
718 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
719 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
720 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
721 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
722 nau8825_xtalk_imm_stop(nau8825);
723 msleep(150);
724 nau8825->xtalk_state = NAU8825_XTALK_IMM;
725 break;
726 case NAU8825_XTALK_IMM:
727 /* In impedance measure state, the orignal and cross talk
728 * signal level vlues are ready. The side tone gain is deter-
729 * mined with these signal level. After all, restore codec
730 * configuration.
731 */
732 sidetone = nau8825_xtalk_sidetone(
733 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
734 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
735 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
736 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
737 (sidetone << 8) | sidetone);
738 nau8825_xtalk_clean(nau8825, false);
739 nau8825->xtalk_state = NAU8825_XTALK_DONE;
740 break;
741 default:
742 break;
743 }
744}
745
746static void nau8825_xtalk_work(struct work_struct *work)
747{
748 struct nau8825 *nau8825 = container_of(
749 work, struct nau8825, xtalk_work);
750
751 nau8825_xtalk_measure(nau8825);
752 /* To determine the cross talk side tone gain when reach
753 * the impedance measure state.
754 */
755 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
756 nau8825_xtalk_measure(nau8825);
757
758 /* Delay jack report until cross talk detection process
759 * completed. It can avoid application to do playback
760 * preparation before cross talk detection is still working.
761 * Meanwhile, the protection of the cross talk detection
762 * is released.
763 */
764 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
765 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
766 nau8825->xtalk_event_mask);
767 nau8825_sema_release(nau8825);
768 nau8825->xtalk_protect = false;
769 }
770}
771
772static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
773{
774 /* If the crosstalk is eanbled and the process is on going,
775 * the driver forces to cancel the crosstalk task and
776 * restores the configuration to original status.
777 */
778 if (nau8825->xtalk_enable && nau8825->xtalk_state !=
779 NAU8825_XTALK_DONE) {
780 cancel_work_sync(&nau8825->xtalk_work);
781 nau8825_xtalk_clean(nau8825, true);
782 }
783 /* Reset parameters for cross talk suppression function */
784 nau8825_sema_reset(nau8825);
785 nau8825->xtalk_state = NAU8825_XTALK_DONE;
786 nau8825->xtalk_protect = false;
787}
788
789static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
790{
791 switch (reg) {
792 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
793 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
794 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
795 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
796 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
797 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
798 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
799 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
800 case NAU8825_REG_MISC_CTRL:
801 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_FLL2_UPPER:
802 case NAU8825_REG_BIAS_ADJ:
803 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
804 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
805 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
806 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
807 return true;
808 default:
809 return false;
810 }
811
812}
813
814static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
815{
816 switch (reg) {
817 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
818 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
819 case NAU8825_REG_INTERRUPT_MASK:
820 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
821 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
822 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
823 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
824 case NAU8825_REG_IMM_MODE_CTRL:
825 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
826 case NAU8825_REG_MISC_CTRL:
827 case NAU8825_REG_FLL2_LOWER ... NAU8825_REG_FLL2_UPPER:
828 case NAU8825_REG_BIAS_ADJ:
829 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
830 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
831 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
832 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
833 return true;
834 default:
835 return false;
836 }
837}
838
839static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
840{
841 switch (reg) {
842 case NAU8825_REG_RESET:
843 case NAU8825_REG_IRQ_STATUS:
844 case NAU8825_REG_INT_CLR_KEY_STATUS:
845 case NAU8825_REG_IMM_RMS_L:
846 case NAU8825_REG_IMM_RMS_R:
847 case NAU8825_REG_I2C_DEVICE_ID:
848 case NAU8825_REG_SARDOUT_RAM_STATUS:
849 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
850 case NAU8825_REG_GENERAL_STATUS:
851 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
852 return true;
853 default:
854 return false;
855 }
856}
857
858static int nau8825_fepga_event(struct snd_soc_dapm_widget *w,
859 struct snd_kcontrol *kcontrol, int event)
860{
861 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
862 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
863
864 switch (event) {
865 case SND_SOC_DAPM_POST_PMU:
866 regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA,
867 NAU8825_ACDC_CTRL_MASK,
868 NAU8825_ACDC_VREF_MICP | NAU8825_ACDC_VREF_MICN);
869 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
870 NAU8825_DISCHRG_EN, NAU8825_DISCHRG_EN);
871 msleep(40);
872 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
873 NAU8825_DISCHRG_EN, 0);
874 regmap_update_bits(nau8825->regmap, NAU8825_REG_FEPGA,
875 NAU8825_ACDC_CTRL_MASK, 0);
876 break;
877 default:
878 break;
879 }
880
881 return 0;
882}
883
884static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
885 struct snd_kcontrol *kcontrol, int event)
886{
887 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
888 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
889
890 switch (event) {
891 case SND_SOC_DAPM_POST_PMU:
892 msleep(nau8825->adc_delay);
893 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
894 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
895 break;
896 case SND_SOC_DAPM_POST_PMD:
897 if (!nau8825->irq)
898 regmap_update_bits(nau8825->regmap,
899 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
900 break;
901 default:
902 return -EINVAL;
903 }
904
905 return 0;
906}
907
908static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
909 struct snd_kcontrol *kcontrol, int event)
910{
911 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
912 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
913
914 switch (event) {
915 case SND_SOC_DAPM_POST_PMU:
916 /* Prevent startup click by letting charge pump to ramp up */
917 msleep(10);
918 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
919 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
920 break;
921 case SND_SOC_DAPM_PRE_PMD:
922 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
923 NAU8825_JAMNODCLOW, 0);
924 break;
925 default:
926 return -EINVAL;
927 }
928
929 return 0;
930}
931
932static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
933 struct snd_kcontrol *kcontrol, int event)
934{
935 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
936 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
937
938 switch (event) {
939 case SND_SOC_DAPM_PRE_PMU:
940 /* Disables the TESTDAC to let DAC signal pass through. */
941 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
942 NAU8825_BIAS_TESTDAC_EN, 0);
943 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
944 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
945 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
946 else
947 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
948 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
949 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
950 break;
951 case SND_SOC_DAPM_POST_PMD:
952 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
953 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
954 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
955 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
956 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
957 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
958 else
959 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
960 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
961
962 break;
963 default:
964 return -EINVAL;
965 }
966
967 return 0;
968}
969
970static int system_clock_control(struct snd_soc_dapm_widget *w,
971 struct snd_kcontrol *k, int event)
972{
973 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
974 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
975 struct regmap *regmap = nau8825->regmap;
976
977 if (SND_SOC_DAPM_EVENT_OFF(event)) {
978 dev_dbg(nau8825->dev, "system clock control : POWER OFF\n");
979 /* Set clock source to disable or internal clock before the
980 * playback or capture end. Codec needs clock for Jack
981 * detection and button press if jack inserted; otherwise,
982 * the clock should be closed.
983 */
984 if (nau8825_is_jack_inserted(regmap)) {
985 nau8825_configure_sysclk(nau8825,
986 NAU8825_CLK_INTERNAL, 0);
987 } else {
988 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
989 }
990 }
991
992 return 0;
993}
994
995static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
996 struct snd_ctl_elem_value *ucontrol)
997{
998 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
999 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
1000
1001 if (!component->regmap)
1002 return -EINVAL;
1003
1004 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
1005 ucontrol->value.bytes.data, params->max);
1006 return 0;
1007}
1008
1009static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
1010 struct snd_ctl_elem_value *ucontrol)
1011{
1012 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1013 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
1014 void *data;
1015
1016 if (!component->regmap)
1017 return -EINVAL;
1018
1019 data = kmemdup(ucontrol->value.bytes.data,
1020 params->max, GFP_KERNEL | GFP_DMA);
1021 if (!data)
1022 return -ENOMEM;
1023
1024 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1025 NAU8825_BIQ_WRT_EN, 0);
1026 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
1027 data, params->max);
1028 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1029 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
1030
1031 kfree(data);
1032 return 0;
1033}
1034
1035static const char * const nau8825_biq_path[] = {
1036 "ADC", "DAC"
1037};
1038
1039static const struct soc_enum nau8825_biq_path_enum =
1040 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
1041 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
1042
1043static const char * const nau8825_adc_decimation[] = {
1044 "32", "64", "128", "256"
1045};
1046
1047static const struct soc_enum nau8825_adc_decimation_enum =
1048 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1049 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1050
1051static const char * const nau8825_dac_oversampl[] = {
1052 "64", "256", "128", "", "32"
1053};
1054
1055static const struct soc_enum nau8825_dac_oversampl_enum =
1056 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1057 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1058
1059static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1060static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1061static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1062static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1063static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1064
1065static const struct snd_kcontrol_new nau8825_controls[] = {
1066 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1067 0, 0xff, 0, adc_vol_tlv),
1068 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1069 12, 8, 0x0f, 0, sidetone_vol_tlv),
1070 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1071 6, 0, 0x3f, 1, dac_vol_tlv),
1072 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1073 8, 37, 0, fepga_gain_tlv),
1074 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1075 0, 8, 0xff, 0, crosstalk_vol_tlv),
1076
1077 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1078 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1079 /* programmable biquad filter */
1080 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1081 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1082 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1083};
1084
1085/* DAC Mux 0x33[9] and 0x34[9] */
1086static const char * const nau8825_dac_src[] = {
1087 "DACL", "DACR",
1088};
1089
1090static SOC_ENUM_SINGLE_DECL(
1091 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1092 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1093
1094static SOC_ENUM_SINGLE_DECL(
1095 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1096 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1097
1098static const struct snd_kcontrol_new nau8825_dacl_mux =
1099 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1100
1101static const struct snd_kcontrol_new nau8825_dacr_mux =
1102 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1103
1104
1105static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1106 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1107 15, 1),
1108 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
1109 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
1110 system_clock_control, SND_SOC_DAPM_POST_PMD),
1111
1112 SND_SOC_DAPM_INPUT("MIC"),
1113 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1114
1115 SND_SOC_DAPM_PGA_E("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1116 NULL, 0, nau8825_fepga_event, SND_SOC_DAPM_POST_PMU),
1117
1118 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1119 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1120 SND_SOC_DAPM_POST_PMD),
1121 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1122 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1123 0),
1124
1125 /* ADC for button press detection. A dapm supply widget is used to
1126 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1127 * during suspend.
1128 */
1129 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1130 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1131
1132 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1133 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1134 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1135 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1136
1137 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1138 NAU8825_ENABLE_DACR_SFT, 0),
1139 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1140 NAU8825_ENABLE_DACL_SFT, 0),
1141 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1142
1143 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1144 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1145
1146 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1147 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1148 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1149 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1150
1151 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1152 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1153 SND_SOC_DAPM_PRE_PMD),
1154
1155 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1156 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1157 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1158 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1159 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1160 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1161 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1162 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1163 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1164 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1165 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1166 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1167
1168 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1169 SND_SOC_NOPM, 0, 0, nau8825_output_dac_event,
1170 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1171 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1172 SND_SOC_NOPM, 0, 0, nau8825_output_dac_event,
1173 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1174
1175
1176 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1177 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1178 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1179 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1180 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1181
1182 /* High current HPOL/R boost driver */
1183 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1184 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1185
1186 /* Class G operation control*/
1187 SND_SOC_DAPM_PGA_S("Class G", 10,
1188 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1189
1190 SND_SOC_DAPM_OUTPUT("HPOL"),
1191 SND_SOC_DAPM_OUTPUT("HPOR"),
1192};
1193
1194static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1195 {"Frontend PGA", NULL, "MIC"},
1196 {"ADC", NULL, "Frontend PGA"},
1197 {"ADC", NULL, "ADC Clock"},
1198 {"ADC", NULL, "ADC Power"},
1199 {"AIFTX", NULL, "ADC"},
1200 {"AIFTX", NULL, "System Clock"},
1201
1202 {"AIFRX", NULL, "System Clock"},
1203 {"DDACL", NULL, "AIFRX"},
1204 {"DDACR", NULL, "AIFRX"},
1205 {"DDACL", NULL, "DDAC Clock"},
1206 {"DDACR", NULL, "DDAC Clock"},
1207 {"DACL Mux", "DACL", "DDACL"},
1208 {"DACL Mux", "DACR", "DDACR"},
1209 {"DACR Mux", "DACL", "DDACL"},
1210 {"DACR Mux", "DACR", "DDACR"},
1211 {"HP amp L", NULL, "DACL Mux"},
1212 {"HP amp R", NULL, "DACR Mux"},
1213 {"Charge Pump", NULL, "HP amp L"},
1214 {"Charge Pump", NULL, "HP amp R"},
1215 {"ADACL", NULL, "Charge Pump"},
1216 {"ADACR", NULL, "Charge Pump"},
1217 {"ADACL Clock", NULL, "ADACL"},
1218 {"ADACR Clock", NULL, "ADACR"},
1219 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1220 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1221 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1222 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1223 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1224 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1225 {"Output DACL", NULL, "Output Driver L Stage 3"},
1226 {"Output DACR", NULL, "Output Driver R Stage 3"},
1227 {"HPOL Pulldown", NULL, "Output DACL"},
1228 {"HPOR Pulldown", NULL, "Output DACR"},
1229 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1230 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1231 {"Class G", NULL, "HP Boost Driver"},
1232 {"HPOL", NULL, "Class G"},
1233 {"HPOR", NULL, "Class G"},
1234};
1235
1236static const struct nau8825_osr_attr *
1237nau8825_get_osr(struct nau8825 *nau8825, int stream)
1238{
1239 unsigned int osr;
1240
1241 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1242 regmap_read(nau8825->regmap,
1243 NAU8825_REG_DAC_CTRL1, &osr);
1244 osr &= NAU8825_DAC_OVERSAMPLE_MASK;
1245 if (osr >= ARRAY_SIZE(osr_dac_sel))
1246 return NULL;
1247 return &osr_dac_sel[osr];
1248 } else {
1249 regmap_read(nau8825->regmap,
1250 NAU8825_REG_ADC_RATE, &osr);
1251 osr &= NAU8825_ADC_SYNC_DOWN_MASK;
1252 if (osr >= ARRAY_SIZE(osr_adc_sel))
1253 return NULL;
1254 return &osr_adc_sel[osr];
1255 }
1256}
1257
1258static int nau8825_dai_startup(struct snd_pcm_substream *substream,
1259 struct snd_soc_dai *dai)
1260{
1261 struct snd_soc_component *component = dai->component;
1262 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1263 const struct nau8825_osr_attr *osr;
1264
1265 osr = nau8825_get_osr(nau8825, substream->stream);
1266 if (!osr || !osr->osr)
1267 return -EINVAL;
1268
1269 return snd_pcm_hw_constraint_minmax(substream->runtime,
1270 SNDRV_PCM_HW_PARAM_RATE,
1271 0, CLK_DA_AD_MAX / osr->osr);
1272}
1273
1274static int nau8825_hw_params(struct snd_pcm_substream *substream,
1275 struct snd_pcm_hw_params *params,
1276 struct snd_soc_dai *dai)
1277{
1278 struct snd_soc_component *component = dai->component;
1279 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1280 unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div;
1281 const struct nau8825_osr_attr *osr;
1282 int err = -EINVAL;
1283
1284 nau8825_sema_acquire(nau8825, 3 * HZ);
1285
1286 /* CLK_DAC or CLK_ADC = OSR * FS
1287 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1288 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1289 * values must be selected such that the maximum frequency is less
1290 * than 6.144 MHz.
1291 */
1292 osr = nau8825_get_osr(nau8825, substream->stream);
1293 if (!osr || !osr->osr)
1294 goto error;
1295 if (params_rate(params) * osr->osr > CLK_DA_AD_MAX)
1296 goto error;
1297 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1298 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1299 NAU8825_CLK_DAC_SRC_MASK,
1300 osr->clk_src << NAU8825_CLK_DAC_SRC_SFT);
1301 else
1302 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1303 NAU8825_CLK_ADC_SRC_MASK,
1304 osr->clk_src << NAU8825_CLK_ADC_SRC_SFT);
1305
1306 /* make BCLK and LRC divde configuration if the codec as master. */
1307 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2, &ctrl_val);
1308 if (ctrl_val & NAU8825_I2S_MS_MASTER) {
1309 /* get the bclk and fs ratio */
1310 bclk_fs = snd_soc_params_to_bclk(params) / params_rate(params);
1311 if (bclk_fs <= 32)
1312 bclk_div = 2;
1313 else if (bclk_fs <= 64)
1314 bclk_div = 1;
1315 else if (bclk_fs <= 128)
1316 bclk_div = 0;
1317 else
1318 goto error;
1319 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1320 NAU8825_I2S_LRC_DIV_MASK | NAU8825_I2S_BLK_DIV_MASK,
1321 ((bclk_div + 1) << NAU8825_I2S_LRC_DIV_SFT) | bclk_div);
1322 }
1323
1324 switch (params_width(params)) {
1325 case 16:
1326 val_len |= NAU8825_I2S_DL_16;
1327 break;
1328 case 20:
1329 val_len |= NAU8825_I2S_DL_20;
1330 break;
1331 case 24:
1332 val_len |= NAU8825_I2S_DL_24;
1333 break;
1334 case 32:
1335 val_len |= NAU8825_I2S_DL_32;
1336 break;
1337 default:
1338 goto error;
1339 }
1340
1341 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1342 NAU8825_I2S_DL_MASK, val_len);
1343 err = 0;
1344
1345 error:
1346 /* Release the semaphore. */
1347 nau8825_sema_release(nau8825);
1348
1349 return err;
1350}
1351
1352static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1353{
1354 struct snd_soc_component *component = codec_dai->component;
1355 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1356 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1357
1358 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1359 case SND_SOC_DAIFMT_CBM_CFM:
1360 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1361 break;
1362 case SND_SOC_DAIFMT_CBS_CFS:
1363 break;
1364 default:
1365 return -EINVAL;
1366 }
1367
1368 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1369 case SND_SOC_DAIFMT_NB_NF:
1370 break;
1371 case SND_SOC_DAIFMT_IB_NF:
1372 ctrl1_val |= NAU8825_I2S_BP_INV;
1373 break;
1374 default:
1375 return -EINVAL;
1376 }
1377
1378 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1379 case SND_SOC_DAIFMT_I2S:
1380 ctrl1_val |= NAU8825_I2S_DF_I2S;
1381 break;
1382 case SND_SOC_DAIFMT_LEFT_J:
1383 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1384 break;
1385 case SND_SOC_DAIFMT_RIGHT_J:
1386 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1387 break;
1388 case SND_SOC_DAIFMT_DSP_A:
1389 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1390 break;
1391 case SND_SOC_DAIFMT_DSP_B:
1392 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1393 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1394 break;
1395 default:
1396 return -EINVAL;
1397 }
1398
1399 nau8825_sema_acquire(nau8825, 3 * HZ);
1400
1401 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1402 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1403 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1404 ctrl1_val);
1405 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1406 NAU8825_I2S_MS_MASK, ctrl2_val);
1407
1408 /* Release the semaphore. */
1409 nau8825_sema_release(nau8825);
1410
1411 return 0;
1412}
1413
1414/**
1415 * nau8825_set_tdm_slot - configure DAI TDM.
1416 * @dai: DAI
1417 * @tx_mask: bitmask representing active TX slots.
1418 * @rx_mask: bitmask representing active RX slots.
1419 * @slots: Number of slots in use.
1420 * @slot_width: Width in bits for each slot.
1421 *
1422 * Configures a DAI for TDM operation. Support TDM 4/8 slots.
1423 * The limitation is DAC and ADC need shift 4 slots at 8 slots mode.
1424 */
1425static int nau8825_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
1426 unsigned int rx_mask, int slots, int slot_width)
1427{
1428 struct snd_soc_component *component = dai->component;
1429 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1430 unsigned int ctrl_val = 0, ctrl_offset = 0, value = 0, dac_s, adc_s;
1431
1432 if (slots != 4 && slots != 8) {
1433 dev_err(nau8825->dev, "Only support 4 or 8 slots!\n");
1434 return -EINVAL;
1435 }
1436
1437 /* The driver is limited to 1-channel for ADC, and 2-channel for DAC on TDM mode */
1438 if (hweight_long((unsigned long) tx_mask) != 1 ||
1439 hweight_long((unsigned long) rx_mask) != 2) {
1440 dev_err(nau8825->dev,
1441 "The limitation is 1-channel for ADC, and 2-channel for DAC on TDM mode.\n");
1442 return -EINVAL;
1443 }
1444
1445 if (((tx_mask & 0xf) && (tx_mask & 0xf0)) ||
1446 ((rx_mask & 0xf) && (rx_mask & 0xf0)) ||
1447 ((tx_mask & 0xf) && (rx_mask & 0xf0)) ||
1448 ((rx_mask & 0xf) && (tx_mask & 0xf0))) {
1449 dev_err(nau8825->dev,
1450 "Slot assignment of DAC and ADC need to set same interval.\n");
1451 return -EINVAL;
1452 }
1453
1454 /* The offset of fixed 4 slots for 8 slots support */
1455 if (rx_mask & 0xf0) {
1456 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1457 NAU8825_I2S_PCM_TS_EN_MASK, NAU8825_I2S_PCM_TS_EN);
1458 regmap_read(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1, &value);
1459 ctrl_val |= NAU8825_TDM_OFFSET_EN;
1460 ctrl_offset = 4 * slot_width;
1461 if (!(value & NAU8825_I2S_PCMB_MASK))
1462 ctrl_offset += 1;
1463 dac_s = (rx_mask & 0xf0) >> 4;
1464 adc_s = fls((tx_mask & 0xf0) >> 4);
1465 } else {
1466 dac_s = rx_mask & 0xf;
1467 adc_s = fls(tx_mask & 0xf);
1468 }
1469
1470 ctrl_val |= NAU8825_TDM_MODE;
1471
1472 switch (dac_s) {
1473 case 0x3:
1474 ctrl_val |= 1 << NAU8825_TDM_DACR_RX_SFT;
1475 break;
1476 case 0x5:
1477 ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT;
1478 break;
1479 case 0x6:
1480 ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT;
1481 ctrl_val |= 2 << NAU8825_TDM_DACR_RX_SFT;
1482 break;
1483 case 0x9:
1484 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT;
1485 break;
1486 case 0xa:
1487 ctrl_val |= 1 << NAU8825_TDM_DACL_RX_SFT;
1488 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT;
1489 break;
1490 case 0xc:
1491 ctrl_val |= 2 << NAU8825_TDM_DACL_RX_SFT;
1492 ctrl_val |= 3 << NAU8825_TDM_DACR_RX_SFT;
1493 break;
1494 default:
1495 return -EINVAL;
1496 }
1497
1498 ctrl_val |= adc_s - 1;
1499
1500 regmap_update_bits(nau8825->regmap, NAU8825_REG_TDM_CTRL,
1501 NAU8825_TDM_MODE | NAU8825_TDM_OFFSET_EN |
1502 NAU8825_TDM_DACL_RX_MASK | NAU8825_TDM_DACR_RX_MASK |
1503 NAU8825_TDM_TX_MASK, ctrl_val);
1504 regmap_update_bits(nau8825->regmap, NAU8825_REG_LEFT_TIME_SLOT,
1505 NAU8825_TSLOT_L0_MASK, ctrl_offset);
1506
1507 return 0;
1508}
1509
1510static const struct snd_soc_dai_ops nau8825_dai_ops = {
1511 .startup = nau8825_dai_startup,
1512 .hw_params = nau8825_hw_params,
1513 .set_fmt = nau8825_set_dai_fmt,
1514 .set_tdm_slot = nau8825_set_tdm_slot,
1515};
1516
1517#define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1518#define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1519 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1520
1521static struct snd_soc_dai_driver nau8825_dai = {
1522 .name = "nau8825-hifi",
1523 .playback = {
1524 .stream_name = "Playback",
1525 .channels_min = 1,
1526 .channels_max = 2,
1527 .rates = NAU8825_RATES,
1528 .formats = NAU8825_FORMATS,
1529 },
1530 .capture = {
1531 .stream_name = "Capture",
1532 .channels_min = 1,
1533 .channels_max = 2, /* Only 1 channel of data */
1534 .rates = NAU8825_RATES,
1535 .formats = NAU8825_FORMATS,
1536 },
1537 .ops = &nau8825_dai_ops,
1538};
1539
1540/**
1541 * nau8825_enable_jack_detect - Specify a jack for event reporting
1542 *
1543 * @component: component to register the jack with
1544 * @jack: jack to use to report headset and button events on
1545 *
1546 * After this function has been called the headset insert/remove and button
1547 * events will be routed to the given jack. Jack can be null to stop
1548 * reporting.
1549 */
1550int nau8825_enable_jack_detect(struct snd_soc_component *component,
1551 struct snd_soc_jack *jack)
1552{
1553 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
1554 struct regmap *regmap = nau8825->regmap;
1555
1556 nau8825->jack = jack;
1557
1558 if (!nau8825->jack) {
1559 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1560 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R |
1561 NAU8825_SPKR_DWN1L, 0);
1562 return 0;
1563 }
1564 /* Ground HP Outputs[1:0], needed for headset auto detection
1565 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1566 */
1567 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1568 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1569 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1570
1571 return 0;
1572}
1573EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1574
1575
1576static bool nau8825_is_jack_inserted(struct regmap *regmap)
1577{
1578 bool active_high, is_high;
1579 int status, jkdet;
1580
1581 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
1582 active_high = jkdet & NAU8825_JACK_POLARITY;
1583 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1584 is_high = status & NAU8825_GPIO2JD1;
1585 /* return jack connection status according to jack insertion logic
1586 * active high or active low.
1587 */
1588 return active_high == is_high;
1589}
1590
1591static void nau8825_restart_jack_detection(struct regmap *regmap)
1592{
1593 /* this will restart the entire jack detection process including MIC/GND
1594 * switching and create interrupts. We have to go from 0 to 1 and back
1595 * to 0 to restart.
1596 */
1597 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1598 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1599 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1600 NAU8825_JACK_DET_RESTART, 0);
1601}
1602
1603static void nau8825_int_status_clear_all(struct regmap *regmap)
1604{
1605 int active_irq, clear_irq, i;
1606
1607 /* Reset the intrruption status from rightmost bit if the corres-
1608 * ponding irq event occurs.
1609 */
1610 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1611 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1612 clear_irq = (0x1 << i);
1613 if (active_irq & clear_irq)
1614 regmap_write(regmap,
1615 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1616 }
1617}
1618
1619static void nau8825_eject_jack(struct nau8825 *nau8825)
1620{
1621 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1622 struct regmap *regmap = nau8825->regmap;
1623
1624 /* Force to cancel the cross talk detection process */
1625 nau8825_xtalk_cancel(nau8825);
1626
1627 snd_soc_dapm_disable_pin(dapm, "SAR");
1628 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1629 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1630 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1631 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1632 /* ground HPL/HPR, MICGRND1/2 */
1633 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1634
1635 snd_soc_dapm_sync(dapm);
1636
1637 /* Clear all interruption status */
1638 nau8825_int_status_clear_all(regmap);
1639
1640 /* Enable the insertion interruption, disable the ejection inter-
1641 * ruption, and then bypass de-bounce circuit.
1642 */
1643 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1644 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1645 NAU8825_IRQ_EJECT_DIS);
1646 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1647 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1648 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1649 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1650 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1651 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1652 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1653
1654 /* Disable ADC needed for interruptions at audo mode */
1655 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1656 NAU8825_ENABLE_ADC, 0);
1657
1658 /* Close clock for jack type detection at manual mode */
1659 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1660}
1661
1662/* Enable audo mode interruptions with internal clock. */
1663static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1664{
1665 struct regmap *regmap = nau8825->regmap;
1666
1667 /* Enable HSD function */
1668 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1669 NAU8825_HSD_AUTO_MODE, NAU8825_HSD_AUTO_MODE);
1670
1671 /* Enable headset jack type detection complete interruption and
1672 * jack ejection interruption.
1673 */
1674 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1675 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1676
1677 /* Enable internal VCO needed for interruptions */
1678 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1679 /* Raise up the internal clock for jack detection */
1680 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
1681 NAU8825_CLK_MCLK_SRC_MASK, 0);
1682
1683 /* Enable ADC needed for interruptions */
1684 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1685 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1686
1687 /* Chip needs one FSCLK cycle in order to generate interruptions,
1688 * as we cannot guarantee one will be provided by the system. Turning
1689 * master mode on then off enables us to generate that FSCLK cycle
1690 * with a minimum of contention on the clock bus.
1691 */
1692 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1693 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1694 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1695 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1696
1697 /* Not bypass de-bounce circuit */
1698 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1699 NAU8825_JACK_DET_DB_BYPASS, 0);
1700
1701 /* Unmask all interruptions */
1702 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1703
1704 /* Restart the jack detection process at auto mode */
1705 nau8825_restart_jack_detection(regmap);
1706}
1707
1708static int nau8825_button_decode(int value)
1709{
1710 int buttons = 0;
1711
1712 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1713 if (value & BIT(0))
1714 buttons |= SND_JACK_BTN_0;
1715 if (value & BIT(1))
1716 buttons |= SND_JACK_BTN_1;
1717 if (value & BIT(2))
1718 buttons |= SND_JACK_BTN_2;
1719 if (value & BIT(3))
1720 buttons |= SND_JACK_BTN_3;
1721 if (value & BIT(4))
1722 buttons |= SND_JACK_BTN_4;
1723 if (value & BIT(5))
1724 buttons |= SND_JACK_BTN_5;
1725
1726 return buttons;
1727}
1728
1729static int nau8825_high_imped_detection(struct nau8825 *nau8825)
1730{
1731 struct regmap *regmap = nau8825->regmap;
1732 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1733 unsigned int adc_mg1, adc_mg2;
1734
1735 /* Initial phase */
1736 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1737 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
1738 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2);
1739 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1,
1740 NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND);
1741 regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0x6);
1742 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1743 NAU8825_MICBIAS_LOWNOISE_MASK | NAU8825_MICBIAS_VOLTAGE_MASK,
1744 NAU8825_MICBIAS_LOWNOISE_EN);
1745 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1746 NAU8825_SAR_INPUT_MASK | NAU8825_SAR_TRACKING_GAIN_MASK |
1747 NAU8825_SAR_HV_SEL_MASK | NAU8825_SAR_RES_SEL_MASK |
1748 NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK,
1749 NAU8825_SAR_HV_SEL_VDDMIC | NAU8825_SAR_RES_SEL_70K);
1750
1751 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1752 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1753 snd_soc_dapm_sync(dapm);
1754
1755 /* Configure settings for first reading of SARADC */
1756 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1757 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
1758 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND2);
1759 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1760 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1761 NAU8825_MICBIAS_JKR2);
1762 regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg1);
1763
1764 /* Configure settings for second reading of SARADC */
1765 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1766 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1767 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1768 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
1769 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 |
1770 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1771 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1772 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
1773 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1);
1774 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1775 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1776 NAU8825_MICBIAS_JKSLV);
1777 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1778 NAU8825_SAR_INPUT_MASK, NAU8825_SAR_INPUT_JKSLV);
1779 regmap_read(regmap, NAU8825_REG_SARDOUT_RAM_STATUS, &adc_mg2);
1780
1781 /* Disable phase */
1782 snd_soc_dapm_disable_pin(dapm, "SAR");
1783 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1784 snd_soc_dapm_sync(dapm);
1785
1786 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1787 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_LOWNOISE_MASK |
1788 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1789 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1790 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 | NAU8825_SPKR_DWN1R |
1791 NAU8825_SPKR_DWN1L, NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2 |
1792 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1793 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_1,
1794 NAU8825_TESTDACIN_MASK, NAU8825_TESTDACIN_GND);
1795 regmap_write(regmap, NAU8825_REG_TRIM_SETTINGS, 0);
1796 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1797 NAU8825_SAR_TRACKING_GAIN_MASK | NAU8825_SAR_HV_SEL_MASK,
1798 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1799 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1800 NAU8825_SAR_COMPARE_TIME_MASK | NAU8825_SAR_SAMPLING_TIME_MASK,
1801 (nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT) |
1802 (nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT));
1803 dev_dbg(nau8825->dev, "adc_mg1:%x, adc_mg2:%x\n", adc_mg1, adc_mg2);
1804
1805 /* Confirmation phase */
1806 if (adc_mg1 > adc_mg2) {
1807 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1808
1809 /* Unground MICGND1 */
1810 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1811 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2,
1812 NAU8825_SPKR_ENGND2);
1813 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1814 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1815 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1816 NAU8825_MICBIAS_JKR2);
1817 /* Attach SARADC to MICGND1 */
1818 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1819 NAU8825_SAR_INPUT_MASK,
1820 NAU8825_SAR_INPUT_JKR2);
1821 } else if (adc_mg1 < adc_mg2) {
1822 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1823
1824 /* Unground MICGND2 */
1825 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1826 NAU8825_SPKR_ENGND1 | NAU8825_SPKR_ENGND2,
1827 NAU8825_SPKR_ENGND1);
1828 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1829 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1830 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1831 NAU8825_MICBIAS_JKSLV);
1832 /* Attach SARADC to MICGND2 */
1833 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1834 NAU8825_SAR_INPUT_MASK,
1835 NAU8825_SAR_INPUT_JKSLV);
1836 } else {
1837 dev_err(nau8825->dev, "Jack broken.\n");
1838 return -EINVAL;
1839 }
1840
1841 return 0;
1842}
1843
1844static int nau8825_jack_insert(struct nau8825 *nau8825)
1845{
1846 struct regmap *regmap = nau8825->regmap;
1847 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1848 int jack_status_reg, mic_detected;
1849 int type = 0;
1850
1851 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1852 mic_detected = (jack_status_reg >> 10) & 3;
1853 /* The JKSLV and JKR2 all detected in high impedance headset */
1854 if (mic_detected == 0x3)
1855 nau8825->high_imped = true;
1856 else
1857 nau8825->high_imped = false;
1858
1859 switch (mic_detected) {
1860 case 0:
1861 /* no mic */
1862 type = SND_JACK_HEADPHONE;
1863 break;
1864 case 1:
1865 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1866 type = SND_JACK_HEADSET;
1867
1868 /* Unground MICGND1 */
1869 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1870 1 << 2);
1871 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1872 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1873 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1874 NAU8825_MICBIAS_JKR2);
1875 /* Attach SARADC to MICGND1 */
1876 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1877 NAU8825_SAR_INPUT_MASK,
1878 NAU8825_SAR_INPUT_JKR2);
1879
1880 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1881 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1882 snd_soc_dapm_sync(dapm);
1883 break;
1884 case 2:
1885 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1886 type = SND_JACK_HEADSET;
1887
1888 /* Unground MICGND2 */
1889 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1890 2 << 2);
1891 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1892 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1893 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1894 NAU8825_MICBIAS_JKSLV);
1895 /* Attach SARADC to MICGND2 */
1896 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1897 NAU8825_SAR_INPUT_MASK,
1898 NAU8825_SAR_INPUT_JKSLV);
1899
1900 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1901 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1902 snd_soc_dapm_sync(dapm);
1903 break;
1904 case 3:
1905 /* Detection failure case */
1906 dev_warn(nau8825->dev,
1907 "Detection failure. Try the manually mechanism for jack type checking.\n");
1908 if (!nau8825_high_imped_detection(nau8825)) {
1909 type = SND_JACK_HEADSET;
1910 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1911 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1912 snd_soc_dapm_sync(dapm);
1913 } else
1914 type = SND_JACK_HEADPHONE;
1915 break;
1916 }
1917
1918 /* Update to the default divider of internal clock for power saving */
1919 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
1920 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
1921
1922 /* Disable HSD function */
1923 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, NAU8825_HSD_AUTO_MODE, 0);
1924
1925 /* Leaving HPOL/R grounded after jack insert by default. They will be
1926 * ungrounded as part of the widget power up sequence at the beginning
1927 * of playback to reduce pop.
1928 */
1929 return type;
1930}
1931
1932#define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1933 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1934
1935static irqreturn_t nau8825_interrupt(int irq, void *data)
1936{
1937 struct nau8825 *nau8825 = (struct nau8825 *)data;
1938 struct regmap *regmap = nau8825->regmap;
1939 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1940
1941 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1942 dev_err(nau8825->dev, "failed to read irq status\n");
1943 return IRQ_NONE;
1944 }
1945
1946 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1947 NAU8825_JACK_EJECTION_DETECTED) {
1948
1949 nau8825_eject_jack(nau8825);
1950 event_mask |= SND_JACK_HEADSET;
1951 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1952 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1953 int key_status;
1954
1955 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1956 &key_status);
1957
1958 /* upper 8 bits of the register are for short pressed keys,
1959 * lower 8 bits - for long pressed buttons
1960 */
1961 nau8825->button_pressed = nau8825_button_decode(
1962 key_status >> 8);
1963
1964 event |= nau8825->button_pressed;
1965 event_mask |= NAU8825_BUTTONS;
1966 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1967 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1968 event_mask = NAU8825_BUTTONS;
1969 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1970 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1971 if (nau8825_is_jack_inserted(regmap)) {
1972 event |= nau8825_jack_insert(nau8825);
1973 if (nau8825->xtalk_enable && !nau8825->high_imped) {
1974 /* Apply the cross talk suppression in the
1975 * headset without high impedance.
1976 */
1977 if (!nau8825->xtalk_protect) {
1978 /* Raise protection for cross talk de-
1979 * tection if no protection before.
1980 * The driver has to cancel the pro-
1981 * cess and restore changes if process
1982 * is ongoing when ejection.
1983 */
1984 int ret;
1985 nau8825->xtalk_protect = true;
1986 ret = nau8825_sema_acquire(nau8825, 0);
1987 if (ret)
1988 nau8825->xtalk_protect = false;
1989 }
1990 /* Startup cross talk detection process */
1991 if (nau8825->xtalk_protect) {
1992 nau8825->xtalk_state =
1993 NAU8825_XTALK_PREPARE;
1994 schedule_work(&nau8825->xtalk_work);
1995 }
1996 } else {
1997 /* The cross talk suppression shouldn't apply
1998 * in the headset with high impedance. Thus,
1999 * relieve the protection raised before.
2000 */
2001 if (nau8825->xtalk_protect) {
2002 nau8825_sema_release(nau8825);
2003 nau8825->xtalk_protect = false;
2004 }
2005 }
2006 } else {
2007 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
2008 nau8825_eject_jack(nau8825);
2009 }
2010
2011 event_mask |= SND_JACK_HEADSET;
2012 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
2013 /* Record the interruption report event for driver to report
2014 * the event later. The jack report will delay until cross
2015 * talk detection process is done.
2016 */
2017 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
2018 nau8825->xtalk_event = event;
2019 nau8825->xtalk_event_mask = event_mask;
2020 }
2021 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
2022 /* crosstalk detection enable and process on going */
2023 if (nau8825->xtalk_enable && nau8825->xtalk_protect)
2024 schedule_work(&nau8825->xtalk_work);
2025 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
2026 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
2027 NAU8825_JACK_INSERTION_DETECTED) {
2028 /* One more step to check GPIO status directly. Thus, the
2029 * driver can confirm the real insertion interruption because
2030 * the intrruption at manual mode has bypassed debounce
2031 * circuit which can get rid of unstable status.
2032 */
2033 if (nau8825_is_jack_inserted(regmap)) {
2034 /* Turn off insertion interruption at manual mode */
2035 regmap_update_bits(regmap,
2036 NAU8825_REG_INTERRUPT_DIS_CTRL,
2037 NAU8825_IRQ_INSERT_DIS,
2038 NAU8825_IRQ_INSERT_DIS);
2039 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2040 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
2041 /* Enable interruption for jack type detection at audo
2042 * mode which can detect microphone and jack type.
2043 */
2044 nau8825_setup_auto_irq(nau8825);
2045 }
2046 }
2047
2048 if (!clear_irq)
2049 clear_irq = active_irq;
2050 /* clears the rightmost interruption */
2051 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
2052
2053 /* Delay jack report until cross talk detection is done. It can avoid
2054 * application to do playback preparation when cross talk detection
2055 * process is still working. Otherwise, the resource like clock and
2056 * power will be issued by them at the same time and conflict happens.
2057 */
2058 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
2059 snd_soc_jack_report(nau8825->jack, event, event_mask);
2060
2061 return IRQ_HANDLED;
2062}
2063
2064static void nau8825_setup_buttons(struct nau8825 *nau8825)
2065{
2066 struct regmap *regmap = nau8825->regmap;
2067
2068 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
2069 NAU8825_SAR_TRACKING_GAIN_MASK,
2070 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
2071 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
2072 NAU8825_SAR_COMPARE_TIME_MASK,
2073 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
2074 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
2075 NAU8825_SAR_SAMPLING_TIME_MASK,
2076 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
2077
2078 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
2079 NAU8825_KEYDET_LEVELS_NR_MASK,
2080 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
2081 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
2082 NAU8825_KEYDET_HYSTERESIS_MASK,
2083 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
2084 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
2085 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
2086 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
2087
2088 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
2089 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
2090 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
2091 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
2092 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
2093 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
2094 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
2095 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
2096
2097 /* Enable short press and release interruptions */
2098 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2099 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
2100 0);
2101}
2102
2103static void nau8825_init_regs(struct nau8825 *nau8825)
2104{
2105 struct regmap *regmap = nau8825->regmap;
2106
2107 /* Latch IIC LSB value */
2108 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
2109 /* Enable Bias/Vmid */
2110 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
2111 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
2112 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
2113 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
2114
2115 /* VMID Tieoff */
2116 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
2117 NAU8825_BIAS_VMID_SEL_MASK,
2118 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
2119 /* Disable Boost Driver, Automatic Short circuit protection enable */
2120 regmap_update_bits(regmap, NAU8825_REG_BOOST,
2121 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
2122 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
2123 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
2124 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
2125
2126 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
2127 NAU8825_JKDET_OUTPUT_EN,
2128 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
2129 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
2130 NAU8825_JKDET_PULL_EN,
2131 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
2132 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
2133 NAU8825_JKDET_PULL_UP,
2134 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
2135 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2136 NAU8825_JACK_POLARITY,
2137 /* jkdet_polarity - 1 is for active-low */
2138 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
2139
2140 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2141 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
2142 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
2143 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2144 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
2145 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
2146
2147 /* Pull up IRQ pin */
2148 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2149 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN,
2150 NAU8825_IRQ_PIN_PULLUP | NAU8825_IRQ_PIN_PULL_EN);
2151 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
2152 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
2153
2154 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
2155 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
2156
2157 if (nau8825->sar_threshold_num)
2158 nau8825_setup_buttons(nau8825);
2159
2160 /* Default oversampling/decimations settings are unusable
2161 * (audible hiss). Set it to something better.
2162 */
2163 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
2164 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
2165 NAU8825_ADC_SYNC_DOWN_64);
2166 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
2167 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
2168 /* Disable DACR/L power */
2169 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
2170 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
2171 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
2172 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
2173 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
2174 * signal to avoid any glitches due to power up transients in both
2175 * the analog and digital DAC circuit.
2176 */
2177 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
2178 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
2179 /* CICCLP off */
2180 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
2181 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
2182
2183 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
2184 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
2185 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
2186 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
2187 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
2188 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
2189 /* Class G timer 64ms */
2190 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
2191 NAU8825_CLASSG_TIMER_MASK,
2192 0x20 << NAU8825_CLASSG_TIMER_SFT);
2193 /* DAC clock delay 2ns, VREF */
2194 regmap_update_bits(regmap, NAU8825_REG_RDAC,
2195 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
2196 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
2197 (0x3 << NAU8825_RDAC_VREF_SFT));
2198 /* Config L/R channel */
2199 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
2200 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
2201 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
2202 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
2203 /* Disable short Frame Sync detection logic */
2204 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
2205 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
2206 /* ADCDAT IO drive strength control */
2207 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
2208 NAU8825_ADCOUT_DS_MASK,
2209 nau8825->adcout_ds << NAU8825_ADCOUT_DS_SFT);
2210}
2211
2212static const struct regmap_config nau8825_regmap_config = {
2213 .val_bits = NAU8825_REG_DATA_LEN,
2214 .reg_bits = NAU8825_REG_ADDR_LEN,
2215
2216 .max_register = NAU8825_REG_MAX,
2217 .readable_reg = nau8825_readable_reg,
2218 .writeable_reg = nau8825_writeable_reg,
2219 .volatile_reg = nau8825_volatile_reg,
2220
2221 .cache_type = REGCACHE_RBTREE,
2222 .reg_defaults = nau8825_reg_defaults,
2223 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
2224};
2225
2226static int nau8825_component_probe(struct snd_soc_component *component)
2227{
2228 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2229 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
2230
2231 nau8825->dapm = dapm;
2232
2233 return 0;
2234}
2235
2236static void nau8825_component_remove(struct snd_soc_component *component)
2237{
2238 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2239
2240 /* Cancel and reset cross tak suppresstion detection funciton */
2241 nau8825_xtalk_cancel(nau8825);
2242}
2243
2244/**
2245 * nau8825_calc_fll_param - Calculate FLL parameters.
2246 * @fll_in: external clock provided to codec.
2247 * @fs: sampling rate.
2248 * @fll_param: Pointer to structure of FLL parameters.
2249 *
2250 * Calculate FLL parameters to configure codec.
2251 *
2252 * Returns 0 for success or negative error code.
2253 */
2254static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
2255 struct nau8825_fll *fll_param)
2256{
2257 u64 fvco, fvco_max;
2258 unsigned int fref, i, fvco_sel;
2259
2260 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
2261 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
2262 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
2263 */
2264 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
2265 fref = fll_in / fll_pre_scalar[i].param;
2266 if (fref <= NAU_FREF_MAX)
2267 break;
2268 }
2269 if (i == ARRAY_SIZE(fll_pre_scalar))
2270 return -EINVAL;
2271 fll_param->clk_ref_div = fll_pre_scalar[i].val;
2272
2273 /* Choose the FLL ratio based on FREF */
2274 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
2275 if (fref >= fll_ratio[i].param)
2276 break;
2277 }
2278 if (i == ARRAY_SIZE(fll_ratio))
2279 return -EINVAL;
2280 fll_param->ratio = fll_ratio[i].val;
2281
2282 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
2283 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
2284 * guaranteed across the full range of operation.
2285 * FDCO = freq_out * 2 * mclk_src_scaling
2286 */
2287 fvco_max = 0;
2288 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
2289 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
2290 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
2291 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
2292 fvco_max < fvco) {
2293 fvco_max = fvco;
2294 fvco_sel = i;
2295 }
2296 }
2297 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
2298 return -EINVAL;
2299 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
2300
2301 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
2302 * input based on FDCO, FREF and FLL ratio.
2303 */
2304 fvco = div_u64(fvco_max << fll_param->fll_frac_num, fref * fll_param->ratio);
2305 fll_param->fll_int = (fvco >> fll_param->fll_frac_num) & 0x3FF;
2306 if (fll_param->fll_frac_num == 16)
2307 fll_param->fll_frac = fvco & 0xFFFF;
2308 else
2309 fll_param->fll_frac = fvco & 0xFFFFFF;
2310 return 0;
2311}
2312
2313static void nau8825_fll_apply(struct nau8825 *nau8825,
2314 struct nau8825_fll *fll_param)
2315{
2316 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2317 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
2318 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
2319 /* Make DSP operate at high speed for better performance. */
2320 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
2321 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
2322 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
2323 /* FLL 16/24 bit fractional input */
2324 if (fll_param->fll_frac_num == 16)
2325 regmap_write(nau8825->regmap, NAU8825_REG_FLL2,
2326 fll_param->fll_frac);
2327 else {
2328 regmap_write(nau8825->regmap, NAU8825_REG_FLL2_LOWER,
2329 fll_param->fll_frac & 0xffff);
2330 regmap_write(nau8825->regmap, NAU8825_REG_FLL2_UPPER,
2331 (fll_param->fll_frac >> 16) & 0xff);
2332 }
2333 /* FLL 10-bit integer input */
2334 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2335 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
2336 /* FLL pre-scaler */
2337 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
2338 NAU8825_FLL_REF_DIV_MASK,
2339 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
2340 /* select divided VCO input */
2341 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2342 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
2343 /* Disable free-running mode */
2344 regmap_update_bits(nau8825->regmap,
2345 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
2346 if (fll_param->fll_frac) {
2347 /* set FLL loop filter enable and cutoff frequency at 500Khz */
2348 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2349 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2350 NAU8825_FLL_FTR_SW_MASK,
2351 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2352 NAU8825_FLL_FTR_SW_FILTER);
2353 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2354 NAU8825_SDM_EN | NAU8825_CUTOFF500,
2355 NAU8825_SDM_EN | NAU8825_CUTOFF500);
2356 } else {
2357 /* disable FLL loop filter and cutoff frequency */
2358 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2359 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2360 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
2361 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2362 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
2363 }
2364}
2365
2366/* freq_out must be 256*Fs in order to achieve the best performance */
2367static int nau8825_set_pll(struct snd_soc_component *component, int pll_id, int source,
2368 unsigned int freq_in, unsigned int freq_out)
2369{
2370 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2371 struct nau8825_fll fll_param;
2372 int ret, fs;
2373
2374 if (nau8825->sw_id == NAU8825_SOFTWARE_ID_NAU8825)
2375 fll_param.fll_frac_num = 16;
2376 else
2377 fll_param.fll_frac_num = 24;
2378
2379 fs = freq_out / 256;
2380 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
2381 if (ret < 0) {
2382 dev_err(component->dev, "Unsupported input clock %d\n", freq_in);
2383 return ret;
2384 }
2385 dev_dbg(component->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
2386 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
2387 fll_param.fll_int, fll_param.clk_ref_div);
2388
2389 nau8825_fll_apply(nau8825, &fll_param);
2390 mdelay(2);
2391 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2392 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2393 return 0;
2394}
2395
2396static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
2397{
2398 int ret;
2399
2400 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
2401 if (IS_ERR(nau8825->mclk)) {
2402 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
2403 return 0;
2404 }
2405
2406 if (!nau8825->mclk_freq) {
2407 ret = clk_prepare_enable(nau8825->mclk);
2408 if (ret) {
2409 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2410 return ret;
2411 }
2412 }
2413
2414 if (nau8825->mclk_freq != freq) {
2415 freq = clk_round_rate(nau8825->mclk, freq);
2416 ret = clk_set_rate(nau8825->mclk, freq);
2417 if (ret) {
2418 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2419 return ret;
2420 }
2421 nau8825->mclk_freq = freq;
2422 }
2423
2424 return 0;
2425}
2426
2427static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2428{
2429 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2430 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2431 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2432 NAU8825_DCO_EN, 0);
2433 /* Make DSP operate as default setting for power saving. */
2434 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2435 NAU8825_ICTRL_LATCH_MASK, 0);
2436}
2437
2438static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2439 unsigned int freq)
2440{
2441 struct regmap *regmap = nau8825->regmap;
2442 int ret;
2443
2444 switch (clk_id) {
2445 case NAU8825_CLK_DIS:
2446 /* Clock provided externally and disable internal VCO clock */
2447 nau8825_configure_mclk_as_sysclk(regmap);
2448 if (nau8825->mclk_freq) {
2449 clk_disable_unprepare(nau8825->mclk);
2450 nau8825->mclk_freq = 0;
2451 }
2452
2453 break;
2454 case NAU8825_CLK_MCLK:
2455 /* Acquire the semaphore to synchronize the playback and
2456 * interrupt handler. In order to avoid the playback inter-
2457 * fered by cross talk process, the driver make the playback
2458 * preparation halted until cross talk process finish.
2459 */
2460 nau8825_sema_acquire(nau8825, 3 * HZ);
2461 nau8825_configure_mclk_as_sysclk(regmap);
2462 /* MCLK not changed by clock tree */
2463 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2464 NAU8825_CLK_MCLK_SRC_MASK, 0);
2465 /* Release the semaphore. */
2466 nau8825_sema_release(nau8825);
2467
2468 ret = nau8825_mclk_prepare(nau8825, freq);
2469 if (ret)
2470 return ret;
2471
2472 break;
2473 case NAU8825_CLK_INTERNAL:
2474 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2475 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2476 NAU8825_DCO_EN, NAU8825_DCO_EN);
2477 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2478 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2479 /* Decrease the VCO frequency and make DSP operate
2480 * as default setting for power saving.
2481 */
2482 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2483 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2484 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2485 NAU8825_ICTRL_LATCH_MASK |
2486 NAU8825_FLL_RATIO_MASK, 0x10);
2487 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2488 NAU8825_SDM_EN, NAU8825_SDM_EN);
2489 } else {
2490 /* The clock turns off intentionally for power saving
2491 * when no headset connected.
2492 */
2493 nau8825_configure_mclk_as_sysclk(regmap);
2494 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2495 }
2496 if (nau8825->mclk_freq) {
2497 clk_disable_unprepare(nau8825->mclk);
2498 nau8825->mclk_freq = 0;
2499 }
2500
2501 break;
2502 case NAU8825_CLK_FLL_MCLK:
2503 /* Acquire the semaphore to synchronize the playback and
2504 * interrupt handler. In order to avoid the playback inter-
2505 * fered by cross talk process, the driver make the playback
2506 * preparation halted until cross talk process finish.
2507 */
2508 nau8825_sema_acquire(nau8825, 3 * HZ);
2509 /* Higher FLL reference input frequency can only set lower
2510 * gain error, such as 0000 for input reference from MCLK
2511 * 12.288Mhz.
2512 */
2513 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2514 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2515 NAU8825_FLL_CLK_SRC_MCLK | 0);
2516 /* Release the semaphore. */
2517 nau8825_sema_release(nau8825);
2518
2519 ret = nau8825_mclk_prepare(nau8825, freq);
2520 if (ret)
2521 return ret;
2522
2523 break;
2524 case NAU8825_CLK_FLL_BLK:
2525 /* Acquire the semaphore to synchronize the playback and
2526 * interrupt handler. In order to avoid the playback inter-
2527 * fered by cross talk process, the driver make the playback
2528 * preparation halted until cross talk process finish.
2529 */
2530 nau8825_sema_acquire(nau8825, 3 * HZ);
2531 /* If FLL reference input is from low frequency source,
2532 * higher error gain can apply such as 0xf which has
2533 * the most sensitive gain error correction threshold,
2534 * Therefore, FLL has the most accurate DCO to
2535 * target frequency.
2536 */
2537 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2538 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2539 NAU8825_FLL_CLK_SRC_BLK |
2540 (0xf << NAU8825_GAIN_ERR_SFT));
2541 /* Release the semaphore. */
2542 nau8825_sema_release(nau8825);
2543
2544 if (nau8825->mclk_freq) {
2545 clk_disable_unprepare(nau8825->mclk);
2546 nau8825->mclk_freq = 0;
2547 }
2548
2549 break;
2550 case NAU8825_CLK_FLL_FS:
2551 /* Acquire the semaphore to synchronize the playback and
2552 * interrupt handler. In order to avoid the playback inter-
2553 * fered by cross talk process, the driver make the playback
2554 * preparation halted until cross talk process finish.
2555 */
2556 nau8825_sema_acquire(nau8825, 3 * HZ);
2557 /* If FLL reference input is from low frequency source,
2558 * higher error gain can apply such as 0xf which has
2559 * the most sensitive gain error correction threshold,
2560 * Therefore, FLL has the most accurate DCO to
2561 * target frequency.
2562 */
2563 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2564 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2565 NAU8825_FLL_CLK_SRC_FS |
2566 (0xf << NAU8825_GAIN_ERR_SFT));
2567 /* Release the semaphore. */
2568 nau8825_sema_release(nau8825);
2569
2570 if (nau8825->mclk_freq) {
2571 clk_disable_unprepare(nau8825->mclk);
2572 nau8825->mclk_freq = 0;
2573 }
2574
2575 break;
2576 default:
2577 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2578 return -EINVAL;
2579 }
2580
2581 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2582 clk_id);
2583 return 0;
2584}
2585
2586static int nau8825_set_sysclk(struct snd_soc_component *component, int clk_id,
2587 int source, unsigned int freq, int dir)
2588{
2589 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2590
2591 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2592}
2593
2594static int nau8825_resume_setup(struct nau8825 *nau8825)
2595{
2596 struct regmap *regmap = nau8825->regmap;
2597
2598 /* Close clock when jack type detection at manual mode */
2599 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2600
2601 /* Clear all interruption status */
2602 nau8825_int_status_clear_all(regmap);
2603
2604 /* Enable both insertion and ejection interruptions, and then
2605 * bypass de-bounce circuit.
2606 */
2607 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2608 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2609 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2610 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2611 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2612 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2613 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2614 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2615
2616 return 0;
2617}
2618
2619static int nau8825_set_bias_level(struct snd_soc_component *component,
2620 enum snd_soc_bias_level level)
2621{
2622 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2623 int ret;
2624
2625 switch (level) {
2626 case SND_SOC_BIAS_ON:
2627 break;
2628
2629 case SND_SOC_BIAS_PREPARE:
2630 break;
2631
2632 case SND_SOC_BIAS_STANDBY:
2633 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
2634 if (nau8825->mclk_freq) {
2635 ret = clk_prepare_enable(nau8825->mclk);
2636 if (ret) {
2637 dev_err(nau8825->dev, "Unable to prepare component mclk\n");
2638 return ret;
2639 }
2640 }
2641 /* Setup codec configuration after resume */
2642 nau8825_resume_setup(nau8825);
2643 }
2644 break;
2645
2646 case SND_SOC_BIAS_OFF:
2647 /* Reset the configuration of jack type for detection */
2648 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
2649 regmap_update_bits(nau8825->regmap, NAU8825_REG_MIC_BIAS,
2650 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
2651 /* ground HPL/HPR, MICGRND1/2 */
2652 regmap_update_bits(nau8825->regmap,
2653 NAU8825_REG_HSD_CTRL, 0xf, 0xf);
2654 /* Cancel and reset cross talk detection funciton */
2655 nau8825_xtalk_cancel(nau8825);
2656 /* Turn off all interruptions before system shutdown. Keep the
2657 * interruption quiet before resume setup completes.
2658 */
2659 regmap_write(nau8825->regmap,
2660 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2661 /* Disable ADC needed for interruptions at audo mode */
2662 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2663 NAU8825_ENABLE_ADC, 0);
2664 if (nau8825->mclk_freq)
2665 clk_disable_unprepare(nau8825->mclk);
2666 break;
2667 }
2668 return 0;
2669}
2670
2671static int __maybe_unused nau8825_suspend(struct snd_soc_component *component)
2672{
2673 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2674
2675 disable_irq(nau8825->irq);
2676 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
2677 /* Power down codec power; don't suppoet button wakeup */
2678 snd_soc_dapm_disable_pin(nau8825->dapm, "SAR");
2679 snd_soc_dapm_disable_pin(nau8825->dapm, "MICBIAS");
2680 snd_soc_dapm_sync(nau8825->dapm);
2681 regcache_cache_only(nau8825->regmap, true);
2682 regcache_mark_dirty(nau8825->regmap);
2683
2684 return 0;
2685}
2686
2687static int __maybe_unused nau8825_resume(struct snd_soc_component *component)
2688{
2689 struct nau8825 *nau8825 = snd_soc_component_get_drvdata(component);
2690 int ret;
2691
2692 regcache_cache_only(nau8825->regmap, false);
2693 regcache_sync(nau8825->regmap);
2694 nau8825->xtalk_protect = true;
2695 ret = nau8825_sema_acquire(nau8825, 0);
2696 if (ret)
2697 nau8825->xtalk_protect = false;
2698 enable_irq(nau8825->irq);
2699
2700 return 0;
2701}
2702
2703static int nau8825_set_jack(struct snd_soc_component *component,
2704 struct snd_soc_jack *jack, void *data)
2705{
2706 return nau8825_enable_jack_detect(component, jack);
2707}
2708
2709static const struct snd_soc_component_driver nau8825_component_driver = {
2710 .probe = nau8825_component_probe,
2711 .remove = nau8825_component_remove,
2712 .set_sysclk = nau8825_set_sysclk,
2713 .set_pll = nau8825_set_pll,
2714 .set_bias_level = nau8825_set_bias_level,
2715 .suspend = nau8825_suspend,
2716 .resume = nau8825_resume,
2717 .controls = nau8825_controls,
2718 .num_controls = ARRAY_SIZE(nau8825_controls),
2719 .dapm_widgets = nau8825_dapm_widgets,
2720 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2721 .dapm_routes = nau8825_dapm_routes,
2722 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2723 .set_jack = nau8825_set_jack,
2724 .suspend_bias_off = 1,
2725 .idle_bias_on = 1,
2726 .use_pmdown_time = 1,
2727 .endianness = 1,
2728};
2729
2730static void nau8825_reset_chip(struct regmap *regmap)
2731{
2732 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2733 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2734}
2735
2736static void nau8825_print_device_properties(struct nau8825 *nau8825)
2737{
2738 int i;
2739 struct device *dev = nau8825->dev;
2740
2741 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2742 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2743 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2744 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2745 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2746 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2747
2748 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2749 for (i = 0; i < nau8825->sar_threshold_num; i++)
2750 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2751 nau8825->sar_threshold[i]);
2752
2753 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2754 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2755 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2756 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2757 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2758 dev_dbg(dev, "jack-insert-debounce: %d\n",
2759 nau8825->jack_insert_debounce);
2760 dev_dbg(dev, "jack-eject-debounce: %d\n",
2761 nau8825->jack_eject_debounce);
2762 dev_dbg(dev, "crosstalk-enable: %d\n",
2763 nau8825->xtalk_enable);
2764 dev_dbg(dev, "adcout-drive-strong: %d\n", nau8825->adcout_ds);
2765 dev_dbg(dev, "adc-delay-ms: %d\n", nau8825->adc_delay);
2766}
2767
2768static int nau8825_read_device_properties(struct device *dev,
2769 struct nau8825 *nau8825) {
2770 int ret;
2771
2772 nau8825->jkdet_enable = device_property_read_bool(dev,
2773 "nuvoton,jkdet-enable");
2774 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2775 "nuvoton,jkdet-pull-enable");
2776 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2777 "nuvoton,jkdet-pull-up");
2778 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2779 &nau8825->jkdet_polarity);
2780 if (ret)
2781 nau8825->jkdet_polarity = 1;
2782 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
2783 &nau8825->micbias_voltage);
2784 if (ret)
2785 nau8825->micbias_voltage = 6;
2786 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
2787 &nau8825->vref_impedance);
2788 if (ret)
2789 nau8825->vref_impedance = 2;
2790 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2791 &nau8825->sar_threshold_num);
2792 if (ret)
2793 nau8825->sar_threshold_num = 4;
2794 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2795 nau8825->sar_threshold, nau8825->sar_threshold_num);
2796 if (ret) {
2797 nau8825->sar_threshold[0] = 0x08;
2798 nau8825->sar_threshold[1] = 0x12;
2799 nau8825->sar_threshold[2] = 0x26;
2800 nau8825->sar_threshold[3] = 0x73;
2801 }
2802 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2803 &nau8825->sar_hysteresis);
2804 if (ret)
2805 nau8825->sar_hysteresis = 0;
2806 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
2807 &nau8825->sar_voltage);
2808 if (ret)
2809 nau8825->sar_voltage = 6;
2810 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
2811 &nau8825->sar_compare_time);
2812 if (ret)
2813 nau8825->sar_compare_time = 1;
2814 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2815 &nau8825->sar_sampling_time);
2816 if (ret)
2817 nau8825->sar_sampling_time = 1;
2818 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
2819 &nau8825->key_debounce);
2820 if (ret)
2821 nau8825->key_debounce = 3;
2822 ret = device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2823 &nau8825->jack_insert_debounce);
2824 if (ret)
2825 nau8825->jack_insert_debounce = 7;
2826 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2827 &nau8825->jack_eject_debounce);
2828 if (ret)
2829 nau8825->jack_eject_debounce = 0;
2830 nau8825->xtalk_enable = device_property_read_bool(dev,
2831 "nuvoton,crosstalk-enable");
2832 nau8825->adcout_ds = device_property_read_bool(dev, "nuvoton,adcout-drive-strong");
2833 ret = device_property_read_u32(dev, "nuvoton,adc-delay-ms", &nau8825->adc_delay);
2834 if (ret)
2835 nau8825->adc_delay = 125;
2836 if (nau8825->adc_delay < 125 || nau8825->adc_delay > 500)
2837 dev_warn(dev, "Please set the suitable delay time!\n");
2838
2839 nau8825->mclk = devm_clk_get_optional(dev, "mclk");
2840 if (IS_ERR(nau8825->mclk))
2841 return PTR_ERR(nau8825->mclk);
2842 if (!nau8825->mclk)
2843 /* The MCLK is managed externally or not used at all */
2844 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2845
2846 return 0;
2847}
2848
2849static int nau8825_setup_irq(struct nau8825 *nau8825)
2850{
2851 int ret;
2852
2853 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2854 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2855 "nau8825", nau8825);
2856
2857 if (ret) {
2858 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2859 nau8825->irq, ret);
2860 return ret;
2861 }
2862
2863 return 0;
2864}
2865
2866static int nau8825_i2c_probe(struct i2c_client *i2c)
2867{
2868 struct device *dev = &i2c->dev;
2869 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2870 int ret, value;
2871
2872 if (!nau8825) {
2873 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2874 if (!nau8825)
2875 return -ENOMEM;
2876 ret = nau8825_read_device_properties(dev, nau8825);
2877 if (ret)
2878 return ret;
2879 }
2880
2881 i2c_set_clientdata(i2c, nau8825);
2882
2883 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2884 if (IS_ERR(nau8825->regmap))
2885 return PTR_ERR(nau8825->regmap);
2886 nau8825->dev = dev;
2887 nau8825->irq = i2c->irq;
2888 /* Initiate parameters, semaphore and work queue which are needed in
2889 * cross talk suppression measurment function.
2890 */
2891 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2892 nau8825->xtalk_protect = false;
2893 nau8825->xtalk_baktab_initialized = false;
2894 sema_init(&nau8825->xtalk_sem, 1);
2895 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2896
2897 nau8825_print_device_properties(nau8825);
2898
2899 nau8825_reset_chip(nau8825->regmap);
2900 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2901 if (ret < 0) {
2902 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2903 ret);
2904 return ret;
2905 }
2906 nau8825->sw_id = value & NAU8825_SOFTWARE_ID_MASK;
2907 switch (nau8825->sw_id) {
2908 case NAU8825_SOFTWARE_ID_NAU8825:
2909 break;
2910 case NAU8825_SOFTWARE_ID_NAU8825C:
2911 ret = regmap_register_patch(nau8825->regmap, nau8825_regmap_patch,
2912 ARRAY_SIZE(nau8825_regmap_patch));
2913 if (ret) {
2914 dev_err(dev, "Failed to register Rev C patch: %d\n", ret);
2915 return ret;
2916 }
2917 break;
2918 default:
2919 dev_err(dev, "Not a NAU8825 chip\n");
2920 return -ENODEV;
2921 }
2922
2923 nau8825_init_regs(nau8825);
2924
2925 if (i2c->irq)
2926 nau8825_setup_irq(nau8825);
2927
2928 return devm_snd_soc_register_component(&i2c->dev,
2929 &nau8825_component_driver,
2930 &nau8825_dai, 1);
2931}
2932
2933static void nau8825_i2c_remove(struct i2c_client *client)
2934{}
2935
2936static const struct i2c_device_id nau8825_i2c_ids[] = {
2937 { "nau8825" },
2938 { }
2939};
2940MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2941
2942#ifdef CONFIG_OF
2943static const struct of_device_id nau8825_of_ids[] = {
2944 { .compatible = "nuvoton,nau8825", },
2945 {}
2946};
2947MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2948#endif
2949
2950#ifdef CONFIG_ACPI
2951static const struct acpi_device_id nau8825_acpi_match[] = {
2952 { "10508825", 0 },
2953 {},
2954};
2955MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2956#endif
2957
2958static struct i2c_driver nau8825_driver = {
2959 .driver = {
2960 .name = "nau8825",
2961 .of_match_table = of_match_ptr(nau8825_of_ids),
2962 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2963 },
2964 .probe = nau8825_i2c_probe,
2965 .remove = nau8825_i2c_remove,
2966 .id_table = nau8825_i2c_ids,
2967};
2968module_i2c_driver(nau8825_driver);
2969
2970MODULE_DESCRIPTION("ASoC nau8825 driver");
2971MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2972MODULE_LICENSE("GPL");
1/*
2 * Nuvoton NAU8825 audio codec driver
3 *
4 * Copyright 2015 Google Chromium project.
5 * Author: Anatol Pomozov <anatol@chromium.org>
6 * Copyright 2015 Nuvoton Technology Corp.
7 * Co-author: Meng-Huang Kuo <mhkuo@nuvoton.com>
8 *
9 * Licensed under the GPL-2.
10 */
11
12#include <linux/module.h>
13#include <linux/delay.h>
14#include <linux/init.h>
15#include <linux/i2c.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/clk.h>
19#include <linux/acpi.h>
20#include <linux/math64.h>
21#include <linux/semaphore.h>
22
23#include <sound/initval.h>
24#include <sound/tlv.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/jack.h>
30
31
32#include "nau8825.h"
33
34
35#define NUVOTON_CODEC_DAI "nau8825-hifi"
36
37#define NAU_FREF_MAX 13500000
38#define NAU_FVCO_MAX 124000000
39#define NAU_FVCO_MIN 90000000
40
41/* cross talk suppression detection */
42#define LOG10_MAGIC 646456993
43#define GAIN_AUGMENT 22500
44#define SIDETONE_BASE 207000
45
46/* the maximum frequency of CLK_ADC and CLK_DAC */
47#define CLK_DA_AD_MAX 6144000
48
49static int nau8825_configure_sysclk(struct nau8825 *nau8825,
50 int clk_id, unsigned int freq);
51
52struct nau8825_fll {
53 int mclk_src;
54 int ratio;
55 int fll_frac;
56 int fll_int;
57 int clk_ref_div;
58};
59
60struct nau8825_fll_attr {
61 unsigned int param;
62 unsigned int val;
63};
64
65/* scaling for mclk from sysclk_src output */
66static const struct nau8825_fll_attr mclk_src_scaling[] = {
67 { 1, 0x0 },
68 { 2, 0x2 },
69 { 4, 0x3 },
70 { 8, 0x4 },
71 { 16, 0x5 },
72 { 32, 0x6 },
73 { 3, 0x7 },
74 { 6, 0xa },
75 { 12, 0xb },
76 { 24, 0xc },
77 { 48, 0xd },
78 { 96, 0xe },
79 { 5, 0xf },
80};
81
82/* ratio for input clk freq */
83static const struct nau8825_fll_attr fll_ratio[] = {
84 { 512000, 0x01 },
85 { 256000, 0x02 },
86 { 128000, 0x04 },
87 { 64000, 0x08 },
88 { 32000, 0x10 },
89 { 8000, 0x20 },
90 { 4000, 0x40 },
91};
92
93static const struct nau8825_fll_attr fll_pre_scalar[] = {
94 { 1, 0x0 },
95 { 2, 0x1 },
96 { 4, 0x2 },
97 { 8, 0x3 },
98};
99
100/* over sampling rate */
101struct nau8825_osr_attr {
102 unsigned int osr;
103 unsigned int clk_src;
104};
105
106static const struct nau8825_osr_attr osr_dac_sel[] = {
107 { 64, 2 }, /* OSR 64, SRC 1/4 */
108 { 256, 0 }, /* OSR 256, SRC 1 */
109 { 128, 1 }, /* OSR 128, SRC 1/2 */
110 { 0, 0 },
111 { 32, 3 }, /* OSR 32, SRC 1/8 */
112};
113
114static const struct nau8825_osr_attr osr_adc_sel[] = {
115 { 32, 3 }, /* OSR 32, SRC 1/8 */
116 { 64, 2 }, /* OSR 64, SRC 1/4 */
117 { 128, 1 }, /* OSR 128, SRC 1/2 */
118 { 256, 0 }, /* OSR 256, SRC 1 */
119};
120
121static const struct reg_default nau8825_reg_defaults[] = {
122 { NAU8825_REG_ENA_CTRL, 0x00ff },
123 { NAU8825_REG_IIC_ADDR_SET, 0x0 },
124 { NAU8825_REG_CLK_DIVIDER, 0x0050 },
125 { NAU8825_REG_FLL1, 0x0 },
126 { NAU8825_REG_FLL2, 0x3126 },
127 { NAU8825_REG_FLL3, 0x0008 },
128 { NAU8825_REG_FLL4, 0x0010 },
129 { NAU8825_REG_FLL5, 0x0 },
130 { NAU8825_REG_FLL6, 0x6000 },
131 { NAU8825_REG_FLL_VCO_RSV, 0xf13c },
132 { NAU8825_REG_HSD_CTRL, 0x000c },
133 { NAU8825_REG_JACK_DET_CTRL, 0x0 },
134 { NAU8825_REG_INTERRUPT_MASK, 0x0 },
135 { NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff },
136 { NAU8825_REG_SAR_CTRL, 0x0015 },
137 { NAU8825_REG_KEYDET_CTRL, 0x0110 },
138 { NAU8825_REG_VDET_THRESHOLD_1, 0x0 },
139 { NAU8825_REG_VDET_THRESHOLD_2, 0x0 },
140 { NAU8825_REG_VDET_THRESHOLD_3, 0x0 },
141 { NAU8825_REG_VDET_THRESHOLD_4, 0x0 },
142 { NAU8825_REG_GPIO34_CTRL, 0x0 },
143 { NAU8825_REG_GPIO12_CTRL, 0x0 },
144 { NAU8825_REG_TDM_CTRL, 0x0 },
145 { NAU8825_REG_I2S_PCM_CTRL1, 0x000b },
146 { NAU8825_REG_I2S_PCM_CTRL2, 0x8010 },
147 { NAU8825_REG_LEFT_TIME_SLOT, 0x0 },
148 { NAU8825_REG_RIGHT_TIME_SLOT, 0x0 },
149 { NAU8825_REG_BIQ_CTRL, 0x0 },
150 { NAU8825_REG_BIQ_COF1, 0x0 },
151 { NAU8825_REG_BIQ_COF2, 0x0 },
152 { NAU8825_REG_BIQ_COF3, 0x0 },
153 { NAU8825_REG_BIQ_COF4, 0x0 },
154 { NAU8825_REG_BIQ_COF5, 0x0 },
155 { NAU8825_REG_BIQ_COF6, 0x0 },
156 { NAU8825_REG_BIQ_COF7, 0x0 },
157 { NAU8825_REG_BIQ_COF8, 0x0 },
158 { NAU8825_REG_BIQ_COF9, 0x0 },
159 { NAU8825_REG_BIQ_COF10, 0x0 },
160 { NAU8825_REG_ADC_RATE, 0x0010 },
161 { NAU8825_REG_DAC_CTRL1, 0x0001 },
162 { NAU8825_REG_DAC_CTRL2, 0x0 },
163 { NAU8825_REG_DAC_DGAIN_CTRL, 0x0 },
164 { NAU8825_REG_ADC_DGAIN_CTRL, 0x00cf },
165 { NAU8825_REG_MUTE_CTRL, 0x0 },
166 { NAU8825_REG_HSVOL_CTRL, 0x0 },
167 { NAU8825_REG_DACL_CTRL, 0x02cf },
168 { NAU8825_REG_DACR_CTRL, 0x00cf },
169 { NAU8825_REG_ADC_DRC_KNEE_IP12, 0x1486 },
170 { NAU8825_REG_ADC_DRC_KNEE_IP34, 0x0f12 },
171 { NAU8825_REG_ADC_DRC_SLOPES, 0x25ff },
172 { NAU8825_REG_ADC_DRC_ATKDCY, 0x3457 },
173 { NAU8825_REG_DAC_DRC_KNEE_IP12, 0x1486 },
174 { NAU8825_REG_DAC_DRC_KNEE_IP34, 0x0f12 },
175 { NAU8825_REG_DAC_DRC_SLOPES, 0x25f9 },
176 { NAU8825_REG_DAC_DRC_ATKDCY, 0x3457 },
177 { NAU8825_REG_IMM_MODE_CTRL, 0x0 },
178 { NAU8825_REG_CLASSG_CTRL, 0x0 },
179 { NAU8825_REG_OPT_EFUSE_CTRL, 0x0 },
180 { NAU8825_REG_MISC_CTRL, 0x0 },
181 { NAU8825_REG_BIAS_ADJ, 0x0 },
182 { NAU8825_REG_TRIM_SETTINGS, 0x0 },
183 { NAU8825_REG_ANALOG_CONTROL_1, 0x0 },
184 { NAU8825_REG_ANALOG_CONTROL_2, 0x0 },
185 { NAU8825_REG_ANALOG_ADC_1, 0x0011 },
186 { NAU8825_REG_ANALOG_ADC_2, 0x0020 },
187 { NAU8825_REG_RDAC, 0x0008 },
188 { NAU8825_REG_MIC_BIAS, 0x0006 },
189 { NAU8825_REG_BOOST, 0x0 },
190 { NAU8825_REG_FEPGA, 0x0 },
191 { NAU8825_REG_POWER_UP_CONTROL, 0x0 },
192 { NAU8825_REG_CHARGE_PUMP, 0x0 },
193};
194
195/* register backup table when cross talk detection */
196static struct reg_default nau8825_xtalk_baktab[] = {
197 { NAU8825_REG_ADC_DGAIN_CTRL, 0 },
198 { NAU8825_REG_HSVOL_CTRL, 0 },
199 { NAU8825_REG_DACL_CTRL, 0 },
200 { NAU8825_REG_DACR_CTRL, 0 },
201};
202
203static const unsigned short logtable[256] = {
204 0x0000, 0x0171, 0x02e0, 0x044e, 0x05ba, 0x0725, 0x088e, 0x09f7,
205 0x0b5d, 0x0cc3, 0x0e27, 0x0f8a, 0x10eb, 0x124b, 0x13aa, 0x1508,
206 0x1664, 0x17bf, 0x1919, 0x1a71, 0x1bc8, 0x1d1e, 0x1e73, 0x1fc6,
207 0x2119, 0x226a, 0x23ba, 0x2508, 0x2656, 0x27a2, 0x28ed, 0x2a37,
208 0x2b80, 0x2cc8, 0x2e0f, 0x2f54, 0x3098, 0x31dc, 0x331e, 0x345f,
209 0x359f, 0x36de, 0x381b, 0x3958, 0x3a94, 0x3bce, 0x3d08, 0x3e41,
210 0x3f78, 0x40af, 0x41e4, 0x4319, 0x444c, 0x457f, 0x46b0, 0x47e1,
211 0x4910, 0x4a3f, 0x4b6c, 0x4c99, 0x4dc5, 0x4eef, 0x5019, 0x5142,
212 0x526a, 0x5391, 0x54b7, 0x55dc, 0x5700, 0x5824, 0x5946, 0x5a68,
213 0x5b89, 0x5ca8, 0x5dc7, 0x5ee5, 0x6003, 0x611f, 0x623a, 0x6355,
214 0x646f, 0x6588, 0x66a0, 0x67b7, 0x68ce, 0x69e4, 0x6af8, 0x6c0c,
215 0x6d20, 0x6e32, 0x6f44, 0x7055, 0x7165, 0x7274, 0x7383, 0x7490,
216 0x759d, 0x76aa, 0x77b5, 0x78c0, 0x79ca, 0x7ad3, 0x7bdb, 0x7ce3,
217 0x7dea, 0x7ef0, 0x7ff6, 0x80fb, 0x81ff, 0x8302, 0x8405, 0x8507,
218 0x8608, 0x8709, 0x8809, 0x8908, 0x8a06, 0x8b04, 0x8c01, 0x8cfe,
219 0x8dfa, 0x8ef5, 0x8fef, 0x90e9, 0x91e2, 0x92db, 0x93d2, 0x94ca,
220 0x95c0, 0x96b6, 0x97ab, 0x98a0, 0x9994, 0x9a87, 0x9b7a, 0x9c6c,
221 0x9d5e, 0x9e4f, 0x9f3f, 0xa02e, 0xa11e, 0xa20c, 0xa2fa, 0xa3e7,
222 0xa4d4, 0xa5c0, 0xa6ab, 0xa796, 0xa881, 0xa96a, 0xaa53, 0xab3c,
223 0xac24, 0xad0c, 0xadf2, 0xaed9, 0xafbe, 0xb0a4, 0xb188, 0xb26c,
224 0xb350, 0xb433, 0xb515, 0xb5f7, 0xb6d9, 0xb7ba, 0xb89a, 0xb97a,
225 0xba59, 0xbb38, 0xbc16, 0xbcf4, 0xbdd1, 0xbead, 0xbf8a, 0xc065,
226 0xc140, 0xc21b, 0xc2f5, 0xc3cf, 0xc4a8, 0xc580, 0xc658, 0xc730,
227 0xc807, 0xc8de, 0xc9b4, 0xca8a, 0xcb5f, 0xcc34, 0xcd08, 0xcddc,
228 0xceaf, 0xcf82, 0xd054, 0xd126, 0xd1f7, 0xd2c8, 0xd399, 0xd469,
229 0xd538, 0xd607, 0xd6d6, 0xd7a4, 0xd872, 0xd93f, 0xda0c, 0xdad9,
230 0xdba5, 0xdc70, 0xdd3b, 0xde06, 0xded0, 0xdf9a, 0xe063, 0xe12c,
231 0xe1f5, 0xe2bd, 0xe385, 0xe44c, 0xe513, 0xe5d9, 0xe69f, 0xe765,
232 0xe82a, 0xe8ef, 0xe9b3, 0xea77, 0xeb3b, 0xebfe, 0xecc1, 0xed83,
233 0xee45, 0xef06, 0xefc8, 0xf088, 0xf149, 0xf209, 0xf2c8, 0xf387,
234 0xf446, 0xf505, 0xf5c3, 0xf680, 0xf73e, 0xf7fb, 0xf8b7, 0xf973,
235 0xfa2f, 0xfaea, 0xfba5, 0xfc60, 0xfd1a, 0xfdd4, 0xfe8e, 0xff47
236};
237
238/**
239 * nau8825_sema_acquire - acquire the semaphore of nau88l25
240 * @nau8825: component to register the codec private data with
241 * @timeout: how long in jiffies to wait before failure or zero to wait
242 * until release
243 *
244 * Attempts to acquire the semaphore with number of jiffies. If no more
245 * tasks are allowed to acquire the semaphore, calling this function will
246 * put the task to sleep. If the semaphore is not released within the
247 * specified number of jiffies, this function returns.
248 * Acquires the semaphore without jiffies. If no more tasks are allowed
249 * to acquire the semaphore, calling this function will put the task to
250 * sleep until the semaphore is released.
251 * If the semaphore is not released within the specified number of jiffies,
252 * this function returns -ETIME.
253 * If the sleep is interrupted by a signal, this function will return -EINTR.
254 * It returns 0 if the semaphore was acquired successfully.
255 */
256static int nau8825_sema_acquire(struct nau8825 *nau8825, long timeout)
257{
258 int ret;
259
260 if (timeout) {
261 ret = down_timeout(&nau8825->xtalk_sem, timeout);
262 if (ret < 0)
263 dev_warn(nau8825->dev, "Acquire semaphone timeout\n");
264 } else {
265 ret = down_interruptible(&nau8825->xtalk_sem);
266 if (ret < 0)
267 dev_warn(nau8825->dev, "Acquire semaphone fail\n");
268 }
269
270 return ret;
271}
272
273/**
274 * nau8825_sema_release - release the semaphore of nau88l25
275 * @nau8825: component to register the codec private data with
276 *
277 * Release the semaphore which may be called from any context and
278 * even by tasks which have never called down().
279 */
280static inline void nau8825_sema_release(struct nau8825 *nau8825)
281{
282 up(&nau8825->xtalk_sem);
283}
284
285/**
286 * nau8825_sema_reset - reset the semaphore for nau88l25
287 * @nau8825: component to register the codec private data with
288 *
289 * Reset the counter of the semaphore. Call this function to restart
290 * a new round task management.
291 */
292static inline void nau8825_sema_reset(struct nau8825 *nau8825)
293{
294 nau8825->xtalk_sem.count = 1;
295}
296
297/**
298 * Ramp up the headphone volume change gradually to target level.
299 *
300 * @nau8825: component to register the codec private data with
301 * @vol_from: the volume to start up
302 * @vol_to: the target volume
303 * @step: the volume span to move on
304 *
305 * The headphone volume is from 0dB to minimum -54dB and -1dB per step.
306 * If the volume changes sharp, there is a pop noise heard in headphone. We
307 * provide the function to ramp up the volume up or down by delaying 10ms
308 * per step.
309 */
310static void nau8825_hpvol_ramp(struct nau8825 *nau8825,
311 unsigned int vol_from, unsigned int vol_to, unsigned int step)
312{
313 unsigned int value, volume, ramp_up, from, to;
314
315 if (vol_from == vol_to || step == 0) {
316 return;
317 } else if (vol_from < vol_to) {
318 ramp_up = true;
319 from = vol_from;
320 to = vol_to;
321 } else {
322 ramp_up = false;
323 from = vol_to;
324 to = vol_from;
325 }
326 /* only handle volume from 0dB to minimum -54dB */
327 if (to > NAU8825_HP_VOL_MIN)
328 to = NAU8825_HP_VOL_MIN;
329
330 for (volume = from; volume < to; volume += step) {
331 if (ramp_up)
332 value = volume;
333 else
334 value = to - volume + from;
335 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
336 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
337 (value << NAU8825_HPL_VOL_SFT) | value);
338 usleep_range(10000, 10500);
339 }
340 if (ramp_up)
341 value = to;
342 else
343 value = from;
344 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSVOL_CTRL,
345 NAU8825_HPL_VOL_MASK | NAU8825_HPR_VOL_MASK,
346 (value << NAU8825_HPL_VOL_SFT) | value);
347}
348
349/**
350 * Computes log10 of a value; the result is round off to 3 decimal. This func-
351 * tion takes reference to dvb-math. The source code locates as the following.
352 * Linux/drivers/media/dvb-core/dvb_math.c
353 *
354 * return log10(value) * 1000
355 */
356static u32 nau8825_intlog10_dec3(u32 value)
357{
358 u32 msb, logentry, significand, interpolation, log10val;
359 u64 log2val;
360
361 /* first detect the msb (count begins at 0) */
362 msb = fls(value) - 1;
363 /**
364 * now we use a logtable after the following method:
365 *
366 * log2(2^x * y) * 2^24 = x * 2^24 + log2(y) * 2^24
367 * where x = msb and therefore 1 <= y < 2
368 * first y is determined by shifting the value left
369 * so that msb is bit 31
370 * 0x00231f56 -> 0x8C7D5800
371 * the result is y * 2^31 -> "significand"
372 * then the highest 9 bits are used for a table lookup
373 * the highest bit is discarded because it's always set
374 * the highest nine bits in our example are 100011000
375 * so we would use the entry 0x18
376 */
377 significand = value << (31 - msb);
378 logentry = (significand >> 23) & 0xff;
379 /**
380 * last step we do is interpolation because of the
381 * limitations of the log table the error is that part of
382 * the significand which isn't used for lookup then we
383 * compute the ratio between the error and the next table entry
384 * and interpolate it between the log table entry used and the
385 * next one the biggest error possible is 0x7fffff
386 * (in our example it's 0x7D5800)
387 * needed value for next table entry is 0x800000
388 * so the interpolation is
389 * (error / 0x800000) * (logtable_next - logtable_current)
390 * in the implementation the division is moved to the end for
391 * better accuracy there is also an overflow correction if
392 * logtable_next is 256
393 */
394 interpolation = ((significand & 0x7fffff) *
395 ((logtable[(logentry + 1) & 0xff] -
396 logtable[logentry]) & 0xffff)) >> 15;
397
398 log2val = ((msb << 24) + (logtable[logentry] << 8) + interpolation);
399 /**
400 * log10(x) = log2(x) * log10(2)
401 */
402 log10val = (log2val * LOG10_MAGIC) >> 31;
403 /**
404 * the result is round off to 3 decimal
405 */
406 return log10val / ((1 << 24) / 1000);
407}
408
409/**
410 * computes cross talk suppression sidetone gain.
411 *
412 * @sig_org: orignal signal level
413 * @sig_cros: cross talk signal level
414 *
415 * The orignal and cross talk signal vlues need to be characterized.
416 * Once these values have been characterized, this sidetone value
417 * can be converted to decibel with the equation below.
418 * sidetone = 20 * log (original signal level / crosstalk signal level)
419 *
420 * return cross talk sidetone gain
421 */
422static u32 nau8825_xtalk_sidetone(u32 sig_org, u32 sig_cros)
423{
424 u32 gain, sidetone;
425
426 if (unlikely(sig_org == 0) || unlikely(sig_cros == 0)) {
427 WARN_ON(1);
428 return 0;
429 }
430
431 sig_org = nau8825_intlog10_dec3(sig_org);
432 sig_cros = nau8825_intlog10_dec3(sig_cros);
433 if (sig_org >= sig_cros)
434 gain = (sig_org - sig_cros) * 20 + GAIN_AUGMENT;
435 else
436 gain = (sig_cros - sig_org) * 20 + GAIN_AUGMENT;
437 sidetone = SIDETONE_BASE - gain * 2;
438 sidetone /= 1000;
439
440 return sidetone;
441}
442
443static int nau8825_xtalk_baktab_index_by_reg(unsigned int reg)
444{
445 int index;
446
447 for (index = 0; index < ARRAY_SIZE(nau8825_xtalk_baktab); index++)
448 if (nau8825_xtalk_baktab[index].reg == reg)
449 return index;
450 return -EINVAL;
451}
452
453static void nau8825_xtalk_backup(struct nau8825 *nau8825)
454{
455 int i;
456
457 /* Backup some register values to backup table */
458 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++)
459 regmap_read(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
460 &nau8825_xtalk_baktab[i].def);
461}
462
463static void nau8825_xtalk_restore(struct nau8825 *nau8825)
464{
465 int i, volume;
466
467 /* Restore register values from backup table; When the driver restores
468 * the headphone volumem, it needs recover to original level gradually
469 * with 3dB per step for less pop noise.
470 */
471 for (i = 0; i < ARRAY_SIZE(nau8825_xtalk_baktab); i++) {
472 if (nau8825_xtalk_baktab[i].reg == NAU8825_REG_HSVOL_CTRL) {
473 /* Ramping up the volume change to reduce pop noise */
474 volume = nau8825_xtalk_baktab[i].def &
475 NAU8825_HPR_VOL_MASK;
476 nau8825_hpvol_ramp(nau8825, 0, volume, 3);
477 continue;
478 }
479 regmap_write(nau8825->regmap, nau8825_xtalk_baktab[i].reg,
480 nau8825_xtalk_baktab[i].def);
481 }
482}
483
484static void nau8825_xtalk_prepare_dac(struct nau8825 *nau8825)
485{
486 /* Enable power of DAC path */
487 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
488 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
489 NAU8825_ENABLE_ADC | NAU8825_ENABLE_ADC_CLK |
490 NAU8825_ENABLE_DAC_CLK, NAU8825_ENABLE_DACR |
491 NAU8825_ENABLE_DACL | NAU8825_ENABLE_ADC |
492 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK);
493 /* Prevent startup click by letting charge pump to ramp up and
494 * change bump enable
495 */
496 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
497 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN,
498 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN);
499 /* Enable clock sync of DAC and DAC clock */
500 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
501 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN |
502 NAU8825_RDAC_FS_BCLK_ENB,
503 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN);
504 /* Power up output driver with 2 stage */
505 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
506 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
507 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L,
508 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
509 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L);
510 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
511 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L,
512 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L);
513 /* HP outputs not shouted to ground */
514 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
515 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L, 0);
516 /* Enable HP boost driver */
517 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
518 NAU8825_HP_BOOST_DIS, NAU8825_HP_BOOST_DIS);
519 /* Enable class G compare path to supply 1.8V or 0.9V. */
520 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLASSG_CTRL,
521 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN,
522 NAU8825_CLASSG_LDAC_EN | NAU8825_CLASSG_RDAC_EN);
523}
524
525static void nau8825_xtalk_prepare_adc(struct nau8825 *nau8825)
526{
527 /* Power up left ADC and raise 5dB than Vmid for Vref */
528 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
529 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK,
530 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_VMID_PLUS_0_5DB);
531}
532
533static void nau8825_xtalk_clock(struct nau8825 *nau8825)
534{
535 /* Recover FLL default value */
536 regmap_write(nau8825->regmap, NAU8825_REG_FLL1, 0x0);
537 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, 0x3126);
538 regmap_write(nau8825->regmap, NAU8825_REG_FLL3, 0x0008);
539 regmap_write(nau8825->regmap, NAU8825_REG_FLL4, 0x0010);
540 regmap_write(nau8825->regmap, NAU8825_REG_FLL5, 0x0);
541 regmap_write(nau8825->regmap, NAU8825_REG_FLL6, 0x6000);
542 /* Enable internal VCO clock for detection signal generated */
543 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
544 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
545 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN,
546 NAU8825_DCO_EN);
547 /* Given specific clock frequency of internal clock to
548 * generate signal.
549 */
550 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
551 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
552 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
553 NAU8825_FLL_RATIO_MASK, 0x10);
554}
555
556static void nau8825_xtalk_prepare(struct nau8825 *nau8825)
557{
558 int volume, index;
559
560 /* Backup those registers changed by cross talk detection */
561 nau8825_xtalk_backup(nau8825);
562 /* Config IIS as master to output signal by codec */
563 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
564 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
565 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_MASTER |
566 (0x2 << NAU8825_I2S_LRC_DIV_SFT) | 0x1);
567 /* Ramp up headphone volume to 0dB to get better performance and
568 * avoid pop noise in headphone.
569 */
570 index = nau8825_xtalk_baktab_index_by_reg(NAU8825_REG_HSVOL_CTRL);
571 if (index != -EINVAL) {
572 volume = nau8825_xtalk_baktab[index].def &
573 NAU8825_HPR_VOL_MASK;
574 nau8825_hpvol_ramp(nau8825, volume, 0, 3);
575 }
576 nau8825_xtalk_clock(nau8825);
577 nau8825_xtalk_prepare_dac(nau8825);
578 nau8825_xtalk_prepare_adc(nau8825);
579 /* Config channel path and digital gain */
580 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
581 NAU8825_DACL_CH_SEL_MASK | NAU8825_DACL_CH_VOL_MASK,
582 NAU8825_DACL_CH_SEL_L | 0xab);
583 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
584 NAU8825_DACR_CH_SEL_MASK | NAU8825_DACR_CH_VOL_MASK,
585 NAU8825_DACR_CH_SEL_R | 0xab);
586 /* Config cross talk parameters and generate the 23Hz sine wave with
587 * 1/16 full scale of signal level for impedance measurement.
588 */
589 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
590 NAU8825_IMM_THD_MASK | NAU8825_IMM_GEN_VOL_MASK |
591 NAU8825_IMM_CYC_MASK | NAU8825_IMM_DAC_SRC_MASK,
592 (0x9 << NAU8825_IMM_THD_SFT) | NAU8825_IMM_GEN_VOL_1_16th |
593 NAU8825_IMM_CYC_8192 | NAU8825_IMM_DAC_SRC_SIN);
594 /* RMS intrruption enable */
595 regmap_update_bits(nau8825->regmap,
596 NAU8825_REG_INTERRUPT_MASK, NAU8825_IRQ_RMS_EN, 0);
597 /* Power up left and right DAC */
598 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
599 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL, 0);
600}
601
602static void nau8825_xtalk_clean_dac(struct nau8825 *nau8825)
603{
604 /* Disable HP boost driver */
605 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
606 NAU8825_HP_BOOST_DIS, 0);
607 /* HP outputs shouted to ground */
608 regmap_update_bits(nau8825->regmap, NAU8825_REG_HSD_CTRL,
609 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
610 NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
611 /* Power down left and right DAC */
612 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
613 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
614 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
615 /* Enable the TESTDAC and disable L/R HP impedance */
616 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
617 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP |
618 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
619 /* Power down output driver with 2 stage */
620 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
621 NAU8825_POWERUP_HP_DRV_R | NAU8825_POWERUP_HP_DRV_L, 0);
622 regmap_update_bits(nau8825->regmap, NAU8825_REG_POWER_UP_CONTROL,
623 NAU8825_POWERUP_INTEGR_R | NAU8825_POWERUP_INTEGR_L |
624 NAU8825_POWERUP_DRV_IN_R | NAU8825_POWERUP_DRV_IN_L, 0);
625 /* Disable clock sync of DAC and DAC clock */
626 regmap_update_bits(nau8825->regmap, NAU8825_REG_RDAC,
627 NAU8825_RDAC_EN | NAU8825_RDAC_CLK_EN, 0);
628 /* Disable charge pump ramp up function and change bump */
629 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
630 NAU8825_JAMNODCLOW | NAU8825_CHANRGE_PUMP_EN, 0);
631 /* Disable power of DAC path */
632 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
633 NAU8825_ENABLE_DACR | NAU8825_ENABLE_DACL |
634 NAU8825_ENABLE_ADC_CLK | NAU8825_ENABLE_DAC_CLK, 0);
635 if (!nau8825->irq)
636 regmap_update_bits(nau8825->regmap,
637 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
638}
639
640static void nau8825_xtalk_clean_adc(struct nau8825 *nau8825)
641{
642 /* Power down left ADC and restore voltage to Vmid */
643 regmap_update_bits(nau8825->regmap, NAU8825_REG_ANALOG_ADC_2,
644 NAU8825_POWERUP_ADCL | NAU8825_ADC_VREFSEL_MASK, 0);
645}
646
647static void nau8825_xtalk_clean(struct nau8825 *nau8825)
648{
649 /* Enable internal VCO needed for interruptions */
650 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
651 nau8825_xtalk_clean_dac(nau8825);
652 nau8825_xtalk_clean_adc(nau8825);
653 /* Clear cross talk parameters and disable */
654 regmap_write(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL, 0);
655 /* RMS intrruption disable */
656 regmap_update_bits(nau8825->regmap, NAU8825_REG_INTERRUPT_MASK,
657 NAU8825_IRQ_RMS_EN, NAU8825_IRQ_RMS_EN);
658 /* Recover default value for IIS */
659 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
660 NAU8825_I2S_MS_MASK | NAU8825_I2S_LRC_DIV_MASK |
661 NAU8825_I2S_BLK_DIV_MASK, NAU8825_I2S_MS_SLAVE);
662 /* Restore value of specific register for cross talk */
663 nau8825_xtalk_restore(nau8825);
664}
665
666static void nau8825_xtalk_imm_start(struct nau8825 *nau8825, int vol)
667{
668 /* Apply ADC volume for better cross talk performance */
669 regmap_update_bits(nau8825->regmap, NAU8825_REG_ADC_DGAIN_CTRL,
670 NAU8825_ADC_DIG_VOL_MASK, vol);
671 /* Disables JKTIP(HPL) DAC channel for right to left measurement.
672 * Do it before sending signal in order to erase pop noise.
673 */
674 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
675 NAU8825_BIAS_TESTDACR_EN | NAU8825_BIAS_TESTDACL_EN,
676 NAU8825_BIAS_TESTDACL_EN);
677 switch (nau8825->xtalk_state) {
678 case NAU8825_XTALK_HPR_R2L:
679 /* Enable right headphone impedance */
680 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
681 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
682 NAU8825_BIAS_HPR_IMP);
683 break;
684 case NAU8825_XTALK_HPL_R2L:
685 /* Enable left headphone impedance */
686 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
687 NAU8825_BIAS_HPR_IMP | NAU8825_BIAS_HPL_IMP,
688 NAU8825_BIAS_HPL_IMP);
689 break;
690 default:
691 break;
692 }
693 msleep(100);
694 /* Impedance measurement mode enable */
695 regmap_update_bits(nau8825->regmap, NAU8825_REG_IMM_MODE_CTRL,
696 NAU8825_IMM_EN, NAU8825_IMM_EN);
697}
698
699static void nau8825_xtalk_imm_stop(struct nau8825 *nau8825)
700{
701 /* Impedance measurement mode disable */
702 regmap_update_bits(nau8825->regmap,
703 NAU8825_REG_IMM_MODE_CTRL, NAU8825_IMM_EN, 0);
704}
705
706/* The cross talk measurement function can reduce cross talk across the
707 * JKTIP(HPL) and JKR1(HPR) outputs which measures the cross talk signal
708 * level to determine what cross talk reduction gain is. This system works by
709 * sending a 23Hz -24dBV sine wave into the headset output DAC and through
710 * the PGA. The output of the PGA is then connected to an internal current
711 * sense which measures the attenuated 23Hz signal and passing the output to
712 * an ADC which converts the measurement to a binary code. With two separated
713 * measurement, one for JKR1(HPR) and the other JKTIP(HPL), measurement data
714 * can be separated read in IMM_RMS_L for HSR and HSL after each measurement.
715 * Thus, the measurement function has four states to complete whole sequence.
716 * 1. Prepare state : Prepare the resource for detection and transfer to HPR
717 * IMM stat to make JKR1(HPR) impedance measure.
718 * 2. HPR IMM state : Read out orignal signal level of JKR1(HPR) and transfer
719 * to HPL IMM state to make JKTIP(HPL) impedance measure.
720 * 3. HPL IMM state : Read out cross talk signal level of JKTIP(HPL) and
721 * transfer to IMM state to determine suppression sidetone gain.
722 * 4. IMM state : Computes cross talk suppression sidetone gain with orignal
723 * and cross talk signal level. Apply this gain and then restore codec
724 * configuration. Then transfer to Done state for ending.
725 */
726static void nau8825_xtalk_measure(struct nau8825 *nau8825)
727{
728 u32 sidetone;
729
730 switch (nau8825->xtalk_state) {
731 case NAU8825_XTALK_PREPARE:
732 /* In prepare state, set up clock, intrruption, DAC path, ADC
733 * path and cross talk detection parameters for preparation.
734 */
735 nau8825_xtalk_prepare(nau8825);
736 msleep(280);
737 /* Trigger right headphone impedance detection */
738 nau8825->xtalk_state = NAU8825_XTALK_HPR_R2L;
739 nau8825_xtalk_imm_start(nau8825, 0x00d2);
740 break;
741 case NAU8825_XTALK_HPR_R2L:
742 /* In right headphone IMM state, read out right headphone
743 * impedance measure result, and then start up left side.
744 */
745 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
746 &nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
747 dev_dbg(nau8825->dev, "HPR_R2L imm: %x\n",
748 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L]);
749 /* Disable then re-enable IMM mode to update */
750 nau8825_xtalk_imm_stop(nau8825);
751 /* Trigger left headphone impedance detection */
752 nau8825->xtalk_state = NAU8825_XTALK_HPL_R2L;
753 nau8825_xtalk_imm_start(nau8825, 0x00ff);
754 break;
755 case NAU8825_XTALK_HPL_R2L:
756 /* In left headphone IMM state, read out left headphone
757 * impedance measure result, and delay some time to wait
758 * detection sine wave output finish. Then, we can calculate
759 * the cross talk suppresstion side tone according to the L/R
760 * headphone imedance.
761 */
762 regmap_read(nau8825->regmap, NAU8825_REG_IMM_RMS_L,
763 &nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
764 dev_dbg(nau8825->dev, "HPL_R2L imm: %x\n",
765 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
766 nau8825_xtalk_imm_stop(nau8825);
767 msleep(150);
768 nau8825->xtalk_state = NAU8825_XTALK_IMM;
769 break;
770 case NAU8825_XTALK_IMM:
771 /* In impedance measure state, the orignal and cross talk
772 * signal level vlues are ready. The side tone gain is deter-
773 * mined with these signal level. After all, restore codec
774 * configuration.
775 */
776 sidetone = nau8825_xtalk_sidetone(
777 nau8825->imp_rms[NAU8825_XTALK_HPR_R2L],
778 nau8825->imp_rms[NAU8825_XTALK_HPL_R2L]);
779 dev_dbg(nau8825->dev, "cross talk sidetone: %x\n", sidetone);
780 regmap_write(nau8825->regmap, NAU8825_REG_DAC_DGAIN_CTRL,
781 (sidetone << 8) | sidetone);
782 nau8825_xtalk_clean(nau8825);
783 nau8825->xtalk_state = NAU8825_XTALK_DONE;
784 break;
785 default:
786 break;
787 }
788}
789
790static void nau8825_xtalk_work(struct work_struct *work)
791{
792 struct nau8825 *nau8825 = container_of(
793 work, struct nau8825, xtalk_work);
794
795 nau8825_xtalk_measure(nau8825);
796 /* To determine the cross talk side tone gain when reach
797 * the impedance measure state.
798 */
799 if (nau8825->xtalk_state == NAU8825_XTALK_IMM)
800 nau8825_xtalk_measure(nau8825);
801
802 /* Delay jack report until cross talk detection process
803 * completed. It can avoid application to do playback
804 * preparation before cross talk detection is still working.
805 * Meanwhile, the protection of the cross talk detection
806 * is released.
807 */
808 if (nau8825->xtalk_state == NAU8825_XTALK_DONE) {
809 snd_soc_jack_report(nau8825->jack, nau8825->xtalk_event,
810 nau8825->xtalk_event_mask);
811 nau8825_sema_release(nau8825);
812 nau8825->xtalk_protect = false;
813 }
814}
815
816static void nau8825_xtalk_cancel(struct nau8825 *nau8825)
817{
818 /* If the xtalk_protect is true, that means the process is still
819 * on going. The driver forces to cancel the cross talk task and
820 * restores the configuration to original status.
821 */
822 if (nau8825->xtalk_protect) {
823 cancel_work_sync(&nau8825->xtalk_work);
824 nau8825_xtalk_clean(nau8825);
825 }
826 /* Reset parameters for cross talk suppression function */
827 nau8825_sema_reset(nau8825);
828 nau8825->xtalk_state = NAU8825_XTALK_DONE;
829 nau8825->xtalk_protect = false;
830}
831
832static bool nau8825_readable_reg(struct device *dev, unsigned int reg)
833{
834 switch (reg) {
835 case NAU8825_REG_ENA_CTRL ... NAU8825_REG_FLL_VCO_RSV:
836 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
837 case NAU8825_REG_INTERRUPT_MASK ... NAU8825_REG_KEYDET_CTRL:
838 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
839 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
840 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
841 case NAU8825_REG_IMM_MODE_CTRL ... NAU8825_REG_IMM_RMS_R:
842 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
843 case NAU8825_REG_MISC_CTRL:
844 case NAU8825_REG_I2C_DEVICE_ID ... NAU8825_REG_SARDOUT_RAM_STATUS:
845 case NAU8825_REG_BIAS_ADJ:
846 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
847 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
848 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
849 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_GENERAL_STATUS:
850 return true;
851 default:
852 return false;
853 }
854
855}
856
857static bool nau8825_writeable_reg(struct device *dev, unsigned int reg)
858{
859 switch (reg) {
860 case NAU8825_REG_RESET ... NAU8825_REG_FLL_VCO_RSV:
861 case NAU8825_REG_HSD_CTRL ... NAU8825_REG_JACK_DET_CTRL:
862 case NAU8825_REG_INTERRUPT_MASK:
863 case NAU8825_REG_INT_CLR_KEY_STATUS ... NAU8825_REG_KEYDET_CTRL:
864 case NAU8825_REG_VDET_THRESHOLD_1 ... NAU8825_REG_DACR_CTRL:
865 case NAU8825_REG_ADC_DRC_KNEE_IP12 ... NAU8825_REG_ADC_DRC_ATKDCY:
866 case NAU8825_REG_DAC_DRC_KNEE_IP12 ... NAU8825_REG_DAC_DRC_ATKDCY:
867 case NAU8825_REG_IMM_MODE_CTRL:
868 case NAU8825_REG_CLASSG_CTRL ... NAU8825_REG_OPT_EFUSE_CTRL:
869 case NAU8825_REG_MISC_CTRL:
870 case NAU8825_REG_BIAS_ADJ:
871 case NAU8825_REG_TRIM_SETTINGS ... NAU8825_REG_ANALOG_CONTROL_2:
872 case NAU8825_REG_ANALOG_ADC_1 ... NAU8825_REG_MIC_BIAS:
873 case NAU8825_REG_BOOST ... NAU8825_REG_FEPGA:
874 case NAU8825_REG_POWER_UP_CONTROL ... NAU8825_REG_CHARGE_PUMP:
875 return true;
876 default:
877 return false;
878 }
879}
880
881static bool nau8825_volatile_reg(struct device *dev, unsigned int reg)
882{
883 switch (reg) {
884 case NAU8825_REG_RESET:
885 case NAU8825_REG_IRQ_STATUS:
886 case NAU8825_REG_INT_CLR_KEY_STATUS:
887 case NAU8825_REG_IMM_RMS_L:
888 case NAU8825_REG_IMM_RMS_R:
889 case NAU8825_REG_I2C_DEVICE_ID:
890 case NAU8825_REG_SARDOUT_RAM_STATUS:
891 case NAU8825_REG_CHARGE_PUMP_INPUT_READ:
892 case NAU8825_REG_GENERAL_STATUS:
893 case NAU8825_REG_BIQ_CTRL ... NAU8825_REG_BIQ_COF10:
894 return true;
895 default:
896 return false;
897 }
898}
899
900static int nau8825_adc_event(struct snd_soc_dapm_widget *w,
901 struct snd_kcontrol *kcontrol, int event)
902{
903 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
904 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
905
906 switch (event) {
907 case SND_SOC_DAPM_POST_PMU:
908 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
909 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
910 break;
911 case SND_SOC_DAPM_POST_PMD:
912 if (!nau8825->irq)
913 regmap_update_bits(nau8825->regmap,
914 NAU8825_REG_ENA_CTRL, NAU8825_ENABLE_ADC, 0);
915 break;
916 default:
917 return -EINVAL;
918 }
919
920 return 0;
921}
922
923static int nau8825_pump_event(struct snd_soc_dapm_widget *w,
924 struct snd_kcontrol *kcontrol, int event)
925{
926 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
927 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
928
929 switch (event) {
930 case SND_SOC_DAPM_POST_PMU:
931 /* Prevent startup click by letting charge pump to ramp up */
932 msleep(10);
933 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
934 NAU8825_JAMNODCLOW, NAU8825_JAMNODCLOW);
935 break;
936 case SND_SOC_DAPM_PRE_PMD:
937 regmap_update_bits(nau8825->regmap, NAU8825_REG_CHARGE_PUMP,
938 NAU8825_JAMNODCLOW, 0);
939 break;
940 default:
941 return -EINVAL;
942 }
943
944 return 0;
945}
946
947static int nau8825_output_dac_event(struct snd_soc_dapm_widget *w,
948 struct snd_kcontrol *kcontrol, int event)
949{
950 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
951 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
952
953 switch (event) {
954 case SND_SOC_DAPM_PRE_PMU:
955 /* Disables the TESTDAC to let DAC signal pass through. */
956 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
957 NAU8825_BIAS_TESTDAC_EN, 0);
958 break;
959 case SND_SOC_DAPM_POST_PMD:
960 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
961 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
962 break;
963 default:
964 return -EINVAL;
965 }
966
967 return 0;
968}
969
970static int nau8825_biq_coeff_get(struct snd_kcontrol *kcontrol,
971 struct snd_ctl_elem_value *ucontrol)
972{
973 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
974 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
975
976 if (!component->regmap)
977 return -EINVAL;
978
979 regmap_raw_read(component->regmap, NAU8825_REG_BIQ_COF1,
980 ucontrol->value.bytes.data, params->max);
981 return 0;
982}
983
984static int nau8825_biq_coeff_put(struct snd_kcontrol *kcontrol,
985 struct snd_ctl_elem_value *ucontrol)
986{
987 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
988 struct soc_bytes_ext *params = (void *)kcontrol->private_value;
989 void *data;
990
991 if (!component->regmap)
992 return -EINVAL;
993
994 data = kmemdup(ucontrol->value.bytes.data,
995 params->max, GFP_KERNEL | GFP_DMA);
996 if (!data)
997 return -ENOMEM;
998
999 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1000 NAU8825_BIQ_WRT_EN, 0);
1001 regmap_raw_write(component->regmap, NAU8825_REG_BIQ_COF1,
1002 data, params->max);
1003 regmap_update_bits(component->regmap, NAU8825_REG_BIQ_CTRL,
1004 NAU8825_BIQ_WRT_EN, NAU8825_BIQ_WRT_EN);
1005
1006 kfree(data);
1007 return 0;
1008}
1009
1010static const char * const nau8825_biq_path[] = {
1011 "ADC", "DAC"
1012};
1013
1014static const struct soc_enum nau8825_biq_path_enum =
1015 SOC_ENUM_SINGLE(NAU8825_REG_BIQ_CTRL, NAU8825_BIQ_PATH_SFT,
1016 ARRAY_SIZE(nau8825_biq_path), nau8825_biq_path);
1017
1018static const char * const nau8825_adc_decimation[] = {
1019 "32", "64", "128", "256"
1020};
1021
1022static const struct soc_enum nau8825_adc_decimation_enum =
1023 SOC_ENUM_SINGLE(NAU8825_REG_ADC_RATE, NAU8825_ADC_SYNC_DOWN_SFT,
1024 ARRAY_SIZE(nau8825_adc_decimation), nau8825_adc_decimation);
1025
1026static const char * const nau8825_dac_oversampl[] = {
1027 "64", "256", "128", "", "32"
1028};
1029
1030static const struct soc_enum nau8825_dac_oversampl_enum =
1031 SOC_ENUM_SINGLE(NAU8825_REG_DAC_CTRL1, NAU8825_DAC_OVERSAMPLE_SFT,
1032 ARRAY_SIZE(nau8825_dac_oversampl), nau8825_dac_oversampl);
1033
1034static const DECLARE_TLV_DB_MINMAX_MUTE(adc_vol_tlv, -10300, 2400);
1035static const DECLARE_TLV_DB_MINMAX_MUTE(sidetone_vol_tlv, -4200, 0);
1036static const DECLARE_TLV_DB_MINMAX(dac_vol_tlv, -5400, 0);
1037static const DECLARE_TLV_DB_MINMAX(fepga_gain_tlv, -100, 3600);
1038static const DECLARE_TLV_DB_MINMAX_MUTE(crosstalk_vol_tlv, -9600, 2400);
1039
1040static const struct snd_kcontrol_new nau8825_controls[] = {
1041 SOC_SINGLE_TLV("Mic Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1042 0, 0xff, 0, adc_vol_tlv),
1043 SOC_DOUBLE_TLV("Headphone Bypass Volume", NAU8825_REG_ADC_DGAIN_CTRL,
1044 12, 8, 0x0f, 0, sidetone_vol_tlv),
1045 SOC_DOUBLE_TLV("Headphone Volume", NAU8825_REG_HSVOL_CTRL,
1046 6, 0, 0x3f, 1, dac_vol_tlv),
1047 SOC_SINGLE_TLV("Frontend PGA Volume", NAU8825_REG_POWER_UP_CONTROL,
1048 8, 37, 0, fepga_gain_tlv),
1049 SOC_DOUBLE_TLV("Headphone Crosstalk Volume", NAU8825_REG_DAC_DGAIN_CTRL,
1050 0, 8, 0xff, 0, crosstalk_vol_tlv),
1051
1052 SOC_ENUM("ADC Decimation Rate", nau8825_adc_decimation_enum),
1053 SOC_ENUM("DAC Oversampling Rate", nau8825_dac_oversampl_enum),
1054 /* programmable biquad filter */
1055 SOC_ENUM("BIQ Path Select", nau8825_biq_path_enum),
1056 SND_SOC_BYTES_EXT("BIQ Coefficients", 20,
1057 nau8825_biq_coeff_get, nau8825_biq_coeff_put),
1058};
1059
1060/* DAC Mux 0x33[9] and 0x34[9] */
1061static const char * const nau8825_dac_src[] = {
1062 "DACL", "DACR",
1063};
1064
1065static SOC_ENUM_SINGLE_DECL(
1066 nau8825_dacl_enum, NAU8825_REG_DACL_CTRL,
1067 NAU8825_DACL_CH_SEL_SFT, nau8825_dac_src);
1068
1069static SOC_ENUM_SINGLE_DECL(
1070 nau8825_dacr_enum, NAU8825_REG_DACR_CTRL,
1071 NAU8825_DACR_CH_SEL_SFT, nau8825_dac_src);
1072
1073static const struct snd_kcontrol_new nau8825_dacl_mux =
1074 SOC_DAPM_ENUM("DACL Source", nau8825_dacl_enum);
1075
1076static const struct snd_kcontrol_new nau8825_dacr_mux =
1077 SOC_DAPM_ENUM("DACR Source", nau8825_dacr_enum);
1078
1079
1080static const struct snd_soc_dapm_widget nau8825_dapm_widgets[] = {
1081 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, NAU8825_REG_I2S_PCM_CTRL2,
1082 15, 1),
1083
1084 SND_SOC_DAPM_INPUT("MIC"),
1085 SND_SOC_DAPM_MICBIAS("MICBIAS", NAU8825_REG_MIC_BIAS, 8, 0),
1086
1087 SND_SOC_DAPM_PGA("Frontend PGA", NAU8825_REG_POWER_UP_CONTROL, 14, 0,
1088 NULL, 0),
1089
1090 SND_SOC_DAPM_ADC_E("ADC", NULL, SND_SOC_NOPM, 0, 0,
1091 nau8825_adc_event, SND_SOC_DAPM_POST_PMU |
1092 SND_SOC_DAPM_POST_PMD),
1093 SND_SOC_DAPM_SUPPLY("ADC Clock", NAU8825_REG_ENA_CTRL, 7, 0, NULL, 0),
1094 SND_SOC_DAPM_SUPPLY("ADC Power", NAU8825_REG_ANALOG_ADC_2, 6, 0, NULL,
1095 0),
1096
1097 /* ADC for button press detection. A dapm supply widget is used to
1098 * prevent dapm_power_widgets keeping the codec at SND_SOC_BIAS_ON
1099 * during suspend.
1100 */
1101 SND_SOC_DAPM_SUPPLY("SAR", NAU8825_REG_SAR_CTRL,
1102 NAU8825_SAR_ADC_EN_SFT, 0, NULL, 0),
1103
1104 SND_SOC_DAPM_PGA_S("ADACL", 2, NAU8825_REG_RDAC, 12, 0, NULL, 0),
1105 SND_SOC_DAPM_PGA_S("ADACR", 2, NAU8825_REG_RDAC, 13, 0, NULL, 0),
1106 SND_SOC_DAPM_PGA_S("ADACL Clock", 3, NAU8825_REG_RDAC, 8, 0, NULL, 0),
1107 SND_SOC_DAPM_PGA_S("ADACR Clock", 3, NAU8825_REG_RDAC, 9, 0, NULL, 0),
1108
1109 SND_SOC_DAPM_DAC("DDACR", NULL, NAU8825_REG_ENA_CTRL,
1110 NAU8825_ENABLE_DACR_SFT, 0),
1111 SND_SOC_DAPM_DAC("DDACL", NULL, NAU8825_REG_ENA_CTRL,
1112 NAU8825_ENABLE_DACL_SFT, 0),
1113 SND_SOC_DAPM_SUPPLY("DDAC Clock", NAU8825_REG_ENA_CTRL, 6, 0, NULL, 0),
1114
1115 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacl_mux),
1116 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8825_dacr_mux),
1117
1118 SND_SOC_DAPM_PGA_S("HP amp L", 0,
1119 NAU8825_REG_CLASSG_CTRL, 1, 0, NULL, 0),
1120 SND_SOC_DAPM_PGA_S("HP amp R", 0,
1121 NAU8825_REG_CLASSG_CTRL, 2, 0, NULL, 0),
1122
1123 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8825_REG_CHARGE_PUMP, 5, 0,
1124 nau8825_pump_event, SND_SOC_DAPM_POST_PMU |
1125 SND_SOC_DAPM_PRE_PMD),
1126
1127 SND_SOC_DAPM_PGA_S("Output Driver R Stage 1", 4,
1128 NAU8825_REG_POWER_UP_CONTROL, 5, 0, NULL, 0),
1129 SND_SOC_DAPM_PGA_S("Output Driver L Stage 1", 4,
1130 NAU8825_REG_POWER_UP_CONTROL, 4, 0, NULL, 0),
1131 SND_SOC_DAPM_PGA_S("Output Driver R Stage 2", 5,
1132 NAU8825_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
1133 SND_SOC_DAPM_PGA_S("Output Driver L Stage 2", 5,
1134 NAU8825_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
1135 SND_SOC_DAPM_PGA_S("Output Driver R Stage 3", 6,
1136 NAU8825_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
1137 SND_SOC_DAPM_PGA_S("Output Driver L Stage 3", 6,
1138 NAU8825_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
1139
1140 SND_SOC_DAPM_PGA_S("Output DACL", 7,
1141 NAU8825_REG_CHARGE_PUMP, 8, 1, nau8825_output_dac_event,
1142 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1143 SND_SOC_DAPM_PGA_S("Output DACR", 7,
1144 NAU8825_REG_CHARGE_PUMP, 9, 1, nau8825_output_dac_event,
1145 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1146
1147 /* HPOL/R are ungrounded by disabling 16 Ohm pull-downs on playback */
1148 SND_SOC_DAPM_PGA_S("HPOL Pulldown", 8,
1149 NAU8825_REG_HSD_CTRL, 0, 1, NULL, 0),
1150 SND_SOC_DAPM_PGA_S("HPOR Pulldown", 8,
1151 NAU8825_REG_HSD_CTRL, 1, 1, NULL, 0),
1152
1153 /* High current HPOL/R boost driver */
1154 SND_SOC_DAPM_PGA_S("HP Boost Driver", 9,
1155 NAU8825_REG_BOOST, 9, 1, NULL, 0),
1156
1157 /* Class G operation control*/
1158 SND_SOC_DAPM_PGA_S("Class G", 10,
1159 NAU8825_REG_CLASSG_CTRL, 0, 0, NULL, 0),
1160
1161 SND_SOC_DAPM_OUTPUT("HPOL"),
1162 SND_SOC_DAPM_OUTPUT("HPOR"),
1163};
1164
1165static const struct snd_soc_dapm_route nau8825_dapm_routes[] = {
1166 {"Frontend PGA", NULL, "MIC"},
1167 {"ADC", NULL, "Frontend PGA"},
1168 {"ADC", NULL, "ADC Clock"},
1169 {"ADC", NULL, "ADC Power"},
1170 {"AIFTX", NULL, "ADC"},
1171
1172 {"DDACL", NULL, "Playback"},
1173 {"DDACR", NULL, "Playback"},
1174 {"DDACL", NULL, "DDAC Clock"},
1175 {"DDACR", NULL, "DDAC Clock"},
1176 {"DACL Mux", "DACL", "DDACL"},
1177 {"DACL Mux", "DACR", "DDACR"},
1178 {"DACR Mux", "DACL", "DDACL"},
1179 {"DACR Mux", "DACR", "DDACR"},
1180 {"HP amp L", NULL, "DACL Mux"},
1181 {"HP amp R", NULL, "DACR Mux"},
1182 {"Charge Pump", NULL, "HP amp L"},
1183 {"Charge Pump", NULL, "HP amp R"},
1184 {"ADACL", NULL, "Charge Pump"},
1185 {"ADACR", NULL, "Charge Pump"},
1186 {"ADACL Clock", NULL, "ADACL"},
1187 {"ADACR Clock", NULL, "ADACR"},
1188 {"Output Driver L Stage 1", NULL, "ADACL Clock"},
1189 {"Output Driver R Stage 1", NULL, "ADACR Clock"},
1190 {"Output Driver L Stage 2", NULL, "Output Driver L Stage 1"},
1191 {"Output Driver R Stage 2", NULL, "Output Driver R Stage 1"},
1192 {"Output Driver L Stage 3", NULL, "Output Driver L Stage 2"},
1193 {"Output Driver R Stage 3", NULL, "Output Driver R Stage 2"},
1194 {"Output DACL", NULL, "Output Driver L Stage 3"},
1195 {"Output DACR", NULL, "Output Driver R Stage 3"},
1196 {"HPOL Pulldown", NULL, "Output DACL"},
1197 {"HPOR Pulldown", NULL, "Output DACR"},
1198 {"HP Boost Driver", NULL, "HPOL Pulldown"},
1199 {"HP Boost Driver", NULL, "HPOR Pulldown"},
1200 {"Class G", NULL, "HP Boost Driver"},
1201 {"HPOL", NULL, "Class G"},
1202 {"HPOR", NULL, "Class G"},
1203};
1204
1205static int nau8825_clock_check(struct nau8825 *nau8825,
1206 int stream, int rate, int osr)
1207{
1208 int osrate;
1209
1210 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1211 if (osr >= ARRAY_SIZE(osr_dac_sel))
1212 return -EINVAL;
1213 osrate = osr_dac_sel[osr].osr;
1214 } else {
1215 if (osr >= ARRAY_SIZE(osr_adc_sel))
1216 return -EINVAL;
1217 osrate = osr_adc_sel[osr].osr;
1218 }
1219
1220 if (!osrate || rate * osr > CLK_DA_AD_MAX) {
1221 dev_err(nau8825->dev, "exceed the maximum frequency of CLK_ADC or CLK_DAC\n");
1222 return -EINVAL;
1223 }
1224
1225 return 0;
1226}
1227
1228static int nau8825_hw_params(struct snd_pcm_substream *substream,
1229 struct snd_pcm_hw_params *params,
1230 struct snd_soc_dai *dai)
1231{
1232 struct snd_soc_codec *codec = dai->codec;
1233 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1234 unsigned int val_len = 0, osr;
1235
1236 nau8825_sema_acquire(nau8825, 3 * HZ);
1237
1238 /* CLK_DAC or CLK_ADC = OSR * FS
1239 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1240 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1241 * values must be selected such that the maximum frequency is less
1242 * than 6.144 MHz.
1243 */
1244 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1245 regmap_read(nau8825->regmap, NAU8825_REG_DAC_CTRL1, &osr);
1246 osr &= NAU8825_DAC_OVERSAMPLE_MASK;
1247 if (nau8825_clock_check(nau8825, substream->stream,
1248 params_rate(params), osr))
1249 return -EINVAL;
1250 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1251 NAU8825_CLK_DAC_SRC_MASK,
1252 osr_dac_sel[osr].clk_src << NAU8825_CLK_DAC_SRC_SFT);
1253 } else {
1254 regmap_read(nau8825->regmap, NAU8825_REG_ADC_RATE, &osr);
1255 osr &= NAU8825_ADC_SYNC_DOWN_MASK;
1256 if (nau8825_clock_check(nau8825, substream->stream,
1257 params_rate(params), osr))
1258 return -EINVAL;
1259 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1260 NAU8825_CLK_ADC_SRC_MASK,
1261 osr_adc_sel[osr].clk_src << NAU8825_CLK_ADC_SRC_SFT);
1262 }
1263
1264 switch (params_width(params)) {
1265 case 16:
1266 val_len |= NAU8825_I2S_DL_16;
1267 break;
1268 case 20:
1269 val_len |= NAU8825_I2S_DL_20;
1270 break;
1271 case 24:
1272 val_len |= NAU8825_I2S_DL_24;
1273 break;
1274 case 32:
1275 val_len |= NAU8825_I2S_DL_32;
1276 break;
1277 default:
1278 return -EINVAL;
1279 }
1280
1281 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1282 NAU8825_I2S_DL_MASK, val_len);
1283
1284 /* Release the semaphone. */
1285 nau8825_sema_release(nau8825);
1286
1287 return 0;
1288}
1289
1290static int nau8825_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
1291{
1292 struct snd_soc_codec *codec = codec_dai->codec;
1293 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1294 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1295
1296 nau8825_sema_acquire(nau8825, 3 * HZ);
1297
1298 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1299 case SND_SOC_DAIFMT_CBM_CFM:
1300 ctrl2_val |= NAU8825_I2S_MS_MASTER;
1301 break;
1302 case SND_SOC_DAIFMT_CBS_CFS:
1303 break;
1304 default:
1305 return -EINVAL;
1306 }
1307
1308 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1309 case SND_SOC_DAIFMT_NB_NF:
1310 break;
1311 case SND_SOC_DAIFMT_IB_NF:
1312 ctrl1_val |= NAU8825_I2S_BP_INV;
1313 break;
1314 default:
1315 return -EINVAL;
1316 }
1317
1318 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1319 case SND_SOC_DAIFMT_I2S:
1320 ctrl1_val |= NAU8825_I2S_DF_I2S;
1321 break;
1322 case SND_SOC_DAIFMT_LEFT_J:
1323 ctrl1_val |= NAU8825_I2S_DF_LEFT;
1324 break;
1325 case SND_SOC_DAIFMT_RIGHT_J:
1326 ctrl1_val |= NAU8825_I2S_DF_RIGTH;
1327 break;
1328 case SND_SOC_DAIFMT_DSP_A:
1329 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1330 break;
1331 case SND_SOC_DAIFMT_DSP_B:
1332 ctrl1_val |= NAU8825_I2S_DF_PCM_AB;
1333 ctrl1_val |= NAU8825_I2S_PCMB_EN;
1334 break;
1335 default:
1336 return -EINVAL;
1337 }
1338
1339 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL1,
1340 NAU8825_I2S_DL_MASK | NAU8825_I2S_DF_MASK |
1341 NAU8825_I2S_BP_MASK | NAU8825_I2S_PCMB_MASK,
1342 ctrl1_val);
1343 regmap_update_bits(nau8825->regmap, NAU8825_REG_I2S_PCM_CTRL2,
1344 NAU8825_I2S_MS_MASK, ctrl2_val);
1345
1346 /* Release the semaphone. */
1347 nau8825_sema_release(nau8825);
1348
1349 return 0;
1350}
1351
1352static const struct snd_soc_dai_ops nau8825_dai_ops = {
1353 .hw_params = nau8825_hw_params,
1354 .set_fmt = nau8825_set_dai_fmt,
1355};
1356
1357#define NAU8825_RATES SNDRV_PCM_RATE_8000_192000
1358#define NAU8825_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1359 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1360
1361static struct snd_soc_dai_driver nau8825_dai = {
1362 .name = "nau8825-hifi",
1363 .playback = {
1364 .stream_name = "Playback",
1365 .channels_min = 1,
1366 .channels_max = 2,
1367 .rates = NAU8825_RATES,
1368 .formats = NAU8825_FORMATS,
1369 },
1370 .capture = {
1371 .stream_name = "Capture",
1372 .channels_min = 1,
1373 .channels_max = 1,
1374 .rates = NAU8825_RATES,
1375 .formats = NAU8825_FORMATS,
1376 },
1377 .ops = &nau8825_dai_ops,
1378};
1379
1380/**
1381 * nau8825_enable_jack_detect - Specify a jack for event reporting
1382 *
1383 * @component: component to register the jack with
1384 * @jack: jack to use to report headset and button events on
1385 *
1386 * After this function has been called the headset insert/remove and button
1387 * events will be routed to the given jack. Jack can be null to stop
1388 * reporting.
1389 */
1390int nau8825_enable_jack_detect(struct snd_soc_codec *codec,
1391 struct snd_soc_jack *jack)
1392{
1393 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1394 struct regmap *regmap = nau8825->regmap;
1395
1396 nau8825->jack = jack;
1397
1398 /* Ground HP Outputs[1:0], needed for headset auto detection
1399 * Enable Automatic Mic/Gnd switching reading on insert interrupt[6]
1400 */
1401 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL,
1402 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L,
1403 NAU8825_HSD_AUTO_MODE | NAU8825_SPKR_DWN1R | NAU8825_SPKR_DWN1L);
1404
1405 return 0;
1406}
1407EXPORT_SYMBOL_GPL(nau8825_enable_jack_detect);
1408
1409
1410static bool nau8825_is_jack_inserted(struct regmap *regmap)
1411{
1412 bool active_high, is_high;
1413 int status, jkdet;
1414
1415 regmap_read(regmap, NAU8825_REG_JACK_DET_CTRL, &jkdet);
1416 active_high = jkdet & NAU8825_JACK_POLARITY;
1417 regmap_read(regmap, NAU8825_REG_I2C_DEVICE_ID, &status);
1418 is_high = status & NAU8825_GPIO2JD1;
1419 /* return jack connection status according to jack insertion logic
1420 * active high or active low.
1421 */
1422 return active_high == is_high;
1423}
1424
1425static void nau8825_restart_jack_detection(struct regmap *regmap)
1426{
1427 /* this will restart the entire jack detection process including MIC/GND
1428 * switching and create interrupts. We have to go from 0 to 1 and back
1429 * to 0 to restart.
1430 */
1431 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1432 NAU8825_JACK_DET_RESTART, NAU8825_JACK_DET_RESTART);
1433 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1434 NAU8825_JACK_DET_RESTART, 0);
1435}
1436
1437static void nau8825_int_status_clear_all(struct regmap *regmap)
1438{
1439 int active_irq, clear_irq, i;
1440
1441 /* Reset the intrruption status from rightmost bit if the corres-
1442 * ponding irq event occurs.
1443 */
1444 regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq);
1445 for (i = 0; i < NAU8825_REG_DATA_LEN; i++) {
1446 clear_irq = (0x1 << i);
1447 if (active_irq & clear_irq)
1448 regmap_write(regmap,
1449 NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1450 }
1451}
1452
1453static void nau8825_eject_jack(struct nau8825 *nau8825)
1454{
1455 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1456 struct regmap *regmap = nau8825->regmap;
1457
1458 /* Force to cancel the cross talk detection process */
1459 nau8825_xtalk_cancel(nau8825);
1460
1461 snd_soc_dapm_disable_pin(dapm, "SAR");
1462 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
1463 /* Detach 2kOhm Resistors from MICBIAS to MICGND1/2 */
1464 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1465 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2, 0);
1466 /* ground HPL/HPR, MICGRND1/2 */
1467 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 0xf, 0xf);
1468
1469 snd_soc_dapm_sync(dapm);
1470
1471 /* Clear all interruption status */
1472 nau8825_int_status_clear_all(regmap);
1473
1474 /* Enable the insertion interruption, disable the ejection inter-
1475 * ruption, and then bypass de-bounce circuit.
1476 */
1477 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
1478 NAU8825_IRQ_EJECT_DIS | NAU8825_IRQ_INSERT_DIS,
1479 NAU8825_IRQ_EJECT_DIS);
1480 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1481 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1482 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_INSERT_EN,
1483 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_EJECT_EN |
1484 NAU8825_IRQ_HEADSET_COMPLETE_EN);
1485 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1486 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
1487
1488 /* Disable ADC needed for interruptions at audo mode */
1489 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1490 NAU8825_ENABLE_ADC, 0);
1491
1492 /* Close clock for jack type detection at manual mode */
1493 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
1494}
1495
1496/* Enable audo mode interruptions with internal clock. */
1497static void nau8825_setup_auto_irq(struct nau8825 *nau8825)
1498{
1499 struct regmap *regmap = nau8825->regmap;
1500
1501 /* Enable headset jack type detection complete interruption and
1502 * jack ejection interruption.
1503 */
1504 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1505 NAU8825_IRQ_HEADSET_COMPLETE_EN | NAU8825_IRQ_EJECT_EN, 0);
1506
1507 /* Enable internal VCO needed for interruptions */
1508 nau8825_configure_sysclk(nau8825, NAU8825_CLK_INTERNAL, 0);
1509
1510 /* Enable ADC needed for interruptions */
1511 regmap_update_bits(regmap, NAU8825_REG_ENA_CTRL,
1512 NAU8825_ENABLE_ADC, NAU8825_ENABLE_ADC);
1513
1514 /* Chip needs one FSCLK cycle in order to generate interruptions,
1515 * as we cannot guarantee one will be provided by the system. Turning
1516 * master mode on then off enables us to generate that FSCLK cycle
1517 * with a minimum of contention on the clock bus.
1518 */
1519 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1520 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_MASTER);
1521 regmap_update_bits(regmap, NAU8825_REG_I2S_PCM_CTRL2,
1522 NAU8825_I2S_MS_MASK, NAU8825_I2S_MS_SLAVE);
1523
1524 /* Not bypass de-bounce circuit */
1525 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1526 NAU8825_JACK_DET_DB_BYPASS, 0);
1527
1528 /* Unmask all interruptions */
1529 regmap_write(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL, 0);
1530
1531 /* Restart the jack detection process at auto mode */
1532 nau8825_restart_jack_detection(regmap);
1533}
1534
1535static int nau8825_button_decode(int value)
1536{
1537 int buttons = 0;
1538
1539 /* The chip supports up to 8 buttons, but ALSA defines only 6 buttons */
1540 if (value & BIT(0))
1541 buttons |= SND_JACK_BTN_0;
1542 if (value & BIT(1))
1543 buttons |= SND_JACK_BTN_1;
1544 if (value & BIT(2))
1545 buttons |= SND_JACK_BTN_2;
1546 if (value & BIT(3))
1547 buttons |= SND_JACK_BTN_3;
1548 if (value & BIT(4))
1549 buttons |= SND_JACK_BTN_4;
1550 if (value & BIT(5))
1551 buttons |= SND_JACK_BTN_5;
1552
1553 return buttons;
1554}
1555
1556static int nau8825_jack_insert(struct nau8825 *nau8825)
1557{
1558 struct regmap *regmap = nau8825->regmap;
1559 struct snd_soc_dapm_context *dapm = nau8825->dapm;
1560 int jack_status_reg, mic_detected;
1561 int type = 0;
1562
1563 regmap_read(regmap, NAU8825_REG_GENERAL_STATUS, &jack_status_reg);
1564 mic_detected = (jack_status_reg >> 10) & 3;
1565 /* The JKSLV and JKR2 all detected in high impedance headset */
1566 if (mic_detected == 0x3)
1567 nau8825->high_imped = true;
1568 else
1569 nau8825->high_imped = false;
1570
1571 switch (mic_detected) {
1572 case 0:
1573 /* no mic */
1574 type = SND_JACK_HEADPHONE;
1575 break;
1576 case 1:
1577 dev_dbg(nau8825->dev, "OMTP (micgnd1) mic connected\n");
1578 type = SND_JACK_HEADSET;
1579
1580 /* Unground MICGND1 */
1581 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1582 1 << 2);
1583 /* Attach 2kOhm Resistor from MICBIAS to MICGND1 */
1584 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1585 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1586 NAU8825_MICBIAS_JKR2);
1587 /* Attach SARADC to MICGND1 */
1588 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1589 NAU8825_SAR_INPUT_MASK,
1590 NAU8825_SAR_INPUT_JKR2);
1591
1592 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1593 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1594 snd_soc_dapm_sync(dapm);
1595 break;
1596 case 2:
1597 case 3:
1598 dev_dbg(nau8825->dev, "CTIA (micgnd2) mic connected\n");
1599 type = SND_JACK_HEADSET;
1600
1601 /* Unground MICGND2 */
1602 regmap_update_bits(regmap, NAU8825_REG_HSD_CTRL, 3 << 2,
1603 2 << 2);
1604 /* Attach 2kOhm Resistor from MICBIAS to MICGND2 */
1605 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1606 NAU8825_MICBIAS_JKSLV | NAU8825_MICBIAS_JKR2,
1607 NAU8825_MICBIAS_JKSLV);
1608 /* Attach SARADC to MICGND2 */
1609 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1610 NAU8825_SAR_INPUT_MASK,
1611 NAU8825_SAR_INPUT_JKSLV);
1612
1613 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
1614 snd_soc_dapm_force_enable_pin(dapm, "SAR");
1615 snd_soc_dapm_sync(dapm);
1616 break;
1617 }
1618
1619 /* Leaving HPOL/R grounded after jack insert by default. They will be
1620 * ungrounded as part of the widget power up sequence at the beginning
1621 * of playback to reduce pop.
1622 */
1623 return type;
1624}
1625
1626#define NAU8825_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
1627 SND_JACK_BTN_2 | SND_JACK_BTN_3)
1628
1629static irqreturn_t nau8825_interrupt(int irq, void *data)
1630{
1631 struct nau8825 *nau8825 = (struct nau8825 *)data;
1632 struct regmap *regmap = nau8825->regmap;
1633 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
1634
1635 if (regmap_read(regmap, NAU8825_REG_IRQ_STATUS, &active_irq)) {
1636 dev_err(nau8825->dev, "failed to read irq status\n");
1637 return IRQ_NONE;
1638 }
1639
1640 if ((active_irq & NAU8825_JACK_EJECTION_IRQ_MASK) ==
1641 NAU8825_JACK_EJECTION_DETECTED) {
1642
1643 nau8825_eject_jack(nau8825);
1644 event_mask |= SND_JACK_HEADSET;
1645 clear_irq = NAU8825_JACK_EJECTION_IRQ_MASK;
1646 } else if (active_irq & NAU8825_KEY_SHORT_PRESS_IRQ) {
1647 int key_status;
1648
1649 regmap_read(regmap, NAU8825_REG_INT_CLR_KEY_STATUS,
1650 &key_status);
1651
1652 /* upper 8 bits of the register are for short pressed keys,
1653 * lower 8 bits - for long pressed buttons
1654 */
1655 nau8825->button_pressed = nau8825_button_decode(
1656 key_status >> 8);
1657
1658 event |= nau8825->button_pressed;
1659 event_mask |= NAU8825_BUTTONS;
1660 clear_irq = NAU8825_KEY_SHORT_PRESS_IRQ;
1661 } else if (active_irq & NAU8825_KEY_RELEASE_IRQ) {
1662 event_mask = NAU8825_BUTTONS;
1663 clear_irq = NAU8825_KEY_RELEASE_IRQ;
1664 } else if (active_irq & NAU8825_HEADSET_COMPLETION_IRQ) {
1665 if (nau8825_is_jack_inserted(regmap)) {
1666 event |= nau8825_jack_insert(nau8825);
1667 if (!nau8825->high_imped) {
1668 /* Apply the cross talk suppression in the
1669 * headset without high impedance.
1670 */
1671 if (!nau8825->xtalk_protect) {
1672 /* Raise protection for cross talk de-
1673 * tection if no protection before.
1674 * The driver has to cancel the pro-
1675 * cess and restore changes if process
1676 * is ongoing when ejection.
1677 */
1678 int ret;
1679 nau8825->xtalk_protect = true;
1680 ret = nau8825_sema_acquire(nau8825, 0);
1681 if (ret < 0)
1682 nau8825->xtalk_protect = false;
1683 }
1684 /* Startup cross talk detection process */
1685 nau8825->xtalk_state = NAU8825_XTALK_PREPARE;
1686 schedule_work(&nau8825->xtalk_work);
1687 } else {
1688 /* The cross talk suppression shouldn't apply
1689 * in the headset with high impedance. Thus,
1690 * relieve the protection raised before.
1691 */
1692 if (nau8825->xtalk_protect) {
1693 nau8825_sema_release(nau8825);
1694 nau8825->xtalk_protect = false;
1695 }
1696 }
1697 } else {
1698 dev_warn(nau8825->dev, "Headset completion IRQ fired but no headset connected\n");
1699 nau8825_eject_jack(nau8825);
1700 }
1701
1702 event_mask |= SND_JACK_HEADSET;
1703 clear_irq = NAU8825_HEADSET_COMPLETION_IRQ;
1704 /* Record the interruption report event for driver to report
1705 * the event later. The jack report will delay until cross
1706 * talk detection process is done.
1707 */
1708 if (nau8825->xtalk_state == NAU8825_XTALK_PREPARE) {
1709 nau8825->xtalk_event = event;
1710 nau8825->xtalk_event_mask = event_mask;
1711 }
1712 } else if (active_irq & NAU8825_IMPEDANCE_MEAS_IRQ) {
1713 schedule_work(&nau8825->xtalk_work);
1714 clear_irq = NAU8825_IMPEDANCE_MEAS_IRQ;
1715 } else if ((active_irq & NAU8825_JACK_INSERTION_IRQ_MASK) ==
1716 NAU8825_JACK_INSERTION_DETECTED) {
1717 /* One more step to check GPIO status directly. Thus, the
1718 * driver can confirm the real insertion interruption because
1719 * the intrruption at manual mode has bypassed debounce
1720 * circuit which can get rid of unstable status.
1721 */
1722 if (nau8825_is_jack_inserted(regmap)) {
1723 /* Turn off insertion interruption at manual mode */
1724 regmap_update_bits(regmap,
1725 NAU8825_REG_INTERRUPT_DIS_CTRL,
1726 NAU8825_IRQ_INSERT_DIS,
1727 NAU8825_IRQ_INSERT_DIS);
1728 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1729 NAU8825_IRQ_INSERT_EN, NAU8825_IRQ_INSERT_EN);
1730 /* Enable interruption for jack type detection at audo
1731 * mode which can detect microphone and jack type.
1732 */
1733 nau8825_setup_auto_irq(nau8825);
1734 }
1735 }
1736
1737 if (!clear_irq)
1738 clear_irq = active_irq;
1739 /* clears the rightmost interruption */
1740 regmap_write(regmap, NAU8825_REG_INT_CLR_KEY_STATUS, clear_irq);
1741
1742 /* Delay jack report until cross talk detection is done. It can avoid
1743 * application to do playback preparation when cross talk detection
1744 * process is still working. Otherwise, the resource like clock and
1745 * power will be issued by them at the same time and conflict happens.
1746 */
1747 if (event_mask && nau8825->xtalk_state == NAU8825_XTALK_DONE)
1748 snd_soc_jack_report(nau8825->jack, event, event_mask);
1749
1750 return IRQ_HANDLED;
1751}
1752
1753static void nau8825_setup_buttons(struct nau8825 *nau8825)
1754{
1755 struct regmap *regmap = nau8825->regmap;
1756
1757 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1758 NAU8825_SAR_TRACKING_GAIN_MASK,
1759 nau8825->sar_voltage << NAU8825_SAR_TRACKING_GAIN_SFT);
1760 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1761 NAU8825_SAR_COMPARE_TIME_MASK,
1762 nau8825->sar_compare_time << NAU8825_SAR_COMPARE_TIME_SFT);
1763 regmap_update_bits(regmap, NAU8825_REG_SAR_CTRL,
1764 NAU8825_SAR_SAMPLING_TIME_MASK,
1765 nau8825->sar_sampling_time << NAU8825_SAR_SAMPLING_TIME_SFT);
1766
1767 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1768 NAU8825_KEYDET_LEVELS_NR_MASK,
1769 (nau8825->sar_threshold_num - 1) << NAU8825_KEYDET_LEVELS_NR_SFT);
1770 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1771 NAU8825_KEYDET_HYSTERESIS_MASK,
1772 nau8825->sar_hysteresis << NAU8825_KEYDET_HYSTERESIS_SFT);
1773 regmap_update_bits(regmap, NAU8825_REG_KEYDET_CTRL,
1774 NAU8825_KEYDET_SHORTKEY_DEBOUNCE_MASK,
1775 nau8825->key_debounce << NAU8825_KEYDET_SHORTKEY_DEBOUNCE_SFT);
1776
1777 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_1,
1778 (nau8825->sar_threshold[0] << 8) | nau8825->sar_threshold[1]);
1779 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_2,
1780 (nau8825->sar_threshold[2] << 8) | nau8825->sar_threshold[3]);
1781 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_3,
1782 (nau8825->sar_threshold[4] << 8) | nau8825->sar_threshold[5]);
1783 regmap_write(regmap, NAU8825_REG_VDET_THRESHOLD_4,
1784 (nau8825->sar_threshold[6] << 8) | nau8825->sar_threshold[7]);
1785
1786 /* Enable short press and release interruptions */
1787 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
1788 NAU8825_IRQ_KEY_SHORT_PRESS_EN | NAU8825_IRQ_KEY_RELEASE_EN,
1789 0);
1790}
1791
1792static void nau8825_init_regs(struct nau8825 *nau8825)
1793{
1794 struct regmap *regmap = nau8825->regmap;
1795
1796 /* Latch IIC LSB value */
1797 regmap_write(regmap, NAU8825_REG_IIC_ADDR_SET, 0x0001);
1798 /* Enable Bias/Vmid */
1799 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1800 NAU8825_BIAS_VMID, NAU8825_BIAS_VMID);
1801 regmap_update_bits(nau8825->regmap, NAU8825_REG_BOOST,
1802 NAU8825_GLOBAL_BIAS_EN, NAU8825_GLOBAL_BIAS_EN);
1803
1804 /* VMID Tieoff */
1805 regmap_update_bits(regmap, NAU8825_REG_BIAS_ADJ,
1806 NAU8825_BIAS_VMID_SEL_MASK,
1807 nau8825->vref_impedance << NAU8825_BIAS_VMID_SEL_SFT);
1808 /* Disable Boost Driver, Automatic Short circuit protection enable */
1809 regmap_update_bits(regmap, NAU8825_REG_BOOST,
1810 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1811 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN,
1812 NAU8825_PRECHARGE_DIS | NAU8825_HP_BOOST_DIS |
1813 NAU8825_HP_BOOST_G_DIS | NAU8825_SHORT_SHUTDOWN_EN);
1814
1815 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1816 NAU8825_JKDET_OUTPUT_EN,
1817 nau8825->jkdet_enable ? 0 : NAU8825_JKDET_OUTPUT_EN);
1818 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1819 NAU8825_JKDET_PULL_EN,
1820 nau8825->jkdet_pull_enable ? 0 : NAU8825_JKDET_PULL_EN);
1821 regmap_update_bits(regmap, NAU8825_REG_GPIO12_CTRL,
1822 NAU8825_JKDET_PULL_UP,
1823 nau8825->jkdet_pull_up ? NAU8825_JKDET_PULL_UP : 0);
1824 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1825 NAU8825_JACK_POLARITY,
1826 /* jkdet_polarity - 1 is for active-low */
1827 nau8825->jkdet_polarity ? 0 : NAU8825_JACK_POLARITY);
1828
1829 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1830 NAU8825_JACK_INSERT_DEBOUNCE_MASK,
1831 nau8825->jack_insert_debounce << NAU8825_JACK_INSERT_DEBOUNCE_SFT);
1832 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
1833 NAU8825_JACK_EJECT_DEBOUNCE_MASK,
1834 nau8825->jack_eject_debounce << NAU8825_JACK_EJECT_DEBOUNCE_SFT);
1835
1836 /* Mask unneeded IRQs: 1 - disable, 0 - enable */
1837 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK, 0x7ff, 0x7ff);
1838
1839 regmap_update_bits(regmap, NAU8825_REG_MIC_BIAS,
1840 NAU8825_MICBIAS_VOLTAGE_MASK, nau8825->micbias_voltage);
1841
1842 if (nau8825->sar_threshold_num)
1843 nau8825_setup_buttons(nau8825);
1844
1845 /* Default oversampling/decimations settings are unusable
1846 * (audible hiss). Set it to something better.
1847 */
1848 regmap_update_bits(regmap, NAU8825_REG_ADC_RATE,
1849 NAU8825_ADC_SYNC_DOWN_MASK | NAU8825_ADC_SINC4_EN,
1850 NAU8825_ADC_SYNC_DOWN_64);
1851 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1852 NAU8825_DAC_OVERSAMPLE_MASK, NAU8825_DAC_OVERSAMPLE_64);
1853 /* Disable DACR/L power */
1854 regmap_update_bits(regmap, NAU8825_REG_CHARGE_PUMP,
1855 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL,
1856 NAU8825_POWER_DOWN_DACR | NAU8825_POWER_DOWN_DACL);
1857 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1858 * signal to avoid any glitches due to power up transients in both
1859 * the analog and digital DAC circuit.
1860 */
1861 regmap_update_bits(nau8825->regmap, NAU8825_REG_BIAS_ADJ,
1862 NAU8825_BIAS_TESTDAC_EN, NAU8825_BIAS_TESTDAC_EN);
1863 /* CICCLP off */
1864 regmap_update_bits(regmap, NAU8825_REG_DAC_CTRL1,
1865 NAU8825_DAC_CLIP_OFF, NAU8825_DAC_CLIP_OFF);
1866
1867 /* Class AB bias current to 2x, DAC Capacitor enable MSB/LSB */
1868 regmap_update_bits(regmap, NAU8825_REG_ANALOG_CONTROL_2,
1869 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1870 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB,
1871 NAU8825_HP_NON_CLASSG_CURRENT_2xADJ |
1872 NAU8825_DAC_CAPACITOR_MSB | NAU8825_DAC_CAPACITOR_LSB);
1873 /* Class G timer 64ms */
1874 regmap_update_bits(regmap, NAU8825_REG_CLASSG_CTRL,
1875 NAU8825_CLASSG_TIMER_MASK,
1876 0x20 << NAU8825_CLASSG_TIMER_SFT);
1877 /* DAC clock delay 2ns, VREF */
1878 regmap_update_bits(regmap, NAU8825_REG_RDAC,
1879 NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK,
1880 (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) |
1881 (0x3 << NAU8825_RDAC_VREF_SFT));
1882 /* Config L/R channel */
1883 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL,
1884 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L);
1885 regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL,
1886 NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R);
1887 /* Disable short Frame Sync detection logic */
1888 regmap_update_bits(regmap, NAU8825_REG_LEFT_TIME_SLOT,
1889 NAU8825_DIS_FS_SHORT_DET, NAU8825_DIS_FS_SHORT_DET);
1890}
1891
1892static const struct regmap_config nau8825_regmap_config = {
1893 .val_bits = NAU8825_REG_DATA_LEN,
1894 .reg_bits = NAU8825_REG_ADDR_LEN,
1895
1896 .max_register = NAU8825_REG_MAX,
1897 .readable_reg = nau8825_readable_reg,
1898 .writeable_reg = nau8825_writeable_reg,
1899 .volatile_reg = nau8825_volatile_reg,
1900
1901 .cache_type = REGCACHE_RBTREE,
1902 .reg_defaults = nau8825_reg_defaults,
1903 .num_reg_defaults = ARRAY_SIZE(nau8825_reg_defaults),
1904};
1905
1906static int nau8825_codec_probe(struct snd_soc_codec *codec)
1907{
1908 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1909 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1910
1911 nau8825->dapm = dapm;
1912
1913 return 0;
1914}
1915
1916static int nau8825_codec_remove(struct snd_soc_codec *codec)
1917{
1918 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
1919
1920 /* Cancel and reset cross tak suppresstion detection funciton */
1921 nau8825_xtalk_cancel(nau8825);
1922
1923 return 0;
1924}
1925
1926/**
1927 * nau8825_calc_fll_param - Calculate FLL parameters.
1928 * @fll_in: external clock provided to codec.
1929 * @fs: sampling rate.
1930 * @fll_param: Pointer to structure of FLL parameters.
1931 *
1932 * Calculate FLL parameters to configure codec.
1933 *
1934 * Returns 0 for success or negative error code.
1935 */
1936static int nau8825_calc_fll_param(unsigned int fll_in, unsigned int fs,
1937 struct nau8825_fll *fll_param)
1938{
1939 u64 fvco, fvco_max;
1940 unsigned int fref, i, fvco_sel;
1941
1942 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1943 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1944 * FREF = freq_in / NAU8825_FLL_REF_DIV_MASK
1945 */
1946 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1947 fref = fll_in / fll_pre_scalar[i].param;
1948 if (fref <= NAU_FREF_MAX)
1949 break;
1950 }
1951 if (i == ARRAY_SIZE(fll_pre_scalar))
1952 return -EINVAL;
1953 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1954
1955 /* Choose the FLL ratio based on FREF */
1956 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1957 if (fref >= fll_ratio[i].param)
1958 break;
1959 }
1960 if (i == ARRAY_SIZE(fll_ratio))
1961 return -EINVAL;
1962 fll_param->ratio = fll_ratio[i].val;
1963
1964 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1965 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1966 * guaranteed across the full range of operation.
1967 * FDCO = freq_out * 2 * mclk_src_scaling
1968 */
1969 fvco_max = 0;
1970 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1971 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1972 fvco = 256 * fs * 2 * mclk_src_scaling[i].param;
1973 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1974 fvco_max < fvco) {
1975 fvco_max = fvco;
1976 fvco_sel = i;
1977 }
1978 }
1979 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1980 return -EINVAL;
1981 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1982
1983 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1984 * input based on FDCO, FREF and FLL ratio.
1985 */
1986 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1987 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1988 fll_param->fll_frac = fvco & 0xFFFF;
1989 return 0;
1990}
1991
1992static void nau8825_fll_apply(struct nau8825 *nau8825,
1993 struct nau8825_fll *fll_param)
1994{
1995 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
1996 NAU8825_CLK_SRC_MASK | NAU8825_CLK_MCLK_SRC_MASK,
1997 NAU8825_CLK_SRC_MCLK | fll_param->mclk_src);
1998 /* Make DSP operate at high speed for better performance. */
1999 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL1,
2000 NAU8825_FLL_RATIO_MASK | NAU8825_ICTRL_LATCH_MASK,
2001 fll_param->ratio | (0x6 << NAU8825_ICTRL_LATCH_SFT));
2002 /* FLL 16-bit fractional input */
2003 regmap_write(nau8825->regmap, NAU8825_REG_FLL2, fll_param->fll_frac);
2004 /* FLL 10-bit integer input */
2005 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL3,
2006 NAU8825_FLL_INTEGER_MASK, fll_param->fll_int);
2007 /* FLL pre-scaler */
2008 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL4,
2009 NAU8825_FLL_REF_DIV_MASK,
2010 fll_param->clk_ref_div << NAU8825_FLL_REF_DIV_SFT);
2011 /* select divided VCO input */
2012 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2013 NAU8825_FLL_CLK_SW_MASK, NAU8825_FLL_CLK_SW_REF);
2014 /* Disable free-running mode */
2015 regmap_update_bits(nau8825->regmap,
2016 NAU8825_REG_FLL6, NAU8825_DCO_EN, 0);
2017 if (fll_param->fll_frac) {
2018 /* set FLL loop filter enable and cutoff frequency at 500Khz */
2019 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2020 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2021 NAU8825_FLL_FTR_SW_MASK,
2022 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2023 NAU8825_FLL_FTR_SW_FILTER);
2024 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2025 NAU8825_SDM_EN | NAU8825_CUTOFF500,
2026 NAU8825_SDM_EN | NAU8825_CUTOFF500);
2027 } else {
2028 /* disable FLL loop filter and cutoff frequency */
2029 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL5,
2030 NAU8825_FLL_PDB_DAC_EN | NAU8825_FLL_LOOP_FTR_EN |
2031 NAU8825_FLL_FTR_SW_MASK, NAU8825_FLL_FTR_SW_ACCU);
2032 regmap_update_bits(nau8825->regmap, NAU8825_REG_FLL6,
2033 NAU8825_SDM_EN | NAU8825_CUTOFF500, 0);
2034 }
2035}
2036
2037/* freq_out must be 256*Fs in order to achieve the best performance */
2038static int nau8825_set_pll(struct snd_soc_codec *codec, int pll_id, int source,
2039 unsigned int freq_in, unsigned int freq_out)
2040{
2041 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2042 struct nau8825_fll fll_param;
2043 int ret, fs;
2044
2045 fs = freq_out / 256;
2046 ret = nau8825_calc_fll_param(freq_in, fs, &fll_param);
2047 if (ret < 0) {
2048 dev_err(codec->dev, "Unsupported input clock %d\n", freq_in);
2049 return ret;
2050 }
2051 dev_dbg(codec->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
2052 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
2053 fll_param.fll_int, fll_param.clk_ref_div);
2054
2055 nau8825_fll_apply(nau8825, &fll_param);
2056 mdelay(2);
2057 regmap_update_bits(nau8825->regmap, NAU8825_REG_CLK_DIVIDER,
2058 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2059 return 0;
2060}
2061
2062static int nau8825_mclk_prepare(struct nau8825 *nau8825, unsigned int freq)
2063{
2064 int ret = 0;
2065
2066 nau8825->mclk = devm_clk_get(nau8825->dev, "mclk");
2067 if (IS_ERR(nau8825->mclk)) {
2068 dev_info(nau8825->dev, "No 'mclk' clock found, assume MCLK is managed externally");
2069 return 0;
2070 }
2071
2072 if (!nau8825->mclk_freq) {
2073 ret = clk_prepare_enable(nau8825->mclk);
2074 if (ret) {
2075 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2076 return ret;
2077 }
2078 }
2079
2080 if (nau8825->mclk_freq != freq) {
2081 freq = clk_round_rate(nau8825->mclk, freq);
2082 ret = clk_set_rate(nau8825->mclk, freq);
2083 if (ret) {
2084 dev_err(nau8825->dev, "Unable to set mclk rate\n");
2085 return ret;
2086 }
2087 nau8825->mclk_freq = freq;
2088 }
2089
2090 return 0;
2091}
2092
2093static void nau8825_configure_mclk_as_sysclk(struct regmap *regmap)
2094{
2095 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2096 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK);
2097 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2098 NAU8825_DCO_EN, 0);
2099 /* Make DSP operate as default setting for power saving. */
2100 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2101 NAU8825_ICTRL_LATCH_MASK, 0);
2102}
2103
2104static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id,
2105 unsigned int freq)
2106{
2107 struct regmap *regmap = nau8825->regmap;
2108 int ret;
2109
2110 switch (clk_id) {
2111 case NAU8825_CLK_DIS:
2112 /* Clock provided externally and disable internal VCO clock */
2113 nau8825_configure_mclk_as_sysclk(regmap);
2114 if (nau8825->mclk_freq) {
2115 clk_disable_unprepare(nau8825->mclk);
2116 nau8825->mclk_freq = 0;
2117 }
2118
2119 break;
2120 case NAU8825_CLK_MCLK:
2121 /* Acquire the semaphone to synchronize the playback and
2122 * interrupt handler. In order to avoid the playback inter-
2123 * fered by cross talk process, the driver make the playback
2124 * preparation halted until cross talk process finish.
2125 */
2126 nau8825_sema_acquire(nau8825, 3 * HZ);
2127 nau8825_configure_mclk_as_sysclk(regmap);
2128 /* MCLK not changed by clock tree */
2129 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2130 NAU8825_CLK_MCLK_SRC_MASK, 0);
2131 /* Release the semaphone. */
2132 nau8825_sema_release(nau8825);
2133
2134 ret = nau8825_mclk_prepare(nau8825, freq);
2135 if (ret)
2136 return ret;
2137
2138 break;
2139 case NAU8825_CLK_INTERNAL:
2140 if (nau8825_is_jack_inserted(nau8825->regmap)) {
2141 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2142 NAU8825_DCO_EN, NAU8825_DCO_EN);
2143 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2144 NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_VCO);
2145 /* Decrease the VCO frequency and make DSP operate
2146 * as default setting for power saving.
2147 */
2148 regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER,
2149 NAU8825_CLK_MCLK_SRC_MASK, 0xf);
2150 regmap_update_bits(regmap, NAU8825_REG_FLL1,
2151 NAU8825_ICTRL_LATCH_MASK |
2152 NAU8825_FLL_RATIO_MASK, 0x10);
2153 regmap_update_bits(regmap, NAU8825_REG_FLL6,
2154 NAU8825_SDM_EN, NAU8825_SDM_EN);
2155 } else {
2156 /* The clock turns off intentionally for power saving
2157 * when no headset connected.
2158 */
2159 nau8825_configure_mclk_as_sysclk(regmap);
2160 dev_warn(nau8825->dev, "Disable clock for power saving when no headset connected\n");
2161 }
2162 if (nau8825->mclk_freq) {
2163 clk_disable_unprepare(nau8825->mclk);
2164 nau8825->mclk_freq = 0;
2165 }
2166
2167 break;
2168 case NAU8825_CLK_FLL_MCLK:
2169 /* Acquire the semaphone to synchronize the playback and
2170 * interrupt handler. In order to avoid the playback inter-
2171 * fered by cross talk process, the driver make the playback
2172 * preparation halted until cross talk process finish.
2173 */
2174 nau8825_sema_acquire(nau8825, 3 * HZ);
2175 /* Higher FLL reference input frequency can only set lower
2176 * gain error, such as 0000 for input reference from MCLK
2177 * 12.288Mhz.
2178 */
2179 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2180 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2181 NAU8825_FLL_CLK_SRC_MCLK | 0);
2182 /* Release the semaphone. */
2183 nau8825_sema_release(nau8825);
2184
2185 ret = nau8825_mclk_prepare(nau8825, freq);
2186 if (ret)
2187 return ret;
2188
2189 break;
2190 case NAU8825_CLK_FLL_BLK:
2191 /* Acquire the semaphone to synchronize the playback and
2192 * interrupt handler. In order to avoid the playback inter-
2193 * fered by cross talk process, the driver make the playback
2194 * preparation halted until cross talk process finish.
2195 */
2196 nau8825_sema_acquire(nau8825, 3 * HZ);
2197 /* If FLL reference input is from low frequency source,
2198 * higher error gain can apply such as 0xf which has
2199 * the most sensitive gain error correction threshold,
2200 * Therefore, FLL has the most accurate DCO to
2201 * target frequency.
2202 */
2203 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2204 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2205 NAU8825_FLL_CLK_SRC_BLK |
2206 (0xf << NAU8825_GAIN_ERR_SFT));
2207 /* Release the semaphone. */
2208 nau8825_sema_release(nau8825);
2209
2210 if (nau8825->mclk_freq) {
2211 clk_disable_unprepare(nau8825->mclk);
2212 nau8825->mclk_freq = 0;
2213 }
2214
2215 break;
2216 case NAU8825_CLK_FLL_FS:
2217 /* Acquire the semaphone to synchronize the playback and
2218 * interrupt handler. In order to avoid the playback inter-
2219 * fered by cross talk process, the driver make the playback
2220 * preparation halted until cross talk process finish.
2221 */
2222 nau8825_sema_acquire(nau8825, 3 * HZ);
2223 /* If FLL reference input is from low frequency source,
2224 * higher error gain can apply such as 0xf which has
2225 * the most sensitive gain error correction threshold,
2226 * Therefore, FLL has the most accurate DCO to
2227 * target frequency.
2228 */
2229 regmap_update_bits(regmap, NAU8825_REG_FLL3,
2230 NAU8825_FLL_CLK_SRC_MASK | NAU8825_GAIN_ERR_MASK,
2231 NAU8825_FLL_CLK_SRC_FS |
2232 (0xf << NAU8825_GAIN_ERR_SFT));
2233 /* Release the semaphone. */
2234 nau8825_sema_release(nau8825);
2235
2236 if (nau8825->mclk_freq) {
2237 clk_disable_unprepare(nau8825->mclk);
2238 nau8825->mclk_freq = 0;
2239 }
2240
2241 break;
2242 default:
2243 dev_err(nau8825->dev, "Invalid clock id (%d)\n", clk_id);
2244 return -EINVAL;
2245 }
2246
2247 dev_dbg(nau8825->dev, "Sysclk is %dHz and clock id is %d\n", freq,
2248 clk_id);
2249 return 0;
2250}
2251
2252static int nau8825_set_sysclk(struct snd_soc_codec *codec, int clk_id,
2253 int source, unsigned int freq, int dir)
2254{
2255 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2256
2257 return nau8825_configure_sysclk(nau8825, clk_id, freq);
2258}
2259
2260static int nau8825_resume_setup(struct nau8825 *nau8825)
2261{
2262 struct regmap *regmap = nau8825->regmap;
2263
2264 /* Close clock when jack type detection at manual mode */
2265 nau8825_configure_sysclk(nau8825, NAU8825_CLK_DIS, 0);
2266
2267 /* Clear all interruption status */
2268 nau8825_int_status_clear_all(regmap);
2269
2270 /* Enable both insertion and ejection interruptions, and then
2271 * bypass de-bounce circuit.
2272 */
2273 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_MASK,
2274 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN |
2275 NAU8825_IRQ_EJECT_EN | NAU8825_IRQ_INSERT_EN,
2276 NAU8825_IRQ_OUTPUT_EN | NAU8825_IRQ_HEADSET_COMPLETE_EN);
2277 regmap_update_bits(regmap, NAU8825_REG_JACK_DET_CTRL,
2278 NAU8825_JACK_DET_DB_BYPASS, NAU8825_JACK_DET_DB_BYPASS);
2279 regmap_update_bits(regmap, NAU8825_REG_INTERRUPT_DIS_CTRL,
2280 NAU8825_IRQ_INSERT_DIS | NAU8825_IRQ_EJECT_DIS, 0);
2281
2282 return 0;
2283}
2284
2285static int nau8825_set_bias_level(struct snd_soc_codec *codec,
2286 enum snd_soc_bias_level level)
2287{
2288 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2289 int ret;
2290
2291 switch (level) {
2292 case SND_SOC_BIAS_ON:
2293 break;
2294
2295 case SND_SOC_BIAS_PREPARE:
2296 break;
2297
2298 case SND_SOC_BIAS_STANDBY:
2299 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
2300 if (nau8825->mclk_freq) {
2301 ret = clk_prepare_enable(nau8825->mclk);
2302 if (ret) {
2303 dev_err(nau8825->dev, "Unable to prepare codec mclk\n");
2304 return ret;
2305 }
2306 }
2307 /* Setup codec configuration after resume */
2308 nau8825_resume_setup(nau8825);
2309 }
2310 break;
2311
2312 case SND_SOC_BIAS_OFF:
2313 /* Cancel and reset cross talk detection funciton */
2314 nau8825_xtalk_cancel(nau8825);
2315 /* Turn off all interruptions before system shutdown. Keep the
2316 * interruption quiet before resume setup completes.
2317 */
2318 regmap_write(nau8825->regmap,
2319 NAU8825_REG_INTERRUPT_DIS_CTRL, 0xffff);
2320 /* Disable ADC needed for interruptions at audo mode */
2321 regmap_update_bits(nau8825->regmap, NAU8825_REG_ENA_CTRL,
2322 NAU8825_ENABLE_ADC, 0);
2323 if (nau8825->mclk_freq)
2324 clk_disable_unprepare(nau8825->mclk);
2325 break;
2326 }
2327 return 0;
2328}
2329
2330static int __maybe_unused nau8825_suspend(struct snd_soc_codec *codec)
2331{
2332 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2333
2334 disable_irq(nau8825->irq);
2335 snd_soc_codec_force_bias_level(codec, SND_SOC_BIAS_OFF);
2336 regcache_cache_only(nau8825->regmap, true);
2337 regcache_mark_dirty(nau8825->regmap);
2338
2339 return 0;
2340}
2341
2342static int __maybe_unused nau8825_resume(struct snd_soc_codec *codec)
2343{
2344 struct nau8825 *nau8825 = snd_soc_codec_get_drvdata(codec);
2345 int ret;
2346
2347 regcache_cache_only(nau8825->regmap, false);
2348 regcache_sync(nau8825->regmap);
2349 nau8825->xtalk_protect = true;
2350 ret = nau8825_sema_acquire(nau8825, 0);
2351 if (ret < 0)
2352 nau8825->xtalk_protect = false;
2353 enable_irq(nau8825->irq);
2354
2355 return 0;
2356}
2357
2358static struct snd_soc_codec_driver nau8825_codec_driver = {
2359 .probe = nau8825_codec_probe,
2360 .remove = nau8825_codec_remove,
2361 .set_sysclk = nau8825_set_sysclk,
2362 .set_pll = nau8825_set_pll,
2363 .set_bias_level = nau8825_set_bias_level,
2364 .suspend_bias_off = true,
2365 .suspend = nau8825_suspend,
2366 .resume = nau8825_resume,
2367
2368 .component_driver = {
2369 .controls = nau8825_controls,
2370 .num_controls = ARRAY_SIZE(nau8825_controls),
2371 .dapm_widgets = nau8825_dapm_widgets,
2372 .num_dapm_widgets = ARRAY_SIZE(nau8825_dapm_widgets),
2373 .dapm_routes = nau8825_dapm_routes,
2374 .num_dapm_routes = ARRAY_SIZE(nau8825_dapm_routes),
2375 },
2376};
2377
2378static void nau8825_reset_chip(struct regmap *regmap)
2379{
2380 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2381 regmap_write(regmap, NAU8825_REG_RESET, 0x00);
2382}
2383
2384static void nau8825_print_device_properties(struct nau8825 *nau8825)
2385{
2386 int i;
2387 struct device *dev = nau8825->dev;
2388
2389 dev_dbg(dev, "jkdet-enable: %d\n", nau8825->jkdet_enable);
2390 dev_dbg(dev, "jkdet-pull-enable: %d\n", nau8825->jkdet_pull_enable);
2391 dev_dbg(dev, "jkdet-pull-up: %d\n", nau8825->jkdet_pull_up);
2392 dev_dbg(dev, "jkdet-polarity: %d\n", nau8825->jkdet_polarity);
2393 dev_dbg(dev, "micbias-voltage: %d\n", nau8825->micbias_voltage);
2394 dev_dbg(dev, "vref-impedance: %d\n", nau8825->vref_impedance);
2395
2396 dev_dbg(dev, "sar-threshold-num: %d\n", nau8825->sar_threshold_num);
2397 for (i = 0; i < nau8825->sar_threshold_num; i++)
2398 dev_dbg(dev, "sar-threshold[%d]=%d\n", i,
2399 nau8825->sar_threshold[i]);
2400
2401 dev_dbg(dev, "sar-hysteresis: %d\n", nau8825->sar_hysteresis);
2402 dev_dbg(dev, "sar-voltage: %d\n", nau8825->sar_voltage);
2403 dev_dbg(dev, "sar-compare-time: %d\n", nau8825->sar_compare_time);
2404 dev_dbg(dev, "sar-sampling-time: %d\n", nau8825->sar_sampling_time);
2405 dev_dbg(dev, "short-key-debounce: %d\n", nau8825->key_debounce);
2406 dev_dbg(dev, "jack-insert-debounce: %d\n",
2407 nau8825->jack_insert_debounce);
2408 dev_dbg(dev, "jack-eject-debounce: %d\n",
2409 nau8825->jack_eject_debounce);
2410}
2411
2412static int nau8825_read_device_properties(struct device *dev,
2413 struct nau8825 *nau8825) {
2414
2415 nau8825->jkdet_enable = device_property_read_bool(dev,
2416 "nuvoton,jkdet-enable");
2417 nau8825->jkdet_pull_enable = device_property_read_bool(dev,
2418 "nuvoton,jkdet-pull-enable");
2419 nau8825->jkdet_pull_up = device_property_read_bool(dev,
2420 "nuvoton,jkdet-pull-up");
2421 device_property_read_u32(dev, "nuvoton,jkdet-polarity",
2422 &nau8825->jkdet_polarity);
2423 device_property_read_u32(dev, "nuvoton,micbias-voltage",
2424 &nau8825->micbias_voltage);
2425 device_property_read_u32(dev, "nuvoton,vref-impedance",
2426 &nau8825->vref_impedance);
2427 device_property_read_u32(dev, "nuvoton,sar-threshold-num",
2428 &nau8825->sar_threshold_num);
2429 device_property_read_u32_array(dev, "nuvoton,sar-threshold",
2430 nau8825->sar_threshold, nau8825->sar_threshold_num);
2431 device_property_read_u32(dev, "nuvoton,sar-hysteresis",
2432 &nau8825->sar_hysteresis);
2433 device_property_read_u32(dev, "nuvoton,sar-voltage",
2434 &nau8825->sar_voltage);
2435 device_property_read_u32(dev, "nuvoton,sar-compare-time",
2436 &nau8825->sar_compare_time);
2437 device_property_read_u32(dev, "nuvoton,sar-sampling-time",
2438 &nau8825->sar_sampling_time);
2439 device_property_read_u32(dev, "nuvoton,short-key-debounce",
2440 &nau8825->key_debounce);
2441 device_property_read_u32(dev, "nuvoton,jack-insert-debounce",
2442 &nau8825->jack_insert_debounce);
2443 device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
2444 &nau8825->jack_eject_debounce);
2445
2446 nau8825->mclk = devm_clk_get(dev, "mclk");
2447 if (PTR_ERR(nau8825->mclk) == -EPROBE_DEFER) {
2448 return -EPROBE_DEFER;
2449 } else if (PTR_ERR(nau8825->mclk) == -ENOENT) {
2450 /* The MCLK is managed externally or not used at all */
2451 nau8825->mclk = NULL;
2452 dev_info(dev, "No 'mclk' clock found, assume MCLK is managed externally");
2453 } else if (IS_ERR(nau8825->mclk)) {
2454 return -EINVAL;
2455 }
2456
2457 return 0;
2458}
2459
2460static int nau8825_setup_irq(struct nau8825 *nau8825)
2461{
2462 int ret;
2463
2464 ret = devm_request_threaded_irq(nau8825->dev, nau8825->irq, NULL,
2465 nau8825_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
2466 "nau8825", nau8825);
2467
2468 if (ret) {
2469 dev_err(nau8825->dev, "Cannot request irq %d (%d)\n",
2470 nau8825->irq, ret);
2471 return ret;
2472 }
2473
2474 return 0;
2475}
2476
2477static int nau8825_i2c_probe(struct i2c_client *i2c,
2478 const struct i2c_device_id *id)
2479{
2480 struct device *dev = &i2c->dev;
2481 struct nau8825 *nau8825 = dev_get_platdata(&i2c->dev);
2482 int ret, value;
2483
2484 if (!nau8825) {
2485 nau8825 = devm_kzalloc(dev, sizeof(*nau8825), GFP_KERNEL);
2486 if (!nau8825)
2487 return -ENOMEM;
2488 ret = nau8825_read_device_properties(dev, nau8825);
2489 if (ret)
2490 return ret;
2491 }
2492
2493 i2c_set_clientdata(i2c, nau8825);
2494
2495 nau8825->regmap = devm_regmap_init_i2c(i2c, &nau8825_regmap_config);
2496 if (IS_ERR(nau8825->regmap))
2497 return PTR_ERR(nau8825->regmap);
2498 nau8825->dev = dev;
2499 nau8825->irq = i2c->irq;
2500 /* Initiate parameters, semaphone and work queue which are needed in
2501 * cross talk suppression measurment function.
2502 */
2503 nau8825->xtalk_state = NAU8825_XTALK_DONE;
2504 nau8825->xtalk_protect = false;
2505 sema_init(&nau8825->xtalk_sem, 1);
2506 INIT_WORK(&nau8825->xtalk_work, nau8825_xtalk_work);
2507
2508 nau8825_print_device_properties(nau8825);
2509
2510 nau8825_reset_chip(nau8825->regmap);
2511 ret = regmap_read(nau8825->regmap, NAU8825_REG_I2C_DEVICE_ID, &value);
2512 if (ret < 0) {
2513 dev_err(dev, "Failed to read device id from the NAU8825: %d\n",
2514 ret);
2515 return ret;
2516 }
2517 if ((value & NAU8825_SOFTWARE_ID_MASK) !=
2518 NAU8825_SOFTWARE_ID_NAU8825) {
2519 dev_err(dev, "Not a NAU8825 chip\n");
2520 return -ENODEV;
2521 }
2522
2523 nau8825_init_regs(nau8825);
2524
2525 if (i2c->irq)
2526 nau8825_setup_irq(nau8825);
2527
2528 return snd_soc_register_codec(&i2c->dev, &nau8825_codec_driver,
2529 &nau8825_dai, 1);
2530}
2531
2532static int nau8825_i2c_remove(struct i2c_client *client)
2533{
2534 snd_soc_unregister_codec(&client->dev);
2535 return 0;
2536}
2537
2538static const struct i2c_device_id nau8825_i2c_ids[] = {
2539 { "nau8825", 0 },
2540 { }
2541};
2542MODULE_DEVICE_TABLE(i2c, nau8825_i2c_ids);
2543
2544#ifdef CONFIG_OF
2545static const struct of_device_id nau8825_of_ids[] = {
2546 { .compatible = "nuvoton,nau8825", },
2547 {}
2548};
2549MODULE_DEVICE_TABLE(of, nau8825_of_ids);
2550#endif
2551
2552#ifdef CONFIG_ACPI
2553static const struct acpi_device_id nau8825_acpi_match[] = {
2554 { "10508825", 0 },
2555 {},
2556};
2557MODULE_DEVICE_TABLE(acpi, nau8825_acpi_match);
2558#endif
2559
2560static struct i2c_driver nau8825_driver = {
2561 .driver = {
2562 .name = "nau8825",
2563 .of_match_table = of_match_ptr(nau8825_of_ids),
2564 .acpi_match_table = ACPI_PTR(nau8825_acpi_match),
2565 },
2566 .probe = nau8825_i2c_probe,
2567 .remove = nau8825_i2c_remove,
2568 .id_table = nau8825_i2c_ids,
2569};
2570module_i2c_driver(nau8825_driver);
2571
2572MODULE_DESCRIPTION("ASoC nau8825 driver");
2573MODULE_AUTHOR("Anatol Pomozov <anatol@chromium.org>");
2574MODULE_LICENSE("GPL");