Loading...
Note: File does not exist in v4.10.11.
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * NAU88L24 ALSA SoC audio driver
4 *
5 * Copyright 2016 Nuvoton Technology Corp.
6 * Author: John Hsu <KCHSU0@nuvoton.com>
7 */
8
9#include <linux/module.h>
10#include <linux/delay.h>
11#include <linux/dmi.h>
12#include <linux/init.h>
13#include <linux/i2c.h>
14#include <linux/regmap.h>
15#include <linux/slab.h>
16#include <linux/clk.h>
17#include <linux/acpi.h>
18#include <linux/math64.h>
19#include <linux/semaphore.h>
20
21#include <sound/initval.h>
22#include <sound/tlv.h>
23#include <sound/core.h>
24#include <sound/pcm.h>
25#include <sound/pcm_params.h>
26#include <sound/soc.h>
27#include <sound/jack.h>
28
29#include "nau8824.h"
30
31#define NAU8824_JD_ACTIVE_HIGH BIT(0)
32#define NAU8824_MONO_SPEAKER BIT(1)
33
34static int nau8824_quirk;
35static int quirk_override = -1;
36module_param_named(quirk, quirk_override, uint, 0444);
37MODULE_PARM_DESC(quirk, "Board-specific quirk override");
38
39static int nau8824_config_sysclk(struct nau8824 *nau8824,
40 int clk_id, unsigned int freq);
41static bool nau8824_is_jack_inserted(struct nau8824 *nau8824);
42
43/* the ADC threshold of headset */
44#define DMIC_CLK 3072000
45
46/* the ADC threshold of headset */
47#define HEADSET_SARADC_THD 0x80
48
49/* the parameter threshold of FLL */
50#define NAU_FREF_MAX 13500000
51#define NAU_FVCO_MAX 100000000
52#define NAU_FVCO_MIN 90000000
53
54/* scaling for mclk from sysclk_src output */
55static const struct nau8824_fll_attr mclk_src_scaling[] = {
56 { 1, 0x0 },
57 { 2, 0x2 },
58 { 4, 0x3 },
59 { 8, 0x4 },
60 { 16, 0x5 },
61 { 32, 0x6 },
62 { 3, 0x7 },
63 { 6, 0xa },
64 { 12, 0xb },
65 { 24, 0xc },
66};
67
68/* ratio for input clk freq */
69static const struct nau8824_fll_attr fll_ratio[] = {
70 { 512000, 0x01 },
71 { 256000, 0x02 },
72 { 128000, 0x04 },
73 { 64000, 0x08 },
74 { 32000, 0x10 },
75 { 8000, 0x20 },
76 { 4000, 0x40 },
77};
78
79static const struct nau8824_fll_attr fll_pre_scalar[] = {
80 { 1, 0x0 },
81 { 2, 0x1 },
82 { 4, 0x2 },
83 { 8, 0x3 },
84};
85
86/* the maximum frequency of CLK_ADC and CLK_DAC */
87#define CLK_DA_AD_MAX 6144000
88
89/* over sampling rate */
90static const struct nau8824_osr_attr osr_dac_sel[] = {
91 { 64, 2 }, /* OSR 64, SRC 1/4 */
92 { 256, 0 }, /* OSR 256, SRC 1 */
93 { 128, 1 }, /* OSR 128, SRC 1/2 */
94 { 0, 0 },
95 { 32, 3 }, /* OSR 32, SRC 1/8 */
96};
97
98static const struct nau8824_osr_attr osr_adc_sel[] = {
99 { 32, 3 }, /* OSR 32, SRC 1/8 */
100 { 64, 2 }, /* OSR 64, SRC 1/4 */
101 { 128, 1 }, /* OSR 128, SRC 1/2 */
102 { 256, 0 }, /* OSR 256, SRC 1 */
103};
104
105static const struct reg_default nau8824_reg_defaults[] = {
106 { NAU8824_REG_ENA_CTRL, 0x0000 },
107 { NAU8824_REG_CLK_GATING_ENA, 0x0000 },
108 { NAU8824_REG_CLK_DIVIDER, 0x0000 },
109 { NAU8824_REG_FLL1, 0x0000 },
110 { NAU8824_REG_FLL2, 0x3126 },
111 { NAU8824_REG_FLL3, 0x0008 },
112 { NAU8824_REG_FLL4, 0x0010 },
113 { NAU8824_REG_FLL5, 0xC000 },
114 { NAU8824_REG_FLL6, 0x6000 },
115 { NAU8824_REG_FLL_VCO_RSV, 0xF13C },
116 { NAU8824_REG_JACK_DET_CTRL, 0x0000 },
117 { NAU8824_REG_INTERRUPT_SETTING_1, 0x0000 },
118 { NAU8824_REG_IRQ, 0x0000 },
119 { NAU8824_REG_CLEAR_INT_REG, 0x0000 },
120 { NAU8824_REG_INTERRUPT_SETTING, 0x1000 },
121 { NAU8824_REG_SAR_ADC, 0x0015 },
122 { NAU8824_REG_VDET_COEFFICIENT, 0x0110 },
123 { NAU8824_REG_VDET_THRESHOLD_1, 0x0000 },
124 { NAU8824_REG_VDET_THRESHOLD_2, 0x0000 },
125 { NAU8824_REG_VDET_THRESHOLD_3, 0x0000 },
126 { NAU8824_REG_VDET_THRESHOLD_4, 0x0000 },
127 { NAU8824_REG_GPIO_SEL, 0x0000 },
128 { NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 0x000B },
129 { NAU8824_REG_PORT0_I2S_PCM_CTRL_2, 0x0010 },
130 { NAU8824_REG_PORT0_LEFT_TIME_SLOT, 0x0000 },
131 { NAU8824_REG_PORT0_RIGHT_TIME_SLOT, 0x0000 },
132 { NAU8824_REG_TDM_CTRL, 0x0000 },
133 { NAU8824_REG_ADC_HPF_FILTER, 0x0000 },
134 { NAU8824_REG_ADC_FILTER_CTRL, 0x0002 },
135 { NAU8824_REG_DAC_FILTER_CTRL_1, 0x0000 },
136 { NAU8824_REG_DAC_FILTER_CTRL_2, 0x0000 },
137 { NAU8824_REG_NOTCH_FILTER_1, 0x0000 },
138 { NAU8824_REG_NOTCH_FILTER_2, 0x0000 },
139 { NAU8824_REG_EQ1_LOW, 0x112C },
140 { NAU8824_REG_EQ2_EQ3, 0x2C2C },
141 { NAU8824_REG_EQ4_EQ5, 0x2C2C },
142 { NAU8824_REG_ADC_CH0_DGAIN_CTRL, 0x0100 },
143 { NAU8824_REG_ADC_CH1_DGAIN_CTRL, 0x0100 },
144 { NAU8824_REG_ADC_CH2_DGAIN_CTRL, 0x0100 },
145 { NAU8824_REG_ADC_CH3_DGAIN_CTRL, 0x0100 },
146 { NAU8824_REG_DAC_MUTE_CTRL, 0x0000 },
147 { NAU8824_REG_DAC_CH0_DGAIN_CTRL, 0x0100 },
148 { NAU8824_REG_DAC_CH1_DGAIN_CTRL, 0x0100 },
149 { NAU8824_REG_ADC_TO_DAC_ST, 0x0000 },
150 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH01, 0x1486 },
151 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH01, 0x0F12 },
152 { NAU8824_REG_DRC_SLOPE_ADC_CH01, 0x25FF },
153 { NAU8824_REG_DRC_ATKDCY_ADC_CH01, 0x3457 },
154 { NAU8824_REG_DRC_KNEE_IP12_ADC_CH23, 0x1486 },
155 { NAU8824_REG_DRC_KNEE_IP34_ADC_CH23, 0x0F12 },
156 { NAU8824_REG_DRC_SLOPE_ADC_CH23, 0x25FF },
157 { NAU8824_REG_DRC_ATKDCY_ADC_CH23, 0x3457 },
158 { NAU8824_REG_DRC_GAINL_ADC0, 0x0200 },
159 { NAU8824_REG_DRC_GAINL_ADC1, 0x0200 },
160 { NAU8824_REG_DRC_GAINL_ADC2, 0x0200 },
161 { NAU8824_REG_DRC_GAINL_ADC3, 0x0200 },
162 { NAU8824_REG_DRC_KNEE_IP12_DAC, 0x1486 },
163 { NAU8824_REG_DRC_KNEE_IP34_DAC, 0x0F12 },
164 { NAU8824_REG_DRC_SLOPE_DAC, 0x25F9 },
165 { NAU8824_REG_DRC_ATKDCY_DAC, 0x3457 },
166 { NAU8824_REG_DRC_GAIN_DAC_CH0, 0x0200 },
167 { NAU8824_REG_DRC_GAIN_DAC_CH1, 0x0200 },
168 { NAU8824_REG_MODE, 0x0000 },
169 { NAU8824_REG_MODE1, 0x0000 },
170 { NAU8824_REG_MODE2, 0x0000 },
171 { NAU8824_REG_CLASSG, 0x0000 },
172 { NAU8824_REG_OTP_EFUSE, 0x0000 },
173 { NAU8824_REG_OTPDOUT_1, 0x0000 },
174 { NAU8824_REG_OTPDOUT_2, 0x0000 },
175 { NAU8824_REG_MISC_CTRL, 0x0000 },
176 { NAU8824_REG_I2C_TIMEOUT, 0xEFFF },
177 { NAU8824_REG_TEST_MODE, 0x0000 },
178 { NAU8824_REG_I2C_DEVICE_ID, 0x1AF1 },
179 { NAU8824_REG_SAR_ADC_DATA_OUT, 0x00FF },
180 { NAU8824_REG_BIAS_ADJ, 0x0000 },
181 { NAU8824_REG_PGA_GAIN, 0x0000 },
182 { NAU8824_REG_TRIM_SETTINGS, 0x0000 },
183 { NAU8824_REG_ANALOG_CONTROL_1, 0x0000 },
184 { NAU8824_REG_ANALOG_CONTROL_2, 0x0000 },
185 { NAU8824_REG_ENABLE_LO, 0x0000 },
186 { NAU8824_REG_GAIN_LO, 0x0000 },
187 { NAU8824_REG_CLASSD_GAIN_1, 0x0000 },
188 { NAU8824_REG_CLASSD_GAIN_2, 0x0000 },
189 { NAU8824_REG_ANALOG_ADC_1, 0x0011 },
190 { NAU8824_REG_ANALOG_ADC_2, 0x0020 },
191 { NAU8824_REG_RDAC, 0x0008 },
192 { NAU8824_REG_MIC_BIAS, 0x0006 },
193 { NAU8824_REG_HS_VOLUME_CONTROL, 0x0000 },
194 { NAU8824_REG_BOOST, 0x0000 },
195 { NAU8824_REG_FEPGA, 0x0000 },
196 { NAU8824_REG_FEPGA_II, 0x0000 },
197 { NAU8824_REG_FEPGA_SE, 0x0000 },
198 { NAU8824_REG_FEPGA_ATTENUATION, 0x0000 },
199 { NAU8824_REG_ATT_PORT0, 0x0000 },
200 { NAU8824_REG_ATT_PORT1, 0x0000 },
201 { NAU8824_REG_POWER_UP_CONTROL, 0x0000 },
202 { NAU8824_REG_CHARGE_PUMP_CONTROL, 0x0300 },
203 { NAU8824_REG_CHARGE_PUMP_INPUT, 0x0013 },
204};
205
206static int nau8824_sema_acquire(struct nau8824 *nau8824, long timeout)
207{
208 int ret;
209
210 if (timeout) {
211 ret = down_timeout(&nau8824->jd_sem, timeout);
212 if (ret < 0)
213 dev_warn(nau8824->dev, "Acquire semaphore timeout\n");
214 } else {
215 ret = down_interruptible(&nau8824->jd_sem);
216 if (ret < 0)
217 dev_warn(nau8824->dev, "Acquire semaphore fail\n");
218 }
219
220 return ret;
221}
222
223static inline void nau8824_sema_release(struct nau8824 *nau8824)
224{
225 up(&nau8824->jd_sem);
226}
227
228static bool nau8824_readable_reg(struct device *dev, unsigned int reg)
229{
230 switch (reg) {
231 case NAU8824_REG_ENA_CTRL ... NAU8824_REG_FLL_VCO_RSV:
232 case NAU8824_REG_JACK_DET_CTRL:
233 case NAU8824_REG_INTERRUPT_SETTING_1:
234 case NAU8824_REG_IRQ:
235 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
236 case NAU8824_REG_GPIO_SEL:
237 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
238 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
239 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
240 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01 ... NAU8824_REG_DRC_GAINL_ADC3:
241 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_GAIN_DAC_CH1:
242 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
243 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
244 case NAU8824_REG_I2C_TIMEOUT:
245 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
246 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
247 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
248 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_INPUT:
249 return true;
250 default:
251 return false;
252 }
253
254}
255
256static bool nau8824_writeable_reg(struct device *dev, unsigned int reg)
257{
258 switch (reg) {
259 case NAU8824_REG_RESET ... NAU8824_REG_FLL_VCO_RSV:
260 case NAU8824_REG_JACK_DET_CTRL:
261 case NAU8824_REG_INTERRUPT_SETTING_1:
262 case NAU8824_REG_CLEAR_INT_REG ... NAU8824_REG_VDET_THRESHOLD_4:
263 case NAU8824_REG_GPIO_SEL:
264 case NAU8824_REG_PORT0_I2S_PCM_CTRL_1 ... NAU8824_REG_TDM_CTRL:
265 case NAU8824_REG_ADC_HPF_FILTER ... NAU8824_REG_EQ4_EQ5:
266 case NAU8824_REG_ADC_CH0_DGAIN_CTRL ... NAU8824_REG_ADC_TO_DAC_ST:
267 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH01:
268 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH01:
269 case NAU8824_REG_DRC_SLOPE_ADC_CH01:
270 case NAU8824_REG_DRC_ATKDCY_ADC_CH01:
271 case NAU8824_REG_DRC_KNEE_IP12_ADC_CH23:
272 case NAU8824_REG_DRC_KNEE_IP34_ADC_CH23:
273 case NAU8824_REG_DRC_SLOPE_ADC_CH23:
274 case NAU8824_REG_DRC_ATKDCY_ADC_CH23:
275 case NAU8824_REG_DRC_KNEE_IP12_DAC ... NAU8824_REG_DRC_ATKDCY_DAC:
276 case NAU8824_REG_CLASSG ... NAU8824_REG_OTP_EFUSE:
277 case NAU8824_REG_I2C_TIMEOUT:
278 case NAU8824_REG_BIAS_ADJ ... NAU8824_REG_CLASSD_GAIN_2:
279 case NAU8824_REG_ANALOG_ADC_1 ... NAU8824_REG_ATT_PORT1:
280 case NAU8824_REG_POWER_UP_CONTROL ... NAU8824_REG_CHARGE_PUMP_CONTROL:
281 return true;
282 default:
283 return false;
284 }
285}
286
287static bool nau8824_volatile_reg(struct device *dev, unsigned int reg)
288{
289 switch (reg) {
290 case NAU8824_REG_RESET:
291 case NAU8824_REG_IRQ ... NAU8824_REG_CLEAR_INT_REG:
292 case NAU8824_REG_DRC_GAINL_ADC0 ... NAU8824_REG_DRC_GAINL_ADC3:
293 case NAU8824_REG_DRC_GAIN_DAC_CH0 ... NAU8824_REG_DRC_GAIN_DAC_CH1:
294 case NAU8824_REG_OTPDOUT_1 ... NAU8824_REG_OTPDOUT_2:
295 case NAU8824_REG_I2C_DEVICE_ID ... NAU8824_REG_SAR_ADC_DATA_OUT:
296 case NAU8824_REG_CHARGE_PUMP_INPUT:
297 return true;
298 default:
299 return false;
300 }
301}
302
303static const char * const nau8824_companding[] = {
304 "Off", "NC", "u-law", "A-law" };
305
306static const struct soc_enum nau8824_companding_adc_enum =
307 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 12,
308 ARRAY_SIZE(nau8824_companding), nau8824_companding);
309
310static const struct soc_enum nau8824_companding_dac_enum =
311 SOC_ENUM_SINGLE(NAU8824_REG_PORT0_I2S_PCM_CTRL_1, 14,
312 ARRAY_SIZE(nau8824_companding), nau8824_companding);
313
314static const char * const nau8824_adc_decimation[] = {
315 "32", "64", "128", "256" };
316
317static const struct soc_enum nau8824_adc_decimation_enum =
318 SOC_ENUM_SINGLE(NAU8824_REG_ADC_FILTER_CTRL, 0,
319 ARRAY_SIZE(nau8824_adc_decimation), nau8824_adc_decimation);
320
321static const char * const nau8824_dac_oversampl[] = {
322 "64", "256", "128", "", "32" };
323
324static const struct soc_enum nau8824_dac_oversampl_enum =
325 SOC_ENUM_SINGLE(NAU8824_REG_DAC_FILTER_CTRL_1, 0,
326 ARRAY_SIZE(nau8824_dac_oversampl), nau8824_dac_oversampl);
327
328static const char * const nau8824_input_channel[] = {
329 "Input CH0", "Input CH1", "Input CH2", "Input CH3" };
330
331static const struct soc_enum nau8824_adc_ch0_enum =
332 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH0_DGAIN_CTRL, 9,
333 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
334
335static const struct soc_enum nau8824_adc_ch1_enum =
336 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH1_DGAIN_CTRL, 9,
337 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
338
339static const struct soc_enum nau8824_adc_ch2_enum =
340 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH2_DGAIN_CTRL, 9,
341 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
342
343static const struct soc_enum nau8824_adc_ch3_enum =
344 SOC_ENUM_SINGLE(NAU8824_REG_ADC_CH3_DGAIN_CTRL, 9,
345 ARRAY_SIZE(nau8824_input_channel), nau8824_input_channel);
346
347static const char * const nau8824_tdm_slot[] = {
348 "Slot 0", "Slot 1", "Slot 2", "Slot 3" };
349
350static const struct soc_enum nau8824_dac_left_sel_enum =
351 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 6,
352 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
353
354static const struct soc_enum nau8824_dac_right_sel_enum =
355 SOC_ENUM_SINGLE(NAU8824_REG_TDM_CTRL, 4,
356 ARRAY_SIZE(nau8824_tdm_slot), nau8824_tdm_slot);
357
358static const DECLARE_TLV_DB_MINMAX_MUTE(spk_vol_tlv, 0, 2400);
359static const DECLARE_TLV_DB_MINMAX(hp_vol_tlv, -3000, 0);
360static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, 0, 200, 0);
361static const DECLARE_TLV_DB_SCALE(dmic_vol_tlv, -12800, 50, 0);
362
363static const struct snd_kcontrol_new nau8824_snd_controls[] = {
364 SOC_ENUM("ADC Companding", nau8824_companding_adc_enum),
365 SOC_ENUM("DAC Companding", nau8824_companding_dac_enum),
366
367 SOC_ENUM("ADC Decimation Rate", nau8824_adc_decimation_enum),
368 SOC_ENUM("DAC Oversampling Rate", nau8824_dac_oversampl_enum),
369
370 SOC_SINGLE_TLV("Speaker Right DACR Volume",
371 NAU8824_REG_CLASSD_GAIN_1, 8, 0x1f, 0, spk_vol_tlv),
372 SOC_SINGLE_TLV("Speaker Left DACL Volume",
373 NAU8824_REG_CLASSD_GAIN_2, 0, 0x1f, 0, spk_vol_tlv),
374 SOC_SINGLE_TLV("Speaker Left DACR Volume",
375 NAU8824_REG_CLASSD_GAIN_1, 0, 0x1f, 0, spk_vol_tlv),
376 SOC_SINGLE_TLV("Speaker Right DACL Volume",
377 NAU8824_REG_CLASSD_GAIN_2, 8, 0x1f, 0, spk_vol_tlv),
378
379 SOC_SINGLE_TLV("Headphone Right DACR Volume",
380 NAU8824_REG_ATT_PORT0, 8, 0x1f, 0, hp_vol_tlv),
381 SOC_SINGLE_TLV("Headphone Left DACL Volume",
382 NAU8824_REG_ATT_PORT0, 0, 0x1f, 0, hp_vol_tlv),
383 SOC_SINGLE_TLV("Headphone Right DACL Volume",
384 NAU8824_REG_ATT_PORT1, 8, 0x1f, 0, hp_vol_tlv),
385 SOC_SINGLE_TLV("Headphone Left DACR Volume",
386 NAU8824_REG_ATT_PORT1, 0, 0x1f, 0, hp_vol_tlv),
387
388 SOC_SINGLE_TLV("MIC1 Volume", NAU8824_REG_FEPGA_II,
389 NAU8824_FEPGA_GAINL_SFT, 0x12, 0, mic_vol_tlv),
390 SOC_SINGLE_TLV("MIC2 Volume", NAU8824_REG_FEPGA_II,
391 NAU8824_FEPGA_GAINR_SFT, 0x12, 0, mic_vol_tlv),
392
393 SOC_SINGLE_TLV("DMIC1 Volume", NAU8824_REG_ADC_CH0_DGAIN_CTRL,
394 0, 0x164, 0, dmic_vol_tlv),
395 SOC_SINGLE_TLV("DMIC2 Volume", NAU8824_REG_ADC_CH1_DGAIN_CTRL,
396 0, 0x164, 0, dmic_vol_tlv),
397 SOC_SINGLE_TLV("DMIC3 Volume", NAU8824_REG_ADC_CH2_DGAIN_CTRL,
398 0, 0x164, 0, dmic_vol_tlv),
399 SOC_SINGLE_TLV("DMIC4 Volume", NAU8824_REG_ADC_CH3_DGAIN_CTRL,
400 0, 0x164, 0, dmic_vol_tlv),
401
402 SOC_ENUM("ADC CH0 Select", nau8824_adc_ch0_enum),
403 SOC_ENUM("ADC CH1 Select", nau8824_adc_ch1_enum),
404 SOC_ENUM("ADC CH2 Select", nau8824_adc_ch2_enum),
405 SOC_ENUM("ADC CH3 Select", nau8824_adc_ch3_enum),
406
407 SOC_SINGLE("ADC CH0 TX Switch", NAU8824_REG_TDM_CTRL, 0, 1, 0),
408 SOC_SINGLE("ADC CH1 TX Switch", NAU8824_REG_TDM_CTRL, 1, 1, 0),
409 SOC_SINGLE("ADC CH2 TX Switch", NAU8824_REG_TDM_CTRL, 2, 1, 0),
410 SOC_SINGLE("ADC CH3 TX Switch", NAU8824_REG_TDM_CTRL, 3, 1, 0),
411
412 SOC_ENUM("DACL Channel Source", nau8824_dac_left_sel_enum),
413 SOC_ENUM("DACR Channel Source", nau8824_dac_right_sel_enum),
414
415 SOC_SINGLE("DACL LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 0, 1, 0),
416 SOC_SINGLE("DACR LR Mix", NAU8824_REG_DAC_MUTE_CTRL, 1, 1, 0),
417
418 SOC_SINGLE("THD for key media",
419 NAU8824_REG_VDET_THRESHOLD_1, 8, 0xff, 0),
420 SOC_SINGLE("THD for key voice command",
421 NAU8824_REG_VDET_THRESHOLD_1, 0, 0xff, 0),
422 SOC_SINGLE("THD for key volume up",
423 NAU8824_REG_VDET_THRESHOLD_2, 8, 0xff, 0),
424 SOC_SINGLE("THD for key volume down",
425 NAU8824_REG_VDET_THRESHOLD_2, 0, 0xff, 0),
426};
427
428static int nau8824_output_dac_event(struct snd_soc_dapm_widget *w,
429 struct snd_kcontrol *kcontrol, int event)
430{
431 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
432 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
433
434 switch (event) {
435 case SND_SOC_DAPM_PRE_PMU:
436 /* Disables the TESTDAC to let DAC signal pass through. */
437 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
438 NAU8824_TEST_DAC_EN, 0);
439 break;
440 case SND_SOC_DAPM_POST_PMD:
441 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENABLE_LO,
442 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
443 break;
444 default:
445 return -EINVAL;
446 }
447
448 return 0;
449}
450
451static int nau8824_spk_event(struct snd_soc_dapm_widget *w,
452 struct snd_kcontrol *kcontrol, int event)
453{
454 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
455 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
456
457 switch (event) {
458 case SND_SOC_DAPM_PRE_PMU:
459 regmap_update_bits(nau8824->regmap,
460 NAU8824_REG_ANALOG_CONTROL_2,
461 NAU8824_CLASSD_CLAMP_DIS, NAU8824_CLASSD_CLAMP_DIS);
462 break;
463 case SND_SOC_DAPM_POST_PMD:
464 regmap_update_bits(nau8824->regmap,
465 NAU8824_REG_ANALOG_CONTROL_2,
466 NAU8824_CLASSD_CLAMP_DIS, 0);
467 break;
468 default:
469 return -EINVAL;
470 }
471
472 return 0;
473}
474
475static int nau8824_pump_event(struct snd_soc_dapm_widget *w,
476 struct snd_kcontrol *kcontrol, int event)
477{
478 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
479 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
480
481 switch (event) {
482 case SND_SOC_DAPM_POST_PMU:
483 /* Prevent startup click by letting charge pump to ramp up */
484 msleep(10);
485 regmap_update_bits(nau8824->regmap,
486 NAU8824_REG_CHARGE_PUMP_CONTROL,
487 NAU8824_JAMNODCLOW, NAU8824_JAMNODCLOW);
488 break;
489 case SND_SOC_DAPM_PRE_PMD:
490 regmap_update_bits(nau8824->regmap,
491 NAU8824_REG_CHARGE_PUMP_CONTROL,
492 NAU8824_JAMNODCLOW, 0);
493 break;
494 default:
495 return -EINVAL;
496 }
497
498 return 0;
499}
500
501static int system_clock_control(struct snd_soc_dapm_widget *w,
502 struct snd_kcontrol *k, int event)
503{
504 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
505 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
506 struct regmap *regmap = nau8824->regmap;
507 unsigned int value;
508 bool clk_fll, error;
509 int ret;
510
511 if (SND_SOC_DAPM_EVENT_OFF(event)) {
512 dev_dbg(nau8824->dev, "system clock control : POWER OFF\n");
513 /* Set clock source to disable or internal clock before the
514 * playback or capture end. Codec needs clock for Jack
515 * detection and button press if jack inserted; otherwise,
516 * the clock should be closed.
517 */
518 if (nau8824_is_jack_inserted(nau8824)) {
519 nau8824_config_sysclk(nau8824,
520 NAU8824_CLK_INTERNAL, 0);
521 } else {
522 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
523 }
524
525 clk_disable_unprepare(nau8824->mclk);
526 } else {
527 dev_dbg(nau8824->dev, "system clock control : POWER ON\n");
528
529 ret = clk_prepare_enable(nau8824->mclk);
530 if (ret)
531 return ret;
532
533 /* Check the clock source setting is proper or not
534 * no matter the source is from FLL or MCLK.
535 */
536 regmap_read(regmap, NAU8824_REG_FLL1, &value);
537 clk_fll = value & NAU8824_FLL_RATIO_MASK;
538 /* It's error to use internal clock when playback */
539 regmap_read(regmap, NAU8824_REG_FLL6, &value);
540 error = value & NAU8824_DCO_EN;
541 if (!error) {
542 /* Check error depending on source is FLL or MCLK. */
543 regmap_read(regmap, NAU8824_REG_CLK_DIVIDER, &value);
544 if (clk_fll)
545 error = !(value & NAU8824_CLK_SRC_VCO);
546 else
547 error = value & NAU8824_CLK_SRC_VCO;
548 }
549 /* Recover the clock source setting if error. */
550 if (error) {
551 if (clk_fll) {
552 regmap_update_bits(regmap,
553 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
554 regmap_update_bits(regmap,
555 NAU8824_REG_CLK_DIVIDER,
556 NAU8824_CLK_SRC_MASK,
557 NAU8824_CLK_SRC_VCO);
558 } else {
559 nau8824_config_sysclk(nau8824,
560 NAU8824_CLK_MCLK, 0);
561 }
562 }
563 }
564
565 return 0;
566}
567
568static int dmic_clock_control(struct snd_soc_dapm_widget *w,
569 struct snd_kcontrol *k, int event)
570{
571 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
572 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
573 int src;
574 unsigned int freq;
575
576 freq = clk_get_rate(nau8824->mclk);
577 if (!freq)
578 freq = nau8824->fs * 256;
579
580 /* The DMIC clock is gotten from system clock (256fs) divided by
581 * DMIC_SRC (1, 2, 4, 8, 16, 32). The clock has to be equal or
582 * less than 3.072 MHz.
583 */
584 for (src = 0; src < 5; src++) {
585 if (freq / (0x1 << src) <= DMIC_CLK)
586 break;
587 }
588 dev_dbg(nau8824->dev, "dmic src %d for mclk %d\n", src, freq);
589 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
590 NAU8824_CLK_DMIC_SRC_MASK, (src << NAU8824_CLK_DMIC_SRC_SFT));
591
592 return 0;
593}
594
595static const struct snd_kcontrol_new nau8824_adc_ch0_dmic =
596 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
597 NAU8824_ADC_CH0_DMIC_SFT, 1, 0);
598
599static const struct snd_kcontrol_new nau8824_adc_ch1_dmic =
600 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
601 NAU8824_ADC_CH1_DMIC_SFT, 1, 0);
602
603static const struct snd_kcontrol_new nau8824_adc_ch2_dmic =
604 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
605 NAU8824_ADC_CH2_DMIC_SFT, 1, 0);
606
607static const struct snd_kcontrol_new nau8824_adc_ch3_dmic =
608 SOC_DAPM_SINGLE("Switch", NAU8824_REG_ENA_CTRL,
609 NAU8824_ADC_CH3_DMIC_SFT, 1, 0);
610
611static const struct snd_kcontrol_new nau8824_adc_left_mixer[] = {
612 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
613 NAU8824_FEPGA_MODEL_MIC1_SFT, 1, 0),
614 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
615 NAU8824_FEPGA_MODEL_HSMIC_SFT, 1, 0),
616};
617
618static const struct snd_kcontrol_new nau8824_adc_right_mixer[] = {
619 SOC_DAPM_SINGLE("MIC Switch", NAU8824_REG_FEPGA,
620 NAU8824_FEPGA_MODER_MIC2_SFT, 1, 0),
621 SOC_DAPM_SINGLE("HSMIC Switch", NAU8824_REG_FEPGA,
622 NAU8824_FEPGA_MODER_HSMIC_SFT, 1, 0),
623};
624
625static const struct snd_kcontrol_new nau8824_hp_left_mixer[] = {
626 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
627 NAU8824_DACR_HPL_EN_SFT, 1, 0),
628 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
629 NAU8824_DACL_HPL_EN_SFT, 1, 0),
630};
631
632static const struct snd_kcontrol_new nau8824_hp_right_mixer[] = {
633 SOC_DAPM_SINGLE("DAC Left Switch", NAU8824_REG_ENABLE_LO,
634 NAU8824_DACL_HPR_EN_SFT, 1, 0),
635 SOC_DAPM_SINGLE("DAC Right Switch", NAU8824_REG_ENABLE_LO,
636 NAU8824_DACR_HPR_EN_SFT, 1, 0),
637};
638
639static const char * const nau8824_dac_src[] = { "DACL", "DACR" };
640
641static SOC_ENUM_SINGLE_DECL(
642 nau8824_dacl_enum, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
643 NAU8824_DAC_CH0_SEL_SFT, nau8824_dac_src);
644
645static SOC_ENUM_SINGLE_DECL(
646 nau8824_dacr_enum, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
647 NAU8824_DAC_CH1_SEL_SFT, nau8824_dac_src);
648
649static const struct snd_kcontrol_new nau8824_dacl_mux =
650 SOC_DAPM_ENUM("DACL Source", nau8824_dacl_enum);
651
652static const struct snd_kcontrol_new nau8824_dacr_mux =
653 SOC_DAPM_ENUM("DACR Source", nau8824_dacr_enum);
654
655
656static const struct snd_soc_dapm_widget nau8824_dapm_widgets[] = {
657 SND_SOC_DAPM_SUPPLY("System Clock", SND_SOC_NOPM, 0, 0,
658 system_clock_control, SND_SOC_DAPM_POST_PMD |
659 SND_SOC_DAPM_POST_PMU),
660
661 SND_SOC_DAPM_INPUT("HSMIC1"),
662 SND_SOC_DAPM_INPUT("HSMIC2"),
663 SND_SOC_DAPM_INPUT("MIC1"),
664 SND_SOC_DAPM_INPUT("MIC2"),
665 SND_SOC_DAPM_INPUT("DMIC1"),
666 SND_SOC_DAPM_INPUT("DMIC2"),
667 SND_SOC_DAPM_INPUT("DMIC3"),
668 SND_SOC_DAPM_INPUT("DMIC4"),
669
670 SND_SOC_DAPM_SUPPLY("SAR", NAU8824_REG_SAR_ADC,
671 NAU8824_SAR_ADC_EN_SFT, 0, NULL, 0),
672 SND_SOC_DAPM_SUPPLY("MICBIAS", NAU8824_REG_MIC_BIAS,
673 NAU8824_MICBIAS_POWERUP_SFT, 0, NULL, 0),
674 SND_SOC_DAPM_SUPPLY("DMIC12 Power", NAU8824_REG_BIAS_ADJ,
675 NAU8824_DMIC1_EN_SFT, 0, NULL, 0),
676 SND_SOC_DAPM_SUPPLY("DMIC34 Power", NAU8824_REG_BIAS_ADJ,
677 NAU8824_DMIC2_EN_SFT, 0, NULL, 0),
678 SND_SOC_DAPM_SUPPLY("DMIC Clock", SND_SOC_NOPM, 0, 0,
679 dmic_clock_control, SND_SOC_DAPM_POST_PMU),
680
681 SND_SOC_DAPM_SWITCH("DMIC1 Enable", SND_SOC_NOPM,
682 0, 0, &nau8824_adc_ch0_dmic),
683 SND_SOC_DAPM_SWITCH("DMIC2 Enable", SND_SOC_NOPM,
684 0, 0, &nau8824_adc_ch1_dmic),
685 SND_SOC_DAPM_SWITCH("DMIC3 Enable", SND_SOC_NOPM,
686 0, 0, &nau8824_adc_ch2_dmic),
687 SND_SOC_DAPM_SWITCH("DMIC4 Enable", SND_SOC_NOPM,
688 0, 0, &nau8824_adc_ch3_dmic),
689
690 SND_SOC_DAPM_MIXER("Left ADC", NAU8824_REG_POWER_UP_CONTROL,
691 12, 0, nau8824_adc_left_mixer,
692 ARRAY_SIZE(nau8824_adc_left_mixer)),
693 SND_SOC_DAPM_MIXER("Right ADC", NAU8824_REG_POWER_UP_CONTROL,
694 13, 0, nau8824_adc_right_mixer,
695 ARRAY_SIZE(nau8824_adc_right_mixer)),
696
697 SND_SOC_DAPM_ADC("ADCL", NULL, NAU8824_REG_ANALOG_ADC_2,
698 NAU8824_ADCL_EN_SFT, 0),
699 SND_SOC_DAPM_ADC("ADCR", NULL, NAU8824_REG_ANALOG_ADC_2,
700 NAU8824_ADCR_EN_SFT, 0),
701
702 SND_SOC_DAPM_AIF_OUT("AIFTX", "Capture", 0, SND_SOC_NOPM, 0, 0),
703 SND_SOC_DAPM_AIF_IN("AIFRX", "Playback", 0, SND_SOC_NOPM, 0, 0),
704
705 SND_SOC_DAPM_DAC("DACL", NULL, NAU8824_REG_RDAC,
706 NAU8824_DACL_EN_SFT, 0),
707 SND_SOC_DAPM_SUPPLY("DACL Clock", NAU8824_REG_RDAC,
708 NAU8824_DACL_CLK_SFT, 0, NULL, 0),
709 SND_SOC_DAPM_DAC("DACR", NULL, NAU8824_REG_RDAC,
710 NAU8824_DACR_EN_SFT, 0),
711 SND_SOC_DAPM_SUPPLY("DACR Clock", NAU8824_REG_RDAC,
712 NAU8824_DACR_CLK_SFT, 0, NULL, 0),
713
714 SND_SOC_DAPM_MUX("DACL Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacl_mux),
715 SND_SOC_DAPM_MUX("DACR Mux", SND_SOC_NOPM, 0, 0, &nau8824_dacr_mux),
716
717 SND_SOC_DAPM_PGA_S("Output DACL", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
718 8, 1, nau8824_output_dac_event,
719 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
720 SND_SOC_DAPM_PGA_S("Output DACR", 0, NAU8824_REG_CHARGE_PUMP_CONTROL,
721 9, 1, nau8824_output_dac_event,
722 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
723
724 SND_SOC_DAPM_PGA_S("ClassD", 0, NAU8824_REG_CLASSD_GAIN_1,
725 NAU8824_CLASSD_EN_SFT, 0, nau8824_spk_event,
726 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
727
728 SND_SOC_DAPM_MIXER("Left Headphone", NAU8824_REG_CLASSG,
729 NAU8824_CLASSG_LDAC_EN_SFT, 0, nau8824_hp_left_mixer,
730 ARRAY_SIZE(nau8824_hp_left_mixer)),
731 SND_SOC_DAPM_MIXER("Right Headphone", NAU8824_REG_CLASSG,
732 NAU8824_CLASSG_RDAC_EN_SFT, 0, nau8824_hp_right_mixer,
733 ARRAY_SIZE(nau8824_hp_right_mixer)),
734 SND_SOC_DAPM_PGA_S("Charge Pump", 1, NAU8824_REG_CHARGE_PUMP_CONTROL,
735 NAU8824_CHARGE_PUMP_EN_SFT, 0, nau8824_pump_event,
736 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
737 SND_SOC_DAPM_PGA("Output Driver L",
738 NAU8824_REG_POWER_UP_CONTROL, 3, 0, NULL, 0),
739 SND_SOC_DAPM_PGA("Output Driver R",
740 NAU8824_REG_POWER_UP_CONTROL, 2, 0, NULL, 0),
741 SND_SOC_DAPM_PGA("Main Driver L",
742 NAU8824_REG_POWER_UP_CONTROL, 1, 0, NULL, 0),
743 SND_SOC_DAPM_PGA("Main Driver R",
744 NAU8824_REG_POWER_UP_CONTROL, 0, 0, NULL, 0),
745 SND_SOC_DAPM_PGA("HP Boost Driver", NAU8824_REG_BOOST,
746 NAU8824_HP_BOOST_DIS_SFT, 1, NULL, 0),
747 SND_SOC_DAPM_PGA("Class G", NAU8824_REG_CLASSG,
748 NAU8824_CLASSG_EN_SFT, 0, NULL, 0),
749
750 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
751 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
752 SND_SOC_DAPM_OUTPUT("HPOL"),
753 SND_SOC_DAPM_OUTPUT("HPOR"),
754};
755
756static const struct snd_soc_dapm_route nau8824_dapm_routes[] = {
757 {"DMIC1 Enable", "Switch", "DMIC1"},
758 {"DMIC2 Enable", "Switch", "DMIC2"},
759 {"DMIC3 Enable", "Switch", "DMIC3"},
760 {"DMIC4 Enable", "Switch", "DMIC4"},
761
762 {"DMIC1", NULL, "DMIC12 Power"},
763 {"DMIC2", NULL, "DMIC12 Power"},
764 {"DMIC3", NULL, "DMIC34 Power"},
765 {"DMIC4", NULL, "DMIC34 Power"},
766 {"DMIC12 Power", NULL, "DMIC Clock"},
767 {"DMIC34 Power", NULL, "DMIC Clock"},
768
769 {"Left ADC", "MIC Switch", "MIC1"},
770 {"Left ADC", "HSMIC Switch", "HSMIC1"},
771 {"Right ADC", "MIC Switch", "MIC2"},
772 {"Right ADC", "HSMIC Switch", "HSMIC2"},
773
774 {"ADCL", NULL, "Left ADC"},
775 {"ADCR", NULL, "Right ADC"},
776
777 {"AIFTX", NULL, "MICBIAS"},
778 {"AIFTX", NULL, "ADCL"},
779 {"AIFTX", NULL, "ADCR"},
780 {"AIFTX", NULL, "DMIC1 Enable"},
781 {"AIFTX", NULL, "DMIC2 Enable"},
782 {"AIFTX", NULL, "DMIC3 Enable"},
783 {"AIFTX", NULL, "DMIC4 Enable"},
784
785 {"AIFTX", NULL, "System Clock"},
786 {"AIFRX", NULL, "System Clock"},
787
788 {"DACL", NULL, "AIFRX"},
789 {"DACL", NULL, "DACL Clock"},
790 {"DACR", NULL, "AIFRX"},
791 {"DACR", NULL, "DACR Clock"},
792
793 {"DACL Mux", "DACL", "DACL"},
794 {"DACL Mux", "DACR", "DACR"},
795 {"DACR Mux", "DACL", "DACL"},
796 {"DACR Mux", "DACR", "DACR"},
797
798 {"Output DACL", NULL, "DACL Mux"},
799 {"Output DACR", NULL, "DACR Mux"},
800
801 {"ClassD", NULL, "Output DACL"},
802 {"ClassD", NULL, "Output DACR"},
803
804 {"Left Headphone", "DAC Left Switch", "Output DACL"},
805 {"Left Headphone", "DAC Right Switch", "Output DACR"},
806 {"Right Headphone", "DAC Left Switch", "Output DACL"},
807 {"Right Headphone", "DAC Right Switch", "Output DACR"},
808
809 {"Charge Pump", NULL, "Left Headphone"},
810 {"Charge Pump", NULL, "Right Headphone"},
811 {"Output Driver L", NULL, "Charge Pump"},
812 {"Output Driver R", NULL, "Charge Pump"},
813 {"Main Driver L", NULL, "Output Driver L"},
814 {"Main Driver R", NULL, "Output Driver R"},
815 {"Class G", NULL, "Main Driver L"},
816 {"Class G", NULL, "Main Driver R"},
817 {"HP Boost Driver", NULL, "Class G"},
818
819 {"SPKOUTL", NULL, "ClassD"},
820 {"SPKOUTR", NULL, "ClassD"},
821 {"HPOL", NULL, "HP Boost Driver"},
822 {"HPOR", NULL, "HP Boost Driver"},
823};
824
825static bool nau8824_is_jack_inserted(struct nau8824 *nau8824)
826{
827 struct snd_soc_jack *jack = nau8824->jack;
828 bool insert = false;
829
830 if (nau8824->irq && jack)
831 insert = jack->status & SND_JACK_HEADPHONE;
832
833 return insert;
834}
835
836static void nau8824_int_status_clear_all(struct regmap *regmap)
837{
838 int active_irq, clear_irq, i;
839
840 /* Reset the intrruption status from rightmost bit if the corres-
841 * ponding irq event occurs.
842 */
843 regmap_read(regmap, NAU8824_REG_IRQ, &active_irq);
844 for (i = 0; i < NAU8824_REG_DATA_LEN; i++) {
845 clear_irq = (0x1 << i);
846 if (active_irq & clear_irq)
847 regmap_write(regmap,
848 NAU8824_REG_CLEAR_INT_REG, clear_irq);
849 }
850}
851
852static void nau8824_eject_jack(struct nau8824 *nau8824)
853{
854 struct snd_soc_dapm_context *dapm = nau8824->dapm;
855 struct regmap *regmap = nau8824->regmap;
856
857 /* Clear all interruption status */
858 nau8824_int_status_clear_all(regmap);
859
860 snd_soc_dapm_disable_pin(dapm, "SAR");
861 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
862 snd_soc_dapm_sync(dapm);
863
864 /* Enable the insertion interruption, disable the ejection
865 * interruption, and then bypass de-bounce circuit.
866 */
867 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
868 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
869 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS,
870 NAU8824_IRQ_KEY_RELEASE_DIS | NAU8824_IRQ_KEY_SHORT_PRESS_DIS |
871 NAU8824_IRQ_EJECT_DIS);
872 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
873 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
874 NAU8824_IRQ_INSERT_EN);
875 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
876 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
877
878 /* Close clock for jack type detection at manual mode */
879 if (dapm->bias_level < SND_SOC_BIAS_PREPARE)
880 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
881}
882
883static void nau8824_jdet_work(struct work_struct *work)
884{
885 struct nau8824 *nau8824 = container_of(
886 work, struct nau8824, jdet_work);
887 struct snd_soc_dapm_context *dapm = nau8824->dapm;
888 struct regmap *regmap = nau8824->regmap;
889 int adc_value, event = 0, event_mask = 0;
890
891 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS");
892 snd_soc_dapm_force_enable_pin(dapm, "SAR");
893 snd_soc_dapm_sync(dapm);
894
895 msleep(100);
896
897 regmap_read(regmap, NAU8824_REG_SAR_ADC_DATA_OUT, &adc_value);
898 adc_value = adc_value & NAU8824_SAR_ADC_DATA_MASK;
899 dev_dbg(nau8824->dev, "SAR ADC data 0x%02x\n", adc_value);
900 if (adc_value < HEADSET_SARADC_THD) {
901 event |= SND_JACK_HEADPHONE;
902
903 snd_soc_dapm_disable_pin(dapm, "SAR");
904 snd_soc_dapm_disable_pin(dapm, "MICBIAS");
905 snd_soc_dapm_sync(dapm);
906 } else {
907 event |= SND_JACK_HEADSET;
908 }
909 event_mask |= SND_JACK_HEADSET;
910 snd_soc_jack_report(nau8824->jack, event, event_mask);
911
912 /* Enable short key press and release interruption. */
913 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
914 NAU8824_IRQ_KEY_RELEASE_DIS |
915 NAU8824_IRQ_KEY_SHORT_PRESS_DIS, 0);
916
917 if (nau8824->resume_lock) {
918 nau8824_sema_release(nau8824);
919 nau8824->resume_lock = false;
920 }
921}
922
923static void nau8824_setup_auto_irq(struct nau8824 *nau8824)
924{
925 struct regmap *regmap = nau8824->regmap;
926
927 /* Enable jack ejection interruption. */
928 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING_1,
929 NAU8824_IRQ_INSERT_EN | NAU8824_IRQ_EJECT_EN,
930 NAU8824_IRQ_EJECT_EN);
931 regmap_update_bits(regmap, NAU8824_REG_INTERRUPT_SETTING,
932 NAU8824_IRQ_EJECT_DIS, 0);
933 /* Enable internal VCO needed for interruptions */
934 if (nau8824->dapm->bias_level < SND_SOC_BIAS_PREPARE)
935 nau8824_config_sysclk(nau8824, NAU8824_CLK_INTERNAL, 0);
936 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
937 NAU8824_JD_SLEEP_MODE, 0);
938}
939
940static int nau8824_button_decode(int value)
941{
942 int buttons = 0;
943
944 /* The chip supports up to 8 buttons, but ALSA defines
945 * only 6 buttons.
946 */
947 if (value & BIT(0))
948 buttons |= SND_JACK_BTN_0;
949 if (value & BIT(1))
950 buttons |= SND_JACK_BTN_1;
951 if (value & BIT(2))
952 buttons |= SND_JACK_BTN_2;
953 if (value & BIT(3))
954 buttons |= SND_JACK_BTN_3;
955 if (value & BIT(4))
956 buttons |= SND_JACK_BTN_4;
957 if (value & BIT(5))
958 buttons |= SND_JACK_BTN_5;
959
960 return buttons;
961}
962
963#define NAU8824_BUTTONS (SND_JACK_BTN_0 | SND_JACK_BTN_1 | \
964 SND_JACK_BTN_2 | SND_JACK_BTN_3)
965
966static irqreturn_t nau8824_interrupt(int irq, void *data)
967{
968 struct nau8824 *nau8824 = (struct nau8824 *)data;
969 struct regmap *regmap = nau8824->regmap;
970 int active_irq, clear_irq = 0, event = 0, event_mask = 0;
971
972 if (regmap_read(regmap, NAU8824_REG_IRQ, &active_irq)) {
973 dev_err(nau8824->dev, "failed to read irq status\n");
974 return IRQ_NONE;
975 }
976 dev_dbg(nau8824->dev, "IRQ %x\n", active_irq);
977
978 if (active_irq & NAU8824_JACK_EJECTION_DETECTED) {
979 nau8824_eject_jack(nau8824);
980 event_mask |= SND_JACK_HEADSET;
981 clear_irq = NAU8824_JACK_EJECTION_DETECTED;
982 /* release semaphore held after resume,
983 * and cancel jack detection
984 */
985 if (nau8824->resume_lock) {
986 nau8824_sema_release(nau8824);
987 nau8824->resume_lock = false;
988 }
989 cancel_work_sync(&nau8824->jdet_work);
990 } else if (active_irq & NAU8824_KEY_SHORT_PRESS_IRQ) {
991 int key_status, button_pressed;
992
993 regmap_read(regmap, NAU8824_REG_CLEAR_INT_REG,
994 &key_status);
995
996 /* lower 8 bits of the register are for pressed keys */
997 button_pressed = nau8824_button_decode(key_status);
998
999 event |= button_pressed;
1000 dev_dbg(nau8824->dev, "button %x pressed\n", event);
1001 event_mask |= NAU8824_BUTTONS;
1002 clear_irq = NAU8824_KEY_SHORT_PRESS_IRQ;
1003 } else if (active_irq & NAU8824_KEY_RELEASE_IRQ) {
1004 event_mask = NAU8824_BUTTONS;
1005 clear_irq = NAU8824_KEY_RELEASE_IRQ;
1006 } else if (active_irq & NAU8824_JACK_INSERTION_DETECTED) {
1007 /* Turn off insertion interruption at manual mode */
1008 regmap_update_bits(regmap,
1009 NAU8824_REG_INTERRUPT_SETTING,
1010 NAU8824_IRQ_INSERT_DIS,
1011 NAU8824_IRQ_INSERT_DIS);
1012 regmap_update_bits(regmap,
1013 NAU8824_REG_INTERRUPT_SETTING_1,
1014 NAU8824_IRQ_INSERT_EN, 0);
1015 /* detect microphone and jack type */
1016 cancel_work_sync(&nau8824->jdet_work);
1017 schedule_work(&nau8824->jdet_work);
1018
1019 /* Enable interruption for jack type detection at audo
1020 * mode which can detect microphone and jack type.
1021 */
1022 nau8824_setup_auto_irq(nau8824);
1023 }
1024
1025 if (!clear_irq)
1026 clear_irq = active_irq;
1027 /* clears the rightmost interruption */
1028 regmap_write(regmap, NAU8824_REG_CLEAR_INT_REG, clear_irq);
1029
1030 if (event_mask)
1031 snd_soc_jack_report(nau8824->jack, event, event_mask);
1032
1033 return IRQ_HANDLED;
1034}
1035
1036static const struct nau8824_osr_attr *
1037nau8824_get_osr(struct nau8824 *nau8824, int stream)
1038{
1039 unsigned int osr;
1040
1041 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1042 regmap_read(nau8824->regmap,
1043 NAU8824_REG_DAC_FILTER_CTRL_1, &osr);
1044 osr &= NAU8824_DAC_OVERSAMPLE_MASK;
1045 if (osr >= ARRAY_SIZE(osr_dac_sel))
1046 return NULL;
1047 return &osr_dac_sel[osr];
1048 } else {
1049 regmap_read(nau8824->regmap,
1050 NAU8824_REG_ADC_FILTER_CTRL, &osr);
1051 osr &= NAU8824_ADC_SYNC_DOWN_MASK;
1052 if (osr >= ARRAY_SIZE(osr_adc_sel))
1053 return NULL;
1054 return &osr_adc_sel[osr];
1055 }
1056}
1057
1058static int nau8824_dai_startup(struct snd_pcm_substream *substream,
1059 struct snd_soc_dai *dai)
1060{
1061 struct snd_soc_component *component = dai->component;
1062 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1063 const struct nau8824_osr_attr *osr;
1064
1065 osr = nau8824_get_osr(nau8824, substream->stream);
1066 if (!osr || !osr->osr)
1067 return -EINVAL;
1068
1069 return snd_pcm_hw_constraint_minmax(substream->runtime,
1070 SNDRV_PCM_HW_PARAM_RATE,
1071 0, CLK_DA_AD_MAX / osr->osr);
1072}
1073
1074static int nau8824_hw_params(struct snd_pcm_substream *substream,
1075 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
1076{
1077 struct snd_soc_component *component = dai->component;
1078 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1079 unsigned int val_len = 0, ctrl_val, bclk_fs, bclk_div;
1080 const struct nau8824_osr_attr *osr;
1081 int err = -EINVAL;
1082
1083 nau8824_sema_acquire(nau8824, HZ);
1084
1085 /* CLK_DAC or CLK_ADC = OSR * FS
1086 * DAC or ADC clock frequency is defined as Over Sampling Rate (OSR)
1087 * multiplied by the audio sample rate (Fs). Note that the OSR and Fs
1088 * values must be selected such that the maximum frequency is less
1089 * than 6.144 MHz.
1090 */
1091 nau8824->fs = params_rate(params);
1092 osr = nau8824_get_osr(nau8824, substream->stream);
1093 if (!osr || !osr->osr)
1094 goto error;
1095 if (nau8824->fs * osr->osr > CLK_DA_AD_MAX)
1096 goto error;
1097 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1098 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1099 NAU8824_CLK_DAC_SRC_MASK,
1100 osr->clk_src << NAU8824_CLK_DAC_SRC_SFT);
1101 else
1102 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1103 NAU8824_CLK_ADC_SRC_MASK,
1104 osr->clk_src << NAU8824_CLK_ADC_SRC_SFT);
1105
1106 /* make BCLK and LRC divde configuration if the codec as master. */
1107 regmap_read(nau8824->regmap,
1108 NAU8824_REG_PORT0_I2S_PCM_CTRL_2, &ctrl_val);
1109 if (ctrl_val & NAU8824_I2S_MS_MASTER) {
1110 /* get the bclk and fs ratio */
1111 bclk_fs = snd_soc_params_to_bclk(params) / nau8824->fs;
1112 if (bclk_fs <= 32)
1113 bclk_div = 0x3;
1114 else if (bclk_fs <= 64)
1115 bclk_div = 0x2;
1116 else if (bclk_fs <= 128)
1117 bclk_div = 0x1;
1118 else if (bclk_fs <= 256)
1119 bclk_div = 0;
1120 else
1121 goto error;
1122 regmap_update_bits(nau8824->regmap,
1123 NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1124 NAU8824_I2S_LRC_DIV_MASK | NAU8824_I2S_BLK_DIV_MASK,
1125 (bclk_div << NAU8824_I2S_LRC_DIV_SFT) | bclk_div);
1126 }
1127
1128 switch (params_width(params)) {
1129 case 16:
1130 val_len |= NAU8824_I2S_DL_16;
1131 break;
1132 case 20:
1133 val_len |= NAU8824_I2S_DL_20;
1134 break;
1135 case 24:
1136 val_len |= NAU8824_I2S_DL_24;
1137 break;
1138 case 32:
1139 val_len |= NAU8824_I2S_DL_32;
1140 break;
1141 default:
1142 goto error;
1143 }
1144
1145 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1146 NAU8824_I2S_DL_MASK, val_len);
1147 err = 0;
1148
1149 error:
1150 nau8824_sema_release(nau8824);
1151
1152 return err;
1153}
1154
1155static int nau8824_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1156{
1157 struct snd_soc_component *component = dai->component;
1158 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1159 unsigned int ctrl1_val = 0, ctrl2_val = 0;
1160
1161 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1162 case SND_SOC_DAIFMT_CBM_CFM:
1163 ctrl2_val |= NAU8824_I2S_MS_MASTER;
1164 break;
1165 case SND_SOC_DAIFMT_CBS_CFS:
1166 break;
1167 default:
1168 return -EINVAL;
1169 }
1170
1171 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1172 case SND_SOC_DAIFMT_NB_NF:
1173 break;
1174 case SND_SOC_DAIFMT_IB_NF:
1175 ctrl1_val |= NAU8824_I2S_BP_INV;
1176 break;
1177 default:
1178 return -EINVAL;
1179 }
1180
1181 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1182 case SND_SOC_DAIFMT_I2S:
1183 ctrl1_val |= NAU8824_I2S_DF_I2S;
1184 break;
1185 case SND_SOC_DAIFMT_LEFT_J:
1186 ctrl1_val |= NAU8824_I2S_DF_LEFT;
1187 break;
1188 case SND_SOC_DAIFMT_RIGHT_J:
1189 ctrl1_val |= NAU8824_I2S_DF_RIGTH;
1190 break;
1191 case SND_SOC_DAIFMT_DSP_A:
1192 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1193 break;
1194 case SND_SOC_DAIFMT_DSP_B:
1195 ctrl1_val |= NAU8824_I2S_DF_PCM_AB;
1196 ctrl1_val |= NAU8824_I2S_PCMB_EN;
1197 break;
1198 default:
1199 return -EINVAL;
1200 }
1201
1202 nau8824_sema_acquire(nau8824, HZ);
1203
1204 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_1,
1205 NAU8824_I2S_DF_MASK | NAU8824_I2S_BP_MASK |
1206 NAU8824_I2S_PCMB_EN, ctrl1_val);
1207 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_I2S_PCM_CTRL_2,
1208 NAU8824_I2S_MS_MASK, ctrl2_val);
1209
1210 nau8824_sema_release(nau8824);
1211
1212 return 0;
1213}
1214
1215/**
1216 * nau8824_set_tdm_slot - configure DAI TDM.
1217 * @dai: DAI
1218 * @tx_mask: Bitmask representing active TX slots. Ex.
1219 * 0xf for normal 4 channel TDM.
1220 * 0xf0 for shifted 4 channel TDM
1221 * @rx_mask: Bitmask [0:1] representing active DACR RX slots.
1222 * Bitmask [2:3] representing active DACL RX slots.
1223 * 00=CH0,01=CH1,10=CH2,11=CH3. Ex.
1224 * 0xf for DACL/R selecting TDM CH3.
1225 * 0xf0 for DACL/R selecting shifted TDM CH3.
1226 * @slots: Number of slots in use.
1227 * @slot_width: Width in bits for each slot.
1228 *
1229 * Configures a DAI for TDM operation. Only support 4 slots TDM.
1230 */
1231static int nau8824_set_tdm_slot(struct snd_soc_dai *dai,
1232 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
1233{
1234 struct snd_soc_component *component = dai->component;
1235 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1236 unsigned int tslot_l = 0, ctrl_val = 0;
1237
1238 if (slots > 4 || ((tx_mask & 0xf0) && (tx_mask & 0xf)) ||
1239 ((rx_mask & 0xf0) && (rx_mask & 0xf)) ||
1240 ((rx_mask & 0xf0) && (tx_mask & 0xf)) ||
1241 ((rx_mask & 0xf) && (tx_mask & 0xf0)))
1242 return -EINVAL;
1243
1244 ctrl_val |= (NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN);
1245 if (tx_mask & 0xf0) {
1246 tslot_l = 4 * slot_width;
1247 ctrl_val |= (tx_mask >> 4);
1248 } else {
1249 ctrl_val |= tx_mask;
1250 }
1251 if (rx_mask & 0xf0)
1252 ctrl_val |= ((rx_mask >> 4) << NAU8824_TDM_DACR_RX_SFT);
1253 else
1254 ctrl_val |= (rx_mask << NAU8824_TDM_DACR_RX_SFT);
1255
1256 regmap_update_bits(nau8824->regmap, NAU8824_REG_TDM_CTRL,
1257 NAU8824_TDM_MODE | NAU8824_TDM_OFFSET_EN |
1258 NAU8824_TDM_DACL_RX_MASK | NAU8824_TDM_DACR_RX_MASK |
1259 NAU8824_TDM_TX_MASK, ctrl_val);
1260 regmap_update_bits(nau8824->regmap, NAU8824_REG_PORT0_LEFT_TIME_SLOT,
1261 NAU8824_TSLOT_L_MASK, tslot_l);
1262
1263 return 0;
1264}
1265
1266/**
1267 * nau8824_calc_fll_param - Calculate FLL parameters.
1268 * @fll_in: external clock provided to codec.
1269 * @fs: sampling rate.
1270 * @fll_param: Pointer to structure of FLL parameters.
1271 *
1272 * Calculate FLL parameters to configure codec.
1273 *
1274 * Returns 0 for success or negative error code.
1275 */
1276static int nau8824_calc_fll_param(unsigned int fll_in,
1277 unsigned int fs, struct nau8824_fll *fll_param)
1278{
1279 u64 fvco, fvco_max;
1280 unsigned int fref, i, fvco_sel;
1281
1282 /* Ensure the reference clock frequency (FREF) is <= 13.5MHz by dividing
1283 * freq_in by 1, 2, 4, or 8 using FLL pre-scalar.
1284 * FREF = freq_in / NAU8824_FLL_REF_DIV_MASK
1285 */
1286 for (i = 0; i < ARRAY_SIZE(fll_pre_scalar); i++) {
1287 fref = fll_in / fll_pre_scalar[i].param;
1288 if (fref <= NAU_FREF_MAX)
1289 break;
1290 }
1291 if (i == ARRAY_SIZE(fll_pre_scalar))
1292 return -EINVAL;
1293 fll_param->clk_ref_div = fll_pre_scalar[i].val;
1294
1295 /* Choose the FLL ratio based on FREF */
1296 for (i = 0; i < ARRAY_SIZE(fll_ratio); i++) {
1297 if (fref >= fll_ratio[i].param)
1298 break;
1299 }
1300 if (i == ARRAY_SIZE(fll_ratio))
1301 return -EINVAL;
1302 fll_param->ratio = fll_ratio[i].val;
1303
1304 /* Calculate the frequency of DCO (FDCO) given freq_out = 256 * Fs.
1305 * FDCO must be within the 90MHz - 124MHz or the FFL cannot be
1306 * guaranteed across the full range of operation.
1307 * FDCO = freq_out * 2 * mclk_src_scaling
1308 */
1309 fvco_max = 0;
1310 fvco_sel = ARRAY_SIZE(mclk_src_scaling);
1311 for (i = 0; i < ARRAY_SIZE(mclk_src_scaling); i++) {
1312 fvco = 256ULL * fs * 2 * mclk_src_scaling[i].param;
1313 if (fvco > NAU_FVCO_MIN && fvco < NAU_FVCO_MAX &&
1314 fvco_max < fvco) {
1315 fvco_max = fvco;
1316 fvco_sel = i;
1317 }
1318 }
1319 if (ARRAY_SIZE(mclk_src_scaling) == fvco_sel)
1320 return -EINVAL;
1321 fll_param->mclk_src = mclk_src_scaling[fvco_sel].val;
1322
1323 /* Calculate the FLL 10-bit integer input and the FLL 16-bit fractional
1324 * input based on FDCO, FREF and FLL ratio.
1325 */
1326 fvco = div_u64(fvco_max << 16, fref * fll_param->ratio);
1327 fll_param->fll_int = (fvco >> 16) & 0x3FF;
1328 fll_param->fll_frac = fvco & 0xFFFF;
1329 return 0;
1330}
1331
1332static void nau8824_fll_apply(struct regmap *regmap,
1333 struct nau8824_fll *fll_param)
1334{
1335 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1336 NAU8824_CLK_SRC_MASK | NAU8824_CLK_MCLK_SRC_MASK,
1337 NAU8824_CLK_SRC_MCLK | fll_param->mclk_src);
1338 regmap_update_bits(regmap, NAU8824_REG_FLL1,
1339 NAU8824_FLL_RATIO_MASK, fll_param->ratio);
1340 /* FLL 16-bit fractional input */
1341 regmap_write(regmap, NAU8824_REG_FLL2, fll_param->fll_frac);
1342 /* FLL 10-bit integer input */
1343 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1344 NAU8824_FLL_INTEGER_MASK, fll_param->fll_int);
1345 /* FLL pre-scaler */
1346 regmap_update_bits(regmap, NAU8824_REG_FLL4,
1347 NAU8824_FLL_REF_DIV_MASK,
1348 fll_param->clk_ref_div << NAU8824_FLL_REF_DIV_SFT);
1349 /* select divided VCO input */
1350 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1351 NAU8824_FLL_CLK_SW_MASK, NAU8824_FLL_CLK_SW_REF);
1352 /* Disable free-running mode */
1353 regmap_update_bits(regmap,
1354 NAU8824_REG_FLL6, NAU8824_DCO_EN, 0);
1355 if (fll_param->fll_frac) {
1356 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1357 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1358 NAU8824_FLL_FTR_SW_MASK,
1359 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1360 NAU8824_FLL_FTR_SW_FILTER);
1361 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1362 NAU8824_SDM_EN, NAU8824_SDM_EN);
1363 } else {
1364 regmap_update_bits(regmap, NAU8824_REG_FLL5,
1365 NAU8824_FLL_PDB_DAC_EN | NAU8824_FLL_LOOP_FTR_EN |
1366 NAU8824_FLL_FTR_SW_MASK, NAU8824_FLL_FTR_SW_ACCU);
1367 regmap_update_bits(regmap,
1368 NAU8824_REG_FLL6, NAU8824_SDM_EN, 0);
1369 }
1370}
1371
1372/* freq_out must be 256*Fs in order to achieve the best performance */
1373static int nau8824_set_pll(struct snd_soc_component *component, int pll_id, int source,
1374 unsigned int freq_in, unsigned int freq_out)
1375{
1376 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1377 struct nau8824_fll fll_param;
1378 int ret, fs;
1379
1380 fs = freq_out / 256;
1381 ret = nau8824_calc_fll_param(freq_in, fs, &fll_param);
1382 if (ret < 0) {
1383 dev_err(nau8824->dev, "Unsupported input clock %d\n", freq_in);
1384 return ret;
1385 }
1386 dev_dbg(nau8824->dev, "mclk_src=%x ratio=%x fll_frac=%x fll_int=%x clk_ref_div=%x\n",
1387 fll_param.mclk_src, fll_param.ratio, fll_param.fll_frac,
1388 fll_param.fll_int, fll_param.clk_ref_div);
1389
1390 nau8824_fll_apply(nau8824->regmap, &fll_param);
1391 mdelay(2);
1392 regmap_update_bits(nau8824->regmap, NAU8824_REG_CLK_DIVIDER,
1393 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1394
1395 return 0;
1396}
1397
1398static int nau8824_config_sysclk(struct nau8824 *nau8824,
1399 int clk_id, unsigned int freq)
1400{
1401 struct regmap *regmap = nau8824->regmap;
1402
1403 switch (clk_id) {
1404 case NAU8824_CLK_DIS:
1405 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1406 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1407 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1408 NAU8824_DCO_EN, 0);
1409 break;
1410
1411 case NAU8824_CLK_MCLK:
1412 nau8824_sema_acquire(nau8824, HZ);
1413 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1414 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_MCLK);
1415 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1416 NAU8824_DCO_EN, 0);
1417 nau8824_sema_release(nau8824);
1418 break;
1419
1420 case NAU8824_CLK_INTERNAL:
1421 regmap_update_bits(regmap, NAU8824_REG_FLL6,
1422 NAU8824_DCO_EN, NAU8824_DCO_EN);
1423 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1424 NAU8824_CLK_SRC_MASK, NAU8824_CLK_SRC_VCO);
1425 break;
1426
1427 case NAU8824_CLK_FLL_MCLK:
1428 nau8824_sema_acquire(nau8824, HZ);
1429 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1430 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_MCLK);
1431 nau8824_sema_release(nau8824);
1432 break;
1433
1434 case NAU8824_CLK_FLL_BLK:
1435 nau8824_sema_acquire(nau8824, HZ);
1436 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1437 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_BLK);
1438 nau8824_sema_release(nau8824);
1439 break;
1440
1441 case NAU8824_CLK_FLL_FS:
1442 nau8824_sema_acquire(nau8824, HZ);
1443 regmap_update_bits(regmap, NAU8824_REG_FLL3,
1444 NAU8824_FLL_CLK_SRC_MASK, NAU8824_FLL_CLK_SRC_FS);
1445 nau8824_sema_release(nau8824);
1446 break;
1447
1448 default:
1449 dev_err(nau8824->dev, "Invalid clock id (%d)\n", clk_id);
1450 return -EINVAL;
1451 }
1452
1453 dev_dbg(nau8824->dev, "Sysclk is %dHz and clock id is %d\n", freq,
1454 clk_id);
1455
1456 return 0;
1457}
1458
1459static int nau8824_set_sysclk(struct snd_soc_component *component,
1460 int clk_id, int source, unsigned int freq, int dir)
1461{
1462 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1463
1464 return nau8824_config_sysclk(nau8824, clk_id, freq);
1465}
1466
1467static void nau8824_resume_setup(struct nau8824 *nau8824)
1468{
1469 nau8824_config_sysclk(nau8824, NAU8824_CLK_DIS, 0);
1470 if (nau8824->irq) {
1471 /* Clear all interruption status */
1472 nau8824_int_status_clear_all(nau8824->regmap);
1473 /* Enable jack detection at sleep mode, insertion detection,
1474 * and ejection detection.
1475 */
1476 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1477 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1478 regmap_update_bits(nau8824->regmap,
1479 NAU8824_REG_INTERRUPT_SETTING_1,
1480 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN,
1481 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN);
1482 regmap_update_bits(nau8824->regmap,
1483 NAU8824_REG_INTERRUPT_SETTING,
1484 NAU8824_IRQ_EJECT_DIS | NAU8824_IRQ_INSERT_DIS, 0);
1485 }
1486}
1487
1488static int nau8824_set_bias_level(struct snd_soc_component *component,
1489 enum snd_soc_bias_level level)
1490{
1491 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1492
1493 switch (level) {
1494 case SND_SOC_BIAS_ON:
1495 break;
1496
1497 case SND_SOC_BIAS_PREPARE:
1498 break;
1499
1500 case SND_SOC_BIAS_STANDBY:
1501 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
1502 /* Setup codec configuration after resume */
1503 nau8824_resume_setup(nau8824);
1504 }
1505 break;
1506
1507 case SND_SOC_BIAS_OFF:
1508 regmap_update_bits(nau8824->regmap,
1509 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1510 regmap_update_bits(nau8824->regmap,
1511 NAU8824_REG_INTERRUPT_SETTING_1,
1512 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1513 break;
1514 }
1515
1516 return 0;
1517}
1518
1519static int nau8824_component_probe(struct snd_soc_component *component)
1520{
1521 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1522 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
1523
1524 nau8824->dapm = dapm;
1525
1526 return 0;
1527}
1528
1529static int __maybe_unused nau8824_suspend(struct snd_soc_component *component)
1530{
1531 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1532
1533 if (nau8824->irq) {
1534 disable_irq(nau8824->irq);
1535 snd_soc_component_force_bias_level(component, SND_SOC_BIAS_OFF);
1536 }
1537 regcache_cache_only(nau8824->regmap, true);
1538 regcache_mark_dirty(nau8824->regmap);
1539
1540 return 0;
1541}
1542
1543static int __maybe_unused nau8824_resume(struct snd_soc_component *component)
1544{
1545 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1546 int ret;
1547
1548 regcache_cache_only(nau8824->regmap, false);
1549 regcache_sync(nau8824->regmap);
1550 if (nau8824->irq) {
1551 /* Hold semaphore to postpone playback happening
1552 * until jack detection done.
1553 */
1554 nau8824->resume_lock = true;
1555 ret = nau8824_sema_acquire(nau8824, 0);
1556 if (ret)
1557 nau8824->resume_lock = false;
1558 enable_irq(nau8824->irq);
1559 }
1560
1561 return 0;
1562}
1563
1564static const struct snd_soc_component_driver nau8824_component_driver = {
1565 .probe = nau8824_component_probe,
1566 .set_sysclk = nau8824_set_sysclk,
1567 .set_pll = nau8824_set_pll,
1568 .set_bias_level = nau8824_set_bias_level,
1569 .suspend = nau8824_suspend,
1570 .resume = nau8824_resume,
1571 .controls = nau8824_snd_controls,
1572 .num_controls = ARRAY_SIZE(nau8824_snd_controls),
1573 .dapm_widgets = nau8824_dapm_widgets,
1574 .num_dapm_widgets = ARRAY_SIZE(nau8824_dapm_widgets),
1575 .dapm_routes = nau8824_dapm_routes,
1576 .num_dapm_routes = ARRAY_SIZE(nau8824_dapm_routes),
1577 .suspend_bias_off = 1,
1578 .idle_bias_on = 1,
1579 .use_pmdown_time = 1,
1580 .endianness = 1,
1581};
1582
1583static const struct snd_soc_dai_ops nau8824_dai_ops = {
1584 .startup = nau8824_dai_startup,
1585 .hw_params = nau8824_hw_params,
1586 .set_fmt = nau8824_set_fmt,
1587 .set_tdm_slot = nau8824_set_tdm_slot,
1588};
1589
1590#define NAU8824_RATES SNDRV_PCM_RATE_8000_192000
1591#define NAU8824_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
1592 | SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1593
1594static struct snd_soc_dai_driver nau8824_dai = {
1595 .name = NAU8824_CODEC_DAI,
1596 .playback = {
1597 .stream_name = "Playback",
1598 .channels_min = 1,
1599 .channels_max = 2,
1600 .rates = NAU8824_RATES,
1601 .formats = NAU8824_FORMATS,
1602 },
1603 .capture = {
1604 .stream_name = "Capture",
1605 .channels_min = 1,
1606 .channels_max = 2,
1607 .rates = NAU8824_RATES,
1608 .formats = NAU8824_FORMATS,
1609 },
1610 .ops = &nau8824_dai_ops,
1611};
1612
1613static const struct regmap_config nau8824_regmap_config = {
1614 .val_bits = NAU8824_REG_ADDR_LEN,
1615 .reg_bits = NAU8824_REG_DATA_LEN,
1616
1617 .max_register = NAU8824_REG_MAX,
1618 .readable_reg = nau8824_readable_reg,
1619 .writeable_reg = nau8824_writeable_reg,
1620 .volatile_reg = nau8824_volatile_reg,
1621
1622 .cache_type = REGCACHE_RBTREE,
1623 .reg_defaults = nau8824_reg_defaults,
1624 .num_reg_defaults = ARRAY_SIZE(nau8824_reg_defaults),
1625};
1626
1627/**
1628 * nau8824_enable_jack_detect - Specify a jack for event reporting
1629 *
1630 * @component: component to register the jack with
1631 * @jack: jack to use to report headset and button events on
1632 *
1633 * After this function has been called the headset insert/remove and button
1634 * events will be routed to the given jack. Jack can be null to stop
1635 * reporting.
1636 */
1637int nau8824_enable_jack_detect(struct snd_soc_component *component,
1638 struct snd_soc_jack *jack)
1639{
1640 struct nau8824 *nau8824 = snd_soc_component_get_drvdata(component);
1641 int ret;
1642
1643 nau8824->jack = jack;
1644 /* Initiate jack detection work queue */
1645 INIT_WORK(&nau8824->jdet_work, nau8824_jdet_work);
1646 ret = devm_request_threaded_irq(nau8824->dev, nau8824->irq, NULL,
1647 nau8824_interrupt, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1648 "nau8824", nau8824);
1649 if (ret) {
1650 dev_err(nau8824->dev, "Cannot request irq %d (%d)\n",
1651 nau8824->irq, ret);
1652 }
1653
1654 return ret;
1655}
1656EXPORT_SYMBOL_GPL(nau8824_enable_jack_detect);
1657
1658static void nau8824_reset_chip(struct regmap *regmap)
1659{
1660 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1661 regmap_write(regmap, NAU8824_REG_RESET, 0x00);
1662}
1663
1664static void nau8824_setup_buttons(struct nau8824 *nau8824)
1665{
1666 struct regmap *regmap = nau8824->regmap;
1667
1668 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1669 NAU8824_SAR_TRACKING_GAIN_MASK,
1670 nau8824->sar_voltage << NAU8824_SAR_TRACKING_GAIN_SFT);
1671 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1672 NAU8824_SAR_COMPARE_TIME_MASK,
1673 nau8824->sar_compare_time << NAU8824_SAR_COMPARE_TIME_SFT);
1674 regmap_update_bits(regmap, NAU8824_REG_SAR_ADC,
1675 NAU8824_SAR_SAMPLING_TIME_MASK,
1676 nau8824->sar_sampling_time << NAU8824_SAR_SAMPLING_TIME_SFT);
1677
1678 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1679 NAU8824_LEVELS_NR_MASK,
1680 (nau8824->sar_threshold_num - 1) << NAU8824_LEVELS_NR_SFT);
1681 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1682 NAU8824_HYSTERESIS_MASK,
1683 nau8824->sar_hysteresis << NAU8824_HYSTERESIS_SFT);
1684 regmap_update_bits(regmap, NAU8824_REG_VDET_COEFFICIENT,
1685 NAU8824_SHORTKEY_DEBOUNCE_MASK,
1686 nau8824->key_debounce << NAU8824_SHORTKEY_DEBOUNCE_SFT);
1687
1688 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_1,
1689 (nau8824->sar_threshold[0] << 8) | nau8824->sar_threshold[1]);
1690 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_2,
1691 (nau8824->sar_threshold[2] << 8) | nau8824->sar_threshold[3]);
1692 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_3,
1693 (nau8824->sar_threshold[4] << 8) | nau8824->sar_threshold[5]);
1694 regmap_write(regmap, NAU8824_REG_VDET_THRESHOLD_4,
1695 (nau8824->sar_threshold[6] << 8) | nau8824->sar_threshold[7]);
1696}
1697
1698static void nau8824_init_regs(struct nau8824 *nau8824)
1699{
1700 struct regmap *regmap = nau8824->regmap;
1701
1702 /* Enable Bias/VMID/VMID Tieoff */
1703 regmap_update_bits(regmap, NAU8824_REG_BIAS_ADJ,
1704 NAU8824_VMID | NAU8824_VMID_SEL_MASK, NAU8824_VMID |
1705 (nau8824->vref_impedance << NAU8824_VMID_SEL_SFT));
1706 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1707 NAU8824_GLOBAL_BIAS_EN, NAU8824_GLOBAL_BIAS_EN);
1708 mdelay(2);
1709 regmap_update_bits(regmap, NAU8824_REG_MIC_BIAS,
1710 NAU8824_MICBIAS_VOLTAGE_MASK, nau8824->micbias_voltage);
1711 /* Disable Boost Driver, Automatic Short circuit protection enable */
1712 regmap_update_bits(regmap, NAU8824_REG_BOOST,
1713 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1714 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN,
1715 NAU8824_PRECHARGE_DIS | NAU8824_HP_BOOST_DIS |
1716 NAU8824_HP_BOOST_G_DIS | NAU8824_SHORT_SHUTDOWN_EN);
1717 /* Scaling for ADC and DAC clock */
1718 regmap_update_bits(regmap, NAU8824_REG_CLK_DIVIDER,
1719 NAU8824_CLK_ADC_SRC_MASK | NAU8824_CLK_DAC_SRC_MASK,
1720 (0x1 << NAU8824_CLK_ADC_SRC_SFT) |
1721 (0x1 << NAU8824_CLK_DAC_SRC_SFT));
1722 regmap_update_bits(regmap, NAU8824_REG_DAC_MUTE_CTRL,
1723 NAU8824_DAC_ZC_EN, NAU8824_DAC_ZC_EN);
1724 regmap_update_bits(regmap, NAU8824_REG_ENA_CTRL,
1725 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1726 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1727 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN,
1728 NAU8824_DAC_CH1_EN | NAU8824_DAC_CH0_EN |
1729 NAU8824_ADC_CH0_EN | NAU8824_ADC_CH1_EN |
1730 NAU8824_ADC_CH2_EN | NAU8824_ADC_CH3_EN);
1731 regmap_update_bits(regmap, NAU8824_REG_CLK_GATING_ENA,
1732 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1733 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1734 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1735 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN,
1736 NAU8824_CLK_ADC_CH23_EN | NAU8824_CLK_ADC_CH01_EN |
1737 NAU8824_CLK_DAC_CH1_EN | NAU8824_CLK_DAC_CH0_EN |
1738 NAU8824_CLK_I2S_EN | NAU8824_CLK_GAIN_EN |
1739 NAU8824_CLK_SAR_EN | NAU8824_CLK_DMIC_CH23_EN);
1740 /* Class G timer 64ms */
1741 regmap_update_bits(regmap, NAU8824_REG_CLASSG,
1742 NAU8824_CLASSG_TIMER_MASK,
1743 0x20 << NAU8824_CLASSG_TIMER_SFT);
1744 regmap_update_bits(regmap, NAU8824_REG_TRIM_SETTINGS,
1745 NAU8824_DRV_CURR_INC, NAU8824_DRV_CURR_INC);
1746 /* Disable DACR/L power */
1747 regmap_update_bits(regmap, NAU8824_REG_CHARGE_PUMP_CONTROL,
1748 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1749 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL,
1750 NAU8824_SPKR_PULL_DOWN | NAU8824_SPKL_PULL_DOWN |
1751 NAU8824_POWER_DOWN_DACR | NAU8824_POWER_DOWN_DACL);
1752 /* Enable TESTDAC. This sets the analog DAC inputs to a '0' input
1753 * signal to avoid any glitches due to power up transients in both
1754 * the analog and digital DAC circuit.
1755 */
1756 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1757 NAU8824_TEST_DAC_EN, NAU8824_TEST_DAC_EN);
1758 /* Config L/R channel */
1759 regmap_update_bits(regmap, NAU8824_REG_DAC_CH0_DGAIN_CTRL,
1760 NAU8824_DAC_CH0_SEL_MASK, NAU8824_DAC_CH0_SEL_I2S0);
1761 regmap_update_bits(regmap, NAU8824_REG_DAC_CH1_DGAIN_CTRL,
1762 NAU8824_DAC_CH1_SEL_MASK, NAU8824_DAC_CH1_SEL_I2S1);
1763 regmap_update_bits(regmap, NAU8824_REG_ENABLE_LO,
1764 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN,
1765 NAU8824_DACR_HPR_EN | NAU8824_DACL_HPL_EN);
1766 /* Default oversampling/decimations settings are unusable
1767 * (audible hiss). Set it to something better.
1768 */
1769 regmap_update_bits(regmap, NAU8824_REG_ADC_FILTER_CTRL,
1770 NAU8824_ADC_SYNC_DOWN_MASK, NAU8824_ADC_SYNC_DOWN_64);
1771 regmap_update_bits(regmap, NAU8824_REG_DAC_FILTER_CTRL_1,
1772 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_MASK,
1773 NAU8824_DAC_CICCLP_OFF | NAU8824_DAC_OVERSAMPLE_64);
1774 /* DAC clock delay 2ns, VREF */
1775 regmap_update_bits(regmap, NAU8824_REG_RDAC,
1776 NAU8824_RDAC_CLK_DELAY_MASK | NAU8824_RDAC_VREF_MASK,
1777 (0x2 << NAU8824_RDAC_CLK_DELAY_SFT) |
1778 (0x3 << NAU8824_RDAC_VREF_SFT));
1779 /* PGA input mode selection */
1780 regmap_update_bits(regmap, NAU8824_REG_FEPGA,
1781 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN,
1782 NAU8824_FEPGA_MODEL_SHORT_EN | NAU8824_FEPGA_MODER_SHORT_EN);
1783 /* Digital microphone control */
1784 regmap_update_bits(regmap, NAU8824_REG_ANALOG_CONTROL_1,
1785 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST,
1786 NAU8824_DMIC_CLK_DRV_STRG | NAU8824_DMIC_CLK_SLEW_FAST);
1787 regmap_update_bits(regmap, NAU8824_REG_JACK_DET_CTRL,
1788 NAU8824_JACK_LOGIC,
1789 /* jkdet_polarity - 1 is for active-low */
1790 nau8824->jkdet_polarity ? 0 : NAU8824_JACK_LOGIC);
1791 regmap_update_bits(regmap,
1792 NAU8824_REG_JACK_DET_CTRL, NAU8824_JACK_EJECT_DT_MASK,
1793 (nau8824->jack_eject_debounce << NAU8824_JACK_EJECT_DT_SFT));
1794 if (nau8824->sar_threshold_num)
1795 nau8824_setup_buttons(nau8824);
1796}
1797
1798static int nau8824_setup_irq(struct nau8824 *nau8824)
1799{
1800 /* Disable interruption before codec initiation done */
1801 regmap_update_bits(nau8824->regmap, NAU8824_REG_ENA_CTRL,
1802 NAU8824_JD_SLEEP_MODE, NAU8824_JD_SLEEP_MODE);
1803 regmap_update_bits(nau8824->regmap,
1804 NAU8824_REG_INTERRUPT_SETTING, 0x3ff, 0x3ff);
1805 regmap_update_bits(nau8824->regmap, NAU8824_REG_INTERRUPT_SETTING_1,
1806 NAU8824_IRQ_EJECT_EN | NAU8824_IRQ_INSERT_EN, 0);
1807
1808 return 0;
1809}
1810
1811static void nau8824_print_device_properties(struct nau8824 *nau8824)
1812{
1813 struct device *dev = nau8824->dev;
1814 int i;
1815
1816 dev_dbg(dev, "jkdet-polarity: %d\n", nau8824->jkdet_polarity);
1817 dev_dbg(dev, "micbias-voltage: %d\n", nau8824->micbias_voltage);
1818 dev_dbg(dev, "vref-impedance: %d\n", nau8824->vref_impedance);
1819
1820 dev_dbg(dev, "sar-threshold-num: %d\n", nau8824->sar_threshold_num);
1821 for (i = 0; i < nau8824->sar_threshold_num; i++)
1822 dev_dbg(dev, "sar-threshold[%d]=%x\n", i,
1823 nau8824->sar_threshold[i]);
1824
1825 dev_dbg(dev, "sar-hysteresis: %d\n", nau8824->sar_hysteresis);
1826 dev_dbg(dev, "sar-voltage: %d\n", nau8824->sar_voltage);
1827 dev_dbg(dev, "sar-compare-time: %d\n", nau8824->sar_compare_time);
1828 dev_dbg(dev, "sar-sampling-time: %d\n", nau8824->sar_sampling_time);
1829 dev_dbg(dev, "short-key-debounce: %d\n", nau8824->key_debounce);
1830 dev_dbg(dev, "jack-eject-debounce: %d\n",
1831 nau8824->jack_eject_debounce);
1832}
1833
1834static int nau8824_read_device_properties(struct device *dev,
1835 struct nau8824 *nau8824) {
1836 int ret;
1837
1838 ret = device_property_read_u32(dev, "nuvoton,jkdet-polarity",
1839 &nau8824->jkdet_polarity);
1840 if (ret)
1841 nau8824->jkdet_polarity = 1;
1842 ret = device_property_read_u32(dev, "nuvoton,micbias-voltage",
1843 &nau8824->micbias_voltage);
1844 if (ret)
1845 nau8824->micbias_voltage = 6;
1846 ret = device_property_read_u32(dev, "nuvoton,vref-impedance",
1847 &nau8824->vref_impedance);
1848 if (ret)
1849 nau8824->vref_impedance = 2;
1850 ret = device_property_read_u32(dev, "nuvoton,sar-threshold-num",
1851 &nau8824->sar_threshold_num);
1852 if (ret)
1853 nau8824->sar_threshold_num = 4;
1854 ret = device_property_read_u32_array(dev, "nuvoton,sar-threshold",
1855 nau8824->sar_threshold, nau8824->sar_threshold_num);
1856 if (ret) {
1857 nau8824->sar_threshold[0] = 0x0a;
1858 nau8824->sar_threshold[1] = 0x14;
1859 nau8824->sar_threshold[2] = 0x26;
1860 nau8824->sar_threshold[3] = 0x73;
1861 }
1862 ret = device_property_read_u32(dev, "nuvoton,sar-hysteresis",
1863 &nau8824->sar_hysteresis);
1864 if (ret)
1865 nau8824->sar_hysteresis = 0;
1866 ret = device_property_read_u32(dev, "nuvoton,sar-voltage",
1867 &nau8824->sar_voltage);
1868 if (ret)
1869 nau8824->sar_voltage = 6;
1870 ret = device_property_read_u32(dev, "nuvoton,sar-compare-time",
1871 &nau8824->sar_compare_time);
1872 if (ret)
1873 nau8824->sar_compare_time = 1;
1874 ret = device_property_read_u32(dev, "nuvoton,sar-sampling-time",
1875 &nau8824->sar_sampling_time);
1876 if (ret)
1877 nau8824->sar_sampling_time = 1;
1878 ret = device_property_read_u32(dev, "nuvoton,short-key-debounce",
1879 &nau8824->key_debounce);
1880 if (ret)
1881 nau8824->key_debounce = 0;
1882 ret = device_property_read_u32(dev, "nuvoton,jack-eject-debounce",
1883 &nau8824->jack_eject_debounce);
1884 if (ret)
1885 nau8824->jack_eject_debounce = 1;
1886
1887 nau8824->mclk = devm_clk_get_optional(dev, "mclk");
1888 if (IS_ERR(nau8824->mclk))
1889 return PTR_ERR(nau8824->mclk);
1890
1891 return 0;
1892}
1893
1894/* Please keep this list alphabetically sorted */
1895static const struct dmi_system_id nau8824_quirk_table[] = {
1896 {
1897 /* Cyberbook T116 rugged tablet */
1898 .matches = {
1899 DMI_EXACT_MATCH(DMI_BOARD_VENDOR, "Default string"),
1900 DMI_EXACT_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
1901 DMI_EXACT_MATCH(DMI_PRODUCT_SKU, "20170531"),
1902 },
1903 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH |
1904 NAU8824_MONO_SPEAKER),
1905 },
1906 {
1907 /* CUBE iwork8 Air */
1908 .matches = {
1909 DMI_MATCH(DMI_SYS_VENDOR, "cube"),
1910 DMI_MATCH(DMI_PRODUCT_NAME, "i1-TF"),
1911 DMI_MATCH(DMI_BOARD_NAME, "Cherry Trail CR"),
1912 },
1913 .driver_data = (void *)(NAU8824_MONO_SPEAKER),
1914 },
1915 {
1916 /* Pipo W2S */
1917 .matches = {
1918 DMI_MATCH(DMI_SYS_VENDOR, "PIPO"),
1919 DMI_MATCH(DMI_PRODUCT_NAME, "W2S"),
1920 },
1921 .driver_data = (void *)(NAU8824_MONO_SPEAKER),
1922 },
1923 {
1924 /* Positivo CW14Q01P */
1925 .matches = {
1926 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1927 DMI_MATCH(DMI_BOARD_NAME, "CW14Q01P"),
1928 },
1929 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
1930 },
1931 {
1932 /* Positivo K1424G */
1933 .matches = {
1934 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1935 DMI_MATCH(DMI_BOARD_NAME, "K1424G"),
1936 },
1937 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
1938 },
1939 {
1940 /* Positivo N14ZP74G */
1941 .matches = {
1942 DMI_MATCH(DMI_SYS_VENDOR, "Positivo Tecnologia SA"),
1943 DMI_MATCH(DMI_BOARD_NAME, "N14ZP74G"),
1944 },
1945 .driver_data = (void *)(NAU8824_JD_ACTIVE_HIGH),
1946 },
1947 {}
1948};
1949
1950static void nau8824_check_quirks(void)
1951{
1952 const struct dmi_system_id *dmi_id;
1953
1954 if (quirk_override != -1) {
1955 nau8824_quirk = quirk_override;
1956 return;
1957 }
1958
1959 dmi_id = dmi_first_match(nau8824_quirk_table);
1960 if (dmi_id)
1961 nau8824_quirk = (unsigned long)dmi_id->driver_data;
1962}
1963
1964const char *nau8824_components(void)
1965{
1966 nau8824_check_quirks();
1967
1968 if (nau8824_quirk & NAU8824_MONO_SPEAKER)
1969 return "cfg-spk:1";
1970 else
1971 return "cfg-spk:2";
1972}
1973EXPORT_SYMBOL_GPL(nau8824_components);
1974
1975static int nau8824_i2c_probe(struct i2c_client *i2c)
1976{
1977 struct device *dev = &i2c->dev;
1978 struct nau8824 *nau8824 = dev_get_platdata(dev);
1979 int ret, value;
1980
1981 if (!nau8824) {
1982 nau8824 = devm_kzalloc(dev, sizeof(*nau8824), GFP_KERNEL);
1983 if (!nau8824)
1984 return -ENOMEM;
1985 ret = nau8824_read_device_properties(dev, nau8824);
1986 if (ret)
1987 return ret;
1988 }
1989 i2c_set_clientdata(i2c, nau8824);
1990
1991 nau8824->regmap = devm_regmap_init_i2c(i2c, &nau8824_regmap_config);
1992 if (IS_ERR(nau8824->regmap))
1993 return PTR_ERR(nau8824->regmap);
1994 nau8824->resume_lock = false;
1995 nau8824->dev = dev;
1996 nau8824->irq = i2c->irq;
1997 sema_init(&nau8824->jd_sem, 1);
1998
1999 nau8824_check_quirks();
2000
2001 if (nau8824_quirk & NAU8824_JD_ACTIVE_HIGH)
2002 nau8824->jkdet_polarity = 0;
2003
2004 nau8824_print_device_properties(nau8824);
2005
2006 ret = regmap_read(nau8824->regmap, NAU8824_REG_I2C_DEVICE_ID, &value);
2007 if (ret < 0) {
2008 dev_err(dev, "Failed to read device id from the NAU8824: %d\n",
2009 ret);
2010 return ret;
2011 }
2012 nau8824_reset_chip(nau8824->regmap);
2013 nau8824_init_regs(nau8824);
2014
2015 if (i2c->irq)
2016 nau8824_setup_irq(nau8824);
2017
2018 return devm_snd_soc_register_component(dev,
2019 &nau8824_component_driver, &nau8824_dai, 1);
2020}
2021
2022static const struct i2c_device_id nau8824_i2c_ids[] = {
2023 { "nau8824" },
2024 { }
2025};
2026MODULE_DEVICE_TABLE(i2c, nau8824_i2c_ids);
2027
2028#ifdef CONFIG_OF
2029static const struct of_device_id nau8824_of_ids[] = {
2030 { .compatible = "nuvoton,nau8824", },
2031 {}
2032};
2033MODULE_DEVICE_TABLE(of, nau8824_of_ids);
2034#endif
2035
2036#ifdef CONFIG_ACPI
2037static const struct acpi_device_id nau8824_acpi_match[] = {
2038 { "10508824", 0 },
2039 {},
2040};
2041MODULE_DEVICE_TABLE(acpi, nau8824_acpi_match);
2042#endif
2043
2044static struct i2c_driver nau8824_i2c_driver = {
2045 .driver = {
2046 .name = "nau8824",
2047 .of_match_table = of_match_ptr(nau8824_of_ids),
2048 .acpi_match_table = ACPI_PTR(nau8824_acpi_match),
2049 },
2050 .probe = nau8824_i2c_probe,
2051 .id_table = nau8824_i2c_ids,
2052};
2053module_i2c_driver(nau8824_i2c_driver);
2054
2055
2056MODULE_DESCRIPTION("ASoC NAU88L24 driver");
2057MODULE_AUTHOR("John Hsu <KCHSU0@nuvoton.com>");
2058MODULE_LICENSE("GPL v2");