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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * mt6357.h -- mt6357 ALSA SoC audio codec driver
4 *
5 * Copyright (c) 2024 Baylibre
6 * Author: Nicolas Belin <nbelin@baylibre.com>
7 */
8
9#ifndef __MT6357_H__
10#define __MT6357_H__
11
12#include <linux/types.h>
13
14/* Reg bit defines */
15/* MT6357_GPIO_DIR0 */
16#define MT6357_GPIO8_DIR_MASK BIT(8)
17#define MT6357_GPIO8_DIR_INPUT 0
18#define MT6357_GPIO8_DIR_OUTPUT BIT(8)
19#define MT6357_GPIO9_DIR_MASK BIT(9)
20#define MT6357_GPIO9_DIR_INPUT 0
21#define MT6357_GPIO9_DIR_OUTPUT BIT(9)
22#define MT6357_GPIO10_DIR_MASK BIT(10)
23#define MT6357_GPIO10_DIR_INPUT 0
24#define MT6357_GPIO10_DIR_OUTPUT BIT(10)
25#define MT6357_GPIO11_DIR_MASK BIT(11)
26#define MT6357_GPIO11_DIR_INPUT 0
27#define MT6357_GPIO11_DIR_OUTPUT BIT(11)
28#define MT6357_GPIO12_DIR_MASK BIT(12)
29#define MT6357_GPIO12_DIR_INPUT 0
30#define MT6357_GPIO12_DIR_OUTPUT BIT(12)
31#define MT6357_GPIO13_DIR_MASK BIT(13)
32#define MT6357_GPIO13_DIR_INPUT 0
33#define MT6357_GPIO13_DIR_OUTPUT BIT(13)
34#define MT6357_GPIO14_DIR_MASK BIT(14)
35#define MT6357_GPIO14_DIR_INPUT 0
36#define MT6357_GPIO14_DIR_OUTPUT BIT(14)
37#define MT6357_GPIO15_DIR_MASK BIT(15)
38#define MT6357_GPIO15_DIR_INPUT 0
39#define MT6357_GPIO15_DIR_OUTPUT BIT(15)
40
41/* MT6357_GPIO_MODE2 */
42#define MT6357_GPIO8_MODE_MASK GENMASK(2, 0)
43#define MT6357_GPIO8_MODE_AUD_CLK_MOSI BIT(0)
44#define MT6357_GPIO8_MODE_GPIO 0
45#define MT6357_GPIO9_MODE_MASK GENMASK(5, 3)
46#define MT6357_GPIO9_MODE_AUD_DAT_MOSI0 BIT(3)
47#define MT6357_GPIO9_MODE_GPIO 0
48#define MT6357_GPIO10_MODE_MASK GENMASK(8, 6)
49#define MT6357_GPIO10_MODE_AUD_DAT_MOSI1 BIT(6)
50#define MT6357_GPIO10_MODE_GPIO 0
51#define MT6357_GPIO11_MODE_MASK GENMASK(11, 9)
52#define MT6357_GPIO11_MODE_AUD_SYNC_MOSI BIT(9)
53#define MT6357_GPIO11_MODE_GPIO 0
54
55/* MT6357_GPIO_MODE2_SET */
56#define MT6357_GPIO8_MODE_SET_MASK GENMASK(2, 0)
57#define MT6357_GPIO8_MODE_SET_AUD_CLK_MOSI BIT(0)
58#define MT6357_GPIO9_MODE_SET_MASK GENMASK(5, 3)
59#define MT6357_GPIO9_MODE_SET_AUD_DAT_MOSI0 BIT(3)
60#define MT6357_GPIO10_MODE_SET_MASK GENMASK(8, 6)
61#define MT6357_GPIO10_MODE_SET_AUD_DAT_MOSI1 BIT(6)
62#define MT6357_GPIO11_MODE_SET_MASK GENMASK(11, 9)
63#define MT6357_GPIO11_MODE_SET_AUD_SYNC_MOSI BIT(9)
64
65/* MT6357_GPIO_MODE2_CLR */
66#define MT6357_GPIO_MODE2_CLEAR_ALL GENMASK(15, 0)
67
68/* MT6357_GPIO_MODE3 */
69#define MT6357_GPIO12_MODE_MASK GENMASK(2, 0)
70#define MT6357_GPIO12_MODE_AUD_CLK_MISO BIT(0)
71#define MT6357_GPIO12_MODE_GPIO 0
72#define MT6357_GPIO13_MODE_MASK GENMASK(5, 3)
73#define MT6357_GPIO13_MODE_AUD_DAT_MISO0 BIT(3)
74#define MT6357_GPIO13_MODE_GPIO 0
75#define MT6357_GPIO14_MODE_MASK GENMASK(8, 6)
76#define MT6357_GPIO14_MODE_AUD_DAT_MISO1 BIT(6)
77#define MT6357_GPIO14_MODE_GPIO 0
78#define MT6357_GPIO15_MODE_MASK GENMASK(11, 9)
79#define MT6357_GPIO15_MODE_AUD_SYNC_MISO BIT(9)
80#define MT6357_GPIO15_MODE_GPIO 0
81
82/* MT6357_GPIO_MODE3_SET */
83#define MT6357_GPIO12_MODE_SET_MASK GENMASK(2, 0)
84#define MT6357_GPIO12_MODE_SET_AUD_CLK_MISO BIT(0)
85#define MT6357_GPIO13_MODE_SET_MASK GENMASK(5, 3)
86#define MT6357_GPIO13_MODE_SET_AUD_DAT_MISO0 BIT(3)
87#define MT6357_GPIO14_MODE_SET_MASK GENMASK(8, 6)
88#define MT6357_GPIO14_MODE_SET_AUD_DAT_MISO1 BIT(6)
89#define MT6357_GPIO15_MODE_SET_MASK GENMASK(11, 9)
90#define MT6357_GPIO15_MODE_SET_AUD_SYNC_MISO BIT(9)
91
92/* MT6357_GPIO_MODE3_CLR */
93#define MT6357_GPIO_MODE3_CLEAR_ALL GENMASK(15, 0)
94
95/* MT6357_DCXO_CW14 */
96#define MT6357_XO_AUDIO_EN_M_SFT 13
97#define MT6357_XO_AUDIO_EN_M_MASK BIT(13)
98#define MT6357_XO_AUDIO_EN_M_ENABLE BIT(13)
99#define MT6357_XO_AUDIO_EN_M_DISABLE 0
100
101/* MT6357_AUD_TOP_CKPDN_CON0 */
102#define MT6357_AUDNCP_CK_PDN_SFT 6
103#define MT6357_ZCD13M_CK_PDN_SFT 5
104#define MT6357_AUDIF_CK_PDN_SFT 2
105#define MT6357_AUD_CK_PDN_SFT 1
106
107/* MT6357_AUDNCP_CLKDIV_CON0 */
108#define MT6357_DIVCKS_CHG BIT(0)
109
110/* MT6357_AUDNCP_CLKDIV_CON1 */
111#define MT6357_DIVCKS_ON BIT(0)
112
113/* MT6357_AUDNCP_CLKDIV_CON3 */
114#define MT6357_DIVCKS_PWD_NCP_MASK BIT(0)
115#define MT6357_DIVCKS_PWD_NCP_DISABLE BIT(0)
116#define MT6357_DIVCKS_PWD_NCP_ENABLE 0
117
118/* MT6357_AUDNCP_CLKDIV_CON4 */
119#define MT6357_DIVCKS_PWD_NCP_ST_SEL_MASK GENMASK(1, 0)
120#define MT6357_DIVCKS_PWD_NCP_ST_50US 0
121#define MT6357_DIVCKS_PWD_NCP_ST_100US 1
122#define MT6357_DIVCKS_PWD_NCP_ST_150US 2
123#define MT6357_DIVCKS_PWD_NCP_ST_200US 3
124
125/* MT6357_AFE_UL_DL_CON0 */
126#define MT6357_AFE_UL_LR_SWAP_SFT 15
127#define MT6357_AFE_ON_SFT 0
128
129/* MT6357_AFE_DL_SRC2_CON0_L */
130#define MT6357_DL_2_SRC_ON_TMP_CTL_PRE_SFT 0
131
132/* MT6357_AFE_UL_SRC_CON0_H */
133#define MT6357_C_TWO_DIGITAL_MIC_CTL_MASK BIT(7)
134#define MT6357_C_TWO_DIGITAL_MIC_ENABLE BIT(7)
135#define MT6357_C_TWO_DIGITAL_MIC_DISABLE 0
136
137/* MT6357_AFE_UL_SRC_CON0_L */
138#define MT6357_UL_SDM_3_LEVEL_CTL_MASK BIT(1)
139#define MT6357_UL_SDM_3_LEVEL_SELECT BIT(1)
140#define MT6357_UL_SDM_3_LEVEL_DESELECT 0
141#define MT6357_UL_SRC_ON_TMP_CTL_MASK BIT(0)
142#define MT6357_UL_SRC_ENABLE BIT(0)
143#define MT6357_UL_SRC_DISABLE 0
144
145/* MT6357_AFE_TOP_CON0 */
146#define MT6357_UL_SINE_ON_SFT 1
147#define MT6357_UL_SINE_ON_MASK BIT(1)
148#define MT6357_DL_SINE_ON_SFT 0
149#define MT6357_DL_SINE_ON_MASK BIT(0)
150
151/* MT6357_AUDIO_TOP_CON0 */
152#define MT6357_PDN_LPBK_CTL_SFT 15
153#define MT6357_PDN_AFE_CTL_SFT 7
154#define MT6357_PDN_DAC_CTL_SFT 6
155#define MT6357_PDN_ADC_CTL_SFT 5
156#define MT6357_PDN_I2S_DL_CTL_SFT 3
157#define MT6357_PWR_CLK_DIS_CTL_SFT 2
158#define MT6357_PDN_AFE_TESTMODEL_CTL_SFT 1
159#define MT6357_PDN_RESERVED_SFT 0
160
161/* MT6357_AFUNC_AUD_CON0 */
162#define MT6357_CCI_AUD_ANACK_INVERT BIT(15)
163#define MT6357_CCI_AUD_ANACK_NORMAL 0
164#define MT6357_CCI_AUDIO_FIFO_WPTR_SFT 12
165#define MT6357_CCI_SCRAMBLER_CG_ENABLE BIT(11)
166#define MT6357_CCI_SCRAMBLER_CG_DISABLE 0
167#define MT6357_CCI_LCK_INV_OUT_OF_PHASE BIT(10)
168#define MT6357_CCI_LCK_INV_IN_PHASE 0
169#define MT6357_CCI_RAND_ENABLE BIT(9)
170#define MT6357_CCI_RAND_DISABLE 0
171#define MT6357_CCI_SPLT_SCRMB_CLK_ON BIT(8)
172#define MT6357_CCI_SPLT_SCRMB_CLK_OFF 0
173#define MT6357_CCI_SPLT_SCRMB_ON BIT(7)
174#define MT6357_CCI_SPLT_SCRMB_OFF 0
175#define MT6357_CCI_AUD_IDAC_TEST_EN_FROM_TEST_IN BIT(6)
176#define MT6357_CCI_AUD_IDAC_TEST_EN_NORMAL_PATH 0
177#define MT6357_CCI_ZERO_PADDING_DISABLE BIT(5)
178#define MT6357_CCI_ZERO_PADDING_ENABLE 0
179#define MT6357_CCI_AUD_SPLIT_TEST_EN_FROM_TEST_IN BIT(4)
180#define MT6357_CCI_AUD_SPLIT_TEST_EN_NORMAL_PATH 0
181#define MT6357_CCI_AUD_SDM_MUTE_L_REG_CTL BIT(3)
182#define MT6357_CCI_AUD_SDM_MUTE_L_NO_CTL 0
183#define MT6357_CCI_AUD_SDM_MUTE_R_REG_CTL BIT(2)
184#define MT6357_CCI_AUD_SDM_MUTE_R_NO_CTL 0
185#define MT6357_CCI_AUD_SDM_7BIT_FROM_SPLITTER3 BIT(1)
186#define MT6357_CCI_AUD_SDM_7BIT_FROM_SPLITTER1 0
187#define MT6357_CCI_SCRAMBLER_ENABLE BIT(0)
188#define MT6357_CCI_SCRAMBLER_DISABLE 0
189
190/* MT6357_AFUNC_AUD_CON2 */
191#define MT6357_CCI_AUDIO_FIFO_ENABLE BIT(3)
192#define MT6357_CCI_AUDIO_FIFO_DISABLE 0
193#define MT6357_CCI_ACD_MODE_NORMAL_PATH BIT(2)
194#define MT6357_CCI_ACD_MODE_TEST_PATH 0
195#define MT6357_CCI_AFIFO_CLK_PWDB_ON BIT(1)
196#define MT6357_CCI_AFIFO_CLK_PWDB_DOWN 0
197#define MT6357_CCI_ACD_FUNC_RSTB_RELEASE BIT(0)
198#define MT6357_CCI_ACD_FUNC_RSTB_RESET 0
199
200/* MT6357_AFE_ADDA_MTKAIF_CFG0 */
201#define MT6357_ADDA_MTKAIF_LPBK_CTL_MASK BIT(1)
202#define MT6357_ADDA_MTKAIF_LPBK_ENABLE BIT(1)
203#define MT6357_ADDA_MTKAIF_LPBK_DISABLE 0
204
205/* MT6357_AFE_SGEN_CFG0 */
206#define MT6357_SGEN_DAC_EN_CTL_SFT 7
207#define MT6357_SGEN_DAC_ENABLE BIT(7)
208#define MT6357_SGEN_MUTE_SW_CTL_SFT 6
209#define MT6357_SGEN_MUTE_SW_DISABLE 0
210
211/* MT6357_AFE_DCCLK_CFG0 */
212#define MT6357_DCCLK_DIV_MASK GENMASK(15, 5)
213#define MT6357_DCCLK_DIV_SFT 5
214#define MT6357_DCCLK_DIV_RUN_VALUE (32 << MT6357_DCCLK_DIV_SFT)
215#define MT6357_DCCLK_DIV_STOP_VALUE (259 << MT6357_DCCLK_DIV_SFT)
216#define MT6357_DCCLK_PDN_MASK BIT(1)
217#define MT6357_DCCLK_PDN BIT(1)
218#define MT6357_DCCLK_OUTPUT 0
219#define MT6357_DCCLK_GEN_ON_MASK BIT(0)
220#define MT6357_DCCLK_GEN_ON BIT(0)
221#define MT6357_DCCLK_GEN_OFF 0
222
223/* MT6357_AFE_DCCLK_CFG1 */
224#define MT6357_DCCLK_RESYNC_BYPASS_MASK BIT(8)
225#define MT6357_DCCLK_RESYNC_BYPASS BIT(8)
226
227/* MT6357_AFE_AUD_PAD_TOP */
228#define MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_MASK GENMASK(15, 8)
229#define MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_ENABLE (BIT(13) | BIT(12) | BIT(8))
230#define MT6357_AUD_PAD_TX_FIFO_NORMAL_PATH_DISABLE (BIT(13) | BIT(12))
231#define MT6357_AUD_PAD_TX_FIFO_LPBK_MASK GENMASK(7, 0)
232#define MT6357_AUD_PAD_TX_FIFO_LPBK_ENABLE (BIT(5) | BIT(4) | BIT(0))
233#define MT6357_AUD_PAD_TX_FIFO_LPBK_DISABLE 0
234
235/* MT6357_AUDENC_ANA_CON0 */
236#define MT6357_AUDADCLINPUTSEL_MASK GENMASK(14, 13)
237#define MT6357_AUDADCLINPUTSEL_PREAMPLIFIER BIT(14)
238#define MT6357_AUDADCLINPUTSEL_IDLE 0
239#define MT6357_AUDADCLPWRUP_SFT 12
240#define MT6357_AUDADCLPWRUP_MASK BIT(12)
241#define MT6357_AUDADCLPWRUP BIT(12)
242#define MT6357_AUDADCLPWRDOWN 0
243#define MT6357_AUDPREAMPLGAIN_SFT 8
244#define MT6357_AUDPREAMPLGAIN_MASK GENMASK(10, 8)
245#define MT6357_AUDPREAMPLGAIN_MAX 4
246#define MT6357_AUDPREAMPLINPUTSEL_SFT 6
247#define MT6357_AUDPREAMPLINPUTSEL_MASK_NOSFT GENMASK(1, 0)
248#define MT6357_AUDPREAMPLDCPRECHARGE_MASK BIT(2)
249#define MT6357_AUDPREAMPLDCPRECHARGE_ENABLE BIT(2)
250#define MT6357_AUDPREAMPLDCPRECHARGE_DISABLE 0
251#define MT6357_AUDPREAMPLDCCEN_MASK BIT(1)
252#define MT6357_AUDPREAMPLDCCEN_DC BIT(1)
253#define MT6357_AUDPREAMPLDCCEN_AC 0
254#define MT6357_AUDPREAMPLON_MASK BIT(0)
255#define MT6357_AUDPREAMPLON_ENABLE BIT(0)
256#define MT6357_AUDPREAMPLON_DISABLE 0
257
258/* MT6357_AUDENC_ANA_CON1 */
259#define MT6357_AUDADCRINPUTSEL_MASK GENMASK(14, 13)
260#define MT6357_AUDADCRINPUTSEL_PREAMPLIFIER BIT(14)
261#define MT6357_AUDADCRINPUTSEL_IDLE 0
262#define MT6357_AUDADCRPWRUP_SFT 12
263#define MT6357_AUDADCRPWRUP_MASK BIT(12)
264#define MT6357_AUDADCRPWRUP BIT(12)
265#define MT6357_AUDADCRPWRDOWN 0
266#define MT6357_AUDPREAMPRGAIN_SFT 8
267#define MT6357_AUDPREAMPRGAIN_MASK GENMASK(10, 8)
268#define MT6357_AUDPREAMPRGAIN_MAX 4
269#define MT6357_AUDPREAMPRINPUTSEL_SFT 6
270#define MT6357_AUDPREAMPRINPUTSEL_MASK_NOSFT GENMASK(1, 0)
271#define MT6357_AUDPREAMPRDCPRECHARGE_MASK BIT(2)
272#define MT6357_AUDPREAMPRDCPRECHARGE_ENABLE BIT(2)
273#define MT6357_AUDPREAMPRDCPRECHARGE_DISABLE 0
274#define MT6357_AUDPREAMPRDCCEN_MASK BIT(1)
275#define MT6357_AUDPREAMPRDCCEN_DC BIT(1)
276#define MT6357_AUDPREAMPRDCCEN_AC 0
277#define MT6357_AUDPREAMPRON_MASK BIT(0)
278#define MT6357_AUDPREAMPRON_ENABLE BIT(0)
279#define MT6357_AUDPREAMPRON_DISABLE 0
280
281/* MT6357_AUDENC_ANA_CON6 */
282#define MT6357_CLKSQ_EN_SFT 0
283
284/* MT6357_AUDENC_ANA_CON7 */
285#define MT6357_AUDDIGMICBIAS_MASK GENMASK(2, 1)
286#define MT6357_AUDDIGMICBIAS_DEFAULT_VALUE BIT(2)
287#define MT6357_AUDDIGMICBIAS_OFF 0
288#define MT6357_AUDDIGMICEN_MASK BIT(0)
289#define MT6357_AUDDIGMICEN_ENABLE BIT(0)
290#define MT6357_AUDDIGMICEN_DISABLE 0
291
292/* MT6357_AUDENC_ANA_CON8 */
293#define MT6357_AUD_MICBIAS0_DCSW2N_EN_MASK BIT(14)
294#define MT6357_AUD_MICBIAS0_DCSW2N_ENABLE BIT(14)
295#define MT6357_AUD_MICBIAS0_DCSW2N_DISABLE 0
296#define MT6357_AUD_MICBIAS0_DCSW2P2_EN_MASK BIT(13)
297#define MT6357_AUD_MICBIAS0_DCSW2P2_ENABLE BIT(13)
298#define MT6357_AUD_MICBIAS0_DCSW2P2_DISABLE 0
299#define MT6357_AUD_MICBIAS0_DCSW2P1_EN_MASK BIT(12)
300#define MT6357_AUD_MICBIAS0_DCSW2P1_ENABLE BIT(12)
301#define MT6357_AUD_MICBIAS0_DCSW2P1_DISABLE 0
302#define MT6357_AUD_MICBIAS0_DCSW0N_EN_MASK BIT(10)
303#define MT6357_AUD_MICBIAS0_DCSW0N_ENABLE BIT(10)
304#define MT6357_AUD_MICBIAS0_DCSWN_DISABLE 0
305#define MT6357_AUD_MICBIAS0_DCSW0P2_EN_MASK BIT(9)
306#define MT6357_AUD_MICBIAS0_DCSW0P2_ENABLE BIT(9)
307#define MT6357_AUD_MICBIAS0_DCSW0P2_DISABLE 0
308#define MT6357_AUD_MICBIAS0_DCSW0P1_EN_MASK BIT(8)
309#define MT6357_AUD_MICBIAS0_DCSW0P1_ENABLE BIT(8)
310#define MT6357_AUD_MICBIAS0_DCSW0P1_DISABLE 0
311#define MT6357_AUD_MICBIAS0_VREF_MASK GENMASK(6, 4)
312#define MT6357_AUD_MICBIAS0_VREF_SFT 4
313#define MT6357_AUD_MICBIAS0_PWD_SFT 0
314
315#define MT6357_AUD_MICBIAS0_DC_MASK (MT6357_AUD_MICBIAS0_DCSW2N_EN_MASK | \
316 MT6357_AUD_MICBIAS0_DCSW2P2_EN_MASK | \
317 MT6357_AUD_MICBIAS0_DCSW2P1_EN_MASK | \
318 MT6357_AUD_MICBIAS0_DCSW0N_EN_MASK | \
319 MT6357_AUD_MICBIAS0_DCSW0P2_EN_MASK | \
320 MT6357_AUD_MICBIAS0_DCSW0P1_EN_MASK)
321
322#define MT6357_AUD_MICBIAS0_DC_ENABLE_ALL (MT6357_AUD_MICBIAS0_DCSW2N_ENABLE | \
323 MT6357_AUD_MICBIAS0_DCSW2P2_ENABLE | \
324 MT6357_AUD_MICBIAS0_DCSW2P1_ENABLE | \
325 MT6357_AUD_MICBIAS0_DCSW0N_ENABLE | \
326 MT6357_AUD_MICBIAS0_DCSW0P2_ENABLE | \
327 MT6357_AUD_MICBIAS0_DCSW0P1_ENABLE)
328
329#define MT6357_AUD_MICBIAS0_DC_ENABLE_P1 (MT6357_AUD_MICBIAS0_DCSW2P1_ENABLE | \
330 MT6357_AUD_MICBIAS0_DCSW0P1_ENABLE)
331
332#define MT6357_AUD_MICBIAS0_DC_DISABLE_ALL 0
333
334/* MT6357_AUDENC_ANA_CON9 */
335#define MT6357_AUD_MICBIAS1_DCSW1P_EN_MASK BIT(8)
336#define MT6357_AUD_MICBIAS1_DCSW1P_ENABLE BIT(8)
337#define MT6357_AUD_MICBIAS1_DCSW1P_DISABLE 0
338#define MT6357_AUD_MICBIAS1_VREF_MASK GENMASK(6, 4)
339#define MT6357_AUD_MICBIAS1_VREF_SFT 4
340#define MT6357_AUD_MICBIAS1_PWD_SFT 0
341
342/* MT6357_AUDDEC_ANA_CON0 */
343#define MT6357_AUD_HPR_SC_VAUDP15_MASK BIT(13)
344#define MT6357_AUD_HPR_SC_VAUDP15_DISABLE BIT(13)
345#define MT6357_AUD_HPR_SC_VAUDP15_ENABLE 0
346#define MT6357_AUD_HPL_SC_VAUDP15_MASK BIT(12)
347#define MT6357_AUD_HPL_SC_VAUDP15_DISABLE BIT(12)
348#define MT6357_AUD_HPL_SC_VAUDP15_ENABLE 0
349#define MT6357_AUD_HPR_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
350#define MT6357_AUD_HPR_MUX_INPUT_VAUDP15_SFT 10
351#define MT6357_AUD_HPL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
352#define MT6357_AUD_HPL_MUX_INPUT_VAUDP15_SFT 8
353#define MT6357_AUD_HPR_BIAS_VAUDP15_MASK BIT(7)
354#define MT6357_AUD_HPR_BIAS_VAUDP15_ENABLE BIT(7)
355#define MT6357_AUD_HPR_BIAS_VAUDP15_DISABLE 0
356#define MT6357_AUD_HPL_BIAS_VAUDP15_MASK BIT(6)
357#define MT6357_AUD_HPL_BIAS_VAUDP15_ENABLE BIT(6)
358#define MT6357_AUD_HPL_BIAS_VAUDP15_DISABLE 0
359#define MT6357_AUD_HPR_PWRUP_VAUDP15_MASK BIT(5)
360#define MT6357_AUD_HPR_PWRUP_VAUDP15_ENABLE BIT(5)
361#define MT6357_AUD_HPR_PWRUP_VAUDP15_DISABLE 0
362#define MT6357_AUD_HPL_PWRUP_VAUDP15_MASK BIT(4)
363#define MT6357_AUD_HPL_PWRUP_VAUDP15_ENABLE BIT(4)
364#define MT6357_AUD_HPL_PWRUP_VAUDP15_DISABLE 0
365#define MT6357_AUD_DACL_PWRUP_VA28_MASK BIT(3)
366#define MT6357_AUD_DACL_PWRUP_VA28_ENABLE BIT(3)
367#define MT6357_AUD_DACL_PWRUP_VA28_DISABLE 0
368#define MT6357_AUD_DACR_PWRUP_VA28_MASK BIT(2)
369#define MT6357_AUD_DACR_PWRUP_VA28_ENABLE BIT(2)
370#define MT6357_AUD_DACR_PWRUP_VA28_DISABLE 0
371#define MT6357_AUD_DACR_PWRUP_VAUDP15_MASK BIT(1)
372#define MT6357_AUD_DACR_PWRUP_VAUDP15_ENABLE BIT(1)
373#define MT6357_AUD_DACR_PWRUP_VAUDP15_DISABLE 0
374#define MT6357_AUD_DACL_PWRUP_VAUDP15_MASK BIT(0)
375#define MT6357_AUD_DACL_PWRUP_VAUDP15_ENABLE BIT(0)
376#define MT6357_AUD_DACL_PWRUP_VAUDP15_DISABLE 0
377
378/* MT6357_AUDDEC_ANA_CON1 */
379#define MT6357_HPROUT_STG_CTRL_VAUDP15_MASK GENMASK(14, 12)
380#define MT6357_HPROUT_STG_CTRL_VAUDP15_SFT 12
381#define MT6357_HPLOUT_STG_CTRL_VAUDP15_MASK GENMASK(10, 8)
382#define MT6357_HPLOUT_STG_CTRL_VAUDP15_SFT 8
383#define MT6357_HPLOUT_STG_CTRL_VAUDP15_MAX 7
384#define MT6357_HPR_SHORT2HPR_AUX_VAUDP15_MASK BIT(7)
385#define MT6357_HPR_SHORT2HPR_AUX_VAUDP15_ENABLE BIT(7)
386#define MT6357_HPR_SHORT2HPR_AUX_VAUDP15_DISABLE 0
387#define MT6357_HPL_SHORT2HPR_AUX_VAUDP15_MASK BIT(6)
388#define MT6357_HPL_SHORT2HPR_AUX_VAUDP15_ENABLE BIT(6)
389#define MT6357_HPL_SHORT2HPR_AUX_VAUDP15_DISABLE 0
390#define MT6357_HPR_AUX_FBRSW_VAUDP15_MASK BIT(5)
391#define MT6357_HPR_AUX_FBRSW_VAUDP15_ENABLE BIT(5)
392#define MT6357_HPR_AUX_FBRSW_VAUDP15_DISABLE 0
393#define MT6357_HPL_AUX_FBRSW_VAUDP15_MASK BIT(4)
394#define MT6357_HPL_AUX_FBRSW_VAUDP15_ENABLE BIT(4)
395#define MT6357_HPL_AUX_FBRSW_VAUDP15_DISABLE 0
396#define MT6357_HPROUT_AUX_PWRUP_VAUDP15_MASK BIT(3)
397#define MT6357_HPROUT_AUX_PWRUP_VAUDP15_ENABLE BIT(3)
398#define MT6357_HPROUT_AUX_PWRUP_VAUDP15_DISABLE 0
399#define MT6357_HPLOUT_AUX_PWRUP_VAUDP15_MASK BIT(2)
400#define MT6357_HPLOUT_AUX_PWRUP_VAUDP15_ENABLE BIT(2)
401#define MT6357_HPLOUT_AUX_PWRUP_VAUDP15_DISABLE 0
402#define MT6357_HPROUT_PWRUP_VAUDP15_MASK BIT(1)
403#define MT6357_HPROUT_PWRUP_VAUDP15_ENABLE BIT(1)
404#define MT6357_HPROUT_PWRUP_VAUDP15_DISABLE 0
405#define MT6357_HPLOUT_PWRUP_VAUDP15_MASK BIT(0)
406#define MT6357_HPLOUT_PWRUP_VAUDP15_ENABLE BIT(0)
407#define MT6357_HPLOUT_PWRUP_VAUDP15_DISABLE 0
408
409/* MT6357_AUDDEC_ANA_CON2 */
410#define MT6357_HPP_SHORT_2VCM_VAUDP15_MASK BIT(10)
411#define MT6357_HPP_SHORT_2VCM_VAUDP15_ENABLE BIT(10)
412#define MT6357_HPP_SHORT_2VCM_VAUDP15_DISABLE 0
413#define MT6357_AUD_REFN_DERES_VAUDP15_MASK BIT(9)
414#define MT6357_AUD_REFN_DERES_VAUDP15_ENABLE BIT(9)
415#define MT6357_AUD_REFN_DERES_VAUDP15_DISABLE 0
416#define MT6357_HPROUT_STB_ENH_VAUDP15_MASK GENMASK(6, 4)
417#define MT6357_HPROUT_STB_ENH_VAUDP15_OPEN 0
418#define MT6357_HPROUT_STB_ENH_VAUDP15_NOPEN_P250 BIT(4)
419#define MT6357_HPROUT_STB_ENH_VAUDP15_N470_POPEN BIT(5)
420#define MT6357_HPROUT_STB_ENH_VAUDP15_N470_P250 (BIT(4) | BIT(5))
421#define MT6357_HPROUT_STB_ENH_VAUDP15_NOPEN_P470 (BIT(4) | BIT(6))
422#define MT6357_HPROUT_STB_ENH_VAUDP15_N470_P470 (BIT(4) | BIT(5) | BIT(6))
423#define MT6357_HPLOUT_STB_ENH_VAUDP15_MASK GENMASK(2, 0)
424#define MT6357_HPLOUT_STB_ENH_VAUDP15_OPEN 0
425#define MT6357_HPLOUT_STB_ENH_VAUDP15_NOPEN_P250 BIT(0)
426#define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_POPEN BIT(1)
427#define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_P250 (BIT(0) | BIT(1))
428#define MT6357_HPLOUT_STB_ENH_VAUDP15_NOPEN_P470 (BIT(0) | BIT(2))
429#define MT6357_HPLOUT_STB_ENH_VAUDP15_N470_P470 (BIT(0) | BIT(1) | BIT(2))
430
431/* MT6357_AUDDEC_ANA_CON3 */
432#define MT6357_AUD_HSOUT_STB_ENH_VAUDP15_MASK BIT(7)
433#define MT6357_AUD_HSOUT_STB_ENH_VAUDP15_ENABLE BIT(7)
434#define MT6357_AUD_HSOUT_STB_ENH_VAUDP15_DISABLE 0
435#define MT6357_AUD_HS_SC_VAUDP15_MASK BIT(4)
436#define MT6357_AUD_HS_SC_VAUDP15_DISABLE BIT(4)
437#define MT6357_AUD_HS_SC_VAUDP15_ENABLE 0
438#define MT6357_AUD_HS_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
439#define MT6357_AUD_HS_MUX_INPUT_VAUDP15_SFT 2
440#define MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_MASK BIT(1)
441#define MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_ENABLE BIT(1)
442#define MT6357_AUD_HS_PWRUP_BIAS_VAUDP15_DISABLE 0
443#define MT6357_AUD_HS_PWRUP_VAUDP15_MASK BIT(0)
444#define MT6357_AUD_HS_PWRUP_VAUDP15_ENABLE BIT(0)
445#define MT6357_AUD_HS_PWRUP_VAUDP15_DISABLE 0
446
447/* MT6357_AUDDEC_ANA_CON4 */
448#define MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_MASK BIT(8)
449#define MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_ENABLE BIT(8)
450#define MT6357_AUD_LOLOUT_STB_ENH_VAUDP15_DISABLE 0
451#define MT6357_AUD_LOL_SC_VAUDP15_MASK BIT(4)
452#define MT6357_AUD_LOL_SC_VAUDP15_DISABLE BIT(4)
453#define MT6357_AUD_LOL_SC_VAUDP15_ENABLE 0
454#define MT6357_AUD_LOL_MUX_INPUT_VAUDP15_MASK_NOSFT GENMASK(1, 0)
455#define MT6357_AUD_LOL_MUX_INPUT_VAUDP15_SFT 2
456#define MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_MASK BIT(1)
457#define MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_ENABLE BIT(1)
458#define MT6357_AUD_LOL_PWRUP_BIAS_VAUDP15_DISABLE 0
459#define MT6357_AUD_LOL_PWRUP_VAUDP15_MASK BIT(0)
460#define MT6357_AUD_LOL_PWRUP_VAUDP15_ENABLE BIT(0)
461#define MT6357_AUD_LOL_PWRUP_VAUDP15_DISABLE 0
462
463/* MT6357_AUDDEC_ANA_CON6 */
464#define MT6357_HP_AUX_LOOP_GAIN_MASK GENMASK(15, 12)
465#define MT6357_HP_AUX_LOOP_GAIN_SFT 12
466#define MT6357_HP_AUX_LOOP_GAIN_MAX 0x0f
467#define MT6357_HPR_AUX_CMFB_LOOP_MASK BIT(11)
468#define MT6357_HPR_AUX_CMFB_LOOP_ENABLE BIT(11)
469#define MT6357_HPR_AUX_CMFB_LOOP_DISABLE 0
470#define MT6357_HPL_AUX_CMFB_LOOP_MASK BIT(10)
471#define MT6357_HPL_AUX_CMFB_LOOP_ENABLE BIT(10)
472#define MT6357_HPL_AUX_CMFB_LOOP_DISABLE 0
473#define MT6357_HPRL_MAIN_CMFB_LOOP_MASK BIT(9)
474#define MT6357_HPRL_MAIN_CMFB_LOOP_ENABLE BIT(9)
475#define MT6357_HPRL_MAIN_CMFB_LOOP_DISABLE 0
476#define MT6357_HP_CMFB_RST_MASK BIT(7)
477#define MT6357_HP_CMFB_RST_NORMAL BIT(7)
478#define MT6357_HP_CMFB_RST_RESET 0
479#define MT6357_DAC_LOW_NOISE_MODE_MASK BIT(0)
480#define MT6357_DAC_LOW_NOISE_MODE_ENABLE BIT(0)
481#define MT6357_DAC_LOW_NOISE_MODE_DISABLE 0
482
483/* MT6357_AUDDEC_ANA_CON7 */
484#define MT6357_HP_IVBUF_DEGAIN_SFT 2
485#define MT6357_HP_IVBUF_DEGAIN_MAX 1
486
487/* MT6357_AUDDEC_ANA_CON10 */
488#define MT6357_AUD_IBIAS_PWRDN_VAUDP15_MASK BIT(8)
489#define MT6357_AUD_IBIAS_PWRDN_VAUDP15_DISABLE BIT(8)
490#define MT6357_AUD_IBIAS_PWRDN_VAUDP15_ENABLE 0
491
492/* MT6357_AUDDEC_ANA_CON11 */
493#define MT6357_RSTB_ENCODER_VA28_MASK BIT(5)
494#define MT6357_RSTB_ENCODER_VA28_ENABLE BIT(5)
495#define MT6357_RSTB_ENCODER_VA28_DISABLE 0
496#define MT6357_AUDGLB_PWRDN_VA28_SFT 4
497#define MT6357_RSTB_DECODER_VA28_MASK BIT(0)
498#define MT6357_RSTB_DECODER_VA28_ENABLE BIT(0)
499#define MT6357_RSTB_DECODER_VA28_DISABLE 0
500
501/* MT6357_AUDDEC_ANA_CON12 */
502#define MT6357_VA28REFGEN_EN_VA28_MASK BIT(13)
503#define MT6357_VA28REFGEN_EN_VA28_ENABLE BIT(13)
504#define MT6357_VA28REFGEN_EN_VA28_DISABLE 0
505#define MT6357_VA33REFGEN_EN_VA18_MASK BIT(12)
506#define MT6357_VA33REFGEN_EN_VA18_ENABLE BIT(12)
507#define MT6357_VA33REFGEN_EN_VA18_DISABLE 0
508#define MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_MASK BIT(10)
509#define MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_ENABLE BIT(10)
510#define MT6357_LCLDO_ENC_REMOTE_SENSE_VA28_DISABLE 0
511#define MT6357_LCLDO_ENC_EN_VA28_MASK BIT(8)
512#define MT6357_LCLDO_ENC_EN_VA28_ENABLE BIT(8)
513#define MT6357_LCLDO_ENC_EN_VA28_DISABLE 0
514#define MT6357_LCLDO_REMOTE_SENSE_VA18_MASK BIT(6)
515#define MT6357_LCLDO_REMOTE_SENSE_VA18_ENABLE BIT(6)
516#define MT6357_LCLDO_REMOTE_SENSE_VA18_DISABLE 0
517#define MT6357_LCLDO_EN_VA18_MASK BIT(4)
518#define MT6357_LCLDO_EN_VA18_ENABLE BIT(4)
519#define MT6357_LCLDO_EN_VA18_DISABLE 0
520#define MT6357_HCLDO_REMOTE_SENSE_VA18_MASK BIT(2)
521#define MT6357_HCLDO_REMOTE_SENSE_VA18_ENABLE BIT(2)
522#define MT6357_HCLDO_REMOTE_SENSE_VA18_DISABLE 0
523#define MT6357_HCLDO_EN_VA18_MASK BIT(0)
524#define MT6357_HCLDO_EN_VA18_ENABLE BIT(0)
525#define MT6357_HCLDO_EN_VA18_DISABLE 0
526
527/* MT6357_AUDDEC_ANA_CON13 */
528#define MT6357_NVREG_EN_VAUDP15_MASK BIT(0)
529#define MT6357_NVREG_EN_VAUDP15_ENABLE BIT(0)
530#define MT6357_NVREG_EN_VAUDP15_DISABLE 0
531
532/* MT6357_AUDDEC_ELR_0 */
533#define MT6357_AUD_HP_TRIM_EN_VAUDP15_MASK BIT(12)
534#define MT6357_AUD_HP_TRIM_EN_VAUDP15_ENABLE BIT(12)
535#define MT6357_AUD_HP_TRIM_EN_VAUDP15_DISABLE 0
536
537/* MT6357_ZCD_CON1 */
538#define MT6357_AUD_LOL_GAIN_MASK GENMASK(4, 0)
539#define MT6357_AUD_LOL_GAIN_SFT 0
540#define MT6357_AUD_LOR_GAIN_MASK GENMASK(11, 7)
541#define MT6357_AUD_LOR_GAIN_SFT 7
542#define MT6357_AUD_LO_GAIN_MAX 0x12
543
544/* MT6357_ZCD_CON2 */
545#define MT6357_AUD_HPL_GAIN_MASK GENMASK(4, 0)
546#define MT6357_AUD_HPL_GAIN_SFT 0
547#define MT6357_AUD_HPR_GAIN_MASK GENMASK(11, 7)
548#define MT6357_AUD_HPR_GAIN_SFT 7
549#define MT6357_AUD_HP_GAIN_MAX 0x12
550
551/* MT6357_ZCD_CON3 */
552#define MT6357_AUD_HS_GAIN_MASK GENMASK(4, 0)
553#define MT6357_AUD_HS_GAIN_SFT 0
554#define MT6357_AUD_HS_GAIN_MAX 0x12
555
556/* Registers list */
557/* gpio direction */
558#define MT6357_GPIO_DIR0 0x0088
559/* mosi */
560#define MT6357_GPIO_MODE2 0x00B6
561#define MT6357_GPIO_MODE2_SET 0x00B8
562#define MT6357_GPIO_MODE2_CLR 0x00BA
563/* miso */
564#define MT6357_GPIO_MODE3 0x00BC
565#define MT6357_GPIO_MODE3_SET 0x00BE
566#define MT6357_GPIO_MODE3_CLR 0x00C0
567
568#define MT6357_DCXO_CW14 0x07AC
569
570#define MT6357_AUD_TOP_CKPDN_CON0 0x208C
571#define MT6357_AUDNCP_CLKDIV_CON0 0x20B4
572#define MT6357_AUDNCP_CLKDIV_CON1 0x20B6
573#define MT6357_AUDNCP_CLKDIV_CON2 0x20B8
574#define MT6357_AUDNCP_CLKDIV_CON3 0x20BA
575#define MT6357_AUDNCP_CLKDIV_CON4 0x20BC
576#define MT6357_AFE_UL_DL_CON0 0x2108
577#define MT6357_AFE_DL_SRC2_CON0_L 0x210A
578#define MT6357_AFE_UL_SRC_CON0_H 0x210C
579#define MT6357_AFE_UL_SRC_CON0_L 0x210E
580#define MT6357_AFE_TOP_CON0 0x2110
581#define MT6357_AUDIO_TOP_CON0 0x2112
582#define MT6357_AFUNC_AUD_CON0 0x2116
583#define MT6357_AFUNC_AUD_CON2 0x211A
584#define MT6357_AFE_ADDA_MTKAIF_CFG0 0x2134
585#define MT6357_AFE_SGEN_CFG0 0x2140
586#define MT6357_AFE_DCCLK_CFG0 0x2146
587#define MT6357_AFE_DCCLK_CFG1 0x2148
588#define MT6357_AFE_AUD_PAD_TOP 0x214C
589#define MT6357_AUDENC_ANA_CON0 0x2188
590#define MT6357_AUDENC_ANA_CON1 0x218A
591#define MT6357_AUDENC_ANA_CON6 0x2194
592#define MT6357_AUDENC_ANA_CON7 0x2196
593#define MT6357_AUDENC_ANA_CON8 0x2198
594#define MT6357_AUDENC_ANA_CON9 0x219A
595#define MT6357_AUDDEC_ANA_CON0 0x2208
596#define MT6357_AUDDEC_ANA_CON1 0x220A
597#define MT6357_AUDDEC_ANA_CON2 0x220C
598#define MT6357_AUDDEC_ANA_CON3 0x220E
599#define MT6357_AUDDEC_ANA_CON4 0x2210
600#define MT6357_AUDDEC_ANA_CON6 0x2214
601#define MT6357_AUDDEC_ANA_CON7 0x2216
602#define MT6357_AUDDEC_ANA_CON10 0x221C
603#define MT6357_AUDDEC_ANA_CON11 0x221E
604#define MT6357_AUDDEC_ANA_CON12 0x2220
605#define MT6357_AUDDEC_ANA_CON13 0x2222
606#define MT6357_AUDDEC_ELR_0 0x2226
607#define MT6357_ZCD_CON1 0x228A
608#define MT6357_ZCD_CON2 0x228C
609#define MT6357_ZCD_CON3 0x228E
610
611enum {
612 DL_GAIN_8DB = 0,
613 DL_GAIN_0DB = 8,
614 DL_GAIN_N_1DB = 9,
615 DL_GAIN_N_10DB = 18,
616 DL_GAIN_N_12DB = 20,
617 DL_GAIN_N_40DB = 0x1f,
618};
619
620enum {
621 UL_GAIN_0DB = 0,
622 UL_GAIN_6DB,
623 UL_GAIN_12DB,
624 UL_GAIN_18DB,
625 UL_GAIN_24DB,
626};
627
628#define MT6357_DL_GAIN_N_40DB_REG (DL_GAIN_N_40DB << 7 | DL_GAIN_N_40DB)
629#define MT6357_DL_GAIN_REG_LEFT_MASK 0x001f
630#define MT6357_DL_GAIN_REG_LEFT_SHIFT 0
631#define MT6357_DL_GAIN_REG_RIGHT_MASK 0x0f80
632#define MT6357_DL_GAIN_REG_RIGHT_SHIFT 7
633#define MT6357_DL_GAIN_REG_MASK 0x0f9f
634
635#define MT6357_SND_SOC_ADV_MT_FMTS (\
636 SNDRV_PCM_FMTBIT_S16_LE |\
637 SNDRV_PCM_FMTBIT_S16_BE |\
638 SNDRV_PCM_FMTBIT_U16_LE |\
639 SNDRV_PCM_FMTBIT_U16_BE |\
640 SNDRV_PCM_FMTBIT_S24_LE |\
641 SNDRV_PCM_FMTBIT_S24_BE |\
642 SNDRV_PCM_FMTBIT_U24_LE |\
643 SNDRV_PCM_FMTBIT_U24_BE |\
644 SNDRV_PCM_FMTBIT_S32_LE |\
645 SNDRV_PCM_FMTBIT_S32_BE |\
646 SNDRV_PCM_FMTBIT_U32_LE |\
647 SNDRV_PCM_FMTBIT_U32_BE)
648
649#define MT6357_SOC_HIGH_USE_RATE (\
650 SNDRV_PCM_RATE_CONTINUOUS |\
651 SNDRV_PCM_RATE_8000_192000)
652
653/* codec private structure */
654struct mt6357_priv {
655 struct device *dev;
656 struct regmap *regmap;
657 bool pull_down_needed;
658 int hp_channel_number;
659};
660#endif