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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 */
5
6#include <linux/module.h>
7#include <linux/moduleparam.h>
8#include <linux/init.h>
9#include <linux/delay.h>
10#include <linux/pm.h>
11#include <linux/i2c.h>
12#include <linux/slab.h>
13#include <linux/platform_device.h>
14#include <linux/regmap.h>
15#include <sound/core.h>
16#include <sound/pcm.h>
17#include <sound/pcm_params.h>
18#include <sound/soc.h>
19#include <sound/tlv.h>
20#include "ml26124.h"
21
22#define DVOL_CTL_DVMUTE_ON BIT(4) /* Digital volume MUTE On */
23#define DVOL_CTL_DVMUTE_OFF 0 /* Digital volume MUTE Off */
24#define ML26124_SAI_NO_DELAY BIT(1)
25#define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0)) /* For mono (Telecodec) */
26#define ML26134_CACHESIZE 212
27#define ML26124_VMID BIT(1)
28#define ML26124_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
29 SNDRV_PCM_RATE_48000)
30#define ML26124_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |\
31 SNDRV_PCM_FMTBIT_S32_LE)
32#define ML26124_NUM_REGISTER ML26134_CACHESIZE
33
34struct ml26124_priv {
35 u32 mclk;
36 u32 rate;
37 struct regmap *regmap;
38 int clk_in;
39 struct snd_pcm_substream *substream;
40};
41
42struct clk_coeff {
43 u32 mclk;
44 u32 rate;
45 u8 pllnl;
46 u8 pllnh;
47 u8 pllml;
48 u8 pllmh;
49 u8 plldiv;
50};
51
52/* ML26124 configuration */
53static const DECLARE_TLV_DB_SCALE(digital_tlv, -7150, 50, 0);
54
55static const DECLARE_TLV_DB_SCALE(alclvl, -2250, 150, 0);
56static const DECLARE_TLV_DB_SCALE(mingain, -1200, 600, 0);
57static const DECLARE_TLV_DB_SCALE(maxgain, -675, 600, 0);
58static const DECLARE_TLV_DB_SCALE(boost_vol, -1200, 75, 0);
59
60static const char * const ml26124_companding[] = {"16bit PCM", "u-law",
61 "A-law"};
62
63static SOC_ENUM_SINGLE_DECL(ml26124_adc_companding_enum,
64 ML26124_SAI_TRANS_CTL, 6, ml26124_companding);
65
66static SOC_ENUM_SINGLE_DECL(ml26124_dac_companding_enum,
67 ML26124_SAI_RCV_CTL, 6, ml26124_companding);
68
69static const struct snd_kcontrol_new ml26124_snd_controls[] = {
70 SOC_SINGLE_TLV("Capture Digital Volume", ML26124_RECORD_DIG_VOL, 0,
71 0xff, 1, digital_tlv),
72 SOC_SINGLE_TLV("Playback Digital Volume", ML26124_PLBAK_DIG_VOL, 0,
73 0xff, 1, digital_tlv),
74 SOC_SINGLE_TLV("Digital Boost Volume", ML26124_DIGI_BOOST_VOL, 0,
75 0x3f, 0, boost_vol),
76 SOC_SINGLE_TLV("EQ Band0 Volume", ML26124_EQ_GAIN_BRAND0, 0,
77 0xff, 1, digital_tlv),
78 SOC_SINGLE_TLV("EQ Band1 Volume", ML26124_EQ_GAIN_BRAND1, 0,
79 0xff, 1, digital_tlv),
80 SOC_SINGLE_TLV("EQ Band2 Volume", ML26124_EQ_GAIN_BRAND2, 0,
81 0xff, 1, digital_tlv),
82 SOC_SINGLE_TLV("EQ Band3 Volume", ML26124_EQ_GAIN_BRAND3, 0,
83 0xff, 1, digital_tlv),
84 SOC_SINGLE_TLV("EQ Band4 Volume", ML26124_EQ_GAIN_BRAND4, 0,
85 0xff, 1, digital_tlv),
86 SOC_SINGLE_TLV("ALC Target Level", ML26124_ALC_TARGET_LEV, 0,
87 0xf, 1, alclvl),
88 SOC_SINGLE_TLV("ALC Min Input Volume", ML26124_ALC_MAXMIN_GAIN, 0,
89 7, 0, mingain),
90 SOC_SINGLE_TLV("ALC Max Input Volume", ML26124_ALC_MAXMIN_GAIN, 4,
91 7, 1, maxgain),
92 SOC_SINGLE_TLV("Playback Limiter Min Input Volume",
93 ML26124_PL_MAXMIN_GAIN, 0, 7, 0, mingain),
94 SOC_SINGLE_TLV("Playback Limiter Max Input Volume",
95 ML26124_PL_MAXMIN_GAIN, 4, 7, 1, maxgain),
96 SOC_SINGLE_TLV("Playback Boost Volume", ML26124_PLYBAK_BOST_VOL, 0,
97 0x3f, 0, boost_vol),
98 SOC_SINGLE("DC High Pass Filter Switch", ML26124_FILTER_EN, 0, 1, 0),
99 SOC_SINGLE("Noise High Pass Filter Switch", ML26124_FILTER_EN, 1, 1, 0),
100 SOC_SINGLE("ZC Switch", ML26124_PW_ZCCMP_PW_MNG, 1,
101 1, 0),
102 SOC_SINGLE("EQ Band0 Switch", ML26124_FILTER_EN, 2, 1, 0),
103 SOC_SINGLE("EQ Band1 Switch", ML26124_FILTER_EN, 3, 1, 0),
104 SOC_SINGLE("EQ Band2 Switch", ML26124_FILTER_EN, 4, 1, 0),
105 SOC_SINGLE("EQ Band3 Switch", ML26124_FILTER_EN, 5, 1, 0),
106 SOC_SINGLE("EQ Band4 Switch", ML26124_FILTER_EN, 6, 1, 0),
107 SOC_SINGLE("Play Limiter", ML26124_DVOL_CTL, 0, 1, 0),
108 SOC_SINGLE("Capture Limiter", ML26124_DVOL_CTL, 1, 1, 0),
109 SOC_SINGLE("Digital Volume Fade Switch", ML26124_DVOL_CTL, 3, 1, 0),
110 SOC_SINGLE("Digital Switch", ML26124_DVOL_CTL, 4, 1, 0),
111 SOC_ENUM("DAC Companding", ml26124_dac_companding_enum),
112 SOC_ENUM("ADC Companding", ml26124_adc_companding_enum),
113};
114
115static const struct snd_kcontrol_new ml26124_output_mixer_controls[] = {
116 SOC_DAPM_SINGLE("DAC Switch", ML26124_SPK_AMP_OUT, 1, 1, 0),
117 SOC_DAPM_SINGLE("Line in loopback Switch", ML26124_SPK_AMP_OUT, 3, 1,
118 0),
119 SOC_DAPM_SINGLE("PGA Switch", ML26124_SPK_AMP_OUT, 5, 1, 0),
120};
121
122/* Input mux */
123static const char * const ml26124_input_select[] = {"Analog MIC SingleEnded in",
124 "Digital MIC in", "Analog MIC Differential in"};
125
126static SOC_ENUM_SINGLE_DECL(ml26124_insel_enum,
127 ML26124_MIC_IF_CTL, 0, ml26124_input_select);
128
129static const struct snd_kcontrol_new ml26124_input_mux_controls =
130 SOC_DAPM_ENUM("Input Select", ml26124_insel_enum);
131
132static const struct snd_kcontrol_new ml26124_line_control =
133 SOC_DAPM_SINGLE("Switch", ML26124_PW_LOUT_PW_MNG, 1, 1, 0);
134
135static const struct snd_soc_dapm_widget ml26124_dapm_widgets[] = {
136 SND_SOC_DAPM_SUPPLY("MCLKEN", ML26124_CLK_EN, 0, 0, NULL, 0),
137 SND_SOC_DAPM_SUPPLY("PLLEN", ML26124_CLK_EN, 1, 0, NULL, 0),
138 SND_SOC_DAPM_SUPPLY("PLLOE", ML26124_CLK_EN, 2, 0, NULL, 0),
139 SND_SOC_DAPM_SUPPLY("MICBIAS", ML26124_PW_REF_PW_MNG, 2, 0, NULL, 0),
140 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
141 &ml26124_output_mixer_controls[0],
142 ARRAY_SIZE(ml26124_output_mixer_controls)),
143 SND_SOC_DAPM_DAC("DAC", "Playback", ML26124_PW_DAC_PW_MNG, 1, 0),
144 SND_SOC_DAPM_ADC("ADC", "Capture", ML26124_PW_IN_PW_MNG, 1, 0),
145 SND_SOC_DAPM_PGA("PGA", ML26124_PW_IN_PW_MNG, 3, 0, NULL, 0),
146 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
147 &ml26124_input_mux_controls),
148 SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
149 &ml26124_line_control),
150 SND_SOC_DAPM_INPUT("MDIN"),
151 SND_SOC_DAPM_INPUT("MIN"),
152 SND_SOC_DAPM_INPUT("LIN"),
153 SND_SOC_DAPM_OUTPUT("SPOUT"),
154 SND_SOC_DAPM_OUTPUT("LOUT"),
155};
156
157static const struct snd_soc_dapm_route ml26124_intercon[] = {
158 /* Supply */
159 {"DAC", NULL, "MCLKEN"},
160 {"ADC", NULL, "MCLKEN"},
161 {"DAC", NULL, "PLLEN"},
162 {"ADC", NULL, "PLLEN"},
163 {"DAC", NULL, "PLLOE"},
164 {"ADC", NULL, "PLLOE"},
165
166 /* output mixer */
167 {"Output Mixer", "DAC Switch", "DAC"},
168 {"Output Mixer", "Line in loopback Switch", "LIN"},
169
170 /* outputs */
171 {"LOUT", NULL, "Output Mixer"},
172 {"SPOUT", NULL, "Output Mixer"},
173 {"Line Out Enable", NULL, "LOUT"},
174
175 /* input */
176 {"ADC", NULL, "Input Mux"},
177 {"Input Mux", "Analog MIC SingleEnded in", "PGA"},
178 {"Input Mux", "Analog MIC Differential in", "PGA"},
179 {"PGA", NULL, "MIN"},
180};
181
182/* PLLOutputFreq(Hz) = InputMclkFreq(Hz) * PLLM / (PLLN * PLLDIV) */
183static const struct clk_coeff coeff_div[] = {
184 {12288000, 16000, 0xc, 0x0, 0x20, 0x0, 0x4},
185 {12288000, 32000, 0xc, 0x0, 0x20, 0x0, 0x4},
186 {12288000, 48000, 0xc, 0x0, 0x30, 0x0, 0x4},
187};
188
189static const struct reg_default ml26124_reg[] = {
190 /* CLOCK control Register */
191 {0x00, 0x00 }, /* Sampling Rate */
192 {0x02, 0x00}, /* PLL NL */
193 {0x04, 0x00}, /* PLLNH */
194 {0x06, 0x00}, /* PLLML */
195 {0x08, 0x00}, /* MLLMH */
196 {0x0a, 0x00}, /* PLLDIV */
197 {0x0c, 0x00}, /* Clock Enable */
198 {0x0e, 0x00}, /* CLK Input/Output Control */
199
200 /* System Control Register */
201 {0x10, 0x00}, /* Software RESET */
202 {0x12, 0x00}, /* Record/Playback Run */
203 {0x14, 0x00}, /* Mic Input/Output control */
204
205 /* Power Management Register */
206 {0x20, 0x00}, /* Reference Power Management */
207 {0x22, 0x00}, /* Input Power Management */
208 {0x24, 0x00}, /* DAC Power Management */
209 {0x26, 0x00}, /* SP-AMP Power Management */
210 {0x28, 0x00}, /* LINEOUT Power Management */
211 {0x2a, 0x00}, /* VIDEO Power Management */
212 {0x2e, 0x00}, /* AC-CMP Power Management */
213
214 /* Analog reference Control Register */
215 {0x30, 0x04}, /* MICBIAS Voltage Control */
216
217 /* Input/Output Amplifier Control Register */
218 {0x32, 0x10}, /* MIC Input Volume */
219 {0x38, 0x00}, /* Mic Boost Volume */
220 {0x3a, 0x33}, /* Speaker AMP Volume */
221 {0x48, 0x00}, /* AMP Volume Control Function Enable */
222 {0x4a, 0x00}, /* Amplifier Volume Fader Control */
223
224 /* Analog Path Control Register */
225 {0x54, 0x00}, /* Speaker AMP Output Control */
226 {0x5a, 0x00}, /* Mic IF Control */
227 {0xe8, 0x01}, /* Mic Select Control */
228
229 /* Audio Interface Control Register */
230 {0x60, 0x00}, /* SAI-Trans Control */
231 {0x62, 0x00}, /* SAI-Receive Control */
232 {0x64, 0x00}, /* SAI Mode select */
233
234 /* DSP Control Register */
235 {0x66, 0x01}, /* Filter Func Enable */
236 {0x68, 0x00}, /* Volume Control Func Enable */
237 {0x6A, 0x00}, /* Mixer & Volume Control*/
238 {0x6C, 0xff}, /* Record Digital Volume */
239 {0x70, 0xff}, /* Playback Digital Volume */
240 {0x72, 0x10}, /* Digital Boost Volume */
241 {0x74, 0xe7}, /* EQ gain Band0 */
242 {0x76, 0xe7}, /* EQ gain Band1 */
243 {0x78, 0xe7}, /* EQ gain Band2 */
244 {0x7A, 0xe7}, /* EQ gain Band3 */
245 {0x7C, 0xe7}, /* EQ gain Band4 */
246 {0x7E, 0x00}, /* HPF2 CutOff*/
247 {0x80, 0x00}, /* EQ Band0 Coef0L */
248 {0x82, 0x00}, /* EQ Band0 Coef0H */
249 {0x84, 0x00}, /* EQ Band0 Coef0L */
250 {0x86, 0x00}, /* EQ Band0 Coef0H */
251 {0x88, 0x00}, /* EQ Band1 Coef0L */
252 {0x8A, 0x00}, /* EQ Band1 Coef0H */
253 {0x8C, 0x00}, /* EQ Band1 Coef0L */
254 {0x8E, 0x00}, /* EQ Band1 Coef0H */
255 {0x90, 0x00}, /* EQ Band2 Coef0L */
256 {0x92, 0x00}, /* EQ Band2 Coef0H */
257 {0x94, 0x00}, /* EQ Band2 Coef0L */
258 {0x96, 0x00}, /* EQ Band2 Coef0H */
259 {0x98, 0x00}, /* EQ Band3 Coef0L */
260 {0x9A, 0x00}, /* EQ Band3 Coef0H */
261 {0x9C, 0x00}, /* EQ Band3 Coef0L */
262 {0x9E, 0x00}, /* EQ Band3 Coef0H */
263 {0xA0, 0x00}, /* EQ Band4 Coef0L */
264 {0xA2, 0x00}, /* EQ Band4 Coef0H */
265 {0xA4, 0x00}, /* EQ Band4 Coef0L */
266 {0xA6, 0x00}, /* EQ Band4 Coef0H */
267
268 /* ALC Control Register */
269 {0xb0, 0x00}, /* ALC Mode */
270 {0xb2, 0x02}, /* ALC Attack Time */
271 {0xb4, 0x03}, /* ALC Decay Time */
272 {0xb6, 0x00}, /* ALC Hold Time */
273 {0xb8, 0x0b}, /* ALC Target Level */
274 {0xba, 0x70}, /* ALC Max/Min Gain */
275 {0xbc, 0x00}, /* Noise Gate Threshold */
276 {0xbe, 0x00}, /* ALC ZeroCross TimeOut */
277
278 /* Playback Limiter Control Register */
279 {0xc0, 0x04}, /* PL Attack Time */
280 {0xc2, 0x05}, /* PL Decay Time */
281 {0xc4, 0x0d}, /* PL Target Level */
282 {0xc6, 0x70}, /* PL Max/Min Gain */
283 {0xc8, 0x10}, /* Playback Boost Volume */
284 {0xca, 0x00}, /* PL ZeroCross TimeOut */
285
286 /* Video Amplifier Control Register */
287 {0xd0, 0x01}, /* VIDEO AMP Gain Control */
288 {0xd2, 0x01}, /* VIDEO AMP Setup 1 */
289 {0xd4, 0x01}, /* VIDEO AMP Control2 */
290};
291
292/* Get sampling rate value of sampling rate setting register (0x0) */
293static inline int get_srate(int rate)
294{
295 int srate;
296
297 switch (rate) {
298 case 16000:
299 srate = 3;
300 break;
301 case 32000:
302 srate = 6;
303 break;
304 case 48000:
305 srate = 8;
306 break;
307 default:
308 return -EINVAL;
309 }
310 return srate;
311}
312
313static inline int get_coeff(int mclk, int rate)
314{
315 int i;
316
317 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
318 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
319 return i;
320 }
321 return -EINVAL;
322}
323
324static int ml26124_hw_params(struct snd_pcm_substream *substream,
325 struct snd_pcm_hw_params *hw_params,
326 struct snd_soc_dai *dai)
327{
328 struct snd_soc_component *component = dai->component;
329 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
330 int i = get_coeff(priv->mclk, params_rate(hw_params));
331 int srate;
332
333 if (i < 0)
334 return i;
335 priv->substream = substream;
336 priv->rate = params_rate(hw_params);
337
338 if (priv->clk_in) {
339 switch (priv->mclk / params_rate(hw_params)) {
340 case 256:
341 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
342 BIT(0) | BIT(1), 1);
343 break;
344 case 512:
345 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
346 BIT(0) | BIT(1), 2);
347 break;
348 case 1024:
349 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
350 BIT(0) | BIT(1), 3);
351 break;
352 default:
353 dev_err(component->dev, "Unsupported MCLKI\n");
354 break;
355 }
356 } else {
357 snd_soc_component_update_bits(component, ML26124_CLK_CTL,
358 BIT(0) | BIT(1), 0);
359 }
360
361 srate = get_srate(params_rate(hw_params));
362 if (srate < 0)
363 return srate;
364
365 snd_soc_component_update_bits(component, ML26124_SMPLING_RATE, 0xf, srate);
366 snd_soc_component_update_bits(component, ML26124_PLLNL, 0xff, coeff_div[i].pllnl);
367 snd_soc_component_update_bits(component, ML26124_PLLNH, 0x1, coeff_div[i].pllnh);
368 snd_soc_component_update_bits(component, ML26124_PLLML, 0xff, coeff_div[i].pllml);
369 snd_soc_component_update_bits(component, ML26124_PLLMH, 0x3f, coeff_div[i].pllmh);
370 snd_soc_component_update_bits(component, ML26124_PLLDIV, 0x1f, coeff_div[i].plldiv);
371
372 return 0;
373}
374
375static int ml26124_mute(struct snd_soc_dai *dai, int mute, int direction)
376{
377 struct snd_soc_component *component = dai->component;
378 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
379
380 switch (priv->substream->stream) {
381 case SNDRV_PCM_STREAM_CAPTURE:
382 snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(0), 1);
383 break;
384 case SNDRV_PCM_STREAM_PLAYBACK:
385 snd_soc_component_update_bits(component, ML26124_REC_PLYBAK_RUN, BIT(1), 2);
386 break;
387 }
388
389 if (mute)
390 snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
391 DVOL_CTL_DVMUTE_ON);
392 else
393 snd_soc_component_update_bits(component, ML26124_DVOL_CTL, BIT(4),
394 DVOL_CTL_DVMUTE_OFF);
395
396 return 0;
397}
398
399static int ml26124_set_dai_fmt(struct snd_soc_dai *codec_dai,
400 unsigned int fmt)
401{
402 unsigned char mode;
403 struct snd_soc_component *component = codec_dai->component;
404
405 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
406 case SND_SOC_DAIFMT_CBP_CFP:
407 mode = 1;
408 break;
409 case SND_SOC_DAIFMT_CBC_CFC:
410 mode = 0;
411 break;
412 default:
413 return -EINVAL;
414 }
415 snd_soc_component_update_bits(component, ML26124_SAI_MODE_SEL, BIT(0), mode);
416
417 /* interface format */
418 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
419 case SND_SOC_DAIFMT_I2S:
420 break;
421 default:
422 return -EINVAL;
423 }
424
425 /* clock inversion */
426 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
427 case SND_SOC_DAIFMT_NB_NF:
428 break;
429 default:
430 return -EINVAL;
431 }
432
433 return 0;
434}
435
436static int ml26124_set_dai_sysclk(struct snd_soc_dai *codec_dai,
437 int clk_id, unsigned int freq, int dir)
438{
439 struct snd_soc_component *component = codec_dai->component;
440 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
441
442 switch (clk_id) {
443 case ML26124_USE_PLLOUT:
444 priv->clk_in = ML26124_USE_PLLOUT;
445 break;
446 case ML26124_USE_MCLKI:
447 priv->clk_in = ML26124_USE_MCLKI;
448 break;
449 default:
450 return -EINVAL;
451 }
452
453 priv->mclk = freq;
454
455 return 0;
456}
457
458static int ml26124_set_bias_level(struct snd_soc_component *component,
459 enum snd_soc_bias_level level)
460{
461 struct ml26124_priv *priv = snd_soc_component_get_drvdata(component);
462
463 switch (level) {
464 case SND_SOC_BIAS_ON:
465 snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
466 ML26124_R26_MASK, ML26124_BLT_PREAMP_ON);
467 msleep(100);
468 snd_soc_component_update_bits(component, ML26124_PW_SPAMP_PW_MNG,
469 ML26124_R26_MASK,
470 ML26124_MICBEN_ON | ML26124_BLT_ALL_ON);
471 break;
472 case SND_SOC_BIAS_PREPARE:
473 break;
474 case SND_SOC_BIAS_STANDBY:
475 /* VMID ON */
476 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
477 snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
478 ML26124_VMID, ML26124_VMID);
479 msleep(500);
480 regcache_sync(priv->regmap);
481 }
482 break;
483 case SND_SOC_BIAS_OFF:
484 /* VMID OFF */
485 snd_soc_component_update_bits(component, ML26124_PW_REF_PW_MNG,
486 ML26124_VMID, 0);
487 break;
488 }
489 return 0;
490}
491
492static const struct snd_soc_dai_ops ml26124_dai_ops = {
493 .hw_params = ml26124_hw_params,
494 .mute_stream = ml26124_mute,
495 .set_fmt = ml26124_set_dai_fmt,
496 .set_sysclk = ml26124_set_dai_sysclk,
497 .no_capture_mute = 1,
498};
499
500static struct snd_soc_dai_driver ml26124_dai = {
501 .name = "ml26124-hifi",
502 .playback = {
503 .stream_name = "Playback",
504 .channels_min = 1,
505 .channels_max = 2,
506 .rates = ML26124_RATES,
507 .formats = ML26124_FORMATS,},
508 .capture = {
509 .stream_name = "Capture",
510 .channels_min = 1,
511 .channels_max = 2,
512 .rates = ML26124_RATES,
513 .formats = ML26124_FORMATS,},
514 .ops = &ml26124_dai_ops,
515 .symmetric_rate = 1,
516};
517
518static int ml26124_probe(struct snd_soc_component *component)
519{
520 /* Software Reset */
521 snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 1);
522 snd_soc_component_update_bits(component, ML26124_SW_RST, 0x01, 0);
523
524 return 0;
525}
526
527static const struct snd_soc_component_driver soc_component_dev_ml26124 = {
528 .probe = ml26124_probe,
529 .set_bias_level = ml26124_set_bias_level,
530 .controls = ml26124_snd_controls,
531 .num_controls = ARRAY_SIZE(ml26124_snd_controls),
532 .dapm_widgets = ml26124_dapm_widgets,
533 .num_dapm_widgets = ARRAY_SIZE(ml26124_dapm_widgets),
534 .dapm_routes = ml26124_intercon,
535 .num_dapm_routes = ARRAY_SIZE(ml26124_intercon),
536 .suspend_bias_off = 1,
537 .idle_bias_on = 1,
538 .use_pmdown_time = 1,
539 .endianness = 1,
540};
541
542static const struct regmap_config ml26124_i2c_regmap = {
543 .val_bits = 8,
544 .reg_bits = 8,
545 .max_register = ML26124_NUM_REGISTER,
546 .reg_defaults = ml26124_reg,
547 .num_reg_defaults = ARRAY_SIZE(ml26124_reg),
548 .cache_type = REGCACHE_RBTREE,
549 .write_flag_mask = 0x01,
550};
551
552static int ml26124_i2c_probe(struct i2c_client *i2c)
553{
554 struct ml26124_priv *priv;
555 int ret;
556
557 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
558 if (!priv)
559 return -ENOMEM;
560
561 i2c_set_clientdata(i2c, priv);
562
563 priv->regmap = devm_regmap_init_i2c(i2c, &ml26124_i2c_regmap);
564 if (IS_ERR(priv->regmap)) {
565 ret = PTR_ERR(priv->regmap);
566 dev_err(&i2c->dev, "regmap_init_i2c() failed: %d\n", ret);
567 return ret;
568 }
569
570 return devm_snd_soc_register_component(&i2c->dev,
571 &soc_component_dev_ml26124, &ml26124_dai, 1);
572}
573
574static const struct i2c_device_id ml26124_i2c_id[] = {
575 { "ml26124" },
576 { }
577};
578MODULE_DEVICE_TABLE(i2c, ml26124_i2c_id);
579
580static struct i2c_driver ml26124_i2c_driver = {
581 .driver = {
582 .name = "ml26124",
583 },
584 .probe = ml26124_i2c_probe,
585 .id_table = ml26124_i2c_id,
586};
587
588module_i2c_driver(ml26124_i2c_driver);
589
590MODULE_AUTHOR("Tomoya MORINAGA <tomoya.rohm@gmail.com>");
591MODULE_DESCRIPTION("LAPIS Semiconductor ML26124 ALSA SoC codec driver");
592MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/pm.h>
23#include <linux/i2c.h>
24#include <linux/slab.h>
25#include <linux/platform_device.h>
26#include <linux/regmap.h>
27#include <sound/core.h>
28#include <sound/pcm.h>
29#include <sound/pcm_params.h>
30#include <sound/soc.h>
31#include <sound/tlv.h>
32#include "ml26124.h"
33
34#define DVOL_CTL_DVMUTE_ON BIT(4) /* Digital volume MUTE On */
35#define DVOL_CTL_DVMUTE_OFF 0 /* Digital volume MUTE Off */
36#define ML26124_SAI_NO_DELAY BIT(1)
37#define ML26124_SAI_FRAME_SYNC (BIT(5) | BIT(0)) /* For mono (Telecodec) */
38#define ML26134_CACHESIZE 212
39#define ML26124_VMID BIT(1)
40#define ML26124_RATES (SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_32000 |\
41 SNDRV_PCM_RATE_48000)
42#define ML26124_FORMATS (SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE |\
43 SNDRV_PCM_FMTBIT_S32_LE)
44#define ML26124_NUM_REGISTER ML26134_CACHESIZE
45
46struct ml26124_priv {
47 u32 mclk;
48 u32 rate;
49 struct regmap *regmap;
50 int clk_in;
51 struct snd_pcm_substream *substream;
52};
53
54struct clk_coeff {
55 u32 mclk;
56 u32 rate;
57 u8 pllnl;
58 u8 pllnh;
59 u8 pllml;
60 u8 pllmh;
61 u8 plldiv;
62};
63
64/* ML26124 configuration */
65static const DECLARE_TLV_DB_SCALE(digital_tlv, -7150, 50, 0);
66
67static const DECLARE_TLV_DB_SCALE(alclvl, -2250, 150, 0);
68static const DECLARE_TLV_DB_SCALE(mingain, -1200, 600, 0);
69static const DECLARE_TLV_DB_SCALE(maxgain, -675, 600, 0);
70static const DECLARE_TLV_DB_SCALE(boost_vol, -1200, 75, 0);
71static const DECLARE_TLV_DB_SCALE(ngth, -7650, 150, 0);
72
73static const char * const ml26124_companding[] = {"16bit PCM", "u-law",
74 "A-law"};
75
76static SOC_ENUM_SINGLE_DECL(ml26124_adc_companding_enum,
77 ML26124_SAI_TRANS_CTL, 6, ml26124_companding);
78
79static SOC_ENUM_SINGLE_DECL(ml26124_dac_companding_enum,
80 ML26124_SAI_RCV_CTL, 6, ml26124_companding);
81
82static const struct snd_kcontrol_new ml26124_snd_controls[] = {
83 SOC_SINGLE_TLV("Capture Digital Volume", ML26124_RECORD_DIG_VOL, 0,
84 0xff, 1, digital_tlv),
85 SOC_SINGLE_TLV("Playback Digital Volume", ML26124_PLBAK_DIG_VOL, 0,
86 0xff, 1, digital_tlv),
87 SOC_SINGLE_TLV("Digital Boost Volume", ML26124_DIGI_BOOST_VOL, 0,
88 0x3f, 0, boost_vol),
89 SOC_SINGLE_TLV("EQ Band0 Volume", ML26124_EQ_GAIN_BRAND0, 0,
90 0xff, 1, digital_tlv),
91 SOC_SINGLE_TLV("EQ Band1 Volume", ML26124_EQ_GAIN_BRAND1, 0,
92 0xff, 1, digital_tlv),
93 SOC_SINGLE_TLV("EQ Band2 Volume", ML26124_EQ_GAIN_BRAND2, 0,
94 0xff, 1, digital_tlv),
95 SOC_SINGLE_TLV("EQ Band3 Volume", ML26124_EQ_GAIN_BRAND3, 0,
96 0xff, 1, digital_tlv),
97 SOC_SINGLE_TLV("EQ Band4 Volume", ML26124_EQ_GAIN_BRAND4, 0,
98 0xff, 1, digital_tlv),
99 SOC_SINGLE_TLV("ALC Target Level", ML26124_ALC_TARGET_LEV, 0,
100 0xf, 1, alclvl),
101 SOC_SINGLE_TLV("ALC Min Input Volume", ML26124_ALC_MAXMIN_GAIN, 0,
102 7, 0, mingain),
103 SOC_SINGLE_TLV("ALC Max Input Volume", ML26124_ALC_MAXMIN_GAIN, 4,
104 7, 1, maxgain),
105 SOC_SINGLE_TLV("Playback Limiter Min Input Volume",
106 ML26124_PL_MAXMIN_GAIN, 0, 7, 0, mingain),
107 SOC_SINGLE_TLV("Playback Limiter Max Input Volume",
108 ML26124_PL_MAXMIN_GAIN, 4, 7, 1, maxgain),
109 SOC_SINGLE_TLV("Playback Boost Volume", ML26124_PLYBAK_BOST_VOL, 0,
110 0x3f, 0, boost_vol),
111 SOC_SINGLE("DC High Pass Filter Switch", ML26124_FILTER_EN, 0, 1, 0),
112 SOC_SINGLE("Noise High Pass Filter Switch", ML26124_FILTER_EN, 1, 1, 0),
113 SOC_SINGLE("ZC Switch", ML26124_PW_ZCCMP_PW_MNG, 1,
114 1, 0),
115 SOC_SINGLE("EQ Band0 Switch", ML26124_FILTER_EN, 2, 1, 0),
116 SOC_SINGLE("EQ Band1 Switch", ML26124_FILTER_EN, 3, 1, 0),
117 SOC_SINGLE("EQ Band2 Switch", ML26124_FILTER_EN, 4, 1, 0),
118 SOC_SINGLE("EQ Band3 Switch", ML26124_FILTER_EN, 5, 1, 0),
119 SOC_SINGLE("EQ Band4 Switch", ML26124_FILTER_EN, 6, 1, 0),
120 SOC_SINGLE("Play Limiter", ML26124_DVOL_CTL, 0, 1, 0),
121 SOC_SINGLE("Capture Limiter", ML26124_DVOL_CTL, 1, 1, 0),
122 SOC_SINGLE("Digital Volume Fade Switch", ML26124_DVOL_CTL, 3, 1, 0),
123 SOC_SINGLE("Digital Switch", ML26124_DVOL_CTL, 4, 1, 0),
124 SOC_ENUM("DAC Companding", ml26124_dac_companding_enum),
125 SOC_ENUM("ADC Companding", ml26124_adc_companding_enum),
126};
127
128static const struct snd_kcontrol_new ml26124_output_mixer_controls[] = {
129 SOC_DAPM_SINGLE("DAC Switch", ML26124_SPK_AMP_OUT, 1, 1, 0),
130 SOC_DAPM_SINGLE("Line in loopback Switch", ML26124_SPK_AMP_OUT, 3, 1,
131 0),
132 SOC_DAPM_SINGLE("PGA Switch", ML26124_SPK_AMP_OUT, 5, 1, 0),
133};
134
135/* Input mux */
136static const char * const ml26124_input_select[] = {"Analog MIC SingleEnded in",
137 "Digital MIC in", "Analog MIC Differential in"};
138
139static SOC_ENUM_SINGLE_DECL(ml26124_insel_enum,
140 ML26124_MIC_IF_CTL, 0, ml26124_input_select);
141
142static const struct snd_kcontrol_new ml26124_input_mux_controls =
143 SOC_DAPM_ENUM("Input Select", ml26124_insel_enum);
144
145static const struct snd_kcontrol_new ml26124_line_control =
146 SOC_DAPM_SINGLE("Switch", ML26124_PW_LOUT_PW_MNG, 1, 1, 0);
147
148static const struct snd_soc_dapm_widget ml26124_dapm_widgets[] = {
149 SND_SOC_DAPM_SUPPLY("MCLKEN", ML26124_CLK_EN, 0, 0, NULL, 0),
150 SND_SOC_DAPM_SUPPLY("PLLEN", ML26124_CLK_EN, 1, 0, NULL, 0),
151 SND_SOC_DAPM_SUPPLY("PLLOE", ML26124_CLK_EN, 2, 0, NULL, 0),
152 SND_SOC_DAPM_SUPPLY("MICBIAS", ML26124_PW_REF_PW_MNG, 2, 0, NULL, 0),
153 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
154 &ml26124_output_mixer_controls[0],
155 ARRAY_SIZE(ml26124_output_mixer_controls)),
156 SND_SOC_DAPM_DAC("DAC", "Playback", ML26124_PW_DAC_PW_MNG, 1, 0),
157 SND_SOC_DAPM_ADC("ADC", "Capture", ML26124_PW_IN_PW_MNG, 1, 0),
158 SND_SOC_DAPM_PGA("PGA", ML26124_PW_IN_PW_MNG, 3, 0, NULL, 0),
159 SND_SOC_DAPM_MUX("Input Mux", SND_SOC_NOPM, 0, 0,
160 &ml26124_input_mux_controls),
161 SND_SOC_DAPM_SWITCH("Line Out Enable", SND_SOC_NOPM, 0, 0,
162 &ml26124_line_control),
163 SND_SOC_DAPM_INPUT("MDIN"),
164 SND_SOC_DAPM_INPUT("MIN"),
165 SND_SOC_DAPM_INPUT("LIN"),
166 SND_SOC_DAPM_OUTPUT("SPOUT"),
167 SND_SOC_DAPM_OUTPUT("LOUT"),
168};
169
170static const struct snd_soc_dapm_route ml26124_intercon[] = {
171 /* Supply */
172 {"DAC", NULL, "MCLKEN"},
173 {"ADC", NULL, "MCLKEN"},
174 {"DAC", NULL, "PLLEN"},
175 {"ADC", NULL, "PLLEN"},
176 {"DAC", NULL, "PLLOE"},
177 {"ADC", NULL, "PLLOE"},
178
179 /* output mixer */
180 {"Output Mixer", "DAC Switch", "DAC"},
181 {"Output Mixer", "Line in loopback Switch", "LIN"},
182
183 /* outputs */
184 {"LOUT", NULL, "Output Mixer"},
185 {"SPOUT", NULL, "Output Mixer"},
186 {"Line Out Enable", NULL, "LOUT"},
187
188 /* input */
189 {"ADC", NULL, "Input Mux"},
190 {"Input Mux", "Analog MIC SingleEnded in", "PGA"},
191 {"Input Mux", "Analog MIC Differential in", "PGA"},
192 {"PGA", NULL, "MIN"},
193};
194
195/* PLLOutputFreq(Hz) = InputMclkFreq(Hz) * PLLM / (PLLN * PLLDIV) */
196static const struct clk_coeff coeff_div[] = {
197 {12288000, 16000, 0xc, 0x0, 0x20, 0x0, 0x4},
198 {12288000, 32000, 0xc, 0x0, 0x20, 0x0, 0x4},
199 {12288000, 48000, 0xc, 0x0, 0x30, 0x0, 0x4},
200};
201
202static const struct reg_default ml26124_reg[] = {
203 /* CLOCK control Register */
204 {0x00, 0x00 }, /* Sampling Rate */
205 {0x02, 0x00}, /* PLL NL */
206 {0x04, 0x00}, /* PLLNH */
207 {0x06, 0x00}, /* PLLML */
208 {0x08, 0x00}, /* MLLMH */
209 {0x0a, 0x00}, /* PLLDIV */
210 {0x0c, 0x00}, /* Clock Enable */
211 {0x0e, 0x00}, /* CLK Input/Output Control */
212
213 /* System Control Register */
214 {0x10, 0x00}, /* Software RESET */
215 {0x12, 0x00}, /* Record/Playback Run */
216 {0x14, 0x00}, /* Mic Input/Output control */
217
218 /* Power Management Register */
219 {0x20, 0x00}, /* Reference Power Management */
220 {0x22, 0x00}, /* Input Power Management */
221 {0x24, 0x00}, /* DAC Power Management */
222 {0x26, 0x00}, /* SP-AMP Power Management */
223 {0x28, 0x00}, /* LINEOUT Power Management */
224 {0x2a, 0x00}, /* VIDEO Power Management */
225 {0x2e, 0x00}, /* AC-CMP Power Management */
226
227 /* Analog reference Control Register */
228 {0x30, 0x04}, /* MICBIAS Voltage Control */
229
230 /* Input/Output Amplifier Control Register */
231 {0x32, 0x10}, /* MIC Input Volume */
232 {0x38, 0x00}, /* Mic Boost Volume */
233 {0x3a, 0x33}, /* Speaker AMP Volume */
234 {0x48, 0x00}, /* AMP Volume Control Function Enable */
235 {0x4a, 0x00}, /* Amplifier Volume Fader Control */
236
237 /* Analog Path Control Register */
238 {0x54, 0x00}, /* Speaker AMP Output Control */
239 {0x5a, 0x00}, /* Mic IF Control */
240 {0xe8, 0x01}, /* Mic Select Control */
241
242 /* Audio Interface Control Register */
243 {0x60, 0x00}, /* SAI-Trans Control */
244 {0x62, 0x00}, /* SAI-Receive Control */
245 {0x64, 0x00}, /* SAI Mode select */
246
247 /* DSP Control Register */
248 {0x66, 0x01}, /* Filter Func Enable */
249 {0x68, 0x00}, /* Volume Control Func Enable */
250 {0x6A, 0x00}, /* Mixer & Volume Control*/
251 {0x6C, 0xff}, /* Record Digital Volume */
252 {0x70, 0xff}, /* Playback Digital Volume */
253 {0x72, 0x10}, /* Digital Boost Volume */
254 {0x74, 0xe7}, /* EQ gain Band0 */
255 {0x76, 0xe7}, /* EQ gain Band1 */
256 {0x78, 0xe7}, /* EQ gain Band2 */
257 {0x7A, 0xe7}, /* EQ gain Band3 */
258 {0x7C, 0xe7}, /* EQ gain Band4 */
259 {0x7E, 0x00}, /* HPF2 CutOff*/
260 {0x80, 0x00}, /* EQ Band0 Coef0L */
261 {0x82, 0x00}, /* EQ Band0 Coef0H */
262 {0x84, 0x00}, /* EQ Band0 Coef0L */
263 {0x86, 0x00}, /* EQ Band0 Coef0H */
264 {0x88, 0x00}, /* EQ Band1 Coef0L */
265 {0x8A, 0x00}, /* EQ Band1 Coef0H */
266 {0x8C, 0x00}, /* EQ Band1 Coef0L */
267 {0x8E, 0x00}, /* EQ Band1 Coef0H */
268 {0x90, 0x00}, /* EQ Band2 Coef0L */
269 {0x92, 0x00}, /* EQ Band2 Coef0H */
270 {0x94, 0x00}, /* EQ Band2 Coef0L */
271 {0x96, 0x00}, /* EQ Band2 Coef0H */
272 {0x98, 0x00}, /* EQ Band3 Coef0L */
273 {0x9A, 0x00}, /* EQ Band3 Coef0H */
274 {0x9C, 0x00}, /* EQ Band3 Coef0L */
275 {0x9E, 0x00}, /* EQ Band3 Coef0H */
276 {0xA0, 0x00}, /* EQ Band4 Coef0L */
277 {0xA2, 0x00}, /* EQ Band4 Coef0H */
278 {0xA4, 0x00}, /* EQ Band4 Coef0L */
279 {0xA6, 0x00}, /* EQ Band4 Coef0H */
280
281 /* ALC Control Register */
282 {0xb0, 0x00}, /* ALC Mode */
283 {0xb2, 0x02}, /* ALC Attack Time */
284 {0xb4, 0x03}, /* ALC Decay Time */
285 {0xb6, 0x00}, /* ALC Hold Time */
286 {0xb8, 0x0b}, /* ALC Target Level */
287 {0xba, 0x70}, /* ALC Max/Min Gain */
288 {0xbc, 0x00}, /* Noise Gate Threshold */
289 {0xbe, 0x00}, /* ALC ZeroCross TimeOut */
290
291 /* Playback Limiter Control Register */
292 {0xc0, 0x04}, /* PL Attack Time */
293 {0xc2, 0x05}, /* PL Decay Time */
294 {0xc4, 0x0d}, /* PL Target Level */
295 {0xc6, 0x70}, /* PL Max/Min Gain */
296 {0xc8, 0x10}, /* Playback Boost Volume */
297 {0xca, 0x00}, /* PL ZeroCross TimeOut */
298
299 /* Video Amplifier Control Register */
300 {0xd0, 0x01}, /* VIDEO AMP Gain Control */
301 {0xd2, 0x01}, /* VIDEO AMP Setup 1 */
302 {0xd4, 0x01}, /* VIDEO AMP Control2 */
303};
304
305/* Get sampling rate value of sampling rate setting register (0x0) */
306static inline int get_srate(int rate)
307{
308 int srate;
309
310 switch (rate) {
311 case 16000:
312 srate = 3;
313 break;
314 case 32000:
315 srate = 6;
316 break;
317 case 48000:
318 srate = 8;
319 break;
320 default:
321 return -EINVAL;
322 }
323 return srate;
324}
325
326static inline int get_coeff(int mclk, int rate)
327{
328 int i;
329
330 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
331 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
332 return i;
333 }
334 return -EINVAL;
335}
336
337static int ml26124_hw_params(struct snd_pcm_substream *substream,
338 struct snd_pcm_hw_params *hw_params,
339 struct snd_soc_dai *dai)
340{
341 struct snd_soc_codec *codec = dai->codec;
342 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
343 int i = get_coeff(priv->mclk, params_rate(hw_params));
344 int srate;
345
346 if (i < 0)
347 return i;
348 priv->substream = substream;
349 priv->rate = params_rate(hw_params);
350
351 if (priv->clk_in) {
352 switch (priv->mclk / params_rate(hw_params)) {
353 case 256:
354 snd_soc_update_bits(codec, ML26124_CLK_CTL,
355 BIT(0) | BIT(1), 1);
356 break;
357 case 512:
358 snd_soc_update_bits(codec, ML26124_CLK_CTL,
359 BIT(0) | BIT(1), 2);
360 break;
361 case 1024:
362 snd_soc_update_bits(codec, ML26124_CLK_CTL,
363 BIT(0) | BIT(1), 3);
364 break;
365 default:
366 dev_err(codec->dev, "Unsupported MCLKI\n");
367 break;
368 }
369 } else {
370 snd_soc_update_bits(codec, ML26124_CLK_CTL,
371 BIT(0) | BIT(1), 0);
372 }
373
374 srate = get_srate(params_rate(hw_params));
375 if (srate < 0)
376 return srate;
377
378 snd_soc_update_bits(codec, ML26124_SMPLING_RATE, 0xf, srate);
379 snd_soc_update_bits(codec, ML26124_PLLNL, 0xff, coeff_div[i].pllnl);
380 snd_soc_update_bits(codec, ML26124_PLLNH, 0x1, coeff_div[i].pllnh);
381 snd_soc_update_bits(codec, ML26124_PLLML, 0xff, coeff_div[i].pllml);
382 snd_soc_update_bits(codec, ML26124_PLLMH, 0x3f, coeff_div[i].pllmh);
383 snd_soc_update_bits(codec, ML26124_PLLDIV, 0x1f, coeff_div[i].plldiv);
384
385 return 0;
386}
387
388static int ml26124_mute(struct snd_soc_dai *dai, int mute)
389{
390 struct snd_soc_codec *codec = dai->codec;
391 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
392
393 switch (priv->substream->stream) {
394 case SNDRV_PCM_STREAM_CAPTURE:
395 snd_soc_update_bits(codec, ML26124_REC_PLYBAK_RUN, BIT(0), 1);
396 break;
397 case SNDRV_PCM_STREAM_PLAYBACK:
398 snd_soc_update_bits(codec, ML26124_REC_PLYBAK_RUN, BIT(1), 2);
399 break;
400 }
401
402 if (mute)
403 snd_soc_update_bits(codec, ML26124_DVOL_CTL, BIT(4),
404 DVOL_CTL_DVMUTE_ON);
405 else
406 snd_soc_update_bits(codec, ML26124_DVOL_CTL, BIT(4),
407 DVOL_CTL_DVMUTE_OFF);
408
409 return 0;
410}
411
412static int ml26124_set_dai_fmt(struct snd_soc_dai *codec_dai,
413 unsigned int fmt)
414{
415 unsigned char mode;
416 struct snd_soc_codec *codec = codec_dai->codec;
417
418 /* set master/slave audio interface */
419 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
420 case SND_SOC_DAIFMT_CBM_CFM:
421 mode = 1;
422 break;
423 case SND_SOC_DAIFMT_CBS_CFS:
424 mode = 0;
425 break;
426 default:
427 return -EINVAL;
428 }
429 snd_soc_update_bits(codec, ML26124_SAI_MODE_SEL, BIT(0), mode);
430
431 /* interface format */
432 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
433 case SND_SOC_DAIFMT_I2S:
434 break;
435 default:
436 return -EINVAL;
437 }
438
439 /* clock inversion */
440 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
441 case SND_SOC_DAIFMT_NB_NF:
442 break;
443 default:
444 return -EINVAL;
445 }
446
447 return 0;
448}
449
450static int ml26124_set_dai_sysclk(struct snd_soc_dai *codec_dai,
451 int clk_id, unsigned int freq, int dir)
452{
453 struct snd_soc_codec *codec = codec_dai->codec;
454 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
455
456 switch (clk_id) {
457 case ML26124_USE_PLLOUT:
458 priv->clk_in = ML26124_USE_PLLOUT;
459 break;
460 case ML26124_USE_MCLKI:
461 priv->clk_in = ML26124_USE_MCLKI;
462 break;
463 default:
464 return -EINVAL;
465 }
466
467 priv->mclk = freq;
468
469 return 0;
470}
471
472static int ml26124_set_bias_level(struct snd_soc_codec *codec,
473 enum snd_soc_bias_level level)
474{
475 struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec);
476
477 switch (level) {
478 case SND_SOC_BIAS_ON:
479 snd_soc_update_bits(codec, ML26124_PW_SPAMP_PW_MNG,
480 ML26124_R26_MASK, ML26124_BLT_PREAMP_ON);
481 msleep(100);
482 snd_soc_update_bits(codec, ML26124_PW_SPAMP_PW_MNG,
483 ML26124_R26_MASK,
484 ML26124_MICBEN_ON | ML26124_BLT_ALL_ON);
485 break;
486 case SND_SOC_BIAS_PREPARE:
487 break;
488 case SND_SOC_BIAS_STANDBY:
489 /* VMID ON */
490 if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
491 snd_soc_update_bits(codec, ML26124_PW_REF_PW_MNG,
492 ML26124_VMID, ML26124_VMID);
493 msleep(500);
494 regcache_sync(priv->regmap);
495 }
496 break;
497 case SND_SOC_BIAS_OFF:
498 /* VMID OFF */
499 snd_soc_update_bits(codec, ML26124_PW_REF_PW_MNG,
500 ML26124_VMID, 0);
501 break;
502 }
503 return 0;
504}
505
506static const struct snd_soc_dai_ops ml26124_dai_ops = {
507 .hw_params = ml26124_hw_params,
508 .digital_mute = ml26124_mute,
509 .set_fmt = ml26124_set_dai_fmt,
510 .set_sysclk = ml26124_set_dai_sysclk,
511};
512
513static struct snd_soc_dai_driver ml26124_dai = {
514 .name = "ml26124-hifi",
515 .playback = {
516 .stream_name = "Playback",
517 .channels_min = 1,
518 .channels_max = 2,
519 .rates = ML26124_RATES,
520 .formats = ML26124_FORMATS,},
521 .capture = {
522 .stream_name = "Capture",
523 .channels_min = 1,
524 .channels_max = 2,
525 .rates = ML26124_RATES,
526 .formats = ML26124_FORMATS,},
527 .ops = &ml26124_dai_ops,
528 .symmetric_rates = 1,
529};
530
531static int ml26124_probe(struct snd_soc_codec *codec)
532{
533 /* Software Reset */
534 snd_soc_update_bits(codec, ML26124_SW_RST, 0x01, 1);
535 snd_soc_update_bits(codec, ML26124_SW_RST, 0x01, 0);
536
537 return 0;
538}
539
540static struct snd_soc_codec_driver soc_codec_dev_ml26124 = {
541 .probe = ml26124_probe,
542 .set_bias_level = ml26124_set_bias_level,
543 .suspend_bias_off = true,
544 .component_driver = {
545 .controls = ml26124_snd_controls,
546 .num_controls = ARRAY_SIZE(ml26124_snd_controls),
547 .dapm_widgets = ml26124_dapm_widgets,
548 .num_dapm_widgets = ARRAY_SIZE(ml26124_dapm_widgets),
549 .dapm_routes = ml26124_intercon,
550 .num_dapm_routes = ARRAY_SIZE(ml26124_intercon),
551 },
552};
553
554static const struct regmap_config ml26124_i2c_regmap = {
555 .val_bits = 8,
556 .reg_bits = 8,
557 .max_register = ML26124_NUM_REGISTER,
558 .reg_defaults = ml26124_reg,
559 .num_reg_defaults = ARRAY_SIZE(ml26124_reg),
560 .cache_type = REGCACHE_RBTREE,
561 .write_flag_mask = 0x01,
562};
563
564static int ml26124_i2c_probe(struct i2c_client *i2c,
565 const struct i2c_device_id *id)
566{
567 struct ml26124_priv *priv;
568 int ret;
569
570 priv = devm_kzalloc(&i2c->dev, sizeof(*priv), GFP_KERNEL);
571 if (!priv)
572 return -ENOMEM;
573
574 i2c_set_clientdata(i2c, priv);
575
576 priv->regmap = devm_regmap_init_i2c(i2c, &ml26124_i2c_regmap);
577 if (IS_ERR(priv->regmap)) {
578 ret = PTR_ERR(priv->regmap);
579 dev_err(&i2c->dev, "regmap_init_i2c() failed: %d\n", ret);
580 return ret;
581 }
582
583 return snd_soc_register_codec(&i2c->dev,
584 &soc_codec_dev_ml26124, &ml26124_dai, 1);
585}
586
587static int ml26124_i2c_remove(struct i2c_client *client)
588{
589 snd_soc_unregister_codec(&client->dev);
590 return 0;
591}
592
593static const struct i2c_device_id ml26124_i2c_id[] = {
594 { "ml26124", 0 },
595 { }
596};
597MODULE_DEVICE_TABLE(i2c, ml26124_i2c_id);
598
599static struct i2c_driver ml26124_i2c_driver = {
600 .driver = {
601 .name = "ml26124",
602 },
603 .probe = ml26124_i2c_probe,
604 .remove = ml26124_i2c_remove,
605 .id_table = ml26124_i2c_id,
606};
607
608module_i2c_driver(ml26124_i2c_driver);
609
610MODULE_AUTHOR("Tomoya MORINAGA <tomoya.rohm@gmail.com>");
611MODULE_DESCRIPTION("LAPIS Semiconductor ML26124 ALSA SoC codec driver");
612MODULE_LICENSE("GPL");