1/* SPDX-License-Identifier: GPL-2.0-or-later */
  2/*
  3 * max98927.h  --  MAX98927 ALSA Soc Audio driver
  4 *
  5 * Copyright (C) 2016-2017 Maxim Integrated Products
  6 * Author: Ryan Lee <ryans.lee@maximintegrated.com>
  7 */
  8#ifndef _MAX98927_H
  9#define _MAX98927_H
 10
 11/* Register Values */
 12#define MAX98927_R0001_INT_RAW1 0x0001
 13#define MAX98927_R0002_INT_RAW2 0x0002
 14#define MAX98927_R0003_INT_RAW3 0x0003
 15#define MAX98927_R0004_INT_STATE1 0x0004
 16#define MAX98927_R0005_INT_STATE2 0x0005
 17#define MAX98927_R0006_INT_STATE3 0x0006
 18#define MAX98927_R0007_INT_FLAG1 0x0007
 19#define MAX98927_R0008_INT_FLAG2 0x0008
 20#define MAX98927_R0009_INT_FLAG3 0x0009
 21#define MAX98927_R000A_INT_EN1 0x000A
 22#define MAX98927_R000B_INT_EN2 0x000B
 23#define MAX98927_R000C_INT_EN3 0x000C
 24#define MAX98927_R000D_INT_FLAG_CLR1	0x000D
 25#define MAX98927_R000E_INT_FLAG_CLR2	0x000E
 26#define MAX98927_R000F_INT_FLAG_CLR3	0x000F
 27#define MAX98927_R0010_IRQ_CTRL 0x0010
 28#define MAX98927_R0011_CLK_MON 0x0011
 29#define MAX98927_R0012_WDOG_CTRL 0x0012
 30#define MAX98927_R0013_WDOG_RST 0x0013
 31#define MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH 0x0014
 32#define MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH 0x0015
 33#define MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS 0x0016
 34#define MAX98927_R0017_PIN_CFG 0x0017
 35#define MAX98927_R0018_PCM_RX_EN_A 0x0018
 36#define MAX98927_R0019_PCM_RX_EN_B 0x0019
 37#define MAX98927_R001A_PCM_TX_EN_A 0x001A
 38#define MAX98927_R001B_PCM_TX_EN_B 0x001B
 39#define MAX98927_R001C_PCM_TX_HIZ_CTRL_A 0x001C
 40#define MAX98927_R001D_PCM_TX_HIZ_CTRL_B 0x001D
 41#define MAX98927_R001E_PCM_TX_CH_SRC_A 0x001E
 42#define MAX98927_R001F_PCM_TX_CH_SRC_B 0x001F
 43#define MAX98927_R0020_PCM_MODE_CFG 0x0020
 44#define MAX98927_R0021_PCM_MASTER_MODE 0x0021
 45#define MAX98927_R0022_PCM_CLK_SETUP 0x0022
 46#define MAX98927_R0023_PCM_SR_SETUP1 0x0023
 47#define MAX98927_R0024_PCM_SR_SETUP2	0x0024
 48#define MAX98927_R0025_PCM_TO_SPK_MONOMIX_A 0x0025
 49#define MAX98927_R0026_PCM_TO_SPK_MONOMIX_B 0x0026
 50#define MAX98927_R0027_ICC_RX_EN_A 0x0027
 51#define MAX98927_R0028_ICC_RX_EN_B 0x0028
 52#define MAX98927_R002B_ICC_TX_EN_A 0x002B
 53#define MAX98927_R002C_ICC_TX_EN_B 0x002C
 54#define MAX98927_R002E_ICC_HIZ_MANUAL_MODE 0x002E
 55#define MAX98927_R002F_ICC_TX_HIZ_EN_A 0x002F
 56#define MAX98927_R0030_ICC_TX_HIZ_EN_B 0x0030
 57#define MAX98927_R0031_ICC_LNK_EN 0x0031
 58#define MAX98927_R0032_PDM_TX_EN 0x0032
 59#define MAX98927_R0033_PDM_TX_HIZ_CTRL 0x0033
 60#define MAX98927_R0034_PDM_TX_CTRL 0x0034
 61#define MAX98927_R0035_PDM_RX_CTRL 0x0035
 62#define MAX98927_R0036_AMP_VOL_CTRL 0x0036
 63#define MAX98927_R0037_AMP_DSP_CFG 0x0037
 64#define MAX98927_R0038_TONE_GEN_DC_CFG 0x0038
 65#define MAX98927_R0039_DRE_CTRL 0x0039
 66#define MAX98927_R003A_AMP_EN 0x003A
 67#define MAX98927_R003B_SPK_SRC_SEL 0x003B
 68#define MAX98927_R003C_SPK_GAIN 0x003C
 69#define MAX98927_R003D_SSM_CFG 0x003D
 70#define MAX98927_R003E_MEAS_EN 0x003E
 71#define MAX98927_R003F_MEAS_DSP_CFG 0x003F
 72#define MAX98927_R0040_BOOST_CTRL0 0x0040
 73#define MAX98927_R0041_BOOST_CTRL3 0x0041
 74#define MAX98927_R0042_BOOST_CTRL1 0x0042
 75#define MAX98927_R0043_MEAS_ADC_CFG 0x0043
 76#define MAX98927_R0044_MEAS_ADC_BASE_MSB 0x0044
 77#define MAX98927_R0045_MEAS_ADC_BASE_LSB 0x0045
 78#define MAX98927_R0046_ADC_CH0_DIVIDE 0x0046
 79#define MAX98927_R0047_ADC_CH1_DIVIDE 0x0047
 80#define MAX98927_R0048_ADC_CH2_DIVIDE 0x0048
 81#define MAX98927_R0049_ADC_CH0_FILT_CFG 0x0049
 82#define MAX98927_R004A_ADC_CH1_FILT_CFG 0x004A
 83#define MAX98927_R004B_ADC_CH2_FILT_CFG 0x004B
 84#define MAX98927_R004C_MEAS_ADC_CH0_READ 0x004C
 85#define MAX98927_R004D_MEAS_ADC_CH1_READ 0x004D
 86#define MAX98927_R004E_MEAS_ADC_CH2_READ 0x004E
 87#define MAX98927_R0051_BROWNOUT_STATUS 0x0051
 88#define MAX98927_R0052_BROWNOUT_EN 0x0052
 89#define MAX98927_R0053_BROWNOUT_INFINITE_HOLD 0x0053
 90#define MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR 0x0054
 91#define MAX98927_R0055_BROWNOUT_LVL_HOLD 0x0055
 92#define MAX98927_R005A_BROWNOUT_LVL1_THRESH 0x005A
 93#define MAX98927_R005B_BROWNOUT_LVL2_THRESH 0x005B
 94#define MAX98927_R005C_BROWNOUT_LVL3_THRESH 0x005C
 95#define MAX98927_R005D_BROWNOUT_LVL4_THRESH 0x005D
 96#define MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS 0x005E
 97#define MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL 0x005F
 98#define MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL 0x0060
 99#define MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE 0x0061
100#define MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT 0x0072
101#define MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1 0x0073
102#define MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2 0x0074
103#define MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3 0x0075
104#define MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT 0x0076
105#define MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1 0x0077
106#define MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2 0x0078
107#define MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3 0x0079
108#define MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT 0x007A
109#define MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1 0x007B
110#define MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2 0x007C
111#define MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3 0x007D
112#define MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT 0x007E
113#define MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1 0x007F
114#define MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2 0x0080
115#define MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3 0x0081
116#define MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM 0x0082
117#define MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY 0x0083
118#define MAX98927_R0084_ENV_TRACK_REL_RATE 0x0084
119#define MAX98927_R0085_ENV_TRACK_HOLD_RATE 0x0085
120#define MAX98927_R0086_ENV_TRACK_CTRL 0x0086
121#define MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ 0x0087
122#define MAX98927_R00FF_GLOBAL_SHDN 0x00FF
123#define MAX98927_R0100_SOFT_RESET 0x0100
124#define MAX98927_R01FF_REV_ID 0x01FF
125
126/* MAX98927_R0018_PCM_RX_EN_A */
127#define MAX98927_PCM_RX_CH0_EN (0x1 << 0)
128#define MAX98927_PCM_RX_CH1_EN (0x1 << 1)
129#define MAX98927_PCM_RX_CH2_EN (0x1 << 2)
130#define MAX98927_PCM_RX_CH3_EN (0x1 << 3)
131#define MAX98927_PCM_RX_CH4_EN (0x1 << 4)
132#define MAX98927_PCM_RX_CH5_EN (0x1 << 5)
133#define MAX98927_PCM_RX_CH6_EN (0x1 << 6)
134#define MAX98927_PCM_RX_CH7_EN (0x1 << 7)
135
136/* MAX98927_R001A_PCM_TX_EN_A */
137#define MAX98927_PCM_TX_CH0_EN (0x1 << 0)
138#define MAX98927_PCM_TX_CH1_EN (0x1 << 1)
139#define MAX98927_PCM_TX_CH2_EN (0x1 << 2)
140#define MAX98927_PCM_TX_CH3_EN (0x1 << 3)
141#define MAX98927_PCM_TX_CH4_EN (0x1 << 4)
142#define MAX98927_PCM_TX_CH5_EN (0x1 << 5)
143#define MAX98927_PCM_TX_CH6_EN (0x1 << 6)
144#define MAX98927_PCM_TX_CH7_EN (0x1 << 7)
145
146/* MAX98927_R001E_PCM_TX_CH_SRC_A */
147#define MAX98927_PCM_TX_CH_SRC_A_V_SHIFT (0)
148#define MAX98927_PCM_TX_CH_SRC_A_I_SHIFT (4)
149
150/* MAX98927_R001F_PCM_TX_CH_SRC_B */
151#define MAX98927_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 5)
152
153/* MAX98927_R0020_PCM_MODE_CFG */
154#define MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 2)
155#define MAX98927_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
156#define MAX98927_PCM_MODE_CFG_FORMAT_SHIFT (3)
157#define MAX98927_PCM_FORMAT_I2S (0x0 << 0)
158#define MAX98927_PCM_FORMAT_LJ (0x1 << 0)
159#define MAX98927_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
160#define MAX98927_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
161#define MAX98927_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
162#define MAX98927_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
163#define MAX98927_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
164#define MAX98927_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
165#define MAX98927_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
166
167/* MAX98927_R0021_PCM_MASTER_MODE */
168#define MAX98927_PCM_MASTER_MODE_MASK (0x3 << 0)
169#define MAX98927_PCM_MASTER_MODE_SLAVE (0x0 << 0)
170#define MAX98927_PCM_MASTER_MODE_MASTER (0x3 << 0)
171
172#define MAX98927_PCM_MASTER_MODE_MCLK_MASK (0xF << 2)
173#define MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT (2)
174
175/* MAX98927_R0022_PCM_CLK_SETUP */
176#define MAX98927_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
177
178/* MAX98927_R0023_PCM_SR_SETUP1 */
179#define MAX98927_PCM_SR_SET1_SR_MASK (0xF << 0)
180
181#define MAX98927_PCM_SR_SET1_SR_8000 (0x0 << 0)
182#define MAX98927_PCM_SR_SET1_SR_11025 (0x1 << 0)
183#define MAX98927_PCM_SR_SET1_SR_12000 (0x2 << 0)
184#define MAX98927_PCM_SR_SET1_SR_16000 (0x3 << 0)
185#define MAX98927_PCM_SR_SET1_SR_22050 (0x4 << 0)
186#define MAX98927_PCM_SR_SET1_SR_24000 (0x5 << 0)
187#define MAX98927_PCM_SR_SET1_SR_32000 (0x6 << 0)
188#define MAX98927_PCM_SR_SET1_SR_44100 (0x7 << 0)
189#define MAX98927_PCM_SR_SET1_SR_48000 (0x8 << 0)
190
191/* MAX98927_R0024_PCM_SR_SETUP2 */
192#define MAX98927_PCM_SR_SET2_SR_MASK (0xF << 4)
193#define MAX98927_PCM_SR_SET2_SR_SHIFT (4)
194#define MAX98927_PCM_SR_SET2_IVADC_SR_MASK (0xf << 0)
195
196/* MAX98927_R0025_PCM_TO_SPK_MONOMIX_A */
197#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
198#define MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
199
200/* MAX98927_R0035_PDM_RX_CTRL */
201#define MAX98927_PDM_RX_EN_MASK (0x1 << 0)
202
203/* MAX98927_R0036_AMP_VOL_CTRL */
204#define MAX98927_AMP_VOL_SEL (0x1 << 7)
205#define MAX98927_AMP_VOL_SEL_WIDTH (1)
206#define MAX98927_AMP_VOL_SEL_SHIFT (7)
207#define MAX98927_AMP_VOL_MASK (0x7f << 0)
208#define MAX98927_AMP_VOL_WIDTH (7)
209#define MAX98927_AMP_VOL_SHIFT (0)
210
211/* MAX98927_R0037_AMP_DSP_CFG */
212#define MAX98927_AMP_DSP_CFG_DCBLK_EN (0x1 << 0)
213#define MAX98927_AMP_DSP_CFG_DITH_EN (0x1 << 1)
214#define MAX98927_AMP_DSP_CFG_RMP_BYPASS (0x1 << 4)
215#define MAX98927_AMP_DSP_CFG_DAC_INV (0x1 << 5)
216#define MAX98927_AMP_DSP_CFG_RMP_SHIFT (4)
217
218/* MAX98927_R0039_DRE_CTRL */
219#define MAX98927_DRE_CTRL_DRE_EN	(0x1 << 0)
220#define MAX98927_DRE_EN_SHIFT 0x1
221
222/* MAX98927_R003A_AMP_EN */
223#define MAX98927_AMP_EN_MASK (0x1 << 0)
224
225/* MAX98927_R003B_SPK_SRC_SEL */
226#define MAX98927_SPK_SRC_MASK (0x3 << 0)
227
228/* MAX98927_R003C_SPK_GAIN */
229#define MAX98927_SPK_PCM_GAIN_MASK (0x7 << 0)
230#define MAX98927_SPK_PDM_GAIN_MASK (0x7 << 4)
231#define MAX98927_SPK_GAIN_WIDTH (3)
232
233/* MAX98927_R003E_MEAS_EN */
234#define MAX98927_MEAS_V_EN (0x1 << 0)
235#define MAX98927_MEAS_I_EN (0x1 << 1)
236
237/* MAX98927_R0040_BOOST_CTRL0 */
238#define MAX98927_BOOST_CTRL0_VOUT_MASK (0x1f << 0)
239#define MAX98927_BOOST_CTRL0_PVDD_MASK (0x1 << 7)
240#define MAX98927_BOOST_CTRL0_PVDD_EN_SHIFT (7)
241
242/* MAX98927_R0052_BROWNOUT_EN */
243#define MAX98927_BROWNOUT_BDE_EN (0x1 << 0)
244#define MAX98927_BROWNOUT_AMP_EN (0x1 << 1)
245#define MAX98927_BROWNOUT_DSP_EN (0x1 << 2)
246#define MAX98927_BROWNOUT_DSP_SHIFT (2)
247
248/* MAX98927_R0100_SOFT_RESET */
249#define MAX98927_SOFT_RESET (0x1 << 0)
250
251/* MAX98927_R00FF_GLOBAL_SHDN */
252#define MAX98927_GLOBAL_EN_MASK (0x1 << 0)
253
254struct max98927_priv {
255	struct regmap *regmap;
256	struct snd_soc_component *component;
257	struct max98927_pdata *pdata;
258	struct gpio_desc *reset_gpio; 
259	unsigned int spk_gain;
260	unsigned int sysclk;
261	unsigned int v_l_slot;
262	unsigned int i_l_slot;
263	bool interleave_mode;
264	unsigned int ch_size;
265	unsigned int rate;
266	unsigned int iface;
267	unsigned int provider;
268	unsigned int digital_gain;
269	bool tdm_mode;
270};
271#endif