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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * cs35l34.h -- CS35L34 ALSA SoC audio driver
4 *
5 * Copyright 2016 Cirrus Logic, Inc.
6 *
7 * Author: Paul Handrigan <Paul.Handrigan@cirrus.com>
8 */
9
10#ifndef __CS35L34_H__
11#define __CS35L34_H__
12
13#define CS35L34_CHIP_ID 0x00035A34
14#define CS35L34_DEVID_AB 0x01 /* Device ID A & B [RO] */
15#define CS35L34_DEVID_CD 0x02 /* Device ID C & D [RO] */
16#define CS35L34_DEVID_E 0x03 /* Device ID E [RO] */
17#define CS35L34_FAB_ID 0x04 /* Fab ID [RO] */
18#define CS35L34_REV_ID 0x05 /* Revision ID [RO] */
19#define CS35L34_PWRCTL1 0x06 /* Power Ctl 1 */
20#define CS35L34_PWRCTL2 0x07 /* Power Ctl 2 */
21#define CS35L34_PWRCTL3 0x08 /* Power Ctl 3 */
22#define CS35L34_ADSP_CLK_CTL 0x0A /* (ADSP) Clock Ctl */
23#define CS35L34_MCLK_CTL 0x0B /* Master Clocking Ctl */
24#define CS35L34_AMP_INP_DRV_CTL 0x14 /* Amp Input Drive Ctl */
25#define CS35L34_AMP_DIG_VOL_CTL 0x15 /* Amplifier Dig Volume Ctl */
26#define CS35L34_AMP_DIG_VOL 0x16 /* Amplifier Dig Volume */
27#define CS35L34_AMP_ANLG_GAIN_CTL 0x17 /* Amplifier Analog Gain Ctl */
28#define CS35L34_PROTECT_CTL 0x18 /* Amp Gain - Prot Ctl Param */
29#define CS35L34_AMP_KEEP_ALIVE_CTL 0x1A /* Amplifier Keep Alive Ctl */
30#define CS35L34_BST_CVTR_V_CTL 0x1D /* Boost Conv Voltage Ctl */
31#define CS35L34_BST_PEAK_I 0x1E /* Boost Conv Peak Current */
32#define CS35L34_BST_RAMP_CTL 0x20 /* Boost Conv Soft Ramp Ctl */
33#define CS35L34_BST_CONV_COEF_1 0x21 /* Boost Conv Coefficients 1 */
34#define CS35L34_BST_CONV_COEF_2 0x22 /* Boost Conv Coefficients 2 */
35#define CS35L34_BST_CONV_SLOPE_COMP 0x23 /* Boost Conv Slope Comp */
36#define CS35L34_BST_CONV_SW_FREQ 0x24 /* Boost Conv L BST SW Freq */
37#define CS35L34_CLASS_H_CTL 0x30 /* CLS H Control */
38#define CS35L34_CLASS_H_HEADRM_CTL 0x31 /* CLS H Headroom Ctl */
39#define CS35L34_CLASS_H_RELEASE_RATE 0x32 /* CLS H Release Rate */
40#define CS35L34_CLASS_H_FET_DRIVE_CTL 0x33 /* CLS H Weak FET Drive Ctl */
41#define CS35L34_CLASS_H_STATUS 0x38 /* CLS H Status */
42#define CS35L34_VPBR_CTL 0x3A /* VPBR Ctl */
43#define CS35L34_VPBR_VOL_CTL 0x3B /* VPBR Volume Ctl */
44#define CS35L34_VPBR_TIMING_CTL 0x3C /* VPBR Timing Ctl */
45#define CS35L34_PRED_MAX_ATTEN_SPK_LOAD 0x40 /* PRD Max Atten / Spkr Load */
46#define CS35L34_PRED_BROWNOUT_THRESH 0x41 /* PRD Brownout Threshold */
47#define CS35L34_PRED_BROWNOUT_VOL_CTL 0x42 /* PRD Brownout Volume Ctl */
48#define CS35L34_PRED_BROWNOUT_RATE_CTL 0x43 /* PRD Brownout Rate Ctl */
49#define CS35L34_PRED_WAIT_CTL 0x44 /* PRD Wait Ctl */
50#define CS35L34_PRED_ZVP_INIT_IMP_CTL 0x46 /* PRD ZVP Initial Imp Ctl */
51#define CS35L34_PRED_MAN_SAFE_VPI_CTL 0x47 /* PRD Manual Safe VPI Ctl */
52#define CS35L34_VPBR_ATTEN_STATUS 0x4B /* VPBR Attenuation Status */
53#define CS35L34_PRED_BRWNOUT_ATT_STATUS 0x4C /* PRD Brownout Atten Status */
54#define CS35L34_SPKR_MON_CTL 0x4E /* Speaker Monitoring Ctl */
55#define CS35L34_ADSP_I2S_CTL 0x50 /* ADSP I2S Ctl */
56#define CS35L34_ADSP_TDM_CTL 0x51 /* ADSP TDM Ctl */
57#define CS35L34_TDM_TX_CTL_1_VMON 0x52 /* TDM TX Ctl 1 (VMON) */
58#define CS35L34_TDM_TX_CTL_2_IMON 0x53 /* TDM TX Ctl 2 (IMON) */
59#define CS35L34_TDM_TX_CTL_3_VPMON 0x54 /* TDM TX Ctl 3 (VPMON) */
60#define CS35L34_TDM_TX_CTL_4_VBSTMON 0x55 /* TDM TX Ctl 4 (VBSTMON) */
61#define CS35L34_TDM_TX_CTL_5_FLAG1 0x56 /* TDM TX Ctl 5 (FLAG1) */
62#define CS35L34_TDM_TX_CTL_6_FLAG2 0x57 /* TDM TX Ctl 6 (FLAG2) */
63#define CS35L34_TDM_TX_SLOT_EN_1 0x5A /* TDM TX Slot Enable */
64#define CS35L34_TDM_TX_SLOT_EN_2 0x5B /* TDM TX Slot Enable */
65#define CS35L34_TDM_TX_SLOT_EN_3 0x5C /* TDM TX Slot Enable */
66#define CS35L34_TDM_TX_SLOT_EN_4 0x5D /* TDM TX Slot Enable */
67#define CS35L34_TDM_RX_CTL_1_AUDIN 0x5E /* TDM RX Ctl 1 */
68#define CS35L34_TDM_RX_CTL_3_ALIVE 0x60 /* TDM RX Ctl 3 (ALIVE) */
69#define CS35L34_MULT_DEV_SYNCH1 0x62 /* Multidevice Synch */
70#define CS35L34_MULT_DEV_SYNCH2 0x63 /* Multidevice Synch 2 */
71#define CS35L34_PROT_RELEASE_CTL 0x64 /* Protection Release Ctl */
72#define CS35L34_DIAG_MODE_REG_LOCK 0x68 /* Diagnostic Mode Reg Lock */
73#define CS35L34_DIAG_MODE_CTL_1 0x69 /* Diagnostic Mode Ctl 1 */
74#define CS35L34_DIAG_MODE_CTL_2 0x6A /* Diagnostic Mode Ctl 2 */
75#define CS35L34_INT_MASK_1 0x70 /* Interrupt Mask 1 */
76#define CS35L34_INT_MASK_2 0x71 /* Interrupt Mask 2 */
77#define CS35L34_INT_MASK_3 0x72 /* Interrupt Mask 3 */
78#define CS35L34_INT_MASK_4 0x73 /* Interrupt Mask 4 */
79#define CS35L34_INT_STATUS_1 0x74 /* Interrupt Status 1 */
80#define CS35L34_INT_STATUS_2 0x75 /* Interrupt Status 2 */
81#define CS35L34_INT_STATUS_3 0x76 /* Interrupt Status 3 */
82#define CS35L34_INT_STATUS_4 0x77 /* Interrupt Status 4 */
83#define CS35L34_OTP_TRIM_STATUS 0x7E /* OTP Trim Status */
84
85#define CS35L34_MAX_REGISTER 0x7F
86#define CS35L34_REGISTER_COUNT 0x4E
87
88#define CS35L34_MCLK_5644 5644800
89#define CS35L34_MCLK_6144 6144000
90#define CS35L34_MCLK_6 6000000
91#define CS35L34_MCLK_11289 11289600
92#define CS35L34_MCLK_12 12000000
93#define CS35L34_MCLK_12288 12288000
94
95/* CS35L34_PWRCTL1 */
96#define CS35L34_SFT_RST (1 << 7)
97#define CS35L34_DISCHG_FLT (1 << 1)
98#define CS35L34_PDN_ALL 1
99
100/* CS35L34_PWRCTL2 */
101#define CS35L34_PDN_VMON (1 << 7)
102#define CS35L34_PDN_IMON (1 << 6)
103#define CS35L34_PDN_CLASSH (1 << 5)
104#define CS35L34_PDN_VPBR (1 << 4)
105#define CS35L34_PDN_PRED (1 << 3)
106#define CS35L34_PDN_BST (1 << 2)
107#define CS35L34_PDN_AMP 1
108
109/* CS35L34_PWRCTL3 */
110#define CS35L34_MCLK_DIS (1 << 7)
111#define CS35L34_PDN_VBSTMON_OUT (1 << 4)
112#define CS35L34_PDN_VMON_OUT (1 << 3)
113/* Tristate the ADSP SDOUT when in I2C mode */
114#define CS35L34_PDN_SDOUT (1 << 2)
115#define CS35L34_PDN_SDIN (1 << 1)
116#define CS35L34_PDN_TDM 1
117
118/* CS35L34_ADSP_CLK_CTL */
119#define CS35L34_ADSP_RATE 0xF
120#define CS35L34_ADSP_DRIVE (1 << 4)
121#define CS35L34_ADSP_M_S (1 << 7)
122
123/* CS35L34_MCLK_CTL */
124#define CS35L34_MCLK_DIV (1 << 4)
125#define CS35L34_MCLK_RATE_MASK 0x7
126#define CS35L34_MCLK_RATE_6P1440 0x2
127#define CS35L34_MCLK_RATE_6P0000 0x1
128#define CS35L34_MCLK_RATE_5P6448 0x0
129#define CS35L34_MCLKDIS (1 << 7)
130#define CS35L34_MCLKDIV2 (1 << 6)
131#define CS35L34_SDOUT_3ST_TDM (1 << 5)
132#define CS35L34_INT_FS_RATE (1 << 4)
133#define CS35L34_ADSP_FS 0xF
134
135/* CS35L34_AMP_INP_DRV_CTL */
136#define CS35L34_DRV_STR_SRC (1 << 1)
137#define CS35L34_DRV_STR 1
138
139/* CS35L34_AMP_DIG_VOL_CTL */
140#define CS35L34_AMP_DSR_RATE_MASK 0xF0
141#define CS35L34_AMP_DSR_RATE_SHIFT (1 << 4)
142#define CS35L34_NOTCH_DIS (1 << 3)
143#define CS35L34_AMP_DIGSFT (1 << 1)
144#define CS35L34_INV 1
145
146/* CS35L34_PROTECT_CTL */
147#define CS35L34_OTW_ATTN_MASK 0xC
148#define CS35L34_OTW_THRD_MASK 0x3
149#define CS35L34_MUTE (1 << 5)
150#define CS35L34_GAIN_ZC (1 << 4)
151#define CS35L34_GAIN_ZC_MASK 0x10
152#define CS35L34_GAIN_ZC_SHIFT 4
153
154/* CS35L34_AMP_KEEP_ALIVE_CTL */
155#define CS35L34_ALIVE_WD_DIS (1 << 2)
156
157/* CS35L34_BST_CVTR_V_CTL */
158#define CS35L34_BST_CVTL_MASK 0x3F
159
160/* CS35L34_BST_PEAK_I */
161#define CS35L34_BST_PEAK_MASK 0x3F
162
163/* CS35L34_ADSP_I2S_CTL */
164#define CS35L34_I2S_LOC_MASK 0xC
165#define CS35L34_I2S_LOC_SHIFT 2
166
167/* CS35L34_MULT_DEV_SYNCH2 */
168#define CS35L34_SYNC2_MASK 0xF
169
170/* CS35L34_PROT_RELEASE_CTL */
171#define CS35L34_CAL_ERR_RLS (1 << 7)
172#define CS35L34_SHORT_RLS (1 << 2)
173#define CS35L34_OTW_RLS (1 << 1)
174#define CS35L34_OTE_RLS 1
175
176/* CS35L34_INT_MASK_1 */
177#define CS35L34_M_CAL_ERR_SHIFT 7
178#define CS35L34_M_CAL_ERR (1 << CS35L34_M_CAL_ERR_SHIFT)
179#define CS35L34_M_ALIVE_ERR_SHIFT 5
180#define CS35L34_M_ALIVE_ERR (1 << CS35L34_M_ALIVE_ERR_SHIFT)
181#define CS35L34_M_ADSP_CLK_SHIFT 4
182#define CS35L34_M_ADSP_CLK_ERR (1 << CS35L34_M_ADSP_CLK_SHIFT)
183#define CS35L34_M_MCLK_SHIFT 3
184#define CS35L34_M_MCLK_ERR (1 << CS35L34_M_MCLK_SHIFT)
185#define CS35L34_M_AMP_SHORT_SHIFT 2
186#define CS35L34_M_AMP_SHORT (1 << CS35L34_M_AMP_SHORT_SHIFT)
187#define CS35L34_M_OTW_SHIFT 1
188#define CS35L34_M_OTW (1 << CS35L34_M_OTW_SHIFT)
189#define CS35L34_M_OTE_SHIFT 0
190#define CS35L34_M_OTE (1 << CS35L34_M_OTE_SHIFT)
191
192/* CS35L34_INT_MASK_2 */
193#define CS35L34_M_PDN_DONE_SHIFT 4
194#define CS35L34_M_PDN_DONE (1 << CS35L34_M_PDN_DONE_SHIFT)
195#define CS35L34_M_PRED_SHIFT 3
196#define CS35L34_M_PRED_ERR (1 << CS35L34_M_PRED_SHIFT)
197#define CS35L34_M_PRED_CLR_SHIFT 2
198#define CS35L34_M_PRED_CLR (1 << CS35L34_M_PRED_CLR_SHIFT)
199#define CS35L34_M_VPBR_SHIFT 1
200#define CS35L34_M_VPBR_ERR (1 << CS35L34_M_VPBR_SHIFT)
201#define CS35L34_M_VPBR_CLR_SHIFT 0
202#define CS35L34_M_VPBR_CLR (1 << CS35L34_M_VPBR_CLR_SHIFT)
203
204/* CS35L34_INT_MASK_3 */
205#define CS35L34_M_BST_HIGH_SHIFT 4
206#define CS35L34_M_BST_HIGH (1 << CS35L34_M_BST_HIGH_SHIFT)
207#define CS35L34_M_BST_HIGH_FLAG_SHIFT 3
208#define CS35L34_M_BST_HIGH_FLAG (1 << CS35L34_M_BST_HIGH_FLAG_SHIFT)
209#define CS35L34_M_BST_IPK_FLAG_SHIFT 2
210#define CS35L34_M_BST_IPK_FLAG (1 << CS35L34_M_BST_IPK_FLAG_SHIFT)
211#define CS35L34_M_LBST_SHORT_SHIFT 0
212#define CS35L34_M_LBST_SHORT (1 << CS35L34_M_LBST_SHORT_SHIFT)
213
214/* CS35L34_INT_MASK_4 */
215#define CS35L34_M_VMON_OVFL_SHIFT 3
216#define CS35L34_M_VMON_OVFL (1 << CS35L34_M_VMON_OVFL_SHIFT)
217#define CS35L34_M_IMON_OVFL_SHIFT 2
218#define CS35L34_M_IMON_OVFL (1 << CS35L34_M_IMON_OVFL_SHIFT)
219#define CS35L34_M_VPMON_OVFL_SHIFT 1
220#define CS35L34_M_VPMON_OVFL (1 << CS35L34_M_VPMON_OVFL_SHIFT)
221#define CS35L34_M_VBSTMON_OVFL_SHIFT 1
222#define CS35L34_M_VBSTMON_OVFL (1 << CS35L34_M_VBSTMON_OVFL_SHIFT)
223
224/* CS35L34_INT_1 */
225#define CS35L34_CAL_ERR (1 << CS35L34_M_CAL_ERR_SHIFT)
226#define CS35L34_ALIVE_ERR (1 << CS35L34_M_ALIVE_ERR_SHIFT)
227#define CS35L34_M_ADSP_CLK_ERR (1 << CS35L34_M_ADSP_CLK_SHIFT)
228#define CS35L34_MCLK_ERR (1 << CS35L34_M_MCLK_SHIFT)
229#define CS35L34_AMP_SHORT (1 << CS35L34_M_AMP_SHORT_SHIFT)
230#define CS35L34_OTW (1 << CS35L34_M_OTW_SHIFT)
231#define CS35L34_OTE (1 << CS35L34_M_OTE_SHIFT)
232
233/* CS35L34_INT_2 */
234#define CS35L34_PDN_DONE (1 << CS35L34_M_PDN_DONE_SHIFT)
235#define CS35L34_PRED_ERR (1 << CS35L34_M_PRED_SHIFT)
236#define CS35L34_PRED_CLR (1 << CS35L34_M_PRED_CLR_SHIFT)
237#define CS35L34_VPBR_ERR (1 << CS35L34_M_VPBR_SHIFT)
238#define CS35L34_VPBR_CLR (1 << CS35L34_M_VPBR_CLR_SHIFT)
239
240/* CS35L34_INT_3 */
241#define CS35L34_BST_HIGH (1 << CS35L34_M_BST_HIGH_SHIFT)
242#define CS35L34_BST_HIGH_FLAG (1 << CS35L34_M_BST_HIGH_FLAG_SHIFT)
243#define CS35L34_BST_IPK_FLAG (1 << CS35L34_M_BST_IPK_FLAG_SHIFT)
244#define CS35L34_LBST_SHORT (1 << CS35L34_M_LBST_SHORT_SHIFT)
245
246/* CS35L34_INT_4 */
247#define CS35L34_VMON_OVFL (1 << CS35L34_M_VMON_OVFL_SHIFT)
248#define CS35L34_IMON_OVFL (1 << CS35L34_M_IMON_OVFL_SHIFT)
249#define CS35L34_VPMON_OVFL (1 << CS35L34_M_VPMON_OVFL_SHIFT)
250#define CS35L34_VBSTMON_OVFL (1 << CS35L34_M_VBSTMON_OVFL_SHIFT)
251
252/* CS35L34_{RX,TX}_X */
253#define CS35L34_X_STATE_SHIFT 7
254#define CS35L34_X_STATE (1 << CS35L34_X_STATE_SHIFT)
255#define CS35L34_X_LOC_SHIFT 0
256#define CS35L34_X_LOC (0x1F << CS35L34_X_LOC_SHIFT)
257
258#define CS35L34_RATES (SNDRV_PCM_RATE_48000 | \
259 SNDRV_PCM_RATE_44100 | \
260 SNDRV_PCM_RATE_32000)
261#define CS35L34_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
262 SNDRV_PCM_FMTBIT_S24_LE | \
263 SNDRV_PCM_FMTBIT_S32_LE)
264
265#endif
1/*
2 * cs35l34.h -- CS35L34 ALSA SoC audio driver
3 *
4 * Copyright 2016 Cirrus Logic, Inc.
5 *
6 * Author: Paul Handrigan <Paul.Handrigan@cirrus.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#ifndef __CS35L34_H__
15#define __CS35L34_H__
16
17#define CS35L34_CHIP_ID 0x00035A34
18#define CS35L34_DEVID_AB 0x01 /* Device ID A & B [RO] */
19#define CS35L34_DEVID_CD 0x02 /* Device ID C & D [RO] */
20#define CS35L34_DEVID_E 0x03 /* Device ID E [RO] */
21#define CS35L34_FAB_ID 0x04 /* Fab ID [RO] */
22#define CS35L34_REV_ID 0x05 /* Revision ID [RO] */
23#define CS35L34_PWRCTL1 0x06 /* Power Ctl 1 */
24#define CS35L34_PWRCTL2 0x07 /* Power Ctl 2 */
25#define CS35L34_PWRCTL3 0x08 /* Power Ctl 3 */
26#define CS35L34_ADSP_CLK_CTL 0x0A /* (ADSP) Clock Ctl */
27#define CS35L34_MCLK_CTL 0x0B /* Master Clocking Ctl */
28#define CS35L34_AMP_INP_DRV_CTL 0x14 /* Amp Input Drive Ctl */
29#define CS35L34_AMP_DIG_VOL_CTL 0x15 /* Amplifier Dig Volume Ctl */
30#define CS35L34_AMP_DIG_VOL 0x16 /* Amplifier Dig Volume */
31#define CS35L34_AMP_ANLG_GAIN_CTL 0x17 /* Amplifier Analog Gain Ctl */
32#define CS35L34_PROTECT_CTL 0x18 /* Amp Gain - Prot Ctl Param */
33#define CS35L34_AMP_KEEP_ALIVE_CTL 0x1A /* Amplifier Keep Alive Ctl */
34#define CS35L34_BST_CVTR_V_CTL 0x1D /* Boost Conv Voltage Ctl */
35#define CS35L34_BST_PEAK_I 0x1E /* Boost Conv Peak Current */
36#define CS35L34_BST_RAMP_CTL 0x20 /* Boost Conv Soft Ramp Ctl */
37#define CS35L34_BST_CONV_COEF_1 0x21 /* Boost Conv Coefficients 1 */
38#define CS35L34_BST_CONV_COEF_2 0x22 /* Boost Conv Coefficients 2 */
39#define CS35L34_BST_CONV_SLOPE_COMP 0x23 /* Boost Conv Slope Comp */
40#define CS35L34_BST_CONV_SW_FREQ 0x24 /* Boost Conv L BST SW Freq */
41#define CS35L34_CLASS_H_CTL 0x30 /* CLS H Control */
42#define CS35L34_CLASS_H_HEADRM_CTL 0x31 /* CLS H Headroom Ctl */
43#define CS35L34_CLASS_H_RELEASE_RATE 0x32 /* CLS H Release Rate */
44#define CS35L34_CLASS_H_FET_DRIVE_CTL 0x33 /* CLS H Weak FET Drive Ctl */
45#define CS35L34_CLASS_H_STATUS 0x38 /* CLS H Status */
46#define CS35L34_VPBR_CTL 0x3A /* VPBR Ctl */
47#define CS35L34_VPBR_VOL_CTL 0x3B /* VPBR Volume Ctl */
48#define CS35L34_VPBR_TIMING_CTL 0x3C /* VPBR Timing Ctl */
49#define CS35L34_PRED_MAX_ATTEN_SPK_LOAD 0x40 /* PRD Max Atten / Spkr Load */
50#define CS35L34_PRED_BROWNOUT_THRESH 0x41 /* PRD Brownout Threshold */
51#define CS35L34_PRED_BROWNOUT_VOL_CTL 0x42 /* PRD Brownout Volume Ctl */
52#define CS35L34_PRED_BROWNOUT_RATE_CTL 0x43 /* PRD Brownout Rate Ctl */
53#define CS35L34_PRED_WAIT_CTL 0x44 /* PRD Wait Ctl */
54#define CS35L34_PRED_ZVP_INIT_IMP_CTL 0x46 /* PRD ZVP Initial Imp Ctl */
55#define CS35L34_PRED_MAN_SAFE_VPI_CTL 0x47 /* PRD Manual Safe VPI Ctl */
56#define CS35L34_VPBR_ATTEN_STATUS 0x4B /* VPBR Attenuation Status */
57#define CS35L34_PRED_BRWNOUT_ATT_STATUS 0x4C /* PRD Brownout Atten Status */
58#define CS35L34_SPKR_MON_CTL 0x4E /* Speaker Monitoring Ctl */
59#define CS35L34_ADSP_I2S_CTL 0x50 /* ADSP I2S Ctl */
60#define CS35L34_ADSP_TDM_CTL 0x51 /* ADSP TDM Ctl */
61#define CS35L34_TDM_TX_CTL_1_VMON 0x52 /* TDM TX Ctl 1 (VMON) */
62#define CS35L34_TDM_TX_CTL_2_IMON 0x53 /* TDM TX Ctl 2 (IMON) */
63#define CS35L34_TDM_TX_CTL_3_VPMON 0x54 /* TDM TX Ctl 3 (VPMON) */
64#define CS35L34_TDM_TX_CTL_4_VBSTMON 0x55 /* TDM TX Ctl 4 (VBSTMON) */
65#define CS35L34_TDM_TX_CTL_5_FLAG1 0x56 /* TDM TX Ctl 5 (FLAG1) */
66#define CS35L34_TDM_TX_CTL_6_FLAG2 0x57 /* TDM TX Ctl 6 (FLAG2) */
67#define CS35L34_TDM_TX_SLOT_EN_1 0x5A /* TDM TX Slot Enable */
68#define CS35L34_TDM_TX_SLOT_EN_2 0x5B /* TDM TX Slot Enable */
69#define CS35L34_TDM_TX_SLOT_EN_3 0x5C /* TDM TX Slot Enable */
70#define CS35L34_TDM_TX_SLOT_EN_4 0x5D /* TDM TX Slot Enable */
71#define CS35L34_TDM_RX_CTL_1_AUDIN 0x5E /* TDM RX Ctl 1 */
72#define CS35L34_TDM_RX_CTL_3_ALIVE 0x60 /* TDM RX Ctl 3 (ALIVE) */
73#define CS35L34_MULT_DEV_SYNCH1 0x62 /* Multidevice Synch */
74#define CS35L34_MULT_DEV_SYNCH2 0x63 /* Multidevice Synch 2 */
75#define CS35L34_PROT_RELEASE_CTL 0x64 /* Protection Release Ctl */
76#define CS35L34_DIAG_MODE_REG_LOCK 0x68 /* Diagnostic Mode Reg Lock */
77#define CS35L34_DIAG_MODE_CTL_1 0x69 /* Diagnostic Mode Ctl 1 */
78#define CS35L34_DIAG_MODE_CTL_2 0x6A /* Diagnostic Mode Ctl 2 */
79#define CS35L34_INT_MASK_1 0x70 /* Interrupt Mask 1 */
80#define CS35L34_INT_MASK_2 0x71 /* Interrupt Mask 2 */
81#define CS35L34_INT_MASK_3 0x72 /* Interrupt Mask 3 */
82#define CS35L34_INT_MASK_4 0x73 /* Interrupt Mask 4 */
83#define CS35L34_INT_STATUS_1 0x74 /* Interrupt Status 1 */
84#define CS35L34_INT_STATUS_2 0x75 /* Interrupt Status 2 */
85#define CS35L34_INT_STATUS_3 0x76 /* Interrupt Status 3 */
86#define CS35L34_INT_STATUS_4 0x77 /* Interrupt Status 4 */
87#define CS35L34_OTP_TRIM_STATUS 0x7E /* OTP Trim Status */
88
89#define CS35L34_MAX_REGISTER 0x7F
90#define CS35L34_REGISTER_COUNT 0x4E
91
92#define CS35L34_MCLK_5644 5644800
93#define CS35L34_MCLK_6144 6144000
94#define CS35L34_MCLK_6 6000000
95#define CS35L34_MCLK_11289 11289600
96#define CS35L34_MCLK_12 12000000
97#define CS35L34_MCLK_12288 12288000
98
99/* CS35L34_PWRCTL1 */
100#define CS35L34_SFT_RST (1 << 7)
101#define CS35L34_DISCHG_FLT (1 << 1)
102#define CS35L34_PDN_ALL 1
103
104/* CS35L34_PWRCTL2 */
105#define CS35L34_PDN_VMON (1 << 7)
106#define CS35L34_PDN_IMON (1 << 6)
107#define CS35L34_PDN_CLASSH (1 << 5)
108#define CS35L34_PDN_VPBR (1 << 4)
109#define CS35L34_PDN_PRED (1 << 3)
110#define CS35L34_PDN_BST (1 << 2)
111#define CS35L34_PDN_AMP 1
112
113/* CS35L34_PWRCTL3 */
114#define CS35L34_MCLK_DIS (1 << 7)
115#define CS35L34_PDN_VBSTMON_OUT (1 << 4)
116#define CS35L34_PDN_VMON_OUT (1 << 3)
117/* Tristate the ADSP SDOUT when in I2C mode */
118#define CS35L34_PDN_SDOUT (1 << 2)
119#define CS35L34_PDN_SDIN (1 << 1)
120#define CS35L34_PDN_TDM 1
121
122/* CS35L34_ADSP_CLK_CTL */
123#define CS35L34_ADSP_RATE 0xF
124#define CS35L34_ADSP_DRIVE (1 << 4)
125#define CS35L34_ADSP_M_S (1 << 7)
126
127/* CS35L34_MCLK_CTL */
128#define CS35L34_MCLK_DIV (1 << 4)
129#define CS35L34_MCLK_RATE_MASK 0x7
130#define CS35L34_MCLK_RATE_6P1440 0x2
131#define CS35L34_MCLK_RATE_6P0000 0x1
132#define CS35L34_MCLK_RATE_5P6448 0x0
133#define CS35L34_MCLKDIS (1 << 7)
134#define CS35L34_MCLKDIV2 (1 << 6)
135#define CS35L34_SDOUT_3ST_TDM (1 << 5)
136#define CS35L34_INT_FS_RATE (1 << 4)
137#define CS35L34_ADSP_FS 0xF
138
139/* CS35L34_AMP_INP_DRV_CTL */
140#define CS35L34_DRV_STR_SRC (1 << 1)
141#define CS35L34_DRV_STR 1
142
143/* CS35L34_AMP_DIG_VOL_CTL */
144#define CS35L34_AMP_DSR_RATE_MASK 0xF0
145#define CS35L34_AMP_DSR_RATE_SHIFT (1 << 4)
146#define CS35L34_NOTCH_DIS (1 << 3)
147#define CS35L34_AMP_DIGSFT (1 << 1)
148#define CS35L34_INV 1
149
150/* CS35L34_PROTECT_CTL */
151#define CS35L34_OTW_ATTN_MASK 0xC
152#define CS35L34_OTW_THRD_MASK 0x3
153#define CS35L34_MUTE (1 << 5)
154#define CS35L34_GAIN_ZC (1 << 4)
155#define CS35L34_GAIN_ZC_MASK 0x10
156#define CS35L34_GAIN_ZC_SHIFT 4
157
158/* CS35L34_AMP_KEEP_ALIVE_CTL */
159#define CS35L34_ALIVE_WD_DIS (1 << 2)
160
161/* CS35L34_BST_CVTR_V_CTL */
162#define CS35L34_BST_CVTL_MASK 0x3F
163
164/* CS35L34_BST_PEAK_I */
165#define CS35L34_BST_PEAK_MASK 0x3F
166
167/* CS35L34_ADSP_I2S_CTL */
168#define CS35L34_I2S_LOC_MASK 0xC
169#define CS35L34_I2S_LOC_SHIFT 2
170
171/* CS35L34_MULT_DEV_SYNCH2 */
172#define CS35L34_SYNC2_MASK 0xF
173
174/* CS35L34_PROT_RELEASE_CTL */
175#define CS35L34_CAL_ERR_RLS (1 << 7)
176#define CS35L34_SHORT_RLS (1 << 2)
177#define CS35L34_OTW_RLS (1 << 1)
178#define CS35L34_OTE_RLS 1
179
180/* CS35L34_INT_MASK_1 */
181#define CS35L34_M_CAL_ERR_SHIFT 7
182#define CS35L34_M_CAL_ERR (1 << CS35L34_M_CAL_ERR_SHIFT)
183#define CS35L34_M_ALIVE_ERR_SHIFT 5
184#define CS35L34_M_ALIVE_ERR (1 << CS35L34_M_ALIVE_ERR_SHIFT)
185#define CS35L34_M_ADSP_CLK_SHIFT 4
186#define CS35L34_M_ADSP_CLK_ERR (1 << CS35L34_M_ADSP_CLK_SHIFT)
187#define CS35L34_M_MCLK_SHIFT 3
188#define CS35L34_M_MCLK_ERR (1 << CS35L34_M_MCLK_SHIFT)
189#define CS35L34_M_AMP_SHORT_SHIFT 2
190#define CS35L34_M_AMP_SHORT (1 << CS35L34_M_AMP_SHORT_SHIFT)
191#define CS35L34_M_OTW_SHIFT 1
192#define CS35L34_M_OTW (1 << CS35L34_M_OTW_SHIFT)
193#define CS35L34_M_OTE_SHIFT 0
194#define CS35L34_M_OTE (1 << CS35L34_M_OTE_SHIFT)
195
196/* CS35L34_INT_MASK_2 */
197#define CS35L34_M_PDN_DONE_SHIFT 4
198#define CS35L34_M_PDN_DONE (1 << CS35L34_M_PDN_DONE_SHIFT)
199#define CS35L34_M_PRED_SHIFT 3
200#define CS35L34_M_PRED_ERR (1 << CS35L34_M_PRED_SHIFT)
201#define CS35L34_M_PRED_CLR_SHIFT 2
202#define CS35L34_M_PRED_CLR (1 << CS35L34_M_PRED_CLR_SHIFT)
203#define CS35L34_M_VPBR_SHIFT 1
204#define CS35L34_M_VPBR_ERR (1 << CS35L34_M_VPBR_SHIFT)
205#define CS35L34_M_VPBR_CLR_SHIFT 0
206#define CS35L34_M_VPBR_CLR (1 << CS35L34_M_VPBR_CLR_SHIFT)
207
208/* CS35L34_INT_MASK_3 */
209#define CS35L34_M_BST_HIGH_SHIFT 4
210#define CS35L34_M_BST_HIGH (1 << CS35L34_M_BST_HIGH_SHIFT)
211#define CS35L34_M_BST_HIGH_FLAG_SHIFT 3
212#define CS35L34_M_BST_HIGH_FLAG (1 << CS35L34_M_BST_HIGH_FLAG_SHIFT)
213#define CS35L34_M_BST_IPK_FLAG_SHIFT 2
214#define CS35L34_M_BST_IPK_FLAG (1 << CS35L34_M_BST_IPK_FLAG_SHIFT)
215#define CS35L34_M_LBST_SHORT_SHIFT 0
216#define CS35L34_M_LBST_SHORT (1 << CS35L34_M_LBST_SHORT_SHIFT)
217
218/* CS35L34_INT_MASK_4 */
219#define CS35L34_M_VMON_OVFL_SHIFT 3
220#define CS35L34_M_VMON_OVFL (1 << CS35L34_M_VMON_OVFL_SHIFT)
221#define CS35L34_M_IMON_OVFL_SHIFT 2
222#define CS35L34_M_IMON_OVFL (1 << CS35L34_M_IMON_OVFL_SHIFT)
223#define CS35L34_M_VPMON_OVFL_SHIFT 1
224#define CS35L34_M_VPMON_OVFL (1 << CS35L34_M_VPMON_OVFL_SHIFT)
225#define CS35L34_M_VBSTMON_OVFL_SHIFT 1
226#define CS35L34_M_VBSTMON_OVFL (1 << CS35L34_M_VBSTMON_OVFL_SHIFT)
227
228/* CS35L34_INT_1 */
229#define CS35L34_CAL_ERR (1 << CS35L34_M_CAL_ERR_SHIFT)
230#define CS35L34_ALIVE_ERR (1 << CS35L34_M_ALIVE_ERR_SHIFT)
231#define CS35L34_M_ADSP_CLK_ERR (1 << CS35L34_M_ADSP_CLK_SHIFT)
232#define CS35L34_MCLK_ERR (1 << CS35L34_M_MCLK_SHIFT)
233#define CS35L34_AMP_SHORT (1 << CS35L34_M_AMP_SHORT_SHIFT)
234#define CS35L34_OTW (1 << CS35L34_M_OTW_SHIFT)
235#define CS35L34_OTE (1 << CS35L34_M_OTE_SHIFT)
236
237/* CS35L34_INT_2 */
238#define CS35L34_PDN_DONE (1 << CS35L34_M_PDN_DONE_SHIFT)
239#define CS35L34_PRED_ERR (1 << CS35L34_M_PRED_SHIFT)
240#define CS35L34_PRED_CLR (1 << CS35L34_M_PRED_CLR_SHIFT)
241#define CS35L34_VPBR_ERR (1 << CS35L34_M_VPBR_SHIFT)
242#define CS35L34_VPBR_CLR (1 << CS35L34_M_VPBR_CLR_SHIFT)
243
244/* CS35L34_INT_3 */
245#define CS35L34_BST_HIGH (1 << CS35L34_M_BST_HIGH_SHIFT)
246#define CS35L34_BST_HIGH_FLAG (1 << CS35L34_M_BST_HIGH_FLAG_SHIFT)
247#define CS35L34_BST_IPK_FLAG (1 << CS35L34_M_BST_IPK_FLAG_SHIFT)
248#define CS35L34_LBST_SHORT (1 << CS35L34_M_LBST_SHORT_SHIFT)
249
250/* CS35L34_INT_4 */
251#define CS35L34_VMON_OVFL (1 << CS35L34_M_VMON_OVFL_SHIFT)
252#define CS35L34_IMON_OVFL (1 << CS35L34_M_IMON_OVFL_SHIFT)
253#define CS35L34_VPMON_OVFL (1 << CS35L34_M_VPMON_OVFL_SHIFT)
254#define CS35L34_VBSTMON_OVFL (1 << CS35L34_M_VBSTMON_OVFL_SHIFT)
255
256/* CS35L34_{RX,TX}_X */
257#define CS35L34_X_STATE_SHIFT 7
258#define CS35L34_X_STATE (1 << CS35L34_X_STATE_SHIFT)
259#define CS35L34_X_LOC_SHIFT 0
260#define CS35L34_X_LOC (0x1F << CS35L34_X_LOC_SHIFT)
261
262#define CS35L34_RATES (SNDRV_PCM_RATE_48000 | \
263 SNDRV_PCM_RATE_44100 | \
264 SNDRV_PCM_RATE_32000)
265#define CS35L34_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
266 SNDRV_PCM_FMTBIT_S24_LE | \
267 SNDRV_PCM_FMTBIT_S32_LE)
268
269#endif