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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/module.h>
7#include <linux/delay.h>
8#include <linux/devm-helpers.h>
9#include <linux/err.h>
10#include <linux/kernel.h>
11#include <linux/interrupt.h>
12#include <linux/bitops.h>
13#include <linux/slab.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/platform_device.h>
17#include <linux/ktime.h>
18#include <linux/regulator/driver.h>
19#include <linux/regmap.h>
20#include <linux/list.h>
21#include <linux/mfd/syscon.h>
22#include <linux/io.h>
23
24/* Pin control enable input pins. */
25#define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30#define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
31
32/* Pin control high power mode input pins. */
33#define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34#define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35#define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36#define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
37#define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08
38#define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
39#define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
40
41/*
42 * Used with enable parameters to specify that hardware default register values
43 * should be left unaltered.
44 */
45#define SPMI_REGULATOR_USE_HW_DEFAULT 2
46
47/* Soft start strength of a voltage switch type regulator */
48enum spmi_vs_soft_start_str {
49 SPMI_VS_SOFT_START_STR_0P05_UA = 0,
50 SPMI_VS_SOFT_START_STR_0P25_UA,
51 SPMI_VS_SOFT_START_STR_0P55_UA,
52 SPMI_VS_SOFT_START_STR_0P75_UA,
53 SPMI_VS_SOFT_START_STR_HW_DEFAULT,
54};
55
56/**
57 * struct spmi_regulator_init_data - spmi-regulator initialization data
58 * @pin_ctrl_enable: Bit mask specifying which hardware pins should be
59 * used to enable the regulator, if any
60 * Value should be an ORing of
61 * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If
62 * the bit specified by
63 * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
64 * set, then pin control enable hardware registers
65 * will not be modified.
66 * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be
67 * used to force the regulator into high power
68 * mode, if any
69 * Value should be an ORing of
70 * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If
71 * the bit specified by
72 * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
73 * set, then pin control mode hardware registers
74 * will not be modified.
75 * @vs_soft_start_strength: This parameter sets the soft start strength for
76 * voltage switch type regulators. Its value
77 * should be one of SPMI_VS_SOFT_START_STR_*. If
78 * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT,
79 * then the soft start strength will be left at its
80 * default hardware value.
81 */
82struct spmi_regulator_init_data {
83 unsigned pin_ctrl_enable;
84 unsigned pin_ctrl_hpm;
85 enum spmi_vs_soft_start_str vs_soft_start_strength;
86};
87
88/* These types correspond to unique register layouts. */
89enum spmi_regulator_logical_type {
90 SPMI_REGULATOR_LOGICAL_TYPE_SMPS,
91 SPMI_REGULATOR_LOGICAL_TYPE_LDO,
92 SPMI_REGULATOR_LOGICAL_TYPE_VS,
93 SPMI_REGULATOR_LOGICAL_TYPE_BOOST,
94 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS,
95 SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP,
96 SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO,
97 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS,
98 SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS,
99 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO,
100 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426,
101 SPMI_REGULATOR_LOGICAL_TYPE_HFS430,
102 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3,
103 SPMI_REGULATOR_LOGICAL_TYPE_LDO_510,
104 SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS,
105};
106
107enum spmi_regulator_type {
108 SPMI_REGULATOR_TYPE_BUCK = 0x03,
109 SPMI_REGULATOR_TYPE_LDO = 0x04,
110 SPMI_REGULATOR_TYPE_VS = 0x05,
111 SPMI_REGULATOR_TYPE_BOOST = 0x1b,
112 SPMI_REGULATOR_TYPE_FTS = 0x1c,
113 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f,
114 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21,
115 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22,
116};
117
118enum spmi_regulator_subtype {
119 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08,
120 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09,
121 SPMI_REGULATOR_SUBTYPE_N50 = 0x01,
122 SPMI_REGULATOR_SUBTYPE_N150 = 0x02,
123 SPMI_REGULATOR_SUBTYPE_N300 = 0x03,
124 SPMI_REGULATOR_SUBTYPE_N600 = 0x04,
125 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05,
126 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06,
127 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07,
128 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14,
129 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15,
130 SPMI_REGULATOR_SUBTYPE_P50 = 0x08,
131 SPMI_REGULATOR_SUBTYPE_P150 = 0x09,
132 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a,
133 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b,
134 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c,
135 SPMI_REGULATOR_SUBTYPE_LN = 0x10,
136 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28,
137 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29,
138 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a,
139 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b,
140 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c,
141 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d,
142 SPMI_REGULATOR_SUBTYPE_HT_N300_ST = 0x30,
143 SPMI_REGULATOR_SUBTYPE_HT_N600_ST = 0x31,
144 SPMI_REGULATOR_SUBTYPE_HT_N1200_ST = 0x32,
145 SPMI_REGULATOR_SUBTYPE_HT_LVP150 = 0x3b,
146 SPMI_REGULATOR_SUBTYPE_HT_LVP300 = 0x3c,
147 SPMI_REGULATOR_SUBTYPE_L660_N300_ST = 0x42,
148 SPMI_REGULATOR_SUBTYPE_L660_N600_ST = 0x43,
149 SPMI_REGULATOR_SUBTYPE_L660_P50 = 0x46,
150 SPMI_REGULATOR_SUBTYPE_L660_P150 = 0x47,
151 SPMI_REGULATOR_SUBTYPE_L660_P600 = 0x49,
152 SPMI_REGULATOR_SUBTYPE_L660_LVP150 = 0x4d,
153 SPMI_REGULATOR_SUBTYPE_L660_LVP600 = 0x4f,
154 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01,
155 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02,
156 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08,
157 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09,
158 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10,
159 SPMI_REGULATOR_SUBTYPE_OTG = 0x11,
160 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01,
161 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08,
162 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09,
163 SPMI_REGULATOR_SUBTYPE_FTS426_CTL = 0x0a,
164 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01,
165 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d,
166 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e,
167 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
168 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
169 SPMI_REGULATOR_SUBTYPE_HFS430 = 0x0a,
170 SPMI_REGULATOR_SUBTYPE_HT_P150 = 0x35,
171 SPMI_REGULATOR_SUBTYPE_HT_P600 = 0x3d,
172 SPMI_REGULATOR_SUBTYPE_HFSMPS_510 = 0x0a,
173 SPMI_REGULATOR_SUBTYPE_FTSMPS_510 = 0x0b,
174 SPMI_REGULATOR_SUBTYPE_LV_P150_510 = 0x71,
175 SPMI_REGULATOR_SUBTYPE_LV_P300_510 = 0x72,
176 SPMI_REGULATOR_SUBTYPE_LV_P600_510 = 0x73,
177 SPMI_REGULATOR_SUBTYPE_N300_510 = 0x6a,
178 SPMI_REGULATOR_SUBTYPE_N600_510 = 0x6b,
179 SPMI_REGULATOR_SUBTYPE_N1200_510 = 0x6c,
180 SPMI_REGULATOR_SUBTYPE_MV_P50_510 = 0x7a,
181 SPMI_REGULATOR_SUBTYPE_MV_P150_510 = 0x7b,
182 SPMI_REGULATOR_SUBTYPE_MV_P600_510 = 0x7d,
183};
184
185enum spmi_common_regulator_registers {
186 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01,
187 SPMI_COMMON_REG_TYPE = 0x04,
188 SPMI_COMMON_REG_SUBTYPE = 0x05,
189 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40,
190 SPMI_COMMON_REG_VOLTAGE_SET = 0x41,
191 SPMI_COMMON_REG_MODE = 0x45,
192 SPMI_COMMON_REG_ENABLE = 0x46,
193 SPMI_COMMON_REG_PULL_DOWN = 0x48,
194 SPMI_COMMON_REG_SOFT_START = 0x4c,
195 SPMI_COMMON_REG_STEP_CTRL = 0x61,
196};
197
198/*
199 * Second common register layout used by newer devices starting with ftsmps426
200 * Note that some of the registers from the first common layout remain
201 * unchanged and their definition is not duplicated.
202 */
203enum spmi_ftsmps426_regulator_registers {
204 SPMI_FTSMPS426_REG_VOLTAGE_LSB = 0x40,
205 SPMI_FTSMPS426_REG_VOLTAGE_MSB = 0x41,
206 SPMI_FTSMPS426_REG_VOLTAGE_ULS_LSB = 0x68,
207 SPMI_FTSMPS426_REG_VOLTAGE_ULS_MSB = 0x69,
208};
209
210/*
211 * Third common register layout
212 */
213enum spmi_hfsmps_regulator_registers {
214 SPMI_HFSMPS_REG_STEP_CTRL = 0x3c,
215 SPMI_HFSMPS_REG_PULL_DOWN = 0xa0,
216};
217
218enum spmi_vs_registers {
219 SPMI_VS_REG_OCP = 0x4a,
220 SPMI_VS_REG_SOFT_START = 0x4c,
221};
222
223enum spmi_boost_registers {
224 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a,
225};
226
227enum spmi_boost_byp_registers {
228 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b,
229};
230
231enum spmi_saw3_registers {
232 SAW3_SECURE = 0x00,
233 SAW3_ID = 0x04,
234 SAW3_SPM_STS = 0x0C,
235 SAW3_AVS_STS = 0x10,
236 SAW3_PMIC_STS = 0x14,
237 SAW3_RST = 0x18,
238 SAW3_VCTL = 0x1C,
239 SAW3_AVS_CTL = 0x20,
240 SAW3_AVS_LIMIT = 0x24,
241 SAW3_AVS_DLY = 0x28,
242 SAW3_AVS_HYSTERESIS = 0x2C,
243 SAW3_SPM_STS2 = 0x38,
244 SAW3_SPM_PMIC_DATA_3 = 0x4C,
245 SAW3_VERSION = 0xFD0,
246};
247
248/* Used for indexing into ctrl_reg. These are offsets from 0x40 */
249enum spmi_common_control_register_index {
250 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0,
251 SPMI_COMMON_IDX_VOLTAGE_SET = 1,
252 SPMI_COMMON_IDX_MODE = 5,
253 SPMI_COMMON_IDX_ENABLE = 6,
254};
255
256/* Common regulator control register layout */
257#define SPMI_COMMON_ENABLE_MASK 0x80
258#define SPMI_COMMON_ENABLE 0x80
259#define SPMI_COMMON_DISABLE 0x00
260#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08
261#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04
262#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02
263#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01
264#define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f
265
266/* Common regulator mode register layout */
267#define SPMI_COMMON_MODE_HPM_MASK 0x80
268#define SPMI_COMMON_MODE_AUTO_MASK 0x40
269#define SPMI_COMMON_MODE_BYPASS_MASK 0x20
270#define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10
271#define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08
272#define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04
273#define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02
274#define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01
275#define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f
276
277#define SPMI_FTSMPS426_MODE_BYPASS_MASK 3
278#define SPMI_FTSMPS426_MODE_RETENTION_MASK 4
279#define SPMI_FTSMPS426_MODE_LPM_MASK 5
280#define SPMI_FTSMPS426_MODE_AUTO_MASK 6
281#define SPMI_FTSMPS426_MODE_HPM_MASK 7
282
283#define SPMI_FTSMPS426_MODE_MASK 0x07
284
285/* Third common regulator mode register values */
286#define SPMI_HFSMPS_MODE_BYPASS_MASK 2
287#define SPMI_HFSMPS_MODE_RETENTION_MASK 3
288#define SPMI_HFSMPS_MODE_LPM_MASK 4
289#define SPMI_HFSMPS_MODE_AUTO_MASK 6
290#define SPMI_HFSMPS_MODE_HPM_MASK 7
291
292#define SPMI_HFSMPS_MODE_MASK 0x07
293
294/* Common regulator pull down control register layout */
295#define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80
296
297/* LDO regulator current limit control register layout */
298#define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80
299
300/* LDO regulator soft start control register layout */
301#define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80
302
303/* VS regulator over current protection control register layout */
304#define SPMI_VS_OCP_OVERRIDE 0x01
305#define SPMI_VS_OCP_NO_OVERRIDE 0x00
306
307/* VS regulator soft start control register layout */
308#define SPMI_VS_SOFT_START_ENABLE_MASK 0x80
309#define SPMI_VS_SOFT_START_SEL_MASK 0x03
310
311/* Boost regulator current limit control register layout */
312#define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80
313#define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07
314
315#define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10
316#define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30
317#define SPMI_VS_OCP_FALL_DELAY_US 90
318#define SPMI_VS_OCP_FAULT_DELAY_US 20000
319
320#define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18
321#define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3
322#define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07
323#define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0
324
325/* Clock rate in kHz of the FTSMPS regulator reference clock. */
326#define SPMI_FTSMPS_CLOCK_RATE 19200
327
328/* Minimum voltage stepper delay for each step. */
329#define SPMI_FTSMPS_STEP_DELAY 8
330#define SPMI_DEFAULT_STEP_DELAY 20
331
332/*
333 * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to
334 * adjust the step rate in order to account for oscillator variance.
335 */
336#define SPMI_FTSMPS_STEP_MARGIN_NUM 4
337#define SPMI_FTSMPS_STEP_MARGIN_DEN 5
338
339/* slew_rate has units of uV/us. */
340#define SPMI_HFSMPS_SLEW_RATE_38p4 38400
341
342#define SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK 0x03
343#define SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT 0
344
345/* Clock rate in kHz of the FTSMPS426 regulator reference clock. */
346#define SPMI_FTSMPS426_CLOCK_RATE 4800
347
348#define SPMI_HFS430_CLOCK_RATE 1600
349
350/* Minimum voltage stepper delay for each step. */
351#define SPMI_FTSMPS426_STEP_DELAY 2
352
353/*
354 * The ratio SPMI_FTSMPS426_STEP_MARGIN_NUM/SPMI_FTSMPS426_STEP_MARGIN_DEN is
355 * used to adjust the step rate in order to account for oscillator variance.
356 */
357#define SPMI_FTSMPS426_STEP_MARGIN_NUM 10
358#define SPMI_FTSMPS426_STEP_MARGIN_DEN 11
359
360
361/* VSET value to decide the range of ULT SMPS */
362#define ULT_SMPS_RANGE_SPLIT 0x60
363
364/**
365 * struct spmi_voltage_range - regulator set point voltage mapping description
366 * @min_uV: Minimum programmable output voltage resulting from
367 * set point register value 0x00
368 * @max_uV: Maximum programmable output voltage
369 * @step_uV: Output voltage increase resulting from the set point
370 * register value increasing by 1
371 * @set_point_min_uV: Minimum allowed voltage
372 * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order
373 * to pick which range should be used in the case of
374 * overlapping set points.
375 * @n_voltages: Number of preferred voltage set points present in this
376 * range
377 * @range_sel: Voltage range register value corresponding to this range
378 *
379 * The following relationships must be true for the values used in this struct:
380 * (max_uV - min_uV) % step_uV == 0
381 * (set_point_min_uV - min_uV) % step_uV == 0*
382 * (set_point_max_uV - min_uV) % step_uV == 0*
383 * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1
384 *
385 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to
386 * specify that the voltage range has meaning, but is not preferred.
387 */
388struct spmi_voltage_range {
389 int min_uV;
390 int max_uV;
391 int step_uV;
392 int set_point_min_uV;
393 int set_point_max_uV;
394 unsigned n_voltages;
395 u8 range_sel;
396};
397
398/*
399 * The ranges specified in the spmi_voltage_set_points struct must be listed
400 * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV.
401 */
402struct spmi_voltage_set_points {
403 struct spmi_voltage_range *range;
404 int count;
405 unsigned n_voltages;
406};
407
408struct spmi_regulator {
409 struct regulator_desc desc;
410 struct device *dev;
411 struct delayed_work ocp_work;
412 struct regmap *regmap;
413 struct spmi_voltage_set_points *set_points;
414 enum spmi_regulator_logical_type logical_type;
415 int ocp_irq;
416 int ocp_count;
417 int ocp_max_retries;
418 int ocp_retry_delay_ms;
419 int hpm_min_load;
420 int slew_rate;
421 ktime_t vs_enable_time;
422 u16 base;
423 struct list_head node;
424};
425
426struct spmi_regulator_mapping {
427 enum spmi_regulator_type type;
428 enum spmi_regulator_subtype subtype;
429 enum spmi_regulator_logical_type logical_type;
430 u32 revision_min;
431 u32 revision_max;
432 const struct regulator_ops *ops;
433 struct spmi_voltage_set_points *set_points;
434 int hpm_min_load;
435};
436
437struct spmi_regulator_data {
438 const char *name;
439 u16 base;
440 const char *supply;
441 const char *ocp;
442 u16 force_type;
443};
444
445#define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \
446 _logical_type, _ops_val, _set_points_val, _hpm_min_load) \
447 { \
448 .type = SPMI_REGULATOR_TYPE_##_type, \
449 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
450 .revision_min = _dig_major_min, \
451 .revision_max = _dig_major_max, \
452 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \
453 .ops = &spmi_##_ops_val##_ops, \
454 .set_points = &_set_points_val##_set_points, \
455 .hpm_min_load = _hpm_min_load, \
456 }
457
458#define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \
459 { \
460 .type = SPMI_REGULATOR_TYPE_VS, \
461 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
462 .revision_min = _dig_major_min, \
463 .revision_max = _dig_major_max, \
464 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \
465 .ops = &spmi_vs_ops, \
466 }
467
468#define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \
469 _set_point_max_uV, _max_uV, _step_uV) \
470 { \
471 .min_uV = _min_uV, \
472 .max_uV = _max_uV, \
473 .set_point_min_uV = _set_point_min_uV, \
474 .set_point_max_uV = _set_point_max_uV, \
475 .step_uV = _step_uV, \
476 .range_sel = _range_sel, \
477 }
478
479#define DEFINE_SPMI_SET_POINTS(name) \
480struct spmi_voltage_set_points name##_set_points = { \
481 .range = name##_ranges, \
482 .count = ARRAY_SIZE(name##_ranges), \
483}
484
485/*
486 * These tables contain the physically available PMIC regulator voltage setpoint
487 * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed
488 * to ensure that the setpoints available to software are monotonically
489 * increasing and unique. The set_voltage callback functions expect these
490 * properties to hold.
491 */
492static struct spmi_voltage_range pldo_ranges[] = {
493 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
494 SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000),
495 SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000),
496};
497
498static struct spmi_voltage_range nldo1_ranges[] = {
499 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
500};
501
502static struct spmi_voltage_range nldo2_ranges[] = {
503 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500),
504 SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250),
505 SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500),
506};
507
508static struct spmi_voltage_range nldo3_ranges[] = {
509 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
510 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500),
511 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500),
512};
513
514static struct spmi_voltage_range ln_ldo_ranges[] = {
515 SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000),
516 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000),
517};
518
519static struct spmi_voltage_range smps_ranges[] = {
520 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
521 SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000),
522};
523
524static struct spmi_voltage_range ftsmps_ranges[] = {
525 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000),
526 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000),
527};
528
529static struct spmi_voltage_range ftsmps2p5_ranges[] = {
530 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000),
531 SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000),
532};
533
534static struct spmi_voltage_range ftsmps426_ranges[] = {
535 SPMI_VOLTAGE_RANGE(0, 0, 320000, 1352000, 1352000, 4000),
536};
537
538static struct spmi_voltage_range boost_ranges[] = {
539 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000),
540};
541
542static struct spmi_voltage_range boost_byp_ranges[] = {
543 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000),
544};
545
546static struct spmi_voltage_range ult_lo_smps_ranges[] = {
547 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
548 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000),
549};
550
551static struct spmi_voltage_range ult_ho_smps_ranges[] = {
552 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000),
553};
554
555static struct spmi_voltage_range ult_nldo_ranges[] = {
556 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
557};
558
559static struct spmi_voltage_range ult_pldo_ranges[] = {
560 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500),
561};
562
563static struct spmi_voltage_range pldo660_ranges[] = {
564 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 3544000, 3544000, 8000),
565};
566
567static struct spmi_voltage_range nldo660_ranges[] = {
568 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
569};
570
571static struct spmi_voltage_range ht_lvpldo_ranges[] = {
572 SPMI_VOLTAGE_RANGE(0, 1504000, 1504000, 2000000, 2000000, 8000),
573};
574
575static struct spmi_voltage_range ht_nldo_ranges[] = {
576 SPMI_VOLTAGE_RANGE(0, 312000, 312000, 1304000, 1304000, 8000),
577};
578
579static struct spmi_voltage_range hfs430_ranges[] = {
580 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 2040000, 2040000, 8000),
581};
582
583static struct spmi_voltage_range ht_p150_ranges[] = {
584 SPMI_VOLTAGE_RANGE(0, 1616000, 1616000, 3304000, 3304000, 8000),
585};
586
587static struct spmi_voltage_range ht_p600_ranges[] = {
588 SPMI_VOLTAGE_RANGE(0, 1704000, 1704000, 1896000, 1896000, 8000),
589};
590
591static struct spmi_voltage_range nldo_510_ranges[] = {
592 SPMI_VOLTAGE_RANGE(0, 320000, 320000, 1304000, 1304000, 8000),
593};
594
595static struct spmi_voltage_range ftsmps510_ranges[] = {
596 SPMI_VOLTAGE_RANGE(0, 300000, 300000, 1372000, 1372000, 4000),
597};
598
599static DEFINE_SPMI_SET_POINTS(pldo);
600static DEFINE_SPMI_SET_POINTS(nldo1);
601static DEFINE_SPMI_SET_POINTS(nldo2);
602static DEFINE_SPMI_SET_POINTS(nldo3);
603static DEFINE_SPMI_SET_POINTS(ln_ldo);
604static DEFINE_SPMI_SET_POINTS(smps);
605static DEFINE_SPMI_SET_POINTS(ftsmps);
606static DEFINE_SPMI_SET_POINTS(ftsmps2p5);
607static DEFINE_SPMI_SET_POINTS(ftsmps426);
608static DEFINE_SPMI_SET_POINTS(boost);
609static DEFINE_SPMI_SET_POINTS(boost_byp);
610static DEFINE_SPMI_SET_POINTS(ult_lo_smps);
611static DEFINE_SPMI_SET_POINTS(ult_ho_smps);
612static DEFINE_SPMI_SET_POINTS(ult_nldo);
613static DEFINE_SPMI_SET_POINTS(ult_pldo);
614static DEFINE_SPMI_SET_POINTS(pldo660);
615static DEFINE_SPMI_SET_POINTS(nldo660);
616static DEFINE_SPMI_SET_POINTS(ht_lvpldo);
617static DEFINE_SPMI_SET_POINTS(ht_nldo);
618static DEFINE_SPMI_SET_POINTS(hfs430);
619static DEFINE_SPMI_SET_POINTS(ht_p150);
620static DEFINE_SPMI_SET_POINTS(ht_p600);
621static DEFINE_SPMI_SET_POINTS(nldo_510);
622static DEFINE_SPMI_SET_POINTS(ftsmps510);
623
624static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
625 int len)
626{
627 return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len);
628}
629
630static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr,
631 u8 *buf, int len)
632{
633 return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len);
634}
635
636static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val,
637 u8 mask)
638{
639 return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val);
640}
641
642static int spmi_regulator_vs_enable(struct regulator_dev *rdev)
643{
644 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
645
646 if (vreg->ocp_irq) {
647 vreg->ocp_count = 0;
648 vreg->vs_enable_time = ktime_get();
649 }
650
651 return regulator_enable_regmap(rdev);
652}
653
654static int spmi_regulator_vs_ocp(struct regulator_dev *rdev, int lim_uA,
655 int severity, bool enable)
656{
657 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
658 u8 reg = SPMI_VS_OCP_OVERRIDE;
659
660 if (lim_uA || !enable || severity != REGULATOR_SEVERITY_PROT)
661 return -EINVAL;
662
663 return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1);
664}
665
666static int spmi_regulator_select_voltage(struct spmi_regulator *vreg,
667 int min_uV, int max_uV)
668{
669 const struct spmi_voltage_range *range;
670 int uV = min_uV;
671 int lim_min_uV, lim_max_uV, i, range_id, range_max_uV;
672 int selector, voltage_sel;
673
674 /* Check if request voltage is outside of physically settable range. */
675 lim_min_uV = vreg->set_points->range[0].set_point_min_uV;
676 lim_max_uV =
677 vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV;
678
679 if (uV < lim_min_uV && max_uV >= lim_min_uV)
680 uV = lim_min_uV;
681
682 if (uV < lim_min_uV || uV > lim_max_uV) {
683 dev_err(vreg->dev,
684 "request v=[%d, %d] is outside possible v=[%d, %d]\n",
685 min_uV, max_uV, lim_min_uV, lim_max_uV);
686 return -EINVAL;
687 }
688
689 /* Find the range which uV is inside of. */
690 for (i = vreg->set_points->count - 1; i > 0; i--) {
691 range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV;
692 if (uV > range_max_uV && range_max_uV > 0)
693 break;
694 }
695
696 range_id = i;
697 range = &vreg->set_points->range[range_id];
698
699 /*
700 * Force uV to be an allowed set point by applying a ceiling function to
701 * the uV value.
702 */
703 voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
704 uV = voltage_sel * range->step_uV + range->min_uV;
705
706 if (uV > max_uV) {
707 dev_err(vreg->dev,
708 "request v=[%d, %d] cannot be met by any set point; "
709 "next set point: %d\n",
710 min_uV, max_uV, uV);
711 return -EINVAL;
712 }
713
714 selector = 0;
715 for (i = 0; i < range_id; i++)
716 selector += vreg->set_points->range[i].n_voltages;
717 selector += (uV - range->set_point_min_uV) / range->step_uV;
718
719 return selector;
720}
721
722static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg,
723 unsigned selector, u8 *range_sel,
724 u8 *voltage_sel)
725{
726 const struct spmi_voltage_range *range, *end;
727 unsigned offset;
728
729 range = vreg->set_points->range;
730 end = range + vreg->set_points->count;
731
732 for (; range < end; range++) {
733 if (selector < range->n_voltages) {
734 /*
735 * hardware selectors between set point min and real
736 * min are invalid so we ignore them
737 */
738 offset = range->set_point_min_uV - range->min_uV;
739 offset /= range->step_uV;
740 *voltage_sel = selector + offset;
741 *range_sel = range->range_sel;
742 return 0;
743 }
744
745 selector -= range->n_voltages;
746 }
747
748 return -EINVAL;
749}
750
751static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel,
752 const struct spmi_voltage_range *range)
753{
754 unsigned sw_sel = 0;
755 unsigned offset, max_hw_sel;
756 const struct spmi_voltage_range *r = vreg->set_points->range;
757 const struct spmi_voltage_range *end = r + vreg->set_points->count;
758
759 for (; r < end; r++) {
760 if (r == range && range->n_voltages) {
761 /*
762 * hardware selectors between set point min and real
763 * min and between set point max and real max are
764 * invalid so we return an error if they're
765 * programmed into the hardware
766 */
767 offset = range->set_point_min_uV - range->min_uV;
768 offset /= range->step_uV;
769 if (hw_sel < offset)
770 return -EINVAL;
771
772 max_hw_sel = range->set_point_max_uV - range->min_uV;
773 max_hw_sel /= range->step_uV;
774 if (hw_sel > max_hw_sel)
775 return -EINVAL;
776
777 return sw_sel + hw_sel - offset;
778 }
779 sw_sel += r->n_voltages;
780 }
781
782 return -EINVAL;
783}
784
785static const struct spmi_voltage_range *
786spmi_regulator_find_range(struct spmi_regulator *vreg)
787{
788 u8 range_sel;
789 const struct spmi_voltage_range *range, *end;
790
791 range = vreg->set_points->range;
792 end = range + vreg->set_points->count;
793
794 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1);
795
796 for (; range < end; range++)
797 if (range->range_sel == range_sel)
798 return range;
799
800 return NULL;
801}
802
803static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
804 int min_uV, int max_uV)
805{
806 const struct spmi_voltage_range *range;
807 int uV = min_uV;
808 int i, selector;
809
810 range = spmi_regulator_find_range(vreg);
811 if (!range)
812 goto different_range;
813
814 if (uV < range->min_uV && max_uV >= range->min_uV)
815 uV = range->min_uV;
816
817 if (uV < range->min_uV || uV > range->max_uV) {
818 /* Current range doesn't support the requested voltage. */
819 goto different_range;
820 }
821
822 /*
823 * Force uV to be an allowed set point by applying a ceiling function to
824 * the uV value.
825 */
826 uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
827 uV = uV * range->step_uV + range->min_uV;
828
829 if (uV > max_uV) {
830 /*
831 * No set point in the current voltage range is within the
832 * requested min_uV to max_uV range.
833 */
834 goto different_range;
835 }
836
837 selector = 0;
838 for (i = 0; i < vreg->set_points->count; i++) {
839 if (uV >= vreg->set_points->range[i].set_point_min_uV
840 && uV <= vreg->set_points->range[i].set_point_max_uV) {
841 selector +=
842 (uV - vreg->set_points->range[i].set_point_min_uV)
843 / vreg->set_points->range[i].step_uV;
844 break;
845 }
846
847 selector += vreg->set_points->range[i].n_voltages;
848 }
849
850 if (selector >= vreg->set_points->n_voltages)
851 goto different_range;
852
853 return selector;
854
855different_range:
856 return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
857}
858
859static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev,
860 int min_uV, int max_uV)
861{
862 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
863
864 /*
865 * Favor staying in the current voltage range if possible. This avoids
866 * voltage spikes that occur when changing the voltage range.
867 */
868 return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV);
869}
870
871static int
872spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector)
873{
874 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
875 int ret;
876 u8 buf[2];
877 u8 range_sel, voltage_sel;
878
879 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
880 if (ret)
881 return ret;
882
883 buf[0] = range_sel;
884 buf[1] = voltage_sel;
885 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2);
886}
887
888static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
889 unsigned selector);
890
891static int spmi_regulator_ftsmps426_set_voltage(struct regulator_dev *rdev,
892 unsigned selector)
893{
894 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
895 u8 buf[2];
896 int mV;
897
898 mV = spmi_regulator_common_list_voltage(rdev, selector) / 1000;
899
900 buf[0] = mV & 0xff;
901 buf[1] = mV >> 8;
902 return spmi_vreg_write(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
903}
904
905static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
906 unsigned int old_selector, unsigned int new_selector)
907{
908 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
909 int diff_uV;
910
911 diff_uV = abs(spmi_regulator_common_list_voltage(rdev, new_selector) -
912 spmi_regulator_common_list_voltage(rdev, old_selector));
913
914 return DIV_ROUND_UP(diff_uV, vreg->slew_rate);
915}
916
917static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev)
918{
919 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
920 const struct spmi_voltage_range *range;
921 u8 voltage_sel;
922
923 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
924
925 range = spmi_regulator_find_range(vreg);
926 if (!range)
927 return -EINVAL;
928
929 return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
930}
931
932static int spmi_regulator_ftsmps426_get_voltage(struct regulator_dev *rdev)
933{
934 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
935 const struct spmi_voltage_range *range;
936 u8 buf[2];
937 int uV;
938
939 spmi_vreg_read(vreg, SPMI_FTSMPS426_REG_VOLTAGE_LSB, buf, 2);
940
941 uV = (((unsigned int)buf[1] << 8) | (unsigned int)buf[0]) * 1000;
942 range = vreg->set_points->range;
943
944 return (uV - range->set_point_min_uV) / range->step_uV;
945}
946
947static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev,
948 int min_uV, int max_uV)
949{
950 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
951
952 return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
953}
954
955static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev,
956 unsigned selector)
957{
958 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
959 u8 sel = selector;
960
961 /*
962 * Certain types of regulators do not have a range select register so
963 * only voltage set register needs to be written.
964 */
965 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1);
966}
967
968static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev)
969{
970 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
971 u8 selector;
972 int ret;
973
974 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1);
975 if (ret)
976 return ret;
977
978 return selector;
979}
980
981static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev,
982 unsigned selector)
983{
984 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
985 int ret;
986 u8 range_sel, voltage_sel;
987
988 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
989 if (ret)
990 return ret;
991
992 /*
993 * Calculate VSET based on range
994 * In case of range 0: voltage_sel is a 7 bit value, can be written
995 * witout any modification.
996 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to
997 * [011].
998 */
999 if (range_sel == 1)
1000 voltage_sel |= ULT_SMPS_RANGE_SPLIT;
1001
1002 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET,
1003 voltage_sel, 0xff);
1004}
1005
1006static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev)
1007{
1008 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1009 const struct spmi_voltage_range *range;
1010 u8 voltage_sel;
1011
1012 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
1013
1014 range = spmi_regulator_find_range(vreg);
1015 if (!range)
1016 return -EINVAL;
1017
1018 if (range->range_sel == 1)
1019 voltage_sel &= ~ULT_SMPS_RANGE_SPLIT;
1020
1021 return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
1022}
1023
1024static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
1025 unsigned selector)
1026{
1027 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1028 int uV = 0;
1029 int i;
1030
1031 if (selector >= vreg->set_points->n_voltages)
1032 return 0;
1033
1034 for (i = 0; i < vreg->set_points->count; i++) {
1035 if (selector < vreg->set_points->range[i].n_voltages) {
1036 uV = selector * vreg->set_points->range[i].step_uV
1037 + vreg->set_points->range[i].set_point_min_uV;
1038 break;
1039 }
1040
1041 selector -= vreg->set_points->range[i].n_voltages;
1042 }
1043
1044 return uV;
1045}
1046
1047static int
1048spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable)
1049{
1050 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1051 u8 mask = SPMI_COMMON_MODE_BYPASS_MASK;
1052 u8 val = 0;
1053
1054 if (enable)
1055 val = mask;
1056
1057 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1058}
1059
1060static int
1061spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable)
1062{
1063 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1064 u8 val;
1065 int ret;
1066
1067 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1);
1068 *enable = val & SPMI_COMMON_MODE_BYPASS_MASK;
1069
1070 return ret;
1071}
1072
1073static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev)
1074{
1075 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1076 u8 reg;
1077
1078 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1);
1079
1080 reg &= SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
1081
1082 switch (reg) {
1083 case SPMI_COMMON_MODE_HPM_MASK:
1084 return REGULATOR_MODE_NORMAL;
1085 case SPMI_COMMON_MODE_AUTO_MASK:
1086 return REGULATOR_MODE_FAST;
1087 default:
1088 return REGULATOR_MODE_IDLE;
1089 }
1090}
1091
1092static unsigned int spmi_regulator_ftsmps426_get_mode(struct regulator_dev *rdev)
1093{
1094 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1095 u8 reg;
1096
1097 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1);
1098
1099 switch (reg) {
1100 case SPMI_FTSMPS426_MODE_HPM_MASK:
1101 return REGULATOR_MODE_NORMAL;
1102 case SPMI_FTSMPS426_MODE_AUTO_MASK:
1103 return REGULATOR_MODE_FAST;
1104 default:
1105 return REGULATOR_MODE_IDLE;
1106 }
1107}
1108
1109static unsigned int spmi_regulator_hfsmps_get_mode(struct regulator_dev *rdev)
1110{
1111 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1112 u8 reg;
1113
1114 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1);
1115
1116 switch (reg) {
1117 case SPMI_HFSMPS_MODE_HPM_MASK:
1118 return REGULATOR_MODE_NORMAL;
1119 case SPMI_HFSMPS_MODE_AUTO_MASK:
1120 return REGULATOR_MODE_FAST;
1121 default:
1122 return REGULATOR_MODE_IDLE;
1123 }
1124}
1125
1126static int
1127spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode)
1128{
1129 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1130 u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
1131 u8 val;
1132
1133 switch (mode) {
1134 case REGULATOR_MODE_NORMAL:
1135 val = SPMI_COMMON_MODE_HPM_MASK;
1136 break;
1137 case REGULATOR_MODE_FAST:
1138 val = SPMI_COMMON_MODE_AUTO_MASK;
1139 break;
1140 default:
1141 val = 0;
1142 break;
1143 }
1144
1145 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1146}
1147
1148static int
1149spmi_regulator_ftsmps426_set_mode(struct regulator_dev *rdev, unsigned int mode)
1150{
1151 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1152 u8 mask = SPMI_FTSMPS426_MODE_MASK;
1153 u8 val;
1154
1155 switch (mode) {
1156 case REGULATOR_MODE_NORMAL:
1157 val = SPMI_FTSMPS426_MODE_HPM_MASK;
1158 break;
1159 case REGULATOR_MODE_FAST:
1160 val = SPMI_FTSMPS426_MODE_AUTO_MASK;
1161 break;
1162 case REGULATOR_MODE_IDLE:
1163 val = SPMI_FTSMPS426_MODE_LPM_MASK;
1164 break;
1165 default:
1166 return -EINVAL;
1167 }
1168
1169 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1170}
1171
1172static int
1173spmi_regulator_hfsmps_set_mode(struct regulator_dev *rdev, unsigned int mode)
1174{
1175 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1176 u8 mask = SPMI_HFSMPS_MODE_MASK;
1177 u8 val;
1178
1179 switch (mode) {
1180 case REGULATOR_MODE_NORMAL:
1181 val = SPMI_HFSMPS_MODE_HPM_MASK;
1182 break;
1183 case REGULATOR_MODE_FAST:
1184 val = SPMI_HFSMPS_MODE_AUTO_MASK;
1185 break;
1186 case REGULATOR_MODE_IDLE:
1187 val = vreg->logical_type ==
1188 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3 ?
1189 SPMI_HFSMPS_MODE_RETENTION_MASK :
1190 SPMI_HFSMPS_MODE_LPM_MASK;
1191 break;
1192 default:
1193 return -EINVAL;
1194 }
1195
1196 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
1197}
1198
1199static int
1200spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA)
1201{
1202 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1203 unsigned int mode;
1204
1205 if (load_uA >= vreg->hpm_min_load)
1206 mode = REGULATOR_MODE_NORMAL;
1207 else
1208 mode = REGULATOR_MODE_IDLE;
1209
1210 return spmi_regulator_common_set_mode(rdev, mode);
1211}
1212
1213static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev)
1214{
1215 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1216 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK;
1217
1218 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN,
1219 mask, mask);
1220}
1221
1222static int spmi_regulator_hfsmps_set_pull_down(struct regulator_dev *rdev)
1223{
1224 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1225 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK;
1226
1227 return spmi_vreg_update_bits(vreg, SPMI_HFSMPS_REG_PULL_DOWN,
1228 mask, mask);
1229}
1230
1231static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev)
1232{
1233 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1234 unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK;
1235
1236 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START,
1237 mask, mask);
1238}
1239
1240static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA)
1241{
1242 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1243 enum spmi_regulator_logical_type type = vreg->logical_type;
1244 unsigned int current_reg;
1245 u8 reg;
1246 u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK |
1247 SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
1248 int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500;
1249
1250 if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST)
1251 current_reg = SPMI_BOOST_REG_CURRENT_LIMIT;
1252 else
1253 current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT;
1254
1255 if (ilim_uA > max || ilim_uA <= 0)
1256 return -EINVAL;
1257
1258 reg = (ilim_uA - 1) / 500;
1259 reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
1260
1261 return spmi_vreg_update_bits(vreg, current_reg, reg, mask);
1262}
1263
1264static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg)
1265{
1266 int ret;
1267
1268 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
1269 SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK);
1270
1271 vreg->vs_enable_time = ktime_get();
1272
1273 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
1274 SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK);
1275
1276 return ret;
1277}
1278
1279static void spmi_regulator_vs_ocp_work(struct work_struct *work)
1280{
1281 struct delayed_work *dwork = to_delayed_work(work);
1282 struct spmi_regulator *vreg
1283 = container_of(dwork, struct spmi_regulator, ocp_work);
1284
1285 spmi_regulator_vs_clear_ocp(vreg);
1286}
1287
1288static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data)
1289{
1290 struct spmi_regulator *vreg = data;
1291 ktime_t ocp_irq_time;
1292 s64 ocp_trigger_delay_us;
1293
1294 ocp_irq_time = ktime_get();
1295 ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time,
1296 vreg->vs_enable_time);
1297
1298 /*
1299 * Reset the OCP count if there is a large delay between switch enable
1300 * and when OCP triggers. This is indicative of a hotplug event as
1301 * opposed to a fault.
1302 */
1303 if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US)
1304 vreg->ocp_count = 0;
1305
1306 /* Wait for switch output to settle back to 0 V after OCP triggered. */
1307 udelay(SPMI_VS_OCP_FALL_DELAY_US);
1308
1309 vreg->ocp_count++;
1310
1311 if (vreg->ocp_count == 1) {
1312 /* Immediately clear the over current condition. */
1313 spmi_regulator_vs_clear_ocp(vreg);
1314 } else if (vreg->ocp_count <= vreg->ocp_max_retries) {
1315 /* Schedule the over current clear task to run later. */
1316 schedule_delayed_work(&vreg->ocp_work,
1317 msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1);
1318 } else {
1319 dev_err(vreg->dev,
1320 "OCP triggered %d times; no further retries\n",
1321 vreg->ocp_count);
1322 }
1323
1324 return IRQ_HANDLED;
1325}
1326
1327#define SAW3_VCTL_DATA_MASK 0xFF
1328#define SAW3_VCTL_CLEAR_MASK 0x700FF
1329#define SAW3_AVS_CTL_EN_MASK 0x1
1330#define SAW3_AVS_CTL_TGGL_MASK 0x8000000
1331#define SAW3_AVS_CTL_CLEAR_MASK 0x7efc00
1332
1333static struct regmap *saw_regmap;
1334
1335static void spmi_saw_set_vdd(void *data)
1336{
1337 u32 vctl, data3, avs_ctl, pmic_sts;
1338 bool avs_enabled = false;
1339 unsigned long timeout;
1340 u8 voltage_sel = *(u8 *)data;
1341
1342 regmap_read(saw_regmap, SAW3_AVS_CTL, &avs_ctl);
1343 regmap_read(saw_regmap, SAW3_VCTL, &vctl);
1344 regmap_read(saw_regmap, SAW3_SPM_PMIC_DATA_3, &data3);
1345
1346 /* select the band */
1347 vctl &= ~SAW3_VCTL_CLEAR_MASK;
1348 vctl |= (u32)voltage_sel;
1349
1350 data3 &= ~SAW3_VCTL_CLEAR_MASK;
1351 data3 |= (u32)voltage_sel;
1352
1353 /* If AVS is enabled, switch it off during the voltage change */
1354 avs_enabled = SAW3_AVS_CTL_EN_MASK & avs_ctl;
1355 if (avs_enabled) {
1356 avs_ctl &= ~SAW3_AVS_CTL_TGGL_MASK;
1357 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
1358 }
1359
1360 regmap_write(saw_regmap, SAW3_RST, 1);
1361 regmap_write(saw_regmap, SAW3_VCTL, vctl);
1362 regmap_write(saw_regmap, SAW3_SPM_PMIC_DATA_3, data3);
1363
1364 timeout = jiffies + usecs_to_jiffies(100);
1365 do {
1366 regmap_read(saw_regmap, SAW3_PMIC_STS, &pmic_sts);
1367 pmic_sts &= SAW3_VCTL_DATA_MASK;
1368 if (pmic_sts == (u32)voltage_sel)
1369 break;
1370
1371 cpu_relax();
1372
1373 } while (time_before(jiffies, timeout));
1374
1375 /* After successful voltage change, switch the AVS back on */
1376 if (avs_enabled) {
1377 pmic_sts &= 0x3f;
1378 avs_ctl &= ~SAW3_AVS_CTL_CLEAR_MASK;
1379 avs_ctl |= ((pmic_sts - 4) << 10);
1380 avs_ctl |= (pmic_sts << 17);
1381 avs_ctl |= SAW3_AVS_CTL_TGGL_MASK;
1382 regmap_write(saw_regmap, SAW3_AVS_CTL, avs_ctl);
1383 }
1384}
1385
1386static int
1387spmi_regulator_saw_set_voltage(struct regulator_dev *rdev, unsigned selector)
1388{
1389 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
1390 int ret;
1391 u8 range_sel, voltage_sel;
1392
1393 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
1394 if (ret)
1395 return ret;
1396
1397 if (0 != range_sel) {
1398 dev_dbg(&rdev->dev, "range_sel = %02X voltage_sel = %02X", \
1399 range_sel, voltage_sel);
1400 return -EINVAL;
1401 }
1402
1403 /* Always do the SAW register writes on the first CPU */
1404 return smp_call_function_single(0, spmi_saw_set_vdd, \
1405 &voltage_sel, true);
1406}
1407
1408static struct regulator_ops spmi_saw_ops = {};
1409
1410static const struct regulator_ops spmi_smps_ops = {
1411 .enable = regulator_enable_regmap,
1412 .disable = regulator_disable_regmap,
1413 .is_enabled = regulator_is_enabled_regmap,
1414 .set_voltage_sel = spmi_regulator_common_set_voltage,
1415 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1416 .get_voltage_sel = spmi_regulator_common_get_voltage,
1417 .map_voltage = spmi_regulator_common_map_voltage,
1418 .list_voltage = spmi_regulator_common_list_voltage,
1419 .set_mode = spmi_regulator_common_set_mode,
1420 .get_mode = spmi_regulator_common_get_mode,
1421 .set_load = spmi_regulator_common_set_load,
1422 .set_pull_down = spmi_regulator_common_set_pull_down,
1423};
1424
1425static const struct regulator_ops spmi_ldo_ops = {
1426 .enable = regulator_enable_regmap,
1427 .disable = regulator_disable_regmap,
1428 .is_enabled = regulator_is_enabled_regmap,
1429 .set_voltage_sel = spmi_regulator_common_set_voltage,
1430 .get_voltage_sel = spmi_regulator_common_get_voltage,
1431 .map_voltage = spmi_regulator_common_map_voltage,
1432 .list_voltage = spmi_regulator_common_list_voltage,
1433 .set_mode = spmi_regulator_common_set_mode,
1434 .get_mode = spmi_regulator_common_get_mode,
1435 .set_load = spmi_regulator_common_set_load,
1436 .set_bypass = spmi_regulator_common_set_bypass,
1437 .get_bypass = spmi_regulator_common_get_bypass,
1438 .set_pull_down = spmi_regulator_common_set_pull_down,
1439 .set_soft_start = spmi_regulator_common_set_soft_start,
1440};
1441
1442static const struct regulator_ops spmi_ln_ldo_ops = {
1443 .enable = regulator_enable_regmap,
1444 .disable = regulator_disable_regmap,
1445 .is_enabled = regulator_is_enabled_regmap,
1446 .set_voltage_sel = spmi_regulator_common_set_voltage,
1447 .get_voltage_sel = spmi_regulator_common_get_voltage,
1448 .map_voltage = spmi_regulator_common_map_voltage,
1449 .list_voltage = spmi_regulator_common_list_voltage,
1450 .set_bypass = spmi_regulator_common_set_bypass,
1451 .get_bypass = spmi_regulator_common_get_bypass,
1452};
1453
1454static const struct regulator_ops spmi_vs_ops = {
1455 .enable = spmi_regulator_vs_enable,
1456 .disable = regulator_disable_regmap,
1457 .is_enabled = regulator_is_enabled_regmap,
1458 .set_pull_down = spmi_regulator_common_set_pull_down,
1459 .set_soft_start = spmi_regulator_common_set_soft_start,
1460 .set_over_current_protection = spmi_regulator_vs_ocp,
1461 .set_mode = spmi_regulator_common_set_mode,
1462 .get_mode = spmi_regulator_common_get_mode,
1463};
1464
1465static const struct regulator_ops spmi_boost_ops = {
1466 .enable = regulator_enable_regmap,
1467 .disable = regulator_disable_regmap,
1468 .is_enabled = regulator_is_enabled_regmap,
1469 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1470 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1471 .map_voltage = spmi_regulator_single_map_voltage,
1472 .list_voltage = spmi_regulator_common_list_voltage,
1473 .set_input_current_limit = spmi_regulator_set_ilim,
1474};
1475
1476static const struct regulator_ops spmi_ftsmps_ops = {
1477 .enable = regulator_enable_regmap,
1478 .disable = regulator_disable_regmap,
1479 .is_enabled = regulator_is_enabled_regmap,
1480 .set_voltage_sel = spmi_regulator_common_set_voltage,
1481 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1482 .get_voltage_sel = spmi_regulator_common_get_voltage,
1483 .map_voltage = spmi_regulator_common_map_voltage,
1484 .list_voltage = spmi_regulator_common_list_voltage,
1485 .set_mode = spmi_regulator_common_set_mode,
1486 .get_mode = spmi_regulator_common_get_mode,
1487 .set_load = spmi_regulator_common_set_load,
1488 .set_pull_down = spmi_regulator_common_set_pull_down,
1489};
1490
1491static const struct regulator_ops spmi_ult_lo_smps_ops = {
1492 .enable = regulator_enable_regmap,
1493 .disable = regulator_disable_regmap,
1494 .is_enabled = regulator_is_enabled_regmap,
1495 .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage,
1496 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1497 .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage,
1498 .list_voltage = spmi_regulator_common_list_voltage,
1499 .set_mode = spmi_regulator_common_set_mode,
1500 .get_mode = spmi_regulator_common_get_mode,
1501 .set_load = spmi_regulator_common_set_load,
1502 .set_pull_down = spmi_regulator_common_set_pull_down,
1503};
1504
1505static const struct regulator_ops spmi_ult_ho_smps_ops = {
1506 .enable = regulator_enable_regmap,
1507 .disable = regulator_disable_regmap,
1508 .is_enabled = regulator_is_enabled_regmap,
1509 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1510 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1511 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1512 .map_voltage = spmi_regulator_single_map_voltage,
1513 .list_voltage = spmi_regulator_common_list_voltage,
1514 .set_mode = spmi_regulator_common_set_mode,
1515 .get_mode = spmi_regulator_common_get_mode,
1516 .set_load = spmi_regulator_common_set_load,
1517 .set_pull_down = spmi_regulator_common_set_pull_down,
1518};
1519
1520static const struct regulator_ops spmi_ult_ldo_ops = {
1521 .enable = regulator_enable_regmap,
1522 .disable = regulator_disable_regmap,
1523 .is_enabled = regulator_is_enabled_regmap,
1524 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1525 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1526 .map_voltage = spmi_regulator_single_map_voltage,
1527 .list_voltage = spmi_regulator_common_list_voltage,
1528 .set_mode = spmi_regulator_common_set_mode,
1529 .get_mode = spmi_regulator_common_get_mode,
1530 .set_load = spmi_regulator_common_set_load,
1531 .set_bypass = spmi_regulator_common_set_bypass,
1532 .get_bypass = spmi_regulator_common_get_bypass,
1533 .set_pull_down = spmi_regulator_common_set_pull_down,
1534 .set_soft_start = spmi_regulator_common_set_soft_start,
1535};
1536
1537static const struct regulator_ops spmi_ftsmps426_ops = {
1538 .enable = regulator_enable_regmap,
1539 .disable = regulator_disable_regmap,
1540 .is_enabled = regulator_is_enabled_regmap,
1541 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
1542 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1543 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
1544 .map_voltage = spmi_regulator_single_map_voltage,
1545 .list_voltage = spmi_regulator_common_list_voltage,
1546 .set_mode = spmi_regulator_ftsmps426_set_mode,
1547 .get_mode = spmi_regulator_ftsmps426_get_mode,
1548 .set_load = spmi_regulator_common_set_load,
1549 .set_pull_down = spmi_regulator_common_set_pull_down,
1550};
1551
1552static const struct regulator_ops spmi_hfs430_ops = {
1553 .enable = regulator_enable_regmap,
1554 .disable = regulator_disable_regmap,
1555 .is_enabled = regulator_is_enabled_regmap,
1556 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
1557 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1558 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
1559 .map_voltage = spmi_regulator_single_map_voltage,
1560 .list_voltage = spmi_regulator_common_list_voltage,
1561 .set_mode = spmi_regulator_ftsmps426_set_mode,
1562 .get_mode = spmi_regulator_ftsmps426_get_mode,
1563};
1564
1565static const struct regulator_ops spmi_hfsmps_ops = {
1566 .enable = regulator_enable_regmap,
1567 .disable = regulator_disable_regmap,
1568 .is_enabled = regulator_is_enabled_regmap,
1569 .set_voltage_sel = spmi_regulator_ftsmps426_set_voltage,
1570 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1571 .get_voltage_sel = spmi_regulator_ftsmps426_get_voltage,
1572 .map_voltage = spmi_regulator_single_map_voltage,
1573 .list_voltage = spmi_regulator_common_list_voltage,
1574 .set_mode = spmi_regulator_hfsmps_set_mode,
1575 .get_mode = spmi_regulator_hfsmps_get_mode,
1576 .set_load = spmi_regulator_common_set_load,
1577 .set_pull_down = spmi_regulator_hfsmps_set_pull_down,
1578};
1579
1580/* Maximum possible digital major revision value */
1581#define INF 0xFF
1582
1583static const struct spmi_regulator_mapping supported_regulators[] = {
1584 /* type subtype dig_min dig_max ltype ops setpoints hpm_min */
1585 SPMI_VREG(LDO, HT_P600, 0, INF, HFS430, hfs430, ht_p600, 10000),
1586 SPMI_VREG(LDO, HT_P150, 0, INF, HFS430, hfs430, ht_p150, 10000),
1587 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
1588 SPMI_VREG(BUCK, HFS430, 0, 3, HFS430, hfs430, hfs430, 10000),
1589 SPMI_VREG(BUCK, HFSMPS_510, 4, INF, HFSMPS, hfsmps, hfs430, 100000),
1590 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
1591 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000),
1592 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000),
1593 SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000),
1594 SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000),
1595 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000),
1596 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000),
1597 SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000),
1598 SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000),
1599 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000),
1600 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000),
1601 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000),
1602 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000),
1603 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000),
1604 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0),
1605 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000),
1606 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000),
1607 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000),
1608 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000),
1609 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000),
1610 SPMI_VREG(LDO, HT_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1611 ht_nldo, 30000),
1612 SPMI_VREG(LDO, HT_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1613 ht_nldo, 30000),
1614 SPMI_VREG(LDO, HT_N1200_ST, 0, INF, FTSMPS426, ftsmps426,
1615 ht_nldo, 30000),
1616 SPMI_VREG(LDO, HT_LVP150, 0, INF, FTSMPS426, ftsmps426,
1617 ht_lvpldo, 10000),
1618 SPMI_VREG(LDO, HT_LVP300, 0, INF, FTSMPS426, ftsmps426,
1619 ht_lvpldo, 10000),
1620 SPMI_VREG(LDO, L660_N300_ST, 0, INF, FTSMPS426, ftsmps426,
1621 nldo660, 10000),
1622 SPMI_VREG(LDO, L660_N600_ST, 0, INF, FTSMPS426, ftsmps426,
1623 nldo660, 10000),
1624 SPMI_VREG(LDO, L660_P50, 0, INF, FTSMPS426, ftsmps426,
1625 pldo660, 10000),
1626 SPMI_VREG(LDO, L660_P150, 0, INF, FTSMPS426, ftsmps426,
1627 pldo660, 10000),
1628 SPMI_VREG(LDO, L660_P600, 0, INF, FTSMPS426, ftsmps426,
1629 pldo660, 10000),
1630 SPMI_VREG(LDO, L660_LVP150, 0, INF, FTSMPS426, ftsmps426,
1631 ht_lvpldo, 10000),
1632 SPMI_VREG(LDO, L660_LVP600, 0, INF, FTSMPS426, ftsmps426,
1633 ht_lvpldo, 10000),
1634 SPMI_VREG_VS(LV100, 0, INF),
1635 SPMI_VREG_VS(LV300, 0, INF),
1636 SPMI_VREG_VS(MV300, 0, INF),
1637 SPMI_VREG_VS(MV500, 0, INF),
1638 SPMI_VREG_VS(HDMI, 0, INF),
1639 SPMI_VREG_VS(OTG, 0, INF),
1640 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
1641 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000),
1642 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000),
1643 SPMI_VREG(FTS, FTS426_CTL, 0, INF, FTSMPS426, ftsmps426, ftsmps426, 100000),
1644 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0),
1645 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1646 ult_lo_smps, 100000),
1647 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1648 ult_lo_smps, 100000),
1649 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1650 ult_lo_smps, 100000),
1651 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps,
1652 ult_ho_smps, 100000),
1653 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1654 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1655 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1656 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1657 SPMI_VREG(ULT_LDO, LV_P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1658 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1659 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1660 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1661 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1662 SPMI_VREG(ULT_LDO, P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1663 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1664 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000),
1665 SPMI_VREG(LDO, LV_P150_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000),
1666 SPMI_VREG(LDO, LV_P300_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000),
1667 SPMI_VREG(LDO, LV_P600_510, 0, INF, LDO_510, hfsmps, ht_lvpldo, 10000),
1668 SPMI_VREG(LDO, MV_P50_510, 0, INF, LDO_510, hfsmps, pldo660, 10000),
1669 SPMI_VREG(LDO, MV_P150_510, 0, INF, LDO_510, hfsmps, pldo660, 10000),
1670 SPMI_VREG(LDO, MV_P600_510, 0, INF, LDO_510, hfsmps, pldo660, 10000),
1671 SPMI_VREG(LDO, N300_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000),
1672 SPMI_VREG(LDO, N600_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000),
1673 SPMI_VREG(LDO, N1200_510, 0, INF, LDO_510, hfsmps, nldo_510, 10000),
1674 SPMI_VREG(FTS, FTSMPS_510, 0, INF, FTSMPS3, hfsmps, ftsmps510, 100000),
1675};
1676
1677static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points)
1678{
1679 unsigned int n;
1680 struct spmi_voltage_range *range = points->range;
1681
1682 for (; range < points->range + points->count; range++) {
1683 n = 0;
1684 if (range->set_point_max_uV) {
1685 n = range->set_point_max_uV - range->set_point_min_uV;
1686 n = (n / range->step_uV) + 1;
1687 }
1688 range->n_voltages = n;
1689 points->n_voltages += n;
1690 }
1691}
1692
1693static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type)
1694{
1695 const struct spmi_regulator_mapping *mapping;
1696 int ret, i;
1697 u32 dig_major_rev;
1698 u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1];
1699 u8 type, subtype;
1700
1701 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version,
1702 ARRAY_SIZE(version));
1703 if (ret) {
1704 dev_dbg(vreg->dev, "could not read version registers\n");
1705 return ret;
1706 }
1707 dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV
1708 - SPMI_COMMON_REG_DIG_MAJOR_REV];
1709
1710 if (!force_type) {
1711 type = version[SPMI_COMMON_REG_TYPE -
1712 SPMI_COMMON_REG_DIG_MAJOR_REV];
1713 subtype = version[SPMI_COMMON_REG_SUBTYPE -
1714 SPMI_COMMON_REG_DIG_MAJOR_REV];
1715 } else {
1716 type = force_type >> 8;
1717 subtype = force_type;
1718 }
1719
1720 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) {
1721 mapping = &supported_regulators[i];
1722 if (mapping->type == type && mapping->subtype == subtype
1723 && mapping->revision_min <= dig_major_rev
1724 && mapping->revision_max >= dig_major_rev)
1725 goto found;
1726 }
1727
1728 dev_err(vreg->dev,
1729 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n",
1730 vreg->desc.name, type, subtype, dig_major_rev);
1731
1732 return -ENODEV;
1733
1734found:
1735 vreg->logical_type = mapping->logical_type;
1736 vreg->set_points = mapping->set_points;
1737 vreg->hpm_min_load = mapping->hpm_min_load;
1738 vreg->desc.ops = mapping->ops;
1739
1740 if (mapping->set_points) {
1741 if (!mapping->set_points->n_voltages)
1742 spmi_calculate_num_voltages(mapping->set_points);
1743 vreg->desc.n_voltages = mapping->set_points->n_voltages;
1744 }
1745
1746 return 0;
1747}
1748
1749static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg)
1750{
1751 int ret;
1752 u8 reg = 0;
1753 int step, delay, slew_rate, step_delay;
1754 const struct spmi_voltage_range *range;
1755
1756 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1);
1757 if (ret) {
1758 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1759 return ret;
1760 }
1761
1762 range = spmi_regulator_find_range(vreg);
1763 if (!range)
1764 return -EINVAL;
1765
1766 switch (vreg->logical_type) {
1767 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1768 step_delay = SPMI_FTSMPS_STEP_DELAY;
1769 break;
1770 default:
1771 step_delay = SPMI_DEFAULT_STEP_DELAY;
1772 break;
1773 }
1774
1775 step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK;
1776 step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT;
1777
1778 delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK;
1779 delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT;
1780
1781 /* slew_rate has units of uV/us */
1782 slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step);
1783 slew_rate /= 1000 * (step_delay << delay);
1784 slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM;
1785 slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN;
1786
1787 /* Ensure that the slew rate is greater than 0 */
1788 vreg->slew_rate = max(slew_rate, 1);
1789
1790 return ret;
1791}
1792
1793static int spmi_regulator_init_slew_rate_ftsmps426(struct spmi_regulator *vreg,
1794 int clock_rate)
1795{
1796 int ret;
1797 u8 reg = 0;
1798 int delay, slew_rate;
1799 const struct spmi_voltage_range *range = &vreg->set_points->range[0];
1800
1801 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1);
1802 if (ret) {
1803 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1804 return ret;
1805 }
1806
1807 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK;
1808 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT;
1809
1810 /* slew_rate has units of uV/us */
1811 slew_rate = clock_rate * range->step_uV;
1812 slew_rate /= 1000 * (SPMI_FTSMPS426_STEP_DELAY << delay);
1813 slew_rate *= SPMI_FTSMPS426_STEP_MARGIN_NUM;
1814 slew_rate /= SPMI_FTSMPS426_STEP_MARGIN_DEN;
1815
1816 /* Ensure that the slew rate is greater than 0 */
1817 vreg->slew_rate = max(slew_rate, 1);
1818
1819 return ret;
1820}
1821
1822static int spmi_regulator_init_slew_rate_hfsmps(struct spmi_regulator *vreg)
1823{
1824 int ret;
1825 u8 reg = 0;
1826 int delay;
1827
1828 ret = spmi_vreg_read(vreg, SPMI_HFSMPS_REG_STEP_CTRL, ®, 1);
1829 if (ret) {
1830 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1831 return ret;
1832 }
1833
1834 delay = reg & SPMI_FTSMPS426_STEP_CTRL_DELAY_MASK;
1835 delay >>= SPMI_FTSMPS426_STEP_CTRL_DELAY_SHIFT;
1836
1837 vreg->slew_rate = SPMI_HFSMPS_SLEW_RATE_38p4 >> delay;
1838
1839 return ret;
1840}
1841
1842static int spmi_regulator_init_registers(struct spmi_regulator *vreg,
1843 const struct spmi_regulator_init_data *data)
1844{
1845 int ret;
1846 enum spmi_regulator_logical_type type;
1847 u8 ctrl_reg[8], reg, mask;
1848
1849 type = vreg->logical_type;
1850
1851 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1852 if (ret)
1853 return ret;
1854
1855 /* Set up enable pin control. */
1856 if (!(data->pin_ctrl_enable & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) {
1857 switch (type) {
1858 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1859 case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
1860 case SPMI_REGULATOR_LOGICAL_TYPE_VS:
1861 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=
1862 ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1863 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=
1864 data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1865 break;
1866 default:
1867 break;
1868 }
1869 }
1870
1871 /* Set up mode pin control. */
1872 if (!(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
1873 switch (type) {
1874 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1875 case SPMI_REGULATOR_LOGICAL_TYPE_LDO:
1876 ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1877 ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1878 ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1879 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1880 break;
1881 case SPMI_REGULATOR_LOGICAL_TYPE_VS:
1882 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
1883 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
1884 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO:
1885 ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1886 ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1887 ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1888 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1889 break;
1890 default:
1891 break;
1892 }
1893 }
1894
1895 /* Write back any control register values that were modified. */
1896 ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1897 if (ret)
1898 return ret;
1899
1900 /* Set soft start strength and over current protection for VS. */
1901 if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) {
1902 if (data->vs_soft_start_strength
1903 != SPMI_VS_SOFT_START_STR_HW_DEFAULT) {
1904 reg = data->vs_soft_start_strength
1905 & SPMI_VS_SOFT_START_SEL_MASK;
1906 mask = SPMI_VS_SOFT_START_SEL_MASK;
1907 return spmi_vreg_update_bits(vreg,
1908 SPMI_VS_REG_SOFT_START,
1909 reg, mask);
1910 }
1911 }
1912
1913 return 0;
1914}
1915
1916static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg,
1917 struct device_node *node, struct spmi_regulator_init_data *data)
1918{
1919 /*
1920 * Initialize configuration parameters to use hardware default in case
1921 * no value is specified via device tree.
1922 */
1923 data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT;
1924 data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT;
1925 data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT;
1926
1927 /* These bindings are optional, so it is okay if they aren't found. */
1928 of_property_read_u32(node, "qcom,ocp-max-retries",
1929 &vreg->ocp_max_retries);
1930 of_property_read_u32(node, "qcom,ocp-retry-delay",
1931 &vreg->ocp_retry_delay_ms);
1932 of_property_read_u32(node, "qcom,pin-ctrl-enable",
1933 &data->pin_ctrl_enable);
1934 of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm);
1935 of_property_read_u32(node, "qcom,vs-soft-start-strength",
1936 &data->vs_soft_start_strength);
1937}
1938
1939static unsigned int spmi_regulator_of_map_mode(unsigned int mode)
1940{
1941 if (mode == 1)
1942 return REGULATOR_MODE_NORMAL;
1943 if (mode == 2)
1944 return REGULATOR_MODE_FAST;
1945
1946 return REGULATOR_MODE_IDLE;
1947}
1948
1949static int spmi_regulator_of_parse(struct device_node *node,
1950 const struct regulator_desc *desc,
1951 struct regulator_config *config)
1952{
1953 struct spmi_regulator_init_data data = { };
1954 struct spmi_regulator *vreg = config->driver_data;
1955 struct device *dev = config->dev;
1956 int ret;
1957
1958 spmi_regulator_get_dt_config(vreg, node, &data);
1959
1960 if (!vreg->ocp_max_retries)
1961 vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES;
1962 if (!vreg->ocp_retry_delay_ms)
1963 vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS;
1964
1965 ret = spmi_regulator_init_registers(vreg, &data);
1966 if (ret) {
1967 dev_err(dev, "common initialization failed, ret=%d\n", ret);
1968 return ret;
1969 }
1970
1971 switch (vreg->logical_type) {
1972 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1973 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
1974 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
1975 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1976 ret = spmi_regulator_init_slew_rate(vreg);
1977 if (ret)
1978 return ret;
1979 break;
1980 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS426:
1981 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
1982 SPMI_FTSMPS426_CLOCK_RATE);
1983 if (ret)
1984 return ret;
1985 break;
1986 case SPMI_REGULATOR_LOGICAL_TYPE_HFS430:
1987 ret = spmi_regulator_init_slew_rate_ftsmps426(vreg,
1988 SPMI_HFS430_CLOCK_RATE);
1989 if (ret)
1990 return ret;
1991 break;
1992 case SPMI_REGULATOR_LOGICAL_TYPE_HFSMPS:
1993 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS3:
1994 ret = spmi_regulator_init_slew_rate_hfsmps(vreg);
1995 if (ret)
1996 return ret;
1997 break;
1998 default:
1999 break;
2000 }
2001
2002 if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS)
2003 vreg->ocp_irq = 0;
2004
2005 if (vreg->ocp_irq) {
2006 ret = devm_request_irq(dev, vreg->ocp_irq,
2007 spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp",
2008 vreg);
2009 if (ret < 0) {
2010 dev_err(dev, "failed to request irq %d, ret=%d\n",
2011 vreg->ocp_irq, ret);
2012 return ret;
2013 }
2014
2015 ret = devm_delayed_work_autocancel(dev, &vreg->ocp_work,
2016 spmi_regulator_vs_ocp_work);
2017 if (ret)
2018 return ret;
2019 }
2020
2021 return 0;
2022}
2023
2024static const struct spmi_regulator_data pm6125_regulators[] = {
2025 { "s1", 0x1400, "vdd_s1" },
2026 { "s2", 0x1700, "vdd_s2" },
2027 { "s3", 0x1a00, "vdd_s3" },
2028 { "s4", 0x1d00, "vdd_s4" },
2029 { "s5", 0x2000, "vdd_s5" },
2030 { "s6", 0x2300, "vdd_s6" },
2031 { "s7", 0x2600, "vdd_s7" },
2032 { "s8", 0x2900, "vdd_s8" },
2033 { "l1", 0x4000, "vdd_l1_l7_l17_l18" },
2034 { "l2", 0x4100, "vdd_l2_l3_l4" },
2035 { "l3", 0x4200, "vdd_l2_l3_l4" },
2036 { "l4", 0x4300, "vdd_l2_l3_l4" },
2037 { "l5", 0x4400, "vdd_l5_l15_l19_l20_l21_l22" },
2038 { "l6", 0x4500, "vdd_l6_l8" },
2039 { "l7", 0x4600, "vdd_l1_l7_l17_l18" },
2040 { "l8", 0x4700, "vdd_l6_l8" },
2041 { "l9", 0x4800, "vdd_l9_l11" },
2042 { "l10", 0x4900, "vdd_l10_l13_l14" },
2043 { "l11", 0x4a00, "vdd_l9_l11" },
2044 { "l12", 0x4b00, "vdd_l12_l16" },
2045 { "l13", 0x4c00, "vdd_l10_l13_l14" },
2046 { "l14", 0x4d00, "vdd_l10_l13_l14" },
2047 { "l15", 0x4e00, "vdd_l5_l15_l19_l20_l21_l22" },
2048 { "l16", 0x4f00, "vdd_l12_l16" },
2049 { "l17", 0x5000, "vdd_l1_l7_l17_l18" },
2050 { "l18", 0x5100, "vdd_l1_l7_l17_l18" },
2051 { "l19", 0x5200, "vdd_l5_l15_l19_l20_l21_l22" },
2052 { "l20", 0x5300, "vdd_l5_l15_l19_l20_l21_l22" },
2053 { "l21", 0x5400, "vdd_l5_l15_l19_l20_l21_l22" },
2054 { "l22", 0x5500, "vdd_l5_l15_l19_l20_l21_l22" },
2055 { "l23", 0x5600, "vdd_l23_l24" },
2056 { "l24", 0x5700, "vdd_l23_l24" },
2057};
2058
2059static const struct spmi_regulator_data pm660_regulators[] = {
2060 { "s1", 0x1400, "vdd_s1", },
2061 { "s2", 0x1700, "vdd_s2", },
2062 { "s3", 0x1a00, "vdd_s3", },
2063 { "s4", 0x1d00, "vdd_s3", },
2064 { "s5", 0x2000, "vdd_s5", },
2065 { "s6", 0x2300, "vdd_s6", },
2066 { "l1", 0x4000, "vdd_l1_l6_l7", },
2067 { "l2", 0x4100, "vdd_l2_l3", },
2068 { "l3", 0x4200, "vdd_l2_l3", },
2069 /* l4 is unaccessible on PM660 */
2070 { "l5", 0x4400, "vdd_l5", },
2071 { "l6", 0x4500, "vdd_l1_l6_l7", },
2072 { "l7", 0x4600, "vdd_l1_l6_l7", },
2073 { "l8", 0x4700, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2074 { "l9", 0x4800, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2075 { "l10", 0x4900, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2076 { "l11", 0x4a00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2077 { "l12", 0x4b00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2078 { "l13", 0x4c00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2079 { "l14", 0x4d00, "vdd_l8_l9_l10_l11_l12_l13_l14", },
2080 { "l15", 0x4e00, "vdd_l15_l16_l17_l18_l19", },
2081 { "l16", 0x4f00, "vdd_l15_l16_l17_l18_l19", },
2082 { "l17", 0x5000, "vdd_l15_l16_l17_l18_l19", },
2083 { "l18", 0x5100, "vdd_l15_l16_l17_l18_l19", },
2084 { "l19", 0x5200, "vdd_l15_l16_l17_l18_l19", },
2085 { }
2086};
2087
2088static const struct spmi_regulator_data pm660l_regulators[] = {
2089 { "s1", 0x1400, "vdd_s1", },
2090 { "s2", 0x1700, "vdd_s2", },
2091 { "s3", 0x1a00, "vdd_s3", },
2092 { "s4", 0x1d00, "vdd_s4", },
2093 { "s5", 0x2000, "vdd_s5", },
2094 { "l1", 0x4000, "vdd_l1_l9_l10", },
2095 { "l2", 0x4100, "vdd_l2", },
2096 { "l3", 0x4200, "vdd_l3_l5_l7_l8", },
2097 { "l4", 0x4300, "vdd_l4_l6", },
2098 { "l5", 0x4400, "vdd_l3_l5_l7_l8", },
2099 { "l6", 0x4500, "vdd_l4_l6", },
2100 { "l7", 0x4600, "vdd_l3_l5_l7_l8", },
2101 { "l8", 0x4700, "vdd_l3_l5_l7_l8", },
2102 { "l9", 0x4800, "vdd_l1_l9_l10", },
2103 { "l10", 0x4900, "vdd_l1_l9_l10", },
2104 { }
2105};
2106
2107static const struct spmi_regulator_data pm8004_regulators[] = {
2108 { "s2", 0x1700, "vdd_s2", },
2109 { "s5", 0x2000, "vdd_s5", },
2110 { }
2111};
2112
2113static const struct spmi_regulator_data pm8005_regulators[] = {
2114 { "s1", 0x1400, "vdd_s1", },
2115 { "s2", 0x1700, "vdd_s2", },
2116 { "s3", 0x1a00, "vdd_s3", },
2117 { "s4", 0x1d00, "vdd_s4", },
2118 { }
2119};
2120
2121static const struct spmi_regulator_data pm8019_regulators[] = {
2122 { "s1", 0x1400, "vdd_s1", },
2123 { "s2", 0x1700, "vdd_s2", },
2124 { "s3", 0x1a00, "vdd_s3", },
2125 { "s4", 0x1d00, "vdd_s4", },
2126 { "l1", 0x4000, "vdd_l1", },
2127 { "l2", 0x4100, "vdd_l2_l3", },
2128 { "l3", 0x4200, "vdd_l2_l3", },
2129 { "l4", 0x4300, "vdd_l4_l5_l6", },
2130 { "l5", 0x4400, "vdd_l4_l5_l6", },
2131 { "l6", 0x4500, "vdd_l4_l5_l6", },
2132 { "l7", 0x4600, "vdd_l7_l8_l11", },
2133 { "l8", 0x4700, "vdd_l7_l8_l11", },
2134 { "l9", 0x4800, "vdd_l9", },
2135 { "l10", 0x4900, "vdd_l10", },
2136 { "l11", 0x4a00, "vdd_l7_l8_l11", },
2137 { "l12", 0x4b00, "vdd_l12", },
2138 { "l13", 0x4c00, "vdd_l13_l14", },
2139 { "l14", 0x4d00, "vdd_l13_l14", },
2140 { }
2141};
2142
2143static const struct spmi_regulator_data pm8226_regulators[] = {
2144 { "s1", 0x1400, "vdd_s1", },
2145 { "s2", 0x1700, "vdd_s2", },
2146 { "s3", 0x1a00, "vdd_s3", },
2147 { "s4", 0x1d00, "vdd_s4", },
2148 { "s5", 0x2000, "vdd_s5", },
2149 { "l1", 0x4000, "vdd_l1_l2_l4_l5", },
2150 { "l2", 0x4100, "vdd_l1_l2_l4_l5", },
2151 { "l3", 0x4200, "vdd_l3_l24_l26", },
2152 { "l4", 0x4300, "vdd_l1_l2_l4_l5", },
2153 { "l5", 0x4400, "vdd_l1_l2_l4_l5", },
2154 { "l6", 0x4500, "vdd_l6_l7_l8_l9_l27", },
2155 { "l7", 0x4600, "vdd_l6_l7_l8_l9_l27", },
2156 { "l8", 0x4700, "vdd_l6_l7_l8_l9_l27", },
2157 { "l9", 0x4800, "vdd_l6_l7_l8_l9_l27", },
2158 { "l10", 0x4900, "vdd_l10_l11_l13", },
2159 { "l11", 0x4a00, "vdd_l10_l11_l13", },
2160 { "l12", 0x4b00, "vdd_l12_l14", },
2161 { "l13", 0x4c00, "vdd_l10_l11_l13", },
2162 { "l14", 0x4d00, "vdd_l12_l14", },
2163 { "l15", 0x4e00, "vdd_l15_l16_l17_l18", },
2164 { "l16", 0x4f00, "vdd_l15_l16_l17_l18", },
2165 { "l17", 0x5000, "vdd_l15_l16_l17_l18", },
2166 { "l18", 0x5100, "vdd_l15_l16_l17_l18", },
2167 { "l19", 0x5200, "vdd_l19_l20_l21_l22_l23_l28", },
2168 { "l20", 0x5300, "vdd_l19_l20_l21_l22_l23_l28", },
2169 { "l21", 0x5400, "vdd_l19_l20_l21_l22_l23_l28", },
2170 { "l22", 0x5500, "vdd_l19_l20_l21_l22_l23_l28", },
2171 { "l23", 0x5600, "vdd_l19_l20_l21_l22_l23_l28", },
2172 { "l24", 0x5700, "vdd_l3_l24_l26", },
2173 { "l25", 0x5800, "vdd_l25", },
2174 { "l26", 0x5900, "vdd_l3_l24_l26", },
2175 { "l27", 0x5a00, "vdd_l6_l7_l8_l9_l27", },
2176 { "l28", 0x5b00, "vdd_l19_l20_l21_l22_l23_l28", },
2177 { "lvs1", 0x8000, "vdd_lvs1", },
2178 { }
2179};
2180
2181static const struct spmi_regulator_data pm8841_regulators[] = {
2182 { "s1", 0x1400, "vdd_s1", },
2183 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 },
2184 { "s3", 0x1a00, "vdd_s3", },
2185 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 },
2186 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 },
2187 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 },
2188 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 },
2189 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 },
2190 { }
2191};
2192
2193static const struct spmi_regulator_data pm8909_regulators[] = {
2194 { "s1", 0x1400, "vdd_s1", },
2195 { "s2", 0x1700, "vdd_s2", },
2196 { "l1", 0x4000, "vdd_l1", },
2197 { "l2", 0x4100, "vdd_l2_l5", },
2198 { "l3", 0x4200, "vdd_l3_l6_l10", },
2199 { "l4", 0x4300, "vdd_l4_l7", },
2200 { "l5", 0x4400, "vdd_l2_l5", },
2201 { "l6", 0x4500, "vdd_l3_l6_l10", },
2202 { "l7", 0x4600, "vdd_l4_l7", },
2203 { "l8", 0x4700, "vdd_l8_l11_l15_l18", },
2204 { "l9", 0x4800, "vdd_l9_l12_l14_l17", },
2205 { "l10", 0x4900, "vdd_l3_l6_l10", },
2206 { "l11", 0x4a00, "vdd_l8_l11_l15_l18", },
2207 { "l12", 0x4b00, "vdd_l9_l12_l14_l17", },
2208 { "l13", 0x4c00, "vdd_l13", },
2209 { "l14", 0x4d00, "vdd_l9_l12_l14_l17", },
2210 { "l15", 0x4e00, "vdd_l8_l11_l15_l18", },
2211 { "l17", 0x5000, "vdd_l9_l12_l14_l17", },
2212 { "l18", 0x5100, "vdd_l8_l11_l15_l18", },
2213 { }
2214};
2215
2216static const struct spmi_regulator_data pm8916_regulators[] = {
2217 { "s1", 0x1400, "vdd_s1", },
2218 { "s2", 0x1700, "vdd_s2", },
2219 { "s3", 0x1a00, "vdd_s3", },
2220 { "s4", 0x1d00, "vdd_s4", },
2221 { "l1", 0x4000, "vdd_l1_l3", },
2222 { "l2", 0x4100, "vdd_l2", },
2223 { "l3", 0x4200, "vdd_l1_l3", },
2224 { "l4", 0x4300, "vdd_l4_l5_l6", },
2225 { "l5", 0x4400, "vdd_l4_l5_l6", },
2226 { "l6", 0x4500, "vdd_l4_l5_l6", },
2227 { "l7", 0x4600, "vdd_l7", },
2228 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", },
2229 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", },
2230 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", },
2231 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", },
2232 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", },
2233 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", },
2234 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", },
2235 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", },
2236 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", },
2237 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", },
2238 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", },
2239 { }
2240};
2241
2242static const struct spmi_regulator_data pm8937_regulators[] = {
2243 { "s1", 0x1400, "vdd_s1", },
2244 { "s2", 0x1700, "vdd_s2", },
2245 { "s3", 0x1a00, "vdd_s3", },
2246 { "s4", 0x1d00, "vdd_s4", },
2247 { "s5", 0x2000, "vdd_s5", },
2248 { "s6", 0x2300, "vdd_s6", },
2249 { "l1", 0x4000, "vdd_l1_l19", },
2250 { "l2", 0x4100, "vdd_l2_l23", },
2251 { "l3", 0x4200, "vdd_l3", },
2252 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
2253 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
2254 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
2255 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
2256 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
2257 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
2258 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
2259 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
2260 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
2261 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
2262 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
2263 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
2264 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
2265 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
2266 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
2267 { "l19", 0x5200, "vdd_l1_l19", },
2268 { "l20", 0x5300, "vdd_l20_l21", },
2269 { "l21", 0x5400, "vdd_l21_l21", },
2270 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
2271 { "l23", 0x5600, "vdd_l2_l23", },
2272 { }
2273};
2274
2275static const struct spmi_regulator_data pm8941_regulators[] = {
2276 { "s1", 0x1400, "vdd_s1", },
2277 { "s2", 0x1700, "vdd_s2", },
2278 { "s3", 0x1a00, "vdd_s3", },
2279 { "s4", 0xa000, },
2280 { "l1", 0x4000, "vdd_l1_l3", },
2281 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", },
2282 { "l3", 0x4200, "vdd_l1_l3", },
2283 { "l4", 0x4300, "vdd_l4_l11", },
2284 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 },
2285 { "l6", 0x4500, "vdd_l6_l12_l14_l15", },
2286 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 },
2287 { "l8", 0x4700, "vdd_l8_l16_l18_19", },
2288 { "l9", 0x4800, "vdd_l9_l10_l17_l22", },
2289 { "l10", 0x4900, "vdd_l9_l10_l17_l22", },
2290 { "l11", 0x4a00, "vdd_l4_l11", },
2291 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", },
2292 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", },
2293 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", },
2294 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", },
2295 { "l16", 0x4f00, "vdd_l8_l16_l18_19", },
2296 { "l17", 0x5000, "vdd_l9_l10_l17_l22", },
2297 { "l18", 0x5100, "vdd_l8_l16_l18_19", },
2298 { "l19", 0x5200, "vdd_l8_l16_l18_19", },
2299 { "l20", 0x5300, "vdd_l13_l20_l23_l24", },
2300 { "l21", 0x5400, "vdd_l21", },
2301 { "l22", 0x5500, "vdd_l9_l10_l17_l22", },
2302 { "l23", 0x5600, "vdd_l13_l20_l23_l24", },
2303 { "l24", 0x5700, "vdd_l13_l20_l23_l24", },
2304 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
2305 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
2306 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
2307 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
2308 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
2309 { }
2310};
2311
2312static const struct spmi_regulator_data pm8950_regulators[] = {
2313 { "s1", 0x1400, "vdd_s1", },
2314 { "s2", 0x1700, "vdd_s2", },
2315 { "s3", 0x1a00, "vdd_s3", },
2316 { "s4", 0x1d00, "vdd_s4", },
2317 { "s5", 0x2000, "vdd_s5", },
2318 { "s6", 0x2300, "vdd_s6", },
2319 { "l1", 0x4000, "vdd_l1_l19", },
2320 { "l2", 0x4100, "vdd_l2_l23", },
2321 { "l3", 0x4200, "vdd_l3", },
2322 { "l4", 0x4300, "vdd_l4_l5_l6_l7_l16", },
2323 { "l5", 0x4400, "vdd_l4_l5_l6_l7_l16", },
2324 { "l6", 0x4500, "vdd_l4_l5_l6_l7_l16", },
2325 { "l7", 0x4600, "vdd_l4_l5_l6_l7_l16", },
2326 { "l8", 0x4700, "vdd_l8_l11_l12_l17_l22", },
2327 { "l9", 0x4800, "vdd_l9_l10_l13_l14_l15_l18", },
2328 { "l10", 0x4900, "vdd_l9_l10_l13_l14_l15_l18", },
2329 { "l11", 0x4a00, "vdd_l8_l11_l12_l17_l22", },
2330 { "l12", 0x4b00, "vdd_l8_l11_l12_l17_l22", },
2331 { "l13", 0x4c00, "vdd_l9_l10_l13_l14_l15_l18", },
2332 { "l14", 0x4d00, "vdd_l9_l10_l13_l14_l15_l18", },
2333 { "l15", 0x4e00, "vdd_l9_l10_l13_l14_l15_l18", },
2334 { "l16", 0x4f00, "vdd_l4_l5_l6_l7_l16", },
2335 { "l17", 0x5000, "vdd_l8_l11_l12_l17_l22", },
2336 { "l18", 0x5100, "vdd_l9_l10_l13_l14_l15_l18", },
2337 { "l19", 0x5200, "vdd_l1_l19", },
2338 { "l20", 0x5300, "vdd_l20", },
2339 { "l21", 0x5400, "vdd_l21", },
2340 { "l22", 0x5500, "vdd_l8_l11_l12_l17_l22", },
2341 { "l23", 0x5600, "vdd_l2_l23", },
2342 { }
2343};
2344
2345static const struct spmi_regulator_data pm8994_regulators[] = {
2346 { "s1", 0x1400, "vdd_s1", },
2347 { "s2", 0x1700, "vdd_s2", },
2348 { "s3", 0x1a00, "vdd_s3", },
2349 { "s4", 0x1d00, "vdd_s4", },
2350 { "s5", 0x2000, "vdd_s5", },
2351 { "s6", 0x2300, "vdd_s6", },
2352 { "s7", 0x2600, "vdd_s7", },
2353 { "s8", 0x2900, "vdd_s8", },
2354 { "s9", 0x2c00, "vdd_s9", },
2355 { "s10", 0x2f00, "vdd_s10", },
2356 { "s11", 0x3200, "vdd_s11", },
2357 { "s12", 0x3500, "vdd_s12", },
2358 { "l1", 0x4000, "vdd_l1", },
2359 { "l2", 0x4100, "vdd_l2_l26_l28", },
2360 { "l3", 0x4200, "vdd_l3_l11", },
2361 { "l4", 0x4300, "vdd_l4_l27_l31", },
2362 { "l5", 0x4400, "vdd_l5_l7", },
2363 { "l6", 0x4500, "vdd_l6_l12_l32", },
2364 { "l7", 0x4600, "vdd_l5_l7", },
2365 { "l8", 0x4700, "vdd_l8_l16_l30", },
2366 { "l9", 0x4800, "vdd_l9_l10_l18_l22", },
2367 { "l10", 0x4900, "vdd_l9_l10_l18_l22", },
2368 { "l11", 0x4a00, "vdd_l3_l11", },
2369 { "l12", 0x4b00, "vdd_l6_l12_l32", },
2370 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", },
2371 { "l14", 0x4d00, "vdd_l14_l15", },
2372 { "l15", 0x4e00, "vdd_l14_l15", },
2373 { "l16", 0x4f00, "vdd_l8_l16_l30", },
2374 { "l17", 0x5000, "vdd_l17_l29", },
2375 { "l18", 0x5100, "vdd_l9_l10_l18_l22", },
2376 { "l19", 0x5200, "vdd_l13_l19_l23_l24", },
2377 { "l20", 0x5300, "vdd_l20_l21", },
2378 { "l21", 0x5400, "vdd_l20_l21", },
2379 { "l22", 0x5500, "vdd_l9_l10_l18_l22", },
2380 { "l23", 0x5600, "vdd_l13_l19_l23_l24", },
2381 { "l24", 0x5700, "vdd_l13_l19_l23_l24", },
2382 { "l25", 0x5800, "vdd_l25", },
2383 { "l26", 0x5900, "vdd_l2_l26_l28", },
2384 { "l27", 0x5a00, "vdd_l4_l27_l31", },
2385 { "l28", 0x5b00, "vdd_l2_l26_l28", },
2386 { "l29", 0x5c00, "vdd_l17_l29", },
2387 { "l30", 0x5d00, "vdd_l8_l16_l30", },
2388 { "l31", 0x5e00, "vdd_l4_l27_l31", },
2389 { "l32", 0x5f00, "vdd_l6_l12_l32", },
2390 { "lvs1", 0x8000, "vdd_lvs_1_2", },
2391 { "lvs2", 0x8100, "vdd_lvs_1_2", },
2392 { }
2393};
2394
2395static const struct spmi_regulator_data pma8084_regulators[] = {
2396 { "s1", 0x1400, "vdd_s1", },
2397 { "s2", 0x1700, "vdd_s2", },
2398 { "s3", 0x1a00, "vdd_s3", },
2399 { "s4", 0x1d00, "vdd_s4", },
2400 { "s5", 0x2000, "vdd_s5", },
2401 { "s6", 0x2300, "vdd_s6", },
2402 { "s7", 0x2600, "vdd_s7", },
2403 { "s8", 0x2900, "vdd_s8", },
2404 { "s9", 0x2c00, "vdd_s9", },
2405 { "s10", 0x2f00, "vdd_s10", },
2406 { "s11", 0x3200, "vdd_s11", },
2407 { "s12", 0x3500, "vdd_s12", },
2408 { "l1", 0x4000, "vdd_l1_l11", },
2409 { "l2", 0x4100, "vdd_l2_l3_l4_l27", },
2410 { "l3", 0x4200, "vdd_l2_l3_l4_l27", },
2411 { "l4", 0x4300, "vdd_l2_l3_l4_l27", },
2412 { "l5", 0x4400, "vdd_l5_l7", },
2413 { "l6", 0x4500, "vdd_l6_l12_l14_l15_l26", },
2414 { "l7", 0x4600, "vdd_l5_l7", },
2415 { "l8", 0x4700, "vdd_l8", },
2416 { "l9", 0x4800, "vdd_l9_l10_l13_l20_l23_l24", },
2417 { "l10", 0x4900, "vdd_l9_l10_l13_l20_l23_l24", },
2418 { "l11", 0x4a00, "vdd_l1_l11", },
2419 { "l12", 0x4b00, "vdd_l6_l12_l14_l15_l26", },
2420 { "l13", 0x4c00, "vdd_l9_l10_l13_l20_l23_l24", },
2421 { "l14", 0x4d00, "vdd_l6_l12_l14_l15_l26", },
2422 { "l15", 0x4e00, "vdd_l6_l12_l14_l15_l26", },
2423 { "l16", 0x4f00, "vdd_l16_l25", },
2424 { "l17", 0x5000, "vdd_l17", },
2425 { "l18", 0x5100, "vdd_l18", },
2426 { "l19", 0x5200, "vdd_l19", },
2427 { "l20", 0x5300, "vdd_l9_l10_l13_l20_l23_l24", },
2428 { "l21", 0x5400, "vdd_l21", },
2429 { "l22", 0x5500, "vdd_l22", },
2430 { "l23", 0x5600, "vdd_l9_l10_l13_l20_l23_l24", },
2431 { "l24", 0x5700, "vdd_l9_l10_l13_l20_l23_l24", },
2432 { "l25", 0x5800, "vdd_l16_l25", },
2433 { "l26", 0x5900, "vdd_l6_l12_l14_l15_l26", },
2434 { "l27", 0x5a00, "vdd_l2_l3_l4_l27", },
2435 { "lvs1", 0x8000, "vdd_lvs1_2", },
2436 { "lvs2", 0x8100, "vdd_lvs1_2", },
2437 { "lvs3", 0x8200, "vdd_lvs3_4", },
2438 { "lvs4", 0x8300, "vdd_lvs3_4", },
2439 { "5vs1", 0x8400, "vdd_5vs1", },
2440 { }
2441};
2442
2443static const struct spmi_regulator_data pmi8994_regulators[] = {
2444 { "s1", 0x1400, "vdd_s1", },
2445 { "s2", 0x1700, "vdd_s2", },
2446 { "s3", 0x1a00, "vdd_s3", },
2447 { "l1", 0x4000, "vdd_l1", },
2448 { }
2449};
2450
2451static const struct spmi_regulator_data pmp8074_regulators[] = {
2452 { "s1", 0x1400, "vdd_s1"},
2453 { "s2", 0x1700, "vdd_s2"},
2454 { "s3", 0x1a00, "vdd_s3"},
2455 { "s4", 0x1d00, "vdd_s4"},
2456 { "s5", 0x2000, "vdd_s5"},
2457 { "l1", 0x4000, "vdd_l1_l2"},
2458 { "l2", 0x4100, "vdd_l1_l2"},
2459 { "l3", 0x4200, "vdd_l3_l8"},
2460 { "l4", 0x4300, "vdd_l4"},
2461 { "l5", 0x4400, "vdd_l5_l6_l15"},
2462 { "l6", 0x4500, "vdd_l5_l6_l15"},
2463 { "l7", 0x4600, "vdd_l7"},
2464 { "l8", 0x4700, "vdd_l3_l8"},
2465 { "l9", 0x4800, "vdd_l9"},
2466 /* l10 is currently unsupported HT_P50 */
2467 { "l11", 0x4a00, "vdd_l10_l11_l12_l13"},
2468 { "l12", 0x4b00, "vdd_l10_l11_l12_l13"},
2469 { "l13", 0x4c00, "vdd_l10_l11_l12_l13"},
2470 { }
2471};
2472
2473static const struct spmi_regulator_data pms405_regulators[] = {
2474 { "s3", 0x1a00, "vdd_s3"},
2475 { }
2476};
2477
2478static const struct of_device_id qcom_spmi_regulator_match[] = {
2479 { .compatible = "qcom,pm6125-regulators", .data = &pm6125_regulators },
2480 { .compatible = "qcom,pm660-regulators", .data = &pm660_regulators },
2481 { .compatible = "qcom,pm660l-regulators", .data = &pm660l_regulators },
2482 { .compatible = "qcom,pm8004-regulators", .data = &pm8004_regulators },
2483 { .compatible = "qcom,pm8005-regulators", .data = &pm8005_regulators },
2484 { .compatible = "qcom,pm8019-regulators", .data = &pm8019_regulators },
2485 { .compatible = "qcom,pm8226-regulators", .data = &pm8226_regulators },
2486 { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators },
2487 { .compatible = "qcom,pm8909-regulators", .data = &pm8909_regulators },
2488 { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators },
2489 { .compatible = "qcom,pm8937-regulators", .data = &pm8937_regulators },
2490 { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators },
2491 { .compatible = "qcom,pm8950-regulators", .data = &pm8950_regulators },
2492 { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators },
2493 { .compatible = "qcom,pma8084-regulators", .data = &pma8084_regulators },
2494 { .compatible = "qcom,pmi8994-regulators", .data = &pmi8994_regulators },
2495 { .compatible = "qcom,pmp8074-regulators", .data = &pmp8074_regulators },
2496 { .compatible = "qcom,pms405-regulators", .data = &pms405_regulators },
2497 { }
2498};
2499MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match);
2500
2501static int qcom_spmi_regulator_probe(struct platform_device *pdev)
2502{
2503 const struct spmi_regulator_data *reg;
2504 const struct spmi_voltage_range *range;
2505 struct regulator_config config = { };
2506 struct regulator_dev *rdev;
2507 struct spmi_regulator *vreg;
2508 struct regmap *regmap;
2509 const char *name;
2510 struct device *dev = &pdev->dev;
2511 struct device_node *node = pdev->dev.of_node;
2512 struct device_node *syscon, *reg_node;
2513 struct property *reg_prop;
2514 int ret, lenp;
2515 struct list_head *vreg_list;
2516
2517 vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL);
2518 if (!vreg_list)
2519 return -ENOMEM;
2520 INIT_LIST_HEAD(vreg_list);
2521 platform_set_drvdata(pdev, vreg_list);
2522
2523 regmap = dev_get_regmap(dev->parent, NULL);
2524 if (!regmap)
2525 return -ENODEV;
2526
2527 reg = device_get_match_data(&pdev->dev);
2528 if (!reg)
2529 return -ENODEV;
2530
2531 syscon = of_parse_phandle(node, "qcom,saw-reg", 0);
2532 if (syscon) {
2533 saw_regmap = syscon_node_to_regmap(syscon);
2534 of_node_put(syscon);
2535 if (IS_ERR(saw_regmap))
2536 dev_err(dev, "ERROR reading SAW regmap\n");
2537 }
2538
2539 for (; reg->name; reg++) {
2540
2541 if (saw_regmap) {
2542 reg_node = of_get_child_by_name(node, reg->name);
2543 reg_prop = of_find_property(reg_node, "qcom,saw-slave",
2544 &lenp);
2545 of_node_put(reg_node);
2546 if (reg_prop)
2547 continue;
2548 }
2549
2550 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
2551 if (!vreg)
2552 return -ENOMEM;
2553
2554 vreg->dev = dev;
2555 vreg->base = reg->base;
2556 vreg->regmap = regmap;
2557 if (reg->ocp) {
2558 vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp);
2559 if (vreg->ocp_irq < 0)
2560 return vreg->ocp_irq;
2561 }
2562 vreg->desc.id = -1;
2563 vreg->desc.owner = THIS_MODULE;
2564 vreg->desc.type = REGULATOR_VOLTAGE;
2565 vreg->desc.enable_reg = reg->base + SPMI_COMMON_REG_ENABLE;
2566 vreg->desc.enable_mask = SPMI_COMMON_ENABLE_MASK;
2567 vreg->desc.enable_val = SPMI_COMMON_ENABLE;
2568 vreg->desc.name = name = reg->name;
2569 vreg->desc.supply_name = reg->supply;
2570 vreg->desc.of_match = reg->name;
2571 vreg->desc.of_parse_cb = spmi_regulator_of_parse;
2572 vreg->desc.of_map_mode = spmi_regulator_of_map_mode;
2573
2574 ret = spmi_regulator_match(vreg, reg->force_type);
2575 if (ret)
2576 continue;
2577
2578 if (saw_regmap) {
2579 reg_node = of_get_child_by_name(node, reg->name);
2580 if (of_property_read_bool(reg_node, "qcom,saw-leader")) {
2581 spmi_saw_ops = *(vreg->desc.ops);
2582 spmi_saw_ops.set_voltage_sel =
2583 spmi_regulator_saw_set_voltage;
2584 vreg->desc.ops = &spmi_saw_ops;
2585 }
2586 of_node_put(reg_node);
2587 }
2588
2589 if (vreg->set_points && vreg->set_points->count == 1) {
2590 /* since there is only one range */
2591 range = vreg->set_points->range;
2592 vreg->desc.uV_step = range->step_uV;
2593 }
2594
2595 config.dev = dev;
2596 config.driver_data = vreg;
2597 config.regmap = regmap;
2598 rdev = devm_regulator_register(dev, &vreg->desc, &config);
2599 if (IS_ERR(rdev)) {
2600 dev_err(dev, "failed to register %s\n", name);
2601 return PTR_ERR(rdev);
2602 }
2603
2604 INIT_LIST_HEAD(&vreg->node);
2605 list_add(&vreg->node, vreg_list);
2606 }
2607
2608 return 0;
2609}
2610
2611static struct platform_driver qcom_spmi_regulator_driver = {
2612 .driver = {
2613 .name = "qcom-spmi-regulator",
2614 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2615 .of_match_table = qcom_spmi_regulator_match,
2616 },
2617 .probe = qcom_spmi_regulator_probe,
2618};
2619module_platform_driver(qcom_spmi_regulator_driver);
2620
2621MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver");
2622MODULE_LICENSE("GPL v2");
2623MODULE_ALIAS("platform:qcom-spmi-regulator");
1/*
2 * Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/delay.h>
16#include <linux/err.h>
17#include <linux/kernel.h>
18#include <linux/interrupt.h>
19#include <linux/bitops.h>
20#include <linux/slab.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/platform_device.h>
24#include <linux/ktime.h>
25#include <linux/regulator/driver.h>
26#include <linux/regmap.h>
27#include <linux/list.h>
28
29/* Pin control enable input pins. */
30#define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
31#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
32#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
33#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
34#define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
35#define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
36
37/* Pin control high power mode input pins. */
38#define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
39#define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
40#define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
41#define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
42#define SPMI_REGULATOR_PIN_CTRL_HPM_EN3 0x08
43#define SPMI_REGULATOR_PIN_CTRL_HPM_SLEEP_B 0x10
44#define SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT 0x20
45
46/*
47 * Used with enable parameters to specify that hardware default register values
48 * should be left unaltered.
49 */
50#define SPMI_REGULATOR_USE_HW_DEFAULT 2
51
52/* Soft start strength of a voltage switch type regulator */
53enum spmi_vs_soft_start_str {
54 SPMI_VS_SOFT_START_STR_0P05_UA = 0,
55 SPMI_VS_SOFT_START_STR_0P25_UA,
56 SPMI_VS_SOFT_START_STR_0P55_UA,
57 SPMI_VS_SOFT_START_STR_0P75_UA,
58 SPMI_VS_SOFT_START_STR_HW_DEFAULT,
59};
60
61/**
62 * struct spmi_regulator_init_data - spmi-regulator initialization data
63 * @pin_ctrl_enable: Bit mask specifying which hardware pins should be
64 * used to enable the regulator, if any
65 * Value should be an ORing of
66 * SPMI_REGULATOR_PIN_CTRL_ENABLE_* constants. If
67 * the bit specified by
68 * SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT is
69 * set, then pin control enable hardware registers
70 * will not be modified.
71 * @pin_ctrl_hpm: Bit mask specifying which hardware pins should be
72 * used to force the regulator into high power
73 * mode, if any
74 * Value should be an ORing of
75 * SPMI_REGULATOR_PIN_CTRL_HPM_* constants. If
76 * the bit specified by
77 * SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT is
78 * set, then pin control mode hardware registers
79 * will not be modified.
80 * @vs_soft_start_strength: This parameter sets the soft start strength for
81 * voltage switch type regulators. Its value
82 * should be one of SPMI_VS_SOFT_START_STR_*. If
83 * its value is SPMI_VS_SOFT_START_STR_HW_DEFAULT,
84 * then the soft start strength will be left at its
85 * default hardware value.
86 */
87struct spmi_regulator_init_data {
88 unsigned pin_ctrl_enable;
89 unsigned pin_ctrl_hpm;
90 enum spmi_vs_soft_start_str vs_soft_start_strength;
91};
92
93/* These types correspond to unique register layouts. */
94enum spmi_regulator_logical_type {
95 SPMI_REGULATOR_LOGICAL_TYPE_SMPS,
96 SPMI_REGULATOR_LOGICAL_TYPE_LDO,
97 SPMI_REGULATOR_LOGICAL_TYPE_VS,
98 SPMI_REGULATOR_LOGICAL_TYPE_BOOST,
99 SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS,
100 SPMI_REGULATOR_LOGICAL_TYPE_BOOST_BYP,
101 SPMI_REGULATOR_LOGICAL_TYPE_LN_LDO,
102 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS,
103 SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS,
104 SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO,
105};
106
107enum spmi_regulator_type {
108 SPMI_REGULATOR_TYPE_BUCK = 0x03,
109 SPMI_REGULATOR_TYPE_LDO = 0x04,
110 SPMI_REGULATOR_TYPE_VS = 0x05,
111 SPMI_REGULATOR_TYPE_BOOST = 0x1b,
112 SPMI_REGULATOR_TYPE_FTS = 0x1c,
113 SPMI_REGULATOR_TYPE_BOOST_BYP = 0x1f,
114 SPMI_REGULATOR_TYPE_ULT_LDO = 0x21,
115 SPMI_REGULATOR_TYPE_ULT_BUCK = 0x22,
116};
117
118enum spmi_regulator_subtype {
119 SPMI_REGULATOR_SUBTYPE_GP_CTL = 0x08,
120 SPMI_REGULATOR_SUBTYPE_RF_CTL = 0x09,
121 SPMI_REGULATOR_SUBTYPE_N50 = 0x01,
122 SPMI_REGULATOR_SUBTYPE_N150 = 0x02,
123 SPMI_REGULATOR_SUBTYPE_N300 = 0x03,
124 SPMI_REGULATOR_SUBTYPE_N600 = 0x04,
125 SPMI_REGULATOR_SUBTYPE_N1200 = 0x05,
126 SPMI_REGULATOR_SUBTYPE_N600_ST = 0x06,
127 SPMI_REGULATOR_SUBTYPE_N1200_ST = 0x07,
128 SPMI_REGULATOR_SUBTYPE_N900_ST = 0x14,
129 SPMI_REGULATOR_SUBTYPE_N300_ST = 0x15,
130 SPMI_REGULATOR_SUBTYPE_P50 = 0x08,
131 SPMI_REGULATOR_SUBTYPE_P150 = 0x09,
132 SPMI_REGULATOR_SUBTYPE_P300 = 0x0a,
133 SPMI_REGULATOR_SUBTYPE_P600 = 0x0b,
134 SPMI_REGULATOR_SUBTYPE_P1200 = 0x0c,
135 SPMI_REGULATOR_SUBTYPE_LN = 0x10,
136 SPMI_REGULATOR_SUBTYPE_LV_P50 = 0x28,
137 SPMI_REGULATOR_SUBTYPE_LV_P150 = 0x29,
138 SPMI_REGULATOR_SUBTYPE_LV_P300 = 0x2a,
139 SPMI_REGULATOR_SUBTYPE_LV_P600 = 0x2b,
140 SPMI_REGULATOR_SUBTYPE_LV_P1200 = 0x2c,
141 SPMI_REGULATOR_SUBTYPE_LV_P450 = 0x2d,
142 SPMI_REGULATOR_SUBTYPE_LV100 = 0x01,
143 SPMI_REGULATOR_SUBTYPE_LV300 = 0x02,
144 SPMI_REGULATOR_SUBTYPE_MV300 = 0x08,
145 SPMI_REGULATOR_SUBTYPE_MV500 = 0x09,
146 SPMI_REGULATOR_SUBTYPE_HDMI = 0x10,
147 SPMI_REGULATOR_SUBTYPE_OTG = 0x11,
148 SPMI_REGULATOR_SUBTYPE_5V_BOOST = 0x01,
149 SPMI_REGULATOR_SUBTYPE_FTS_CTL = 0x08,
150 SPMI_REGULATOR_SUBTYPE_FTS2p5_CTL = 0x09,
151 SPMI_REGULATOR_SUBTYPE_BB_2A = 0x01,
152 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL1 = 0x0d,
153 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL2 = 0x0e,
154 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL3 = 0x0f,
155 SPMI_REGULATOR_SUBTYPE_ULT_HF_CTL4 = 0x10,
156};
157
158enum spmi_common_regulator_registers {
159 SPMI_COMMON_REG_DIG_MAJOR_REV = 0x01,
160 SPMI_COMMON_REG_TYPE = 0x04,
161 SPMI_COMMON_REG_SUBTYPE = 0x05,
162 SPMI_COMMON_REG_VOLTAGE_RANGE = 0x40,
163 SPMI_COMMON_REG_VOLTAGE_SET = 0x41,
164 SPMI_COMMON_REG_MODE = 0x45,
165 SPMI_COMMON_REG_ENABLE = 0x46,
166 SPMI_COMMON_REG_PULL_DOWN = 0x48,
167 SPMI_COMMON_REG_SOFT_START = 0x4c,
168 SPMI_COMMON_REG_STEP_CTRL = 0x61,
169};
170
171enum spmi_vs_registers {
172 SPMI_VS_REG_OCP = 0x4a,
173 SPMI_VS_REG_SOFT_START = 0x4c,
174};
175
176enum spmi_boost_registers {
177 SPMI_BOOST_REG_CURRENT_LIMIT = 0x4a,
178};
179
180enum spmi_boost_byp_registers {
181 SPMI_BOOST_BYP_REG_CURRENT_LIMIT = 0x4b,
182};
183
184/* Used for indexing into ctrl_reg. These are offets from 0x40 */
185enum spmi_common_control_register_index {
186 SPMI_COMMON_IDX_VOLTAGE_RANGE = 0,
187 SPMI_COMMON_IDX_VOLTAGE_SET = 1,
188 SPMI_COMMON_IDX_MODE = 5,
189 SPMI_COMMON_IDX_ENABLE = 6,
190};
191
192/* Common regulator control register layout */
193#define SPMI_COMMON_ENABLE_MASK 0x80
194#define SPMI_COMMON_ENABLE 0x80
195#define SPMI_COMMON_DISABLE 0x00
196#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN3_MASK 0x08
197#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN2_MASK 0x04
198#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN1_MASK 0x02
199#define SPMI_COMMON_ENABLE_FOLLOW_HW_EN0_MASK 0x01
200#define SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK 0x0f
201
202/* Common regulator mode register layout */
203#define SPMI_COMMON_MODE_HPM_MASK 0x80
204#define SPMI_COMMON_MODE_AUTO_MASK 0x40
205#define SPMI_COMMON_MODE_BYPASS_MASK 0x20
206#define SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK 0x10
207#define SPMI_COMMON_MODE_FOLLOW_HW_EN3_MASK 0x08
208#define SPMI_COMMON_MODE_FOLLOW_HW_EN2_MASK 0x04
209#define SPMI_COMMON_MODE_FOLLOW_HW_EN1_MASK 0x02
210#define SPMI_COMMON_MODE_FOLLOW_HW_EN0_MASK 0x01
211#define SPMI_COMMON_MODE_FOLLOW_ALL_MASK 0x1f
212
213/* Common regulator pull down control register layout */
214#define SPMI_COMMON_PULL_DOWN_ENABLE_MASK 0x80
215
216/* LDO regulator current limit control register layout */
217#define SPMI_LDO_CURRENT_LIMIT_ENABLE_MASK 0x80
218
219/* LDO regulator soft start control register layout */
220#define SPMI_LDO_SOFT_START_ENABLE_MASK 0x80
221
222/* VS regulator over current protection control register layout */
223#define SPMI_VS_OCP_OVERRIDE 0x01
224#define SPMI_VS_OCP_NO_OVERRIDE 0x00
225
226/* VS regulator soft start control register layout */
227#define SPMI_VS_SOFT_START_ENABLE_MASK 0x80
228#define SPMI_VS_SOFT_START_SEL_MASK 0x03
229
230/* Boost regulator current limit control register layout */
231#define SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK 0x80
232#define SPMI_BOOST_CURRENT_LIMIT_MASK 0x07
233
234#define SPMI_VS_OCP_DEFAULT_MAX_RETRIES 10
235#define SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS 30
236#define SPMI_VS_OCP_FALL_DELAY_US 90
237#define SPMI_VS_OCP_FAULT_DELAY_US 20000
238
239#define SPMI_FTSMPS_STEP_CTRL_STEP_MASK 0x18
240#define SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT 3
241#define SPMI_FTSMPS_STEP_CTRL_DELAY_MASK 0x07
242#define SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT 0
243
244/* Clock rate in kHz of the FTSMPS regulator reference clock. */
245#define SPMI_FTSMPS_CLOCK_RATE 19200
246
247/* Minimum voltage stepper delay for each step. */
248#define SPMI_FTSMPS_STEP_DELAY 8
249#define SPMI_DEFAULT_STEP_DELAY 20
250
251/*
252 * The ratio SPMI_FTSMPS_STEP_MARGIN_NUM/SPMI_FTSMPS_STEP_MARGIN_DEN is used to
253 * adjust the step rate in order to account for oscillator variance.
254 */
255#define SPMI_FTSMPS_STEP_MARGIN_NUM 4
256#define SPMI_FTSMPS_STEP_MARGIN_DEN 5
257
258/* VSET value to decide the range of ULT SMPS */
259#define ULT_SMPS_RANGE_SPLIT 0x60
260
261/**
262 * struct spmi_voltage_range - regulator set point voltage mapping description
263 * @min_uV: Minimum programmable output voltage resulting from
264 * set point register value 0x00
265 * @max_uV: Maximum programmable output voltage
266 * @step_uV: Output voltage increase resulting from the set point
267 * register value increasing by 1
268 * @set_point_min_uV: Minimum allowed voltage
269 * @set_point_max_uV: Maximum allowed voltage. This may be tweaked in order
270 * to pick which range should be used in the case of
271 * overlapping set points.
272 * @n_voltages: Number of preferred voltage set points present in this
273 * range
274 * @range_sel: Voltage range register value corresponding to this range
275 *
276 * The following relationships must be true for the values used in this struct:
277 * (max_uV - min_uV) % step_uV == 0
278 * (set_point_min_uV - min_uV) % step_uV == 0*
279 * (set_point_max_uV - min_uV) % step_uV == 0*
280 * n_voltages = (set_point_max_uV - set_point_min_uV) / step_uV + 1
281 *
282 * *Note, set_point_min_uV == set_point_max_uV == 0 is allowed in order to
283 * specify that the voltage range has meaning, but is not preferred.
284 */
285struct spmi_voltage_range {
286 int min_uV;
287 int max_uV;
288 int step_uV;
289 int set_point_min_uV;
290 int set_point_max_uV;
291 unsigned n_voltages;
292 u8 range_sel;
293};
294
295/*
296 * The ranges specified in the spmi_voltage_set_points struct must be listed
297 * so that range[i].set_point_max_uV < range[i+1].set_point_min_uV.
298 */
299struct spmi_voltage_set_points {
300 struct spmi_voltage_range *range;
301 int count;
302 unsigned n_voltages;
303};
304
305struct spmi_regulator {
306 struct regulator_desc desc;
307 struct device *dev;
308 struct delayed_work ocp_work;
309 struct regmap *regmap;
310 struct spmi_voltage_set_points *set_points;
311 enum spmi_regulator_logical_type logical_type;
312 int ocp_irq;
313 int ocp_count;
314 int ocp_max_retries;
315 int ocp_retry_delay_ms;
316 int hpm_min_load;
317 int slew_rate;
318 ktime_t vs_enable_time;
319 u16 base;
320 struct list_head node;
321};
322
323struct spmi_regulator_mapping {
324 enum spmi_regulator_type type;
325 enum spmi_regulator_subtype subtype;
326 enum spmi_regulator_logical_type logical_type;
327 u32 revision_min;
328 u32 revision_max;
329 struct regulator_ops *ops;
330 struct spmi_voltage_set_points *set_points;
331 int hpm_min_load;
332};
333
334struct spmi_regulator_data {
335 const char *name;
336 u16 base;
337 const char *supply;
338 const char *ocp;
339 u16 force_type;
340};
341
342#define SPMI_VREG(_type, _subtype, _dig_major_min, _dig_major_max, \
343 _logical_type, _ops_val, _set_points_val, _hpm_min_load) \
344 { \
345 .type = SPMI_REGULATOR_TYPE_##_type, \
346 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
347 .revision_min = _dig_major_min, \
348 .revision_max = _dig_major_max, \
349 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_##_logical_type, \
350 .ops = &spmi_##_ops_val##_ops, \
351 .set_points = &_set_points_val##_set_points, \
352 .hpm_min_load = _hpm_min_load, \
353 }
354
355#define SPMI_VREG_VS(_subtype, _dig_major_min, _dig_major_max) \
356 { \
357 .type = SPMI_REGULATOR_TYPE_VS, \
358 .subtype = SPMI_REGULATOR_SUBTYPE_##_subtype, \
359 .revision_min = _dig_major_min, \
360 .revision_max = _dig_major_max, \
361 .logical_type = SPMI_REGULATOR_LOGICAL_TYPE_VS, \
362 .ops = &spmi_vs_ops, \
363 }
364
365#define SPMI_VOLTAGE_RANGE(_range_sel, _min_uV, _set_point_min_uV, \
366 _set_point_max_uV, _max_uV, _step_uV) \
367 { \
368 .min_uV = _min_uV, \
369 .max_uV = _max_uV, \
370 .set_point_min_uV = _set_point_min_uV, \
371 .set_point_max_uV = _set_point_max_uV, \
372 .step_uV = _step_uV, \
373 .range_sel = _range_sel, \
374 }
375
376#define DEFINE_SPMI_SET_POINTS(name) \
377struct spmi_voltage_set_points name##_set_points = { \
378 .range = name##_ranges, \
379 .count = ARRAY_SIZE(name##_ranges), \
380}
381
382/*
383 * These tables contain the physically available PMIC regulator voltage setpoint
384 * ranges. Where two ranges overlap in hardware, one of the ranges is trimmed
385 * to ensure that the setpoints available to software are monotonically
386 * increasing and unique. The set_voltage callback functions expect these
387 * properties to hold.
388 */
389static struct spmi_voltage_range pldo_ranges[] = {
390 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
391 SPMI_VOLTAGE_RANGE(3, 1500000, 1550000, 3075000, 3075000, 25000),
392 SPMI_VOLTAGE_RANGE(4, 1750000, 3100000, 4900000, 4900000, 50000),
393};
394
395static struct spmi_voltage_range nldo1_ranges[] = {
396 SPMI_VOLTAGE_RANGE(2, 750000, 750000, 1537500, 1537500, 12500),
397};
398
399static struct spmi_voltage_range nldo2_ranges[] = {
400 SPMI_VOLTAGE_RANGE(0, 375000, 0, 0, 1537500, 12500),
401 SPMI_VOLTAGE_RANGE(1, 375000, 375000, 768750, 768750, 6250),
402 SPMI_VOLTAGE_RANGE(2, 750000, 775000, 1537500, 1537500, 12500),
403};
404
405static struct spmi_voltage_range nldo3_ranges[] = {
406 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
407 SPMI_VOLTAGE_RANGE(1, 375000, 0, 0, 1537500, 12500),
408 SPMI_VOLTAGE_RANGE(2, 750000, 0, 0, 1537500, 12500),
409};
410
411static struct spmi_voltage_range ln_ldo_ranges[] = {
412 SPMI_VOLTAGE_RANGE(1, 690000, 690000, 1110000, 1110000, 60000),
413 SPMI_VOLTAGE_RANGE(0, 1380000, 1380000, 2220000, 2220000, 120000),
414};
415
416static struct spmi_voltage_range smps_ranges[] = {
417 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
418 SPMI_VOLTAGE_RANGE(1, 1550000, 1575000, 3125000, 3125000, 25000),
419};
420
421static struct spmi_voltage_range ftsmps_ranges[] = {
422 SPMI_VOLTAGE_RANGE(0, 0, 350000, 1275000, 1275000, 5000),
423 SPMI_VOLTAGE_RANGE(1, 0, 1280000, 2040000, 2040000, 10000),
424};
425
426static struct spmi_voltage_range ftsmps2p5_ranges[] = {
427 SPMI_VOLTAGE_RANGE(0, 80000, 350000, 1355000, 1355000, 5000),
428 SPMI_VOLTAGE_RANGE(1, 160000, 1360000, 2200000, 2200000, 10000),
429};
430
431static struct spmi_voltage_range boost_ranges[] = {
432 SPMI_VOLTAGE_RANGE(0, 4000000, 4000000, 5550000, 5550000, 50000),
433};
434
435static struct spmi_voltage_range boost_byp_ranges[] = {
436 SPMI_VOLTAGE_RANGE(0, 2500000, 2500000, 5200000, 5650000, 50000),
437};
438
439static struct spmi_voltage_range ult_lo_smps_ranges[] = {
440 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1562500, 1562500, 12500),
441 SPMI_VOLTAGE_RANGE(1, 750000, 0, 0, 1525000, 25000),
442};
443
444static struct spmi_voltage_range ult_ho_smps_ranges[] = {
445 SPMI_VOLTAGE_RANGE(0, 1550000, 1550000, 2325000, 2325000, 25000),
446};
447
448static struct spmi_voltage_range ult_nldo_ranges[] = {
449 SPMI_VOLTAGE_RANGE(0, 375000, 375000, 1537500, 1537500, 12500),
450};
451
452static struct spmi_voltage_range ult_pldo_ranges[] = {
453 SPMI_VOLTAGE_RANGE(0, 1750000, 1750000, 3337500, 3337500, 12500),
454};
455
456static DEFINE_SPMI_SET_POINTS(pldo);
457static DEFINE_SPMI_SET_POINTS(nldo1);
458static DEFINE_SPMI_SET_POINTS(nldo2);
459static DEFINE_SPMI_SET_POINTS(nldo3);
460static DEFINE_SPMI_SET_POINTS(ln_ldo);
461static DEFINE_SPMI_SET_POINTS(smps);
462static DEFINE_SPMI_SET_POINTS(ftsmps);
463static DEFINE_SPMI_SET_POINTS(ftsmps2p5);
464static DEFINE_SPMI_SET_POINTS(boost);
465static DEFINE_SPMI_SET_POINTS(boost_byp);
466static DEFINE_SPMI_SET_POINTS(ult_lo_smps);
467static DEFINE_SPMI_SET_POINTS(ult_ho_smps);
468static DEFINE_SPMI_SET_POINTS(ult_nldo);
469static DEFINE_SPMI_SET_POINTS(ult_pldo);
470
471static inline int spmi_vreg_read(struct spmi_regulator *vreg, u16 addr, u8 *buf,
472 int len)
473{
474 return regmap_bulk_read(vreg->regmap, vreg->base + addr, buf, len);
475}
476
477static inline int spmi_vreg_write(struct spmi_regulator *vreg, u16 addr,
478 u8 *buf, int len)
479{
480 return regmap_bulk_write(vreg->regmap, vreg->base + addr, buf, len);
481}
482
483static int spmi_vreg_update_bits(struct spmi_regulator *vreg, u16 addr, u8 val,
484 u8 mask)
485{
486 return regmap_update_bits(vreg->regmap, vreg->base + addr, mask, val);
487}
488
489static int spmi_regulator_common_is_enabled(struct regulator_dev *rdev)
490{
491 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
492 u8 reg;
493
494 spmi_vreg_read(vreg, SPMI_COMMON_REG_ENABLE, ®, 1);
495
496 return (reg & SPMI_COMMON_ENABLE_MASK) == SPMI_COMMON_ENABLE;
497}
498
499static int spmi_regulator_common_enable(struct regulator_dev *rdev)
500{
501 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
502
503 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
504 SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK);
505}
506
507static int spmi_regulator_vs_enable(struct regulator_dev *rdev)
508{
509 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
510
511 if (vreg->ocp_irq) {
512 vreg->ocp_count = 0;
513 vreg->vs_enable_time = ktime_get();
514 }
515
516 return spmi_regulator_common_enable(rdev);
517}
518
519static int spmi_regulator_vs_ocp(struct regulator_dev *rdev)
520{
521 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
522 u8 reg = SPMI_VS_OCP_OVERRIDE;
523
524 return spmi_vreg_write(vreg, SPMI_VS_REG_OCP, ®, 1);
525}
526
527static int spmi_regulator_common_disable(struct regulator_dev *rdev)
528{
529 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
530
531 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
532 SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK);
533}
534
535static int spmi_regulator_select_voltage(struct spmi_regulator *vreg,
536 int min_uV, int max_uV)
537{
538 const struct spmi_voltage_range *range;
539 int uV = min_uV;
540 int lim_min_uV, lim_max_uV, i, range_id, range_max_uV;
541 int selector, voltage_sel;
542
543 /* Check if request voltage is outside of physically settable range. */
544 lim_min_uV = vreg->set_points->range[0].set_point_min_uV;
545 lim_max_uV =
546 vreg->set_points->range[vreg->set_points->count - 1].set_point_max_uV;
547
548 if (uV < lim_min_uV && max_uV >= lim_min_uV)
549 uV = lim_min_uV;
550
551 if (uV < lim_min_uV || uV > lim_max_uV) {
552 dev_err(vreg->dev,
553 "request v=[%d, %d] is outside possible v=[%d, %d]\n",
554 min_uV, max_uV, lim_min_uV, lim_max_uV);
555 return -EINVAL;
556 }
557
558 /* Find the range which uV is inside of. */
559 for (i = vreg->set_points->count - 1; i > 0; i--) {
560 range_max_uV = vreg->set_points->range[i - 1].set_point_max_uV;
561 if (uV > range_max_uV && range_max_uV > 0)
562 break;
563 }
564
565 range_id = i;
566 range = &vreg->set_points->range[range_id];
567
568 /*
569 * Force uV to be an allowed set point by applying a ceiling function to
570 * the uV value.
571 */
572 voltage_sel = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
573 uV = voltage_sel * range->step_uV + range->min_uV;
574
575 if (uV > max_uV) {
576 dev_err(vreg->dev,
577 "request v=[%d, %d] cannot be met by any set point; "
578 "next set point: %d\n",
579 min_uV, max_uV, uV);
580 return -EINVAL;
581 }
582
583 selector = 0;
584 for (i = 0; i < range_id; i++)
585 selector += vreg->set_points->range[i].n_voltages;
586 selector += (uV - range->set_point_min_uV) / range->step_uV;
587
588 return selector;
589}
590
591static int spmi_sw_selector_to_hw(struct spmi_regulator *vreg,
592 unsigned selector, u8 *range_sel,
593 u8 *voltage_sel)
594{
595 const struct spmi_voltage_range *range, *end;
596
597 range = vreg->set_points->range;
598 end = range + vreg->set_points->count;
599
600 for (; range < end; range++) {
601 if (selector < range->n_voltages) {
602 *voltage_sel = selector;
603 *range_sel = range->range_sel;
604 return 0;
605 }
606
607 selector -= range->n_voltages;
608 }
609
610 return -EINVAL;
611}
612
613static int spmi_hw_selector_to_sw(struct spmi_regulator *vreg, u8 hw_sel,
614 const struct spmi_voltage_range *range)
615{
616 int sw_sel = hw_sel;
617 const struct spmi_voltage_range *r = vreg->set_points->range;
618
619 while (r != range) {
620 sw_sel += r->n_voltages;
621 r++;
622 }
623
624 return sw_sel;
625}
626
627static const struct spmi_voltage_range *
628spmi_regulator_find_range(struct spmi_regulator *vreg)
629{
630 u8 range_sel;
631 const struct spmi_voltage_range *range, *end;
632
633 range = vreg->set_points->range;
634 end = range + vreg->set_points->count;
635
636 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, &range_sel, 1);
637
638 for (; range < end; range++)
639 if (range->range_sel == range_sel)
640 return range;
641
642 return NULL;
643}
644
645static int spmi_regulator_select_voltage_same_range(struct spmi_regulator *vreg,
646 int min_uV, int max_uV)
647{
648 const struct spmi_voltage_range *range;
649 int uV = min_uV;
650 int i, selector;
651
652 range = spmi_regulator_find_range(vreg);
653 if (!range)
654 goto different_range;
655
656 if (uV < range->min_uV && max_uV >= range->min_uV)
657 uV = range->min_uV;
658
659 if (uV < range->min_uV || uV > range->max_uV) {
660 /* Current range doesn't support the requested voltage. */
661 goto different_range;
662 }
663
664 /*
665 * Force uV to be an allowed set point by applying a ceiling function to
666 * the uV value.
667 */
668 uV = DIV_ROUND_UP(uV - range->min_uV, range->step_uV);
669 uV = uV * range->step_uV + range->min_uV;
670
671 if (uV > max_uV) {
672 /*
673 * No set point in the current voltage range is within the
674 * requested min_uV to max_uV range.
675 */
676 goto different_range;
677 }
678
679 selector = 0;
680 for (i = 0; i < vreg->set_points->count; i++) {
681 if (uV >= vreg->set_points->range[i].set_point_min_uV
682 && uV <= vreg->set_points->range[i].set_point_max_uV) {
683 selector +=
684 (uV - vreg->set_points->range[i].set_point_min_uV)
685 / vreg->set_points->range[i].step_uV;
686 break;
687 }
688
689 selector += vreg->set_points->range[i].n_voltages;
690 }
691
692 if (selector >= vreg->set_points->n_voltages)
693 goto different_range;
694
695 return selector;
696
697different_range:
698 return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
699}
700
701static int spmi_regulator_common_map_voltage(struct regulator_dev *rdev,
702 int min_uV, int max_uV)
703{
704 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
705
706 /*
707 * Favor staying in the current voltage range if possible. This avoids
708 * voltage spikes that occur when changing the voltage range.
709 */
710 return spmi_regulator_select_voltage_same_range(vreg, min_uV, max_uV);
711}
712
713static int
714spmi_regulator_common_set_voltage(struct regulator_dev *rdev, unsigned selector)
715{
716 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
717 int ret;
718 u8 buf[2];
719 u8 range_sel, voltage_sel;
720
721 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
722 if (ret)
723 return ret;
724
725 buf[0] = range_sel;
726 buf[1] = voltage_sel;
727 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, buf, 2);
728}
729
730static int spmi_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
731 unsigned int old_selector, unsigned int new_selector)
732{
733 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
734 const struct spmi_voltage_range *range;
735 int diff_uV;
736
737 range = spmi_regulator_find_range(vreg);
738 if (!range)
739 return -EINVAL;
740
741 diff_uV = abs(new_selector - old_selector) * range->step_uV;
742
743 return DIV_ROUND_UP(diff_uV, vreg->slew_rate);
744}
745
746static int spmi_regulator_common_get_voltage(struct regulator_dev *rdev)
747{
748 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
749 const struct spmi_voltage_range *range;
750 u8 voltage_sel;
751
752 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
753
754 range = spmi_regulator_find_range(vreg);
755 if (!range)
756 return -EINVAL;
757
758 return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
759}
760
761static int spmi_regulator_single_map_voltage(struct regulator_dev *rdev,
762 int min_uV, int max_uV)
763{
764 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
765
766 return spmi_regulator_select_voltage(vreg, min_uV, max_uV);
767}
768
769static int spmi_regulator_single_range_set_voltage(struct regulator_dev *rdev,
770 unsigned selector)
771{
772 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
773 u8 sel = selector;
774
775 /*
776 * Certain types of regulators do not have a range select register so
777 * only voltage set register needs to be written.
778 */
779 return spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &sel, 1);
780}
781
782static int spmi_regulator_single_range_get_voltage(struct regulator_dev *rdev)
783{
784 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
785 u8 selector;
786 int ret;
787
788 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &selector, 1);
789 if (ret)
790 return ret;
791
792 return selector;
793}
794
795static int spmi_regulator_ult_lo_smps_set_voltage(struct regulator_dev *rdev,
796 unsigned selector)
797{
798 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
799 int ret;
800 u8 range_sel, voltage_sel;
801
802 ret = spmi_sw_selector_to_hw(vreg, selector, &range_sel, &voltage_sel);
803 if (ret)
804 return ret;
805
806 /*
807 * Calculate VSET based on range
808 * In case of range 0: voltage_sel is a 7 bit value, can be written
809 * witout any modification.
810 * In case of range 1: voltage_sel is a 5 bit value, bits[7-5] set to
811 * [011].
812 */
813 if (range_sel == 1)
814 voltage_sel |= ULT_SMPS_RANGE_SPLIT;
815
816 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_VOLTAGE_SET,
817 voltage_sel, 0xff);
818}
819
820static int spmi_regulator_ult_lo_smps_get_voltage(struct regulator_dev *rdev)
821{
822 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
823 const struct spmi_voltage_range *range;
824 u8 voltage_sel;
825
826 spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_SET, &voltage_sel, 1);
827
828 range = spmi_regulator_find_range(vreg);
829 if (!range)
830 return -EINVAL;
831
832 if (range->range_sel == 1)
833 voltage_sel &= ~ULT_SMPS_RANGE_SPLIT;
834
835 return spmi_hw_selector_to_sw(vreg, voltage_sel, range);
836}
837
838static int spmi_regulator_common_list_voltage(struct regulator_dev *rdev,
839 unsigned selector)
840{
841 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
842 int uV = 0;
843 int i;
844
845 if (selector >= vreg->set_points->n_voltages)
846 return 0;
847
848 for (i = 0; i < vreg->set_points->count; i++) {
849 if (selector < vreg->set_points->range[i].n_voltages) {
850 uV = selector * vreg->set_points->range[i].step_uV
851 + vreg->set_points->range[i].set_point_min_uV;
852 break;
853 }
854
855 selector -= vreg->set_points->range[i].n_voltages;
856 }
857
858 return uV;
859}
860
861static int
862spmi_regulator_common_set_bypass(struct regulator_dev *rdev, bool enable)
863{
864 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
865 u8 mask = SPMI_COMMON_MODE_BYPASS_MASK;
866 u8 val = 0;
867
868 if (enable)
869 val = mask;
870
871 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
872}
873
874static int
875spmi_regulator_common_get_bypass(struct regulator_dev *rdev, bool *enable)
876{
877 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
878 u8 val;
879 int ret;
880
881 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, &val, 1);
882 *enable = val & SPMI_COMMON_MODE_BYPASS_MASK;
883
884 return ret;
885}
886
887static unsigned int spmi_regulator_common_get_mode(struct regulator_dev *rdev)
888{
889 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
890 u8 reg;
891
892 spmi_vreg_read(vreg, SPMI_COMMON_REG_MODE, ®, 1);
893
894 if (reg & SPMI_COMMON_MODE_HPM_MASK)
895 return REGULATOR_MODE_NORMAL;
896
897 if (reg & SPMI_COMMON_MODE_AUTO_MASK)
898 return REGULATOR_MODE_FAST;
899
900 return REGULATOR_MODE_IDLE;
901}
902
903static int
904spmi_regulator_common_set_mode(struct regulator_dev *rdev, unsigned int mode)
905{
906 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
907 u8 mask = SPMI_COMMON_MODE_HPM_MASK | SPMI_COMMON_MODE_AUTO_MASK;
908 u8 val = 0;
909
910 if (mode == REGULATOR_MODE_NORMAL)
911 val = SPMI_COMMON_MODE_HPM_MASK;
912 else if (mode == REGULATOR_MODE_FAST)
913 val = SPMI_COMMON_MODE_AUTO_MASK;
914
915 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_MODE, val, mask);
916}
917
918static int
919spmi_regulator_common_set_load(struct regulator_dev *rdev, int load_uA)
920{
921 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
922 unsigned int mode;
923
924 if (load_uA >= vreg->hpm_min_load)
925 mode = REGULATOR_MODE_NORMAL;
926 else
927 mode = REGULATOR_MODE_IDLE;
928
929 return spmi_regulator_common_set_mode(rdev, mode);
930}
931
932static int spmi_regulator_common_set_pull_down(struct regulator_dev *rdev)
933{
934 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
935 unsigned int mask = SPMI_COMMON_PULL_DOWN_ENABLE_MASK;
936
937 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_PULL_DOWN,
938 mask, mask);
939}
940
941static int spmi_regulator_common_set_soft_start(struct regulator_dev *rdev)
942{
943 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
944 unsigned int mask = SPMI_LDO_SOFT_START_ENABLE_MASK;
945
946 return spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_SOFT_START,
947 mask, mask);
948}
949
950static int spmi_regulator_set_ilim(struct regulator_dev *rdev, int ilim_uA)
951{
952 struct spmi_regulator *vreg = rdev_get_drvdata(rdev);
953 enum spmi_regulator_logical_type type = vreg->logical_type;
954 unsigned int current_reg;
955 u8 reg;
956 u8 mask = SPMI_BOOST_CURRENT_LIMIT_MASK |
957 SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
958 int max = (SPMI_BOOST_CURRENT_LIMIT_MASK + 1) * 500;
959
960 if (type == SPMI_REGULATOR_LOGICAL_TYPE_BOOST)
961 current_reg = SPMI_BOOST_REG_CURRENT_LIMIT;
962 else
963 current_reg = SPMI_BOOST_BYP_REG_CURRENT_LIMIT;
964
965 if (ilim_uA > max || ilim_uA <= 0)
966 return -EINVAL;
967
968 reg = (ilim_uA - 1) / 500;
969 reg |= SPMI_BOOST_CURRENT_LIMIT_ENABLE_MASK;
970
971 return spmi_vreg_update_bits(vreg, current_reg, reg, mask);
972}
973
974static int spmi_regulator_vs_clear_ocp(struct spmi_regulator *vreg)
975{
976 int ret;
977
978 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
979 SPMI_COMMON_DISABLE, SPMI_COMMON_ENABLE_MASK);
980
981 vreg->vs_enable_time = ktime_get();
982
983 ret = spmi_vreg_update_bits(vreg, SPMI_COMMON_REG_ENABLE,
984 SPMI_COMMON_ENABLE, SPMI_COMMON_ENABLE_MASK);
985
986 return ret;
987}
988
989static void spmi_regulator_vs_ocp_work(struct work_struct *work)
990{
991 struct delayed_work *dwork = to_delayed_work(work);
992 struct spmi_regulator *vreg
993 = container_of(dwork, struct spmi_regulator, ocp_work);
994
995 spmi_regulator_vs_clear_ocp(vreg);
996}
997
998static irqreturn_t spmi_regulator_vs_ocp_isr(int irq, void *data)
999{
1000 struct spmi_regulator *vreg = data;
1001 ktime_t ocp_irq_time;
1002 s64 ocp_trigger_delay_us;
1003
1004 ocp_irq_time = ktime_get();
1005 ocp_trigger_delay_us = ktime_us_delta(ocp_irq_time,
1006 vreg->vs_enable_time);
1007
1008 /*
1009 * Reset the OCP count if there is a large delay between switch enable
1010 * and when OCP triggers. This is indicative of a hotplug event as
1011 * opposed to a fault.
1012 */
1013 if (ocp_trigger_delay_us > SPMI_VS_OCP_FAULT_DELAY_US)
1014 vreg->ocp_count = 0;
1015
1016 /* Wait for switch output to settle back to 0 V after OCP triggered. */
1017 udelay(SPMI_VS_OCP_FALL_DELAY_US);
1018
1019 vreg->ocp_count++;
1020
1021 if (vreg->ocp_count == 1) {
1022 /* Immediately clear the over current condition. */
1023 spmi_regulator_vs_clear_ocp(vreg);
1024 } else if (vreg->ocp_count <= vreg->ocp_max_retries) {
1025 /* Schedule the over current clear task to run later. */
1026 schedule_delayed_work(&vreg->ocp_work,
1027 msecs_to_jiffies(vreg->ocp_retry_delay_ms) + 1);
1028 } else {
1029 dev_err(vreg->dev,
1030 "OCP triggered %d times; no further retries\n",
1031 vreg->ocp_count);
1032 }
1033
1034 return IRQ_HANDLED;
1035}
1036
1037static struct regulator_ops spmi_smps_ops = {
1038 .enable = spmi_regulator_common_enable,
1039 .disable = spmi_regulator_common_disable,
1040 .is_enabled = spmi_regulator_common_is_enabled,
1041 .set_voltage_sel = spmi_regulator_common_set_voltage,
1042 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1043 .get_voltage_sel = spmi_regulator_common_get_voltage,
1044 .map_voltage = spmi_regulator_common_map_voltage,
1045 .list_voltage = spmi_regulator_common_list_voltage,
1046 .set_mode = spmi_regulator_common_set_mode,
1047 .get_mode = spmi_regulator_common_get_mode,
1048 .set_load = spmi_regulator_common_set_load,
1049 .set_pull_down = spmi_regulator_common_set_pull_down,
1050};
1051
1052static struct regulator_ops spmi_ldo_ops = {
1053 .enable = spmi_regulator_common_enable,
1054 .disable = spmi_regulator_common_disable,
1055 .is_enabled = spmi_regulator_common_is_enabled,
1056 .set_voltage_sel = spmi_regulator_common_set_voltage,
1057 .get_voltage_sel = spmi_regulator_common_get_voltage,
1058 .map_voltage = spmi_regulator_common_map_voltage,
1059 .list_voltage = spmi_regulator_common_list_voltage,
1060 .set_mode = spmi_regulator_common_set_mode,
1061 .get_mode = spmi_regulator_common_get_mode,
1062 .set_load = spmi_regulator_common_set_load,
1063 .set_bypass = spmi_regulator_common_set_bypass,
1064 .get_bypass = spmi_regulator_common_get_bypass,
1065 .set_pull_down = spmi_regulator_common_set_pull_down,
1066 .set_soft_start = spmi_regulator_common_set_soft_start,
1067};
1068
1069static struct regulator_ops spmi_ln_ldo_ops = {
1070 .enable = spmi_regulator_common_enable,
1071 .disable = spmi_regulator_common_disable,
1072 .is_enabled = spmi_regulator_common_is_enabled,
1073 .set_voltage_sel = spmi_regulator_common_set_voltage,
1074 .get_voltage_sel = spmi_regulator_common_get_voltage,
1075 .map_voltage = spmi_regulator_common_map_voltage,
1076 .list_voltage = spmi_regulator_common_list_voltage,
1077 .set_bypass = spmi_regulator_common_set_bypass,
1078 .get_bypass = spmi_regulator_common_get_bypass,
1079};
1080
1081static struct regulator_ops spmi_vs_ops = {
1082 .enable = spmi_regulator_vs_enable,
1083 .disable = spmi_regulator_common_disable,
1084 .is_enabled = spmi_regulator_common_is_enabled,
1085 .set_pull_down = spmi_regulator_common_set_pull_down,
1086 .set_soft_start = spmi_regulator_common_set_soft_start,
1087 .set_over_current_protection = spmi_regulator_vs_ocp,
1088 .set_mode = spmi_regulator_common_set_mode,
1089 .get_mode = spmi_regulator_common_get_mode,
1090};
1091
1092static struct regulator_ops spmi_boost_ops = {
1093 .enable = spmi_regulator_common_enable,
1094 .disable = spmi_regulator_common_disable,
1095 .is_enabled = spmi_regulator_common_is_enabled,
1096 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1097 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1098 .map_voltage = spmi_regulator_single_map_voltage,
1099 .list_voltage = spmi_regulator_common_list_voltage,
1100 .set_input_current_limit = spmi_regulator_set_ilim,
1101};
1102
1103static struct regulator_ops spmi_ftsmps_ops = {
1104 .enable = spmi_regulator_common_enable,
1105 .disable = spmi_regulator_common_disable,
1106 .is_enabled = spmi_regulator_common_is_enabled,
1107 .set_voltage_sel = spmi_regulator_common_set_voltage,
1108 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1109 .get_voltage_sel = spmi_regulator_common_get_voltage,
1110 .map_voltage = spmi_regulator_common_map_voltage,
1111 .list_voltage = spmi_regulator_common_list_voltage,
1112 .set_mode = spmi_regulator_common_set_mode,
1113 .get_mode = spmi_regulator_common_get_mode,
1114 .set_load = spmi_regulator_common_set_load,
1115 .set_pull_down = spmi_regulator_common_set_pull_down,
1116};
1117
1118static struct regulator_ops spmi_ult_lo_smps_ops = {
1119 .enable = spmi_regulator_common_enable,
1120 .disable = spmi_regulator_common_disable,
1121 .is_enabled = spmi_regulator_common_is_enabled,
1122 .set_voltage_sel = spmi_regulator_ult_lo_smps_set_voltage,
1123 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1124 .get_voltage_sel = spmi_regulator_ult_lo_smps_get_voltage,
1125 .list_voltage = spmi_regulator_common_list_voltage,
1126 .set_mode = spmi_regulator_common_set_mode,
1127 .get_mode = spmi_regulator_common_get_mode,
1128 .set_load = spmi_regulator_common_set_load,
1129 .set_pull_down = spmi_regulator_common_set_pull_down,
1130};
1131
1132static struct regulator_ops spmi_ult_ho_smps_ops = {
1133 .enable = spmi_regulator_common_enable,
1134 .disable = spmi_regulator_common_disable,
1135 .is_enabled = spmi_regulator_common_is_enabled,
1136 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1137 .set_voltage_time_sel = spmi_regulator_set_voltage_time_sel,
1138 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1139 .map_voltage = spmi_regulator_single_map_voltage,
1140 .list_voltage = spmi_regulator_common_list_voltage,
1141 .set_mode = spmi_regulator_common_set_mode,
1142 .get_mode = spmi_regulator_common_get_mode,
1143 .set_load = spmi_regulator_common_set_load,
1144 .set_pull_down = spmi_regulator_common_set_pull_down,
1145};
1146
1147static struct regulator_ops spmi_ult_ldo_ops = {
1148 .enable = spmi_regulator_common_enable,
1149 .disable = spmi_regulator_common_disable,
1150 .is_enabled = spmi_regulator_common_is_enabled,
1151 .set_voltage_sel = spmi_regulator_single_range_set_voltage,
1152 .get_voltage_sel = spmi_regulator_single_range_get_voltage,
1153 .map_voltage = spmi_regulator_single_map_voltage,
1154 .list_voltage = spmi_regulator_common_list_voltage,
1155 .set_mode = spmi_regulator_common_set_mode,
1156 .get_mode = spmi_regulator_common_get_mode,
1157 .set_load = spmi_regulator_common_set_load,
1158 .set_bypass = spmi_regulator_common_set_bypass,
1159 .get_bypass = spmi_regulator_common_get_bypass,
1160 .set_pull_down = spmi_regulator_common_set_pull_down,
1161 .set_soft_start = spmi_regulator_common_set_soft_start,
1162};
1163
1164/* Maximum possible digital major revision value */
1165#define INF 0xFF
1166
1167static const struct spmi_regulator_mapping supported_regulators[] = {
1168 /* type subtype dig_min dig_max ltype ops setpoints hpm_min */
1169 SPMI_VREG(BUCK, GP_CTL, 0, INF, SMPS, smps, smps, 100000),
1170 SPMI_VREG(LDO, N300, 0, INF, LDO, ldo, nldo1, 10000),
1171 SPMI_VREG(LDO, N600, 0, 0, LDO, ldo, nldo2, 10000),
1172 SPMI_VREG(LDO, N1200, 0, 0, LDO, ldo, nldo2, 10000),
1173 SPMI_VREG(LDO, N600, 1, INF, LDO, ldo, nldo3, 10000),
1174 SPMI_VREG(LDO, N1200, 1, INF, LDO, ldo, nldo3, 10000),
1175 SPMI_VREG(LDO, N600_ST, 0, 0, LDO, ldo, nldo2, 10000),
1176 SPMI_VREG(LDO, N1200_ST, 0, 0, LDO, ldo, nldo2, 10000),
1177 SPMI_VREG(LDO, N600_ST, 1, INF, LDO, ldo, nldo3, 10000),
1178 SPMI_VREG(LDO, N1200_ST, 1, INF, LDO, ldo, nldo3, 10000),
1179 SPMI_VREG(LDO, P50, 0, INF, LDO, ldo, pldo, 5000),
1180 SPMI_VREG(LDO, P150, 0, INF, LDO, ldo, pldo, 10000),
1181 SPMI_VREG(LDO, P300, 0, INF, LDO, ldo, pldo, 10000),
1182 SPMI_VREG(LDO, P600, 0, INF, LDO, ldo, pldo, 10000),
1183 SPMI_VREG(LDO, P1200, 0, INF, LDO, ldo, pldo, 10000),
1184 SPMI_VREG(LDO, LN, 0, INF, LN_LDO, ln_ldo, ln_ldo, 0),
1185 SPMI_VREG(LDO, LV_P50, 0, INF, LDO, ldo, pldo, 5000),
1186 SPMI_VREG(LDO, LV_P150, 0, INF, LDO, ldo, pldo, 10000),
1187 SPMI_VREG(LDO, LV_P300, 0, INF, LDO, ldo, pldo, 10000),
1188 SPMI_VREG(LDO, LV_P600, 0, INF, LDO, ldo, pldo, 10000),
1189 SPMI_VREG(LDO, LV_P1200, 0, INF, LDO, ldo, pldo, 10000),
1190 SPMI_VREG_VS(LV100, 0, INF),
1191 SPMI_VREG_VS(LV300, 0, INF),
1192 SPMI_VREG_VS(MV300, 0, INF),
1193 SPMI_VREG_VS(MV500, 0, INF),
1194 SPMI_VREG_VS(HDMI, 0, INF),
1195 SPMI_VREG_VS(OTG, 0, INF),
1196 SPMI_VREG(BOOST, 5V_BOOST, 0, INF, BOOST, boost, boost, 0),
1197 SPMI_VREG(FTS, FTS_CTL, 0, INF, FTSMPS, ftsmps, ftsmps, 100000),
1198 SPMI_VREG(FTS, FTS2p5_CTL, 0, INF, FTSMPS, ftsmps, ftsmps2p5, 100000),
1199 SPMI_VREG(BOOST_BYP, BB_2A, 0, INF, BOOST_BYP, boost, boost_byp, 0),
1200 SPMI_VREG(ULT_BUCK, ULT_HF_CTL1, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1201 ult_lo_smps, 100000),
1202 SPMI_VREG(ULT_BUCK, ULT_HF_CTL2, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1203 ult_lo_smps, 100000),
1204 SPMI_VREG(ULT_BUCK, ULT_HF_CTL3, 0, INF, ULT_LO_SMPS, ult_lo_smps,
1205 ult_lo_smps, 100000),
1206 SPMI_VREG(ULT_BUCK, ULT_HF_CTL4, 0, INF, ULT_HO_SMPS, ult_ho_smps,
1207 ult_ho_smps, 100000),
1208 SPMI_VREG(ULT_LDO, N300_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1209 SPMI_VREG(ULT_LDO, N600_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1210 SPMI_VREG(ULT_LDO, N900_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1211 SPMI_VREG(ULT_LDO, N1200_ST, 0, INF, ULT_LDO, ult_ldo, ult_nldo, 10000),
1212 SPMI_VREG(ULT_LDO, LV_P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1213 SPMI_VREG(ULT_LDO, LV_P300, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1214 SPMI_VREG(ULT_LDO, LV_P450, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1215 SPMI_VREG(ULT_LDO, P600, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1216 SPMI_VREG(ULT_LDO, P150, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 10000),
1217 SPMI_VREG(ULT_LDO, P50, 0, INF, ULT_LDO, ult_ldo, ult_pldo, 5000),
1218};
1219
1220static void spmi_calculate_num_voltages(struct spmi_voltage_set_points *points)
1221{
1222 unsigned int n;
1223 struct spmi_voltage_range *range = points->range;
1224
1225 for (; range < points->range + points->count; range++) {
1226 n = 0;
1227 if (range->set_point_max_uV) {
1228 n = range->set_point_max_uV - range->set_point_min_uV;
1229 n = (n / range->step_uV) + 1;
1230 }
1231 range->n_voltages = n;
1232 points->n_voltages += n;
1233 }
1234}
1235
1236static int spmi_regulator_match(struct spmi_regulator *vreg, u16 force_type)
1237{
1238 const struct spmi_regulator_mapping *mapping;
1239 int ret, i;
1240 u32 dig_major_rev;
1241 u8 version[SPMI_COMMON_REG_SUBTYPE - SPMI_COMMON_REG_DIG_MAJOR_REV + 1];
1242 u8 type, subtype;
1243
1244 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_DIG_MAJOR_REV, version,
1245 ARRAY_SIZE(version));
1246 if (ret) {
1247 dev_dbg(vreg->dev, "could not read version registers\n");
1248 return ret;
1249 }
1250 dig_major_rev = version[SPMI_COMMON_REG_DIG_MAJOR_REV
1251 - SPMI_COMMON_REG_DIG_MAJOR_REV];
1252 if (!force_type) {
1253 type = version[SPMI_COMMON_REG_TYPE -
1254 SPMI_COMMON_REG_DIG_MAJOR_REV];
1255 subtype = version[SPMI_COMMON_REG_SUBTYPE -
1256 SPMI_COMMON_REG_DIG_MAJOR_REV];
1257 } else {
1258 type = force_type >> 8;
1259 subtype = force_type;
1260 }
1261
1262 for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) {
1263 mapping = &supported_regulators[i];
1264 if (mapping->type == type && mapping->subtype == subtype
1265 && mapping->revision_min <= dig_major_rev
1266 && mapping->revision_max >= dig_major_rev)
1267 goto found;
1268 }
1269
1270 dev_err(vreg->dev,
1271 "unsupported regulator: name=%s type=0x%02X, subtype=0x%02X, dig major rev=0x%02X\n",
1272 vreg->desc.name, type, subtype, dig_major_rev);
1273
1274 return -ENODEV;
1275
1276found:
1277 vreg->logical_type = mapping->logical_type;
1278 vreg->set_points = mapping->set_points;
1279 vreg->hpm_min_load = mapping->hpm_min_load;
1280 vreg->desc.ops = mapping->ops;
1281
1282 if (mapping->set_points) {
1283 if (!mapping->set_points->n_voltages)
1284 spmi_calculate_num_voltages(mapping->set_points);
1285 vreg->desc.n_voltages = mapping->set_points->n_voltages;
1286 }
1287
1288 return 0;
1289}
1290
1291static int spmi_regulator_init_slew_rate(struct spmi_regulator *vreg)
1292{
1293 int ret;
1294 u8 reg = 0;
1295 int step, delay, slew_rate, step_delay;
1296 const struct spmi_voltage_range *range;
1297
1298 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_STEP_CTRL, ®, 1);
1299 if (ret) {
1300 dev_err(vreg->dev, "spmi read failed, ret=%d\n", ret);
1301 return ret;
1302 }
1303
1304 range = spmi_regulator_find_range(vreg);
1305 if (!range)
1306 return -EINVAL;
1307
1308 switch (vreg->logical_type) {
1309 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1310 step_delay = SPMI_FTSMPS_STEP_DELAY;
1311 break;
1312 default:
1313 step_delay = SPMI_DEFAULT_STEP_DELAY;
1314 break;
1315 }
1316
1317 step = reg & SPMI_FTSMPS_STEP_CTRL_STEP_MASK;
1318 step >>= SPMI_FTSMPS_STEP_CTRL_STEP_SHIFT;
1319
1320 delay = reg & SPMI_FTSMPS_STEP_CTRL_DELAY_MASK;
1321 delay >>= SPMI_FTSMPS_STEP_CTRL_DELAY_SHIFT;
1322
1323 /* slew_rate has units of uV/us */
1324 slew_rate = SPMI_FTSMPS_CLOCK_RATE * range->step_uV * (1 << step);
1325 slew_rate /= 1000 * (step_delay << delay);
1326 slew_rate *= SPMI_FTSMPS_STEP_MARGIN_NUM;
1327 slew_rate /= SPMI_FTSMPS_STEP_MARGIN_DEN;
1328
1329 /* Ensure that the slew rate is greater than 0 */
1330 vreg->slew_rate = max(slew_rate, 1);
1331
1332 return ret;
1333}
1334
1335static int spmi_regulator_init_registers(struct spmi_regulator *vreg,
1336 const struct spmi_regulator_init_data *data)
1337{
1338 int ret;
1339 enum spmi_regulator_logical_type type;
1340 u8 ctrl_reg[8], reg, mask;
1341
1342 type = vreg->logical_type;
1343
1344 ret = spmi_vreg_read(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1345 if (ret)
1346 return ret;
1347
1348 /* Set up enable pin control. */
1349 if ((type == SPMI_REGULATOR_LOGICAL_TYPE_SMPS
1350 || type == SPMI_REGULATOR_LOGICAL_TYPE_LDO
1351 || type == SPMI_REGULATOR_LOGICAL_TYPE_VS)
1352 && !(data->pin_ctrl_enable
1353 & SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT)) {
1354 ctrl_reg[SPMI_COMMON_IDX_ENABLE] &=
1355 ~SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1356 ctrl_reg[SPMI_COMMON_IDX_ENABLE] |=
1357 data->pin_ctrl_enable & SPMI_COMMON_ENABLE_FOLLOW_ALL_MASK;
1358 }
1359
1360 /* Set up mode pin control. */
1361 if ((type == SPMI_REGULATOR_LOGICAL_TYPE_SMPS
1362 || type == SPMI_REGULATOR_LOGICAL_TYPE_LDO)
1363 && !(data->pin_ctrl_hpm
1364 & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
1365 ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1366 ~SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1367 ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1368 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_ALL_MASK;
1369 }
1370
1371 if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS
1372 && !(data->pin_ctrl_hpm & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
1373 ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1374 ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1375 ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1376 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1377 }
1378
1379 if ((type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS
1380 || type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS
1381 || type == SPMI_REGULATOR_LOGICAL_TYPE_ULT_LDO)
1382 && !(data->pin_ctrl_hpm
1383 & SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT)) {
1384 ctrl_reg[SPMI_COMMON_IDX_MODE] &=
1385 ~SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1386 ctrl_reg[SPMI_COMMON_IDX_MODE] |=
1387 data->pin_ctrl_hpm & SPMI_COMMON_MODE_FOLLOW_AWAKE_MASK;
1388 }
1389
1390 /* Write back any control register values that were modified. */
1391 ret = spmi_vreg_write(vreg, SPMI_COMMON_REG_VOLTAGE_RANGE, ctrl_reg, 8);
1392 if (ret)
1393 return ret;
1394
1395 /* Set soft start strength and over current protection for VS. */
1396 if (type == SPMI_REGULATOR_LOGICAL_TYPE_VS) {
1397 if (data->vs_soft_start_strength
1398 != SPMI_VS_SOFT_START_STR_HW_DEFAULT) {
1399 reg = data->vs_soft_start_strength
1400 & SPMI_VS_SOFT_START_SEL_MASK;
1401 mask = SPMI_VS_SOFT_START_SEL_MASK;
1402 return spmi_vreg_update_bits(vreg,
1403 SPMI_VS_REG_SOFT_START,
1404 reg, mask);
1405 }
1406 }
1407
1408 return 0;
1409}
1410
1411static void spmi_regulator_get_dt_config(struct spmi_regulator *vreg,
1412 struct device_node *node, struct spmi_regulator_init_data *data)
1413{
1414 /*
1415 * Initialize configuration parameters to use hardware default in case
1416 * no value is specified via device tree.
1417 */
1418 data->pin_ctrl_enable = SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT;
1419 data->pin_ctrl_hpm = SPMI_REGULATOR_PIN_CTRL_HPM_HW_DEFAULT;
1420 data->vs_soft_start_strength = SPMI_VS_SOFT_START_STR_HW_DEFAULT;
1421
1422 /* These bindings are optional, so it is okay if they aren't found. */
1423 of_property_read_u32(node, "qcom,ocp-max-retries",
1424 &vreg->ocp_max_retries);
1425 of_property_read_u32(node, "qcom,ocp-retry-delay",
1426 &vreg->ocp_retry_delay_ms);
1427 of_property_read_u32(node, "qcom,pin-ctrl-enable",
1428 &data->pin_ctrl_enable);
1429 of_property_read_u32(node, "qcom,pin-ctrl-hpm", &data->pin_ctrl_hpm);
1430 of_property_read_u32(node, "qcom,vs-soft-start-strength",
1431 &data->vs_soft_start_strength);
1432}
1433
1434static unsigned int spmi_regulator_of_map_mode(unsigned int mode)
1435{
1436 if (mode == 1)
1437 return REGULATOR_MODE_NORMAL;
1438 if (mode == 2)
1439 return REGULATOR_MODE_FAST;
1440
1441 return REGULATOR_MODE_IDLE;
1442}
1443
1444static int spmi_regulator_of_parse(struct device_node *node,
1445 const struct regulator_desc *desc,
1446 struct regulator_config *config)
1447{
1448 struct spmi_regulator_init_data data = { };
1449 struct spmi_regulator *vreg = config->driver_data;
1450 struct device *dev = config->dev;
1451 int ret;
1452
1453 spmi_regulator_get_dt_config(vreg, node, &data);
1454
1455 if (!vreg->ocp_max_retries)
1456 vreg->ocp_max_retries = SPMI_VS_OCP_DEFAULT_MAX_RETRIES;
1457 if (!vreg->ocp_retry_delay_ms)
1458 vreg->ocp_retry_delay_ms = SPMI_VS_OCP_DEFAULT_RETRY_DELAY_MS;
1459
1460 ret = spmi_regulator_init_registers(vreg, &data);
1461 if (ret) {
1462 dev_err(dev, "common initialization failed, ret=%d\n", ret);
1463 return ret;
1464 }
1465
1466 switch (vreg->logical_type) {
1467 case SPMI_REGULATOR_LOGICAL_TYPE_FTSMPS:
1468 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_LO_SMPS:
1469 case SPMI_REGULATOR_LOGICAL_TYPE_ULT_HO_SMPS:
1470 case SPMI_REGULATOR_LOGICAL_TYPE_SMPS:
1471 ret = spmi_regulator_init_slew_rate(vreg);
1472 if (ret)
1473 return ret;
1474 default:
1475 break;
1476 }
1477
1478 if (vreg->logical_type != SPMI_REGULATOR_LOGICAL_TYPE_VS)
1479 vreg->ocp_irq = 0;
1480
1481 if (vreg->ocp_irq) {
1482 ret = devm_request_irq(dev, vreg->ocp_irq,
1483 spmi_regulator_vs_ocp_isr, IRQF_TRIGGER_RISING, "ocp",
1484 vreg);
1485 if (ret < 0) {
1486 dev_err(dev, "failed to request irq %d, ret=%d\n",
1487 vreg->ocp_irq, ret);
1488 return ret;
1489 }
1490
1491 INIT_DELAYED_WORK(&vreg->ocp_work, spmi_regulator_vs_ocp_work);
1492 }
1493
1494 return 0;
1495}
1496
1497static const struct spmi_regulator_data pm8941_regulators[] = {
1498 { "s1", 0x1400, "vdd_s1", },
1499 { "s2", 0x1700, "vdd_s2", },
1500 { "s3", 0x1a00, "vdd_s3", },
1501 { "s4", 0xa000, },
1502 { "l1", 0x4000, "vdd_l1_l3", },
1503 { "l2", 0x4100, "vdd_l2_lvs_1_2_3", },
1504 { "l3", 0x4200, "vdd_l1_l3", },
1505 { "l4", 0x4300, "vdd_l4_l11", },
1506 { "l5", 0x4400, "vdd_l5_l7", NULL, 0x0410 },
1507 { "l6", 0x4500, "vdd_l6_l12_l14_l15", },
1508 { "l7", 0x4600, "vdd_l5_l7", NULL, 0x0410 },
1509 { "l8", 0x4700, "vdd_l8_l16_l18_19", },
1510 { "l9", 0x4800, "vdd_l9_l10_l17_l22", },
1511 { "l10", 0x4900, "vdd_l9_l10_l17_l22", },
1512 { "l11", 0x4a00, "vdd_l4_l11", },
1513 { "l12", 0x4b00, "vdd_l6_l12_l14_l15", },
1514 { "l13", 0x4c00, "vdd_l13_l20_l23_l24", },
1515 { "l14", 0x4d00, "vdd_l6_l12_l14_l15", },
1516 { "l15", 0x4e00, "vdd_l6_l12_l14_l15", },
1517 { "l16", 0x4f00, "vdd_l8_l16_l18_19", },
1518 { "l17", 0x5000, "vdd_l9_l10_l17_l22", },
1519 { "l18", 0x5100, "vdd_l8_l16_l18_19", },
1520 { "l19", 0x5200, "vdd_l8_l16_l18_19", },
1521 { "l20", 0x5300, "vdd_l13_l20_l23_l24", },
1522 { "l21", 0x5400, "vdd_l21", },
1523 { "l22", 0x5500, "vdd_l9_l10_l17_l22", },
1524 { "l23", 0x5600, "vdd_l13_l20_l23_l24", },
1525 { "l24", 0x5700, "vdd_l13_l20_l23_l24", },
1526 { "lvs1", 0x8000, "vdd_l2_lvs_1_2_3", },
1527 { "lvs2", 0x8100, "vdd_l2_lvs_1_2_3", },
1528 { "lvs3", 0x8200, "vdd_l2_lvs_1_2_3", },
1529 { "5vs1", 0x8300, "vin_5vs", "ocp-5vs1", },
1530 { "5vs2", 0x8400, "vin_5vs", "ocp-5vs2", },
1531 { }
1532};
1533
1534static const struct spmi_regulator_data pm8841_regulators[] = {
1535 { "s1", 0x1400, "vdd_s1", },
1536 { "s2", 0x1700, "vdd_s2", NULL, 0x1c08 },
1537 { "s3", 0x1a00, "vdd_s3", },
1538 { "s4", 0x1d00, "vdd_s4", NULL, 0x1c08 },
1539 { "s5", 0x2000, "vdd_s5", NULL, 0x1c08 },
1540 { "s6", 0x2300, "vdd_s6", NULL, 0x1c08 },
1541 { "s7", 0x2600, "vdd_s7", NULL, 0x1c08 },
1542 { "s8", 0x2900, "vdd_s8", NULL, 0x1c08 },
1543 { }
1544};
1545
1546static const struct spmi_regulator_data pm8916_regulators[] = {
1547 { "s1", 0x1400, "vdd_s1", },
1548 { "s2", 0x1700, "vdd_s2", },
1549 { "s3", 0x1a00, "vdd_s3", },
1550 { "s4", 0x1d00, "vdd_s4", },
1551 { "l1", 0x4000, "vdd_l1_l3", },
1552 { "l2", 0x4100, "vdd_l2", },
1553 { "l3", 0x4200, "vdd_l1_l3", },
1554 { "l4", 0x4300, "vdd_l4_l5_l6", },
1555 { "l5", 0x4400, "vdd_l4_l5_l6", },
1556 { "l6", 0x4500, "vdd_l4_l5_l6", },
1557 { "l7", 0x4600, "vdd_l7", },
1558 { "l8", 0x4700, "vdd_l8_l11_l14_l15_l16", },
1559 { "l9", 0x4800, "vdd_l9_l10_l12_l13_l17_l18", },
1560 { "l10", 0x4900, "vdd_l9_l10_l12_l13_l17_l18", },
1561 { "l11", 0x4a00, "vdd_l8_l11_l14_l15_l16", },
1562 { "l12", 0x4b00, "vdd_l9_l10_l12_l13_l17_l18", },
1563 { "l13", 0x4c00, "vdd_l9_l10_l12_l13_l17_l18", },
1564 { "l14", 0x4d00, "vdd_l8_l11_l14_l15_l16", },
1565 { "l15", 0x4e00, "vdd_l8_l11_l14_l15_l16", },
1566 { "l16", 0x4f00, "vdd_l8_l11_l14_l15_l16", },
1567 { "l17", 0x5000, "vdd_l9_l10_l12_l13_l17_l18", },
1568 { "l18", 0x5100, "vdd_l9_l10_l12_l13_l17_l18", },
1569 { }
1570};
1571
1572static const struct spmi_regulator_data pm8994_regulators[] = {
1573 { "s1", 0x1400, "vdd_s1", },
1574 { "s2", 0x1700, "vdd_s2", },
1575 { "s3", 0x1a00, "vdd_s3", },
1576 { "s4", 0x1d00, "vdd_s4", },
1577 { "s5", 0x2000, "vdd_s5", },
1578 { "s6", 0x2300, "vdd_s6", },
1579 { "s7", 0x2600, "vdd_s7", },
1580 { "s8", 0x2900, "vdd_s8", },
1581 { "s9", 0x2c00, "vdd_s9", },
1582 { "s10", 0x2f00, "vdd_s10", },
1583 { "s11", 0x3200, "vdd_s11", },
1584 { "s12", 0x3500, "vdd_s12", },
1585 { "l1", 0x4000, "vdd_l1", },
1586 { "l2", 0x4100, "vdd_l2_l26_l28", },
1587 { "l3", 0x4200, "vdd_l3_l11", },
1588 { "l4", 0x4300, "vdd_l4_l27_l31", },
1589 { "l5", 0x4400, "vdd_l5_l7", },
1590 { "l6", 0x4500, "vdd_l6_l12_l32", },
1591 { "l7", 0x4600, "vdd_l5_l7", },
1592 { "l8", 0x4700, "vdd_l8_l16_l30", },
1593 { "l9", 0x4800, "vdd_l9_l10_l18_l22", },
1594 { "l10", 0x4900, "vdd_l9_l10_l18_l22", },
1595 { "l11", 0x4a00, "vdd_l3_l11", },
1596 { "l12", 0x4b00, "vdd_l6_l12_l32", },
1597 { "l13", 0x4c00, "vdd_l13_l19_l23_l24", },
1598 { "l14", 0x4d00, "vdd_l14_l15", },
1599 { "l15", 0x4e00, "vdd_l14_l15", },
1600 { "l16", 0x4f00, "vdd_l8_l16_l30", },
1601 { "l17", 0x5000, "vdd_l17_l29", },
1602 { "l18", 0x5100, "vdd_l9_l10_l18_l22", },
1603 { "l19", 0x5200, "vdd_l13_l19_l23_l24", },
1604 { "l20", 0x5300, "vdd_l20_l21", },
1605 { "l21", 0x5400, "vdd_l20_l21", },
1606 { "l22", 0x5500, "vdd_l9_l10_l18_l22", },
1607 { "l23", 0x5600, "vdd_l13_l19_l23_l24", },
1608 { "l24", 0x5700, "vdd_l13_l19_l23_l24", },
1609 { "l25", 0x5800, "vdd_l25", },
1610 { "l26", 0x5900, "vdd_l2_l26_l28", },
1611 { "l27", 0x5a00, "vdd_l4_l27_l31", },
1612 { "l28", 0x5b00, "vdd_l2_l26_l28", },
1613 { "l29", 0x5c00, "vdd_l17_l29", },
1614 { "l30", 0x5d00, "vdd_l8_l16_l30", },
1615 { "l31", 0x5e00, "vdd_l4_l27_l31", },
1616 { "l32", 0x5f00, "vdd_l6_l12_l32", },
1617 { "lvs1", 0x8000, "vdd_lvs_1_2", },
1618 { "lvs2", 0x8100, "vdd_lvs_1_2", },
1619 { }
1620};
1621
1622static const struct of_device_id qcom_spmi_regulator_match[] = {
1623 { .compatible = "qcom,pm8841-regulators", .data = &pm8841_regulators },
1624 { .compatible = "qcom,pm8916-regulators", .data = &pm8916_regulators },
1625 { .compatible = "qcom,pm8941-regulators", .data = &pm8941_regulators },
1626 { .compatible = "qcom,pm8994-regulators", .data = &pm8994_regulators },
1627 { }
1628};
1629MODULE_DEVICE_TABLE(of, qcom_spmi_regulator_match);
1630
1631static int qcom_spmi_regulator_probe(struct platform_device *pdev)
1632{
1633 const struct spmi_regulator_data *reg;
1634 const struct of_device_id *match;
1635 struct regulator_config config = { };
1636 struct regulator_dev *rdev;
1637 struct spmi_regulator *vreg;
1638 struct regmap *regmap;
1639 const char *name;
1640 struct device *dev = &pdev->dev;
1641 int ret;
1642 struct list_head *vreg_list;
1643
1644 vreg_list = devm_kzalloc(dev, sizeof(*vreg_list), GFP_KERNEL);
1645 if (!vreg_list)
1646 return -ENOMEM;
1647 INIT_LIST_HEAD(vreg_list);
1648 platform_set_drvdata(pdev, vreg_list);
1649
1650 regmap = dev_get_regmap(dev->parent, NULL);
1651 if (!regmap)
1652 return -ENODEV;
1653
1654 match = of_match_device(qcom_spmi_regulator_match, &pdev->dev);
1655 if (!match)
1656 return -ENODEV;
1657
1658 for (reg = match->data; reg->name; reg++) {
1659 vreg = devm_kzalloc(dev, sizeof(*vreg), GFP_KERNEL);
1660 if (!vreg)
1661 return -ENOMEM;
1662
1663 vreg->dev = dev;
1664 vreg->base = reg->base;
1665 vreg->regmap = regmap;
1666
1667 if (reg->ocp) {
1668 vreg->ocp_irq = platform_get_irq_byname(pdev, reg->ocp);
1669 if (vreg->ocp_irq < 0) {
1670 ret = vreg->ocp_irq;
1671 goto err;
1672 }
1673 }
1674
1675 vreg->desc.id = -1;
1676 vreg->desc.owner = THIS_MODULE;
1677 vreg->desc.type = REGULATOR_VOLTAGE;
1678 vreg->desc.name = name = reg->name;
1679 vreg->desc.supply_name = reg->supply;
1680 vreg->desc.of_match = reg->name;
1681 vreg->desc.of_parse_cb = spmi_regulator_of_parse;
1682 vreg->desc.of_map_mode = spmi_regulator_of_map_mode;
1683
1684 ret = spmi_regulator_match(vreg, reg->force_type);
1685 if (ret)
1686 continue;
1687
1688 config.dev = dev;
1689 config.driver_data = vreg;
1690 rdev = devm_regulator_register(dev, &vreg->desc, &config);
1691 if (IS_ERR(rdev)) {
1692 dev_err(dev, "failed to register %s\n", name);
1693 ret = PTR_ERR(rdev);
1694 goto err;
1695 }
1696
1697 INIT_LIST_HEAD(&vreg->node);
1698 list_add(&vreg->node, vreg_list);
1699 }
1700
1701 return 0;
1702
1703err:
1704 list_for_each_entry(vreg, vreg_list, node)
1705 if (vreg->ocp_irq)
1706 cancel_delayed_work_sync(&vreg->ocp_work);
1707 return ret;
1708}
1709
1710static int qcom_spmi_regulator_remove(struct platform_device *pdev)
1711{
1712 struct spmi_regulator *vreg;
1713 struct list_head *vreg_list = platform_get_drvdata(pdev);
1714
1715 list_for_each_entry(vreg, vreg_list, node)
1716 if (vreg->ocp_irq)
1717 cancel_delayed_work_sync(&vreg->ocp_work);
1718
1719 return 0;
1720}
1721
1722static struct platform_driver qcom_spmi_regulator_driver = {
1723 .driver = {
1724 .name = "qcom-spmi-regulator",
1725 .of_match_table = qcom_spmi_regulator_match,
1726 },
1727 .probe = qcom_spmi_regulator_probe,
1728 .remove = qcom_spmi_regulator_remove,
1729};
1730module_platform_driver(qcom_spmi_regulator_driver);
1731
1732MODULE_DESCRIPTION("Qualcomm SPMI PMIC regulator driver");
1733MODULE_LICENSE("GPL v2");
1734MODULE_ALIAS("platform:qcom-spmi-regulator");