Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI detection and setup code
4 */
5
6#include <linux/kernel.h>
7#include <linux/delay.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/msi.h>
11#include <linux/of_pci.h>
12#include <linux/pci_hotplug.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/cpumask.h>
16#include <linux/aer.h>
17#include <linux/acpi.h>
18#include <linux/hypervisor.h>
19#include <linux/irqdomain.h>
20#include <linux/pm_runtime.h>
21#include <linux/bitfield.h>
22#include "pci.h"
23
24#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
25#define CARDBUS_RESERVE_BUSNR 3
26
27static struct resource busn_resource = {
28 .name = "PCI busn",
29 .start = 0,
30 .end = 255,
31 .flags = IORESOURCE_BUS,
32};
33
34/* Ugh. Need to stop exporting this to modules. */
35LIST_HEAD(pci_root_buses);
36EXPORT_SYMBOL(pci_root_buses);
37
38static LIST_HEAD(pci_domain_busn_res_list);
39
40struct pci_domain_busn_res {
41 struct list_head list;
42 struct resource res;
43 int domain_nr;
44};
45
46static struct resource *get_pci_domain_busn_res(int domain_nr)
47{
48 struct pci_domain_busn_res *r;
49
50 list_for_each_entry(r, &pci_domain_busn_res_list, list)
51 if (r->domain_nr == domain_nr)
52 return &r->res;
53
54 r = kzalloc(sizeof(*r), GFP_KERNEL);
55 if (!r)
56 return NULL;
57
58 r->domain_nr = domain_nr;
59 r->res.start = 0;
60 r->res.end = 0xff;
61 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
62
63 list_add_tail(&r->list, &pci_domain_busn_res_list);
64
65 return &r->res;
66}
67
68/*
69 * Some device drivers need know if PCI is initiated.
70 * Basically, we think PCI is not initiated when there
71 * is no device to be found on the pci_bus_type.
72 */
73int no_pci_devices(void)
74{
75 struct device *dev;
76 int no_devices;
77
78 dev = bus_find_next_device(&pci_bus_type, NULL);
79 no_devices = (dev == NULL);
80 put_device(dev);
81 return no_devices;
82}
83EXPORT_SYMBOL(no_pci_devices);
84
85/*
86 * PCI Bus Class
87 */
88static void release_pcibus_dev(struct device *dev)
89{
90 struct pci_bus *pci_bus = to_pci_bus(dev);
91
92 put_device(pci_bus->bridge);
93 pci_bus_remove_resources(pci_bus);
94 pci_release_bus_of_node(pci_bus);
95 kfree(pci_bus);
96}
97
98static const struct class pcibus_class = {
99 .name = "pci_bus",
100 .dev_release = &release_pcibus_dev,
101 .dev_groups = pcibus_groups,
102};
103
104static int __init pcibus_class_init(void)
105{
106 return class_register(&pcibus_class);
107}
108postcore_initcall(pcibus_class_init);
109
110static u64 pci_size(u64 base, u64 maxbase, u64 mask)
111{
112 u64 size = mask & maxbase; /* Find the significant bits */
113 if (!size)
114 return 0;
115
116 /*
117 * Get the lowest of them to find the decode size, and from that
118 * the extent.
119 */
120 size = size & ~(size-1);
121
122 /*
123 * base == maxbase can be valid only if the BAR has already been
124 * programmed with all 1s.
125 */
126 if (base == maxbase && ((base | (size - 1)) & mask) != mask)
127 return 0;
128
129 return size;
130}
131
132static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
133{
134 u32 mem_type;
135 unsigned long flags;
136
137 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
138 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
139 flags |= IORESOURCE_IO;
140 return flags;
141 }
142
143 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
144 flags |= IORESOURCE_MEM;
145 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
146 flags |= IORESOURCE_PREFETCH;
147
148 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
149 switch (mem_type) {
150 case PCI_BASE_ADDRESS_MEM_TYPE_32:
151 break;
152 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
153 /* 1M mem BAR treated as 32-bit BAR */
154 break;
155 case PCI_BASE_ADDRESS_MEM_TYPE_64:
156 flags |= IORESOURCE_MEM_64;
157 break;
158 default:
159 /* mem unknown type treated as 32-bit BAR */
160 break;
161 }
162 return flags;
163}
164
165#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
166
167/**
168 * __pci_read_base - Read a PCI BAR
169 * @dev: the PCI device
170 * @type: type of the BAR
171 * @res: resource buffer to be filled in
172 * @pos: BAR position in the config space
173 *
174 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
175 */
176int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
177 struct resource *res, unsigned int pos)
178{
179 u32 l = 0, sz = 0, mask;
180 u64 l64, sz64, mask64;
181 u16 orig_cmd;
182 struct pci_bus_region region, inverted_region;
183 const char *res_name = pci_resource_name(dev, res - dev->resource);
184
185 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
186
187 /* No printks while decoding is disabled! */
188 if (!dev->mmio_always_on) {
189 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
190 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
191 pci_write_config_word(dev, PCI_COMMAND,
192 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
193 }
194 }
195
196 res->name = pci_name(dev);
197
198 pci_read_config_dword(dev, pos, &l);
199 pci_write_config_dword(dev, pos, l | mask);
200 pci_read_config_dword(dev, pos, &sz);
201 pci_write_config_dword(dev, pos, l);
202
203 /*
204 * All bits set in sz means the device isn't working properly.
205 * If the BAR isn't implemented, all bits must be 0. If it's a
206 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
207 * 1 must be clear.
208 */
209 if (PCI_POSSIBLE_ERROR(sz))
210 sz = 0;
211
212 /*
213 * I don't know how l can have all bits set. Copied from old code.
214 * Maybe it fixes a bug on some ancient platform.
215 */
216 if (PCI_POSSIBLE_ERROR(l))
217 l = 0;
218
219 if (type == pci_bar_unknown) {
220 res->flags = decode_bar(dev, l);
221 res->flags |= IORESOURCE_SIZEALIGN;
222 if (res->flags & IORESOURCE_IO) {
223 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
224 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
225 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
226 } else {
227 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
228 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
229 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
230 }
231 } else {
232 if (l & PCI_ROM_ADDRESS_ENABLE)
233 res->flags |= IORESOURCE_ROM_ENABLE;
234 l64 = l & PCI_ROM_ADDRESS_MASK;
235 sz64 = sz & PCI_ROM_ADDRESS_MASK;
236 mask64 = PCI_ROM_ADDRESS_MASK;
237 }
238
239 if (res->flags & IORESOURCE_MEM_64) {
240 pci_read_config_dword(dev, pos + 4, &l);
241 pci_write_config_dword(dev, pos + 4, ~0);
242 pci_read_config_dword(dev, pos + 4, &sz);
243 pci_write_config_dword(dev, pos + 4, l);
244
245 l64 |= ((u64)l << 32);
246 sz64 |= ((u64)sz << 32);
247 mask64 |= ((u64)~0 << 32);
248 }
249
250 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
251 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
252
253 if (!sz64)
254 goto fail;
255
256 sz64 = pci_size(l64, sz64, mask64);
257 if (!sz64) {
258 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name);
259 goto fail;
260 }
261
262 if (res->flags & IORESOURCE_MEM_64) {
263 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
264 && sz64 > 0x100000000ULL) {
265 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
266 res->start = 0;
267 res->end = 0;
268 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n",
269 res_name, (unsigned long long)sz64);
270 goto out;
271 }
272
273 if ((sizeof(pci_bus_addr_t) < 8) && l) {
274 /* Above 32-bit boundary; try to reallocate */
275 res->flags |= IORESOURCE_UNSET;
276 res->start = 0;
277 res->end = sz64 - 1;
278 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n",
279 res_name, (unsigned long long)l64);
280 goto out;
281 }
282 }
283
284 region.start = l64;
285 region.end = l64 + sz64 - 1;
286
287 pcibios_bus_to_resource(dev->bus, res, ®ion);
288 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
289
290 /*
291 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
292 * the corresponding resource address (the physical address used by
293 * the CPU. Converting that resource address back to a bus address
294 * should yield the original BAR value:
295 *
296 * resource_to_bus(bus_to_resource(A)) == A
297 *
298 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
299 * be claimed by the device.
300 */
301 if (inverted_region.start != region.start) {
302 res->flags |= IORESOURCE_UNSET;
303 res->start = 0;
304 res->end = region.end - region.start;
305 pci_info(dev, "%s: initial BAR value %#010llx invalid\n",
306 res_name, (unsigned long long)region.start);
307 }
308
309 goto out;
310
311
312fail:
313 res->flags = 0;
314out:
315 if (res->flags)
316 pci_info(dev, "%s %pR\n", res_name, res);
317
318 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
319}
320
321static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
322{
323 unsigned int pos, reg;
324
325 if (dev->non_compliant_bars)
326 return;
327
328 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */
329 if (dev->is_virtfn)
330 return;
331
332 for (pos = 0; pos < howmany; pos++) {
333 struct resource *res = &dev->resource[pos];
334 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
335 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
336 }
337
338 if (rom) {
339 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
340 dev->rom_base_reg = rom;
341 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
342 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
343 __pci_read_base(dev, pci_bar_mem32, res, rom);
344 }
345}
346
347static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res,
348 bool log)
349{
350 u8 io_base_lo, io_limit_lo;
351 unsigned long io_mask, io_granularity, base, limit;
352 struct pci_bus_region region;
353
354 io_mask = PCI_IO_RANGE_MASK;
355 io_granularity = 0x1000;
356 if (dev->io_window_1k) {
357 /* Support 1K I/O space granularity */
358 io_mask = PCI_IO_1K_RANGE_MASK;
359 io_granularity = 0x400;
360 }
361
362 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
363 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
364 base = (io_base_lo & io_mask) << 8;
365 limit = (io_limit_lo & io_mask) << 8;
366
367 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
368 u16 io_base_hi, io_limit_hi;
369
370 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
371 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
372 base |= ((unsigned long) io_base_hi << 16);
373 limit |= ((unsigned long) io_limit_hi << 16);
374 }
375
376 if (base <= limit) {
377 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
378 region.start = base;
379 region.end = limit + io_granularity - 1;
380 pcibios_bus_to_resource(dev->bus, res, ®ion);
381 if (log)
382 pci_info(dev, " bridge window %pR\n", res);
383 }
384}
385
386static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res,
387 bool log)
388{
389 u16 mem_base_lo, mem_limit_lo;
390 unsigned long base, limit;
391 struct pci_bus_region region;
392
393 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
394 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
395 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
396 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
397 if (base <= limit) {
398 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
399 region.start = base;
400 region.end = limit + 0xfffff;
401 pcibios_bus_to_resource(dev->bus, res, ®ion);
402 if (log)
403 pci_info(dev, " bridge window %pR\n", res);
404 }
405}
406
407static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res,
408 bool log)
409{
410 u16 mem_base_lo, mem_limit_lo;
411 u64 base64, limit64;
412 pci_bus_addr_t base, limit;
413 struct pci_bus_region region;
414
415 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
416 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
417 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
418 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
419
420 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
421 u32 mem_base_hi, mem_limit_hi;
422
423 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
424 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
425
426 /*
427 * Some bridges set the base > limit by default, and some
428 * (broken) BIOSes do not initialize them. If we find
429 * this, just assume they are not being used.
430 */
431 if (mem_base_hi <= mem_limit_hi) {
432 base64 |= (u64) mem_base_hi << 32;
433 limit64 |= (u64) mem_limit_hi << 32;
434 }
435 }
436
437 base = (pci_bus_addr_t) base64;
438 limit = (pci_bus_addr_t) limit64;
439
440 if (base != base64) {
441 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
442 (unsigned long long) base64);
443 return;
444 }
445
446 if (base <= limit) {
447 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
448 IORESOURCE_MEM | IORESOURCE_PREFETCH;
449 if (res->flags & PCI_PREF_RANGE_TYPE_64)
450 res->flags |= IORESOURCE_MEM_64;
451 region.start = base;
452 region.end = limit + 0xfffff;
453 pcibios_bus_to_resource(dev->bus, res, ®ion);
454 if (log)
455 pci_info(dev, " bridge window %pR\n", res);
456 }
457}
458
459static void pci_read_bridge_windows(struct pci_dev *bridge)
460{
461 u32 buses;
462 u16 io;
463 u32 pmem, tmp;
464 struct resource res;
465
466 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses);
467 res.flags = IORESOURCE_BUS;
468 res.start = (buses >> 8) & 0xff;
469 res.end = (buses >> 16) & 0xff;
470 pci_info(bridge, "PCI bridge to %pR%s\n", &res,
471 bridge->transparent ? " (subtractive decode)" : "");
472
473 pci_read_config_word(bridge, PCI_IO_BASE, &io);
474 if (!io) {
475 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
476 pci_read_config_word(bridge, PCI_IO_BASE, &io);
477 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
478 }
479 if (io) {
480 bridge->io_window = 1;
481 pci_read_bridge_io(bridge, &res, true);
482 }
483
484 pci_read_bridge_mmio(bridge, &res, true);
485
486 /*
487 * DECchip 21050 pass 2 errata: the bridge may miss an address
488 * disconnect boundary by one PCI data phase. Workaround: do not
489 * use prefetching on this device.
490 */
491 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
492 return;
493
494 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
495 if (!pmem) {
496 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
497 0xffe0fff0);
498 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
499 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
500 }
501 if (!pmem)
502 return;
503
504 bridge->pref_window = 1;
505
506 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
507
508 /*
509 * Bridge claims to have a 64-bit prefetchable memory
510 * window; verify that the upper bits are actually
511 * writable.
512 */
513 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem);
514 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
515 0xffffffff);
516 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
517 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem);
518 if (tmp)
519 bridge->pref_64_window = 1;
520 }
521
522 pci_read_bridge_mmio_pref(bridge, &res, true);
523}
524
525void pci_read_bridge_bases(struct pci_bus *child)
526{
527 struct pci_dev *dev = child->self;
528 struct resource *res;
529 int i;
530
531 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
532 return;
533
534 pci_info(dev, "PCI bridge to %pR%s\n",
535 &child->busn_res,
536 dev->transparent ? " (subtractive decode)" : "");
537
538 pci_bus_remove_resources(child);
539 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
540 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
541
542 pci_read_bridge_io(child->self, child->resource[0], false);
543 pci_read_bridge_mmio(child->self, child->resource[1], false);
544 pci_read_bridge_mmio_pref(child->self, child->resource[2], false);
545
546 if (!dev->transparent)
547 return;
548
549 pci_bus_for_each_resource(child->parent, res) {
550 if (!res || !res->flags)
551 continue;
552
553 pci_bus_add_resource(child, res);
554 pci_info(dev, " bridge window %pR (subtractive decode)\n", res);
555 }
556}
557
558static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
559{
560 struct pci_bus *b;
561
562 b = kzalloc(sizeof(*b), GFP_KERNEL);
563 if (!b)
564 return NULL;
565
566 INIT_LIST_HEAD(&b->node);
567 INIT_LIST_HEAD(&b->children);
568 INIT_LIST_HEAD(&b->devices);
569 INIT_LIST_HEAD(&b->slots);
570 INIT_LIST_HEAD(&b->resources);
571 b->max_bus_speed = PCI_SPEED_UNKNOWN;
572 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
573#ifdef CONFIG_PCI_DOMAINS_GENERIC
574 if (parent)
575 b->domain_nr = parent->domain_nr;
576#endif
577 return b;
578}
579
580static void pci_release_host_bridge_dev(struct device *dev)
581{
582 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
583
584 if (bridge->release_fn)
585 bridge->release_fn(bridge);
586
587 pci_free_resource_list(&bridge->windows);
588 pci_free_resource_list(&bridge->dma_ranges);
589 kfree(bridge);
590}
591
592static void pci_init_host_bridge(struct pci_host_bridge *bridge)
593{
594 INIT_LIST_HEAD(&bridge->windows);
595 INIT_LIST_HEAD(&bridge->dma_ranges);
596
597 /*
598 * We assume we can manage these PCIe features. Some systems may
599 * reserve these for use by the platform itself, e.g., an ACPI BIOS
600 * may implement its own AER handling and use _OSC to prevent the
601 * OS from interfering.
602 */
603 bridge->native_aer = 1;
604 bridge->native_pcie_hotplug = 1;
605 bridge->native_shpc_hotplug = 1;
606 bridge->native_pme = 1;
607 bridge->native_ltr = 1;
608 bridge->native_dpc = 1;
609 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
610 bridge->native_cxl_error = 1;
611
612 device_initialize(&bridge->dev);
613}
614
615struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
616{
617 struct pci_host_bridge *bridge;
618
619 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
620 if (!bridge)
621 return NULL;
622
623 pci_init_host_bridge(bridge);
624 bridge->dev.release = pci_release_host_bridge_dev;
625
626 return bridge;
627}
628EXPORT_SYMBOL(pci_alloc_host_bridge);
629
630static void devm_pci_alloc_host_bridge_release(void *data)
631{
632 pci_free_host_bridge(data);
633}
634
635struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
636 size_t priv)
637{
638 int ret;
639 struct pci_host_bridge *bridge;
640
641 bridge = pci_alloc_host_bridge(priv);
642 if (!bridge)
643 return NULL;
644
645 bridge->dev.parent = dev;
646
647 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release,
648 bridge);
649 if (ret)
650 return NULL;
651
652 ret = devm_of_pci_bridge_init(dev, bridge);
653 if (ret)
654 return NULL;
655
656 return bridge;
657}
658EXPORT_SYMBOL(devm_pci_alloc_host_bridge);
659
660void pci_free_host_bridge(struct pci_host_bridge *bridge)
661{
662 put_device(&bridge->dev);
663}
664EXPORT_SYMBOL(pci_free_host_bridge);
665
666/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */
667static const unsigned char pcix_bus_speed[] = {
668 PCI_SPEED_UNKNOWN, /* 0 */
669 PCI_SPEED_66MHz_PCIX, /* 1 */
670 PCI_SPEED_100MHz_PCIX, /* 2 */
671 PCI_SPEED_133MHz_PCIX, /* 3 */
672 PCI_SPEED_UNKNOWN, /* 4 */
673 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
674 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
675 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
676 PCI_SPEED_UNKNOWN, /* 8 */
677 PCI_SPEED_66MHz_PCIX_266, /* 9 */
678 PCI_SPEED_100MHz_PCIX_266, /* A */
679 PCI_SPEED_133MHz_PCIX_266, /* B */
680 PCI_SPEED_UNKNOWN, /* C */
681 PCI_SPEED_66MHz_PCIX_533, /* D */
682 PCI_SPEED_100MHz_PCIX_533, /* E */
683 PCI_SPEED_133MHz_PCIX_533 /* F */
684};
685
686/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */
687const unsigned char pcie_link_speed[] = {
688 PCI_SPEED_UNKNOWN, /* 0 */
689 PCIE_SPEED_2_5GT, /* 1 */
690 PCIE_SPEED_5_0GT, /* 2 */
691 PCIE_SPEED_8_0GT, /* 3 */
692 PCIE_SPEED_16_0GT, /* 4 */
693 PCIE_SPEED_32_0GT, /* 5 */
694 PCIE_SPEED_64_0GT, /* 6 */
695 PCI_SPEED_UNKNOWN, /* 7 */
696 PCI_SPEED_UNKNOWN, /* 8 */
697 PCI_SPEED_UNKNOWN, /* 9 */
698 PCI_SPEED_UNKNOWN, /* A */
699 PCI_SPEED_UNKNOWN, /* B */
700 PCI_SPEED_UNKNOWN, /* C */
701 PCI_SPEED_UNKNOWN, /* D */
702 PCI_SPEED_UNKNOWN, /* E */
703 PCI_SPEED_UNKNOWN /* F */
704};
705EXPORT_SYMBOL_GPL(pcie_link_speed);
706
707const char *pci_speed_string(enum pci_bus_speed speed)
708{
709 /* Indexed by the pci_bus_speed enum */
710 static const char *speed_strings[] = {
711 "33 MHz PCI", /* 0x00 */
712 "66 MHz PCI", /* 0x01 */
713 "66 MHz PCI-X", /* 0x02 */
714 "100 MHz PCI-X", /* 0x03 */
715 "133 MHz PCI-X", /* 0x04 */
716 NULL, /* 0x05 */
717 NULL, /* 0x06 */
718 NULL, /* 0x07 */
719 NULL, /* 0x08 */
720 "66 MHz PCI-X 266", /* 0x09 */
721 "100 MHz PCI-X 266", /* 0x0a */
722 "133 MHz PCI-X 266", /* 0x0b */
723 "Unknown AGP", /* 0x0c */
724 "1x AGP", /* 0x0d */
725 "2x AGP", /* 0x0e */
726 "4x AGP", /* 0x0f */
727 "8x AGP", /* 0x10 */
728 "66 MHz PCI-X 533", /* 0x11 */
729 "100 MHz PCI-X 533", /* 0x12 */
730 "133 MHz PCI-X 533", /* 0x13 */
731 "2.5 GT/s PCIe", /* 0x14 */
732 "5.0 GT/s PCIe", /* 0x15 */
733 "8.0 GT/s PCIe", /* 0x16 */
734 "16.0 GT/s PCIe", /* 0x17 */
735 "32.0 GT/s PCIe", /* 0x18 */
736 "64.0 GT/s PCIe", /* 0x19 */
737 };
738
739 if (speed < ARRAY_SIZE(speed_strings))
740 return speed_strings[speed];
741 return "Unknown";
742}
743EXPORT_SYMBOL_GPL(pci_speed_string);
744
745void pcie_update_link_speed(struct pci_bus *bus)
746{
747 struct pci_dev *bridge = bus->self;
748 u16 linksta;
749
750 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
751 __pcie_update_link_speed(bus, linksta);
752}
753EXPORT_SYMBOL_GPL(pcie_update_link_speed);
754
755static unsigned char agp_speeds[] = {
756 AGP_UNKNOWN,
757 AGP_1X,
758 AGP_2X,
759 AGP_4X,
760 AGP_8X
761};
762
763static enum pci_bus_speed agp_speed(int agp3, int agpstat)
764{
765 int index = 0;
766
767 if (agpstat & 4)
768 index = 3;
769 else if (agpstat & 2)
770 index = 2;
771 else if (agpstat & 1)
772 index = 1;
773 else
774 goto out;
775
776 if (agp3) {
777 index += 2;
778 if (index == 5)
779 index = 0;
780 }
781
782 out:
783 return agp_speeds[index];
784}
785
786static void pci_set_bus_speed(struct pci_bus *bus)
787{
788 struct pci_dev *bridge = bus->self;
789 int pos;
790
791 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
792 if (!pos)
793 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
794 if (pos) {
795 u32 agpstat, agpcmd;
796
797 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
798 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
799
800 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
801 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
802 }
803
804 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
805 if (pos) {
806 u16 status;
807 enum pci_bus_speed max;
808
809 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
810 &status);
811
812 if (status & PCI_X_SSTATUS_533MHZ) {
813 max = PCI_SPEED_133MHz_PCIX_533;
814 } else if (status & PCI_X_SSTATUS_266MHZ) {
815 max = PCI_SPEED_133MHz_PCIX_266;
816 } else if (status & PCI_X_SSTATUS_133MHZ) {
817 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
818 max = PCI_SPEED_133MHz_PCIX_ECC;
819 else
820 max = PCI_SPEED_133MHz_PCIX;
821 } else {
822 max = PCI_SPEED_66MHz_PCIX;
823 }
824
825 bus->max_bus_speed = max;
826 bus->cur_bus_speed =
827 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)];
828
829 return;
830 }
831
832 if (pci_is_pcie(bridge)) {
833 u32 linkcap;
834
835 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
836 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
837
838 pcie_update_link_speed(bus);
839 }
840}
841
842static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
843{
844 struct irq_domain *d;
845
846 /* If the host bridge driver sets a MSI domain of the bridge, use it */
847 d = dev_get_msi_domain(bus->bridge);
848
849 /*
850 * Any firmware interface that can resolve the msi_domain
851 * should be called from here.
852 */
853 if (!d)
854 d = pci_host_bridge_of_msi_domain(bus);
855 if (!d)
856 d = pci_host_bridge_acpi_msi_domain(bus);
857
858 /*
859 * If no IRQ domain was found via the OF tree, try looking it up
860 * directly through the fwnode_handle.
861 */
862 if (!d) {
863 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
864
865 if (fwnode)
866 d = irq_find_matching_fwnode(fwnode,
867 DOMAIN_BUS_PCI_MSI);
868 }
869
870 return d;
871}
872
873static void pci_set_bus_msi_domain(struct pci_bus *bus)
874{
875 struct irq_domain *d;
876 struct pci_bus *b;
877
878 /*
879 * The bus can be a root bus, a subordinate bus, or a virtual bus
880 * created by an SR-IOV device. Walk up to the first bridge device
881 * found or derive the domain from the host bridge.
882 */
883 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
884 if (b->self)
885 d = dev_get_msi_domain(&b->self->dev);
886 }
887
888 if (!d)
889 d = pci_host_bridge_msi_domain(b);
890
891 dev_set_msi_domain(&bus->dev, d);
892}
893
894static bool pci_preserve_config(struct pci_host_bridge *host_bridge)
895{
896 if (pci_acpi_preserve_config(host_bridge))
897 return true;
898
899 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node)
900 return of_pci_preserve_config(host_bridge->dev.parent->of_node);
901
902 return false;
903}
904
905static int pci_register_host_bridge(struct pci_host_bridge *bridge)
906{
907 struct device *parent = bridge->dev.parent;
908 struct resource_entry *window, *next, *n;
909 struct pci_bus *bus, *b;
910 resource_size_t offset, next_offset;
911 LIST_HEAD(resources);
912 struct resource *res, *next_res;
913 char addr[64], *fmt;
914 const char *name;
915 int err;
916
917 bus = pci_alloc_bus(NULL);
918 if (!bus)
919 return -ENOMEM;
920
921 bridge->bus = bus;
922
923 bus->sysdata = bridge->sysdata;
924 bus->ops = bridge->ops;
925 bus->number = bus->busn_res.start = bridge->busnr;
926#ifdef CONFIG_PCI_DOMAINS_GENERIC
927 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET)
928 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
929 else
930 bus->domain_nr = bridge->domain_nr;
931 if (bus->domain_nr < 0) {
932 err = bus->domain_nr;
933 goto free;
934 }
935#endif
936
937 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
938 if (b) {
939 /* Ignore it if we already got here via a different bridge */
940 dev_dbg(&b->dev, "bus already known\n");
941 err = -EEXIST;
942 goto free;
943 }
944
945 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
946 bridge->busnr);
947
948 err = pcibios_root_bridge_prepare(bridge);
949 if (err)
950 goto free;
951
952 /* Temporarily move resources off the list */
953 list_splice_init(&bridge->windows, &resources);
954 err = device_add(&bridge->dev);
955 if (err) {
956 put_device(&bridge->dev);
957 goto free;
958 }
959 bus->bridge = get_device(&bridge->dev);
960 device_enable_async_suspend(bus->bridge);
961 pci_set_bus_of_node(bus);
962 pci_set_bus_msi_domain(bus);
963 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) &&
964 !pci_host_of_has_msi_map(parent))
965 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
966
967 if (!parent)
968 set_dev_node(bus->bridge, pcibus_to_node(bus));
969
970 bus->dev.class = &pcibus_class;
971 bus->dev.parent = bus->bridge;
972
973 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
974 name = dev_name(&bus->dev);
975
976 err = device_register(&bus->dev);
977 if (err)
978 goto unregister;
979
980 pcibios_add_bus(bus);
981
982 if (bus->ops->add_bus) {
983 err = bus->ops->add_bus(bus);
984 if (WARN_ON(err < 0))
985 dev_err(&bus->dev, "failed to add bus: %d\n", err);
986 }
987
988 /* Create legacy_io and legacy_mem files for this bus */
989 pci_create_legacy_files(bus);
990
991 if (parent)
992 dev_info(parent, "PCI host bridge to bus %s\n", name);
993 else
994 pr_info("PCI host bridge to bus %s\n", name);
995
996 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE)
997 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n");
998
999 /* Check if the boot configuration by FW needs to be preserved */
1000 bridge->preserve_config = pci_preserve_config(bridge);
1001
1002 /* Coalesce contiguous windows */
1003 resource_list_for_each_entry_safe(window, n, &resources) {
1004 if (list_is_last(&window->node, &resources))
1005 break;
1006
1007 next = list_next_entry(window, node);
1008 offset = window->offset;
1009 res = window->res;
1010 next_offset = next->offset;
1011 next_res = next->res;
1012
1013 if (res->flags != next_res->flags || offset != next_offset)
1014 continue;
1015
1016 if (res->end + 1 == next_res->start) {
1017 next_res->start = res->start;
1018 res->flags = res->start = res->end = 0;
1019 }
1020 }
1021
1022 /* Add initial resources to the bus */
1023 resource_list_for_each_entry_safe(window, n, &resources) {
1024 offset = window->offset;
1025 res = window->res;
1026 if (!res->flags && !res->start && !res->end) {
1027 release_resource(res);
1028 resource_list_destroy_entry(window);
1029 continue;
1030 }
1031
1032 list_move_tail(&window->node, &bridge->windows);
1033
1034 if (res->flags & IORESOURCE_BUS)
1035 pci_bus_insert_busn_res(bus, bus->number, res->end);
1036 else
1037 pci_bus_add_resource(bus, res);
1038
1039 if (offset) {
1040 if (resource_type(res) == IORESOURCE_IO)
1041 fmt = " (bus address [%#06llx-%#06llx])";
1042 else
1043 fmt = " (bus address [%#010llx-%#010llx])";
1044
1045 snprintf(addr, sizeof(addr), fmt,
1046 (unsigned long long)(res->start - offset),
1047 (unsigned long long)(res->end - offset));
1048 } else
1049 addr[0] = '\0';
1050
1051 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
1052 }
1053
1054 down_write(&pci_bus_sem);
1055 list_add_tail(&bus->node, &pci_root_buses);
1056 up_write(&pci_bus_sem);
1057
1058 return 0;
1059
1060unregister:
1061 put_device(&bridge->dev);
1062 device_del(&bridge->dev);
1063
1064free:
1065#ifdef CONFIG_PCI_DOMAINS_GENERIC
1066 pci_bus_release_domain_nr(parent, bus->domain_nr);
1067#endif
1068 kfree(bus);
1069 return err;
1070}
1071
1072static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge)
1073{
1074 int pos;
1075 u32 status;
1076
1077 /*
1078 * If extended config space isn't accessible on a bridge's primary
1079 * bus, we certainly can't access it on the secondary bus.
1080 */
1081 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1082 return false;
1083
1084 /*
1085 * PCIe Root Ports and switch ports are PCIe on both sides, so if
1086 * extended config space is accessible on the primary, it's also
1087 * accessible on the secondary.
1088 */
1089 if (pci_is_pcie(bridge) &&
1090 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT ||
1091 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM ||
1092 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM))
1093 return true;
1094
1095 /*
1096 * For the other bridge types:
1097 * - PCI-to-PCI bridges
1098 * - PCIe-to-PCI/PCI-X forward bridges
1099 * - PCI/PCI-X-to-PCIe reverse bridges
1100 * extended config space on the secondary side is only accessible
1101 * if the bridge supports PCI-X Mode 2.
1102 */
1103 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
1104 if (!pos)
1105 return false;
1106
1107 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status);
1108 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ);
1109}
1110
1111static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
1112 struct pci_dev *bridge, int busnr)
1113{
1114 struct pci_bus *child;
1115 struct pci_host_bridge *host;
1116 int i;
1117 int ret;
1118
1119 /* Allocate a new bus and inherit stuff from the parent */
1120 child = pci_alloc_bus(parent);
1121 if (!child)
1122 return NULL;
1123
1124 child->parent = parent;
1125 child->sysdata = parent->sysdata;
1126 child->bus_flags = parent->bus_flags;
1127
1128 host = pci_find_host_bridge(parent);
1129 if (host->child_ops)
1130 child->ops = host->child_ops;
1131 else
1132 child->ops = parent->ops;
1133
1134 /*
1135 * Initialize some portions of the bus device, but don't register
1136 * it now as the parent is not properly set up yet.
1137 */
1138 child->dev.class = &pcibus_class;
1139 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
1140
1141 /* Set up the primary, secondary and subordinate bus numbers */
1142 child->number = child->busn_res.start = busnr;
1143 child->primary = parent->busn_res.start;
1144 child->busn_res.end = 0xff;
1145
1146 if (!bridge) {
1147 child->dev.parent = parent->bridge;
1148 goto add_dev;
1149 }
1150
1151 child->self = bridge;
1152 child->bridge = get_device(&bridge->dev);
1153 child->dev.parent = child->bridge;
1154 pci_set_bus_of_node(child);
1155 pci_set_bus_speed(child);
1156
1157 /*
1158 * Check whether extended config space is accessible on the child
1159 * bus. Note that we currently assume it is always accessible on
1160 * the root bus.
1161 */
1162 if (!pci_bridge_child_ext_cfg_accessible(bridge)) {
1163 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG;
1164 pci_info(child, "extended config space not accessible\n");
1165 }
1166
1167 /* Set up default resource pointers and names */
1168 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
1169 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
1170 child->resource[i]->name = child->name;
1171 }
1172 bridge->subordinate = child;
1173
1174add_dev:
1175 pci_set_bus_msi_domain(child);
1176 ret = device_register(&child->dev);
1177 WARN_ON(ret < 0);
1178
1179 pcibios_add_bus(child);
1180
1181 if (child->ops->add_bus) {
1182 ret = child->ops->add_bus(child);
1183 if (WARN_ON(ret < 0))
1184 dev_err(&child->dev, "failed to add bus: %d\n", ret);
1185 }
1186
1187 /* Create legacy_io and legacy_mem files for this bus */
1188 pci_create_legacy_files(child);
1189
1190 return child;
1191}
1192
1193struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
1194 int busnr)
1195{
1196 struct pci_bus *child;
1197
1198 child = pci_alloc_child_bus(parent, dev, busnr);
1199 if (child) {
1200 down_write(&pci_bus_sem);
1201 list_add_tail(&child->node, &parent->children);
1202 up_write(&pci_bus_sem);
1203 }
1204 return child;
1205}
1206EXPORT_SYMBOL(pci_add_new_bus);
1207
1208static void pci_enable_rrs_sv(struct pci_dev *pdev)
1209{
1210 u16 root_cap = 0;
1211
1212 /* Enable Configuration RRS Software Visibility if supported */
1213 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
1214 if (root_cap & PCI_EXP_RTCAP_RRS_SV) {
1215 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
1216 PCI_EXP_RTCTL_RRS_SVE);
1217 pdev->config_rrs_sv = 1;
1218 }
1219}
1220
1221static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
1222 unsigned int available_buses);
1223/**
1224 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus
1225 * numbers from EA capability.
1226 * @dev: Bridge
1227 * @sec: updated with secondary bus number from EA
1228 * @sub: updated with subordinate bus number from EA
1229 *
1230 * If @dev is a bridge with EA capability that specifies valid secondary
1231 * and subordinate bus numbers, return true with the bus numbers in @sec
1232 * and @sub. Otherwise return false.
1233 */
1234static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub)
1235{
1236 int ea, offset;
1237 u32 dw;
1238 u8 ea_sec, ea_sub;
1239
1240 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE)
1241 return false;
1242
1243 /* find PCI EA capability in list */
1244 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
1245 if (!ea)
1246 return false;
1247
1248 offset = ea + PCI_EA_FIRST_ENT;
1249 pci_read_config_dword(dev, offset, &dw);
1250 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw);
1251 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw);
1252 if (ea_sec == 0 || ea_sub < ea_sec)
1253 return false;
1254
1255 *sec = ea_sec;
1256 *sub = ea_sub;
1257 return true;
1258}
1259
1260/*
1261 * pci_scan_bridge_extend() - Scan buses behind a bridge
1262 * @bus: Parent bus the bridge is on
1263 * @dev: Bridge itself
1264 * @max: Starting subordinate number of buses behind this bridge
1265 * @available_buses: Total number of buses available for this bridge and
1266 * the devices below. After the minimal bus space has
1267 * been allocated the remaining buses will be
1268 * distributed equally between hotplug-capable bridges.
1269 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1270 * that need to be reconfigured.
1271 *
1272 * If it's a bridge, configure it and scan the bus behind it.
1273 * For CardBus bridges, we don't scan behind as the devices will
1274 * be handled by the bridge driver itself.
1275 *
1276 * We need to process bridges in two passes -- first we scan those
1277 * already configured by the BIOS and after we are done with all of
1278 * them, we proceed to assigning numbers to the remaining buses in
1279 * order to avoid overlaps between old and new bus numbers.
1280 *
1281 * Return: New subordinate number covering all buses behind this bridge.
1282 */
1283static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev,
1284 int max, unsigned int available_buses,
1285 int pass)
1286{
1287 struct pci_bus *child;
1288 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
1289 u32 buses, i, j = 0;
1290 u16 bctl;
1291 u8 primary, secondary, subordinate;
1292 int broken = 0;
1293 bool fixed_buses;
1294 u8 fixed_sec, fixed_sub;
1295 int next_busnr;
1296
1297 /*
1298 * Make sure the bridge is powered on to be able to access config
1299 * space of devices below it.
1300 */
1301 pm_runtime_get_sync(&dev->dev);
1302
1303 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
1304 primary = buses & 0xFF;
1305 secondary = (buses >> 8) & 0xFF;
1306 subordinate = (buses >> 16) & 0xFF;
1307
1308 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
1309 secondary, subordinate, pass);
1310
1311 if (!primary && (primary != bus->number) && secondary && subordinate) {
1312 pci_warn(dev, "Primary bus is hard wired to 0\n");
1313 primary = bus->number;
1314 }
1315
1316 /* Check if setup is sensible at all */
1317 if (!pass &&
1318 (primary != bus->number || secondary <= bus->number ||
1319 secondary > subordinate)) {
1320 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
1321 secondary, subordinate);
1322 broken = 1;
1323 }
1324
1325 /*
1326 * Disable Master-Abort Mode during probing to avoid reporting of
1327 * bus errors in some architectures.
1328 */
1329 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
1330 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
1331 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
1332
1333 pci_enable_rrs_sv(dev);
1334
1335 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
1336 !is_cardbus && !broken) {
1337 unsigned int cmax, buses;
1338
1339 /*
1340 * Bus already configured by firmware, process it in the
1341 * first pass and just note the configuration.
1342 */
1343 if (pass)
1344 goto out;
1345
1346 /*
1347 * The bus might already exist for two reasons: Either we
1348 * are rescanning the bus or the bus is reachable through
1349 * more than one bridge. The second case can happen with
1350 * the i450NX chipset.
1351 */
1352 child = pci_find_bus(pci_domain_nr(bus), secondary);
1353 if (!child) {
1354 child = pci_add_new_bus(bus, dev, secondary);
1355 if (!child)
1356 goto out;
1357 child->primary = primary;
1358 pci_bus_insert_busn_res(child, secondary, subordinate);
1359 child->bridge_ctl = bctl;
1360 }
1361
1362 buses = subordinate - secondary;
1363 cmax = pci_scan_child_bus_extend(child, buses);
1364 if (cmax > subordinate)
1365 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n",
1366 subordinate, cmax);
1367
1368 /* Subordinate should equal child->busn_res.end */
1369 if (subordinate > max)
1370 max = subordinate;
1371 } else {
1372
1373 /*
1374 * We need to assign a number to this bus which we always
1375 * do in the second pass.
1376 */
1377 if (!pass) {
1378 if (pcibios_assign_all_busses() || broken || is_cardbus)
1379
1380 /*
1381 * Temporarily disable forwarding of the
1382 * configuration cycles on all bridges in
1383 * this bus segment to avoid possible
1384 * conflicts in the second pass between two
1385 * bridges programmed with overlapping bus
1386 * ranges.
1387 */
1388 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1389 buses & ~0xffffff);
1390 goto out;
1391 }
1392
1393 /* Clear errors */
1394 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1395
1396 /* Read bus numbers from EA Capability (if present) */
1397 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub);
1398 if (fixed_buses)
1399 next_busnr = fixed_sec;
1400 else
1401 next_busnr = max + 1;
1402
1403 /*
1404 * Prevent assigning a bus number that already exists.
1405 * This can happen when a bridge is hot-plugged, so in this
1406 * case we only re-scan this bus.
1407 */
1408 child = pci_find_bus(pci_domain_nr(bus), next_busnr);
1409 if (!child) {
1410 child = pci_add_new_bus(bus, dev, next_busnr);
1411 if (!child)
1412 goto out;
1413 pci_bus_insert_busn_res(child, next_busnr,
1414 bus->busn_res.end);
1415 }
1416 max++;
1417 if (available_buses)
1418 available_buses--;
1419
1420 buses = (buses & 0xff000000)
1421 | ((unsigned int)(child->primary) << 0)
1422 | ((unsigned int)(child->busn_res.start) << 8)
1423 | ((unsigned int)(child->busn_res.end) << 16);
1424
1425 /*
1426 * yenta.c forces a secondary latency timer of 176.
1427 * Copy that behaviour here.
1428 */
1429 if (is_cardbus) {
1430 buses &= ~0xff000000;
1431 buses |= CARDBUS_LATENCY_TIMER << 24;
1432 }
1433
1434 /* We need to blast all three values with a single write */
1435 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1436
1437 if (!is_cardbus) {
1438 child->bridge_ctl = bctl;
1439 max = pci_scan_child_bus_extend(child, available_buses);
1440 } else {
1441
1442 /*
1443 * For CardBus bridges, we leave 4 bus numbers as
1444 * cards with a PCI-to-PCI bridge can be inserted
1445 * later.
1446 */
1447 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1448 struct pci_bus *parent = bus;
1449 if (pci_find_bus(pci_domain_nr(bus),
1450 max+i+1))
1451 break;
1452 while (parent->parent) {
1453 if ((!pcibios_assign_all_busses()) &&
1454 (parent->busn_res.end > max) &&
1455 (parent->busn_res.end <= max+i)) {
1456 j = 1;
1457 }
1458 parent = parent->parent;
1459 }
1460 if (j) {
1461
1462 /*
1463 * Often, there are two CardBus
1464 * bridges -- try to leave one
1465 * valid bus number for each one.
1466 */
1467 i /= 2;
1468 break;
1469 }
1470 }
1471 max += i;
1472 }
1473
1474 /*
1475 * Set subordinate bus number to its real value.
1476 * If fixed subordinate bus number exists from EA
1477 * capability then use it.
1478 */
1479 if (fixed_buses)
1480 max = fixed_sub;
1481 pci_bus_update_busn_res_end(child, max);
1482 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1483 }
1484
1485 sprintf(child->name,
1486 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1487 pci_domain_nr(bus), child->number);
1488
1489 /* Check that all devices are accessible */
1490 while (bus->parent) {
1491 if ((child->busn_res.end > bus->busn_res.end) ||
1492 (child->number > bus->busn_res.end) ||
1493 (child->number < bus->number) ||
1494 (child->busn_res.end < bus->number)) {
1495 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n",
1496 &child->busn_res);
1497 break;
1498 }
1499 bus = bus->parent;
1500 }
1501
1502out:
1503 /* Clear errors in the Secondary Status Register */
1504 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff);
1505
1506 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1507
1508 pm_runtime_put(&dev->dev);
1509
1510 return max;
1511}
1512
1513/*
1514 * pci_scan_bridge() - Scan buses behind a bridge
1515 * @bus: Parent bus the bridge is on
1516 * @dev: Bridge itself
1517 * @max: Starting subordinate number of buses behind this bridge
1518 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges
1519 * that need to be reconfigured.
1520 *
1521 * If it's a bridge, configure it and scan the bus behind it.
1522 * For CardBus bridges, we don't scan behind as the devices will
1523 * be handled by the bridge driver itself.
1524 *
1525 * We need to process bridges in two passes -- first we scan those
1526 * already configured by the BIOS and after we are done with all of
1527 * them, we proceed to assigning numbers to the remaining buses in
1528 * order to avoid overlaps between old and new bus numbers.
1529 *
1530 * Return: New subordinate number covering all buses behind this bridge.
1531 */
1532int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
1533{
1534 return pci_scan_bridge_extend(bus, dev, max, 0, pass);
1535}
1536EXPORT_SYMBOL(pci_scan_bridge);
1537
1538/*
1539 * Read interrupt line and base address registers.
1540 * The architecture-dependent code can tweak these, of course.
1541 */
1542static void pci_read_irq(struct pci_dev *dev)
1543{
1544 unsigned char irq;
1545
1546 /* VFs are not allowed to use INTx, so skip the config reads */
1547 if (dev->is_virtfn) {
1548 dev->pin = 0;
1549 dev->irq = 0;
1550 return;
1551 }
1552
1553 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1554 dev->pin = irq;
1555 if (irq)
1556 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1557 dev->irq = irq;
1558}
1559
1560void set_pcie_port_type(struct pci_dev *pdev)
1561{
1562 int pos;
1563 u16 reg16;
1564 u32 reg32;
1565 int type;
1566 struct pci_dev *parent;
1567
1568 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1569 if (!pos)
1570 return;
1571
1572 pdev->pcie_cap = pos;
1573 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1574 pdev->pcie_flags_reg = reg16;
1575 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap);
1576 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap);
1577
1578 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32);
1579 if (reg32 & PCI_EXP_LNKCAP_DLLLARC)
1580 pdev->link_active_reporting = 1;
1581
1582 parent = pci_upstream_bridge(pdev);
1583 if (!parent)
1584 return;
1585
1586 /*
1587 * Some systems do not identify their upstream/downstream ports
1588 * correctly so detect impossible configurations here and correct
1589 * the port type accordingly.
1590 */
1591 type = pci_pcie_type(pdev);
1592 if (type == PCI_EXP_TYPE_DOWNSTREAM) {
1593 /*
1594 * If pdev claims to be downstream port but the parent
1595 * device is also downstream port assume pdev is actually
1596 * upstream port.
1597 */
1598 if (pcie_downstream_port(parent)) {
1599 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n");
1600 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1601 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM;
1602 }
1603 } else if (type == PCI_EXP_TYPE_UPSTREAM) {
1604 /*
1605 * If pdev claims to be upstream port but the parent
1606 * device is also upstream port assume pdev is actually
1607 * downstream port.
1608 */
1609 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) {
1610 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n");
1611 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE;
1612 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM;
1613 }
1614 }
1615}
1616
1617void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1618{
1619 u32 reg32;
1620
1621 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1622 if (reg32 & PCI_EXP_SLTCAP_HPC)
1623 pdev->is_hotplug_bridge = 1;
1624}
1625
1626static void set_pcie_thunderbolt(struct pci_dev *dev)
1627{
1628 u16 vsec;
1629
1630 /* Is the device part of a Thunderbolt controller? */
1631 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT);
1632 if (vsec)
1633 dev->is_thunderbolt = 1;
1634}
1635
1636static void set_pcie_untrusted(struct pci_dev *dev)
1637{
1638 struct pci_dev *parent = pci_upstream_bridge(dev);
1639
1640 if (!parent)
1641 return;
1642 /*
1643 * If the upstream bridge is untrusted we treat this device as
1644 * untrusted as well.
1645 */
1646 if (parent->untrusted) {
1647 dev->untrusted = true;
1648 return;
1649 }
1650
1651 if (arch_pci_dev_is_removable(dev)) {
1652 pci_dbg(dev, "marking as untrusted\n");
1653 dev->untrusted = true;
1654 }
1655}
1656
1657static void pci_set_removable(struct pci_dev *dev)
1658{
1659 struct pci_dev *parent = pci_upstream_bridge(dev);
1660
1661 if (!parent)
1662 return;
1663 /*
1664 * We (only) consider everything tunneled below an external_facing
1665 * device to be removable by the user. We're mainly concerned with
1666 * consumer platforms with user accessible thunderbolt ports that are
1667 * vulnerable to DMA attacks, and we expect those ports to be marked by
1668 * the firmware as external_facing. Devices in traditional hotplug
1669 * slots can technically be removed, but the expectation is that unless
1670 * the port is marked with external_facing, such devices are less
1671 * accessible to user / may not be removed by end user, and thus not
1672 * exposed as "removable" to userspace.
1673 */
1674 if (dev_is_removable(&parent->dev)) {
1675 dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1676 return;
1677 }
1678
1679 if (arch_pci_dev_is_removable(dev)) {
1680 pci_dbg(dev, "marking as removable\n");
1681 dev_set_removable(&dev->dev, DEVICE_REMOVABLE);
1682 }
1683}
1684
1685/**
1686 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config?
1687 * @dev: PCI device
1688 *
1689 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1690 * when forwarding a type1 configuration request the bridge must check that
1691 * the extended register address field is zero. The bridge is not permitted
1692 * to forward the transactions and must handle it as an Unsupported Request.
1693 * Some bridges do not follow this rule and simply drop the extended register
1694 * bits, resulting in the standard config space being aliased, every 256
1695 * bytes across the entire configuration space. Test for this condition by
1696 * comparing the first dword of each potential alias to the vendor/device ID.
1697 * Known offenders:
1698 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1699 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1700 */
1701static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1702{
1703#ifdef CONFIG_PCI_QUIRKS
1704 int pos, ret;
1705 u32 header, tmp;
1706
1707 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1708
1709 for (pos = PCI_CFG_SPACE_SIZE;
1710 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1711 ret = pci_read_config_dword(dev, pos, &tmp);
1712 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp))
1713 return false;
1714 }
1715
1716 return true;
1717#else
1718 return false;
1719#endif
1720}
1721
1722/**
1723 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device
1724 * @dev: PCI device
1725 *
1726 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1727 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1728 * access it. Maybe we don't have a way to generate extended config space
1729 * accesses, or the device is behind a reverse Express bridge. So we try
1730 * reading the dword at 0x100 which must either be 0 or a valid extended
1731 * capability header.
1732 */
1733static int pci_cfg_space_size_ext(struct pci_dev *dev)
1734{
1735 u32 status;
1736 int pos = PCI_CFG_SPACE_SIZE;
1737
1738 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1739 return PCI_CFG_SPACE_SIZE;
1740 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev))
1741 return PCI_CFG_SPACE_SIZE;
1742
1743 return PCI_CFG_SPACE_EXP_SIZE;
1744}
1745
1746int pci_cfg_space_size(struct pci_dev *dev)
1747{
1748 int pos;
1749 u32 status;
1750 u16 class;
1751
1752#ifdef CONFIG_PCI_IOV
1753 /*
1754 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to
1755 * implement a PCIe capability and therefore must implement extended
1756 * config space. We can skip the NO_EXTCFG test below and the
1757 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of
1758 * the fact that the SR-IOV capability on the PF resides in extended
1759 * config space and must be accessible and non-aliased to have enabled
1760 * support for this VF. This is a micro performance optimization for
1761 * systems supporting many VFs.
1762 */
1763 if (dev->is_virtfn)
1764 return PCI_CFG_SPACE_EXP_SIZE;
1765#endif
1766
1767 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG)
1768 return PCI_CFG_SPACE_SIZE;
1769
1770 class = dev->class >> 8;
1771 if (class == PCI_CLASS_BRIDGE_HOST)
1772 return pci_cfg_space_size_ext(dev);
1773
1774 if (pci_is_pcie(dev))
1775 return pci_cfg_space_size_ext(dev);
1776
1777 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1778 if (!pos)
1779 return PCI_CFG_SPACE_SIZE;
1780
1781 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1782 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1783 return pci_cfg_space_size_ext(dev);
1784
1785 return PCI_CFG_SPACE_SIZE;
1786}
1787
1788static u32 pci_class(struct pci_dev *dev)
1789{
1790 u32 class;
1791
1792#ifdef CONFIG_PCI_IOV
1793 if (dev->is_virtfn)
1794 return dev->physfn->sriov->class;
1795#endif
1796 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1797 return class;
1798}
1799
1800static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device)
1801{
1802#ifdef CONFIG_PCI_IOV
1803 if (dev->is_virtfn) {
1804 *vendor = dev->physfn->sriov->subsystem_vendor;
1805 *device = dev->physfn->sriov->subsystem_device;
1806 return;
1807 }
1808#endif
1809 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor);
1810 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device);
1811}
1812
1813static u8 pci_hdr_type(struct pci_dev *dev)
1814{
1815 u8 hdr_type;
1816
1817#ifdef CONFIG_PCI_IOV
1818 if (dev->is_virtfn)
1819 return dev->physfn->sriov->hdr_type;
1820#endif
1821 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
1822 return hdr_type;
1823}
1824
1825#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1826
1827/**
1828 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability
1829 * @dev: PCI device
1830 *
1831 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this
1832 * at enumeration-time to avoid modifying PCI_COMMAND at run-time.
1833 */
1834static int pci_intx_mask_broken(struct pci_dev *dev)
1835{
1836 u16 orig, toggle, new;
1837
1838 pci_read_config_word(dev, PCI_COMMAND, &orig);
1839 toggle = orig ^ PCI_COMMAND_INTX_DISABLE;
1840 pci_write_config_word(dev, PCI_COMMAND, toggle);
1841 pci_read_config_word(dev, PCI_COMMAND, &new);
1842
1843 pci_write_config_word(dev, PCI_COMMAND, orig);
1844
1845 /*
1846 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI
1847 * r2.3, so strictly speaking, a device is not *broken* if it's not
1848 * writable. But we'll live with the misnomer for now.
1849 */
1850 if (new != toggle)
1851 return 1;
1852 return 0;
1853}
1854
1855static void early_dump_pci_device(struct pci_dev *pdev)
1856{
1857 u32 value[256 / 4];
1858 int i;
1859
1860 pci_info(pdev, "config space:\n");
1861
1862 for (i = 0; i < 256; i += 4)
1863 pci_read_config_dword(pdev, i, &value[i / 4]);
1864
1865 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1866 value, 256, false);
1867}
1868
1869static const char *pci_type_str(struct pci_dev *dev)
1870{
1871 static const char * const str[] = {
1872 "PCIe Endpoint",
1873 "PCIe Legacy Endpoint",
1874 "PCIe unknown",
1875 "PCIe unknown",
1876 "PCIe Root Port",
1877 "PCIe Switch Upstream Port",
1878 "PCIe Switch Downstream Port",
1879 "PCIe to PCI/PCI-X bridge",
1880 "PCI/PCI-X to PCIe bridge",
1881 "PCIe Root Complex Integrated Endpoint",
1882 "PCIe Root Complex Event Collector",
1883 };
1884 int type;
1885
1886 if (pci_is_pcie(dev)) {
1887 type = pci_pcie_type(dev);
1888 if (type < ARRAY_SIZE(str))
1889 return str[type];
1890
1891 return "PCIe unknown";
1892 }
1893
1894 switch (dev->hdr_type) {
1895 case PCI_HEADER_TYPE_NORMAL:
1896 return "conventional PCI endpoint";
1897 case PCI_HEADER_TYPE_BRIDGE:
1898 return "conventional PCI bridge";
1899 case PCI_HEADER_TYPE_CARDBUS:
1900 return "CardBus bridge";
1901 default:
1902 return "conventional PCI";
1903 }
1904}
1905
1906/**
1907 * pci_setup_device - Fill in class and map information of a device
1908 * @dev: the device structure to fill
1909 *
1910 * Initialize the device structure with information about the device's
1911 * vendor,class,memory and IO-space addresses, IRQ lines etc.
1912 * Called at initialisation of the PCI subsystem and by CardBus services.
1913 * Returns 0 on success and negative if unknown type of device (not normal,
1914 * bridge or CardBus).
1915 */
1916int pci_setup_device(struct pci_dev *dev)
1917{
1918 u32 class;
1919 u16 cmd;
1920 u8 hdr_type;
1921 int err, pos = 0;
1922 struct pci_bus_region region;
1923 struct resource *res;
1924
1925 hdr_type = pci_hdr_type(dev);
1926
1927 dev->sysdata = dev->bus->sysdata;
1928 dev->dev.parent = dev->bus->bridge;
1929 dev->dev.bus = &pci_bus_type;
1930 dev->hdr_type = hdr_type & 0x7f;
1931 dev->multifunction = !!(hdr_type & 0x80);
1932 dev->error_state = pci_channel_io_normal;
1933 set_pcie_port_type(dev);
1934
1935 err = pci_set_of_node(dev);
1936 if (err)
1937 return err;
1938 pci_set_acpi_fwnode(dev);
1939
1940 pci_dev_assign_slot(dev);
1941
1942 /*
1943 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1944 * set this higher, assuming the system even supports it.
1945 */
1946 dev->dma_mask = 0xffffffff;
1947
1948 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1949 dev->bus->number, PCI_SLOT(dev->devfn),
1950 PCI_FUNC(dev->devfn));
1951
1952 class = pci_class(dev);
1953
1954 dev->revision = class & 0xff;
1955 dev->class = class >> 8; /* upper 3 bytes */
1956
1957 if (pci_early_dump)
1958 early_dump_pci_device(dev);
1959
1960 /* Need to have dev->class ready */
1961 dev->cfg_size = pci_cfg_space_size(dev);
1962
1963 /* Need to have dev->cfg_size ready */
1964 set_pcie_thunderbolt(dev);
1965
1966 set_pcie_untrusted(dev);
1967
1968 if (pci_is_pcie(dev))
1969 dev->supported_speeds = pcie_get_supported_speeds(dev);
1970
1971 /* "Unknown power state" */
1972 dev->current_state = PCI_UNKNOWN;
1973
1974 /* Early fixups, before probing the BARs */
1975 pci_fixup_device(pci_fixup_early, dev);
1976
1977 pci_set_removable(dev);
1978
1979 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n",
1980 dev->vendor, dev->device, dev->hdr_type, dev->class,
1981 pci_type_str(dev));
1982
1983 /* Device class may be changed after fixup */
1984 class = dev->class >> 8;
1985
1986 if (dev->non_compliant_bars && !dev->mmio_always_on) {
1987 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1988 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1989 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1990 cmd &= ~PCI_COMMAND_IO;
1991 cmd &= ~PCI_COMMAND_MEMORY;
1992 pci_write_config_word(dev, PCI_COMMAND, cmd);
1993 }
1994 }
1995
1996 dev->broken_intx_masking = pci_intx_mask_broken(dev);
1997
1998 switch (dev->hdr_type) { /* header type */
1999 case PCI_HEADER_TYPE_NORMAL: /* standard header */
2000 if (class == PCI_CLASS_BRIDGE_PCI)
2001 goto bad;
2002 pci_read_irq(dev);
2003 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
2004
2005 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device);
2006
2007 /*
2008 * Do the ugly legacy mode stuff here rather than broken chip
2009 * quirk code. Legacy mode ATA controllers have fixed
2010 * addresses. These are not always echoed in BAR0-3, and
2011 * BAR0-3 in a few cases contain junk!
2012 */
2013 if (class == PCI_CLASS_STORAGE_IDE) {
2014 u8 progif;
2015 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
2016 if ((progif & 1) == 0) {
2017 region.start = 0x1F0;
2018 region.end = 0x1F7;
2019 res = &dev->resource[0];
2020 res->flags = LEGACY_IO_RESOURCE;
2021 pcibios_bus_to_resource(dev->bus, res, ®ion);
2022 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n",
2023 res);
2024 region.start = 0x3F6;
2025 region.end = 0x3F6;
2026 res = &dev->resource[1];
2027 res->flags = LEGACY_IO_RESOURCE;
2028 pcibios_bus_to_resource(dev->bus, res, ®ion);
2029 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n",
2030 res);
2031 }
2032 if ((progif & 4) == 0) {
2033 region.start = 0x170;
2034 region.end = 0x177;
2035 res = &dev->resource[2];
2036 res->flags = LEGACY_IO_RESOURCE;
2037 pcibios_bus_to_resource(dev->bus, res, ®ion);
2038 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n",
2039 res);
2040 region.start = 0x376;
2041 region.end = 0x376;
2042 res = &dev->resource[3];
2043 res->flags = LEGACY_IO_RESOURCE;
2044 pcibios_bus_to_resource(dev->bus, res, ®ion);
2045 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n",
2046 res);
2047 }
2048 }
2049 break;
2050
2051 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
2052 /*
2053 * The PCI-to-PCI bridge spec requires that subtractive
2054 * decoding (i.e. transparent) bridge must have programming
2055 * interface code of 0x01.
2056 */
2057 pci_read_irq(dev);
2058 dev->transparent = ((dev->class & 0xff) == 1);
2059 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
2060 pci_read_bridge_windows(dev);
2061 set_pcie_hotplug_bridge(dev);
2062 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
2063 if (pos) {
2064 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
2065 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
2066 }
2067 break;
2068
2069 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
2070 if (class != PCI_CLASS_BRIDGE_CARDBUS)
2071 goto bad;
2072 pci_read_irq(dev);
2073 pci_read_bases(dev, 1, 0);
2074 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
2075 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
2076 break;
2077
2078 default: /* unknown header */
2079 pci_err(dev, "unknown header type %02x, ignoring device\n",
2080 dev->hdr_type);
2081 pci_release_of_node(dev);
2082 return -EIO;
2083
2084 bad:
2085 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n",
2086 dev->class, dev->hdr_type);
2087 dev->class = PCI_CLASS_NOT_DEFINED << 8;
2088 }
2089
2090 /* We found a fine healthy device, go go go... */
2091 return 0;
2092}
2093
2094static void pci_configure_mps(struct pci_dev *dev)
2095{
2096 struct pci_dev *bridge = pci_upstream_bridge(dev);
2097 int mps, mpss, p_mps, rc;
2098
2099 if (!pci_is_pcie(dev))
2100 return;
2101
2102 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */
2103 if (dev->is_virtfn)
2104 return;
2105
2106 /*
2107 * For Root Complex Integrated Endpoints, program the maximum
2108 * supported value unless limited by the PCIE_BUS_PEER2PEER case.
2109 */
2110 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
2111 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2112 mps = 128;
2113 else
2114 mps = 128 << dev->pcie_mpss;
2115 rc = pcie_set_mps(dev, mps);
2116 if (rc) {
2117 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2118 mps);
2119 }
2120 return;
2121 }
2122
2123 if (!bridge || !pci_is_pcie(bridge))
2124 return;
2125
2126 mps = pcie_get_mps(dev);
2127 p_mps = pcie_get_mps(bridge);
2128
2129 if (mps == p_mps)
2130 return;
2131
2132 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
2133 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2134 mps, pci_name(bridge), p_mps);
2135 return;
2136 }
2137
2138 /*
2139 * Fancier MPS configuration is done later by
2140 * pcie_bus_configure_settings()
2141 */
2142 if (pcie_bus_config != PCIE_BUS_DEFAULT)
2143 return;
2144
2145 mpss = 128 << dev->pcie_mpss;
2146 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) {
2147 pcie_set_mps(bridge, mpss);
2148 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n",
2149 mpss, p_mps, 128 << bridge->pcie_mpss);
2150 p_mps = pcie_get_mps(bridge);
2151 }
2152
2153 rc = pcie_set_mps(dev, p_mps);
2154 if (rc) {
2155 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
2156 p_mps);
2157 return;
2158 }
2159
2160 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n",
2161 p_mps, mps, mpss);
2162}
2163
2164int pci_configure_extended_tags(struct pci_dev *dev, void *ign)
2165{
2166 struct pci_host_bridge *host;
2167 u32 cap;
2168 u16 ctl;
2169 int ret;
2170
2171 if (!pci_is_pcie(dev))
2172 return 0;
2173
2174 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
2175 if (ret)
2176 return 0;
2177
2178 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG))
2179 return 0;
2180
2181 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
2182 if (ret)
2183 return 0;
2184
2185 host = pci_find_host_bridge(dev->bus);
2186 if (!host)
2187 return 0;
2188
2189 /*
2190 * If some device in the hierarchy doesn't handle Extended Tags
2191 * correctly, make sure they're disabled.
2192 */
2193 if (host->no_ext_tags) {
2194 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) {
2195 pci_info(dev, "disabling Extended Tags\n");
2196 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2197 PCI_EXP_DEVCTL_EXT_TAG);
2198 }
2199 return 0;
2200 }
2201
2202 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) {
2203 pci_info(dev, "enabling Extended Tags\n");
2204 pcie_capability_set_word(dev, PCI_EXP_DEVCTL,
2205 PCI_EXP_DEVCTL_EXT_TAG);
2206 }
2207 return 0;
2208}
2209
2210/**
2211 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable
2212 * @dev: PCI device to query
2213 *
2214 * Returns true if the device has enabled relaxed ordering attribute.
2215 */
2216bool pcie_relaxed_ordering_enabled(struct pci_dev *dev)
2217{
2218 u16 v;
2219
2220 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v);
2221
2222 return !!(v & PCI_EXP_DEVCTL_RELAX_EN);
2223}
2224EXPORT_SYMBOL(pcie_relaxed_ordering_enabled);
2225
2226static void pci_configure_relaxed_ordering(struct pci_dev *dev)
2227{
2228 struct pci_dev *root;
2229
2230 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */
2231 if (dev->is_virtfn)
2232 return;
2233
2234 if (!pcie_relaxed_ordering_enabled(dev))
2235 return;
2236
2237 /*
2238 * For now, we only deal with Relaxed Ordering issues with Root
2239 * Ports. Peer-to-Peer DMA is another can of worms.
2240 */
2241 root = pcie_find_root_port(dev);
2242 if (!root)
2243 return;
2244
2245 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) {
2246 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL,
2247 PCI_EXP_DEVCTL_RELAX_EN);
2248 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n");
2249 }
2250}
2251
2252static void pci_configure_eetlp_prefix(struct pci_dev *dev)
2253{
2254#ifdef CONFIG_PCI_PASID
2255 struct pci_dev *bridge;
2256 int pcie_type;
2257 u32 cap;
2258
2259 if (!pci_is_pcie(dev))
2260 return;
2261
2262 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
2263 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
2264 return;
2265
2266 pcie_type = pci_pcie_type(dev);
2267 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT ||
2268 pcie_type == PCI_EXP_TYPE_RC_END)
2269 dev->eetlp_prefix_path = 1;
2270 else {
2271 bridge = pci_upstream_bridge(dev);
2272 if (bridge && bridge->eetlp_prefix_path)
2273 dev->eetlp_prefix_path = 1;
2274 }
2275#endif
2276}
2277
2278static void pci_configure_serr(struct pci_dev *dev)
2279{
2280 u16 control;
2281
2282 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
2283
2284 /*
2285 * A bridge will not forward ERR_ messages coming from an
2286 * endpoint unless SERR# forwarding is enabled.
2287 */
2288 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control);
2289 if (!(control & PCI_BRIDGE_CTL_SERR)) {
2290 control |= PCI_BRIDGE_CTL_SERR;
2291 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control);
2292 }
2293 }
2294}
2295
2296static void pci_configure_device(struct pci_dev *dev)
2297{
2298 pci_configure_mps(dev);
2299 pci_configure_extended_tags(dev, NULL);
2300 pci_configure_relaxed_ordering(dev);
2301 pci_configure_ltr(dev);
2302 pci_configure_aspm_l1ss(dev);
2303 pci_configure_eetlp_prefix(dev);
2304 pci_configure_serr(dev);
2305
2306 pci_acpi_program_hp_params(dev);
2307}
2308
2309static void pci_release_capabilities(struct pci_dev *dev)
2310{
2311 pci_aer_exit(dev);
2312 pci_rcec_exit(dev);
2313 pci_iov_release(dev);
2314 pci_free_cap_save_buffers(dev);
2315}
2316
2317/**
2318 * pci_release_dev - Free a PCI device structure when all users of it are
2319 * finished
2320 * @dev: device that's been disconnected
2321 *
2322 * Will be called only by the device core when all users of this PCI device are
2323 * done.
2324 */
2325static void pci_release_dev(struct device *dev)
2326{
2327 struct pci_dev *pci_dev;
2328
2329 pci_dev = to_pci_dev(dev);
2330 pci_release_capabilities(pci_dev);
2331 pci_release_of_node(pci_dev);
2332 pcibios_release_device(pci_dev);
2333 pci_bus_put(pci_dev->bus);
2334 kfree(pci_dev->driver_override);
2335 bitmap_free(pci_dev->dma_alias_mask);
2336 dev_dbg(dev, "device released\n");
2337 kfree(pci_dev);
2338}
2339
2340static const struct device_type pci_dev_type = {
2341 .groups = pci_dev_attr_groups,
2342};
2343
2344struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
2345{
2346 struct pci_dev *dev;
2347
2348 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
2349 if (!dev)
2350 return NULL;
2351
2352 INIT_LIST_HEAD(&dev->bus_list);
2353 dev->dev.type = &pci_dev_type;
2354 dev->bus = pci_bus_get(bus);
2355 dev->driver_exclusive_resource = (struct resource) {
2356 .name = "PCI Exclusive",
2357 .start = 0,
2358 .end = -1,
2359 };
2360
2361 spin_lock_init(&dev->pcie_cap_lock);
2362#ifdef CONFIG_PCI_MSI
2363 raw_spin_lock_init(&dev->msi_lock);
2364#endif
2365 return dev;
2366}
2367EXPORT_SYMBOL(pci_alloc_dev);
2368
2369static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l,
2370 int timeout)
2371{
2372 int delay = 1;
2373
2374 if (!pci_bus_rrs_vendor_id(*l))
2375 return true; /* not a Configuration RRS completion */
2376
2377 if (!timeout)
2378 return false; /* RRS, but caller doesn't want to wait */
2379
2380 /*
2381 * We got the reserved Vendor ID that indicates a completion with
2382 * Configuration Request Retry Status (RRS). Retry until we get a
2383 * valid Vendor ID or we time out.
2384 */
2385 while (pci_bus_rrs_vendor_id(*l)) {
2386 if (delay > timeout) {
2387 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n",
2388 pci_domain_nr(bus), bus->number,
2389 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2390
2391 return false;
2392 }
2393 if (delay >= 1000)
2394 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n",
2395 pci_domain_nr(bus), bus->number,
2396 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2397
2398 msleep(delay);
2399 delay *= 2;
2400
2401 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2402 return false;
2403 }
2404
2405 if (delay >= 1000)
2406 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n",
2407 pci_domain_nr(bus), bus->number,
2408 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1);
2409
2410 return true;
2411}
2412
2413bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2414 int timeout)
2415{
2416 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
2417 return false;
2418
2419 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */
2420 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 ||
2421 *l == 0x0000ffff || *l == 0xffff0000)
2422 return false;
2423
2424 if (pci_bus_rrs_vendor_id(*l))
2425 return pci_bus_wait_rrs(bus, devfn, l, timeout);
2426
2427 return true;
2428}
2429
2430bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
2431 int timeout)
2432{
2433#ifdef CONFIG_PCI_QUIRKS
2434 struct pci_dev *bridge = bus->self;
2435
2436 /*
2437 * Certain IDT switches have an issue where they improperly trigger
2438 * ACS Source Validation errors on completions for config reads.
2439 */
2440 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT &&
2441 bridge->device == 0x80b5)
2442 return pci_idt_bus_quirk(bus, devfn, l, timeout);
2443#endif
2444
2445 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout);
2446}
2447EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
2448
2449/*
2450 * Read the config data for a PCI device, sanity-check it,
2451 * and fill in the dev structure.
2452 */
2453static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
2454{
2455 struct pci_dev *dev;
2456 u32 l;
2457
2458 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
2459 return NULL;
2460
2461 dev = pci_alloc_dev(bus);
2462 if (!dev)
2463 return NULL;
2464
2465 dev->devfn = devfn;
2466 dev->vendor = l & 0xffff;
2467 dev->device = (l >> 16) & 0xffff;
2468
2469 if (pci_setup_device(dev)) {
2470 pci_bus_put(dev->bus);
2471 kfree(dev);
2472 return NULL;
2473 }
2474
2475 return dev;
2476}
2477
2478void pcie_report_downtraining(struct pci_dev *dev)
2479{
2480 if (!pci_is_pcie(dev))
2481 return;
2482
2483 /* Look from the device up to avoid downstream ports with no devices */
2484 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) &&
2485 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) &&
2486 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM))
2487 return;
2488
2489 /* Multi-function PCIe devices share the same link/status */
2490 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn)
2491 return;
2492
2493 /* Print link status only if the device is constrained by the fabric */
2494 __pcie_print_link_status(dev, false);
2495}
2496
2497static void pci_init_capabilities(struct pci_dev *dev)
2498{
2499 pci_ea_init(dev); /* Enhanced Allocation */
2500 pci_msi_init(dev); /* Disable MSI */
2501 pci_msix_init(dev); /* Disable MSI-X */
2502
2503 /* Buffers for saving PCIe and PCI-X capabilities */
2504 pci_allocate_cap_save_buffers(dev);
2505
2506 pci_pm_init(dev); /* Power Management */
2507 pci_vpd_init(dev); /* Vital Product Data */
2508 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */
2509 pci_iov_init(dev); /* Single Root I/O Virtualization */
2510 pci_ats_init(dev); /* Address Translation Services */
2511 pci_pri_init(dev); /* Page Request Interface */
2512 pci_pasid_init(dev); /* Process Address Space ID */
2513 pci_acs_init(dev); /* Access Control Services */
2514 pci_ptm_init(dev); /* Precision Time Measurement */
2515 pci_aer_init(dev); /* Advanced Error Reporting */
2516 pci_dpc_init(dev); /* Downstream Port Containment */
2517 pci_rcec_init(dev); /* Root Complex Event Collector */
2518 pci_doe_init(dev); /* Data Object Exchange */
2519 pci_tph_init(dev); /* TLP Processing Hints */
2520
2521 pcie_report_downtraining(dev);
2522 pci_init_reset_methods(dev);
2523}
2524
2525/*
2526 * This is the equivalent of pci_host_bridge_msi_domain() that acts on
2527 * devices. Firmware interfaces that can select the MSI domain on a
2528 * per-device basis should be called from here.
2529 */
2530static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
2531{
2532 struct irq_domain *d;
2533
2534 /*
2535 * If a domain has been set through the pcibios_device_add()
2536 * callback, then this is the one (platform code knows best).
2537 */
2538 d = dev_get_msi_domain(&dev->dev);
2539 if (d)
2540 return d;
2541
2542 /*
2543 * Let's see if we have a firmware interface able to provide
2544 * the domain.
2545 */
2546 d = pci_msi_get_device_domain(dev);
2547 if (d)
2548 return d;
2549
2550 return NULL;
2551}
2552
2553static void pci_set_msi_domain(struct pci_dev *dev)
2554{
2555 struct irq_domain *d;
2556
2557 /*
2558 * If the platform or firmware interfaces cannot supply a
2559 * device-specific MSI domain, then inherit the default domain
2560 * from the host bridge itself.
2561 */
2562 d = pci_dev_msi_domain(dev);
2563 if (!d)
2564 d = dev_get_msi_domain(&dev->bus->dev);
2565
2566 dev_set_msi_domain(&dev->dev, d);
2567}
2568
2569void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
2570{
2571 int ret;
2572
2573 pci_configure_device(dev);
2574
2575 device_initialize(&dev->dev);
2576 dev->dev.release = pci_release_dev;
2577
2578 set_dev_node(&dev->dev, pcibus_to_node(bus));
2579 dev->dev.dma_mask = &dev->dma_mask;
2580 dev->dev.dma_parms = &dev->dma_parms;
2581 dev->dev.coherent_dma_mask = 0xffffffffull;
2582
2583 dma_set_max_seg_size(&dev->dev, 65536);
2584 dma_set_seg_boundary(&dev->dev, 0xffffffff);
2585
2586 pcie_failed_link_retrain(dev);
2587
2588 /* Fix up broken headers */
2589 pci_fixup_device(pci_fixup_header, dev);
2590
2591 pci_reassigndev_resource_alignment(dev);
2592
2593 dev->state_saved = false;
2594
2595 pci_init_capabilities(dev);
2596
2597 /*
2598 * Add the device to our list of discovered devices
2599 * and the bus list for fixup functions, etc.
2600 */
2601 down_write(&pci_bus_sem);
2602 list_add_tail(&dev->bus_list, &bus->devices);
2603 up_write(&pci_bus_sem);
2604
2605 ret = pcibios_device_add(dev);
2606 WARN_ON(ret < 0);
2607
2608 /* Set up MSI IRQ domain */
2609 pci_set_msi_domain(dev);
2610
2611 /* Notifier could use PCI capabilities */
2612 dev->match_driver = false;
2613 ret = device_add(&dev->dev);
2614 WARN_ON(ret < 0);
2615
2616 pci_npem_create(dev);
2617}
2618
2619struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
2620{
2621 struct pci_dev *dev;
2622
2623 dev = pci_get_slot(bus, devfn);
2624 if (dev) {
2625 pci_dev_put(dev);
2626 return dev;
2627 }
2628
2629 dev = pci_scan_device(bus, devfn);
2630 if (!dev)
2631 return NULL;
2632
2633 pci_device_add(dev, bus);
2634
2635 return dev;
2636}
2637EXPORT_SYMBOL(pci_scan_single_device);
2638
2639static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2640{
2641 int pos;
2642 u16 cap = 0;
2643 unsigned int next_fn;
2644
2645 if (!dev)
2646 return -ENODEV;
2647
2648 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
2649 if (!pos)
2650 return -ENODEV;
2651
2652 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
2653 next_fn = PCI_ARI_CAP_NFN(cap);
2654 if (next_fn <= fn)
2655 return -ENODEV; /* protect against malformed list */
2656
2657 return next_fn;
2658}
2659
2660static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
2661{
2662 if (pci_ari_enabled(bus))
2663 return next_ari_fn(bus, dev, fn);
2664
2665 if (fn >= 7)
2666 return -ENODEV;
2667 /* only multifunction devices may have more functions */
2668 if (dev && !dev->multifunction)
2669 return -ENODEV;
2670
2671 return fn + 1;
2672}
2673
2674static int only_one_child(struct pci_bus *bus)
2675{
2676 struct pci_dev *bridge = bus->self;
2677
2678 /*
2679 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so
2680 * we scan for all possible devices, not just Device 0.
2681 */
2682 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2683 return 0;
2684
2685 /*
2686 * A PCIe Downstream Port normally leads to a Link with only Device
2687 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan
2688 * only for Device 0 in that situation.
2689 */
2690 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge))
2691 return 1;
2692
2693 return 0;
2694}
2695
2696/**
2697 * pci_scan_slot - Scan a PCI slot on a bus for devices
2698 * @bus: PCI bus to scan
2699 * @devfn: slot number to scan (must have zero function)
2700 *
2701 * Scan a PCI slot on the specified PCI bus for devices, adding
2702 * discovered devices to the @bus->devices list. New devices
2703 * will not have is_added set.
2704 *
2705 * Returns the number of new devices found.
2706 */
2707int pci_scan_slot(struct pci_bus *bus, int devfn)
2708{
2709 struct pci_dev *dev;
2710 int fn = 0, nr = 0;
2711
2712 if (only_one_child(bus) && (devfn > 0))
2713 return 0; /* Already scanned the entire slot */
2714
2715 do {
2716 dev = pci_scan_single_device(bus, devfn + fn);
2717 if (dev) {
2718 if (!pci_dev_is_added(dev))
2719 nr++;
2720 if (fn > 0)
2721 dev->multifunction = 1;
2722 } else if (fn == 0) {
2723 /*
2724 * Function 0 is required unless we are running on
2725 * a hypervisor that passes through individual PCI
2726 * functions.
2727 */
2728 if (!hypervisor_isolated_pci_functions())
2729 break;
2730 }
2731 fn = next_fn(bus, dev, fn);
2732 } while (fn >= 0);
2733
2734 /* Only one slot has PCIe device */
2735 if (bus->self && nr)
2736 pcie_aspm_init_link_state(bus->self);
2737
2738 return nr;
2739}
2740EXPORT_SYMBOL(pci_scan_slot);
2741
2742static int pcie_find_smpss(struct pci_dev *dev, void *data)
2743{
2744 u8 *smpss = data;
2745
2746 if (!pci_is_pcie(dev))
2747 return 0;
2748
2749 /*
2750 * We don't have a way to change MPS settings on devices that have
2751 * drivers attached. A hot-added device might support only the minimum
2752 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2753 * where devices may be hot-added, we limit the fabric MPS to 128 so
2754 * hot-added devices will work correctly.
2755 *
2756 * However, if we hot-add a device to a slot directly below a Root
2757 * Port, it's impossible for there to be other existing devices below
2758 * the port. We don't limit the MPS in this case because we can
2759 * reconfigure MPS on both the Root Port and the hot-added device,
2760 * and there are no other devices involved.
2761 *
2762 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2763 */
2764 if (dev->is_hotplug_bridge &&
2765 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2766 *smpss = 0;
2767
2768 if (*smpss > dev->pcie_mpss)
2769 *smpss = dev->pcie_mpss;
2770
2771 return 0;
2772}
2773
2774static void pcie_write_mps(struct pci_dev *dev, int mps)
2775{
2776 int rc;
2777
2778 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2779 mps = 128 << dev->pcie_mpss;
2780
2781 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2782 dev->bus->self)
2783
2784 /*
2785 * For "Performance", the assumption is made that
2786 * downstream communication will never be larger than
2787 * the MRRS. So, the MPS only needs to be configured
2788 * for the upstream communication. This being the case,
2789 * walk from the top down and set the MPS of the child
2790 * to that of the parent bus.
2791 *
2792 * Configure the device MPS with the smaller of the
2793 * device MPSS or the bridge MPS (which is assumed to be
2794 * properly configured at this point to the largest
2795 * allowable MPS based on its parent bus).
2796 */
2797 mps = min(mps, pcie_get_mps(dev->bus->self));
2798 }
2799
2800 rc = pcie_set_mps(dev, mps);
2801 if (rc)
2802 pci_err(dev, "Failed attempting to set the MPS\n");
2803}
2804
2805static void pcie_write_mrrs(struct pci_dev *dev)
2806{
2807 int rc, mrrs;
2808
2809 /*
2810 * In the "safe" case, do not configure the MRRS. There appear to be
2811 * issues with setting MRRS to 0 on a number of devices.
2812 */
2813 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2814 return;
2815
2816 /*
2817 * For max performance, the MRRS must be set to the largest supported
2818 * value. However, it cannot be configured larger than the MPS the
2819 * device or the bus can support. This should already be properly
2820 * configured by a prior call to pcie_write_mps().
2821 */
2822 mrrs = pcie_get_mps(dev);
2823
2824 /*
2825 * MRRS is a R/W register. Invalid values can be written, but a
2826 * subsequent read will verify if the value is acceptable or not.
2827 * If the MRRS value provided is not acceptable (e.g., too large),
2828 * shrink the value until it is acceptable to the HW.
2829 */
2830 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2831 rc = pcie_set_readrq(dev, mrrs);
2832 if (!rc)
2833 break;
2834
2835 pci_warn(dev, "Failed attempting to set the MRRS\n");
2836 mrrs /= 2;
2837 }
2838
2839 if (mrrs < 128)
2840 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2841}
2842
2843static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2844{
2845 int mps, orig_mps;
2846
2847 if (!pci_is_pcie(dev))
2848 return 0;
2849
2850 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2851 pcie_bus_config == PCIE_BUS_DEFAULT)
2852 return 0;
2853
2854 mps = 128 << *(u8 *)data;
2855 orig_mps = pcie_get_mps(dev);
2856
2857 pcie_write_mps(dev, mps);
2858 pcie_write_mrrs(dev);
2859
2860 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2861 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2862 orig_mps, pcie_get_readrq(dev));
2863
2864 return 0;
2865}
2866
2867/*
2868 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down,
2869 * parents then children fashion. If this changes, then this code will not
2870 * work as designed.
2871 */
2872void pcie_bus_configure_settings(struct pci_bus *bus)
2873{
2874 u8 smpss = 0;
2875
2876 if (!bus->self)
2877 return;
2878
2879 if (!pci_is_pcie(bus->self))
2880 return;
2881
2882 /*
2883 * FIXME - Peer to peer DMA is possible, though the endpoint would need
2884 * to be aware of the MPS of the destination. To work around this,
2885 * simply force the MPS of the entire system to the smallest possible.
2886 */
2887 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2888 smpss = 0;
2889
2890 if (pcie_bus_config == PCIE_BUS_SAFE) {
2891 smpss = bus->self->pcie_mpss;
2892
2893 pcie_find_smpss(bus->self, &smpss);
2894 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2895 }
2896
2897 pcie_bus_configure_set(bus->self, &smpss);
2898 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2899}
2900EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2901
2902/*
2903 * Called after each bus is probed, but before its children are examined. This
2904 * is marked as __weak because multiple architectures define it.
2905 */
2906void __weak pcibios_fixup_bus(struct pci_bus *bus)
2907{
2908 /* nothing to do, expected to be removed in the future */
2909}
2910
2911/**
2912 * pci_scan_child_bus_extend() - Scan devices below a bus
2913 * @bus: Bus to scan for devices
2914 * @available_buses: Total number of buses available (%0 does not try to
2915 * extend beyond the minimal)
2916 *
2917 * Scans devices below @bus including subordinate buses. Returns new
2918 * subordinate number including all the found devices. Passing
2919 * @available_buses causes the remaining bus space to be distributed
2920 * equally between hotplug-capable bridges to allow future extension of the
2921 * hierarchy.
2922 */
2923static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus,
2924 unsigned int available_buses)
2925{
2926 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
2927 unsigned int start = bus->busn_res.start;
2928 unsigned int devfn, cmax, max = start;
2929 struct pci_dev *dev;
2930
2931 dev_dbg(&bus->dev, "scanning bus\n");
2932
2933 /* Go find them, Rover! */
2934 for (devfn = 0; devfn < 256; devfn += 8)
2935 pci_scan_slot(bus, devfn);
2936
2937 /* Reserve buses for SR-IOV capability */
2938 used_buses = pci_iov_bus_range(bus);
2939 max += used_buses;
2940
2941 /*
2942 * After performing arch-dependent fixup of the bus, look behind
2943 * all PCI-to-PCI bridges on this bus.
2944 */
2945 if (!bus->is_added) {
2946 dev_dbg(&bus->dev, "fixups for bus\n");
2947 pcibios_fixup_bus(bus);
2948 bus->is_added = 1;
2949 }
2950
2951 /*
2952 * Calculate how many hotplug bridges and normal bridges there
2953 * are on this bus. We will distribute the additional available
2954 * buses between hotplug bridges.
2955 */
2956 for_each_pci_bridge(dev, bus) {
2957 if (dev->is_hotplug_bridge)
2958 hotplug_bridges++;
2959 else
2960 normal_bridges++;
2961 }
2962
2963 /*
2964 * Scan bridges that are already configured. We don't touch them
2965 * unless they are misconfigured (which will be done in the second
2966 * scan below).
2967 */
2968 for_each_pci_bridge(dev, bus) {
2969 cmax = max;
2970 max = pci_scan_bridge_extend(bus, dev, max, 0, 0);
2971
2972 /*
2973 * Reserve one bus for each bridge now to avoid extending
2974 * hotplug bridges too much during the second scan below.
2975 */
2976 used_buses++;
2977 if (max - cmax > 1)
2978 used_buses += max - cmax - 1;
2979 }
2980
2981 /* Scan bridges that need to be reconfigured */
2982 for_each_pci_bridge(dev, bus) {
2983 unsigned int buses = 0;
2984
2985 if (!hotplug_bridges && normal_bridges == 1) {
2986 /*
2987 * There is only one bridge on the bus (upstream
2988 * port) so it gets all available buses which it
2989 * can then distribute to the possible hotplug
2990 * bridges below.
2991 */
2992 buses = available_buses;
2993 } else if (dev->is_hotplug_bridge) {
2994 /*
2995 * Distribute the extra buses between hotplug
2996 * bridges if any.
2997 */
2998 buses = available_buses / hotplug_bridges;
2999 buses = min(buses, available_buses - used_buses + 1);
3000 }
3001
3002 cmax = max;
3003 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1);
3004 /* One bus is already accounted so don't add it again */
3005 if (max - cmax > 1)
3006 used_buses += max - cmax - 1;
3007 }
3008
3009 /*
3010 * Make sure a hotplug bridge has at least the minimum requested
3011 * number of buses but allow it to grow up to the maximum available
3012 * bus number if there is room.
3013 */
3014 if (bus->self && bus->self->is_hotplug_bridge) {
3015 used_buses = max_t(unsigned int, available_buses,
3016 pci_hotplug_bus_size - 1);
3017 if (max - start < used_buses) {
3018 max = start + used_buses;
3019
3020 /* Do not allocate more buses than we have room left */
3021 if (max > bus->busn_res.end)
3022 max = bus->busn_res.end;
3023
3024 dev_dbg(&bus->dev, "%pR extended by %#02x\n",
3025 &bus->busn_res, max - start);
3026 }
3027 }
3028
3029 /*
3030 * We've scanned the bus and so we know all about what's on
3031 * the other side of any bridges that may be on this bus plus
3032 * any devices.
3033 *
3034 * Return how far we've got finding sub-buses.
3035 */
3036 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
3037 return max;
3038}
3039
3040/**
3041 * pci_scan_child_bus() - Scan devices below a bus
3042 * @bus: Bus to scan for devices
3043 *
3044 * Scans devices below @bus including subordinate buses. Returns new
3045 * subordinate number including all the found devices.
3046 */
3047unsigned int pci_scan_child_bus(struct pci_bus *bus)
3048{
3049 return pci_scan_child_bus_extend(bus, 0);
3050}
3051EXPORT_SYMBOL_GPL(pci_scan_child_bus);
3052
3053/**
3054 * pcibios_root_bridge_prepare - Platform-specific host bridge setup
3055 * @bridge: Host bridge to set up
3056 *
3057 * Default empty implementation. Replace with an architecture-specific setup
3058 * routine, if necessary.
3059 */
3060int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
3061{
3062 return 0;
3063}
3064
3065void __weak pcibios_add_bus(struct pci_bus *bus)
3066{
3067}
3068
3069void __weak pcibios_remove_bus(struct pci_bus *bus)
3070{
3071}
3072
3073struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
3074 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3075{
3076 int error;
3077 struct pci_host_bridge *bridge;
3078
3079 bridge = pci_alloc_host_bridge(0);
3080 if (!bridge)
3081 return NULL;
3082
3083 bridge->dev.parent = parent;
3084
3085 list_splice_init(resources, &bridge->windows);
3086 bridge->sysdata = sysdata;
3087 bridge->busnr = bus;
3088 bridge->ops = ops;
3089
3090 error = pci_register_host_bridge(bridge);
3091 if (error < 0)
3092 goto err_out;
3093
3094 return bridge->bus;
3095
3096err_out:
3097 put_device(&bridge->dev);
3098 return NULL;
3099}
3100EXPORT_SYMBOL_GPL(pci_create_root_bus);
3101
3102int pci_host_probe(struct pci_host_bridge *bridge)
3103{
3104 struct pci_bus *bus, *child;
3105 int ret;
3106
3107 pci_lock_rescan_remove();
3108 ret = pci_scan_root_bus_bridge(bridge);
3109 pci_unlock_rescan_remove();
3110 if (ret < 0) {
3111 dev_err(bridge->dev.parent, "Scanning root bridge failed");
3112 return ret;
3113 }
3114
3115 bus = bridge->bus;
3116
3117 /* If we must preserve the resource configuration, claim now */
3118 if (bridge->preserve_config)
3119 pci_bus_claim_resources(bus);
3120
3121 /*
3122 * Assign whatever was left unassigned. If we didn't claim above,
3123 * this will reassign everything.
3124 */
3125 pci_assign_unassigned_root_bus_resources(bus);
3126
3127 list_for_each_entry(child, &bus->children, node)
3128 pcie_bus_configure_settings(child);
3129
3130 pci_lock_rescan_remove();
3131 pci_bus_add_devices(bus);
3132 pci_unlock_rescan_remove();
3133
3134 /*
3135 * Ensure pm_runtime_enable() is called for the controller drivers
3136 * before calling pci_host_probe(). The PM framework expects that
3137 * if the parent device supports runtime PM, it will be enabled
3138 * before child runtime PM is enabled.
3139 */
3140 pm_runtime_set_active(&bridge->dev);
3141 pm_runtime_no_callbacks(&bridge->dev);
3142 devm_pm_runtime_enable(&bridge->dev);
3143
3144 return 0;
3145}
3146EXPORT_SYMBOL_GPL(pci_host_probe);
3147
3148int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
3149{
3150 struct resource *res = &b->busn_res;
3151 struct resource *parent_res, *conflict;
3152
3153 res->start = bus;
3154 res->end = bus_max;
3155 res->flags = IORESOURCE_BUS;
3156
3157 if (!pci_is_root_bus(b))
3158 parent_res = &b->parent->busn_res;
3159 else {
3160 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
3161 res->flags |= IORESOURCE_PCI_FIXED;
3162 }
3163
3164 conflict = request_resource_conflict(parent_res, res);
3165
3166 if (conflict)
3167 dev_info(&b->dev,
3168 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
3169 res, pci_is_root_bus(b) ? "domain " : "",
3170 parent_res, conflict->name, conflict);
3171
3172 return conflict == NULL;
3173}
3174
3175int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
3176{
3177 struct resource *res = &b->busn_res;
3178 struct resource old_res = *res;
3179 resource_size_t size;
3180 int ret;
3181
3182 if (res->start > bus_max)
3183 return -EINVAL;
3184
3185 size = bus_max - res->start + 1;
3186 ret = adjust_resource(res, res->start, size);
3187 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n",
3188 &old_res, ret ? "can not be" : "is", bus_max);
3189
3190 if (!ret && !res->parent)
3191 pci_bus_insert_busn_res(b, res->start, res->end);
3192
3193 return ret;
3194}
3195
3196void pci_bus_release_busn_res(struct pci_bus *b)
3197{
3198 struct resource *res = &b->busn_res;
3199 int ret;
3200
3201 if (!res->flags || !res->parent)
3202 return;
3203
3204 ret = release_resource(res);
3205 dev_info(&b->dev, "busn_res: %pR %s released\n",
3206 res, ret ? "can not be" : "is");
3207}
3208
3209int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge)
3210{
3211 struct resource_entry *window;
3212 bool found = false;
3213 struct pci_bus *b;
3214 int max, bus, ret;
3215
3216 if (!bridge)
3217 return -EINVAL;
3218
3219 resource_list_for_each_entry(window, &bridge->windows)
3220 if (window->res->flags & IORESOURCE_BUS) {
3221 bridge->busnr = window->res->start;
3222 found = true;
3223 break;
3224 }
3225
3226 ret = pci_register_host_bridge(bridge);
3227 if (ret < 0)
3228 return ret;
3229
3230 b = bridge->bus;
3231 bus = bridge->busnr;
3232
3233 if (!found) {
3234 dev_info(&b->dev,
3235 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3236 bus);
3237 pci_bus_insert_busn_res(b, bus, 255);
3238 }
3239
3240 max = pci_scan_child_bus(b);
3241
3242 if (!found)
3243 pci_bus_update_busn_res_end(b, max);
3244
3245 return 0;
3246}
3247EXPORT_SYMBOL(pci_scan_root_bus_bridge);
3248
3249struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
3250 struct pci_ops *ops, void *sysdata, struct list_head *resources)
3251{
3252 struct resource_entry *window;
3253 bool found = false;
3254 struct pci_bus *b;
3255 int max;
3256
3257 resource_list_for_each_entry(window, resources)
3258 if (window->res->flags & IORESOURCE_BUS) {
3259 found = true;
3260 break;
3261 }
3262
3263 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
3264 if (!b)
3265 return NULL;
3266
3267 if (!found) {
3268 dev_info(&b->dev,
3269 "No busn resource found for root bus, will use [bus %02x-ff]\n",
3270 bus);
3271 pci_bus_insert_busn_res(b, bus, 255);
3272 }
3273
3274 max = pci_scan_child_bus(b);
3275
3276 if (!found)
3277 pci_bus_update_busn_res_end(b, max);
3278
3279 return b;
3280}
3281EXPORT_SYMBOL(pci_scan_root_bus);
3282
3283struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
3284 void *sysdata)
3285{
3286 LIST_HEAD(resources);
3287 struct pci_bus *b;
3288
3289 pci_add_resource(&resources, &ioport_resource);
3290 pci_add_resource(&resources, &iomem_resource);
3291 pci_add_resource(&resources, &busn_resource);
3292 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
3293 if (b) {
3294 pci_scan_child_bus(b);
3295 } else {
3296 pci_free_resource_list(&resources);
3297 }
3298 return b;
3299}
3300EXPORT_SYMBOL(pci_scan_bus);
3301
3302/**
3303 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices
3304 * @bridge: PCI bridge for the bus to scan
3305 *
3306 * Scan a PCI bus and child buses for new devices, add them,
3307 * and enable them, resizing bridge mmio/io resource if necessary
3308 * and possible. The caller must ensure the child devices are already
3309 * removed for resizing to occur.
3310 *
3311 * Returns the max number of subordinate bus discovered.
3312 */
3313unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
3314{
3315 unsigned int max;
3316 struct pci_bus *bus = bridge->subordinate;
3317
3318 max = pci_scan_child_bus(bus);
3319
3320 pci_assign_unassigned_bridge_resources(bridge);
3321
3322 pci_bus_add_devices(bus);
3323
3324 return max;
3325}
3326
3327/**
3328 * pci_rescan_bus - Scan a PCI bus for devices
3329 * @bus: PCI bus to scan
3330 *
3331 * Scan a PCI bus and child buses for new devices, add them,
3332 * and enable them.
3333 *
3334 * Returns the max number of subordinate bus discovered.
3335 */
3336unsigned int pci_rescan_bus(struct pci_bus *bus)
3337{
3338 unsigned int max;
3339
3340 max = pci_scan_child_bus(bus);
3341 pci_assign_unassigned_bus_resources(bus);
3342 pci_bus_add_devices(bus);
3343
3344 return max;
3345}
3346EXPORT_SYMBOL_GPL(pci_rescan_bus);
3347
3348/*
3349 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
3350 * routines should always be executed under this mutex.
3351 */
3352static DEFINE_MUTEX(pci_rescan_remove_lock);
3353
3354void pci_lock_rescan_remove(void)
3355{
3356 mutex_lock(&pci_rescan_remove_lock);
3357}
3358EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
3359
3360void pci_unlock_rescan_remove(void)
3361{
3362 mutex_unlock(&pci_rescan_remove_lock);
3363}
3364EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
3365
3366static int __init pci_sort_bf_cmp(const struct device *d_a,
3367 const struct device *d_b)
3368{
3369 const struct pci_dev *a = to_pci_dev(d_a);
3370 const struct pci_dev *b = to_pci_dev(d_b);
3371
3372 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
3373 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
3374
3375 if (a->bus->number < b->bus->number) return -1;
3376 else if (a->bus->number > b->bus->number) return 1;
3377
3378 if (a->devfn < b->devfn) return -1;
3379 else if (a->devfn > b->devfn) return 1;
3380
3381 return 0;
3382}
3383
3384void __init pci_sort_breadthfirst(void)
3385{
3386 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
3387}
3388
3389int pci_hp_add_bridge(struct pci_dev *dev)
3390{
3391 struct pci_bus *parent = dev->bus;
3392 int busnr, start = parent->busn_res.start;
3393 unsigned int available_buses = 0;
3394 int end = parent->busn_res.end;
3395
3396 for (busnr = start; busnr <= end; busnr++) {
3397 if (!pci_find_bus(pci_domain_nr(parent), busnr))
3398 break;
3399 }
3400 if (busnr-- > end) {
3401 pci_err(dev, "No bus number available for hot-added bridge\n");
3402 return -1;
3403 }
3404
3405 /* Scan bridges that are already configured */
3406 busnr = pci_scan_bridge(parent, dev, busnr, 0);
3407
3408 /*
3409 * Distribute the available bus numbers between hotplug-capable
3410 * bridges to make extending the chain later possible.
3411 */
3412 available_buses = end - busnr;
3413
3414 /* Scan bridges that need to be reconfigured */
3415 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1);
3416
3417 if (!dev->subordinate)
3418 return -1;
3419
3420 return 0;
3421}
3422EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
1/*
2 * probe.c - PCI detection and setup code
3 */
4
5#include <linux/kernel.h>
6#include <linux/delay.h>
7#include <linux/init.h>
8#include <linux/pci.h>
9#include <linux/of_device.h>
10#include <linux/of_pci.h>
11#include <linux/pci_hotplug.h>
12#include <linux/slab.h>
13#include <linux/module.h>
14#include <linux/cpumask.h>
15#include <linux/pci-aspm.h>
16#include <linux/aer.h>
17#include <linux/acpi.h>
18#include <linux/irqdomain.h>
19#include <linux/pm_runtime.h>
20#include "pci.h"
21
22#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
23#define CARDBUS_RESERVE_BUSNR 3
24
25static struct resource busn_resource = {
26 .name = "PCI busn",
27 .start = 0,
28 .end = 255,
29 .flags = IORESOURCE_BUS,
30};
31
32/* Ugh. Need to stop exporting this to modules. */
33LIST_HEAD(pci_root_buses);
34EXPORT_SYMBOL(pci_root_buses);
35
36static LIST_HEAD(pci_domain_busn_res_list);
37
38struct pci_domain_busn_res {
39 struct list_head list;
40 struct resource res;
41 int domain_nr;
42};
43
44static struct resource *get_pci_domain_busn_res(int domain_nr)
45{
46 struct pci_domain_busn_res *r;
47
48 list_for_each_entry(r, &pci_domain_busn_res_list, list)
49 if (r->domain_nr == domain_nr)
50 return &r->res;
51
52 r = kzalloc(sizeof(*r), GFP_KERNEL);
53 if (!r)
54 return NULL;
55
56 r->domain_nr = domain_nr;
57 r->res.start = 0;
58 r->res.end = 0xff;
59 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
60
61 list_add_tail(&r->list, &pci_domain_busn_res_list);
62
63 return &r->res;
64}
65
66static int find_anything(struct device *dev, void *data)
67{
68 return 1;
69}
70
71/*
72 * Some device drivers need know if pci is initiated.
73 * Basically, we think pci is not initiated when there
74 * is no device to be found on the pci_bus_type.
75 */
76int no_pci_devices(void)
77{
78 struct device *dev;
79 int no_devices;
80
81 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
82 no_devices = (dev == NULL);
83 put_device(dev);
84 return no_devices;
85}
86EXPORT_SYMBOL(no_pci_devices);
87
88/*
89 * PCI Bus Class
90 */
91static void release_pcibus_dev(struct device *dev)
92{
93 struct pci_bus *pci_bus = to_pci_bus(dev);
94
95 put_device(pci_bus->bridge);
96 pci_bus_remove_resources(pci_bus);
97 pci_release_bus_of_node(pci_bus);
98 kfree(pci_bus);
99}
100
101static struct class pcibus_class = {
102 .name = "pci_bus",
103 .dev_release = &release_pcibus_dev,
104 .dev_groups = pcibus_groups,
105};
106
107static int __init pcibus_class_init(void)
108{
109 return class_register(&pcibus_class);
110}
111postcore_initcall(pcibus_class_init);
112
113static u64 pci_size(u64 base, u64 maxbase, u64 mask)
114{
115 u64 size = mask & maxbase; /* Find the significant bits */
116 if (!size)
117 return 0;
118
119 /* Get the lowest of them to find the decode size, and
120 from that the extent. */
121 size = (size & ~(size-1)) - 1;
122
123 /* base == maxbase can be valid only if the BAR has
124 already been programmed with all 1s. */
125 if (base == maxbase && ((base | size) & mask) != mask)
126 return 0;
127
128 return size;
129}
130
131static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
132{
133 u32 mem_type;
134 unsigned long flags;
135
136 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
137 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
138 flags |= IORESOURCE_IO;
139 return flags;
140 }
141
142 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
143 flags |= IORESOURCE_MEM;
144 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
145 flags |= IORESOURCE_PREFETCH;
146
147 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
148 switch (mem_type) {
149 case PCI_BASE_ADDRESS_MEM_TYPE_32:
150 break;
151 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
152 /* 1M mem BAR treated as 32-bit BAR */
153 break;
154 case PCI_BASE_ADDRESS_MEM_TYPE_64:
155 flags |= IORESOURCE_MEM_64;
156 break;
157 default:
158 /* mem unknown type treated as 32-bit BAR */
159 break;
160 }
161 return flags;
162}
163
164#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
165
166/**
167 * pci_read_base - read a PCI BAR
168 * @dev: the PCI device
169 * @type: type of the BAR
170 * @res: resource buffer to be filled in
171 * @pos: BAR position in the config space
172 *
173 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
174 */
175int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
176 struct resource *res, unsigned int pos)
177{
178 u32 l, sz, mask;
179 u64 l64, sz64, mask64;
180 u16 orig_cmd;
181 struct pci_bus_region region, inverted_region;
182
183 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
184
185 /* No printks while decoding is disabled! */
186 if (!dev->mmio_always_on) {
187 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
188 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
189 pci_write_config_word(dev, PCI_COMMAND,
190 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
191 }
192 }
193
194 res->name = pci_name(dev);
195
196 pci_read_config_dword(dev, pos, &l);
197 pci_write_config_dword(dev, pos, l | mask);
198 pci_read_config_dword(dev, pos, &sz);
199 pci_write_config_dword(dev, pos, l);
200
201 /*
202 * All bits set in sz means the device isn't working properly.
203 * If the BAR isn't implemented, all bits must be 0. If it's a
204 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
205 * 1 must be clear.
206 */
207 if (sz == 0xffffffff)
208 sz = 0;
209
210 /*
211 * I don't know how l can have all bits set. Copied from old code.
212 * Maybe it fixes a bug on some ancient platform.
213 */
214 if (l == 0xffffffff)
215 l = 0;
216
217 if (type == pci_bar_unknown) {
218 res->flags = decode_bar(dev, l);
219 res->flags |= IORESOURCE_SIZEALIGN;
220 if (res->flags & IORESOURCE_IO) {
221 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
222 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
223 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
224 } else {
225 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
226 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
227 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
228 }
229 } else {
230 if (l & PCI_ROM_ADDRESS_ENABLE)
231 res->flags |= IORESOURCE_ROM_ENABLE;
232 l64 = l & PCI_ROM_ADDRESS_MASK;
233 sz64 = sz & PCI_ROM_ADDRESS_MASK;
234 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
235 }
236
237 if (res->flags & IORESOURCE_MEM_64) {
238 pci_read_config_dword(dev, pos + 4, &l);
239 pci_write_config_dword(dev, pos + 4, ~0);
240 pci_read_config_dword(dev, pos + 4, &sz);
241 pci_write_config_dword(dev, pos + 4, l);
242
243 l64 |= ((u64)l << 32);
244 sz64 |= ((u64)sz << 32);
245 mask64 |= ((u64)~0 << 32);
246 }
247
248 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
249 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
250
251 if (!sz64)
252 goto fail;
253
254 sz64 = pci_size(l64, sz64, mask64);
255 if (!sz64) {
256 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
257 pos);
258 goto fail;
259 }
260
261 if (res->flags & IORESOURCE_MEM_64) {
262 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
263 && sz64 > 0x100000000ULL) {
264 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
265 res->start = 0;
266 res->end = 0;
267 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
268 pos, (unsigned long long)sz64);
269 goto out;
270 }
271
272 if ((sizeof(pci_bus_addr_t) < 8) && l) {
273 /* Above 32-bit boundary; try to reallocate */
274 res->flags |= IORESOURCE_UNSET;
275 res->start = 0;
276 res->end = sz64;
277 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
278 pos, (unsigned long long)l64);
279 goto out;
280 }
281 }
282
283 region.start = l64;
284 region.end = l64 + sz64;
285
286 pcibios_bus_to_resource(dev->bus, res, ®ion);
287 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
288
289 /*
290 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
291 * the corresponding resource address (the physical address used by
292 * the CPU. Converting that resource address back to a bus address
293 * should yield the original BAR value:
294 *
295 * resource_to_bus(bus_to_resource(A)) == A
296 *
297 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
298 * be claimed by the device.
299 */
300 if (inverted_region.start != region.start) {
301 res->flags |= IORESOURCE_UNSET;
302 res->start = 0;
303 res->end = region.end - region.start;
304 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
305 pos, (unsigned long long)region.start);
306 }
307
308 goto out;
309
310
311fail:
312 res->flags = 0;
313out:
314 if (res->flags)
315 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
316
317 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
318}
319
320static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
321{
322 unsigned int pos, reg;
323
324 if (dev->non_compliant_bars)
325 return;
326
327 for (pos = 0; pos < howmany; pos++) {
328 struct resource *res = &dev->resource[pos];
329 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
330 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
331 }
332
333 if (rom) {
334 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
335 dev->rom_base_reg = rom;
336 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
337 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
338 __pci_read_base(dev, pci_bar_mem32, res, rom);
339 }
340}
341
342static void pci_read_bridge_io(struct pci_bus *child)
343{
344 struct pci_dev *dev = child->self;
345 u8 io_base_lo, io_limit_lo;
346 unsigned long io_mask, io_granularity, base, limit;
347 struct pci_bus_region region;
348 struct resource *res;
349
350 io_mask = PCI_IO_RANGE_MASK;
351 io_granularity = 0x1000;
352 if (dev->io_window_1k) {
353 /* Support 1K I/O space granularity */
354 io_mask = PCI_IO_1K_RANGE_MASK;
355 io_granularity = 0x400;
356 }
357
358 res = child->resource[0];
359 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
360 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
361 base = (io_base_lo & io_mask) << 8;
362 limit = (io_limit_lo & io_mask) << 8;
363
364 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
365 u16 io_base_hi, io_limit_hi;
366
367 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
368 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
369 base |= ((unsigned long) io_base_hi << 16);
370 limit |= ((unsigned long) io_limit_hi << 16);
371 }
372
373 if (base <= limit) {
374 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
375 region.start = base;
376 region.end = limit + io_granularity - 1;
377 pcibios_bus_to_resource(dev->bus, res, ®ion);
378 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
379 }
380}
381
382static void pci_read_bridge_mmio(struct pci_bus *child)
383{
384 struct pci_dev *dev = child->self;
385 u16 mem_base_lo, mem_limit_lo;
386 unsigned long base, limit;
387 struct pci_bus_region region;
388 struct resource *res;
389
390 res = child->resource[1];
391 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
392 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
393 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
394 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
395 if (base <= limit) {
396 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
397 region.start = base;
398 region.end = limit + 0xfffff;
399 pcibios_bus_to_resource(dev->bus, res, ®ion);
400 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
401 }
402}
403
404static void pci_read_bridge_mmio_pref(struct pci_bus *child)
405{
406 struct pci_dev *dev = child->self;
407 u16 mem_base_lo, mem_limit_lo;
408 u64 base64, limit64;
409 pci_bus_addr_t base, limit;
410 struct pci_bus_region region;
411 struct resource *res;
412
413 res = child->resource[2];
414 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
415 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
416 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
417 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
418
419 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
420 u32 mem_base_hi, mem_limit_hi;
421
422 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
423 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
424
425 /*
426 * Some bridges set the base > limit by default, and some
427 * (broken) BIOSes do not initialize them. If we find
428 * this, just assume they are not being used.
429 */
430 if (mem_base_hi <= mem_limit_hi) {
431 base64 |= (u64) mem_base_hi << 32;
432 limit64 |= (u64) mem_limit_hi << 32;
433 }
434 }
435
436 base = (pci_bus_addr_t) base64;
437 limit = (pci_bus_addr_t) limit64;
438
439 if (base != base64) {
440 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
441 (unsigned long long) base64);
442 return;
443 }
444
445 if (base <= limit) {
446 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
447 IORESOURCE_MEM | IORESOURCE_PREFETCH;
448 if (res->flags & PCI_PREF_RANGE_TYPE_64)
449 res->flags |= IORESOURCE_MEM_64;
450 region.start = base;
451 region.end = limit + 0xfffff;
452 pcibios_bus_to_resource(dev->bus, res, ®ion);
453 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
454 }
455}
456
457void pci_read_bridge_bases(struct pci_bus *child)
458{
459 struct pci_dev *dev = child->self;
460 struct resource *res;
461 int i;
462
463 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
464 return;
465
466 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
467 &child->busn_res,
468 dev->transparent ? " (subtractive decode)" : "");
469
470 pci_bus_remove_resources(child);
471 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
472 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
473
474 pci_read_bridge_io(child);
475 pci_read_bridge_mmio(child);
476 pci_read_bridge_mmio_pref(child);
477
478 if (dev->transparent) {
479 pci_bus_for_each_resource(child->parent, res, i) {
480 if (res && res->flags) {
481 pci_bus_add_resource(child, res,
482 PCI_SUBTRACTIVE_DECODE);
483 dev_printk(KERN_DEBUG, &dev->dev,
484 " bridge window %pR (subtractive decode)\n",
485 res);
486 }
487 }
488 }
489}
490
491static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
492{
493 struct pci_bus *b;
494
495 b = kzalloc(sizeof(*b), GFP_KERNEL);
496 if (!b)
497 return NULL;
498
499 INIT_LIST_HEAD(&b->node);
500 INIT_LIST_HEAD(&b->children);
501 INIT_LIST_HEAD(&b->devices);
502 INIT_LIST_HEAD(&b->slots);
503 INIT_LIST_HEAD(&b->resources);
504 b->max_bus_speed = PCI_SPEED_UNKNOWN;
505 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
506#ifdef CONFIG_PCI_DOMAINS_GENERIC
507 if (parent)
508 b->domain_nr = parent->domain_nr;
509#endif
510 return b;
511}
512
513static void pci_release_host_bridge_dev(struct device *dev)
514{
515 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
516
517 if (bridge->release_fn)
518 bridge->release_fn(bridge);
519
520 pci_free_resource_list(&bridge->windows);
521
522 kfree(bridge);
523}
524
525struct pci_host_bridge *pci_alloc_host_bridge(size_t priv)
526{
527 struct pci_host_bridge *bridge;
528
529 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL);
530 if (!bridge)
531 return NULL;
532
533 INIT_LIST_HEAD(&bridge->windows);
534
535 return bridge;
536}
537EXPORT_SYMBOL(pci_alloc_host_bridge);
538
539static const unsigned char pcix_bus_speed[] = {
540 PCI_SPEED_UNKNOWN, /* 0 */
541 PCI_SPEED_66MHz_PCIX, /* 1 */
542 PCI_SPEED_100MHz_PCIX, /* 2 */
543 PCI_SPEED_133MHz_PCIX, /* 3 */
544 PCI_SPEED_UNKNOWN, /* 4 */
545 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
546 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
547 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
548 PCI_SPEED_UNKNOWN, /* 8 */
549 PCI_SPEED_66MHz_PCIX_266, /* 9 */
550 PCI_SPEED_100MHz_PCIX_266, /* A */
551 PCI_SPEED_133MHz_PCIX_266, /* B */
552 PCI_SPEED_UNKNOWN, /* C */
553 PCI_SPEED_66MHz_PCIX_533, /* D */
554 PCI_SPEED_100MHz_PCIX_533, /* E */
555 PCI_SPEED_133MHz_PCIX_533 /* F */
556};
557
558const unsigned char pcie_link_speed[] = {
559 PCI_SPEED_UNKNOWN, /* 0 */
560 PCIE_SPEED_2_5GT, /* 1 */
561 PCIE_SPEED_5_0GT, /* 2 */
562 PCIE_SPEED_8_0GT, /* 3 */
563 PCI_SPEED_UNKNOWN, /* 4 */
564 PCI_SPEED_UNKNOWN, /* 5 */
565 PCI_SPEED_UNKNOWN, /* 6 */
566 PCI_SPEED_UNKNOWN, /* 7 */
567 PCI_SPEED_UNKNOWN, /* 8 */
568 PCI_SPEED_UNKNOWN, /* 9 */
569 PCI_SPEED_UNKNOWN, /* A */
570 PCI_SPEED_UNKNOWN, /* B */
571 PCI_SPEED_UNKNOWN, /* C */
572 PCI_SPEED_UNKNOWN, /* D */
573 PCI_SPEED_UNKNOWN, /* E */
574 PCI_SPEED_UNKNOWN /* F */
575};
576
577void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
578{
579 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
580}
581EXPORT_SYMBOL_GPL(pcie_update_link_speed);
582
583static unsigned char agp_speeds[] = {
584 AGP_UNKNOWN,
585 AGP_1X,
586 AGP_2X,
587 AGP_4X,
588 AGP_8X
589};
590
591static enum pci_bus_speed agp_speed(int agp3, int agpstat)
592{
593 int index = 0;
594
595 if (agpstat & 4)
596 index = 3;
597 else if (agpstat & 2)
598 index = 2;
599 else if (agpstat & 1)
600 index = 1;
601 else
602 goto out;
603
604 if (agp3) {
605 index += 2;
606 if (index == 5)
607 index = 0;
608 }
609
610 out:
611 return agp_speeds[index];
612}
613
614static void pci_set_bus_speed(struct pci_bus *bus)
615{
616 struct pci_dev *bridge = bus->self;
617 int pos;
618
619 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
620 if (!pos)
621 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
622 if (pos) {
623 u32 agpstat, agpcmd;
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
626 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
627
628 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
629 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
630 }
631
632 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
633 if (pos) {
634 u16 status;
635 enum pci_bus_speed max;
636
637 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
638 &status);
639
640 if (status & PCI_X_SSTATUS_533MHZ) {
641 max = PCI_SPEED_133MHz_PCIX_533;
642 } else if (status & PCI_X_SSTATUS_266MHZ) {
643 max = PCI_SPEED_133MHz_PCIX_266;
644 } else if (status & PCI_X_SSTATUS_133MHZ) {
645 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
646 max = PCI_SPEED_133MHz_PCIX_ECC;
647 else
648 max = PCI_SPEED_133MHz_PCIX;
649 } else {
650 max = PCI_SPEED_66MHz_PCIX;
651 }
652
653 bus->max_bus_speed = max;
654 bus->cur_bus_speed = pcix_bus_speed[
655 (status & PCI_X_SSTATUS_FREQ) >> 6];
656
657 return;
658 }
659
660 if (pci_is_pcie(bridge)) {
661 u32 linkcap;
662 u16 linksta;
663
664 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
665 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
666
667 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
668 pcie_update_link_speed(bus, linksta);
669 }
670}
671
672static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
673{
674 struct irq_domain *d;
675
676 /*
677 * Any firmware interface that can resolve the msi_domain
678 * should be called from here.
679 */
680 d = pci_host_bridge_of_msi_domain(bus);
681 if (!d)
682 d = pci_host_bridge_acpi_msi_domain(bus);
683
684#ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
685 /*
686 * If no IRQ domain was found via the OF tree, try looking it up
687 * directly through the fwnode_handle.
688 */
689 if (!d) {
690 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
691
692 if (fwnode)
693 d = irq_find_matching_fwnode(fwnode,
694 DOMAIN_BUS_PCI_MSI);
695 }
696#endif
697
698 return d;
699}
700
701static void pci_set_bus_msi_domain(struct pci_bus *bus)
702{
703 struct irq_domain *d;
704 struct pci_bus *b;
705
706 /*
707 * The bus can be a root bus, a subordinate bus, or a virtual bus
708 * created by an SR-IOV device. Walk up to the first bridge device
709 * found or derive the domain from the host bridge.
710 */
711 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
712 if (b->self)
713 d = dev_get_msi_domain(&b->self->dev);
714 }
715
716 if (!d)
717 d = pci_host_bridge_msi_domain(b);
718
719 dev_set_msi_domain(&bus->dev, d);
720}
721
722int pci_register_host_bridge(struct pci_host_bridge *bridge)
723{
724 struct device *parent = bridge->dev.parent;
725 struct resource_entry *window, *n;
726 struct pci_bus *bus, *b;
727 resource_size_t offset;
728 LIST_HEAD(resources);
729 struct resource *res;
730 char addr[64], *fmt;
731 const char *name;
732 int err;
733
734 bus = pci_alloc_bus(NULL);
735 if (!bus)
736 return -ENOMEM;
737
738 bridge->bus = bus;
739
740 /* temporarily move resources off the list */
741 list_splice_init(&bridge->windows, &resources);
742 bus->sysdata = bridge->sysdata;
743 bus->msi = bridge->msi;
744 bus->ops = bridge->ops;
745 bus->number = bus->busn_res.start = bridge->busnr;
746#ifdef CONFIG_PCI_DOMAINS_GENERIC
747 bus->domain_nr = pci_bus_find_domain_nr(bus, parent);
748#endif
749
750 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr);
751 if (b) {
752 /* If we already got to this bus through a different bridge, ignore it */
753 dev_dbg(&b->dev, "bus already known\n");
754 err = -EEXIST;
755 goto free;
756 }
757
758 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus),
759 bridge->busnr);
760
761 err = pcibios_root_bridge_prepare(bridge);
762 if (err)
763 goto free;
764
765 err = device_register(&bridge->dev);
766 if (err)
767 put_device(&bridge->dev);
768
769 bus->bridge = get_device(&bridge->dev);
770 device_enable_async_suspend(bus->bridge);
771 pci_set_bus_of_node(bus);
772 pci_set_bus_msi_domain(bus);
773
774 if (!parent)
775 set_dev_node(bus->bridge, pcibus_to_node(bus));
776
777 bus->dev.class = &pcibus_class;
778 bus->dev.parent = bus->bridge;
779
780 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number);
781 name = dev_name(&bus->dev);
782
783 err = device_register(&bus->dev);
784 if (err)
785 goto unregister;
786
787 pcibios_add_bus(bus);
788
789 /* Create legacy_io and legacy_mem files for this bus */
790 pci_create_legacy_files(bus);
791
792 if (parent)
793 dev_info(parent, "PCI host bridge to bus %s\n", name);
794 else
795 pr_info("PCI host bridge to bus %s\n", name);
796
797 /* Add initial resources to the bus */
798 resource_list_for_each_entry_safe(window, n, &resources) {
799 list_move_tail(&window->node, &bridge->windows);
800 offset = window->offset;
801 res = window->res;
802
803 if (res->flags & IORESOURCE_BUS)
804 pci_bus_insert_busn_res(bus, bus->number, res->end);
805 else
806 pci_bus_add_resource(bus, res, 0);
807
808 if (offset) {
809 if (resource_type(res) == IORESOURCE_IO)
810 fmt = " (bus address [%#06llx-%#06llx])";
811 else
812 fmt = " (bus address [%#010llx-%#010llx])";
813
814 snprintf(addr, sizeof(addr), fmt,
815 (unsigned long long)(res->start - offset),
816 (unsigned long long)(res->end - offset));
817 } else
818 addr[0] = '\0';
819
820 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr);
821 }
822
823 down_write(&pci_bus_sem);
824 list_add_tail(&bus->node, &pci_root_buses);
825 up_write(&pci_bus_sem);
826
827 return 0;
828
829unregister:
830 put_device(&bridge->dev);
831 device_unregister(&bridge->dev);
832
833free:
834 kfree(bus);
835 return err;
836}
837EXPORT_SYMBOL(pci_register_host_bridge);
838
839static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
840 struct pci_dev *bridge, int busnr)
841{
842 struct pci_bus *child;
843 int i;
844 int ret;
845
846 /*
847 * Allocate a new bus, and inherit stuff from the parent..
848 */
849 child = pci_alloc_bus(parent);
850 if (!child)
851 return NULL;
852
853 child->parent = parent;
854 child->ops = parent->ops;
855 child->msi = parent->msi;
856 child->sysdata = parent->sysdata;
857 child->bus_flags = parent->bus_flags;
858
859 /* initialize some portions of the bus device, but don't register it
860 * now as the parent is not properly set up yet.
861 */
862 child->dev.class = &pcibus_class;
863 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
864
865 /*
866 * Set up the primary, secondary and subordinate
867 * bus numbers.
868 */
869 child->number = child->busn_res.start = busnr;
870 child->primary = parent->busn_res.start;
871 child->busn_res.end = 0xff;
872
873 if (!bridge) {
874 child->dev.parent = parent->bridge;
875 goto add_dev;
876 }
877
878 child->self = bridge;
879 child->bridge = get_device(&bridge->dev);
880 child->dev.parent = child->bridge;
881 pci_set_bus_of_node(child);
882 pci_set_bus_speed(child);
883
884 /* Set up default resource pointers and names.. */
885 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
886 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
887 child->resource[i]->name = child->name;
888 }
889 bridge->subordinate = child;
890
891add_dev:
892 pci_set_bus_msi_domain(child);
893 ret = device_register(&child->dev);
894 WARN_ON(ret < 0);
895
896 pcibios_add_bus(child);
897
898 if (child->ops->add_bus) {
899 ret = child->ops->add_bus(child);
900 if (WARN_ON(ret < 0))
901 dev_err(&child->dev, "failed to add bus: %d\n", ret);
902 }
903
904 /* Create legacy_io and legacy_mem files for this bus */
905 pci_create_legacy_files(child);
906
907 return child;
908}
909
910struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
911 int busnr)
912{
913 struct pci_bus *child;
914
915 child = pci_alloc_child_bus(parent, dev, busnr);
916 if (child) {
917 down_write(&pci_bus_sem);
918 list_add_tail(&child->node, &parent->children);
919 up_write(&pci_bus_sem);
920 }
921 return child;
922}
923EXPORT_SYMBOL(pci_add_new_bus);
924
925static void pci_enable_crs(struct pci_dev *pdev)
926{
927 u16 root_cap = 0;
928
929 /* Enable CRS Software Visibility if supported */
930 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
931 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
932 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
933 PCI_EXP_RTCTL_CRSSVE);
934}
935
936/*
937 * If it's a bridge, configure it and scan the bus behind it.
938 * For CardBus bridges, we don't scan behind as the devices will
939 * be handled by the bridge driver itself.
940 *
941 * We need to process bridges in two passes -- first we scan those
942 * already configured by the BIOS and after we are done with all of
943 * them, we proceed to assigning numbers to the remaining buses in
944 * order to avoid overlaps between old and new bus numbers.
945 */
946int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
947{
948 struct pci_bus *child;
949 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
950 u32 buses, i, j = 0;
951 u16 bctl;
952 u8 primary, secondary, subordinate;
953 int broken = 0;
954
955 /*
956 * Make sure the bridge is powered on to be able to access config
957 * space of devices below it.
958 */
959 pm_runtime_get_sync(&dev->dev);
960
961 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
962 primary = buses & 0xFF;
963 secondary = (buses >> 8) & 0xFF;
964 subordinate = (buses >> 16) & 0xFF;
965
966 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
967 secondary, subordinate, pass);
968
969 if (!primary && (primary != bus->number) && secondary && subordinate) {
970 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
971 primary = bus->number;
972 }
973
974 /* Check if setup is sensible at all */
975 if (!pass &&
976 (primary != bus->number || secondary <= bus->number ||
977 secondary > subordinate)) {
978 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
979 secondary, subordinate);
980 broken = 1;
981 }
982
983 /* Disable MasterAbortMode during probing to avoid reporting
984 of bus errors (in some architectures) */
985 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
986 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
987 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
988
989 pci_enable_crs(dev);
990
991 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
992 !is_cardbus && !broken) {
993 unsigned int cmax;
994 /*
995 * Bus already configured by firmware, process it in the first
996 * pass and just note the configuration.
997 */
998 if (pass)
999 goto out;
1000
1001 /*
1002 * The bus might already exist for two reasons: Either we are
1003 * rescanning the bus or the bus is reachable through more than
1004 * one bridge. The second case can happen with the i450NX
1005 * chipset.
1006 */
1007 child = pci_find_bus(pci_domain_nr(bus), secondary);
1008 if (!child) {
1009 child = pci_add_new_bus(bus, dev, secondary);
1010 if (!child)
1011 goto out;
1012 child->primary = primary;
1013 pci_bus_insert_busn_res(child, secondary, subordinate);
1014 child->bridge_ctl = bctl;
1015 }
1016
1017 cmax = pci_scan_child_bus(child);
1018 if (cmax > subordinate)
1019 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
1020 subordinate, cmax);
1021 /* subordinate should equal child->busn_res.end */
1022 if (subordinate > max)
1023 max = subordinate;
1024 } else {
1025 /*
1026 * We need to assign a number to this bus which we always
1027 * do in the second pass.
1028 */
1029 if (!pass) {
1030 if (pcibios_assign_all_busses() || broken || is_cardbus)
1031 /* Temporarily disable forwarding of the
1032 configuration cycles on all bridges in
1033 this bus segment to avoid possible
1034 conflicts in the second pass between two
1035 bridges programmed with overlapping
1036 bus ranges. */
1037 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
1038 buses & ~0xffffff);
1039 goto out;
1040 }
1041
1042 /* Clear errors */
1043 pci_write_config_word(dev, PCI_STATUS, 0xffff);
1044
1045 /* Prevent assigning a bus number that already exists.
1046 * This can happen when a bridge is hot-plugged, so in
1047 * this case we only re-scan this bus. */
1048 child = pci_find_bus(pci_domain_nr(bus), max+1);
1049 if (!child) {
1050 child = pci_add_new_bus(bus, dev, max+1);
1051 if (!child)
1052 goto out;
1053 pci_bus_insert_busn_res(child, max+1, 0xff);
1054 }
1055 max++;
1056 buses = (buses & 0xff000000)
1057 | ((unsigned int)(child->primary) << 0)
1058 | ((unsigned int)(child->busn_res.start) << 8)
1059 | ((unsigned int)(child->busn_res.end) << 16);
1060
1061 /*
1062 * yenta.c forces a secondary latency timer of 176.
1063 * Copy that behaviour here.
1064 */
1065 if (is_cardbus) {
1066 buses &= ~0xff000000;
1067 buses |= CARDBUS_LATENCY_TIMER << 24;
1068 }
1069
1070 /*
1071 * We need to blast all three values with a single write.
1072 */
1073 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
1074
1075 if (!is_cardbus) {
1076 child->bridge_ctl = bctl;
1077 max = pci_scan_child_bus(child);
1078 } else {
1079 /*
1080 * For CardBus bridges, we leave 4 bus numbers
1081 * as cards with a PCI-to-PCI bridge can be
1082 * inserted later.
1083 */
1084 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
1085 struct pci_bus *parent = bus;
1086 if (pci_find_bus(pci_domain_nr(bus),
1087 max+i+1))
1088 break;
1089 while (parent->parent) {
1090 if ((!pcibios_assign_all_busses()) &&
1091 (parent->busn_res.end > max) &&
1092 (parent->busn_res.end <= max+i)) {
1093 j = 1;
1094 }
1095 parent = parent->parent;
1096 }
1097 if (j) {
1098 /*
1099 * Often, there are two cardbus bridges
1100 * -- try to leave one valid bus number
1101 * for each one.
1102 */
1103 i /= 2;
1104 break;
1105 }
1106 }
1107 max += i;
1108 }
1109 /*
1110 * Set the subordinate bus number to its real value.
1111 */
1112 pci_bus_update_busn_res_end(child, max);
1113 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
1114 }
1115
1116 sprintf(child->name,
1117 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
1118 pci_domain_nr(bus), child->number);
1119
1120 /* Has only triggered on CardBus, fixup is in yenta_socket */
1121 while (bus->parent) {
1122 if ((child->busn_res.end > bus->busn_res.end) ||
1123 (child->number > bus->busn_res.end) ||
1124 (child->number < bus->number) ||
1125 (child->busn_res.end < bus->number)) {
1126 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1127 &child->busn_res,
1128 (bus->number > child->busn_res.end &&
1129 bus->busn_res.end < child->number) ?
1130 "wholly" : "partially",
1131 bus->self->transparent ? " transparent" : "",
1132 dev_name(&bus->dev),
1133 &bus->busn_res);
1134 }
1135 bus = bus->parent;
1136 }
1137
1138out:
1139 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1140
1141 pm_runtime_put(&dev->dev);
1142
1143 return max;
1144}
1145EXPORT_SYMBOL(pci_scan_bridge);
1146
1147/*
1148 * Read interrupt line and base address registers.
1149 * The architecture-dependent code can tweak these, of course.
1150 */
1151static void pci_read_irq(struct pci_dev *dev)
1152{
1153 unsigned char irq;
1154
1155 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1156 dev->pin = irq;
1157 if (irq)
1158 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1159 dev->irq = irq;
1160}
1161
1162void set_pcie_port_type(struct pci_dev *pdev)
1163{
1164 int pos;
1165 u16 reg16;
1166 int type;
1167 struct pci_dev *parent;
1168
1169 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1170 if (!pos)
1171 return;
1172
1173 pdev->pcie_cap = pos;
1174 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
1175 pdev->pcie_flags_reg = reg16;
1176 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
1177 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1178
1179 /*
1180 * A Root Port or a PCI-to-PCIe bridge is always the upstream end
1181 * of a Link. No PCIe component has two Links. Two Links are
1182 * connected by a Switch that has a Port on each Link and internal
1183 * logic to connect the two Ports.
1184 */
1185 type = pci_pcie_type(pdev);
1186 if (type == PCI_EXP_TYPE_ROOT_PORT ||
1187 type == PCI_EXP_TYPE_PCIE_BRIDGE)
1188 pdev->has_secondary_link = 1;
1189 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1190 type == PCI_EXP_TYPE_DOWNSTREAM) {
1191 parent = pci_upstream_bridge(pdev);
1192
1193 /*
1194 * Usually there's an upstream device (Root Port or Switch
1195 * Downstream Port), but we can't assume one exists.
1196 */
1197 if (parent && !parent->has_secondary_link)
1198 pdev->has_secondary_link = 1;
1199 }
1200}
1201
1202void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1203{
1204 u32 reg32;
1205
1206 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
1207 if (reg32 & PCI_EXP_SLTCAP_HPC)
1208 pdev->is_hotplug_bridge = 1;
1209}
1210
1211/**
1212 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1213 * @dev: PCI device
1214 *
1215 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1216 * when forwarding a type1 configuration request the bridge must check that
1217 * the extended register address field is zero. The bridge is not permitted
1218 * to forward the transactions and must handle it as an Unsupported Request.
1219 * Some bridges do not follow this rule and simply drop the extended register
1220 * bits, resulting in the standard config space being aliased, every 256
1221 * bytes across the entire configuration space. Test for this condition by
1222 * comparing the first dword of each potential alias to the vendor/device ID.
1223 * Known offenders:
1224 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1225 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1226 */
1227static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1228{
1229#ifdef CONFIG_PCI_QUIRKS
1230 int pos;
1231 u32 header, tmp;
1232
1233 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1234
1235 for (pos = PCI_CFG_SPACE_SIZE;
1236 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1237 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1238 || header != tmp)
1239 return false;
1240 }
1241
1242 return true;
1243#else
1244 return false;
1245#endif
1246}
1247
1248/**
1249 * pci_cfg_space_size - get the configuration space size of the PCI device.
1250 * @dev: PCI device
1251 *
1252 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1253 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1254 * access it. Maybe we don't have a way to generate extended config space
1255 * accesses, or the device is behind a reverse Express bridge. So we try
1256 * reading the dword at 0x100 which must either be 0 or a valid extended
1257 * capability header.
1258 */
1259static int pci_cfg_space_size_ext(struct pci_dev *dev)
1260{
1261 u32 status;
1262 int pos = PCI_CFG_SPACE_SIZE;
1263
1264 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1265 return PCI_CFG_SPACE_SIZE;
1266 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1267 return PCI_CFG_SPACE_SIZE;
1268
1269 return PCI_CFG_SPACE_EXP_SIZE;
1270}
1271
1272int pci_cfg_space_size(struct pci_dev *dev)
1273{
1274 int pos;
1275 u32 status;
1276 u16 class;
1277
1278 class = dev->class >> 8;
1279 if (class == PCI_CLASS_BRIDGE_HOST)
1280 return pci_cfg_space_size_ext(dev);
1281
1282 if (pci_is_pcie(dev))
1283 return pci_cfg_space_size_ext(dev);
1284
1285 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1286 if (!pos)
1287 return PCI_CFG_SPACE_SIZE;
1288
1289 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1290 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1291 return pci_cfg_space_size_ext(dev);
1292
1293 return PCI_CFG_SPACE_SIZE;
1294}
1295
1296#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1297
1298static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1299{
1300 /*
1301 * Disable the MSI hardware to avoid screaming interrupts
1302 * during boot. This is the power on reset default so
1303 * usually this should be a noop.
1304 */
1305 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1306 if (dev->msi_cap)
1307 pci_msi_set_enable(dev, 0);
1308
1309 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1310 if (dev->msix_cap)
1311 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1312}
1313
1314/**
1315 * pci_setup_device - fill in class and map information of a device
1316 * @dev: the device structure to fill
1317 *
1318 * Initialize the device structure with information about the device's
1319 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1320 * Called at initialisation of the PCI subsystem and by CardBus services.
1321 * Returns 0 on success and negative if unknown type of device (not normal,
1322 * bridge or CardBus).
1323 */
1324int pci_setup_device(struct pci_dev *dev)
1325{
1326 u32 class;
1327 u16 cmd;
1328 u8 hdr_type;
1329 int pos = 0;
1330 struct pci_bus_region region;
1331 struct resource *res;
1332
1333 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1334 return -EIO;
1335
1336 dev->sysdata = dev->bus->sysdata;
1337 dev->dev.parent = dev->bus->bridge;
1338 dev->dev.bus = &pci_bus_type;
1339 dev->hdr_type = hdr_type & 0x7f;
1340 dev->multifunction = !!(hdr_type & 0x80);
1341 dev->error_state = pci_channel_io_normal;
1342 set_pcie_port_type(dev);
1343
1344 pci_dev_assign_slot(dev);
1345 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1346 set this higher, assuming the system even supports it. */
1347 dev->dma_mask = 0xffffffff;
1348
1349 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1350 dev->bus->number, PCI_SLOT(dev->devfn),
1351 PCI_FUNC(dev->devfn));
1352
1353 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1354 dev->revision = class & 0xff;
1355 dev->class = class >> 8; /* upper 3 bytes */
1356
1357 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1358 dev->vendor, dev->device, dev->hdr_type, dev->class);
1359
1360 /* need to have dev->class ready */
1361 dev->cfg_size = pci_cfg_space_size(dev);
1362
1363 /* "Unknown power state" */
1364 dev->current_state = PCI_UNKNOWN;
1365
1366 /* Early fixups, before probing the BARs */
1367 pci_fixup_device(pci_fixup_early, dev);
1368 /* device class may be changed after fixup */
1369 class = dev->class >> 8;
1370
1371 if (dev->non_compliant_bars) {
1372 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1373 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1374 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1375 cmd &= ~PCI_COMMAND_IO;
1376 cmd &= ~PCI_COMMAND_MEMORY;
1377 pci_write_config_word(dev, PCI_COMMAND, cmd);
1378 }
1379 }
1380
1381 switch (dev->hdr_type) { /* header type */
1382 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1383 if (class == PCI_CLASS_BRIDGE_PCI)
1384 goto bad;
1385 pci_read_irq(dev);
1386 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1387 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1388 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1389
1390 /*
1391 * Do the ugly legacy mode stuff here rather than broken chip
1392 * quirk code. Legacy mode ATA controllers have fixed
1393 * addresses. These are not always echoed in BAR0-3, and
1394 * BAR0-3 in a few cases contain junk!
1395 */
1396 if (class == PCI_CLASS_STORAGE_IDE) {
1397 u8 progif;
1398 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1399 if ((progif & 1) == 0) {
1400 region.start = 0x1F0;
1401 region.end = 0x1F7;
1402 res = &dev->resource[0];
1403 res->flags = LEGACY_IO_RESOURCE;
1404 pcibios_bus_to_resource(dev->bus, res, ®ion);
1405 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1406 res);
1407 region.start = 0x3F6;
1408 region.end = 0x3F6;
1409 res = &dev->resource[1];
1410 res->flags = LEGACY_IO_RESOURCE;
1411 pcibios_bus_to_resource(dev->bus, res, ®ion);
1412 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1413 res);
1414 }
1415 if ((progif & 4) == 0) {
1416 region.start = 0x170;
1417 region.end = 0x177;
1418 res = &dev->resource[2];
1419 res->flags = LEGACY_IO_RESOURCE;
1420 pcibios_bus_to_resource(dev->bus, res, ®ion);
1421 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1422 res);
1423 region.start = 0x376;
1424 region.end = 0x376;
1425 res = &dev->resource[3];
1426 res->flags = LEGACY_IO_RESOURCE;
1427 pcibios_bus_to_resource(dev->bus, res, ®ion);
1428 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1429 res);
1430 }
1431 }
1432 break;
1433
1434 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1435 if (class != PCI_CLASS_BRIDGE_PCI)
1436 goto bad;
1437 /* The PCI-to-PCI bridge spec requires that subtractive
1438 decoding (i.e. transparent) bridge must have programming
1439 interface code of 0x01. */
1440 pci_read_irq(dev);
1441 dev->transparent = ((dev->class & 0xff) == 1);
1442 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1443 set_pcie_hotplug_bridge(dev);
1444 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1445 if (pos) {
1446 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1447 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1448 }
1449 break;
1450
1451 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1452 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1453 goto bad;
1454 pci_read_irq(dev);
1455 pci_read_bases(dev, 1, 0);
1456 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1457 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1458 break;
1459
1460 default: /* unknown header */
1461 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1462 dev->hdr_type);
1463 return -EIO;
1464
1465 bad:
1466 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1467 dev->class, dev->hdr_type);
1468 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1469 }
1470
1471 /* We found a fine healthy device, go go go... */
1472 return 0;
1473}
1474
1475static void pci_configure_mps(struct pci_dev *dev)
1476{
1477 struct pci_dev *bridge = pci_upstream_bridge(dev);
1478 int mps, p_mps, rc;
1479
1480 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1481 return;
1482
1483 mps = pcie_get_mps(dev);
1484 p_mps = pcie_get_mps(bridge);
1485
1486 if (mps == p_mps)
1487 return;
1488
1489 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1490 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1491 mps, pci_name(bridge), p_mps);
1492 return;
1493 }
1494
1495 /*
1496 * Fancier MPS configuration is done later by
1497 * pcie_bus_configure_settings()
1498 */
1499 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1500 return;
1501
1502 rc = pcie_set_mps(dev, p_mps);
1503 if (rc) {
1504 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1505 p_mps);
1506 return;
1507 }
1508
1509 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1510 p_mps, mps, 128 << dev->pcie_mpss);
1511}
1512
1513static struct hpp_type0 pci_default_type0 = {
1514 .revision = 1,
1515 .cache_line_size = 8,
1516 .latency_timer = 0x40,
1517 .enable_serr = 0,
1518 .enable_perr = 0,
1519};
1520
1521static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1522{
1523 u16 pci_cmd, pci_bctl;
1524
1525 if (!hpp)
1526 hpp = &pci_default_type0;
1527
1528 if (hpp->revision > 1) {
1529 dev_warn(&dev->dev,
1530 "PCI settings rev %d not supported; using defaults\n",
1531 hpp->revision);
1532 hpp = &pci_default_type0;
1533 }
1534
1535 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1536 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1537 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1538 if (hpp->enable_serr)
1539 pci_cmd |= PCI_COMMAND_SERR;
1540 if (hpp->enable_perr)
1541 pci_cmd |= PCI_COMMAND_PARITY;
1542 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1543
1544 /* Program bridge control value */
1545 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1546 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1547 hpp->latency_timer);
1548 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1549 if (hpp->enable_serr)
1550 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1551 if (hpp->enable_perr)
1552 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1553 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1554 }
1555}
1556
1557static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1558{
1559 if (hpp)
1560 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1561}
1562
1563static bool pcie_root_rcb_set(struct pci_dev *dev)
1564{
1565 struct pci_dev *rp = pcie_find_root_port(dev);
1566 u16 lnkctl;
1567
1568 if (!rp)
1569 return false;
1570
1571 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
1572 if (lnkctl & PCI_EXP_LNKCTL_RCB)
1573 return true;
1574
1575 return false;
1576}
1577
1578static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1579{
1580 int pos;
1581 u32 reg32;
1582
1583 if (!hpp)
1584 return;
1585
1586 if (hpp->revision > 1) {
1587 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1588 hpp->revision);
1589 return;
1590 }
1591
1592 /*
1593 * Don't allow _HPX to change MPS or MRRS settings. We manage
1594 * those to make sure they're consistent with the rest of the
1595 * platform.
1596 */
1597 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1598 PCI_EXP_DEVCTL_READRQ;
1599 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1600 PCI_EXP_DEVCTL_READRQ);
1601
1602 /* Initialize Device Control Register */
1603 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1604 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1605
1606 /* Initialize Link Control Register */
1607 if (pcie_cap_has_lnkctl(dev)) {
1608
1609 /*
1610 * If the Root Port supports Read Completion Boundary of
1611 * 128, set RCB to 128. Otherwise, clear it.
1612 */
1613 hpp->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
1614 hpp->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
1615 if (pcie_root_rcb_set(dev))
1616 hpp->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
1617
1618 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1619 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1620 }
1621
1622 /* Find Advanced Error Reporting Enhanced Capability */
1623 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1624 if (!pos)
1625 return;
1626
1627 /* Initialize Uncorrectable Error Mask Register */
1628 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1629 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1630 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1631
1632 /* Initialize Uncorrectable Error Severity Register */
1633 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1634 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1635 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1636
1637 /* Initialize Correctable Error Mask Register */
1638 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1639 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1640 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1641
1642 /* Initialize Advanced Error Capabilities and Control Register */
1643 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1644 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1645 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1646
1647 /*
1648 * FIXME: The following two registers are not supported yet.
1649 *
1650 * o Secondary Uncorrectable Error Severity Register
1651 * o Secondary Uncorrectable Error Mask Register
1652 */
1653}
1654
1655static void pci_configure_device(struct pci_dev *dev)
1656{
1657 struct hotplug_params hpp;
1658 int ret;
1659
1660 pci_configure_mps(dev);
1661
1662 memset(&hpp, 0, sizeof(hpp));
1663 ret = pci_get_hp_params(dev, &hpp);
1664 if (ret)
1665 return;
1666
1667 program_hpp_type2(dev, hpp.t2);
1668 program_hpp_type1(dev, hpp.t1);
1669 program_hpp_type0(dev, hpp.t0);
1670}
1671
1672static void pci_release_capabilities(struct pci_dev *dev)
1673{
1674 pci_vpd_release(dev);
1675 pci_iov_release(dev);
1676 pci_free_cap_save_buffers(dev);
1677}
1678
1679/**
1680 * pci_release_dev - free a pci device structure when all users of it are finished.
1681 * @dev: device that's been disconnected
1682 *
1683 * Will be called only by the device core when all users of this pci device are
1684 * done.
1685 */
1686static void pci_release_dev(struct device *dev)
1687{
1688 struct pci_dev *pci_dev;
1689
1690 pci_dev = to_pci_dev(dev);
1691 pci_release_capabilities(pci_dev);
1692 pci_release_of_node(pci_dev);
1693 pcibios_release_device(pci_dev);
1694 pci_bus_put(pci_dev->bus);
1695 kfree(pci_dev->driver_override);
1696 kfree(pci_dev->dma_alias_mask);
1697 kfree(pci_dev);
1698}
1699
1700struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1701{
1702 struct pci_dev *dev;
1703
1704 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1705 if (!dev)
1706 return NULL;
1707
1708 INIT_LIST_HEAD(&dev->bus_list);
1709 dev->dev.type = &pci_dev_type;
1710 dev->bus = pci_bus_get(bus);
1711
1712 return dev;
1713}
1714EXPORT_SYMBOL(pci_alloc_dev);
1715
1716bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1717 int crs_timeout)
1718{
1719 int delay = 1;
1720
1721 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1722 return false;
1723
1724 /* some broken boards return 0 or ~0 if a slot is empty: */
1725 if (*l == 0xffffffff || *l == 0x00000000 ||
1726 *l == 0x0000ffff || *l == 0xffff0000)
1727 return false;
1728
1729 /*
1730 * Configuration Request Retry Status. Some root ports return the
1731 * actual device ID instead of the synthetic ID (0xFFFF) required
1732 * by the PCIe spec. Ignore the device ID and only check for
1733 * (vendor id == 1).
1734 */
1735 while ((*l & 0xffff) == 0x0001) {
1736 if (!crs_timeout)
1737 return false;
1738
1739 msleep(delay);
1740 delay *= 2;
1741 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1742 return false;
1743 /* Card hasn't responded in 60 seconds? Must be stuck. */
1744 if (delay > crs_timeout) {
1745 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1746 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1747 PCI_FUNC(devfn));
1748 return false;
1749 }
1750 }
1751
1752 return true;
1753}
1754EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1755
1756/*
1757 * Read the config data for a PCI device, sanity-check it
1758 * and fill in the dev structure...
1759 */
1760static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1761{
1762 struct pci_dev *dev;
1763 u32 l;
1764
1765 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1766 return NULL;
1767
1768 dev = pci_alloc_dev(bus);
1769 if (!dev)
1770 return NULL;
1771
1772 dev->devfn = devfn;
1773 dev->vendor = l & 0xffff;
1774 dev->device = (l >> 16) & 0xffff;
1775
1776 pci_set_of_node(dev);
1777
1778 if (pci_setup_device(dev)) {
1779 pci_bus_put(dev->bus);
1780 kfree(dev);
1781 return NULL;
1782 }
1783
1784 return dev;
1785}
1786
1787static void pci_init_capabilities(struct pci_dev *dev)
1788{
1789 /* Enhanced Allocation */
1790 pci_ea_init(dev);
1791
1792 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1793 pci_msi_setup_pci_dev(dev);
1794
1795 /* Buffers for saving PCIe and PCI-X capabilities */
1796 pci_allocate_cap_save_buffers(dev);
1797
1798 /* Power Management */
1799 pci_pm_init(dev);
1800
1801 /* Vital Product Data */
1802 pci_vpd_init(dev);
1803
1804 /* Alternative Routing-ID Forwarding */
1805 pci_configure_ari(dev);
1806
1807 /* Single Root I/O Virtualization */
1808 pci_iov_init(dev);
1809
1810 /* Address Translation Services */
1811 pci_ats_init(dev);
1812
1813 /* Enable ACS P2P upstream forwarding */
1814 pci_enable_acs(dev);
1815
1816 /* Precision Time Measurement */
1817 pci_ptm_init(dev);
1818
1819 /* Advanced Error Reporting */
1820 pci_aer_init(dev);
1821}
1822
1823/*
1824 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1825 * devices. Firmware interfaces that can select the MSI domain on a
1826 * per-device basis should be called from here.
1827 */
1828static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1829{
1830 struct irq_domain *d;
1831
1832 /*
1833 * If a domain has been set through the pcibios_add_device
1834 * callback, then this is the one (platform code knows best).
1835 */
1836 d = dev_get_msi_domain(&dev->dev);
1837 if (d)
1838 return d;
1839
1840 /*
1841 * Let's see if we have a firmware interface able to provide
1842 * the domain.
1843 */
1844 d = pci_msi_get_device_domain(dev);
1845 if (d)
1846 return d;
1847
1848 return NULL;
1849}
1850
1851static void pci_set_msi_domain(struct pci_dev *dev)
1852{
1853 struct irq_domain *d;
1854
1855 /*
1856 * If the platform or firmware interfaces cannot supply a
1857 * device-specific MSI domain, then inherit the default domain
1858 * from the host bridge itself.
1859 */
1860 d = pci_dev_msi_domain(dev);
1861 if (!d)
1862 d = dev_get_msi_domain(&dev->bus->dev);
1863
1864 dev_set_msi_domain(&dev->dev, d);
1865}
1866
1867/**
1868 * pci_dma_configure - Setup DMA configuration
1869 * @dev: ptr to pci_dev struct of the PCI device
1870 *
1871 * Function to update PCI devices's DMA configuration using the same
1872 * info from the OF node or ACPI node of host bridge's parent (if any).
1873 */
1874static void pci_dma_configure(struct pci_dev *dev)
1875{
1876 struct device *bridge = pci_get_host_bridge_device(dev);
1877
1878 if (IS_ENABLED(CONFIG_OF) &&
1879 bridge->parent && bridge->parent->of_node) {
1880 of_dma_configure(&dev->dev, bridge->parent->of_node);
1881 } else if (has_acpi_companion(bridge)) {
1882 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1883 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1884
1885 if (attr == DEV_DMA_NOT_SUPPORTED)
1886 dev_warn(&dev->dev, "DMA not supported.\n");
1887 else
1888 acpi_dma_configure(&dev->dev, attr);
1889 }
1890
1891 pci_put_host_bridge_device(bridge);
1892}
1893
1894void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1895{
1896 int ret;
1897
1898 pci_configure_device(dev);
1899
1900 device_initialize(&dev->dev);
1901 dev->dev.release = pci_release_dev;
1902
1903 set_dev_node(&dev->dev, pcibus_to_node(bus));
1904 dev->dev.dma_mask = &dev->dma_mask;
1905 dev->dev.dma_parms = &dev->dma_parms;
1906 dev->dev.coherent_dma_mask = 0xffffffffull;
1907 pci_dma_configure(dev);
1908
1909 pci_set_dma_max_seg_size(dev, 65536);
1910 pci_set_dma_seg_boundary(dev, 0xffffffff);
1911
1912 /* Fix up broken headers */
1913 pci_fixup_device(pci_fixup_header, dev);
1914
1915 /* moved out from quirk header fixup code */
1916 pci_reassigndev_resource_alignment(dev);
1917
1918 /* Clear the state_saved flag. */
1919 dev->state_saved = false;
1920
1921 /* Initialize various capabilities */
1922 pci_init_capabilities(dev);
1923
1924 /*
1925 * Add the device to our list of discovered devices
1926 * and the bus list for fixup functions, etc.
1927 */
1928 down_write(&pci_bus_sem);
1929 list_add_tail(&dev->bus_list, &bus->devices);
1930 up_write(&pci_bus_sem);
1931
1932 ret = pcibios_add_device(dev);
1933 WARN_ON(ret < 0);
1934
1935 /* Setup MSI irq domain */
1936 pci_set_msi_domain(dev);
1937
1938 /* Notifier could use PCI capabilities */
1939 dev->match_driver = false;
1940 ret = device_add(&dev->dev);
1941 WARN_ON(ret < 0);
1942}
1943
1944struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1945{
1946 struct pci_dev *dev;
1947
1948 dev = pci_get_slot(bus, devfn);
1949 if (dev) {
1950 pci_dev_put(dev);
1951 return dev;
1952 }
1953
1954 dev = pci_scan_device(bus, devfn);
1955 if (!dev)
1956 return NULL;
1957
1958 pci_device_add(dev, bus);
1959
1960 return dev;
1961}
1962EXPORT_SYMBOL(pci_scan_single_device);
1963
1964static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1965{
1966 int pos;
1967 u16 cap = 0;
1968 unsigned next_fn;
1969
1970 if (pci_ari_enabled(bus)) {
1971 if (!dev)
1972 return 0;
1973 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1974 if (!pos)
1975 return 0;
1976
1977 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1978 next_fn = PCI_ARI_CAP_NFN(cap);
1979 if (next_fn <= fn)
1980 return 0; /* protect against malformed list */
1981
1982 return next_fn;
1983 }
1984
1985 /* dev may be NULL for non-contiguous multifunction devices */
1986 if (!dev || dev->multifunction)
1987 return (fn + 1) % 8;
1988
1989 return 0;
1990}
1991
1992static int only_one_child(struct pci_bus *bus)
1993{
1994 struct pci_dev *parent = bus->self;
1995
1996 if (!parent || !pci_is_pcie(parent))
1997 return 0;
1998 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1999 return 1;
2000
2001 /*
2002 * PCIe downstream ports are bridges that normally lead to only a
2003 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
2004 * possible devices, not just device 0. See PCIe spec r3.0,
2005 * sec 7.3.1.
2006 */
2007 if (parent->has_secondary_link &&
2008 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
2009 return 1;
2010 return 0;
2011}
2012
2013/**
2014 * pci_scan_slot - scan a PCI slot on a bus for devices.
2015 * @bus: PCI bus to scan
2016 * @devfn: slot number to scan (must have zero function.)
2017 *
2018 * Scan a PCI slot on the specified PCI bus for devices, adding
2019 * discovered devices to the @bus->devices list. New devices
2020 * will not have is_added set.
2021 *
2022 * Returns the number of new devices found.
2023 */
2024int pci_scan_slot(struct pci_bus *bus, int devfn)
2025{
2026 unsigned fn, nr = 0;
2027 struct pci_dev *dev;
2028
2029 if (only_one_child(bus) && (devfn > 0))
2030 return 0; /* Already scanned the entire slot */
2031
2032 dev = pci_scan_single_device(bus, devfn);
2033 if (!dev)
2034 return 0;
2035 if (!dev->is_added)
2036 nr++;
2037
2038 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
2039 dev = pci_scan_single_device(bus, devfn + fn);
2040 if (dev) {
2041 if (!dev->is_added)
2042 nr++;
2043 dev->multifunction = 1;
2044 }
2045 }
2046
2047 /* only one slot has pcie device */
2048 if (bus->self && nr)
2049 pcie_aspm_init_link_state(bus->self);
2050
2051 return nr;
2052}
2053EXPORT_SYMBOL(pci_scan_slot);
2054
2055static int pcie_find_smpss(struct pci_dev *dev, void *data)
2056{
2057 u8 *smpss = data;
2058
2059 if (!pci_is_pcie(dev))
2060 return 0;
2061
2062 /*
2063 * We don't have a way to change MPS settings on devices that have
2064 * drivers attached. A hot-added device might support only the minimum
2065 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
2066 * where devices may be hot-added, we limit the fabric MPS to 128 so
2067 * hot-added devices will work correctly.
2068 *
2069 * However, if we hot-add a device to a slot directly below a Root
2070 * Port, it's impossible for there to be other existing devices below
2071 * the port. We don't limit the MPS in this case because we can
2072 * reconfigure MPS on both the Root Port and the hot-added device,
2073 * and there are no other devices involved.
2074 *
2075 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
2076 */
2077 if (dev->is_hotplug_bridge &&
2078 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
2079 *smpss = 0;
2080
2081 if (*smpss > dev->pcie_mpss)
2082 *smpss = dev->pcie_mpss;
2083
2084 return 0;
2085}
2086
2087static void pcie_write_mps(struct pci_dev *dev, int mps)
2088{
2089 int rc;
2090
2091 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
2092 mps = 128 << dev->pcie_mpss;
2093
2094 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
2095 dev->bus->self)
2096 /* For "Performance", the assumption is made that
2097 * downstream communication will never be larger than
2098 * the MRRS. So, the MPS only needs to be configured
2099 * for the upstream communication. This being the case,
2100 * walk from the top down and set the MPS of the child
2101 * to that of the parent bus.
2102 *
2103 * Configure the device MPS with the smaller of the
2104 * device MPSS or the bridge MPS (which is assumed to be
2105 * properly configured at this point to the largest
2106 * allowable MPS based on its parent bus).
2107 */
2108 mps = min(mps, pcie_get_mps(dev->bus->self));
2109 }
2110
2111 rc = pcie_set_mps(dev, mps);
2112 if (rc)
2113 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
2114}
2115
2116static void pcie_write_mrrs(struct pci_dev *dev)
2117{
2118 int rc, mrrs;
2119
2120 /* In the "safe" case, do not configure the MRRS. There appear to be
2121 * issues with setting MRRS to 0 on a number of devices.
2122 */
2123 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
2124 return;
2125
2126 /* For Max performance, the MRRS must be set to the largest supported
2127 * value. However, it cannot be configured larger than the MPS the
2128 * device or the bus can support. This should already be properly
2129 * configured by a prior call to pcie_write_mps.
2130 */
2131 mrrs = pcie_get_mps(dev);
2132
2133 /* MRRS is a R/W register. Invalid values can be written, but a
2134 * subsequent read will verify if the value is acceptable or not.
2135 * If the MRRS value provided is not acceptable (e.g., too large),
2136 * shrink the value until it is acceptable to the HW.
2137 */
2138 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
2139 rc = pcie_set_readrq(dev, mrrs);
2140 if (!rc)
2141 break;
2142
2143 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
2144 mrrs /= 2;
2145 }
2146
2147 if (mrrs < 128)
2148 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
2149}
2150
2151static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
2152{
2153 int mps, orig_mps;
2154
2155 if (!pci_is_pcie(dev))
2156 return 0;
2157
2158 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2159 pcie_bus_config == PCIE_BUS_DEFAULT)
2160 return 0;
2161
2162 mps = 128 << *(u8 *)data;
2163 orig_mps = pcie_get_mps(dev);
2164
2165 pcie_write_mps(dev, mps);
2166 pcie_write_mrrs(dev);
2167
2168 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2169 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2170 orig_mps, pcie_get_readrq(dev));
2171
2172 return 0;
2173}
2174
2175/* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2176 * parents then children fashion. If this changes, then this code will not
2177 * work as designed.
2178 */
2179void pcie_bus_configure_settings(struct pci_bus *bus)
2180{
2181 u8 smpss = 0;
2182
2183 if (!bus->self)
2184 return;
2185
2186 if (!pci_is_pcie(bus->self))
2187 return;
2188
2189 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2190 * to be aware of the MPS of the destination. To work around this,
2191 * simply force the MPS of the entire system to the smallest possible.
2192 */
2193 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2194 smpss = 0;
2195
2196 if (pcie_bus_config == PCIE_BUS_SAFE) {
2197 smpss = bus->self->pcie_mpss;
2198
2199 pcie_find_smpss(bus->self, &smpss);
2200 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2201 }
2202
2203 pcie_bus_configure_set(bus->self, &smpss);
2204 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2205}
2206EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2207
2208unsigned int pci_scan_child_bus(struct pci_bus *bus)
2209{
2210 unsigned int devfn, pass, max = bus->busn_res.start;
2211 struct pci_dev *dev;
2212
2213 dev_dbg(&bus->dev, "scanning bus\n");
2214
2215 /* Go find them, Rover! */
2216 for (devfn = 0; devfn < 0x100; devfn += 8)
2217 pci_scan_slot(bus, devfn);
2218
2219 /* Reserve buses for SR-IOV capability. */
2220 max += pci_iov_bus_range(bus);
2221
2222 /*
2223 * After performing arch-dependent fixup of the bus, look behind
2224 * all PCI-to-PCI bridges on this bus.
2225 */
2226 if (!bus->is_added) {
2227 dev_dbg(&bus->dev, "fixups for bus\n");
2228 pcibios_fixup_bus(bus);
2229 bus->is_added = 1;
2230 }
2231
2232 for (pass = 0; pass < 2; pass++)
2233 list_for_each_entry(dev, &bus->devices, bus_list) {
2234 if (pci_is_bridge(dev))
2235 max = pci_scan_bridge(bus, dev, max, pass);
2236 }
2237
2238 /*
2239 * Make sure a hotplug bridge has at least the minimum requested
2240 * number of buses.
2241 */
2242 if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
2243 if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
2244 max = bus->busn_res.start + pci_hotplug_bus_size - 1;
2245 }
2246
2247 /*
2248 * We've scanned the bus and so we know all about what's on
2249 * the other side of any bridges that may be on this bus plus
2250 * any devices.
2251 *
2252 * Return how far we've got finding sub-buses.
2253 */
2254 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2255 return max;
2256}
2257EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2258
2259/**
2260 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2261 * @bridge: Host bridge to set up.
2262 *
2263 * Default empty implementation. Replace with an architecture-specific setup
2264 * routine, if necessary.
2265 */
2266int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2267{
2268 return 0;
2269}
2270
2271void __weak pcibios_add_bus(struct pci_bus *bus)
2272{
2273}
2274
2275void __weak pcibios_remove_bus(struct pci_bus *bus)
2276{
2277}
2278
2279static struct pci_bus *pci_create_root_bus_msi(struct device *parent,
2280 int bus, struct pci_ops *ops, void *sysdata,
2281 struct list_head *resources, struct msi_controller *msi)
2282{
2283 int error;
2284 struct pci_host_bridge *bridge;
2285
2286 bridge = pci_alloc_host_bridge(0);
2287 if (!bridge)
2288 return NULL;
2289
2290 bridge->dev.parent = parent;
2291 bridge->dev.release = pci_release_host_bridge_dev;
2292
2293 list_splice_init(resources, &bridge->windows);
2294 bridge->sysdata = sysdata;
2295 bridge->busnr = bus;
2296 bridge->ops = ops;
2297 bridge->msi = msi;
2298
2299 error = pci_register_host_bridge(bridge);
2300 if (error < 0)
2301 goto err_out;
2302
2303 return bridge->bus;
2304
2305err_out:
2306 kfree(bridge);
2307 return NULL;
2308}
2309
2310struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2311 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2312{
2313 return pci_create_root_bus_msi(parent, bus, ops, sysdata, resources,
2314 NULL);
2315}
2316EXPORT_SYMBOL_GPL(pci_create_root_bus);
2317
2318int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2319{
2320 struct resource *res = &b->busn_res;
2321 struct resource *parent_res, *conflict;
2322
2323 res->start = bus;
2324 res->end = bus_max;
2325 res->flags = IORESOURCE_BUS;
2326
2327 if (!pci_is_root_bus(b))
2328 parent_res = &b->parent->busn_res;
2329 else {
2330 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2331 res->flags |= IORESOURCE_PCI_FIXED;
2332 }
2333
2334 conflict = request_resource_conflict(parent_res, res);
2335
2336 if (conflict)
2337 dev_printk(KERN_DEBUG, &b->dev,
2338 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2339 res, pci_is_root_bus(b) ? "domain " : "",
2340 parent_res, conflict->name, conflict);
2341
2342 return conflict == NULL;
2343}
2344
2345int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2346{
2347 struct resource *res = &b->busn_res;
2348 struct resource old_res = *res;
2349 resource_size_t size;
2350 int ret;
2351
2352 if (res->start > bus_max)
2353 return -EINVAL;
2354
2355 size = bus_max - res->start + 1;
2356 ret = adjust_resource(res, res->start, size);
2357 dev_printk(KERN_DEBUG, &b->dev,
2358 "busn_res: %pR end %s updated to %02x\n",
2359 &old_res, ret ? "can not be" : "is", bus_max);
2360
2361 if (!ret && !res->parent)
2362 pci_bus_insert_busn_res(b, res->start, res->end);
2363
2364 return ret;
2365}
2366
2367void pci_bus_release_busn_res(struct pci_bus *b)
2368{
2369 struct resource *res = &b->busn_res;
2370 int ret;
2371
2372 if (!res->flags || !res->parent)
2373 return;
2374
2375 ret = release_resource(res);
2376 dev_printk(KERN_DEBUG, &b->dev,
2377 "busn_res: %pR %s released\n",
2378 res, ret ? "can not be" : "is");
2379}
2380
2381struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2382 struct pci_ops *ops, void *sysdata,
2383 struct list_head *resources, struct msi_controller *msi)
2384{
2385 struct resource_entry *window;
2386 bool found = false;
2387 struct pci_bus *b;
2388 int max;
2389
2390 resource_list_for_each_entry(window, resources)
2391 if (window->res->flags & IORESOURCE_BUS) {
2392 found = true;
2393 break;
2394 }
2395
2396 b = pci_create_root_bus_msi(parent, bus, ops, sysdata, resources, msi);
2397 if (!b)
2398 return NULL;
2399
2400 if (!found) {
2401 dev_info(&b->dev,
2402 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2403 bus);
2404 pci_bus_insert_busn_res(b, bus, 255);
2405 }
2406
2407 max = pci_scan_child_bus(b);
2408
2409 if (!found)
2410 pci_bus_update_busn_res_end(b, max);
2411
2412 return b;
2413}
2414
2415struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2416 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2417{
2418 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2419 NULL);
2420}
2421EXPORT_SYMBOL(pci_scan_root_bus);
2422
2423struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2424 void *sysdata)
2425{
2426 LIST_HEAD(resources);
2427 struct pci_bus *b;
2428
2429 pci_add_resource(&resources, &ioport_resource);
2430 pci_add_resource(&resources, &iomem_resource);
2431 pci_add_resource(&resources, &busn_resource);
2432 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2433 if (b) {
2434 pci_scan_child_bus(b);
2435 } else {
2436 pci_free_resource_list(&resources);
2437 }
2438 return b;
2439}
2440EXPORT_SYMBOL(pci_scan_bus);
2441
2442/**
2443 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2444 * @bridge: PCI bridge for the bus to scan
2445 *
2446 * Scan a PCI bus and child buses for new devices, add them,
2447 * and enable them, resizing bridge mmio/io resource if necessary
2448 * and possible. The caller must ensure the child devices are already
2449 * removed for resizing to occur.
2450 *
2451 * Returns the max number of subordinate bus discovered.
2452 */
2453unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2454{
2455 unsigned int max;
2456 struct pci_bus *bus = bridge->subordinate;
2457
2458 max = pci_scan_child_bus(bus);
2459
2460 pci_assign_unassigned_bridge_resources(bridge);
2461
2462 pci_bus_add_devices(bus);
2463
2464 return max;
2465}
2466
2467/**
2468 * pci_rescan_bus - scan a PCI bus for devices.
2469 * @bus: PCI bus to scan
2470 *
2471 * Scan a PCI bus and child buses for new devices, adds them,
2472 * and enables them.
2473 *
2474 * Returns the max number of subordinate bus discovered.
2475 */
2476unsigned int pci_rescan_bus(struct pci_bus *bus)
2477{
2478 unsigned int max;
2479
2480 max = pci_scan_child_bus(bus);
2481 pci_assign_unassigned_bus_resources(bus);
2482 pci_bus_add_devices(bus);
2483
2484 return max;
2485}
2486EXPORT_SYMBOL_GPL(pci_rescan_bus);
2487
2488/*
2489 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2490 * routines should always be executed under this mutex.
2491 */
2492static DEFINE_MUTEX(pci_rescan_remove_lock);
2493
2494void pci_lock_rescan_remove(void)
2495{
2496 mutex_lock(&pci_rescan_remove_lock);
2497}
2498EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2499
2500void pci_unlock_rescan_remove(void)
2501{
2502 mutex_unlock(&pci_rescan_remove_lock);
2503}
2504EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2505
2506static int __init pci_sort_bf_cmp(const struct device *d_a,
2507 const struct device *d_b)
2508{
2509 const struct pci_dev *a = to_pci_dev(d_a);
2510 const struct pci_dev *b = to_pci_dev(d_b);
2511
2512 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2513 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2514
2515 if (a->bus->number < b->bus->number) return -1;
2516 else if (a->bus->number > b->bus->number) return 1;
2517
2518 if (a->devfn < b->devfn) return -1;
2519 else if (a->devfn > b->devfn) return 1;
2520
2521 return 0;
2522}
2523
2524void __init pci_sort_breadthfirst(void)
2525{
2526 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2527}