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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
4 * Ethernet adapters. Based on earlier sk98lin, e100 and
5 * FreeBSD if_sk drivers.
6 *
7 * This driver intentionally does not support all the features
8 * of the original driver such as link fail-over and link management because
9 * those should be done at higher levels.
10 *
11 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 */
13
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/in.h>
17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/netdevice.h>
21#include <linux/etherdevice.h>
22#include <linux/ethtool.h>
23#include <linux/pci.h>
24#include <linux/if_vlan.h>
25#include <linux/ip.h>
26#include <linux/delay.h>
27#include <linux/crc32.h>
28#include <linux/dma-mapping.h>
29#include <linux/debugfs.h>
30#include <linux/sched.h>
31#include <linux/seq_file.h>
32#include <linux/mii.h>
33#include <linux/slab.h>
34#include <linux/dmi.h>
35#include <linux/prefetch.h>
36#include <asm/irq.h>
37
38#include "skge.h"
39
40#define DRV_NAME "skge"
41#define DRV_VERSION "1.14"
42
43#define DEFAULT_TX_RING_SIZE 128
44#define DEFAULT_RX_RING_SIZE 512
45#define MAX_TX_RING_SIZE 1024
46#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
47#define MAX_RX_RING_SIZE 4096
48#define RX_COPY_THRESHOLD 128
49#define RX_BUF_SIZE 1536
50#define PHY_RETRIES 1000
51#define ETH_JUMBO_MTU 9000
52#define TX_WATCHDOG (5 * HZ)
53#define BLINK_MS 250
54#define LINK_HZ HZ
55
56#define SKGE_EEPROM_MAGIC 0x9933aabb
57
58
59MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
60MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
61MODULE_LICENSE("GPL");
62MODULE_VERSION(DRV_VERSION);
63
64static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
65 NETIF_MSG_LINK | NETIF_MSG_IFUP |
66 NETIF_MSG_IFDOWN);
67
68static int debug = -1; /* defaults above */
69module_param(debug, int, 0);
70MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
71
72static const struct pci_device_id skge_id_table[] = {
73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
75#ifdef CONFIG_SKGE_GENESIS
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
77#endif
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
87 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
93static void skge_phy_reset(struct skge_port *skge);
94static void skge_tx_clean(struct net_device *dev);
95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
100static void genesis_mac_init(struct skge_hw *hw, int port);
101static void genesis_link_up(struct skge_port *skge);
102static void skge_set_multicast(struct net_device *dev);
103static irqreturn_t skge_intr(int irq, void *dev_id);
104
105/* Avoid conditionals by using array */
106static const int txqaddr[] = { Q_XA1, Q_XA2 };
107static const int rxqaddr[] = { Q_R1, Q_R2 };
108static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
109static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
110static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
111static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
112
113static inline bool is_genesis(const struct skge_hw *hw)
114{
115#ifdef CONFIG_SKGE_GENESIS
116 return hw->chip_id == CHIP_ID_GENESIS;
117#else
118 return false;
119#endif
120}
121
122static int skge_get_regs_len(struct net_device *dev)
123{
124 return 0x4000;
125}
126
127/*
128 * Returns copy of whole control register region
129 * Note: skip RAM address register because accessing it will
130 * cause bus hangs!
131 */
132static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
133 void *p)
134{
135 const struct skge_port *skge = netdev_priv(dev);
136 const void __iomem *io = skge->hw->regs;
137
138 regs->version = 1;
139 memset(p, 0, regs->len);
140 memcpy_fromio(p, io, B3_RAM_ADDR);
141
142 if (regs->len > B3_RI_WTO_R1) {
143 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
144 regs->len - B3_RI_WTO_R1);
145 }
146}
147
148/* Wake on Lan only supported on Yukon chips with rev 1 or above */
149static u32 wol_supported(const struct skge_hw *hw)
150{
151 if (is_genesis(hw))
152 return 0;
153
154 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
155 return 0;
156
157 return WAKE_MAGIC | WAKE_PHY;
158}
159
160static void skge_wol_init(struct skge_port *skge)
161{
162 struct skge_hw *hw = skge->hw;
163 int port = skge->port;
164 u16 ctrl;
165
166 skge_write16(hw, B0_CTST, CS_RST_CLR);
167 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
168
169 /* Turn on Vaux */
170 skge_write8(hw, B0_POWER_CTRL,
171 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
172
173 /* WA code for COMA mode -- clear PHY reset */
174 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
175 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
176 u32 reg = skge_read32(hw, B2_GP_IO);
177 reg |= GP_DIR_9;
178 reg &= ~GP_IO_9;
179 skge_write32(hw, B2_GP_IO, reg);
180 }
181
182 skge_write32(hw, SK_REG(port, GPHY_CTRL),
183 GPC_DIS_SLEEP |
184 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
185 GPC_ANEG_1 | GPC_RST_SET);
186
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 GPC_DIS_SLEEP |
189 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
190 GPC_ANEG_1 | GPC_RST_CLR);
191
192 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
193
194 /* Force to 10/100 skge_reset will re-enable on resume */
195 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
196 (PHY_AN_100FULL | PHY_AN_100HALF |
197 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
198 /* no 1000 HD/FD */
199 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
200 gm_phy_write(hw, port, PHY_MARV_CTRL,
201 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
202 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
203
204
205 /* Set GMAC to no flow control and auto update for speed/duplex */
206 gma_write16(hw, port, GM_GP_CTRL,
207 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
208 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
209
210 /* Set WOL address */
211 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
212 skge->netdev->dev_addr, ETH_ALEN);
213
214 /* Turn on appropriate WOL control bits */
215 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
216 ctrl = 0;
217 if (skge->wol & WAKE_PHY)
218 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
219 else
220 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
221
222 if (skge->wol & WAKE_MAGIC)
223 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
224 else
225 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
226
227 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
228 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
229
230 /* block receiver */
231 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
232}
233
234static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
235{
236 struct skge_port *skge = netdev_priv(dev);
237
238 wol->supported = wol_supported(skge->hw);
239 wol->wolopts = skge->wol;
240}
241
242static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
243{
244 struct skge_port *skge = netdev_priv(dev);
245 struct skge_hw *hw = skge->hw;
246
247 if ((wol->wolopts & ~wol_supported(hw)) ||
248 !device_can_wakeup(&hw->pdev->dev))
249 return -EOPNOTSUPP;
250
251 skge->wol = wol->wolopts;
252
253 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
254
255 return 0;
256}
257
258/* Determine supported/advertised modes based on hardware.
259 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
260 */
261static u32 skge_supported_modes(const struct skge_hw *hw)
262{
263 u32 supported;
264
265 if (hw->copper) {
266 supported = (SUPPORTED_10baseT_Half |
267 SUPPORTED_10baseT_Full |
268 SUPPORTED_100baseT_Half |
269 SUPPORTED_100baseT_Full |
270 SUPPORTED_1000baseT_Half |
271 SUPPORTED_1000baseT_Full |
272 SUPPORTED_Autoneg |
273 SUPPORTED_TP);
274
275 if (is_genesis(hw))
276 supported &= ~(SUPPORTED_10baseT_Half |
277 SUPPORTED_10baseT_Full |
278 SUPPORTED_100baseT_Half |
279 SUPPORTED_100baseT_Full);
280
281 else if (hw->chip_id == CHIP_ID_YUKON)
282 supported &= ~SUPPORTED_1000baseT_Half;
283 } else
284 supported = (SUPPORTED_1000baseT_Full |
285 SUPPORTED_1000baseT_Half |
286 SUPPORTED_FIBRE |
287 SUPPORTED_Autoneg);
288
289 return supported;
290}
291
292static int skge_get_link_ksettings(struct net_device *dev,
293 struct ethtool_link_ksettings *cmd)
294{
295 struct skge_port *skge = netdev_priv(dev);
296 struct skge_hw *hw = skge->hw;
297 u32 supported, advertising;
298
299 supported = skge_supported_modes(hw);
300
301 if (hw->copper) {
302 cmd->base.port = PORT_TP;
303 cmd->base.phy_address = hw->phy_addr;
304 } else
305 cmd->base.port = PORT_FIBRE;
306
307 advertising = skge->advertising;
308 cmd->base.autoneg = skge->autoneg;
309 cmd->base.speed = skge->speed;
310 cmd->base.duplex = skge->duplex;
311
312 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
313 supported);
314 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
315 advertising);
316
317 return 0;
318}
319
320static int skge_set_link_ksettings(struct net_device *dev,
321 const struct ethtool_link_ksettings *cmd)
322{
323 struct skge_port *skge = netdev_priv(dev);
324 const struct skge_hw *hw = skge->hw;
325 u32 supported = skge_supported_modes(hw);
326 int err = 0;
327 u32 advertising;
328
329 ethtool_convert_link_mode_to_legacy_u32(&advertising,
330 cmd->link_modes.advertising);
331
332 if (cmd->base.autoneg == AUTONEG_ENABLE) {
333 advertising = supported;
334 skge->duplex = -1;
335 skge->speed = -1;
336 } else {
337 u32 setting;
338 u32 speed = cmd->base.speed;
339
340 switch (speed) {
341 case SPEED_1000:
342 if (cmd->base.duplex == DUPLEX_FULL)
343 setting = SUPPORTED_1000baseT_Full;
344 else if (cmd->base.duplex == DUPLEX_HALF)
345 setting = SUPPORTED_1000baseT_Half;
346 else
347 return -EINVAL;
348 break;
349 case SPEED_100:
350 if (cmd->base.duplex == DUPLEX_FULL)
351 setting = SUPPORTED_100baseT_Full;
352 else if (cmd->base.duplex == DUPLEX_HALF)
353 setting = SUPPORTED_100baseT_Half;
354 else
355 return -EINVAL;
356 break;
357
358 case SPEED_10:
359 if (cmd->base.duplex == DUPLEX_FULL)
360 setting = SUPPORTED_10baseT_Full;
361 else if (cmd->base.duplex == DUPLEX_HALF)
362 setting = SUPPORTED_10baseT_Half;
363 else
364 return -EINVAL;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 if ((setting & supported) == 0)
371 return -EINVAL;
372
373 skge->speed = speed;
374 skge->duplex = cmd->base.duplex;
375 }
376
377 skge->autoneg = cmd->base.autoneg;
378 skge->advertising = advertising;
379
380 if (netif_running(dev)) {
381 skge_down(dev);
382 err = skge_up(dev);
383 if (err) {
384 dev_close(dev);
385 return err;
386 }
387 }
388
389 return 0;
390}
391
392static void skge_get_drvinfo(struct net_device *dev,
393 struct ethtool_drvinfo *info)
394{
395 struct skge_port *skge = netdev_priv(dev);
396
397 strscpy(info->driver, DRV_NAME, sizeof(info->driver));
398 strscpy(info->version, DRV_VERSION, sizeof(info->version));
399 strscpy(info->bus_info, pci_name(skge->hw->pdev),
400 sizeof(info->bus_info));
401}
402
403static const struct skge_stat {
404 char name[ETH_GSTRING_LEN];
405 u16 xmac_offset;
406 u16 gma_offset;
407} skge_stats[] = {
408 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
409 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
410
411 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
412 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
413 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
414 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
415 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
416 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
417 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
418 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
419
420 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
421 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
422 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
423 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
424 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
425 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
426
427 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
428 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
429 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
430 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
431 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
432};
433
434static int skge_get_sset_count(struct net_device *dev, int sset)
435{
436 switch (sset) {
437 case ETH_SS_STATS:
438 return ARRAY_SIZE(skge_stats);
439 default:
440 return -EOPNOTSUPP;
441 }
442}
443
444static void skge_get_ethtool_stats(struct net_device *dev,
445 struct ethtool_stats *stats, u64 *data)
446{
447 struct skge_port *skge = netdev_priv(dev);
448
449 if (is_genesis(skge->hw))
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453}
454
455/* Use hardware MIB variables for critical path statistics and
456 * transmit feedback not reported at interrupt.
457 * Other errors are accounted for in interrupt handler.
458 */
459static struct net_device_stats *skge_get_stats(struct net_device *dev)
460{
461 struct skge_port *skge = netdev_priv(dev);
462 u64 data[ARRAY_SIZE(skge_stats)];
463
464 if (is_genesis(skge->hw))
465 genesis_get_stats(skge, data);
466 else
467 yukon_get_stats(skge, data);
468
469 dev->stats.tx_bytes = data[0];
470 dev->stats.rx_bytes = data[1];
471 dev->stats.tx_packets = data[2] + data[4] + data[6];
472 dev->stats.rx_packets = data[3] + data[5] + data[7];
473 dev->stats.multicast = data[3] + data[5];
474 dev->stats.collisions = data[10];
475 dev->stats.tx_aborted_errors = data[12];
476
477 return &dev->stats;
478}
479
480static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
481{
482 int i;
483
484 switch (stringset) {
485 case ETH_SS_STATS:
486 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
487 ethtool_puts(&data, skge_stats[i].name);
488 break;
489 }
490}
491
492static void skge_get_ring_param(struct net_device *dev,
493 struct ethtool_ringparam *p,
494 struct kernel_ethtool_ringparam *kernel_p,
495 struct netlink_ext_ack *extack)
496{
497 struct skge_port *skge = netdev_priv(dev);
498
499 p->rx_max_pending = MAX_RX_RING_SIZE;
500 p->tx_max_pending = MAX_TX_RING_SIZE;
501
502 p->rx_pending = skge->rx_ring.count;
503 p->tx_pending = skge->tx_ring.count;
504}
505
506static int skge_set_ring_param(struct net_device *dev,
507 struct ethtool_ringparam *p,
508 struct kernel_ethtool_ringparam *kernel_p,
509 struct netlink_ext_ack *extack)
510{
511 struct skge_port *skge = netdev_priv(dev);
512 int err = 0;
513
514 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
515 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
516 return -EINVAL;
517
518 skge->rx_ring.count = p->rx_pending;
519 skge->tx_ring.count = p->tx_pending;
520
521 if (netif_running(dev)) {
522 skge_down(dev);
523 err = skge_up(dev);
524 if (err)
525 dev_close(dev);
526 }
527
528 return err;
529}
530
531static u32 skge_get_msglevel(struct net_device *netdev)
532{
533 struct skge_port *skge = netdev_priv(netdev);
534 return skge->msg_enable;
535}
536
537static void skge_set_msglevel(struct net_device *netdev, u32 value)
538{
539 struct skge_port *skge = netdev_priv(netdev);
540 skge->msg_enable = value;
541}
542
543static int skge_nway_reset(struct net_device *dev)
544{
545 struct skge_port *skge = netdev_priv(dev);
546
547 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
548 return -EINVAL;
549
550 skge_phy_reset(skge);
551 return 0;
552}
553
554static void skge_get_pauseparam(struct net_device *dev,
555 struct ethtool_pauseparam *ecmd)
556{
557 struct skge_port *skge = netdev_priv(dev);
558
559 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
560 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
561 ecmd->tx_pause = (ecmd->rx_pause ||
562 (skge->flow_control == FLOW_MODE_LOC_SEND));
563
564 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
565}
566
567static int skge_set_pauseparam(struct net_device *dev,
568 struct ethtool_pauseparam *ecmd)
569{
570 struct skge_port *skge = netdev_priv(dev);
571 struct ethtool_pauseparam old;
572 int err = 0;
573
574 skge_get_pauseparam(dev, &old);
575
576 if (ecmd->autoneg != old.autoneg)
577 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
578 else {
579 if (ecmd->rx_pause && ecmd->tx_pause)
580 skge->flow_control = FLOW_MODE_SYMMETRIC;
581 else if (ecmd->rx_pause && !ecmd->tx_pause)
582 skge->flow_control = FLOW_MODE_SYM_OR_REM;
583 else if (!ecmd->rx_pause && ecmd->tx_pause)
584 skge->flow_control = FLOW_MODE_LOC_SEND;
585 else
586 skge->flow_control = FLOW_MODE_NONE;
587 }
588
589 if (netif_running(dev)) {
590 skge_down(dev);
591 err = skge_up(dev);
592 if (err) {
593 dev_close(dev);
594 return err;
595 }
596 }
597
598 return 0;
599}
600
601/* Chip internal frequency for clock calculations */
602static inline u32 hwkhz(const struct skge_hw *hw)
603{
604 return is_genesis(hw) ? 53125 : 78125;
605}
606
607/* Chip HZ to microseconds */
608static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
609{
610 return (ticks * 1000) / hwkhz(hw);
611}
612
613/* Microseconds to chip HZ */
614static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
615{
616 return hwkhz(hw) * usec / 1000;
617}
618
619static int skge_get_coalesce(struct net_device *dev,
620 struct ethtool_coalesce *ecmd,
621 struct kernel_ethtool_coalesce *kernel_coal,
622 struct netlink_ext_ack *extack)
623{
624 struct skge_port *skge = netdev_priv(dev);
625 struct skge_hw *hw = skge->hw;
626 int port = skge->port;
627
628 ecmd->rx_coalesce_usecs = 0;
629 ecmd->tx_coalesce_usecs = 0;
630
631 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
632 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
633 u32 msk = skge_read32(hw, B2_IRQM_MSK);
634
635 if (msk & rxirqmask[port])
636 ecmd->rx_coalesce_usecs = delay;
637 if (msk & txirqmask[port])
638 ecmd->tx_coalesce_usecs = delay;
639 }
640
641 return 0;
642}
643
644/* Note: interrupt timer is per board, but can turn on/off per port */
645static int skge_set_coalesce(struct net_device *dev,
646 struct ethtool_coalesce *ecmd,
647 struct kernel_ethtool_coalesce *kernel_coal,
648 struct netlink_ext_ack *extack)
649{
650 struct skge_port *skge = netdev_priv(dev);
651 struct skge_hw *hw = skge->hw;
652 int port = skge->port;
653 u32 msk = skge_read32(hw, B2_IRQM_MSK);
654 u32 delay = 25;
655
656 if (ecmd->rx_coalesce_usecs == 0)
657 msk &= ~rxirqmask[port];
658 else if (ecmd->rx_coalesce_usecs < 25 ||
659 ecmd->rx_coalesce_usecs > 33333)
660 return -EINVAL;
661 else {
662 msk |= rxirqmask[port];
663 delay = ecmd->rx_coalesce_usecs;
664 }
665
666 if (ecmd->tx_coalesce_usecs == 0)
667 msk &= ~txirqmask[port];
668 else if (ecmd->tx_coalesce_usecs < 25 ||
669 ecmd->tx_coalesce_usecs > 33333)
670 return -EINVAL;
671 else {
672 msk |= txirqmask[port];
673 delay = min(delay, ecmd->rx_coalesce_usecs);
674 }
675
676 skge_write32(hw, B2_IRQM_MSK, msk);
677 if (msk == 0)
678 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
679 else {
680 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
681 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
682 }
683 return 0;
684}
685
686enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
687static void skge_led(struct skge_port *skge, enum led_mode mode)
688{
689 struct skge_hw *hw = skge->hw;
690 int port = skge->port;
691
692 spin_lock_bh(&hw->phy_lock);
693 if (is_genesis(hw)) {
694 switch (mode) {
695 case LED_MODE_OFF:
696 if (hw->phy_type == SK_PHY_BCOM)
697 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
698 else {
699 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
700 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
701 }
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
703 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
705 break;
706
707 case LED_MODE_ON:
708 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
709 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
710
711 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
712 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
713
714 break;
715
716 case LED_MODE_TST:
717 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
718 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
719 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
720
721 if (hw->phy_type == SK_PHY_BCOM)
722 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
723 else {
724 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
725 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
726 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
727 }
728
729 }
730 } else {
731 switch (mode) {
732 case LED_MODE_OFF:
733 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
734 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
735 PHY_M_LED_MO_DUP(MO_LED_OFF) |
736 PHY_M_LED_MO_10(MO_LED_OFF) |
737 PHY_M_LED_MO_100(MO_LED_OFF) |
738 PHY_M_LED_MO_1000(MO_LED_OFF) |
739 PHY_M_LED_MO_RX(MO_LED_OFF));
740 break;
741 case LED_MODE_ON:
742 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
743 PHY_M_LED_PULS_DUR(PULS_170MS) |
744 PHY_M_LED_BLINK_RT(BLINK_84MS) |
745 PHY_M_LEDC_TX_CTRL |
746 PHY_M_LEDC_DP_CTRL);
747
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
749 PHY_M_LED_MO_RX(MO_LED_OFF) |
750 (skge->speed == SPEED_100 ?
751 PHY_M_LED_MO_100(MO_LED_ON) : 0));
752 break;
753 case LED_MODE_TST:
754 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
755 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
756 PHY_M_LED_MO_DUP(MO_LED_ON) |
757 PHY_M_LED_MO_10(MO_LED_ON) |
758 PHY_M_LED_MO_100(MO_LED_ON) |
759 PHY_M_LED_MO_1000(MO_LED_ON) |
760 PHY_M_LED_MO_RX(MO_LED_ON));
761 }
762 }
763 spin_unlock_bh(&hw->phy_lock);
764}
765
766/* blink LED's for finding board */
767static int skge_set_phys_id(struct net_device *dev,
768 enum ethtool_phys_id_state state)
769{
770 struct skge_port *skge = netdev_priv(dev);
771
772 switch (state) {
773 case ETHTOOL_ID_ACTIVE:
774 return 2; /* cycle on/off twice per second */
775
776 case ETHTOOL_ID_ON:
777 skge_led(skge, LED_MODE_TST);
778 break;
779
780 case ETHTOOL_ID_OFF:
781 skge_led(skge, LED_MODE_OFF);
782 break;
783
784 case ETHTOOL_ID_INACTIVE:
785 /* back to regular LED state */
786 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
787 }
788
789 return 0;
790}
791
792static int skge_get_eeprom_len(struct net_device *dev)
793{
794 struct skge_port *skge = netdev_priv(dev);
795 u32 reg2;
796
797 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
798 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
799}
800
801static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
802{
803 u32 val;
804
805 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
806
807 do {
808 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
809 } while (!(offset & PCI_VPD_ADDR_F));
810
811 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
812 return val;
813}
814
815static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
816{
817 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
818 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
819 offset | PCI_VPD_ADDR_F);
820
821 do {
822 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
823 } while (offset & PCI_VPD_ADDR_F);
824}
825
826static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
827 u8 *data)
828{
829 struct skge_port *skge = netdev_priv(dev);
830 struct pci_dev *pdev = skge->hw->pdev;
831 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
832 int length = eeprom->len;
833 u16 offset = eeprom->offset;
834
835 if (!cap)
836 return -EINVAL;
837
838 eeprom->magic = SKGE_EEPROM_MAGIC;
839
840 while (length > 0) {
841 u32 val = skge_vpd_read(pdev, cap, offset);
842 int n = min_t(int, length, sizeof(val));
843
844 memcpy(data, &val, n);
845 length -= n;
846 data += n;
847 offset += n;
848 }
849 return 0;
850}
851
852static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
853 u8 *data)
854{
855 struct skge_port *skge = netdev_priv(dev);
856 struct pci_dev *pdev = skge->hw->pdev;
857 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
858 int length = eeprom->len;
859 u16 offset = eeprom->offset;
860
861 if (!cap)
862 return -EINVAL;
863
864 if (eeprom->magic != SKGE_EEPROM_MAGIC)
865 return -EINVAL;
866
867 while (length > 0) {
868 u32 val;
869 int n = min_t(int, length, sizeof(val));
870
871 if (n < sizeof(val))
872 val = skge_vpd_read(pdev, cap, offset);
873 memcpy(&val, data, n);
874
875 skge_vpd_write(pdev, cap, offset, val);
876
877 length -= n;
878 data += n;
879 offset += n;
880 }
881 return 0;
882}
883
884static const struct ethtool_ops skge_ethtool_ops = {
885 .supported_coalesce_params = ETHTOOL_COALESCE_USECS,
886 .get_drvinfo = skge_get_drvinfo,
887 .get_regs_len = skge_get_regs_len,
888 .get_regs = skge_get_regs,
889 .get_wol = skge_get_wol,
890 .set_wol = skge_set_wol,
891 .get_msglevel = skge_get_msglevel,
892 .set_msglevel = skge_set_msglevel,
893 .nway_reset = skge_nway_reset,
894 .get_link = ethtool_op_get_link,
895 .get_eeprom_len = skge_get_eeprom_len,
896 .get_eeprom = skge_get_eeprom,
897 .set_eeprom = skge_set_eeprom,
898 .get_ringparam = skge_get_ring_param,
899 .set_ringparam = skge_set_ring_param,
900 .get_pauseparam = skge_get_pauseparam,
901 .set_pauseparam = skge_set_pauseparam,
902 .get_coalesce = skge_get_coalesce,
903 .set_coalesce = skge_set_coalesce,
904 .get_strings = skge_get_strings,
905 .set_phys_id = skge_set_phys_id,
906 .get_sset_count = skge_get_sset_count,
907 .get_ethtool_stats = skge_get_ethtool_stats,
908 .get_link_ksettings = skge_get_link_ksettings,
909 .set_link_ksettings = skge_set_link_ksettings,
910};
911
912/*
913 * Allocate ring elements and chain them together
914 * One-to-one association of board descriptors with ring elements
915 */
916static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
917{
918 struct skge_tx_desc *d;
919 struct skge_element *e;
920 int i;
921
922 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
923 if (!ring->start)
924 return -ENOMEM;
925
926 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
927 e->desc = d;
928 if (i == ring->count - 1) {
929 e->next = ring->start;
930 d->next_offset = base;
931 } else {
932 e->next = e + 1;
933 d->next_offset = base + (i+1) * sizeof(*d);
934 }
935 }
936 ring->to_use = ring->to_clean = ring->start;
937
938 return 0;
939}
940
941/* Allocate and setup a new buffer for receiving */
942static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
943 struct sk_buff *skb, unsigned int bufsize)
944{
945 struct skge_rx_desc *rd = e->desc;
946 dma_addr_t map;
947
948 map = dma_map_single(&skge->hw->pdev->dev, skb->data, bufsize,
949 DMA_FROM_DEVICE);
950
951 if (dma_mapping_error(&skge->hw->pdev->dev, map))
952 return -1;
953
954 rd->dma_lo = lower_32_bits(map);
955 rd->dma_hi = upper_32_bits(map);
956 e->skb = skb;
957 rd->csum1_start = ETH_HLEN;
958 rd->csum2_start = ETH_HLEN;
959 rd->csum1 = 0;
960 rd->csum2 = 0;
961
962 wmb();
963
964 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
965 dma_unmap_addr_set(e, mapaddr, map);
966 dma_unmap_len_set(e, maplen, bufsize);
967 return 0;
968}
969
970/* Resume receiving using existing skb,
971 * Note: DMA address is not changed by chip.
972 * MTU not changed while receiver active.
973 */
974static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
975{
976 struct skge_rx_desc *rd = e->desc;
977
978 rd->csum2 = 0;
979 rd->csum2_start = ETH_HLEN;
980
981 wmb();
982
983 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
984}
985
986
987/* Free all buffers in receive ring, assumes receiver stopped */
988static void skge_rx_clean(struct skge_port *skge)
989{
990 struct skge_hw *hw = skge->hw;
991 struct skge_ring *ring = &skge->rx_ring;
992 struct skge_element *e;
993
994 e = ring->start;
995 do {
996 struct skge_rx_desc *rd = e->desc;
997 rd->control = 0;
998 if (e->skb) {
999 dma_unmap_single(&hw->pdev->dev,
1000 dma_unmap_addr(e, mapaddr),
1001 dma_unmap_len(e, maplen),
1002 DMA_FROM_DEVICE);
1003 dev_kfree_skb(e->skb);
1004 e->skb = NULL;
1005 }
1006 } while ((e = e->next) != ring->start);
1007}
1008
1009
1010/* Allocate buffers for receive ring
1011 * For receive: to_clean is next received frame.
1012 */
1013static int skge_rx_fill(struct net_device *dev)
1014{
1015 struct skge_port *skge = netdev_priv(dev);
1016 struct skge_ring *ring = &skge->rx_ring;
1017 struct skge_element *e;
1018
1019 e = ring->start;
1020 do {
1021 struct sk_buff *skb;
1022
1023 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1024 GFP_KERNEL);
1025 if (!skb)
1026 return -ENOMEM;
1027
1028 skb_reserve(skb, NET_IP_ALIGN);
1029 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1030 dev_kfree_skb(skb);
1031 return -EIO;
1032 }
1033 } while ((e = e->next) != ring->start);
1034
1035 ring->to_clean = ring->start;
1036 return 0;
1037}
1038
1039static const char *skge_pause(enum pause_status status)
1040{
1041 switch (status) {
1042 case FLOW_STAT_NONE:
1043 return "none";
1044 case FLOW_STAT_REM_SEND:
1045 return "rx only";
1046 case FLOW_STAT_LOC_SEND:
1047 return "tx_only";
1048 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1049 return "both";
1050 default:
1051 return "indeterminated";
1052 }
1053}
1054
1055
1056static void skge_link_up(struct skge_port *skge)
1057{
1058 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1059 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1060
1061 netif_carrier_on(skge->netdev);
1062 netif_wake_queue(skge->netdev);
1063
1064 netif_info(skge, link, skge->netdev,
1065 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1066 skge->speed,
1067 skge->duplex == DUPLEX_FULL ? "full" : "half",
1068 skge_pause(skge->flow_status));
1069}
1070
1071static void skge_link_down(struct skge_port *skge)
1072{
1073 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1074 netif_carrier_off(skge->netdev);
1075 netif_stop_queue(skge->netdev);
1076
1077 netif_info(skge, link, skge->netdev, "Link is down\n");
1078}
1079
1080static void xm_link_down(struct skge_hw *hw, int port)
1081{
1082 struct net_device *dev = hw->dev[port];
1083 struct skge_port *skge = netdev_priv(dev);
1084
1085 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1086
1087 if (netif_carrier_ok(dev))
1088 skge_link_down(skge);
1089}
1090
1091static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1092{
1093 int i;
1094
1095 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1096 *val = xm_read16(hw, port, XM_PHY_DATA);
1097
1098 if (hw->phy_type == SK_PHY_XMAC)
1099 goto ready;
1100
1101 for (i = 0; i < PHY_RETRIES; i++) {
1102 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1103 goto ready;
1104 udelay(1);
1105 }
1106
1107 return -ETIMEDOUT;
1108 ready:
1109 *val = xm_read16(hw, port, XM_PHY_DATA);
1110
1111 return 0;
1112}
1113
1114static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1115{
1116 u16 v = 0;
1117 if (__xm_phy_read(hw, port, reg, &v))
1118 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1119 return v;
1120}
1121
1122static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1123{
1124 int i;
1125
1126 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1127 for (i = 0; i < PHY_RETRIES; i++) {
1128 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1129 goto ready;
1130 udelay(1);
1131 }
1132 return -EIO;
1133
1134 ready:
1135 xm_write16(hw, port, XM_PHY_DATA, val);
1136 for (i = 0; i < PHY_RETRIES; i++) {
1137 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1138 return 0;
1139 udelay(1);
1140 }
1141 return -ETIMEDOUT;
1142}
1143
1144static void genesis_init(struct skge_hw *hw)
1145{
1146 /* set blink source counter */
1147 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1148 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1149
1150 /* configure mac arbiter */
1151 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1152
1153 /* configure mac arbiter timeout values */
1154 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1155 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1156 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1157 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1158
1159 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1160 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1161 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1162 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1163
1164 /* configure packet arbiter timeout */
1165 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1166 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1167 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1168 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1169 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1170}
1171
1172static void genesis_reset(struct skge_hw *hw, int port)
1173{
1174 static const u8 zero[8] = { 0 };
1175 u32 reg;
1176
1177 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1178
1179 /* reset the statistics module */
1180 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1181 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1182 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1183 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1184 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1185
1186 /* disable Broadcom PHY IRQ */
1187 if (hw->phy_type == SK_PHY_BCOM)
1188 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1189
1190 xm_outhash(hw, port, XM_HSM, zero);
1191
1192 /* Flush TX and RX fifo */
1193 reg = xm_read32(hw, port, XM_MODE);
1194 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1195 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1196}
1197
1198/* Convert mode to MII values */
1199static const u16 phy_pause_map[] = {
1200 [FLOW_MODE_NONE] = 0,
1201 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1202 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1203 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1204};
1205
1206/* special defines for FIBER (88E1011S only) */
1207static const u16 fiber_pause_map[] = {
1208 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1209 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1210 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1211 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1212};
1213
1214
1215/* Check status of Broadcom phy link */
1216static void bcom_check_link(struct skge_hw *hw, int port)
1217{
1218 struct net_device *dev = hw->dev[port];
1219 struct skge_port *skge = netdev_priv(dev);
1220 u16 status;
1221
1222 /* read twice because of latch */
1223 xm_phy_read(hw, port, PHY_BCOM_STAT);
1224 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1225
1226 if ((status & PHY_ST_LSYNC) == 0) {
1227 xm_link_down(hw, port);
1228 return;
1229 }
1230
1231 if (skge->autoneg == AUTONEG_ENABLE) {
1232 u16 lpa, aux;
1233
1234 if (!(status & PHY_ST_AN_OVER))
1235 return;
1236
1237 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1238 if (lpa & PHY_B_AN_RF) {
1239 netdev_notice(dev, "remote fault\n");
1240 return;
1241 }
1242
1243 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1244
1245 /* Check Duplex mismatch */
1246 switch (aux & PHY_B_AS_AN_RES_MSK) {
1247 case PHY_B_RES_1000FD:
1248 skge->duplex = DUPLEX_FULL;
1249 break;
1250 case PHY_B_RES_1000HD:
1251 skge->duplex = DUPLEX_HALF;
1252 break;
1253 default:
1254 netdev_notice(dev, "duplex mismatch\n");
1255 return;
1256 }
1257
1258 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1259 switch (aux & PHY_B_AS_PAUSE_MSK) {
1260 case PHY_B_AS_PAUSE_MSK:
1261 skge->flow_status = FLOW_STAT_SYMMETRIC;
1262 break;
1263 case PHY_B_AS_PRR:
1264 skge->flow_status = FLOW_STAT_REM_SEND;
1265 break;
1266 case PHY_B_AS_PRT:
1267 skge->flow_status = FLOW_STAT_LOC_SEND;
1268 break;
1269 default:
1270 skge->flow_status = FLOW_STAT_NONE;
1271 }
1272 skge->speed = SPEED_1000;
1273 }
1274
1275 if (!netif_carrier_ok(dev))
1276 genesis_link_up(skge);
1277}
1278
1279/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1280 * Phy on for 100 or 10Mbit operation
1281 */
1282static void bcom_phy_init(struct skge_port *skge)
1283{
1284 struct skge_hw *hw = skge->hw;
1285 int port = skge->port;
1286 int i;
1287 u16 id1, r, ext, ctl;
1288
1289 /* magic workaround patterns for Broadcom */
1290 static const struct {
1291 u16 reg;
1292 u16 val;
1293 } A1hack[] = {
1294 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1295 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1296 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1297 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1298 }, C0hack[] = {
1299 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1300 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1301 };
1302
1303 /* read Id from external PHY (all have the same address) */
1304 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1305
1306 /* Optimize MDIO transfer by suppressing preamble. */
1307 r = xm_read16(hw, port, XM_MMU_CMD);
1308 r |= XM_MMU_NO_PRE;
1309 xm_write16(hw, port, XM_MMU_CMD, r);
1310
1311 switch (id1) {
1312 case PHY_BCOM_ID1_C0:
1313 /*
1314 * Workaround BCOM Errata for the C0 type.
1315 * Write magic patterns to reserved registers.
1316 */
1317 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1318 xm_phy_write(hw, port,
1319 C0hack[i].reg, C0hack[i].val);
1320
1321 break;
1322 case PHY_BCOM_ID1_A1:
1323 /*
1324 * Workaround BCOM Errata for the A1 type.
1325 * Write magic patterns to reserved registers.
1326 */
1327 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1328 xm_phy_write(hw, port,
1329 A1hack[i].reg, A1hack[i].val);
1330 break;
1331 }
1332
1333 /*
1334 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1335 * Disable Power Management after reset.
1336 */
1337 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1338 r |= PHY_B_AC_DIS_PM;
1339 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1340
1341 /* Dummy read */
1342 xm_read16(hw, port, XM_ISRC);
1343
1344 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1345 ctl = PHY_CT_SP1000; /* always 1000mbit */
1346
1347 if (skge->autoneg == AUTONEG_ENABLE) {
1348 /*
1349 * Workaround BCOM Errata #1 for the C5 type.
1350 * 1000Base-T Link Acquisition Failure in Slave Mode
1351 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1352 */
1353 u16 adv = PHY_B_1000C_RD;
1354 if (skge->advertising & ADVERTISED_1000baseT_Half)
1355 adv |= PHY_B_1000C_AHD;
1356 if (skge->advertising & ADVERTISED_1000baseT_Full)
1357 adv |= PHY_B_1000C_AFD;
1358 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1359
1360 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1361 } else {
1362 if (skge->duplex == DUPLEX_FULL)
1363 ctl |= PHY_CT_DUP_MD;
1364 /* Force to slave */
1365 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1366 }
1367
1368 /* Set autonegotiation pause parameters */
1369 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1370 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1371
1372 /* Handle Jumbo frames */
1373 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1374 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1375 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1376
1377 ext |= PHY_B_PEC_HIGH_LA;
1378
1379 }
1380
1381 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1382 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1383
1384 /* Use link status change interrupt */
1385 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1386}
1387
1388static void xm_phy_init(struct skge_port *skge)
1389{
1390 struct skge_hw *hw = skge->hw;
1391 int port = skge->port;
1392 u16 ctrl = 0;
1393
1394 if (skge->autoneg == AUTONEG_ENABLE) {
1395 if (skge->advertising & ADVERTISED_1000baseT_Half)
1396 ctrl |= PHY_X_AN_HD;
1397 if (skge->advertising & ADVERTISED_1000baseT_Full)
1398 ctrl |= PHY_X_AN_FD;
1399
1400 ctrl |= fiber_pause_map[skge->flow_control];
1401
1402 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1403
1404 /* Restart Auto-negotiation */
1405 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1406 } else {
1407 /* Set DuplexMode in Config register */
1408 if (skge->duplex == DUPLEX_FULL)
1409 ctrl |= PHY_CT_DUP_MD;
1410 /*
1411 * Do NOT enable Auto-negotiation here. This would hold
1412 * the link down because no IDLEs are transmitted
1413 */
1414 }
1415
1416 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1417
1418 /* Poll PHY for status changes */
1419 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1420}
1421
1422static int xm_check_link(struct net_device *dev)
1423{
1424 struct skge_port *skge = netdev_priv(dev);
1425 struct skge_hw *hw = skge->hw;
1426 int port = skge->port;
1427 u16 status;
1428
1429 /* read twice because of latch */
1430 xm_phy_read(hw, port, PHY_XMAC_STAT);
1431 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1432
1433 if ((status & PHY_ST_LSYNC) == 0) {
1434 xm_link_down(hw, port);
1435 return 0;
1436 }
1437
1438 if (skge->autoneg == AUTONEG_ENABLE) {
1439 u16 lpa, res;
1440
1441 if (!(status & PHY_ST_AN_OVER))
1442 return 0;
1443
1444 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1445 if (lpa & PHY_B_AN_RF) {
1446 netdev_notice(dev, "remote fault\n");
1447 return 0;
1448 }
1449
1450 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1451
1452 /* Check Duplex mismatch */
1453 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1454 case PHY_X_RS_FD:
1455 skge->duplex = DUPLEX_FULL;
1456 break;
1457 case PHY_X_RS_HD:
1458 skge->duplex = DUPLEX_HALF;
1459 break;
1460 default:
1461 netdev_notice(dev, "duplex mismatch\n");
1462 return 0;
1463 }
1464
1465 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1466 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1467 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1468 (lpa & PHY_X_P_SYM_MD))
1469 skge->flow_status = FLOW_STAT_SYMMETRIC;
1470 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1471 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1472 /* Enable PAUSE receive, disable PAUSE transmit */
1473 skge->flow_status = FLOW_STAT_REM_SEND;
1474 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1475 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1476 /* Disable PAUSE receive, enable PAUSE transmit */
1477 skge->flow_status = FLOW_STAT_LOC_SEND;
1478 else
1479 skge->flow_status = FLOW_STAT_NONE;
1480
1481 skge->speed = SPEED_1000;
1482 }
1483
1484 if (!netif_carrier_ok(dev))
1485 genesis_link_up(skge);
1486 return 1;
1487}
1488
1489/* Poll to check for link coming up.
1490 *
1491 * Since internal PHY is wired to a level triggered pin, can't
1492 * get an interrupt when carrier is detected, need to poll for
1493 * link coming up.
1494 */
1495static void xm_link_timer(struct timer_list *t)
1496{
1497 struct skge_port *skge = from_timer(skge, t, link_timer);
1498 struct net_device *dev = skge->netdev;
1499 struct skge_hw *hw = skge->hw;
1500 int port = skge->port;
1501 int i;
1502 unsigned long flags;
1503
1504 if (!netif_running(dev))
1505 return;
1506
1507 spin_lock_irqsave(&hw->phy_lock, flags);
1508
1509 /*
1510 * Verify that the link by checking GPIO register three times.
1511 * This pin has the signal from the link_sync pin connected to it.
1512 */
1513 for (i = 0; i < 3; i++) {
1514 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1515 goto link_down;
1516 }
1517
1518 /* Re-enable interrupt to detect link down */
1519 if (xm_check_link(dev)) {
1520 u16 msk = xm_read16(hw, port, XM_IMSK);
1521 msk &= ~XM_IS_INP_ASS;
1522 xm_write16(hw, port, XM_IMSK, msk);
1523 xm_read16(hw, port, XM_ISRC);
1524 } else {
1525link_down:
1526 mod_timer(&skge->link_timer,
1527 round_jiffies(jiffies + LINK_HZ));
1528 }
1529 spin_unlock_irqrestore(&hw->phy_lock, flags);
1530}
1531
1532static void genesis_mac_init(struct skge_hw *hw, int port)
1533{
1534 struct net_device *dev = hw->dev[port];
1535 struct skge_port *skge = netdev_priv(dev);
1536 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1537 int i;
1538 u32 r;
1539 static const u8 zero[6] = { 0 };
1540
1541 for (i = 0; i < 10; i++) {
1542 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1543 MFF_SET_MAC_RST);
1544 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1545 goto reset_ok;
1546 udelay(1);
1547 }
1548
1549 netdev_warn(dev, "genesis reset failed\n");
1550
1551 reset_ok:
1552 /* Unreset the XMAC. */
1553 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1554
1555 /*
1556 * Perform additional initialization for external PHYs,
1557 * namely for the 1000baseTX cards that use the XMAC's
1558 * GMII mode.
1559 */
1560 if (hw->phy_type != SK_PHY_XMAC) {
1561 /* Take external Phy out of reset */
1562 r = skge_read32(hw, B2_GP_IO);
1563 if (port == 0)
1564 r |= GP_DIR_0|GP_IO_0;
1565 else
1566 r |= GP_DIR_2|GP_IO_2;
1567
1568 skge_write32(hw, B2_GP_IO, r);
1569
1570 /* Enable GMII interface */
1571 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1572 }
1573
1574
1575 switch (hw->phy_type) {
1576 case SK_PHY_XMAC:
1577 xm_phy_init(skge);
1578 break;
1579 case SK_PHY_BCOM:
1580 bcom_phy_init(skge);
1581 bcom_check_link(hw, port);
1582 }
1583
1584 /* Set Station Address */
1585 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1586
1587 /* We don't use match addresses so clear */
1588 for (i = 1; i < 16; i++)
1589 xm_outaddr(hw, port, XM_EXM(i), zero);
1590
1591 /* Clear MIB counters */
1592 xm_write16(hw, port, XM_STAT_CMD,
1593 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1594 /* Clear two times according to Errata #3 */
1595 xm_write16(hw, port, XM_STAT_CMD,
1596 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1597
1598 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1599 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1600
1601 /* We don't need the FCS appended to the packet. */
1602 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1603 if (jumbo)
1604 r |= XM_RX_BIG_PK_OK;
1605
1606 if (skge->duplex == DUPLEX_HALF) {
1607 /*
1608 * If in manual half duplex mode the other side might be in
1609 * full duplex mode, so ignore if a carrier extension is not seen
1610 * on frames received
1611 */
1612 r |= XM_RX_DIS_CEXT;
1613 }
1614 xm_write16(hw, port, XM_RX_CMD, r);
1615
1616 /* We want short frames padded to 60 bytes. */
1617 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1618
1619 /* Increase threshold for jumbo frames on dual port */
1620 if (hw->ports > 1 && jumbo)
1621 xm_write16(hw, port, XM_TX_THR, 1020);
1622 else
1623 xm_write16(hw, port, XM_TX_THR, 512);
1624
1625 /*
1626 * Enable the reception of all error frames. This is
1627 * a necessary evil due to the design of the XMAC. The
1628 * XMAC's receive FIFO is only 8K in size, however jumbo
1629 * frames can be up to 9000 bytes in length. When bad
1630 * frame filtering is enabled, the XMAC's RX FIFO operates
1631 * in 'store and forward' mode. For this to work, the
1632 * entire frame has to fit into the FIFO, but that means
1633 * that jumbo frames larger than 8192 bytes will be
1634 * truncated. Disabling all bad frame filtering causes
1635 * the RX FIFO to operate in streaming mode, in which
1636 * case the XMAC will start transferring frames out of the
1637 * RX FIFO as soon as the FIFO threshold is reached.
1638 */
1639 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1640
1641
1642 /*
1643 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1644 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1645 * and 'Octets Rx OK Hi Cnt Ov'.
1646 */
1647 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1648
1649 /*
1650 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1651 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1652 * and 'Octets Tx OK Hi Cnt Ov'.
1653 */
1654 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1655
1656 /* Configure MAC arbiter */
1657 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1658
1659 /* configure timeout values */
1660 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1661 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1662 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1663 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1664
1665 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1666 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1667 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1668 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1669
1670 /* Configure Rx MAC FIFO */
1671 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1672 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1673 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1674
1675 /* Configure Tx MAC FIFO */
1676 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1677 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1678 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1679
1680 if (jumbo) {
1681 /* Enable frame flushing if jumbo frames used */
1682 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1683 } else {
1684 /* enable timeout timers if normal frames */
1685 skge_write16(hw, B3_PA_CTRL,
1686 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1687 }
1688}
1689
1690static void genesis_stop(struct skge_port *skge)
1691{
1692 struct skge_hw *hw = skge->hw;
1693 int port = skge->port;
1694 unsigned retries = 1000;
1695 u16 cmd;
1696
1697 /* Disable Tx and Rx */
1698 cmd = xm_read16(hw, port, XM_MMU_CMD);
1699 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1700 xm_write16(hw, port, XM_MMU_CMD, cmd);
1701
1702 genesis_reset(hw, port);
1703
1704 /* Clear Tx packet arbiter timeout IRQ */
1705 skge_write16(hw, B3_PA_CTRL,
1706 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1707
1708 /* Reset the MAC */
1709 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1710 do {
1711 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1712 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1713 break;
1714 } while (--retries > 0);
1715
1716 /* For external PHYs there must be special handling */
1717 if (hw->phy_type != SK_PHY_XMAC) {
1718 u32 reg = skge_read32(hw, B2_GP_IO);
1719 if (port == 0) {
1720 reg |= GP_DIR_0;
1721 reg &= ~GP_IO_0;
1722 } else {
1723 reg |= GP_DIR_2;
1724 reg &= ~GP_IO_2;
1725 }
1726 skge_write32(hw, B2_GP_IO, reg);
1727 skge_read32(hw, B2_GP_IO);
1728 }
1729
1730 xm_write16(hw, port, XM_MMU_CMD,
1731 xm_read16(hw, port, XM_MMU_CMD)
1732 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1733
1734 xm_read16(hw, port, XM_MMU_CMD);
1735}
1736
1737
1738static void genesis_get_stats(struct skge_port *skge, u64 *data)
1739{
1740 struct skge_hw *hw = skge->hw;
1741 int port = skge->port;
1742 int i;
1743 unsigned long timeout = jiffies + HZ;
1744
1745 xm_write16(hw, port,
1746 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1747
1748 /* wait for update to complete */
1749 while (xm_read16(hw, port, XM_STAT_CMD)
1750 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1751 if (time_after(jiffies, timeout))
1752 break;
1753 udelay(10);
1754 }
1755
1756 /* special case for 64 bit octet counter */
1757 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1758 | xm_read32(hw, port, XM_TXO_OK_LO);
1759 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1760 | xm_read32(hw, port, XM_RXO_OK_LO);
1761
1762 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1763 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1764}
1765
1766static void genesis_mac_intr(struct skge_hw *hw, int port)
1767{
1768 struct net_device *dev = hw->dev[port];
1769 struct skge_port *skge = netdev_priv(dev);
1770 u16 status = xm_read16(hw, port, XM_ISRC);
1771
1772 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1773 "mac interrupt status 0x%x\n", status);
1774
1775 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1776 xm_link_down(hw, port);
1777 mod_timer(&skge->link_timer, jiffies + 1);
1778 }
1779
1780 if (status & XM_IS_TXF_UR) {
1781 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1782 ++dev->stats.tx_fifo_errors;
1783 }
1784}
1785
1786static void genesis_link_up(struct skge_port *skge)
1787{
1788 struct skge_hw *hw = skge->hw;
1789 int port = skge->port;
1790 u16 cmd, msk;
1791 u32 mode;
1792
1793 cmd = xm_read16(hw, port, XM_MMU_CMD);
1794
1795 /*
1796 * enabling pause frame reception is required for 1000BT
1797 * because the XMAC is not reset if the link is going down
1798 */
1799 if (skge->flow_status == FLOW_STAT_NONE ||
1800 skge->flow_status == FLOW_STAT_LOC_SEND)
1801 /* Disable Pause Frame Reception */
1802 cmd |= XM_MMU_IGN_PF;
1803 else
1804 /* Enable Pause Frame Reception */
1805 cmd &= ~XM_MMU_IGN_PF;
1806
1807 xm_write16(hw, port, XM_MMU_CMD, cmd);
1808
1809 mode = xm_read32(hw, port, XM_MODE);
1810 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1811 skge->flow_status == FLOW_STAT_LOC_SEND) {
1812 /*
1813 * Configure Pause Frame Generation
1814 * Use internal and external Pause Frame Generation.
1815 * Sending pause frames is edge triggered.
1816 * Send a Pause frame with the maximum pause time if
1817 * internal oder external FIFO full condition occurs.
1818 * Send a zero pause time frame to re-start transmission.
1819 */
1820 /* XM_PAUSE_DA = '010000C28001' (default) */
1821 /* XM_MAC_PTIME = 0xffff (maximum) */
1822 /* remember this value is defined in big endian (!) */
1823 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1824
1825 mode |= XM_PAUSE_MODE;
1826 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1827 } else {
1828 /*
1829 * disable pause frame generation is required for 1000BT
1830 * because the XMAC is not reset if the link is going down
1831 */
1832 /* Disable Pause Mode in Mode Register */
1833 mode &= ~XM_PAUSE_MODE;
1834
1835 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1836 }
1837
1838 xm_write32(hw, port, XM_MODE, mode);
1839
1840 /* Turn on detection of Tx underrun */
1841 msk = xm_read16(hw, port, XM_IMSK);
1842 msk &= ~XM_IS_TXF_UR;
1843 xm_write16(hw, port, XM_IMSK, msk);
1844
1845 xm_read16(hw, port, XM_ISRC);
1846
1847 /* get MMU Command Reg. */
1848 cmd = xm_read16(hw, port, XM_MMU_CMD);
1849 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1850 cmd |= XM_MMU_GMII_FD;
1851
1852 /*
1853 * Workaround BCOM Errata (#10523) for all BCom Phys
1854 * Enable Power Management after link up
1855 */
1856 if (hw->phy_type == SK_PHY_BCOM) {
1857 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1858 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1859 & ~PHY_B_AC_DIS_PM);
1860 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1861 }
1862
1863 /* enable Rx/Tx */
1864 xm_write16(hw, port, XM_MMU_CMD,
1865 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1866 skge_link_up(skge);
1867}
1868
1869
1870static inline void bcom_phy_intr(struct skge_port *skge)
1871{
1872 struct skge_hw *hw = skge->hw;
1873 int port = skge->port;
1874 u16 isrc;
1875
1876 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1877 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1878 "phy interrupt status 0x%x\n", isrc);
1879
1880 if (isrc & PHY_B_IS_PSE)
1881 pr_err("%s: uncorrectable pair swap error\n",
1882 hw->dev[port]->name);
1883
1884 /* Workaround BCom Errata:
1885 * enable and disable loopback mode if "NO HCD" occurs.
1886 */
1887 if (isrc & PHY_B_IS_NO_HDCL) {
1888 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1889 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1890 ctrl | PHY_CT_LOOP);
1891 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1892 ctrl & ~PHY_CT_LOOP);
1893 }
1894
1895 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1896 bcom_check_link(hw, port);
1897
1898}
1899
1900static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1901{
1902 int i;
1903
1904 gma_write16(hw, port, GM_SMI_DATA, val);
1905 gma_write16(hw, port, GM_SMI_CTRL,
1906 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1907 for (i = 0; i < PHY_RETRIES; i++) {
1908 udelay(1);
1909
1910 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1911 return 0;
1912 }
1913
1914 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1915 return -EIO;
1916}
1917
1918static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1919{
1920 int i;
1921
1922 gma_write16(hw, port, GM_SMI_CTRL,
1923 GM_SMI_CT_PHY_AD(hw->phy_addr)
1924 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1925
1926 for (i = 0; i < PHY_RETRIES; i++) {
1927 udelay(1);
1928 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1929 goto ready;
1930 }
1931
1932 return -ETIMEDOUT;
1933 ready:
1934 *val = gma_read16(hw, port, GM_SMI_DATA);
1935 return 0;
1936}
1937
1938static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1939{
1940 u16 v = 0;
1941 if (__gm_phy_read(hw, port, reg, &v))
1942 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1943 return v;
1944}
1945
1946/* Marvell Phy Initialization */
1947static void yukon_init(struct skge_hw *hw, int port)
1948{
1949 struct skge_port *skge = netdev_priv(hw->dev[port]);
1950 u16 ctrl, ct1000, adv;
1951
1952 if (skge->autoneg == AUTONEG_ENABLE) {
1953 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1954
1955 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1956 PHY_M_EC_MAC_S_MSK);
1957 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1958
1959 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1960
1961 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1962 }
1963
1964 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1965 if (skge->autoneg == AUTONEG_DISABLE)
1966 ctrl &= ~PHY_CT_ANE;
1967
1968 ctrl |= PHY_CT_RESET;
1969 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1970
1971 ctrl = 0;
1972 ct1000 = 0;
1973 adv = PHY_AN_CSMA;
1974
1975 if (skge->autoneg == AUTONEG_ENABLE) {
1976 if (hw->copper) {
1977 if (skge->advertising & ADVERTISED_1000baseT_Full)
1978 ct1000 |= PHY_M_1000C_AFD;
1979 if (skge->advertising & ADVERTISED_1000baseT_Half)
1980 ct1000 |= PHY_M_1000C_AHD;
1981 if (skge->advertising & ADVERTISED_100baseT_Full)
1982 adv |= PHY_M_AN_100_FD;
1983 if (skge->advertising & ADVERTISED_100baseT_Half)
1984 adv |= PHY_M_AN_100_HD;
1985 if (skge->advertising & ADVERTISED_10baseT_Full)
1986 adv |= PHY_M_AN_10_FD;
1987 if (skge->advertising & ADVERTISED_10baseT_Half)
1988 adv |= PHY_M_AN_10_HD;
1989
1990 /* Set Flow-control capabilities */
1991 adv |= phy_pause_map[skge->flow_control];
1992 } else {
1993 if (skge->advertising & ADVERTISED_1000baseT_Full)
1994 adv |= PHY_M_AN_1000X_AFD;
1995 if (skge->advertising & ADVERTISED_1000baseT_Half)
1996 adv |= PHY_M_AN_1000X_AHD;
1997
1998 adv |= fiber_pause_map[skge->flow_control];
1999 }
2000
2001 /* Restart Auto-negotiation */
2002 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
2003 } else {
2004 /* forced speed/duplex settings */
2005 ct1000 = PHY_M_1000C_MSE;
2006
2007 if (skge->duplex == DUPLEX_FULL)
2008 ctrl |= PHY_CT_DUP_MD;
2009
2010 switch (skge->speed) {
2011 case SPEED_1000:
2012 ctrl |= PHY_CT_SP1000;
2013 break;
2014 case SPEED_100:
2015 ctrl |= PHY_CT_SP100;
2016 break;
2017 }
2018
2019 ctrl |= PHY_CT_RESET;
2020 }
2021
2022 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2023
2024 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2025 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2026
2027 /* Enable phy interrupt on autonegotiation complete (or link up) */
2028 if (skge->autoneg == AUTONEG_ENABLE)
2029 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2030 else
2031 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2032}
2033
2034static void yukon_reset(struct skge_hw *hw, int port)
2035{
2036 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2037 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2038 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2039 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2040 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2041
2042 gma_write16(hw, port, GM_RX_CTRL,
2043 gma_read16(hw, port, GM_RX_CTRL)
2044 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2045}
2046
2047/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2048static int is_yukon_lite_a0(struct skge_hw *hw)
2049{
2050 u32 reg;
2051 int ret;
2052
2053 if (hw->chip_id != CHIP_ID_YUKON)
2054 return 0;
2055
2056 reg = skge_read32(hw, B2_FAR);
2057 skge_write8(hw, B2_FAR + 3, 0xff);
2058 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2059 skge_write32(hw, B2_FAR, reg);
2060 return ret;
2061}
2062
2063static void yukon_mac_init(struct skge_hw *hw, int port)
2064{
2065 struct skge_port *skge = netdev_priv(hw->dev[port]);
2066 int i;
2067 u32 reg;
2068 const u8 *addr = hw->dev[port]->dev_addr;
2069
2070 /* WA code for COMA mode -- set PHY reset */
2071 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2072 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2073 reg = skge_read32(hw, B2_GP_IO);
2074 reg |= GP_DIR_9 | GP_IO_9;
2075 skge_write32(hw, B2_GP_IO, reg);
2076 }
2077
2078 /* hard reset */
2079 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2080 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2081
2082 /* WA code for COMA mode -- clear PHY reset */
2083 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2084 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2085 reg = skge_read32(hw, B2_GP_IO);
2086 reg |= GP_DIR_9;
2087 reg &= ~GP_IO_9;
2088 skge_write32(hw, B2_GP_IO, reg);
2089 }
2090
2091 /* Set hardware config mode */
2092 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2093 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2094 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2095
2096 /* Clear GMC reset */
2097 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2098 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2099 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2100
2101 if (skge->autoneg == AUTONEG_DISABLE) {
2102 reg = GM_GPCR_AU_ALL_DIS;
2103 gma_write16(hw, port, GM_GP_CTRL,
2104 gma_read16(hw, port, GM_GP_CTRL) | reg);
2105
2106 switch (skge->speed) {
2107 case SPEED_1000:
2108 reg &= ~GM_GPCR_SPEED_100;
2109 reg |= GM_GPCR_SPEED_1000;
2110 break;
2111 case SPEED_100:
2112 reg &= ~GM_GPCR_SPEED_1000;
2113 reg |= GM_GPCR_SPEED_100;
2114 break;
2115 case SPEED_10:
2116 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2117 break;
2118 }
2119
2120 if (skge->duplex == DUPLEX_FULL)
2121 reg |= GM_GPCR_DUP_FULL;
2122 } else
2123 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2124
2125 switch (skge->flow_control) {
2126 case FLOW_MODE_NONE:
2127 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2128 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2129 break;
2130 case FLOW_MODE_LOC_SEND:
2131 /* disable Rx flow-control */
2132 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2133 break;
2134 case FLOW_MODE_SYMMETRIC:
2135 case FLOW_MODE_SYM_OR_REM:
2136 /* enable Tx & Rx flow-control */
2137 break;
2138 }
2139
2140 gma_write16(hw, port, GM_GP_CTRL, reg);
2141 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2142
2143 yukon_init(hw, port);
2144
2145 /* MIB clear */
2146 reg = gma_read16(hw, port, GM_PHY_ADDR);
2147 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2148
2149 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2150 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2151 gma_write16(hw, port, GM_PHY_ADDR, reg);
2152
2153 /* transmit control */
2154 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2155
2156 /* receive control reg: unicast + multicast + no FCS */
2157 gma_write16(hw, port, GM_RX_CTRL,
2158 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2159
2160 /* transmit flow control */
2161 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2162
2163 /* transmit parameter */
2164 gma_write16(hw, port, GM_TX_PARAM,
2165 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2166 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2167 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2168
2169 /* configure the Serial Mode Register */
2170 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2171 | GM_SMOD_VLAN_ENA
2172 | IPG_DATA_VAL(IPG_DATA_DEF);
2173
2174 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2175 reg |= GM_SMOD_JUMBO_ENA;
2176
2177 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2178
2179 /* physical address: used for pause frames */
2180 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2181 /* virtual address for data */
2182 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2183
2184 /* enable interrupt mask for counter overflows */
2185 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2186 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2187 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2188
2189 /* Initialize Mac Fifo */
2190
2191 /* Configure Rx MAC FIFO */
2192 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2193 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2194
2195 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2196 if (is_yukon_lite_a0(hw))
2197 reg &= ~GMF_RX_F_FL_ON;
2198
2199 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2200 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2201 /*
2202 * because Pause Packet Truncation in GMAC is not working
2203 * we have to increase the Flush Threshold to 64 bytes
2204 * in order to flush pause packets in Rx FIFO on Yukon-1
2205 */
2206 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2207
2208 /* Configure Tx MAC FIFO */
2209 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2210 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2211}
2212
2213/* Go into power down mode */
2214static void yukon_suspend(struct skge_hw *hw, int port)
2215{
2216 u16 ctrl;
2217
2218 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2219 ctrl |= PHY_M_PC_POL_R_DIS;
2220 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2221
2222 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2223 ctrl |= PHY_CT_RESET;
2224 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2225
2226 /* switch IEEE compatible power down mode on */
2227 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2228 ctrl |= PHY_CT_PDOWN;
2229 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2230}
2231
2232static void yukon_stop(struct skge_port *skge)
2233{
2234 struct skge_hw *hw = skge->hw;
2235 int port = skge->port;
2236
2237 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2238 yukon_reset(hw, port);
2239
2240 gma_write16(hw, port, GM_GP_CTRL,
2241 gma_read16(hw, port, GM_GP_CTRL)
2242 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2243 gma_read16(hw, port, GM_GP_CTRL);
2244
2245 yukon_suspend(hw, port);
2246
2247 /* set GPHY Control reset */
2248 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2249 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2250}
2251
2252static void yukon_get_stats(struct skge_port *skge, u64 *data)
2253{
2254 struct skge_hw *hw = skge->hw;
2255 int port = skge->port;
2256 int i;
2257
2258 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2259 | gma_read32(hw, port, GM_TXO_OK_LO);
2260 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2261 | gma_read32(hw, port, GM_RXO_OK_LO);
2262
2263 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2264 data[i] = gma_read32(hw, port,
2265 skge_stats[i].gma_offset);
2266}
2267
2268static void yukon_mac_intr(struct skge_hw *hw, int port)
2269{
2270 struct net_device *dev = hw->dev[port];
2271 struct skge_port *skge = netdev_priv(dev);
2272 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2273
2274 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2275 "mac interrupt status 0x%x\n", status);
2276
2277 if (status & GM_IS_RX_FF_OR) {
2278 ++dev->stats.rx_fifo_errors;
2279 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2280 }
2281
2282 if (status & GM_IS_TX_FF_UR) {
2283 ++dev->stats.tx_fifo_errors;
2284 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2285 }
2286
2287}
2288
2289static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2290{
2291 switch (aux & PHY_M_PS_SPEED_MSK) {
2292 case PHY_M_PS_SPEED_1000:
2293 return SPEED_1000;
2294 case PHY_M_PS_SPEED_100:
2295 return SPEED_100;
2296 default:
2297 return SPEED_10;
2298 }
2299}
2300
2301static void yukon_link_up(struct skge_port *skge)
2302{
2303 struct skge_hw *hw = skge->hw;
2304 int port = skge->port;
2305 u16 reg;
2306
2307 /* Enable Transmit FIFO Underrun */
2308 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2309
2310 reg = gma_read16(hw, port, GM_GP_CTRL);
2311 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2312 reg |= GM_GPCR_DUP_FULL;
2313
2314 /* enable Rx/Tx */
2315 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2316 gma_write16(hw, port, GM_GP_CTRL, reg);
2317
2318 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2319 skge_link_up(skge);
2320}
2321
2322static void yukon_link_down(struct skge_port *skge)
2323{
2324 struct skge_hw *hw = skge->hw;
2325 int port = skge->port;
2326 u16 ctrl;
2327
2328 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2329 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2330 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2331
2332 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2333 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2334 ctrl |= PHY_M_AN_ASP;
2335 /* restore Asymmetric Pause bit */
2336 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2337 }
2338
2339 skge_link_down(skge);
2340
2341 yukon_init(hw, port);
2342}
2343
2344static void yukon_phy_intr(struct skge_port *skge)
2345{
2346 struct skge_hw *hw = skge->hw;
2347 int port = skge->port;
2348 const char *reason = NULL;
2349 u16 istatus, phystat;
2350
2351 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2352 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2353
2354 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2355 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2356
2357 if (istatus & PHY_M_IS_AN_COMPL) {
2358 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2359 & PHY_M_AN_RF) {
2360 reason = "remote fault";
2361 goto failed;
2362 }
2363
2364 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2365 reason = "master/slave fault";
2366 goto failed;
2367 }
2368
2369 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2370 reason = "speed/duplex";
2371 goto failed;
2372 }
2373
2374 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2375 ? DUPLEX_FULL : DUPLEX_HALF;
2376 skge->speed = yukon_speed(hw, phystat);
2377
2378 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2379 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2380 case PHY_M_PS_PAUSE_MSK:
2381 skge->flow_status = FLOW_STAT_SYMMETRIC;
2382 break;
2383 case PHY_M_PS_RX_P_EN:
2384 skge->flow_status = FLOW_STAT_REM_SEND;
2385 break;
2386 case PHY_M_PS_TX_P_EN:
2387 skge->flow_status = FLOW_STAT_LOC_SEND;
2388 break;
2389 default:
2390 skge->flow_status = FLOW_STAT_NONE;
2391 }
2392
2393 if (skge->flow_status == FLOW_STAT_NONE ||
2394 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2395 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2396 else
2397 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2398 yukon_link_up(skge);
2399 return;
2400 }
2401
2402 if (istatus & PHY_M_IS_LSP_CHANGE)
2403 skge->speed = yukon_speed(hw, phystat);
2404
2405 if (istatus & PHY_M_IS_DUP_CHANGE)
2406 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2407 if (istatus & PHY_M_IS_LST_CHANGE) {
2408 if (phystat & PHY_M_PS_LINK_UP)
2409 yukon_link_up(skge);
2410 else
2411 yukon_link_down(skge);
2412 }
2413 return;
2414 failed:
2415 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2416
2417 /* XXX restart autonegotiation? */
2418}
2419
2420static void skge_phy_reset(struct skge_port *skge)
2421{
2422 struct skge_hw *hw = skge->hw;
2423 int port = skge->port;
2424 struct net_device *dev = hw->dev[port];
2425
2426 netif_stop_queue(skge->netdev);
2427 netif_carrier_off(skge->netdev);
2428
2429 spin_lock_bh(&hw->phy_lock);
2430 if (is_genesis(hw)) {
2431 genesis_reset(hw, port);
2432 genesis_mac_init(hw, port);
2433 } else {
2434 yukon_reset(hw, port);
2435 yukon_init(hw, port);
2436 }
2437 spin_unlock_bh(&hw->phy_lock);
2438
2439 skge_set_multicast(dev);
2440}
2441
2442/* Basic MII support */
2443static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2444{
2445 struct mii_ioctl_data *data = if_mii(ifr);
2446 struct skge_port *skge = netdev_priv(dev);
2447 struct skge_hw *hw = skge->hw;
2448 int err = -EOPNOTSUPP;
2449
2450 if (!netif_running(dev))
2451 return -ENODEV; /* Phy still in reset */
2452
2453 switch (cmd) {
2454 case SIOCGMIIPHY:
2455 data->phy_id = hw->phy_addr;
2456
2457 fallthrough;
2458 case SIOCGMIIREG: {
2459 u16 val = 0;
2460 spin_lock_bh(&hw->phy_lock);
2461
2462 if (is_genesis(hw))
2463 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2464 else
2465 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2466 spin_unlock_bh(&hw->phy_lock);
2467 data->val_out = val;
2468 break;
2469 }
2470
2471 case SIOCSMIIREG:
2472 spin_lock_bh(&hw->phy_lock);
2473 if (is_genesis(hw))
2474 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2475 data->val_in);
2476 else
2477 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2478 data->val_in);
2479 spin_unlock_bh(&hw->phy_lock);
2480 break;
2481 }
2482 return err;
2483}
2484
2485static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2486{
2487 u32 end;
2488
2489 start /= 8;
2490 len /= 8;
2491 end = start + len - 1;
2492
2493 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2494 skge_write32(hw, RB_ADDR(q, RB_START), start);
2495 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2496 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2497 skge_write32(hw, RB_ADDR(q, RB_END), end);
2498
2499 if (q == Q_R1 || q == Q_R2) {
2500 /* Set thresholds on receive queue's */
2501 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2502 start + (2*len)/3);
2503 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2504 start + (len/3));
2505 } else {
2506 /* Enable store & forward on Tx queue's because
2507 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2508 */
2509 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2510 }
2511
2512 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2513}
2514
2515/* Setup Bus Memory Interface */
2516static void skge_qset(struct skge_port *skge, u16 q,
2517 const struct skge_element *e)
2518{
2519 struct skge_hw *hw = skge->hw;
2520 u32 watermark = 0x600;
2521 u64 base = skge->dma + (e->desc - skge->mem);
2522
2523 /* optimization to reduce window on 32bit/33mhz */
2524 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2525 watermark /= 2;
2526
2527 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2528 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2529 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2530 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2531}
2532
2533static int skge_up(struct net_device *dev)
2534{
2535 struct skge_port *skge = netdev_priv(dev);
2536 struct skge_hw *hw = skge->hw;
2537 int port = skge->port;
2538 u32 chunk, ram_addr;
2539 size_t rx_size, tx_size;
2540 int err;
2541
2542 if (!is_valid_ether_addr(dev->dev_addr))
2543 return -EINVAL;
2544
2545 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2546
2547 if (dev->mtu > RX_BUF_SIZE)
2548 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2549 else
2550 skge->rx_buf_size = RX_BUF_SIZE;
2551
2552
2553 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2554 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2555 skge->mem_size = tx_size + rx_size;
2556 skge->mem = dma_alloc_coherent(&hw->pdev->dev, skge->mem_size,
2557 &skge->dma, GFP_KERNEL);
2558 if (!skge->mem)
2559 return -ENOMEM;
2560
2561 BUG_ON(skge->dma & 7);
2562
2563 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2564 dev_err(&hw->pdev->dev, "dma_alloc_coherent region crosses 4G boundary\n");
2565 err = -EINVAL;
2566 goto free_pci_mem;
2567 }
2568
2569 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2570 if (err)
2571 goto free_pci_mem;
2572
2573 err = skge_rx_fill(dev);
2574 if (err)
2575 goto free_rx_ring;
2576
2577 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2578 skge->dma + rx_size);
2579 if (err)
2580 goto free_rx_ring;
2581
2582 if (hw->ports == 1) {
2583 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2584 dev->name, hw);
2585 if (err) {
2586 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2587 hw->pdev->irq, err);
2588 goto free_tx_ring;
2589 }
2590 }
2591
2592 /* Initialize MAC */
2593 netif_carrier_off(dev);
2594 spin_lock_bh(&hw->phy_lock);
2595 if (is_genesis(hw))
2596 genesis_mac_init(hw, port);
2597 else
2598 yukon_mac_init(hw, port);
2599 spin_unlock_bh(&hw->phy_lock);
2600
2601 /* Configure RAMbuffers - equally between ports and tx/rx */
2602 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2603 ram_addr = hw->ram_offset + 2 * chunk * port;
2604
2605 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2606 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2607
2608 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2609 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2610 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2611
2612 /* Start receiver BMU */
2613 wmb();
2614 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2615 skge_led(skge, LED_MODE_ON);
2616
2617 spin_lock_irq(&hw->hw_lock);
2618 hw->intr_mask |= portmask[port];
2619 skge_write32(hw, B0_IMSK, hw->intr_mask);
2620 skge_read32(hw, B0_IMSK);
2621 spin_unlock_irq(&hw->hw_lock);
2622
2623 napi_enable(&skge->napi);
2624
2625 skge_set_multicast(dev);
2626
2627 return 0;
2628
2629 free_tx_ring:
2630 kfree(skge->tx_ring.start);
2631 free_rx_ring:
2632 skge_rx_clean(skge);
2633 kfree(skge->rx_ring.start);
2634 free_pci_mem:
2635 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2636 skge->dma);
2637 skge->mem = NULL;
2638
2639 return err;
2640}
2641
2642/* stop receiver */
2643static void skge_rx_stop(struct skge_hw *hw, int port)
2644{
2645 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2646 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2647 RB_RST_SET|RB_DIS_OP_MD);
2648 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2649}
2650
2651static int skge_down(struct net_device *dev)
2652{
2653 struct skge_port *skge = netdev_priv(dev);
2654 struct skge_hw *hw = skge->hw;
2655 int port = skge->port;
2656
2657 if (!skge->mem)
2658 return 0;
2659
2660 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2661
2662 netif_tx_disable(dev);
2663
2664 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2665 del_timer_sync(&skge->link_timer);
2666
2667 napi_disable(&skge->napi);
2668 netif_carrier_off(dev);
2669
2670 spin_lock_irq(&hw->hw_lock);
2671 hw->intr_mask &= ~portmask[port];
2672 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2673 skge_read32(hw, B0_IMSK);
2674 spin_unlock_irq(&hw->hw_lock);
2675
2676 if (hw->ports == 1)
2677 free_irq(hw->pdev->irq, hw);
2678
2679 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2680 if (is_genesis(hw))
2681 genesis_stop(skge);
2682 else
2683 yukon_stop(skge);
2684
2685 /* Stop transmitter */
2686 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2687 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2688 RB_RST_SET|RB_DIS_OP_MD);
2689
2690
2691 /* Disable Force Sync bit and Enable Alloc bit */
2692 skge_write8(hw, SK_REG(port, TXA_CTRL),
2693 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2694
2695 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2696 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2697 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2698
2699 /* Reset PCI FIFO */
2700 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2701 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2702
2703 /* Reset the RAM Buffer async Tx queue */
2704 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2705
2706 skge_rx_stop(hw, port);
2707
2708 if (is_genesis(hw)) {
2709 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2710 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2711 } else {
2712 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2713 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2714 }
2715
2716 skge_led(skge, LED_MODE_OFF);
2717
2718 netif_tx_lock_bh(dev);
2719 skge_tx_clean(dev);
2720 netif_tx_unlock_bh(dev);
2721
2722 skge_rx_clean(skge);
2723
2724 kfree(skge->rx_ring.start);
2725 kfree(skge->tx_ring.start);
2726 dma_free_coherent(&hw->pdev->dev, skge->mem_size, skge->mem,
2727 skge->dma);
2728 skge->mem = NULL;
2729 return 0;
2730}
2731
2732static inline int skge_avail(const struct skge_ring *ring)
2733{
2734 smp_mb();
2735 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2736 + (ring->to_clean - ring->to_use) - 1;
2737}
2738
2739static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2740 struct net_device *dev)
2741{
2742 struct skge_port *skge = netdev_priv(dev);
2743 struct skge_hw *hw = skge->hw;
2744 struct skge_element *e;
2745 struct skge_tx_desc *td;
2746 int i;
2747 u32 control, len;
2748 dma_addr_t map;
2749
2750 if (skb_padto(skb, ETH_ZLEN))
2751 return NETDEV_TX_OK;
2752
2753 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2754 return NETDEV_TX_BUSY;
2755
2756 e = skge->tx_ring.to_use;
2757 td = e->desc;
2758 BUG_ON(td->control & BMU_OWN);
2759 e->skb = skb;
2760 len = skb_headlen(skb);
2761 map = dma_map_single(&hw->pdev->dev, skb->data, len, DMA_TO_DEVICE);
2762 if (dma_mapping_error(&hw->pdev->dev, map))
2763 goto mapping_error;
2764
2765 dma_unmap_addr_set(e, mapaddr, map);
2766 dma_unmap_len_set(e, maplen, len);
2767
2768 td->dma_lo = lower_32_bits(map);
2769 td->dma_hi = upper_32_bits(map);
2770
2771 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2772 const int offset = skb_checksum_start_offset(skb);
2773
2774 /* This seems backwards, but it is what the sk98lin
2775 * does. Looks like hardware is wrong?
2776 */
2777 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2778 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2779 control = BMU_TCP_CHECK;
2780 else
2781 control = BMU_UDP_CHECK;
2782
2783 td->csum_offs = 0;
2784 td->csum_start = offset;
2785 td->csum_write = offset + skb->csum_offset;
2786 } else
2787 control = BMU_CHECK;
2788
2789 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2790 control |= BMU_EOF | BMU_IRQ_EOF;
2791 else {
2792 struct skge_tx_desc *tf = td;
2793
2794 control |= BMU_STFWD;
2795 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2796 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2797
2798 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2799 skb_frag_size(frag), DMA_TO_DEVICE);
2800 if (dma_mapping_error(&hw->pdev->dev, map))
2801 goto mapping_unwind;
2802
2803 e = e->next;
2804 e->skb = skb;
2805 tf = e->desc;
2806 BUG_ON(tf->control & BMU_OWN);
2807
2808 tf->dma_lo = lower_32_bits(map);
2809 tf->dma_hi = upper_32_bits(map);
2810 dma_unmap_addr_set(e, mapaddr, map);
2811 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2812
2813 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2814 }
2815 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2816 }
2817 /* Make sure all the descriptors written */
2818 wmb();
2819 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2820 wmb();
2821
2822 netdev_sent_queue(dev, skb->len);
2823
2824 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2825
2826 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2827 "tx queued, slot %td, len %d\n",
2828 e - skge->tx_ring.start, skb->len);
2829
2830 skge->tx_ring.to_use = e->next;
2831 smp_wmb();
2832
2833 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2834 netdev_dbg(dev, "transmit queue full\n");
2835 netif_stop_queue(dev);
2836 }
2837
2838 return NETDEV_TX_OK;
2839
2840mapping_unwind:
2841 e = skge->tx_ring.to_use;
2842 dma_unmap_single(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2843 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2844 while (i-- > 0) {
2845 e = e->next;
2846 dma_unmap_page(&hw->pdev->dev, dma_unmap_addr(e, mapaddr),
2847 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2848 }
2849
2850mapping_error:
2851 if (net_ratelimit())
2852 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2853 dev_kfree_skb_any(skb);
2854 return NETDEV_TX_OK;
2855}
2856
2857
2858/* Free resources associated with this reing element */
2859static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2860 u32 control)
2861{
2862 /* skb header vs. fragment */
2863 if (control & BMU_STF)
2864 dma_unmap_single(&pdev->dev, dma_unmap_addr(e, mapaddr),
2865 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2866 else
2867 dma_unmap_page(&pdev->dev, dma_unmap_addr(e, mapaddr),
2868 dma_unmap_len(e, maplen), DMA_TO_DEVICE);
2869}
2870
2871/* Free all buffers in transmit ring */
2872static void skge_tx_clean(struct net_device *dev)
2873{
2874 struct skge_port *skge = netdev_priv(dev);
2875 struct skge_element *e;
2876
2877 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2878 struct skge_tx_desc *td = e->desc;
2879
2880 skge_tx_unmap(skge->hw->pdev, e, td->control);
2881
2882 if (td->control & BMU_EOF)
2883 dev_kfree_skb(e->skb);
2884 td->control = 0;
2885 }
2886
2887 netdev_reset_queue(dev);
2888 skge->tx_ring.to_clean = e;
2889}
2890
2891static void skge_tx_timeout(struct net_device *dev, unsigned int txqueue)
2892{
2893 struct skge_port *skge = netdev_priv(dev);
2894
2895 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2896
2897 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2898 skge_tx_clean(dev);
2899 netif_wake_queue(dev);
2900}
2901
2902static int skge_change_mtu(struct net_device *dev, int new_mtu)
2903{
2904 int err;
2905
2906 if (!netif_running(dev)) {
2907 WRITE_ONCE(dev->mtu, new_mtu);
2908 return 0;
2909 }
2910
2911 skge_down(dev);
2912
2913 WRITE_ONCE(dev->mtu, new_mtu);
2914
2915 err = skge_up(dev);
2916 if (err)
2917 dev_close(dev);
2918
2919 return err;
2920}
2921
2922static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2923
2924static void genesis_add_filter(u8 filter[8], const u8 *addr)
2925{
2926 u32 crc, bit;
2927
2928 crc = ether_crc_le(ETH_ALEN, addr);
2929 bit = ~crc & 0x3f;
2930 filter[bit/8] |= 1 << (bit%8);
2931}
2932
2933static void genesis_set_multicast(struct net_device *dev)
2934{
2935 struct skge_port *skge = netdev_priv(dev);
2936 struct skge_hw *hw = skge->hw;
2937 int port = skge->port;
2938 struct netdev_hw_addr *ha;
2939 u32 mode;
2940 u8 filter[8];
2941
2942 mode = xm_read32(hw, port, XM_MODE);
2943 mode |= XM_MD_ENA_HASH;
2944 if (dev->flags & IFF_PROMISC)
2945 mode |= XM_MD_ENA_PROM;
2946 else
2947 mode &= ~XM_MD_ENA_PROM;
2948
2949 if (dev->flags & IFF_ALLMULTI)
2950 memset(filter, 0xff, sizeof(filter));
2951 else {
2952 memset(filter, 0, sizeof(filter));
2953
2954 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2955 skge->flow_status == FLOW_STAT_SYMMETRIC)
2956 genesis_add_filter(filter, pause_mc_addr);
2957
2958 netdev_for_each_mc_addr(ha, dev)
2959 genesis_add_filter(filter, ha->addr);
2960 }
2961
2962 xm_write32(hw, port, XM_MODE, mode);
2963 xm_outhash(hw, port, XM_HSM, filter);
2964}
2965
2966static void yukon_add_filter(u8 filter[8], const u8 *addr)
2967{
2968 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2969
2970 filter[bit / 8] |= 1 << (bit % 8);
2971}
2972
2973static void yukon_set_multicast(struct net_device *dev)
2974{
2975 struct skge_port *skge = netdev_priv(dev);
2976 struct skge_hw *hw = skge->hw;
2977 int port = skge->port;
2978 struct netdev_hw_addr *ha;
2979 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2980 skge->flow_status == FLOW_STAT_SYMMETRIC);
2981 u16 reg;
2982 u8 filter[8];
2983
2984 memset(filter, 0, sizeof(filter));
2985
2986 reg = gma_read16(hw, port, GM_RX_CTRL);
2987 reg |= GM_RXCR_UCF_ENA;
2988
2989 if (dev->flags & IFF_PROMISC) /* promiscuous */
2990 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2991 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2992 memset(filter, 0xff, sizeof(filter));
2993 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2994 reg &= ~GM_RXCR_MCF_ENA;
2995 else {
2996 reg |= GM_RXCR_MCF_ENA;
2997
2998 if (rx_pause)
2999 yukon_add_filter(filter, pause_mc_addr);
3000
3001 netdev_for_each_mc_addr(ha, dev)
3002 yukon_add_filter(filter, ha->addr);
3003 }
3004
3005
3006 gma_write16(hw, port, GM_MC_ADDR_H1,
3007 (u16)filter[0] | ((u16)filter[1] << 8));
3008 gma_write16(hw, port, GM_MC_ADDR_H2,
3009 (u16)filter[2] | ((u16)filter[3] << 8));
3010 gma_write16(hw, port, GM_MC_ADDR_H3,
3011 (u16)filter[4] | ((u16)filter[5] << 8));
3012 gma_write16(hw, port, GM_MC_ADDR_H4,
3013 (u16)filter[6] | ((u16)filter[7] << 8));
3014
3015 gma_write16(hw, port, GM_RX_CTRL, reg);
3016}
3017
3018static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3019{
3020 if (is_genesis(hw))
3021 return status >> XMR_FS_LEN_SHIFT;
3022 else
3023 return status >> GMR_FS_LEN_SHIFT;
3024}
3025
3026static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3027{
3028 if (is_genesis(hw))
3029 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3030 else
3031 return (status & GMR_FS_ANY_ERR) ||
3032 (status & GMR_FS_RX_OK) == 0;
3033}
3034
3035static void skge_set_multicast(struct net_device *dev)
3036{
3037 struct skge_port *skge = netdev_priv(dev);
3038
3039 if (is_genesis(skge->hw))
3040 genesis_set_multicast(dev);
3041 else
3042 yukon_set_multicast(dev);
3043
3044}
3045
3046
3047/* Get receive buffer from descriptor.
3048 * Handles copy of small buffers and reallocation failures
3049 */
3050static struct sk_buff *skge_rx_get(struct net_device *dev,
3051 struct skge_element *e,
3052 u32 control, u32 status, u16 csum)
3053{
3054 struct skge_port *skge = netdev_priv(dev);
3055 struct sk_buff *skb;
3056 u16 len = control & BMU_BBC;
3057
3058 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3059 "rx slot %td status 0x%x len %d\n",
3060 e - skge->rx_ring.start, status, len);
3061
3062 if (len > skge->rx_buf_size)
3063 goto error;
3064
3065 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3066 goto error;
3067
3068 if (bad_phy_status(skge->hw, status))
3069 goto error;
3070
3071 if (phy_length(skge->hw, status) != len)
3072 goto error;
3073
3074 if (len < RX_COPY_THRESHOLD) {
3075 skb = netdev_alloc_skb_ip_align(dev, len);
3076 if (!skb)
3077 goto resubmit;
3078
3079 dma_sync_single_for_cpu(&skge->hw->pdev->dev,
3080 dma_unmap_addr(e, mapaddr),
3081 dma_unmap_len(e, maplen),
3082 DMA_FROM_DEVICE);
3083 skb_copy_from_linear_data(e->skb, skb->data, len);
3084 dma_sync_single_for_device(&skge->hw->pdev->dev,
3085 dma_unmap_addr(e, mapaddr),
3086 dma_unmap_len(e, maplen),
3087 DMA_FROM_DEVICE);
3088 skge_rx_reuse(e, skge->rx_buf_size);
3089 } else {
3090 struct skge_element ee;
3091 struct sk_buff *nskb;
3092
3093 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3094 if (!nskb)
3095 goto resubmit;
3096
3097 ee = *e;
3098
3099 skb = ee.skb;
3100 prefetch(skb->data);
3101
3102 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3103 dev_kfree_skb(nskb);
3104 goto resubmit;
3105 }
3106
3107 dma_unmap_single(&skge->hw->pdev->dev,
3108 dma_unmap_addr(&ee, mapaddr),
3109 dma_unmap_len(&ee, maplen), DMA_FROM_DEVICE);
3110 }
3111
3112 skb_put(skb, len);
3113
3114 if (dev->features & NETIF_F_RXCSUM) {
3115 skb->csum = le16_to_cpu(csum);
3116 skb->ip_summed = CHECKSUM_COMPLETE;
3117 }
3118
3119 skb->protocol = eth_type_trans(skb, dev);
3120
3121 return skb;
3122error:
3123
3124 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3125 "rx err, slot %td control 0x%x status 0x%x\n",
3126 e - skge->rx_ring.start, control, status);
3127
3128 if (is_genesis(skge->hw)) {
3129 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3130 dev->stats.rx_length_errors++;
3131 if (status & XMR_FS_FRA_ERR)
3132 dev->stats.rx_frame_errors++;
3133 if (status & XMR_FS_FCS_ERR)
3134 dev->stats.rx_crc_errors++;
3135 } else {
3136 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3137 dev->stats.rx_length_errors++;
3138 if (status & GMR_FS_FRAGMENT)
3139 dev->stats.rx_frame_errors++;
3140 if (status & GMR_FS_CRC_ERR)
3141 dev->stats.rx_crc_errors++;
3142 }
3143
3144resubmit:
3145 skge_rx_reuse(e, skge->rx_buf_size);
3146 return NULL;
3147}
3148
3149/* Free all buffers in Tx ring which are no longer owned by device */
3150static void skge_tx_done(struct net_device *dev)
3151{
3152 struct skge_port *skge = netdev_priv(dev);
3153 struct skge_ring *ring = &skge->tx_ring;
3154 struct skge_element *e;
3155 unsigned int bytes_compl = 0, pkts_compl = 0;
3156
3157 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3158
3159 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3160 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3161
3162 if (control & BMU_OWN)
3163 break;
3164
3165 skge_tx_unmap(skge->hw->pdev, e, control);
3166
3167 if (control & BMU_EOF) {
3168 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3169 "tx done slot %td\n",
3170 e - skge->tx_ring.start);
3171
3172 pkts_compl++;
3173 bytes_compl += e->skb->len;
3174
3175 dev_consume_skb_any(e->skb);
3176 }
3177 }
3178 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3179 skge->tx_ring.to_clean = e;
3180
3181 /* Can run lockless until we need to synchronize to restart queue. */
3182 smp_mb();
3183
3184 if (unlikely(netif_queue_stopped(dev) &&
3185 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3186 netif_tx_lock(dev);
3187 if (unlikely(netif_queue_stopped(dev) &&
3188 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3189 netif_wake_queue(dev);
3190
3191 }
3192 netif_tx_unlock(dev);
3193 }
3194}
3195
3196static int skge_poll(struct napi_struct *napi, int budget)
3197{
3198 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3199 struct net_device *dev = skge->netdev;
3200 struct skge_hw *hw = skge->hw;
3201 struct skge_ring *ring = &skge->rx_ring;
3202 struct skge_element *e;
3203 int work_done = 0;
3204
3205 skge_tx_done(dev);
3206
3207 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3208
3209 for (e = ring->to_clean; prefetch(e->next), work_done < budget; e = e->next) {
3210 struct skge_rx_desc *rd = e->desc;
3211 struct sk_buff *skb;
3212 u32 control;
3213
3214 rmb();
3215 control = rd->control;
3216 if (control & BMU_OWN)
3217 break;
3218
3219 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3220 if (likely(skb)) {
3221 napi_gro_receive(napi, skb);
3222 ++work_done;
3223 }
3224 }
3225 ring->to_clean = e;
3226
3227 /* restart receiver */
3228 wmb();
3229 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3230
3231 if (work_done < budget && napi_complete_done(napi, work_done)) {
3232 unsigned long flags;
3233
3234 spin_lock_irqsave(&hw->hw_lock, flags);
3235 hw->intr_mask |= napimask[skge->port];
3236 skge_write32(hw, B0_IMSK, hw->intr_mask);
3237 skge_read32(hw, B0_IMSK);
3238 spin_unlock_irqrestore(&hw->hw_lock, flags);
3239 }
3240
3241 return work_done;
3242}
3243
3244/* Parity errors seem to happen when Genesis is connected to a switch
3245 * with no other ports present. Heartbeat error??
3246 */
3247static void skge_mac_parity(struct skge_hw *hw, int port)
3248{
3249 struct net_device *dev = hw->dev[port];
3250
3251 ++dev->stats.tx_heartbeat_errors;
3252
3253 if (is_genesis(hw))
3254 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3255 MFF_CLR_PERR);
3256 else
3257 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3258 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3259 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3260 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3261}
3262
3263static void skge_mac_intr(struct skge_hw *hw, int port)
3264{
3265 if (is_genesis(hw))
3266 genesis_mac_intr(hw, port);
3267 else
3268 yukon_mac_intr(hw, port);
3269}
3270
3271/* Handle device specific framing and timeout interrupts */
3272static void skge_error_irq(struct skge_hw *hw)
3273{
3274 struct pci_dev *pdev = hw->pdev;
3275 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3276
3277 if (is_genesis(hw)) {
3278 /* clear xmac errors */
3279 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3280 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3281 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3282 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3283 } else {
3284 /* Timestamp (unused) overflow */
3285 if (hwstatus & IS_IRQ_TIST_OV)
3286 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3287 }
3288
3289 if (hwstatus & IS_RAM_RD_PAR) {
3290 dev_err(&pdev->dev, "Ram read data parity error\n");
3291 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3292 }
3293
3294 if (hwstatus & IS_RAM_WR_PAR) {
3295 dev_err(&pdev->dev, "Ram write data parity error\n");
3296 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3297 }
3298
3299 if (hwstatus & IS_M1_PAR_ERR)
3300 skge_mac_parity(hw, 0);
3301
3302 if (hwstatus & IS_M2_PAR_ERR)
3303 skge_mac_parity(hw, 1);
3304
3305 if (hwstatus & IS_R1_PAR_ERR) {
3306 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3307 hw->dev[0]->name);
3308 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3309 }
3310
3311 if (hwstatus & IS_R2_PAR_ERR) {
3312 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3313 hw->dev[1]->name);
3314 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3315 }
3316
3317 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3318 u16 pci_status, pci_cmd;
3319
3320 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3321 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3322
3323 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3324 pci_cmd, pci_status);
3325
3326 /* Write the error bits back to clear them. */
3327 pci_status &= PCI_STATUS_ERROR_BITS;
3328 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3329 pci_write_config_word(pdev, PCI_COMMAND,
3330 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3331 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3332 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3333
3334 /* if error still set then just ignore it */
3335 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3336 if (hwstatus & IS_IRQ_STAT) {
3337 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3338 hw->intr_mask &= ~IS_HW_ERR;
3339 }
3340 }
3341}
3342
3343/*
3344 * Interrupt from PHY are handled in tasklet (softirq)
3345 * because accessing phy registers requires spin wait which might
3346 * cause excess interrupt latency.
3347 */
3348static void skge_extirq(struct tasklet_struct *t)
3349{
3350 struct skge_hw *hw = from_tasklet(hw, t, phy_task);
3351 int port;
3352
3353 for (port = 0; port < hw->ports; port++) {
3354 struct net_device *dev = hw->dev[port];
3355
3356 if (netif_running(dev)) {
3357 struct skge_port *skge = netdev_priv(dev);
3358
3359 spin_lock(&hw->phy_lock);
3360 if (!is_genesis(hw))
3361 yukon_phy_intr(skge);
3362 else if (hw->phy_type == SK_PHY_BCOM)
3363 bcom_phy_intr(skge);
3364 spin_unlock(&hw->phy_lock);
3365 }
3366 }
3367
3368 spin_lock_irq(&hw->hw_lock);
3369 hw->intr_mask |= IS_EXT_REG;
3370 skge_write32(hw, B0_IMSK, hw->intr_mask);
3371 skge_read32(hw, B0_IMSK);
3372 spin_unlock_irq(&hw->hw_lock);
3373}
3374
3375static irqreturn_t skge_intr(int irq, void *dev_id)
3376{
3377 struct skge_hw *hw = dev_id;
3378 u32 status;
3379 int handled = 0;
3380
3381 spin_lock(&hw->hw_lock);
3382 /* Reading this register masks IRQ */
3383 status = skge_read32(hw, B0_SP_ISRC);
3384 if (status == 0 || status == ~0)
3385 goto out;
3386
3387 handled = 1;
3388 status &= hw->intr_mask;
3389 if (status & IS_EXT_REG) {
3390 hw->intr_mask &= ~IS_EXT_REG;
3391 tasklet_schedule(&hw->phy_task);
3392 }
3393
3394 if (status & (IS_XA1_F|IS_R1_F)) {
3395 struct skge_port *skge = netdev_priv(hw->dev[0]);
3396 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3397 napi_schedule(&skge->napi);
3398 }
3399
3400 if (status & IS_PA_TO_TX1)
3401 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3402
3403 if (status & IS_PA_TO_RX1) {
3404 ++hw->dev[0]->stats.rx_over_errors;
3405 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3406 }
3407
3408
3409 if (status & IS_MAC1)
3410 skge_mac_intr(hw, 0);
3411
3412 if (hw->dev[1]) {
3413 struct skge_port *skge = netdev_priv(hw->dev[1]);
3414
3415 if (status & (IS_XA2_F|IS_R2_F)) {
3416 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3417 napi_schedule(&skge->napi);
3418 }
3419
3420 if (status & IS_PA_TO_RX2) {
3421 ++hw->dev[1]->stats.rx_over_errors;
3422 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3423 }
3424
3425 if (status & IS_PA_TO_TX2)
3426 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3427
3428 if (status & IS_MAC2)
3429 skge_mac_intr(hw, 1);
3430 }
3431
3432 if (status & IS_HW_ERR)
3433 skge_error_irq(hw);
3434out:
3435 skge_write32(hw, B0_IMSK, hw->intr_mask);
3436 skge_read32(hw, B0_IMSK);
3437 spin_unlock(&hw->hw_lock);
3438
3439 return IRQ_RETVAL(handled);
3440}
3441
3442#ifdef CONFIG_NET_POLL_CONTROLLER
3443static void skge_netpoll(struct net_device *dev)
3444{
3445 struct skge_port *skge = netdev_priv(dev);
3446
3447 disable_irq(dev->irq);
3448 skge_intr(dev->irq, skge->hw);
3449 enable_irq(dev->irq);
3450}
3451#endif
3452
3453static int skge_set_mac_address(struct net_device *dev, void *p)
3454{
3455 struct skge_port *skge = netdev_priv(dev);
3456 struct skge_hw *hw = skge->hw;
3457 unsigned port = skge->port;
3458 const struct sockaddr *addr = p;
3459 u16 ctrl;
3460
3461 if (!is_valid_ether_addr(addr->sa_data))
3462 return -EADDRNOTAVAIL;
3463
3464 eth_hw_addr_set(dev, addr->sa_data);
3465
3466 if (!netif_running(dev)) {
3467 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3468 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3469 } else {
3470 /* disable Rx */
3471 spin_lock_bh(&hw->phy_lock);
3472 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3473 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3474
3475 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3476 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3477
3478 if (is_genesis(hw))
3479 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3480 else {
3481 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3482 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3483 }
3484
3485 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3486 spin_unlock_bh(&hw->phy_lock);
3487 }
3488
3489 return 0;
3490}
3491
3492static const struct {
3493 u8 id;
3494 const char *name;
3495} skge_chips[] = {
3496 { CHIP_ID_GENESIS, "Genesis" },
3497 { CHIP_ID_YUKON, "Yukon" },
3498 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3499 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3500};
3501
3502static const char *skge_board_name(const struct skge_hw *hw)
3503{
3504 int i;
3505 static char buf[16];
3506
3507 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3508 if (skge_chips[i].id == hw->chip_id)
3509 return skge_chips[i].name;
3510
3511 snprintf(buf, sizeof(buf), "chipid 0x%x", hw->chip_id);
3512 return buf;
3513}
3514
3515
3516/*
3517 * Setup the board data structure, but don't bring up
3518 * the port(s)
3519 */
3520static int skge_reset(struct skge_hw *hw)
3521{
3522 u32 reg;
3523 u16 ctst, pci_status;
3524 u8 t8, mac_cfg, pmd_type;
3525 int i;
3526
3527 ctst = skge_read16(hw, B0_CTST);
3528
3529 /* do a SW reset */
3530 skge_write8(hw, B0_CTST, CS_RST_SET);
3531 skge_write8(hw, B0_CTST, CS_RST_CLR);
3532
3533 /* clear PCI errors, if any */
3534 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3535 skge_write8(hw, B2_TST_CTRL2, 0);
3536
3537 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3538 pci_write_config_word(hw->pdev, PCI_STATUS,
3539 pci_status | PCI_STATUS_ERROR_BITS);
3540 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3541 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3542
3543 /* restore CLK_RUN bits (for Yukon-Lite) */
3544 skge_write16(hw, B0_CTST,
3545 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3546
3547 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3548 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3549 pmd_type = skge_read8(hw, B2_PMD_TYP);
3550 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3551
3552 switch (hw->chip_id) {
3553 case CHIP_ID_GENESIS:
3554#ifdef CONFIG_SKGE_GENESIS
3555 switch (hw->phy_type) {
3556 case SK_PHY_XMAC:
3557 hw->phy_addr = PHY_ADDR_XMAC;
3558 break;
3559 case SK_PHY_BCOM:
3560 hw->phy_addr = PHY_ADDR_BCOM;
3561 break;
3562 default:
3563 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3564 hw->phy_type);
3565 return -EOPNOTSUPP;
3566 }
3567 break;
3568#else
3569 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3570 return -EOPNOTSUPP;
3571#endif
3572
3573 case CHIP_ID_YUKON:
3574 case CHIP_ID_YUKON_LITE:
3575 case CHIP_ID_YUKON_LP:
3576 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3577 hw->copper = 1;
3578
3579 hw->phy_addr = PHY_ADDR_MARV;
3580 break;
3581
3582 default:
3583 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3584 hw->chip_id);
3585 return -EOPNOTSUPP;
3586 }
3587
3588 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3589 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3590 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3591
3592 /* read the adapters RAM size */
3593 t8 = skge_read8(hw, B2_E_0);
3594 if (is_genesis(hw)) {
3595 if (t8 == 3) {
3596 /* special case: 4 x 64k x 36, offset = 0x80000 */
3597 hw->ram_size = 0x100000;
3598 hw->ram_offset = 0x80000;
3599 } else
3600 hw->ram_size = t8 * 512;
3601 } else if (t8 == 0)
3602 hw->ram_size = 0x20000;
3603 else
3604 hw->ram_size = t8 * 4096;
3605
3606 hw->intr_mask = IS_HW_ERR;
3607
3608 /* Use PHY IRQ for all but fiber based Genesis board */
3609 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3610 hw->intr_mask |= IS_EXT_REG;
3611
3612 if (is_genesis(hw))
3613 genesis_init(hw);
3614 else {
3615 /* switch power to VCC (WA for VAUX problem) */
3616 skge_write8(hw, B0_POWER_CTRL,
3617 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3618
3619 /* avoid boards with stuck Hardware error bits */
3620 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3621 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3622 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3623 hw->intr_mask &= ~IS_HW_ERR;
3624 }
3625
3626 /* Clear PHY COMA */
3627 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3628 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3629 reg &= ~PCI_PHY_COMA;
3630 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3631 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3632
3633
3634 for (i = 0; i < hw->ports; i++) {
3635 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3636 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3637 }
3638 }
3639
3640 /* turn off hardware timer (unused) */
3641 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3642 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3643 skge_write8(hw, B0_LED, LED_STAT_ON);
3644
3645 /* enable the Tx Arbiters */
3646 for (i = 0; i < hw->ports; i++)
3647 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3648
3649 /* Initialize ram interface */
3650 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3651
3652 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3661 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3662 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3663 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3664
3665 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3666
3667 /* Set interrupt moderation for Transmit only
3668 * Receive interrupts avoided by NAPI
3669 */
3670 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3671 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3672 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3673
3674 /* Leave irq disabled until first port is brought up. */
3675 skge_write32(hw, B0_IMSK, 0);
3676
3677 for (i = 0; i < hw->ports; i++) {
3678 if (is_genesis(hw))
3679 genesis_reset(hw, i);
3680 else
3681 yukon_reset(hw, i);
3682 }
3683
3684 return 0;
3685}
3686
3687
3688#ifdef CONFIG_SKGE_DEBUG
3689
3690static struct dentry *skge_debug;
3691
3692static int skge_debug_show(struct seq_file *seq, void *v)
3693{
3694 struct net_device *dev = seq->private;
3695 const struct skge_port *skge = netdev_priv(dev);
3696 const struct skge_hw *hw = skge->hw;
3697 const struct skge_element *e;
3698
3699 if (!netif_running(dev))
3700 return -ENETDOWN;
3701
3702 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3703 skge_read32(hw, B0_IMSK));
3704
3705 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3706 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3707 const struct skge_tx_desc *t = e->desc;
3708 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3709 t->control, t->dma_hi, t->dma_lo, t->status,
3710 t->csum_offs, t->csum_write, t->csum_start);
3711 }
3712
3713 seq_puts(seq, "\nRx Ring:\n");
3714 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3715 const struct skge_rx_desc *r = e->desc;
3716
3717 if (r->control & BMU_OWN)
3718 break;
3719
3720 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3721 r->control, r->dma_hi, r->dma_lo, r->status,
3722 r->timestamp, r->csum1, r->csum1_start);
3723 }
3724
3725 return 0;
3726}
3727DEFINE_SHOW_ATTRIBUTE(skge_debug);
3728
3729/*
3730 * Use network device events to create/remove/rename
3731 * debugfs file entries
3732 */
3733static int skge_device_event(struct notifier_block *unused,
3734 unsigned long event, void *ptr)
3735{
3736 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3737 struct skge_port *skge;
3738
3739 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3740 goto done;
3741
3742 skge = netdev_priv(dev);
3743 switch (event) {
3744 case NETDEV_CHANGENAME:
3745 if (skge->debugfs)
3746 skge->debugfs = debugfs_rename(skge_debug,
3747 skge->debugfs,
3748 skge_debug, dev->name);
3749 break;
3750
3751 case NETDEV_GOING_DOWN:
3752 debugfs_remove(skge->debugfs);
3753 skge->debugfs = NULL;
3754 break;
3755
3756 case NETDEV_UP:
3757 skge->debugfs = debugfs_create_file(dev->name, 0444, skge_debug,
3758 dev, &skge_debug_fops);
3759 break;
3760 }
3761
3762done:
3763 return NOTIFY_DONE;
3764}
3765
3766static struct notifier_block skge_notifier = {
3767 .notifier_call = skge_device_event,
3768};
3769
3770
3771static __init void skge_debug_init(void)
3772{
3773 skge_debug = debugfs_create_dir("skge", NULL);
3774
3775 register_netdevice_notifier(&skge_notifier);
3776}
3777
3778static __exit void skge_debug_cleanup(void)
3779{
3780 if (skge_debug) {
3781 unregister_netdevice_notifier(&skge_notifier);
3782 debugfs_remove(skge_debug);
3783 skge_debug = NULL;
3784 }
3785}
3786
3787#else
3788#define skge_debug_init()
3789#define skge_debug_cleanup()
3790#endif
3791
3792static const struct net_device_ops skge_netdev_ops = {
3793 .ndo_open = skge_up,
3794 .ndo_stop = skge_down,
3795 .ndo_start_xmit = skge_xmit_frame,
3796 .ndo_eth_ioctl = skge_ioctl,
3797 .ndo_get_stats = skge_get_stats,
3798 .ndo_tx_timeout = skge_tx_timeout,
3799 .ndo_change_mtu = skge_change_mtu,
3800 .ndo_validate_addr = eth_validate_addr,
3801 .ndo_set_rx_mode = skge_set_multicast,
3802 .ndo_set_mac_address = skge_set_mac_address,
3803#ifdef CONFIG_NET_POLL_CONTROLLER
3804 .ndo_poll_controller = skge_netpoll,
3805#endif
3806};
3807
3808
3809/* Initialize network device */
3810static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3811 int highmem)
3812{
3813 struct skge_port *skge;
3814 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3815 u8 addr[ETH_ALEN];
3816
3817 if (!dev)
3818 return NULL;
3819
3820 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3821 dev->netdev_ops = &skge_netdev_ops;
3822 dev->ethtool_ops = &skge_ethtool_ops;
3823 dev->watchdog_timeo = TX_WATCHDOG;
3824 dev->irq = hw->pdev->irq;
3825
3826 /* MTU range: 60 - 9000 */
3827 dev->min_mtu = ETH_ZLEN;
3828 dev->max_mtu = ETH_JUMBO_MTU;
3829
3830 if (highmem)
3831 dev->features |= NETIF_F_HIGHDMA;
3832
3833 skge = netdev_priv(dev);
3834 netif_napi_add(dev, &skge->napi, skge_poll);
3835 skge->netdev = dev;
3836 skge->hw = hw;
3837 skge->msg_enable = netif_msg_init(debug, default_msg);
3838
3839 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3840 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3841
3842 /* Auto speed and flow control */
3843 skge->autoneg = AUTONEG_ENABLE;
3844 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3845 skge->duplex = -1;
3846 skge->speed = -1;
3847 skge->advertising = skge_supported_modes(hw);
3848
3849 if (device_can_wakeup(&hw->pdev->dev)) {
3850 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3851 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3852 }
3853
3854 hw->dev[port] = dev;
3855
3856 skge->port = port;
3857
3858 /* Only used for Genesis XMAC */
3859 if (is_genesis(hw))
3860 timer_setup(&skge->link_timer, xm_link_timer, 0);
3861 else {
3862 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3863 NETIF_F_RXCSUM;
3864 dev->features |= dev->hw_features;
3865 }
3866
3867 /* read the mac address */
3868 memcpy_fromio(addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3869 eth_hw_addr_set(dev, addr);
3870
3871 return dev;
3872}
3873
3874static void skge_show_addr(struct net_device *dev)
3875{
3876 const struct skge_port *skge = netdev_priv(dev);
3877
3878 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3879}
3880
3881static int only_32bit_dma;
3882
3883static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3884{
3885 struct net_device *dev, *dev1;
3886 struct skge_hw *hw;
3887 int err, using_dac = 0;
3888
3889 err = pci_enable_device(pdev);
3890 if (err) {
3891 dev_err(&pdev->dev, "cannot enable PCI device\n");
3892 goto err_out;
3893 }
3894
3895 err = pci_request_regions(pdev, DRV_NAME);
3896 if (err) {
3897 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3898 goto err_out_disable_pdev;
3899 }
3900
3901 pci_set_master(pdev);
3902
3903 if (!only_32bit_dma && !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
3904 using_dac = 1;
3905 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
3906 } else if (!(err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))) {
3907 using_dac = 0;
3908 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3909 }
3910
3911 if (err) {
3912 dev_err(&pdev->dev, "no usable DMA configuration\n");
3913 goto err_out_free_regions;
3914 }
3915
3916#ifdef __BIG_ENDIAN
3917 /* byte swap descriptors in hardware */
3918 {
3919 u32 reg;
3920
3921 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3922 reg |= PCI_REV_DESC;
3923 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3924 }
3925#endif
3926
3927 err = -ENOMEM;
3928 /* space for skge@pci:0000:04:00.0 */
3929 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3930 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3931 if (!hw)
3932 goto err_out_free_regions;
3933
3934 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3935
3936 hw->pdev = pdev;
3937 spin_lock_init(&hw->hw_lock);
3938 spin_lock_init(&hw->phy_lock);
3939 tasklet_setup(&hw->phy_task, skge_extirq);
3940
3941 hw->regs = ioremap(pci_resource_start(pdev, 0), 0x4000);
3942 if (!hw->regs) {
3943 dev_err(&pdev->dev, "cannot map device registers\n");
3944 goto err_out_free_hw;
3945 }
3946
3947 err = skge_reset(hw);
3948 if (err)
3949 goto err_out_iounmap;
3950
3951 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3952 DRV_VERSION,
3953 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3954 skge_board_name(hw), hw->chip_rev);
3955
3956 dev = skge_devinit(hw, 0, using_dac);
3957 if (!dev) {
3958 err = -ENOMEM;
3959 goto err_out_led_off;
3960 }
3961
3962 /* Some motherboards are broken and has zero in ROM. */
3963 if (!is_valid_ether_addr(dev->dev_addr))
3964 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3965
3966 err = register_netdev(dev);
3967 if (err) {
3968 dev_err(&pdev->dev, "cannot register net device\n");
3969 goto err_out_free_netdev;
3970 }
3971
3972 skge_show_addr(dev);
3973
3974 if (hw->ports > 1) {
3975 dev1 = skge_devinit(hw, 1, using_dac);
3976 if (!dev1) {
3977 err = -ENOMEM;
3978 goto err_out_unregister;
3979 }
3980
3981 err = register_netdev(dev1);
3982 if (err) {
3983 dev_err(&pdev->dev, "cannot register second net device\n");
3984 goto err_out_free_dev1;
3985 }
3986
3987 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
3988 hw->irq_name, hw);
3989 if (err) {
3990 dev_err(&pdev->dev, "cannot assign irq %d\n",
3991 pdev->irq);
3992 goto err_out_unregister_dev1;
3993 }
3994
3995 skge_show_addr(dev1);
3996 }
3997 pci_set_drvdata(pdev, hw);
3998
3999 return 0;
4000
4001err_out_unregister_dev1:
4002 unregister_netdev(dev1);
4003err_out_free_dev1:
4004 free_netdev(dev1);
4005err_out_unregister:
4006 unregister_netdev(dev);
4007err_out_free_netdev:
4008 free_netdev(dev);
4009err_out_led_off:
4010 skge_write16(hw, B0_LED, LED_STAT_OFF);
4011err_out_iounmap:
4012 iounmap(hw->regs);
4013err_out_free_hw:
4014 kfree(hw);
4015err_out_free_regions:
4016 pci_release_regions(pdev);
4017err_out_disable_pdev:
4018 pci_disable_device(pdev);
4019err_out:
4020 return err;
4021}
4022
4023static void skge_remove(struct pci_dev *pdev)
4024{
4025 struct skge_hw *hw = pci_get_drvdata(pdev);
4026 struct net_device *dev0, *dev1;
4027
4028 if (!hw)
4029 return;
4030
4031 dev1 = hw->dev[1];
4032 if (dev1)
4033 unregister_netdev(dev1);
4034 dev0 = hw->dev[0];
4035 unregister_netdev(dev0);
4036
4037 tasklet_kill(&hw->phy_task);
4038
4039 spin_lock_irq(&hw->hw_lock);
4040 hw->intr_mask = 0;
4041
4042 if (hw->ports > 1) {
4043 skge_write32(hw, B0_IMSK, 0);
4044 skge_read32(hw, B0_IMSK);
4045 }
4046 spin_unlock_irq(&hw->hw_lock);
4047
4048 skge_write16(hw, B0_LED, LED_STAT_OFF);
4049 skge_write8(hw, B0_CTST, CS_RST_SET);
4050
4051 if (hw->ports > 1)
4052 free_irq(pdev->irq, hw);
4053 pci_release_regions(pdev);
4054 pci_disable_device(pdev);
4055 if (dev1)
4056 free_netdev(dev1);
4057 free_netdev(dev0);
4058
4059 iounmap(hw->regs);
4060 kfree(hw);
4061}
4062
4063#ifdef CONFIG_PM_SLEEP
4064static int skge_suspend(struct device *dev)
4065{
4066 struct skge_hw *hw = dev_get_drvdata(dev);
4067 int i;
4068
4069 if (!hw)
4070 return 0;
4071
4072 for (i = 0; i < hw->ports; i++) {
4073 struct net_device *dev = hw->dev[i];
4074 struct skge_port *skge = netdev_priv(dev);
4075
4076 if (netif_running(dev))
4077 skge_down(dev);
4078
4079 if (skge->wol)
4080 skge_wol_init(skge);
4081 }
4082
4083 skge_write32(hw, B0_IMSK, 0);
4084
4085 return 0;
4086}
4087
4088static int skge_resume(struct device *dev)
4089{
4090 struct skge_hw *hw = dev_get_drvdata(dev);
4091 int i, err;
4092
4093 if (!hw)
4094 return 0;
4095
4096 err = skge_reset(hw);
4097 if (err)
4098 goto out;
4099
4100 for (i = 0; i < hw->ports; i++) {
4101 struct net_device *dev = hw->dev[i];
4102
4103 if (netif_running(dev)) {
4104 err = skge_up(dev);
4105
4106 if (err) {
4107 netdev_err(dev, "could not up: %d\n", err);
4108 dev_close(dev);
4109 goto out;
4110 }
4111 }
4112 }
4113out:
4114 return err;
4115}
4116
4117static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4118#define SKGE_PM_OPS (&skge_pm_ops)
4119
4120#else
4121
4122#define SKGE_PM_OPS NULL
4123#endif /* CONFIG_PM_SLEEP */
4124
4125static void skge_shutdown(struct pci_dev *pdev)
4126{
4127 struct skge_hw *hw = pci_get_drvdata(pdev);
4128 int i;
4129
4130 if (!hw)
4131 return;
4132
4133 for (i = 0; i < hw->ports; i++) {
4134 struct net_device *dev = hw->dev[i];
4135 struct skge_port *skge = netdev_priv(dev);
4136
4137 if (skge->wol)
4138 skge_wol_init(skge);
4139 }
4140
4141 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4142 pci_set_power_state(pdev, PCI_D3hot);
4143}
4144
4145static struct pci_driver skge_driver = {
4146 .name = DRV_NAME,
4147 .id_table = skge_id_table,
4148 .probe = skge_probe,
4149 .remove = skge_remove,
4150 .shutdown = skge_shutdown,
4151 .driver.pm = SKGE_PM_OPS,
4152};
4153
4154static const struct dmi_system_id skge_32bit_dma_boards[] = {
4155 {
4156 .ident = "Gigabyte nForce boards",
4157 .matches = {
4158 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4159 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4160 },
4161 },
4162 {
4163 .ident = "ASUS P5NSLI",
4164 .matches = {
4165 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4166 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4167 },
4168 },
4169 {
4170 .ident = "FUJITSU SIEMENS A8NE-FM",
4171 .matches = {
4172 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4173 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4174 },
4175 },
4176 {}
4177};
4178
4179static int __init skge_init_module(void)
4180{
4181 if (dmi_check_system(skge_32bit_dma_boards))
4182 only_32bit_dma = 1;
4183 skge_debug_init();
4184 return pci_register_driver(&skge_driver);
4185}
4186
4187static void __exit skge_cleanup_module(void)
4188{
4189 pci_unregister_driver(&skge_driver);
4190 skge_debug_cleanup();
4191}
4192
4193module_init(skge_init_module);
4194module_exit(skge_cleanup_module);
1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
28#include <linux/in.h>
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/moduleparam.h>
32#include <linux/netdevice.h>
33#include <linux/etherdevice.h>
34#include <linux/ethtool.h>
35#include <linux/pci.h>
36#include <linux/if_vlan.h>
37#include <linux/ip.h>
38#include <linux/delay.h>
39#include <linux/crc32.h>
40#include <linux/dma-mapping.h>
41#include <linux/debugfs.h>
42#include <linux/sched.h>
43#include <linux/seq_file.h>
44#include <linux/mii.h>
45#include <linux/slab.h>
46#include <linux/dmi.h>
47#include <linux/prefetch.h>
48#include <asm/irq.h>
49
50#include "skge.h"
51
52#define DRV_NAME "skge"
53#define DRV_VERSION "1.14"
54
55#define DEFAULT_TX_RING_SIZE 128
56#define DEFAULT_RX_RING_SIZE 512
57#define MAX_TX_RING_SIZE 1024
58#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
59#define MAX_RX_RING_SIZE 4096
60#define RX_COPY_THRESHOLD 128
61#define RX_BUF_SIZE 1536
62#define PHY_RETRIES 1000
63#define ETH_JUMBO_MTU 9000
64#define TX_WATCHDOG (5 * HZ)
65#define NAPI_WEIGHT 64
66#define BLINK_MS 250
67#define LINK_HZ HZ
68
69#define SKGE_EEPROM_MAGIC 0x9933aabb
70
71
72MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
73MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
74MODULE_LICENSE("GPL");
75MODULE_VERSION(DRV_VERSION);
76
77static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
78 NETIF_MSG_LINK | NETIF_MSG_IFUP |
79 NETIF_MSG_IFDOWN);
80
81static int debug = -1; /* defaults above */
82module_param(debug, int, 0);
83MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
84
85static const struct pci_device_id skge_id_table[] = {
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x1700) }, /* 3Com 3C940 */
87 { PCI_DEVICE(PCI_VENDOR_ID_3COM, 0x80EB) }, /* 3Com 3C940B */
88#ifdef CONFIG_SKGE_GENESIS
89 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4300) }, /* SK-9xx */
90#endif
91 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x4320) }, /* SK-98xx V2.0 */
92 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* D-Link DGE-530T (rev.B) */
93 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4c00) }, /* D-Link DGE-530T */
94 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302) }, /* D-Link DGE-530T Rev C1 */
95 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, /* Marvell Yukon 88E8001/8003/8010 */
96 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
97 { PCI_DEVICE(PCI_VENDOR_ID_CNET, 0x434E) }, /* CNet PowerG-2000 */
98 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, 0x1064) }, /* Linksys EG1064 v2 */
99 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 }, /* Linksys EG1032 v2 */
100 { 0 }
101};
102MODULE_DEVICE_TABLE(pci, skge_id_table);
103
104static int skge_up(struct net_device *dev);
105static int skge_down(struct net_device *dev);
106static void skge_phy_reset(struct skge_port *skge);
107static void skge_tx_clean(struct net_device *dev);
108static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
109static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
110static void genesis_get_stats(struct skge_port *skge, u64 *data);
111static void yukon_get_stats(struct skge_port *skge, u64 *data);
112static void yukon_init(struct skge_hw *hw, int port);
113static void genesis_mac_init(struct skge_hw *hw, int port);
114static void genesis_link_up(struct skge_port *skge);
115static void skge_set_multicast(struct net_device *dev);
116static irqreturn_t skge_intr(int irq, void *dev_id);
117
118/* Avoid conditionals by using array */
119static const int txqaddr[] = { Q_XA1, Q_XA2 };
120static const int rxqaddr[] = { Q_R1, Q_R2 };
121static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
122static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
123static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
124static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
125
126static inline bool is_genesis(const struct skge_hw *hw)
127{
128#ifdef CONFIG_SKGE_GENESIS
129 return hw->chip_id == CHIP_ID_GENESIS;
130#else
131 return false;
132#endif
133}
134
135static int skge_get_regs_len(struct net_device *dev)
136{
137 return 0x4000;
138}
139
140/*
141 * Returns copy of whole control register region
142 * Note: skip RAM address register because accessing it will
143 * cause bus hangs!
144 */
145static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
146 void *p)
147{
148 const struct skge_port *skge = netdev_priv(dev);
149 const void __iomem *io = skge->hw->regs;
150
151 regs->version = 1;
152 memset(p, 0, regs->len);
153 memcpy_fromio(p, io, B3_RAM_ADDR);
154
155 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
156 regs->len - B3_RI_WTO_R1);
157}
158
159/* Wake on Lan only supported on Yukon chips with rev 1 or above */
160static u32 wol_supported(const struct skge_hw *hw)
161{
162 if (is_genesis(hw))
163 return 0;
164
165 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
166 return 0;
167
168 return WAKE_MAGIC | WAKE_PHY;
169}
170
171static void skge_wol_init(struct skge_port *skge)
172{
173 struct skge_hw *hw = skge->hw;
174 int port = skge->port;
175 u16 ctrl;
176
177 skge_write16(hw, B0_CTST, CS_RST_CLR);
178 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
179
180 /* Turn on Vaux */
181 skge_write8(hw, B0_POWER_CTRL,
182 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
183
184 /* WA code for COMA mode -- clear PHY reset */
185 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
186 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
187 u32 reg = skge_read32(hw, B2_GP_IO);
188 reg |= GP_DIR_9;
189 reg &= ~GP_IO_9;
190 skge_write32(hw, B2_GP_IO, reg);
191 }
192
193 skge_write32(hw, SK_REG(port, GPHY_CTRL),
194 GPC_DIS_SLEEP |
195 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
196 GPC_ANEG_1 | GPC_RST_SET);
197
198 skge_write32(hw, SK_REG(port, GPHY_CTRL),
199 GPC_DIS_SLEEP |
200 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
201 GPC_ANEG_1 | GPC_RST_CLR);
202
203 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
204
205 /* Force to 10/100 skge_reset will re-enable on resume */
206 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
207 (PHY_AN_100FULL | PHY_AN_100HALF |
208 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
209 /* no 1000 HD/FD */
210 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
211 gm_phy_write(hw, port, PHY_MARV_CTRL,
212 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
213 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
214
215
216 /* Set GMAC to no flow control and auto update for speed/duplex */
217 gma_write16(hw, port, GM_GP_CTRL,
218 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
219 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
220
221 /* Set WOL address */
222 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
223 skge->netdev->dev_addr, ETH_ALEN);
224
225 /* Turn on appropriate WOL control bits */
226 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
227 ctrl = 0;
228 if (skge->wol & WAKE_PHY)
229 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
230 else
231 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
232
233 if (skge->wol & WAKE_MAGIC)
234 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
235 else
236 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
237
238 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
239 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
240
241 /* block receiver */
242 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
243}
244
245static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
246{
247 struct skge_port *skge = netdev_priv(dev);
248
249 wol->supported = wol_supported(skge->hw);
250 wol->wolopts = skge->wol;
251}
252
253static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
254{
255 struct skge_port *skge = netdev_priv(dev);
256 struct skge_hw *hw = skge->hw;
257
258 if ((wol->wolopts & ~wol_supported(hw)) ||
259 !device_can_wakeup(&hw->pdev->dev))
260 return -EOPNOTSUPP;
261
262 skge->wol = wol->wolopts;
263
264 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
265
266 return 0;
267}
268
269/* Determine supported/advertised modes based on hardware.
270 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
271 */
272static u32 skge_supported_modes(const struct skge_hw *hw)
273{
274 u32 supported;
275
276 if (hw->copper) {
277 supported = (SUPPORTED_10baseT_Half |
278 SUPPORTED_10baseT_Full |
279 SUPPORTED_100baseT_Half |
280 SUPPORTED_100baseT_Full |
281 SUPPORTED_1000baseT_Half |
282 SUPPORTED_1000baseT_Full |
283 SUPPORTED_Autoneg |
284 SUPPORTED_TP);
285
286 if (is_genesis(hw))
287 supported &= ~(SUPPORTED_10baseT_Half |
288 SUPPORTED_10baseT_Full |
289 SUPPORTED_100baseT_Half |
290 SUPPORTED_100baseT_Full);
291
292 else if (hw->chip_id == CHIP_ID_YUKON)
293 supported &= ~SUPPORTED_1000baseT_Half;
294 } else
295 supported = (SUPPORTED_1000baseT_Full |
296 SUPPORTED_1000baseT_Half |
297 SUPPORTED_FIBRE |
298 SUPPORTED_Autoneg);
299
300 return supported;
301}
302
303static int skge_get_settings(struct net_device *dev,
304 struct ethtool_cmd *ecmd)
305{
306 struct skge_port *skge = netdev_priv(dev);
307 struct skge_hw *hw = skge->hw;
308
309 ecmd->transceiver = XCVR_INTERNAL;
310 ecmd->supported = skge_supported_modes(hw);
311
312 if (hw->copper) {
313 ecmd->port = PORT_TP;
314 ecmd->phy_address = hw->phy_addr;
315 } else
316 ecmd->port = PORT_FIBRE;
317
318 ecmd->advertising = skge->advertising;
319 ecmd->autoneg = skge->autoneg;
320 ethtool_cmd_speed_set(ecmd, skge->speed);
321 ecmd->duplex = skge->duplex;
322 return 0;
323}
324
325static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
326{
327 struct skge_port *skge = netdev_priv(dev);
328 const struct skge_hw *hw = skge->hw;
329 u32 supported = skge_supported_modes(hw);
330 int err = 0;
331
332 if (ecmd->autoneg == AUTONEG_ENABLE) {
333 ecmd->advertising = supported;
334 skge->duplex = -1;
335 skge->speed = -1;
336 } else {
337 u32 setting;
338 u32 speed = ethtool_cmd_speed(ecmd);
339
340 switch (speed) {
341 case SPEED_1000:
342 if (ecmd->duplex == DUPLEX_FULL)
343 setting = SUPPORTED_1000baseT_Full;
344 else if (ecmd->duplex == DUPLEX_HALF)
345 setting = SUPPORTED_1000baseT_Half;
346 else
347 return -EINVAL;
348 break;
349 case SPEED_100:
350 if (ecmd->duplex == DUPLEX_FULL)
351 setting = SUPPORTED_100baseT_Full;
352 else if (ecmd->duplex == DUPLEX_HALF)
353 setting = SUPPORTED_100baseT_Half;
354 else
355 return -EINVAL;
356 break;
357
358 case SPEED_10:
359 if (ecmd->duplex == DUPLEX_FULL)
360 setting = SUPPORTED_10baseT_Full;
361 else if (ecmd->duplex == DUPLEX_HALF)
362 setting = SUPPORTED_10baseT_Half;
363 else
364 return -EINVAL;
365 break;
366 default:
367 return -EINVAL;
368 }
369
370 if ((setting & supported) == 0)
371 return -EINVAL;
372
373 skge->speed = speed;
374 skge->duplex = ecmd->duplex;
375 }
376
377 skge->autoneg = ecmd->autoneg;
378 skge->advertising = ecmd->advertising;
379
380 if (netif_running(dev)) {
381 skge_down(dev);
382 err = skge_up(dev);
383 if (err) {
384 dev_close(dev);
385 return err;
386 }
387 }
388
389 return 0;
390}
391
392static void skge_get_drvinfo(struct net_device *dev,
393 struct ethtool_drvinfo *info)
394{
395 struct skge_port *skge = netdev_priv(dev);
396
397 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
398 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
399 strlcpy(info->bus_info, pci_name(skge->hw->pdev),
400 sizeof(info->bus_info));
401}
402
403static const struct skge_stat {
404 char name[ETH_GSTRING_LEN];
405 u16 xmac_offset;
406 u16 gma_offset;
407} skge_stats[] = {
408 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
409 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
410
411 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
412 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
413 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
414 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
415 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
416 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
417 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
418 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
419
420 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
421 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
422 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
423 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
424 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
425 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
426
427 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
428 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
429 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
430 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
431 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
432};
433
434static int skge_get_sset_count(struct net_device *dev, int sset)
435{
436 switch (sset) {
437 case ETH_SS_STATS:
438 return ARRAY_SIZE(skge_stats);
439 default:
440 return -EOPNOTSUPP;
441 }
442}
443
444static void skge_get_ethtool_stats(struct net_device *dev,
445 struct ethtool_stats *stats, u64 *data)
446{
447 struct skge_port *skge = netdev_priv(dev);
448
449 if (is_genesis(skge->hw))
450 genesis_get_stats(skge, data);
451 else
452 yukon_get_stats(skge, data);
453}
454
455/* Use hardware MIB variables for critical path statistics and
456 * transmit feedback not reported at interrupt.
457 * Other errors are accounted for in interrupt handler.
458 */
459static struct net_device_stats *skge_get_stats(struct net_device *dev)
460{
461 struct skge_port *skge = netdev_priv(dev);
462 u64 data[ARRAY_SIZE(skge_stats)];
463
464 if (is_genesis(skge->hw))
465 genesis_get_stats(skge, data);
466 else
467 yukon_get_stats(skge, data);
468
469 dev->stats.tx_bytes = data[0];
470 dev->stats.rx_bytes = data[1];
471 dev->stats.tx_packets = data[2] + data[4] + data[6];
472 dev->stats.rx_packets = data[3] + data[5] + data[7];
473 dev->stats.multicast = data[3] + data[5];
474 dev->stats.collisions = data[10];
475 dev->stats.tx_aborted_errors = data[12];
476
477 return &dev->stats;
478}
479
480static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
481{
482 int i;
483
484 switch (stringset) {
485 case ETH_SS_STATS:
486 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
487 memcpy(data + i * ETH_GSTRING_LEN,
488 skge_stats[i].name, ETH_GSTRING_LEN);
489 break;
490 }
491}
492
493static void skge_get_ring_param(struct net_device *dev,
494 struct ethtool_ringparam *p)
495{
496 struct skge_port *skge = netdev_priv(dev);
497
498 p->rx_max_pending = MAX_RX_RING_SIZE;
499 p->tx_max_pending = MAX_TX_RING_SIZE;
500
501 p->rx_pending = skge->rx_ring.count;
502 p->tx_pending = skge->tx_ring.count;
503}
504
505static int skge_set_ring_param(struct net_device *dev,
506 struct ethtool_ringparam *p)
507{
508 struct skge_port *skge = netdev_priv(dev);
509 int err = 0;
510
511 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
512 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
513 return -EINVAL;
514
515 skge->rx_ring.count = p->rx_pending;
516 skge->tx_ring.count = p->tx_pending;
517
518 if (netif_running(dev)) {
519 skge_down(dev);
520 err = skge_up(dev);
521 if (err)
522 dev_close(dev);
523 }
524
525 return err;
526}
527
528static u32 skge_get_msglevel(struct net_device *netdev)
529{
530 struct skge_port *skge = netdev_priv(netdev);
531 return skge->msg_enable;
532}
533
534static void skge_set_msglevel(struct net_device *netdev, u32 value)
535{
536 struct skge_port *skge = netdev_priv(netdev);
537 skge->msg_enable = value;
538}
539
540static int skge_nway_reset(struct net_device *dev)
541{
542 struct skge_port *skge = netdev_priv(dev);
543
544 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
545 return -EINVAL;
546
547 skge_phy_reset(skge);
548 return 0;
549}
550
551static void skge_get_pauseparam(struct net_device *dev,
552 struct ethtool_pauseparam *ecmd)
553{
554 struct skge_port *skge = netdev_priv(dev);
555
556 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
557 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
558 ecmd->tx_pause = (ecmd->rx_pause ||
559 (skge->flow_control == FLOW_MODE_LOC_SEND));
560
561 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
562}
563
564static int skge_set_pauseparam(struct net_device *dev,
565 struct ethtool_pauseparam *ecmd)
566{
567 struct skge_port *skge = netdev_priv(dev);
568 struct ethtool_pauseparam old;
569 int err = 0;
570
571 skge_get_pauseparam(dev, &old);
572
573 if (ecmd->autoneg != old.autoneg)
574 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
575 else {
576 if (ecmd->rx_pause && ecmd->tx_pause)
577 skge->flow_control = FLOW_MODE_SYMMETRIC;
578 else if (ecmd->rx_pause && !ecmd->tx_pause)
579 skge->flow_control = FLOW_MODE_SYM_OR_REM;
580 else if (!ecmd->rx_pause && ecmd->tx_pause)
581 skge->flow_control = FLOW_MODE_LOC_SEND;
582 else
583 skge->flow_control = FLOW_MODE_NONE;
584 }
585
586 if (netif_running(dev)) {
587 skge_down(dev);
588 err = skge_up(dev);
589 if (err) {
590 dev_close(dev);
591 return err;
592 }
593 }
594
595 return 0;
596}
597
598/* Chip internal frequency for clock calculations */
599static inline u32 hwkhz(const struct skge_hw *hw)
600{
601 return is_genesis(hw) ? 53125 : 78125;
602}
603
604/* Chip HZ to microseconds */
605static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
606{
607 return (ticks * 1000) / hwkhz(hw);
608}
609
610/* Microseconds to chip HZ */
611static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
612{
613 return hwkhz(hw) * usec / 1000;
614}
615
616static int skge_get_coalesce(struct net_device *dev,
617 struct ethtool_coalesce *ecmd)
618{
619 struct skge_port *skge = netdev_priv(dev);
620 struct skge_hw *hw = skge->hw;
621 int port = skge->port;
622
623 ecmd->rx_coalesce_usecs = 0;
624 ecmd->tx_coalesce_usecs = 0;
625
626 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
627 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
628 u32 msk = skge_read32(hw, B2_IRQM_MSK);
629
630 if (msk & rxirqmask[port])
631 ecmd->rx_coalesce_usecs = delay;
632 if (msk & txirqmask[port])
633 ecmd->tx_coalesce_usecs = delay;
634 }
635
636 return 0;
637}
638
639/* Note: interrupt timer is per board, but can turn on/off per port */
640static int skge_set_coalesce(struct net_device *dev,
641 struct ethtool_coalesce *ecmd)
642{
643 struct skge_port *skge = netdev_priv(dev);
644 struct skge_hw *hw = skge->hw;
645 int port = skge->port;
646 u32 msk = skge_read32(hw, B2_IRQM_MSK);
647 u32 delay = 25;
648
649 if (ecmd->rx_coalesce_usecs == 0)
650 msk &= ~rxirqmask[port];
651 else if (ecmd->rx_coalesce_usecs < 25 ||
652 ecmd->rx_coalesce_usecs > 33333)
653 return -EINVAL;
654 else {
655 msk |= rxirqmask[port];
656 delay = ecmd->rx_coalesce_usecs;
657 }
658
659 if (ecmd->tx_coalesce_usecs == 0)
660 msk &= ~txirqmask[port];
661 else if (ecmd->tx_coalesce_usecs < 25 ||
662 ecmd->tx_coalesce_usecs > 33333)
663 return -EINVAL;
664 else {
665 msk |= txirqmask[port];
666 delay = min(delay, ecmd->rx_coalesce_usecs);
667 }
668
669 skge_write32(hw, B2_IRQM_MSK, msk);
670 if (msk == 0)
671 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
672 else {
673 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
674 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
675 }
676 return 0;
677}
678
679enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
680static void skge_led(struct skge_port *skge, enum led_mode mode)
681{
682 struct skge_hw *hw = skge->hw;
683 int port = skge->port;
684
685 spin_lock_bh(&hw->phy_lock);
686 if (is_genesis(hw)) {
687 switch (mode) {
688 case LED_MODE_OFF:
689 if (hw->phy_type == SK_PHY_BCOM)
690 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
691 else {
692 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
693 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
694 }
695 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
696 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
697 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
698 break;
699
700 case LED_MODE_ON:
701 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
702 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
703
704 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
705 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
706
707 break;
708
709 case LED_MODE_TST:
710 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
711 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
712 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
713
714 if (hw->phy_type == SK_PHY_BCOM)
715 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
716 else {
717 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
718 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
719 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
720 }
721
722 }
723 } else {
724 switch (mode) {
725 case LED_MODE_OFF:
726 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
727 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
728 PHY_M_LED_MO_DUP(MO_LED_OFF) |
729 PHY_M_LED_MO_10(MO_LED_OFF) |
730 PHY_M_LED_MO_100(MO_LED_OFF) |
731 PHY_M_LED_MO_1000(MO_LED_OFF) |
732 PHY_M_LED_MO_RX(MO_LED_OFF));
733 break;
734 case LED_MODE_ON:
735 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
736 PHY_M_LED_PULS_DUR(PULS_170MS) |
737 PHY_M_LED_BLINK_RT(BLINK_84MS) |
738 PHY_M_LEDC_TX_CTRL |
739 PHY_M_LEDC_DP_CTRL);
740
741 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
742 PHY_M_LED_MO_RX(MO_LED_OFF) |
743 (skge->speed == SPEED_100 ?
744 PHY_M_LED_MO_100(MO_LED_ON) : 0));
745 break;
746 case LED_MODE_TST:
747 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
748 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
749 PHY_M_LED_MO_DUP(MO_LED_ON) |
750 PHY_M_LED_MO_10(MO_LED_ON) |
751 PHY_M_LED_MO_100(MO_LED_ON) |
752 PHY_M_LED_MO_1000(MO_LED_ON) |
753 PHY_M_LED_MO_RX(MO_LED_ON));
754 }
755 }
756 spin_unlock_bh(&hw->phy_lock);
757}
758
759/* blink LED's for finding board */
760static int skge_set_phys_id(struct net_device *dev,
761 enum ethtool_phys_id_state state)
762{
763 struct skge_port *skge = netdev_priv(dev);
764
765 switch (state) {
766 case ETHTOOL_ID_ACTIVE:
767 return 2; /* cycle on/off twice per second */
768
769 case ETHTOOL_ID_ON:
770 skge_led(skge, LED_MODE_TST);
771 break;
772
773 case ETHTOOL_ID_OFF:
774 skge_led(skge, LED_MODE_OFF);
775 break;
776
777 case ETHTOOL_ID_INACTIVE:
778 /* back to regular LED state */
779 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
780 }
781
782 return 0;
783}
784
785static int skge_get_eeprom_len(struct net_device *dev)
786{
787 struct skge_port *skge = netdev_priv(dev);
788 u32 reg2;
789
790 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
791 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
792}
793
794static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
795{
796 u32 val;
797
798 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
799
800 do {
801 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
802 } while (!(offset & PCI_VPD_ADDR_F));
803
804 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
805 return val;
806}
807
808static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
809{
810 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
811 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
812 offset | PCI_VPD_ADDR_F);
813
814 do {
815 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
816 } while (offset & PCI_VPD_ADDR_F);
817}
818
819static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
820 u8 *data)
821{
822 struct skge_port *skge = netdev_priv(dev);
823 struct pci_dev *pdev = skge->hw->pdev;
824 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
825 int length = eeprom->len;
826 u16 offset = eeprom->offset;
827
828 if (!cap)
829 return -EINVAL;
830
831 eeprom->magic = SKGE_EEPROM_MAGIC;
832
833 while (length > 0) {
834 u32 val = skge_vpd_read(pdev, cap, offset);
835 int n = min_t(int, length, sizeof(val));
836
837 memcpy(data, &val, n);
838 length -= n;
839 data += n;
840 offset += n;
841 }
842 return 0;
843}
844
845static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
846 u8 *data)
847{
848 struct skge_port *skge = netdev_priv(dev);
849 struct pci_dev *pdev = skge->hw->pdev;
850 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
851 int length = eeprom->len;
852 u16 offset = eeprom->offset;
853
854 if (!cap)
855 return -EINVAL;
856
857 if (eeprom->magic != SKGE_EEPROM_MAGIC)
858 return -EINVAL;
859
860 while (length > 0) {
861 u32 val;
862 int n = min_t(int, length, sizeof(val));
863
864 if (n < sizeof(val))
865 val = skge_vpd_read(pdev, cap, offset);
866 memcpy(&val, data, n);
867
868 skge_vpd_write(pdev, cap, offset, val);
869
870 length -= n;
871 data += n;
872 offset += n;
873 }
874 return 0;
875}
876
877static const struct ethtool_ops skge_ethtool_ops = {
878 .get_settings = skge_get_settings,
879 .set_settings = skge_set_settings,
880 .get_drvinfo = skge_get_drvinfo,
881 .get_regs_len = skge_get_regs_len,
882 .get_regs = skge_get_regs,
883 .get_wol = skge_get_wol,
884 .set_wol = skge_set_wol,
885 .get_msglevel = skge_get_msglevel,
886 .set_msglevel = skge_set_msglevel,
887 .nway_reset = skge_nway_reset,
888 .get_link = ethtool_op_get_link,
889 .get_eeprom_len = skge_get_eeprom_len,
890 .get_eeprom = skge_get_eeprom,
891 .set_eeprom = skge_set_eeprom,
892 .get_ringparam = skge_get_ring_param,
893 .set_ringparam = skge_set_ring_param,
894 .get_pauseparam = skge_get_pauseparam,
895 .set_pauseparam = skge_set_pauseparam,
896 .get_coalesce = skge_get_coalesce,
897 .set_coalesce = skge_set_coalesce,
898 .get_strings = skge_get_strings,
899 .set_phys_id = skge_set_phys_id,
900 .get_sset_count = skge_get_sset_count,
901 .get_ethtool_stats = skge_get_ethtool_stats,
902};
903
904/*
905 * Allocate ring elements and chain them together
906 * One-to-one association of board descriptors with ring elements
907 */
908static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
909{
910 struct skge_tx_desc *d;
911 struct skge_element *e;
912 int i;
913
914 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
915 if (!ring->start)
916 return -ENOMEM;
917
918 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
919 e->desc = d;
920 if (i == ring->count - 1) {
921 e->next = ring->start;
922 d->next_offset = base;
923 } else {
924 e->next = e + 1;
925 d->next_offset = base + (i+1) * sizeof(*d);
926 }
927 }
928 ring->to_use = ring->to_clean = ring->start;
929
930 return 0;
931}
932
933/* Allocate and setup a new buffer for receiving */
934static int skge_rx_setup(struct skge_port *skge, struct skge_element *e,
935 struct sk_buff *skb, unsigned int bufsize)
936{
937 struct skge_rx_desc *rd = e->desc;
938 dma_addr_t map;
939
940 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
941 PCI_DMA_FROMDEVICE);
942
943 if (pci_dma_mapping_error(skge->hw->pdev, map))
944 return -1;
945
946 rd->dma_lo = lower_32_bits(map);
947 rd->dma_hi = upper_32_bits(map);
948 e->skb = skb;
949 rd->csum1_start = ETH_HLEN;
950 rd->csum2_start = ETH_HLEN;
951 rd->csum1 = 0;
952 rd->csum2 = 0;
953
954 wmb();
955
956 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
957 dma_unmap_addr_set(e, mapaddr, map);
958 dma_unmap_len_set(e, maplen, bufsize);
959 return 0;
960}
961
962/* Resume receiving using existing skb,
963 * Note: DMA address is not changed by chip.
964 * MTU not changed while receiver active.
965 */
966static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
967{
968 struct skge_rx_desc *rd = e->desc;
969
970 rd->csum2 = 0;
971 rd->csum2_start = ETH_HLEN;
972
973 wmb();
974
975 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
976}
977
978
979/* Free all buffers in receive ring, assumes receiver stopped */
980static void skge_rx_clean(struct skge_port *skge)
981{
982 struct skge_hw *hw = skge->hw;
983 struct skge_ring *ring = &skge->rx_ring;
984 struct skge_element *e;
985
986 e = ring->start;
987 do {
988 struct skge_rx_desc *rd = e->desc;
989 rd->control = 0;
990 if (e->skb) {
991 pci_unmap_single(hw->pdev,
992 dma_unmap_addr(e, mapaddr),
993 dma_unmap_len(e, maplen),
994 PCI_DMA_FROMDEVICE);
995 dev_kfree_skb(e->skb);
996 e->skb = NULL;
997 }
998 } while ((e = e->next) != ring->start);
999}
1000
1001
1002/* Allocate buffers for receive ring
1003 * For receive: to_clean is next received frame.
1004 */
1005static int skge_rx_fill(struct net_device *dev)
1006{
1007 struct skge_port *skge = netdev_priv(dev);
1008 struct skge_ring *ring = &skge->rx_ring;
1009 struct skge_element *e;
1010
1011 e = ring->start;
1012 do {
1013 struct sk_buff *skb;
1014
1015 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1016 GFP_KERNEL);
1017 if (!skb)
1018 return -ENOMEM;
1019
1020 skb_reserve(skb, NET_IP_ALIGN);
1021 if (skge_rx_setup(skge, e, skb, skge->rx_buf_size) < 0) {
1022 dev_kfree_skb(skb);
1023 return -EIO;
1024 }
1025 } while ((e = e->next) != ring->start);
1026
1027 ring->to_clean = ring->start;
1028 return 0;
1029}
1030
1031static const char *skge_pause(enum pause_status status)
1032{
1033 switch (status) {
1034 case FLOW_STAT_NONE:
1035 return "none";
1036 case FLOW_STAT_REM_SEND:
1037 return "rx only";
1038 case FLOW_STAT_LOC_SEND:
1039 return "tx_only";
1040 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1041 return "both";
1042 default:
1043 return "indeterminated";
1044 }
1045}
1046
1047
1048static void skge_link_up(struct skge_port *skge)
1049{
1050 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1051 LED_BLK_OFF|LED_SYNC_OFF|LED_REG_ON);
1052
1053 netif_carrier_on(skge->netdev);
1054 netif_wake_queue(skge->netdev);
1055
1056 netif_info(skge, link, skge->netdev,
1057 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1058 skge->speed,
1059 skge->duplex == DUPLEX_FULL ? "full" : "half",
1060 skge_pause(skge->flow_status));
1061}
1062
1063static void skge_link_down(struct skge_port *skge)
1064{
1065 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
1066 netif_carrier_off(skge->netdev);
1067 netif_stop_queue(skge->netdev);
1068
1069 netif_info(skge, link, skge->netdev, "Link is down\n");
1070}
1071
1072static void xm_link_down(struct skge_hw *hw, int port)
1073{
1074 struct net_device *dev = hw->dev[port];
1075 struct skge_port *skge = netdev_priv(dev);
1076
1077 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1078
1079 if (netif_carrier_ok(dev))
1080 skge_link_down(skge);
1081}
1082
1083static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1084{
1085 int i;
1086
1087 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1088 *val = xm_read16(hw, port, XM_PHY_DATA);
1089
1090 if (hw->phy_type == SK_PHY_XMAC)
1091 goto ready;
1092
1093 for (i = 0; i < PHY_RETRIES; i++) {
1094 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1095 goto ready;
1096 udelay(1);
1097 }
1098
1099 return -ETIMEDOUT;
1100 ready:
1101 *val = xm_read16(hw, port, XM_PHY_DATA);
1102
1103 return 0;
1104}
1105
1106static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1107{
1108 u16 v = 0;
1109 if (__xm_phy_read(hw, port, reg, &v))
1110 pr_warn("%s: phy read timed out\n", hw->dev[port]->name);
1111 return v;
1112}
1113
1114static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1115{
1116 int i;
1117
1118 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1119 for (i = 0; i < PHY_RETRIES; i++) {
1120 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1121 goto ready;
1122 udelay(1);
1123 }
1124 return -EIO;
1125
1126 ready:
1127 xm_write16(hw, port, XM_PHY_DATA, val);
1128 for (i = 0; i < PHY_RETRIES; i++) {
1129 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1130 return 0;
1131 udelay(1);
1132 }
1133 return -ETIMEDOUT;
1134}
1135
1136static void genesis_init(struct skge_hw *hw)
1137{
1138 /* set blink source counter */
1139 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1140 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1141
1142 /* configure mac arbiter */
1143 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1144
1145 /* configure mac arbiter timeout values */
1146 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1147 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1148 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1149 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1150
1151 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1152 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1153 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1154 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1155
1156 /* configure packet arbiter timeout */
1157 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1158 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1159 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1160 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1161 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1162}
1163
1164static void genesis_reset(struct skge_hw *hw, int port)
1165{
1166 static const u8 zero[8] = { 0 };
1167 u32 reg;
1168
1169 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1170
1171 /* reset the statistics module */
1172 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1173 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1174 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1175 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1176 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1177
1178 /* disable Broadcom PHY IRQ */
1179 if (hw->phy_type == SK_PHY_BCOM)
1180 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1181
1182 xm_outhash(hw, port, XM_HSM, zero);
1183
1184 /* Flush TX and RX fifo */
1185 reg = xm_read32(hw, port, XM_MODE);
1186 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1187 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1188}
1189
1190/* Convert mode to MII values */
1191static const u16 phy_pause_map[] = {
1192 [FLOW_MODE_NONE] = 0,
1193 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1194 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1195 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1196};
1197
1198/* special defines for FIBER (88E1011S only) */
1199static const u16 fiber_pause_map[] = {
1200 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1201 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1202 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1203 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1204};
1205
1206
1207/* Check status of Broadcom phy link */
1208static void bcom_check_link(struct skge_hw *hw, int port)
1209{
1210 struct net_device *dev = hw->dev[port];
1211 struct skge_port *skge = netdev_priv(dev);
1212 u16 status;
1213
1214 /* read twice because of latch */
1215 xm_phy_read(hw, port, PHY_BCOM_STAT);
1216 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1217
1218 if ((status & PHY_ST_LSYNC) == 0) {
1219 xm_link_down(hw, port);
1220 return;
1221 }
1222
1223 if (skge->autoneg == AUTONEG_ENABLE) {
1224 u16 lpa, aux;
1225
1226 if (!(status & PHY_ST_AN_OVER))
1227 return;
1228
1229 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1230 if (lpa & PHY_B_AN_RF) {
1231 netdev_notice(dev, "remote fault\n");
1232 return;
1233 }
1234
1235 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1236
1237 /* Check Duplex mismatch */
1238 switch (aux & PHY_B_AS_AN_RES_MSK) {
1239 case PHY_B_RES_1000FD:
1240 skge->duplex = DUPLEX_FULL;
1241 break;
1242 case PHY_B_RES_1000HD:
1243 skge->duplex = DUPLEX_HALF;
1244 break;
1245 default:
1246 netdev_notice(dev, "duplex mismatch\n");
1247 return;
1248 }
1249
1250 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1251 switch (aux & PHY_B_AS_PAUSE_MSK) {
1252 case PHY_B_AS_PAUSE_MSK:
1253 skge->flow_status = FLOW_STAT_SYMMETRIC;
1254 break;
1255 case PHY_B_AS_PRR:
1256 skge->flow_status = FLOW_STAT_REM_SEND;
1257 break;
1258 case PHY_B_AS_PRT:
1259 skge->flow_status = FLOW_STAT_LOC_SEND;
1260 break;
1261 default:
1262 skge->flow_status = FLOW_STAT_NONE;
1263 }
1264 skge->speed = SPEED_1000;
1265 }
1266
1267 if (!netif_carrier_ok(dev))
1268 genesis_link_up(skge);
1269}
1270
1271/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1272 * Phy on for 100 or 10Mbit operation
1273 */
1274static void bcom_phy_init(struct skge_port *skge)
1275{
1276 struct skge_hw *hw = skge->hw;
1277 int port = skge->port;
1278 int i;
1279 u16 id1, r, ext, ctl;
1280
1281 /* magic workaround patterns for Broadcom */
1282 static const struct {
1283 u16 reg;
1284 u16 val;
1285 } A1hack[] = {
1286 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1287 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1288 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1289 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1290 }, C0hack[] = {
1291 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1292 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1293 };
1294
1295 /* read Id from external PHY (all have the same address) */
1296 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1297
1298 /* Optimize MDIO transfer by suppressing preamble. */
1299 r = xm_read16(hw, port, XM_MMU_CMD);
1300 r |= XM_MMU_NO_PRE;
1301 xm_write16(hw, port, XM_MMU_CMD, r);
1302
1303 switch (id1) {
1304 case PHY_BCOM_ID1_C0:
1305 /*
1306 * Workaround BCOM Errata for the C0 type.
1307 * Write magic patterns to reserved registers.
1308 */
1309 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1310 xm_phy_write(hw, port,
1311 C0hack[i].reg, C0hack[i].val);
1312
1313 break;
1314 case PHY_BCOM_ID1_A1:
1315 /*
1316 * Workaround BCOM Errata for the A1 type.
1317 * Write magic patterns to reserved registers.
1318 */
1319 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1320 xm_phy_write(hw, port,
1321 A1hack[i].reg, A1hack[i].val);
1322 break;
1323 }
1324
1325 /*
1326 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1327 * Disable Power Management after reset.
1328 */
1329 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1330 r |= PHY_B_AC_DIS_PM;
1331 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1332
1333 /* Dummy read */
1334 xm_read16(hw, port, XM_ISRC);
1335
1336 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1337 ctl = PHY_CT_SP1000; /* always 1000mbit */
1338
1339 if (skge->autoneg == AUTONEG_ENABLE) {
1340 /*
1341 * Workaround BCOM Errata #1 for the C5 type.
1342 * 1000Base-T Link Acquisition Failure in Slave Mode
1343 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1344 */
1345 u16 adv = PHY_B_1000C_RD;
1346 if (skge->advertising & ADVERTISED_1000baseT_Half)
1347 adv |= PHY_B_1000C_AHD;
1348 if (skge->advertising & ADVERTISED_1000baseT_Full)
1349 adv |= PHY_B_1000C_AFD;
1350 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1351
1352 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1353 } else {
1354 if (skge->duplex == DUPLEX_FULL)
1355 ctl |= PHY_CT_DUP_MD;
1356 /* Force to slave */
1357 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1358 }
1359
1360 /* Set autonegotiation pause parameters */
1361 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1362 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1363
1364 /* Handle Jumbo frames */
1365 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1366 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1367 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1368
1369 ext |= PHY_B_PEC_HIGH_LA;
1370
1371 }
1372
1373 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1374 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1375
1376 /* Use link status change interrupt */
1377 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1378}
1379
1380static void xm_phy_init(struct skge_port *skge)
1381{
1382 struct skge_hw *hw = skge->hw;
1383 int port = skge->port;
1384 u16 ctrl = 0;
1385
1386 if (skge->autoneg == AUTONEG_ENABLE) {
1387 if (skge->advertising & ADVERTISED_1000baseT_Half)
1388 ctrl |= PHY_X_AN_HD;
1389 if (skge->advertising & ADVERTISED_1000baseT_Full)
1390 ctrl |= PHY_X_AN_FD;
1391
1392 ctrl |= fiber_pause_map[skge->flow_control];
1393
1394 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1395
1396 /* Restart Auto-negotiation */
1397 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1398 } else {
1399 /* Set DuplexMode in Config register */
1400 if (skge->duplex == DUPLEX_FULL)
1401 ctrl |= PHY_CT_DUP_MD;
1402 /*
1403 * Do NOT enable Auto-negotiation here. This would hold
1404 * the link down because no IDLEs are transmitted
1405 */
1406 }
1407
1408 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1409
1410 /* Poll PHY for status changes */
1411 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1412}
1413
1414static int xm_check_link(struct net_device *dev)
1415{
1416 struct skge_port *skge = netdev_priv(dev);
1417 struct skge_hw *hw = skge->hw;
1418 int port = skge->port;
1419 u16 status;
1420
1421 /* read twice because of latch */
1422 xm_phy_read(hw, port, PHY_XMAC_STAT);
1423 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1424
1425 if ((status & PHY_ST_LSYNC) == 0) {
1426 xm_link_down(hw, port);
1427 return 0;
1428 }
1429
1430 if (skge->autoneg == AUTONEG_ENABLE) {
1431 u16 lpa, res;
1432
1433 if (!(status & PHY_ST_AN_OVER))
1434 return 0;
1435
1436 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1437 if (lpa & PHY_B_AN_RF) {
1438 netdev_notice(dev, "remote fault\n");
1439 return 0;
1440 }
1441
1442 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1443
1444 /* Check Duplex mismatch */
1445 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1446 case PHY_X_RS_FD:
1447 skge->duplex = DUPLEX_FULL;
1448 break;
1449 case PHY_X_RS_HD:
1450 skge->duplex = DUPLEX_HALF;
1451 break;
1452 default:
1453 netdev_notice(dev, "duplex mismatch\n");
1454 return 0;
1455 }
1456
1457 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1458 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1459 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1460 (lpa & PHY_X_P_SYM_MD))
1461 skge->flow_status = FLOW_STAT_SYMMETRIC;
1462 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1463 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1464 /* Enable PAUSE receive, disable PAUSE transmit */
1465 skge->flow_status = FLOW_STAT_REM_SEND;
1466 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1467 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1468 /* Disable PAUSE receive, enable PAUSE transmit */
1469 skge->flow_status = FLOW_STAT_LOC_SEND;
1470 else
1471 skge->flow_status = FLOW_STAT_NONE;
1472
1473 skge->speed = SPEED_1000;
1474 }
1475
1476 if (!netif_carrier_ok(dev))
1477 genesis_link_up(skge);
1478 return 1;
1479}
1480
1481/* Poll to check for link coming up.
1482 *
1483 * Since internal PHY is wired to a level triggered pin, can't
1484 * get an interrupt when carrier is detected, need to poll for
1485 * link coming up.
1486 */
1487static void xm_link_timer(unsigned long arg)
1488{
1489 struct skge_port *skge = (struct skge_port *) arg;
1490 struct net_device *dev = skge->netdev;
1491 struct skge_hw *hw = skge->hw;
1492 int port = skge->port;
1493 int i;
1494 unsigned long flags;
1495
1496 if (!netif_running(dev))
1497 return;
1498
1499 spin_lock_irqsave(&hw->phy_lock, flags);
1500
1501 /*
1502 * Verify that the link by checking GPIO register three times.
1503 * This pin has the signal from the link_sync pin connected to it.
1504 */
1505 for (i = 0; i < 3; i++) {
1506 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1507 goto link_down;
1508 }
1509
1510 /* Re-enable interrupt to detect link down */
1511 if (xm_check_link(dev)) {
1512 u16 msk = xm_read16(hw, port, XM_IMSK);
1513 msk &= ~XM_IS_INP_ASS;
1514 xm_write16(hw, port, XM_IMSK, msk);
1515 xm_read16(hw, port, XM_ISRC);
1516 } else {
1517link_down:
1518 mod_timer(&skge->link_timer,
1519 round_jiffies(jiffies + LINK_HZ));
1520 }
1521 spin_unlock_irqrestore(&hw->phy_lock, flags);
1522}
1523
1524static void genesis_mac_init(struct skge_hw *hw, int port)
1525{
1526 struct net_device *dev = hw->dev[port];
1527 struct skge_port *skge = netdev_priv(dev);
1528 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1529 int i;
1530 u32 r;
1531 static const u8 zero[6] = { 0 };
1532
1533 for (i = 0; i < 10; i++) {
1534 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1535 MFF_SET_MAC_RST);
1536 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1537 goto reset_ok;
1538 udelay(1);
1539 }
1540
1541 netdev_warn(dev, "genesis reset failed\n");
1542
1543 reset_ok:
1544 /* Unreset the XMAC. */
1545 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1546
1547 /*
1548 * Perform additional initialization for external PHYs,
1549 * namely for the 1000baseTX cards that use the XMAC's
1550 * GMII mode.
1551 */
1552 if (hw->phy_type != SK_PHY_XMAC) {
1553 /* Take external Phy out of reset */
1554 r = skge_read32(hw, B2_GP_IO);
1555 if (port == 0)
1556 r |= GP_DIR_0|GP_IO_0;
1557 else
1558 r |= GP_DIR_2|GP_IO_2;
1559
1560 skge_write32(hw, B2_GP_IO, r);
1561
1562 /* Enable GMII interface */
1563 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1564 }
1565
1566
1567 switch (hw->phy_type) {
1568 case SK_PHY_XMAC:
1569 xm_phy_init(skge);
1570 break;
1571 case SK_PHY_BCOM:
1572 bcom_phy_init(skge);
1573 bcom_check_link(hw, port);
1574 }
1575
1576 /* Set Station Address */
1577 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1578
1579 /* We don't use match addresses so clear */
1580 for (i = 1; i < 16; i++)
1581 xm_outaddr(hw, port, XM_EXM(i), zero);
1582
1583 /* Clear MIB counters */
1584 xm_write16(hw, port, XM_STAT_CMD,
1585 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1586 /* Clear two times according to Errata #3 */
1587 xm_write16(hw, port, XM_STAT_CMD,
1588 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1589
1590 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1591 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1592
1593 /* We don't need the FCS appended to the packet. */
1594 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1595 if (jumbo)
1596 r |= XM_RX_BIG_PK_OK;
1597
1598 if (skge->duplex == DUPLEX_HALF) {
1599 /*
1600 * If in manual half duplex mode the other side might be in
1601 * full duplex mode, so ignore if a carrier extension is not seen
1602 * on frames received
1603 */
1604 r |= XM_RX_DIS_CEXT;
1605 }
1606 xm_write16(hw, port, XM_RX_CMD, r);
1607
1608 /* We want short frames padded to 60 bytes. */
1609 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1610
1611 /* Increase threshold for jumbo frames on dual port */
1612 if (hw->ports > 1 && jumbo)
1613 xm_write16(hw, port, XM_TX_THR, 1020);
1614 else
1615 xm_write16(hw, port, XM_TX_THR, 512);
1616
1617 /*
1618 * Enable the reception of all error frames. This is is
1619 * a necessary evil due to the design of the XMAC. The
1620 * XMAC's receive FIFO is only 8K in size, however jumbo
1621 * frames can be up to 9000 bytes in length. When bad
1622 * frame filtering is enabled, the XMAC's RX FIFO operates
1623 * in 'store and forward' mode. For this to work, the
1624 * entire frame has to fit into the FIFO, but that means
1625 * that jumbo frames larger than 8192 bytes will be
1626 * truncated. Disabling all bad frame filtering causes
1627 * the RX FIFO to operate in streaming mode, in which
1628 * case the XMAC will start transferring frames out of the
1629 * RX FIFO as soon as the FIFO threshold is reached.
1630 */
1631 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1632
1633
1634 /*
1635 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1636 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1637 * and 'Octets Rx OK Hi Cnt Ov'.
1638 */
1639 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1640
1641 /*
1642 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1643 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1644 * and 'Octets Tx OK Hi Cnt Ov'.
1645 */
1646 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1647
1648 /* Configure MAC arbiter */
1649 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1650
1651 /* configure timeout values */
1652 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1653 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1654 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1655 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1656
1657 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1658 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1659 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1660 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1661
1662 /* Configure Rx MAC FIFO */
1663 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1664 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1665 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1666
1667 /* Configure Tx MAC FIFO */
1668 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1669 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1670 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1671
1672 if (jumbo) {
1673 /* Enable frame flushing if jumbo frames used */
1674 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1675 } else {
1676 /* enable timeout timers if normal frames */
1677 skge_write16(hw, B3_PA_CTRL,
1678 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1679 }
1680}
1681
1682static void genesis_stop(struct skge_port *skge)
1683{
1684 struct skge_hw *hw = skge->hw;
1685 int port = skge->port;
1686 unsigned retries = 1000;
1687 u16 cmd;
1688
1689 /* Disable Tx and Rx */
1690 cmd = xm_read16(hw, port, XM_MMU_CMD);
1691 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1692 xm_write16(hw, port, XM_MMU_CMD, cmd);
1693
1694 genesis_reset(hw, port);
1695
1696 /* Clear Tx packet arbiter timeout IRQ */
1697 skge_write16(hw, B3_PA_CTRL,
1698 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1699
1700 /* Reset the MAC */
1701 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1702 do {
1703 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1704 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1705 break;
1706 } while (--retries > 0);
1707
1708 /* For external PHYs there must be special handling */
1709 if (hw->phy_type != SK_PHY_XMAC) {
1710 u32 reg = skge_read32(hw, B2_GP_IO);
1711 if (port == 0) {
1712 reg |= GP_DIR_0;
1713 reg &= ~GP_IO_0;
1714 } else {
1715 reg |= GP_DIR_2;
1716 reg &= ~GP_IO_2;
1717 }
1718 skge_write32(hw, B2_GP_IO, reg);
1719 skge_read32(hw, B2_GP_IO);
1720 }
1721
1722 xm_write16(hw, port, XM_MMU_CMD,
1723 xm_read16(hw, port, XM_MMU_CMD)
1724 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1725
1726 xm_read16(hw, port, XM_MMU_CMD);
1727}
1728
1729
1730static void genesis_get_stats(struct skge_port *skge, u64 *data)
1731{
1732 struct skge_hw *hw = skge->hw;
1733 int port = skge->port;
1734 int i;
1735 unsigned long timeout = jiffies + HZ;
1736
1737 xm_write16(hw, port,
1738 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1739
1740 /* wait for update to complete */
1741 while (xm_read16(hw, port, XM_STAT_CMD)
1742 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1743 if (time_after(jiffies, timeout))
1744 break;
1745 udelay(10);
1746 }
1747
1748 /* special case for 64 bit octet counter */
1749 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1750 | xm_read32(hw, port, XM_TXO_OK_LO);
1751 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1752 | xm_read32(hw, port, XM_RXO_OK_LO);
1753
1754 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1755 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1756}
1757
1758static void genesis_mac_intr(struct skge_hw *hw, int port)
1759{
1760 struct net_device *dev = hw->dev[port];
1761 struct skge_port *skge = netdev_priv(dev);
1762 u16 status = xm_read16(hw, port, XM_ISRC);
1763
1764 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1765 "mac interrupt status 0x%x\n", status);
1766
1767 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1768 xm_link_down(hw, port);
1769 mod_timer(&skge->link_timer, jiffies + 1);
1770 }
1771
1772 if (status & XM_IS_TXF_UR) {
1773 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1774 ++dev->stats.tx_fifo_errors;
1775 }
1776}
1777
1778static void genesis_link_up(struct skge_port *skge)
1779{
1780 struct skge_hw *hw = skge->hw;
1781 int port = skge->port;
1782 u16 cmd, msk;
1783 u32 mode;
1784
1785 cmd = xm_read16(hw, port, XM_MMU_CMD);
1786
1787 /*
1788 * enabling pause frame reception is required for 1000BT
1789 * because the XMAC is not reset if the link is going down
1790 */
1791 if (skge->flow_status == FLOW_STAT_NONE ||
1792 skge->flow_status == FLOW_STAT_LOC_SEND)
1793 /* Disable Pause Frame Reception */
1794 cmd |= XM_MMU_IGN_PF;
1795 else
1796 /* Enable Pause Frame Reception */
1797 cmd &= ~XM_MMU_IGN_PF;
1798
1799 xm_write16(hw, port, XM_MMU_CMD, cmd);
1800
1801 mode = xm_read32(hw, port, XM_MODE);
1802 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1803 skge->flow_status == FLOW_STAT_LOC_SEND) {
1804 /*
1805 * Configure Pause Frame Generation
1806 * Use internal and external Pause Frame Generation.
1807 * Sending pause frames is edge triggered.
1808 * Send a Pause frame with the maximum pause time if
1809 * internal oder external FIFO full condition occurs.
1810 * Send a zero pause time frame to re-start transmission.
1811 */
1812 /* XM_PAUSE_DA = '010000C28001' (default) */
1813 /* XM_MAC_PTIME = 0xffff (maximum) */
1814 /* remember this value is defined in big endian (!) */
1815 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1816
1817 mode |= XM_PAUSE_MODE;
1818 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1819 } else {
1820 /*
1821 * disable pause frame generation is required for 1000BT
1822 * because the XMAC is not reset if the link is going down
1823 */
1824 /* Disable Pause Mode in Mode Register */
1825 mode &= ~XM_PAUSE_MODE;
1826
1827 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1828 }
1829
1830 xm_write32(hw, port, XM_MODE, mode);
1831
1832 /* Turn on detection of Tx underrun */
1833 msk = xm_read16(hw, port, XM_IMSK);
1834 msk &= ~XM_IS_TXF_UR;
1835 xm_write16(hw, port, XM_IMSK, msk);
1836
1837 xm_read16(hw, port, XM_ISRC);
1838
1839 /* get MMU Command Reg. */
1840 cmd = xm_read16(hw, port, XM_MMU_CMD);
1841 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1842 cmd |= XM_MMU_GMII_FD;
1843
1844 /*
1845 * Workaround BCOM Errata (#10523) for all BCom Phys
1846 * Enable Power Management after link up
1847 */
1848 if (hw->phy_type == SK_PHY_BCOM) {
1849 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1850 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1851 & ~PHY_B_AC_DIS_PM);
1852 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1853 }
1854
1855 /* enable Rx/Tx */
1856 xm_write16(hw, port, XM_MMU_CMD,
1857 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1858 skge_link_up(skge);
1859}
1860
1861
1862static inline void bcom_phy_intr(struct skge_port *skge)
1863{
1864 struct skge_hw *hw = skge->hw;
1865 int port = skge->port;
1866 u16 isrc;
1867
1868 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1869 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1870 "phy interrupt status 0x%x\n", isrc);
1871
1872 if (isrc & PHY_B_IS_PSE)
1873 pr_err("%s: uncorrectable pair swap error\n",
1874 hw->dev[port]->name);
1875
1876 /* Workaround BCom Errata:
1877 * enable and disable loopback mode if "NO HCD" occurs.
1878 */
1879 if (isrc & PHY_B_IS_NO_HDCL) {
1880 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1881 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1882 ctrl | PHY_CT_LOOP);
1883 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1884 ctrl & ~PHY_CT_LOOP);
1885 }
1886
1887 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1888 bcom_check_link(hw, port);
1889
1890}
1891
1892static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1893{
1894 int i;
1895
1896 gma_write16(hw, port, GM_SMI_DATA, val);
1897 gma_write16(hw, port, GM_SMI_CTRL,
1898 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1899 for (i = 0; i < PHY_RETRIES; i++) {
1900 udelay(1);
1901
1902 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1903 return 0;
1904 }
1905
1906 pr_warn("%s: phy write timeout\n", hw->dev[port]->name);
1907 return -EIO;
1908}
1909
1910static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1911{
1912 int i;
1913
1914 gma_write16(hw, port, GM_SMI_CTRL,
1915 GM_SMI_CT_PHY_AD(hw->phy_addr)
1916 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1917
1918 for (i = 0; i < PHY_RETRIES; i++) {
1919 udelay(1);
1920 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1921 goto ready;
1922 }
1923
1924 return -ETIMEDOUT;
1925 ready:
1926 *val = gma_read16(hw, port, GM_SMI_DATA);
1927 return 0;
1928}
1929
1930static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1931{
1932 u16 v = 0;
1933 if (__gm_phy_read(hw, port, reg, &v))
1934 pr_warn("%s: phy read timeout\n", hw->dev[port]->name);
1935 return v;
1936}
1937
1938/* Marvell Phy Initialization */
1939static void yukon_init(struct skge_hw *hw, int port)
1940{
1941 struct skge_port *skge = netdev_priv(hw->dev[port]);
1942 u16 ctrl, ct1000, adv;
1943
1944 if (skge->autoneg == AUTONEG_ENABLE) {
1945 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1946
1947 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1948 PHY_M_EC_MAC_S_MSK);
1949 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1950
1951 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1952
1953 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1954 }
1955
1956 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1957 if (skge->autoneg == AUTONEG_DISABLE)
1958 ctrl &= ~PHY_CT_ANE;
1959
1960 ctrl |= PHY_CT_RESET;
1961 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1962
1963 ctrl = 0;
1964 ct1000 = 0;
1965 adv = PHY_AN_CSMA;
1966
1967 if (skge->autoneg == AUTONEG_ENABLE) {
1968 if (hw->copper) {
1969 if (skge->advertising & ADVERTISED_1000baseT_Full)
1970 ct1000 |= PHY_M_1000C_AFD;
1971 if (skge->advertising & ADVERTISED_1000baseT_Half)
1972 ct1000 |= PHY_M_1000C_AHD;
1973 if (skge->advertising & ADVERTISED_100baseT_Full)
1974 adv |= PHY_M_AN_100_FD;
1975 if (skge->advertising & ADVERTISED_100baseT_Half)
1976 adv |= PHY_M_AN_100_HD;
1977 if (skge->advertising & ADVERTISED_10baseT_Full)
1978 adv |= PHY_M_AN_10_FD;
1979 if (skge->advertising & ADVERTISED_10baseT_Half)
1980 adv |= PHY_M_AN_10_HD;
1981
1982 /* Set Flow-control capabilities */
1983 adv |= phy_pause_map[skge->flow_control];
1984 } else {
1985 if (skge->advertising & ADVERTISED_1000baseT_Full)
1986 adv |= PHY_M_AN_1000X_AFD;
1987 if (skge->advertising & ADVERTISED_1000baseT_Half)
1988 adv |= PHY_M_AN_1000X_AHD;
1989
1990 adv |= fiber_pause_map[skge->flow_control];
1991 }
1992
1993 /* Restart Auto-negotiation */
1994 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1995 } else {
1996 /* forced speed/duplex settings */
1997 ct1000 = PHY_M_1000C_MSE;
1998
1999 if (skge->duplex == DUPLEX_FULL)
2000 ctrl |= PHY_CT_DUP_MD;
2001
2002 switch (skge->speed) {
2003 case SPEED_1000:
2004 ctrl |= PHY_CT_SP1000;
2005 break;
2006 case SPEED_100:
2007 ctrl |= PHY_CT_SP100;
2008 break;
2009 }
2010
2011 ctrl |= PHY_CT_RESET;
2012 }
2013
2014 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2015
2016 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2017 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2018
2019 /* Enable phy interrupt on autonegotiation complete (or link up) */
2020 if (skge->autoneg == AUTONEG_ENABLE)
2021 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2022 else
2023 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2024}
2025
2026static void yukon_reset(struct skge_hw *hw, int port)
2027{
2028 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2029 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2030 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2031 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2032 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2033
2034 gma_write16(hw, port, GM_RX_CTRL,
2035 gma_read16(hw, port, GM_RX_CTRL)
2036 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2037}
2038
2039/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2040static int is_yukon_lite_a0(struct skge_hw *hw)
2041{
2042 u32 reg;
2043 int ret;
2044
2045 if (hw->chip_id != CHIP_ID_YUKON)
2046 return 0;
2047
2048 reg = skge_read32(hw, B2_FAR);
2049 skge_write8(hw, B2_FAR + 3, 0xff);
2050 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2051 skge_write32(hw, B2_FAR, reg);
2052 return ret;
2053}
2054
2055static void yukon_mac_init(struct skge_hw *hw, int port)
2056{
2057 struct skge_port *skge = netdev_priv(hw->dev[port]);
2058 int i;
2059 u32 reg;
2060 const u8 *addr = hw->dev[port]->dev_addr;
2061
2062 /* WA code for COMA mode -- set PHY reset */
2063 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2064 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2065 reg = skge_read32(hw, B2_GP_IO);
2066 reg |= GP_DIR_9 | GP_IO_9;
2067 skge_write32(hw, B2_GP_IO, reg);
2068 }
2069
2070 /* hard reset */
2071 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2072 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2073
2074 /* WA code for COMA mode -- clear PHY reset */
2075 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2076 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2077 reg = skge_read32(hw, B2_GP_IO);
2078 reg |= GP_DIR_9;
2079 reg &= ~GP_IO_9;
2080 skge_write32(hw, B2_GP_IO, reg);
2081 }
2082
2083 /* Set hardware config mode */
2084 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2085 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2086 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2087
2088 /* Clear GMC reset */
2089 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2090 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2091 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2092
2093 if (skge->autoneg == AUTONEG_DISABLE) {
2094 reg = GM_GPCR_AU_ALL_DIS;
2095 gma_write16(hw, port, GM_GP_CTRL,
2096 gma_read16(hw, port, GM_GP_CTRL) | reg);
2097
2098 switch (skge->speed) {
2099 case SPEED_1000:
2100 reg &= ~GM_GPCR_SPEED_100;
2101 reg |= GM_GPCR_SPEED_1000;
2102 break;
2103 case SPEED_100:
2104 reg &= ~GM_GPCR_SPEED_1000;
2105 reg |= GM_GPCR_SPEED_100;
2106 break;
2107 case SPEED_10:
2108 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2109 break;
2110 }
2111
2112 if (skge->duplex == DUPLEX_FULL)
2113 reg |= GM_GPCR_DUP_FULL;
2114 } else
2115 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2116
2117 switch (skge->flow_control) {
2118 case FLOW_MODE_NONE:
2119 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2120 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2121 break;
2122 case FLOW_MODE_LOC_SEND:
2123 /* disable Rx flow-control */
2124 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2125 break;
2126 case FLOW_MODE_SYMMETRIC:
2127 case FLOW_MODE_SYM_OR_REM:
2128 /* enable Tx & Rx flow-control */
2129 break;
2130 }
2131
2132 gma_write16(hw, port, GM_GP_CTRL, reg);
2133 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2134
2135 yukon_init(hw, port);
2136
2137 /* MIB clear */
2138 reg = gma_read16(hw, port, GM_PHY_ADDR);
2139 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2140
2141 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2142 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2143 gma_write16(hw, port, GM_PHY_ADDR, reg);
2144
2145 /* transmit control */
2146 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2147
2148 /* receive control reg: unicast + multicast + no FCS */
2149 gma_write16(hw, port, GM_RX_CTRL,
2150 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2151
2152 /* transmit flow control */
2153 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2154
2155 /* transmit parameter */
2156 gma_write16(hw, port, GM_TX_PARAM,
2157 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2158 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2159 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2160
2161 /* configure the Serial Mode Register */
2162 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2163 | GM_SMOD_VLAN_ENA
2164 | IPG_DATA_VAL(IPG_DATA_DEF);
2165
2166 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2167 reg |= GM_SMOD_JUMBO_ENA;
2168
2169 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2170
2171 /* physical address: used for pause frames */
2172 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2173 /* virtual address for data */
2174 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2175
2176 /* enable interrupt mask for counter overflows */
2177 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2178 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2179 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2180
2181 /* Initialize Mac Fifo */
2182
2183 /* Configure Rx MAC FIFO */
2184 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2185 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2186
2187 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2188 if (is_yukon_lite_a0(hw))
2189 reg &= ~GMF_RX_F_FL_ON;
2190
2191 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2192 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2193 /*
2194 * because Pause Packet Truncation in GMAC is not working
2195 * we have to increase the Flush Threshold to 64 bytes
2196 * in order to flush pause packets in Rx FIFO on Yukon-1
2197 */
2198 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2199
2200 /* Configure Tx MAC FIFO */
2201 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2202 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2203}
2204
2205/* Go into power down mode */
2206static void yukon_suspend(struct skge_hw *hw, int port)
2207{
2208 u16 ctrl;
2209
2210 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2211 ctrl |= PHY_M_PC_POL_R_DIS;
2212 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2213
2214 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2215 ctrl |= PHY_CT_RESET;
2216 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2217
2218 /* switch IEEE compatible power down mode on */
2219 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2220 ctrl |= PHY_CT_PDOWN;
2221 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2222}
2223
2224static void yukon_stop(struct skge_port *skge)
2225{
2226 struct skge_hw *hw = skge->hw;
2227 int port = skge->port;
2228
2229 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2230 yukon_reset(hw, port);
2231
2232 gma_write16(hw, port, GM_GP_CTRL,
2233 gma_read16(hw, port, GM_GP_CTRL)
2234 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2235 gma_read16(hw, port, GM_GP_CTRL);
2236
2237 yukon_suspend(hw, port);
2238
2239 /* set GPHY Control reset */
2240 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2241 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2242}
2243
2244static void yukon_get_stats(struct skge_port *skge, u64 *data)
2245{
2246 struct skge_hw *hw = skge->hw;
2247 int port = skge->port;
2248 int i;
2249
2250 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2251 | gma_read32(hw, port, GM_TXO_OK_LO);
2252 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2253 | gma_read32(hw, port, GM_RXO_OK_LO);
2254
2255 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2256 data[i] = gma_read32(hw, port,
2257 skge_stats[i].gma_offset);
2258}
2259
2260static void yukon_mac_intr(struct skge_hw *hw, int port)
2261{
2262 struct net_device *dev = hw->dev[port];
2263 struct skge_port *skge = netdev_priv(dev);
2264 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2265
2266 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2267 "mac interrupt status 0x%x\n", status);
2268
2269 if (status & GM_IS_RX_FF_OR) {
2270 ++dev->stats.rx_fifo_errors;
2271 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2272 }
2273
2274 if (status & GM_IS_TX_FF_UR) {
2275 ++dev->stats.tx_fifo_errors;
2276 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2277 }
2278
2279}
2280
2281static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2282{
2283 switch (aux & PHY_M_PS_SPEED_MSK) {
2284 case PHY_M_PS_SPEED_1000:
2285 return SPEED_1000;
2286 case PHY_M_PS_SPEED_100:
2287 return SPEED_100;
2288 default:
2289 return SPEED_10;
2290 }
2291}
2292
2293static void yukon_link_up(struct skge_port *skge)
2294{
2295 struct skge_hw *hw = skge->hw;
2296 int port = skge->port;
2297 u16 reg;
2298
2299 /* Enable Transmit FIFO Underrun */
2300 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2301
2302 reg = gma_read16(hw, port, GM_GP_CTRL);
2303 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2304 reg |= GM_GPCR_DUP_FULL;
2305
2306 /* enable Rx/Tx */
2307 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2308 gma_write16(hw, port, GM_GP_CTRL, reg);
2309
2310 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2311 skge_link_up(skge);
2312}
2313
2314static void yukon_link_down(struct skge_port *skge)
2315{
2316 struct skge_hw *hw = skge->hw;
2317 int port = skge->port;
2318 u16 ctrl;
2319
2320 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2321 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2322 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2323
2324 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2325 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2326 ctrl |= PHY_M_AN_ASP;
2327 /* restore Asymmetric Pause bit */
2328 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2329 }
2330
2331 skge_link_down(skge);
2332
2333 yukon_init(hw, port);
2334}
2335
2336static void yukon_phy_intr(struct skge_port *skge)
2337{
2338 struct skge_hw *hw = skge->hw;
2339 int port = skge->port;
2340 const char *reason = NULL;
2341 u16 istatus, phystat;
2342
2343 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2344 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2345
2346 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2347 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2348
2349 if (istatus & PHY_M_IS_AN_COMPL) {
2350 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2351 & PHY_M_AN_RF) {
2352 reason = "remote fault";
2353 goto failed;
2354 }
2355
2356 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2357 reason = "master/slave fault";
2358 goto failed;
2359 }
2360
2361 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2362 reason = "speed/duplex";
2363 goto failed;
2364 }
2365
2366 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2367 ? DUPLEX_FULL : DUPLEX_HALF;
2368 skge->speed = yukon_speed(hw, phystat);
2369
2370 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2371 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2372 case PHY_M_PS_PAUSE_MSK:
2373 skge->flow_status = FLOW_STAT_SYMMETRIC;
2374 break;
2375 case PHY_M_PS_RX_P_EN:
2376 skge->flow_status = FLOW_STAT_REM_SEND;
2377 break;
2378 case PHY_M_PS_TX_P_EN:
2379 skge->flow_status = FLOW_STAT_LOC_SEND;
2380 break;
2381 default:
2382 skge->flow_status = FLOW_STAT_NONE;
2383 }
2384
2385 if (skge->flow_status == FLOW_STAT_NONE ||
2386 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2387 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2388 else
2389 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2390 yukon_link_up(skge);
2391 return;
2392 }
2393
2394 if (istatus & PHY_M_IS_LSP_CHANGE)
2395 skge->speed = yukon_speed(hw, phystat);
2396
2397 if (istatus & PHY_M_IS_DUP_CHANGE)
2398 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2399 if (istatus & PHY_M_IS_LST_CHANGE) {
2400 if (phystat & PHY_M_PS_LINK_UP)
2401 yukon_link_up(skge);
2402 else
2403 yukon_link_down(skge);
2404 }
2405 return;
2406 failed:
2407 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2408
2409 /* XXX restart autonegotiation? */
2410}
2411
2412static void skge_phy_reset(struct skge_port *skge)
2413{
2414 struct skge_hw *hw = skge->hw;
2415 int port = skge->port;
2416 struct net_device *dev = hw->dev[port];
2417
2418 netif_stop_queue(skge->netdev);
2419 netif_carrier_off(skge->netdev);
2420
2421 spin_lock_bh(&hw->phy_lock);
2422 if (is_genesis(hw)) {
2423 genesis_reset(hw, port);
2424 genesis_mac_init(hw, port);
2425 } else {
2426 yukon_reset(hw, port);
2427 yukon_init(hw, port);
2428 }
2429 spin_unlock_bh(&hw->phy_lock);
2430
2431 skge_set_multicast(dev);
2432}
2433
2434/* Basic MII support */
2435static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2436{
2437 struct mii_ioctl_data *data = if_mii(ifr);
2438 struct skge_port *skge = netdev_priv(dev);
2439 struct skge_hw *hw = skge->hw;
2440 int err = -EOPNOTSUPP;
2441
2442 if (!netif_running(dev))
2443 return -ENODEV; /* Phy still in reset */
2444
2445 switch (cmd) {
2446 case SIOCGMIIPHY:
2447 data->phy_id = hw->phy_addr;
2448
2449 /* fallthru */
2450 case SIOCGMIIREG: {
2451 u16 val = 0;
2452 spin_lock_bh(&hw->phy_lock);
2453
2454 if (is_genesis(hw))
2455 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2456 else
2457 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2458 spin_unlock_bh(&hw->phy_lock);
2459 data->val_out = val;
2460 break;
2461 }
2462
2463 case SIOCSMIIREG:
2464 spin_lock_bh(&hw->phy_lock);
2465 if (is_genesis(hw))
2466 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2467 data->val_in);
2468 else
2469 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2470 data->val_in);
2471 spin_unlock_bh(&hw->phy_lock);
2472 break;
2473 }
2474 return err;
2475}
2476
2477static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2478{
2479 u32 end;
2480
2481 start /= 8;
2482 len /= 8;
2483 end = start + len - 1;
2484
2485 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2486 skge_write32(hw, RB_ADDR(q, RB_START), start);
2487 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2488 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2489 skge_write32(hw, RB_ADDR(q, RB_END), end);
2490
2491 if (q == Q_R1 || q == Q_R2) {
2492 /* Set thresholds on receive queue's */
2493 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2494 start + (2*len)/3);
2495 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2496 start + (len/3));
2497 } else {
2498 /* Enable store & forward on Tx queue's because
2499 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2500 */
2501 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2502 }
2503
2504 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2505}
2506
2507/* Setup Bus Memory Interface */
2508static void skge_qset(struct skge_port *skge, u16 q,
2509 const struct skge_element *e)
2510{
2511 struct skge_hw *hw = skge->hw;
2512 u32 watermark = 0x600;
2513 u64 base = skge->dma + (e->desc - skge->mem);
2514
2515 /* optimization to reduce window on 32bit/33mhz */
2516 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2517 watermark /= 2;
2518
2519 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2520 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2521 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2522 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2523}
2524
2525static int skge_up(struct net_device *dev)
2526{
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
2529 int port = skge->port;
2530 u32 chunk, ram_addr;
2531 size_t rx_size, tx_size;
2532 int err;
2533
2534 if (!is_valid_ether_addr(dev->dev_addr))
2535 return -EINVAL;
2536
2537 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2538
2539 if (dev->mtu > RX_BUF_SIZE)
2540 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2541 else
2542 skge->rx_buf_size = RX_BUF_SIZE;
2543
2544
2545 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2546 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2547 skge->mem_size = tx_size + rx_size;
2548 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2549 if (!skge->mem)
2550 return -ENOMEM;
2551
2552 BUG_ON(skge->dma & 7);
2553
2554 if (upper_32_bits(skge->dma) != upper_32_bits(skge->dma + skge->mem_size)) {
2555 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2556 err = -EINVAL;
2557 goto free_pci_mem;
2558 }
2559
2560 memset(skge->mem, 0, skge->mem_size);
2561
2562 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2563 if (err)
2564 goto free_pci_mem;
2565
2566 err = skge_rx_fill(dev);
2567 if (err)
2568 goto free_rx_ring;
2569
2570 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2571 skge->dma + rx_size);
2572 if (err)
2573 goto free_rx_ring;
2574
2575 if (hw->ports == 1) {
2576 err = request_irq(hw->pdev->irq, skge_intr, IRQF_SHARED,
2577 dev->name, hw);
2578 if (err) {
2579 netdev_err(dev, "Unable to allocate interrupt %d error: %d\n",
2580 hw->pdev->irq, err);
2581 goto free_tx_ring;
2582 }
2583 }
2584
2585 /* Initialize MAC */
2586 netif_carrier_off(dev);
2587 spin_lock_bh(&hw->phy_lock);
2588 if (is_genesis(hw))
2589 genesis_mac_init(hw, port);
2590 else
2591 yukon_mac_init(hw, port);
2592 spin_unlock_bh(&hw->phy_lock);
2593
2594 /* Configure RAMbuffers - equally between ports and tx/rx */
2595 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2596 ram_addr = hw->ram_offset + 2 * chunk * port;
2597
2598 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2599 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2600
2601 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2602 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2603 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2604
2605 /* Start receiver BMU */
2606 wmb();
2607 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2608 skge_led(skge, LED_MODE_ON);
2609
2610 spin_lock_irq(&hw->hw_lock);
2611 hw->intr_mask |= portmask[port];
2612 skge_write32(hw, B0_IMSK, hw->intr_mask);
2613 skge_read32(hw, B0_IMSK);
2614 spin_unlock_irq(&hw->hw_lock);
2615
2616 napi_enable(&skge->napi);
2617
2618 skge_set_multicast(dev);
2619
2620 return 0;
2621
2622 free_tx_ring:
2623 kfree(skge->tx_ring.start);
2624 free_rx_ring:
2625 skge_rx_clean(skge);
2626 kfree(skge->rx_ring.start);
2627 free_pci_mem:
2628 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2629 skge->mem = NULL;
2630
2631 return err;
2632}
2633
2634/* stop receiver */
2635static void skge_rx_stop(struct skge_hw *hw, int port)
2636{
2637 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2638 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2639 RB_RST_SET|RB_DIS_OP_MD);
2640 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2641}
2642
2643static int skge_down(struct net_device *dev)
2644{
2645 struct skge_port *skge = netdev_priv(dev);
2646 struct skge_hw *hw = skge->hw;
2647 int port = skge->port;
2648
2649 if (skge->mem == NULL)
2650 return 0;
2651
2652 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2653
2654 netif_tx_disable(dev);
2655
2656 if (is_genesis(hw) && hw->phy_type == SK_PHY_XMAC)
2657 del_timer_sync(&skge->link_timer);
2658
2659 napi_disable(&skge->napi);
2660 netif_carrier_off(dev);
2661
2662 spin_lock_irq(&hw->hw_lock);
2663 hw->intr_mask &= ~portmask[port];
2664 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2665 skge_read32(hw, B0_IMSK);
2666 spin_unlock_irq(&hw->hw_lock);
2667
2668 if (hw->ports == 1)
2669 free_irq(hw->pdev->irq, hw);
2670
2671 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_REG_OFF);
2672 if (is_genesis(hw))
2673 genesis_stop(skge);
2674 else
2675 yukon_stop(skge);
2676
2677 /* Stop transmitter */
2678 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2679 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2680 RB_RST_SET|RB_DIS_OP_MD);
2681
2682
2683 /* Disable Force Sync bit and Enable Alloc bit */
2684 skge_write8(hw, SK_REG(port, TXA_CTRL),
2685 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2686
2687 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2688 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2689 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2690
2691 /* Reset PCI FIFO */
2692 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2693 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2694
2695 /* Reset the RAM Buffer async Tx queue */
2696 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2697
2698 skge_rx_stop(hw, port);
2699
2700 if (is_genesis(hw)) {
2701 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2702 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2703 } else {
2704 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2705 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2706 }
2707
2708 skge_led(skge, LED_MODE_OFF);
2709
2710 netif_tx_lock_bh(dev);
2711 skge_tx_clean(dev);
2712 netif_tx_unlock_bh(dev);
2713
2714 skge_rx_clean(skge);
2715
2716 kfree(skge->rx_ring.start);
2717 kfree(skge->tx_ring.start);
2718 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2719 skge->mem = NULL;
2720 return 0;
2721}
2722
2723static inline int skge_avail(const struct skge_ring *ring)
2724{
2725 smp_mb();
2726 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2727 + (ring->to_clean - ring->to_use) - 1;
2728}
2729
2730static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2731 struct net_device *dev)
2732{
2733 struct skge_port *skge = netdev_priv(dev);
2734 struct skge_hw *hw = skge->hw;
2735 struct skge_element *e;
2736 struct skge_tx_desc *td;
2737 int i;
2738 u32 control, len;
2739 dma_addr_t map;
2740
2741 if (skb_padto(skb, ETH_ZLEN))
2742 return NETDEV_TX_OK;
2743
2744 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2745 return NETDEV_TX_BUSY;
2746
2747 e = skge->tx_ring.to_use;
2748 td = e->desc;
2749 BUG_ON(td->control & BMU_OWN);
2750 e->skb = skb;
2751 len = skb_headlen(skb);
2752 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2753 if (pci_dma_mapping_error(hw->pdev, map))
2754 goto mapping_error;
2755
2756 dma_unmap_addr_set(e, mapaddr, map);
2757 dma_unmap_len_set(e, maplen, len);
2758
2759 td->dma_lo = lower_32_bits(map);
2760 td->dma_hi = upper_32_bits(map);
2761
2762 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2763 const int offset = skb_checksum_start_offset(skb);
2764
2765 /* This seems backwards, but it is what the sk98lin
2766 * does. Looks like hardware is wrong?
2767 */
2768 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2769 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2770 control = BMU_TCP_CHECK;
2771 else
2772 control = BMU_UDP_CHECK;
2773
2774 td->csum_offs = 0;
2775 td->csum_start = offset;
2776 td->csum_write = offset + skb->csum_offset;
2777 } else
2778 control = BMU_CHECK;
2779
2780 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2781 control |= BMU_EOF | BMU_IRQ_EOF;
2782 else {
2783 struct skge_tx_desc *tf = td;
2784
2785 control |= BMU_STFWD;
2786 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2787 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2788
2789 map = skb_frag_dma_map(&hw->pdev->dev, frag, 0,
2790 skb_frag_size(frag), DMA_TO_DEVICE);
2791 if (dma_mapping_error(&hw->pdev->dev, map))
2792 goto mapping_unwind;
2793
2794 e = e->next;
2795 e->skb = skb;
2796 tf = e->desc;
2797 BUG_ON(tf->control & BMU_OWN);
2798
2799 tf->dma_lo = lower_32_bits(map);
2800 tf->dma_hi = upper_32_bits(map);
2801 dma_unmap_addr_set(e, mapaddr, map);
2802 dma_unmap_len_set(e, maplen, skb_frag_size(frag));
2803
2804 tf->control = BMU_OWN | BMU_SW | control | skb_frag_size(frag);
2805 }
2806 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2807 }
2808 /* Make sure all the descriptors written */
2809 wmb();
2810 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2811 wmb();
2812
2813 netdev_sent_queue(dev, skb->len);
2814
2815 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2816
2817 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2818 "tx queued, slot %td, len %d\n",
2819 e - skge->tx_ring.start, skb->len);
2820
2821 skge->tx_ring.to_use = e->next;
2822 smp_wmb();
2823
2824 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2825 netdev_dbg(dev, "transmit queue full\n");
2826 netif_stop_queue(dev);
2827 }
2828
2829 return NETDEV_TX_OK;
2830
2831mapping_unwind:
2832 e = skge->tx_ring.to_use;
2833 pci_unmap_single(hw->pdev,
2834 dma_unmap_addr(e, mapaddr),
2835 dma_unmap_len(e, maplen),
2836 PCI_DMA_TODEVICE);
2837 while (i-- > 0) {
2838 e = e->next;
2839 pci_unmap_page(hw->pdev,
2840 dma_unmap_addr(e, mapaddr),
2841 dma_unmap_len(e, maplen),
2842 PCI_DMA_TODEVICE);
2843 }
2844
2845mapping_error:
2846 if (net_ratelimit())
2847 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
2848 dev_kfree_skb_any(skb);
2849 return NETDEV_TX_OK;
2850}
2851
2852
2853/* Free resources associated with this reing element */
2854static inline void skge_tx_unmap(struct pci_dev *pdev, struct skge_element *e,
2855 u32 control)
2856{
2857 /* skb header vs. fragment */
2858 if (control & BMU_STF)
2859 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2860 dma_unmap_len(e, maplen),
2861 PCI_DMA_TODEVICE);
2862 else
2863 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2864 dma_unmap_len(e, maplen),
2865 PCI_DMA_TODEVICE);
2866}
2867
2868/* Free all buffers in transmit ring */
2869static void skge_tx_clean(struct net_device *dev)
2870{
2871 struct skge_port *skge = netdev_priv(dev);
2872 struct skge_element *e;
2873
2874 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2875 struct skge_tx_desc *td = e->desc;
2876
2877 skge_tx_unmap(skge->hw->pdev, e, td->control);
2878
2879 if (td->control & BMU_EOF)
2880 dev_kfree_skb(e->skb);
2881 td->control = 0;
2882 }
2883
2884 netdev_reset_queue(dev);
2885 skge->tx_ring.to_clean = e;
2886}
2887
2888static void skge_tx_timeout(struct net_device *dev)
2889{
2890 struct skge_port *skge = netdev_priv(dev);
2891
2892 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2893
2894 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2895 skge_tx_clean(dev);
2896 netif_wake_queue(dev);
2897}
2898
2899static int skge_change_mtu(struct net_device *dev, int new_mtu)
2900{
2901 int err;
2902
2903 if (!netif_running(dev)) {
2904 dev->mtu = new_mtu;
2905 return 0;
2906 }
2907
2908 skge_down(dev);
2909
2910 dev->mtu = new_mtu;
2911
2912 err = skge_up(dev);
2913 if (err)
2914 dev_close(dev);
2915
2916 return err;
2917}
2918
2919static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2920
2921static void genesis_add_filter(u8 filter[8], const u8 *addr)
2922{
2923 u32 crc, bit;
2924
2925 crc = ether_crc_le(ETH_ALEN, addr);
2926 bit = ~crc & 0x3f;
2927 filter[bit/8] |= 1 << (bit%8);
2928}
2929
2930static void genesis_set_multicast(struct net_device *dev)
2931{
2932 struct skge_port *skge = netdev_priv(dev);
2933 struct skge_hw *hw = skge->hw;
2934 int port = skge->port;
2935 struct netdev_hw_addr *ha;
2936 u32 mode;
2937 u8 filter[8];
2938
2939 mode = xm_read32(hw, port, XM_MODE);
2940 mode |= XM_MD_ENA_HASH;
2941 if (dev->flags & IFF_PROMISC)
2942 mode |= XM_MD_ENA_PROM;
2943 else
2944 mode &= ~XM_MD_ENA_PROM;
2945
2946 if (dev->flags & IFF_ALLMULTI)
2947 memset(filter, 0xff, sizeof(filter));
2948 else {
2949 memset(filter, 0, sizeof(filter));
2950
2951 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2952 skge->flow_status == FLOW_STAT_SYMMETRIC)
2953 genesis_add_filter(filter, pause_mc_addr);
2954
2955 netdev_for_each_mc_addr(ha, dev)
2956 genesis_add_filter(filter, ha->addr);
2957 }
2958
2959 xm_write32(hw, port, XM_MODE, mode);
2960 xm_outhash(hw, port, XM_HSM, filter);
2961}
2962
2963static void yukon_add_filter(u8 filter[8], const u8 *addr)
2964{
2965 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2966 filter[bit/8] |= 1 << (bit%8);
2967}
2968
2969static void yukon_set_multicast(struct net_device *dev)
2970{
2971 struct skge_port *skge = netdev_priv(dev);
2972 struct skge_hw *hw = skge->hw;
2973 int port = skge->port;
2974 struct netdev_hw_addr *ha;
2975 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2976 skge->flow_status == FLOW_STAT_SYMMETRIC);
2977 u16 reg;
2978 u8 filter[8];
2979
2980 memset(filter, 0, sizeof(filter));
2981
2982 reg = gma_read16(hw, port, GM_RX_CTRL);
2983 reg |= GM_RXCR_UCF_ENA;
2984
2985 if (dev->flags & IFF_PROMISC) /* promiscuous */
2986 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2987 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2988 memset(filter, 0xff, sizeof(filter));
2989 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2990 reg &= ~GM_RXCR_MCF_ENA;
2991 else {
2992 reg |= GM_RXCR_MCF_ENA;
2993
2994 if (rx_pause)
2995 yukon_add_filter(filter, pause_mc_addr);
2996
2997 netdev_for_each_mc_addr(ha, dev)
2998 yukon_add_filter(filter, ha->addr);
2999 }
3000
3001
3002 gma_write16(hw, port, GM_MC_ADDR_H1,
3003 (u16)filter[0] | ((u16)filter[1] << 8));
3004 gma_write16(hw, port, GM_MC_ADDR_H2,
3005 (u16)filter[2] | ((u16)filter[3] << 8));
3006 gma_write16(hw, port, GM_MC_ADDR_H3,
3007 (u16)filter[4] | ((u16)filter[5] << 8));
3008 gma_write16(hw, port, GM_MC_ADDR_H4,
3009 (u16)filter[6] | ((u16)filter[7] << 8));
3010
3011 gma_write16(hw, port, GM_RX_CTRL, reg);
3012}
3013
3014static inline u16 phy_length(const struct skge_hw *hw, u32 status)
3015{
3016 if (is_genesis(hw))
3017 return status >> XMR_FS_LEN_SHIFT;
3018 else
3019 return status >> GMR_FS_LEN_SHIFT;
3020}
3021
3022static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
3023{
3024 if (is_genesis(hw))
3025 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
3026 else
3027 return (status & GMR_FS_ANY_ERR) ||
3028 (status & GMR_FS_RX_OK) == 0;
3029}
3030
3031static void skge_set_multicast(struct net_device *dev)
3032{
3033 struct skge_port *skge = netdev_priv(dev);
3034
3035 if (is_genesis(skge->hw))
3036 genesis_set_multicast(dev);
3037 else
3038 yukon_set_multicast(dev);
3039
3040}
3041
3042
3043/* Get receive buffer from descriptor.
3044 * Handles copy of small buffers and reallocation failures
3045 */
3046static struct sk_buff *skge_rx_get(struct net_device *dev,
3047 struct skge_element *e,
3048 u32 control, u32 status, u16 csum)
3049{
3050 struct skge_port *skge = netdev_priv(dev);
3051 struct sk_buff *skb;
3052 u16 len = control & BMU_BBC;
3053
3054 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
3055 "rx slot %td status 0x%x len %d\n",
3056 e - skge->rx_ring.start, status, len);
3057
3058 if (len > skge->rx_buf_size)
3059 goto error;
3060
3061 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3062 goto error;
3063
3064 if (bad_phy_status(skge->hw, status))
3065 goto error;
3066
3067 if (phy_length(skge->hw, status) != len)
3068 goto error;
3069
3070 if (len < RX_COPY_THRESHOLD) {
3071 skb = netdev_alloc_skb_ip_align(dev, len);
3072 if (!skb)
3073 goto resubmit;
3074
3075 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3076 dma_unmap_addr(e, mapaddr),
3077 dma_unmap_len(e, maplen),
3078 PCI_DMA_FROMDEVICE);
3079 skb_copy_from_linear_data(e->skb, skb->data, len);
3080 pci_dma_sync_single_for_device(skge->hw->pdev,
3081 dma_unmap_addr(e, mapaddr),
3082 dma_unmap_len(e, maplen),
3083 PCI_DMA_FROMDEVICE);
3084 skge_rx_reuse(e, skge->rx_buf_size);
3085 } else {
3086 struct skge_element ee;
3087 struct sk_buff *nskb;
3088
3089 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3090 if (!nskb)
3091 goto resubmit;
3092
3093 ee = *e;
3094
3095 skb = ee.skb;
3096 prefetch(skb->data);
3097
3098 if (skge_rx_setup(skge, e, nskb, skge->rx_buf_size) < 0) {
3099 dev_kfree_skb(nskb);
3100 goto resubmit;
3101 }
3102
3103 pci_unmap_single(skge->hw->pdev,
3104 dma_unmap_addr(&ee, mapaddr),
3105 dma_unmap_len(&ee, maplen),
3106 PCI_DMA_FROMDEVICE);
3107 }
3108
3109 skb_put(skb, len);
3110
3111 if (dev->features & NETIF_F_RXCSUM) {
3112 skb->csum = csum;
3113 skb->ip_summed = CHECKSUM_COMPLETE;
3114 }
3115
3116 skb->protocol = eth_type_trans(skb, dev);
3117
3118 return skb;
3119error:
3120
3121 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3122 "rx err, slot %td control 0x%x status 0x%x\n",
3123 e - skge->rx_ring.start, control, status);
3124
3125 if (is_genesis(skge->hw)) {
3126 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3127 dev->stats.rx_length_errors++;
3128 if (status & XMR_FS_FRA_ERR)
3129 dev->stats.rx_frame_errors++;
3130 if (status & XMR_FS_FCS_ERR)
3131 dev->stats.rx_crc_errors++;
3132 } else {
3133 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3134 dev->stats.rx_length_errors++;
3135 if (status & GMR_FS_FRAGMENT)
3136 dev->stats.rx_frame_errors++;
3137 if (status & GMR_FS_CRC_ERR)
3138 dev->stats.rx_crc_errors++;
3139 }
3140
3141resubmit:
3142 skge_rx_reuse(e, skge->rx_buf_size);
3143 return NULL;
3144}
3145
3146/* Free all buffers in Tx ring which are no longer owned by device */
3147static void skge_tx_done(struct net_device *dev)
3148{
3149 struct skge_port *skge = netdev_priv(dev);
3150 struct skge_ring *ring = &skge->tx_ring;
3151 struct skge_element *e;
3152 unsigned int bytes_compl = 0, pkts_compl = 0;
3153
3154 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3155
3156 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3157 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3158
3159 if (control & BMU_OWN)
3160 break;
3161
3162 skge_tx_unmap(skge->hw->pdev, e, control);
3163
3164 if (control & BMU_EOF) {
3165 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
3166 "tx done slot %td\n",
3167 e - skge->tx_ring.start);
3168
3169 pkts_compl++;
3170 bytes_compl += e->skb->len;
3171
3172 dev_consume_skb_any(e->skb);
3173 }
3174 }
3175 netdev_completed_queue(dev, pkts_compl, bytes_compl);
3176 skge->tx_ring.to_clean = e;
3177
3178 /* Can run lockless until we need to synchronize to restart queue. */
3179 smp_mb();
3180
3181 if (unlikely(netif_queue_stopped(dev) &&
3182 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3183 netif_tx_lock(dev);
3184 if (unlikely(netif_queue_stopped(dev) &&
3185 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3186 netif_wake_queue(dev);
3187
3188 }
3189 netif_tx_unlock(dev);
3190 }
3191}
3192
3193static int skge_poll(struct napi_struct *napi, int to_do)
3194{
3195 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3196 struct net_device *dev = skge->netdev;
3197 struct skge_hw *hw = skge->hw;
3198 struct skge_ring *ring = &skge->rx_ring;
3199 struct skge_element *e;
3200 int work_done = 0;
3201
3202 skge_tx_done(dev);
3203
3204 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3205
3206 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3207 struct skge_rx_desc *rd = e->desc;
3208 struct sk_buff *skb;
3209 u32 control;
3210
3211 rmb();
3212 control = rd->control;
3213 if (control & BMU_OWN)
3214 break;
3215
3216 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3217 if (likely(skb)) {
3218 napi_gro_receive(napi, skb);
3219 ++work_done;
3220 }
3221 }
3222 ring->to_clean = e;
3223
3224 /* restart receiver */
3225 wmb();
3226 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3227
3228 if (work_done < to_do) {
3229 unsigned long flags;
3230
3231 napi_gro_flush(napi, false);
3232 spin_lock_irqsave(&hw->hw_lock, flags);
3233 __napi_complete(napi);
3234 hw->intr_mask |= napimask[skge->port];
3235 skge_write32(hw, B0_IMSK, hw->intr_mask);
3236 skge_read32(hw, B0_IMSK);
3237 spin_unlock_irqrestore(&hw->hw_lock, flags);
3238 }
3239
3240 return work_done;
3241}
3242
3243/* Parity errors seem to happen when Genesis is connected to a switch
3244 * with no other ports present. Heartbeat error??
3245 */
3246static void skge_mac_parity(struct skge_hw *hw, int port)
3247{
3248 struct net_device *dev = hw->dev[port];
3249
3250 ++dev->stats.tx_heartbeat_errors;
3251
3252 if (is_genesis(hw))
3253 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3254 MFF_CLR_PERR);
3255 else
3256 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3257 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3258 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3259 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3260}
3261
3262static void skge_mac_intr(struct skge_hw *hw, int port)
3263{
3264 if (is_genesis(hw))
3265 genesis_mac_intr(hw, port);
3266 else
3267 yukon_mac_intr(hw, port);
3268}
3269
3270/* Handle device specific framing and timeout interrupts */
3271static void skge_error_irq(struct skge_hw *hw)
3272{
3273 struct pci_dev *pdev = hw->pdev;
3274 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3275
3276 if (is_genesis(hw)) {
3277 /* clear xmac errors */
3278 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3279 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3280 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3281 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3282 } else {
3283 /* Timestamp (unused) overflow */
3284 if (hwstatus & IS_IRQ_TIST_OV)
3285 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3286 }
3287
3288 if (hwstatus & IS_RAM_RD_PAR) {
3289 dev_err(&pdev->dev, "Ram read data parity error\n");
3290 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3291 }
3292
3293 if (hwstatus & IS_RAM_WR_PAR) {
3294 dev_err(&pdev->dev, "Ram write data parity error\n");
3295 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3296 }
3297
3298 if (hwstatus & IS_M1_PAR_ERR)
3299 skge_mac_parity(hw, 0);
3300
3301 if (hwstatus & IS_M2_PAR_ERR)
3302 skge_mac_parity(hw, 1);
3303
3304 if (hwstatus & IS_R1_PAR_ERR) {
3305 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3306 hw->dev[0]->name);
3307 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3308 }
3309
3310 if (hwstatus & IS_R2_PAR_ERR) {
3311 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3312 hw->dev[1]->name);
3313 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3314 }
3315
3316 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3317 u16 pci_status, pci_cmd;
3318
3319 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3320 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3321
3322 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3323 pci_cmd, pci_status);
3324
3325 /* Write the error bits back to clear them. */
3326 pci_status &= PCI_STATUS_ERROR_BITS;
3327 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3328 pci_write_config_word(pdev, PCI_COMMAND,
3329 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3330 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3331 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3332
3333 /* if error still set then just ignore it */
3334 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3335 if (hwstatus & IS_IRQ_STAT) {
3336 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3337 hw->intr_mask &= ~IS_HW_ERR;
3338 }
3339 }
3340}
3341
3342/*
3343 * Interrupt from PHY are handled in tasklet (softirq)
3344 * because accessing phy registers requires spin wait which might
3345 * cause excess interrupt latency.
3346 */
3347static void skge_extirq(unsigned long arg)
3348{
3349 struct skge_hw *hw = (struct skge_hw *) arg;
3350 int port;
3351
3352 for (port = 0; port < hw->ports; port++) {
3353 struct net_device *dev = hw->dev[port];
3354
3355 if (netif_running(dev)) {
3356 struct skge_port *skge = netdev_priv(dev);
3357
3358 spin_lock(&hw->phy_lock);
3359 if (!is_genesis(hw))
3360 yukon_phy_intr(skge);
3361 else if (hw->phy_type == SK_PHY_BCOM)
3362 bcom_phy_intr(skge);
3363 spin_unlock(&hw->phy_lock);
3364 }
3365 }
3366
3367 spin_lock_irq(&hw->hw_lock);
3368 hw->intr_mask |= IS_EXT_REG;
3369 skge_write32(hw, B0_IMSK, hw->intr_mask);
3370 skge_read32(hw, B0_IMSK);
3371 spin_unlock_irq(&hw->hw_lock);
3372}
3373
3374static irqreturn_t skge_intr(int irq, void *dev_id)
3375{
3376 struct skge_hw *hw = dev_id;
3377 u32 status;
3378 int handled = 0;
3379
3380 spin_lock(&hw->hw_lock);
3381 /* Reading this register masks IRQ */
3382 status = skge_read32(hw, B0_SP_ISRC);
3383 if (status == 0 || status == ~0)
3384 goto out;
3385
3386 handled = 1;
3387 status &= hw->intr_mask;
3388 if (status & IS_EXT_REG) {
3389 hw->intr_mask &= ~IS_EXT_REG;
3390 tasklet_schedule(&hw->phy_task);
3391 }
3392
3393 if (status & (IS_XA1_F|IS_R1_F)) {
3394 struct skge_port *skge = netdev_priv(hw->dev[0]);
3395 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3396 napi_schedule(&skge->napi);
3397 }
3398
3399 if (status & IS_PA_TO_TX1)
3400 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3401
3402 if (status & IS_PA_TO_RX1) {
3403 ++hw->dev[0]->stats.rx_over_errors;
3404 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3405 }
3406
3407
3408 if (status & IS_MAC1)
3409 skge_mac_intr(hw, 0);
3410
3411 if (hw->dev[1]) {
3412 struct skge_port *skge = netdev_priv(hw->dev[1]);
3413
3414 if (status & (IS_XA2_F|IS_R2_F)) {
3415 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3416 napi_schedule(&skge->napi);
3417 }
3418
3419 if (status & IS_PA_TO_RX2) {
3420 ++hw->dev[1]->stats.rx_over_errors;
3421 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3422 }
3423
3424 if (status & IS_PA_TO_TX2)
3425 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3426
3427 if (status & IS_MAC2)
3428 skge_mac_intr(hw, 1);
3429 }
3430
3431 if (status & IS_HW_ERR)
3432 skge_error_irq(hw);
3433out:
3434 skge_write32(hw, B0_IMSK, hw->intr_mask);
3435 skge_read32(hw, B0_IMSK);
3436 spin_unlock(&hw->hw_lock);
3437
3438 return IRQ_RETVAL(handled);
3439}
3440
3441#ifdef CONFIG_NET_POLL_CONTROLLER
3442static void skge_netpoll(struct net_device *dev)
3443{
3444 struct skge_port *skge = netdev_priv(dev);
3445
3446 disable_irq(dev->irq);
3447 skge_intr(dev->irq, skge->hw);
3448 enable_irq(dev->irq);
3449}
3450#endif
3451
3452static int skge_set_mac_address(struct net_device *dev, void *p)
3453{
3454 struct skge_port *skge = netdev_priv(dev);
3455 struct skge_hw *hw = skge->hw;
3456 unsigned port = skge->port;
3457 const struct sockaddr *addr = p;
3458 u16 ctrl;
3459
3460 if (!is_valid_ether_addr(addr->sa_data))
3461 return -EADDRNOTAVAIL;
3462
3463 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3464
3465 if (!netif_running(dev)) {
3466 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3467 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3468 } else {
3469 /* disable Rx */
3470 spin_lock_bh(&hw->phy_lock);
3471 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3472 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3473
3474 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3475 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3476
3477 if (is_genesis(hw))
3478 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3479 else {
3480 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3481 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3482 }
3483
3484 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3485 spin_unlock_bh(&hw->phy_lock);
3486 }
3487
3488 return 0;
3489}
3490
3491static const struct {
3492 u8 id;
3493 const char *name;
3494} skge_chips[] = {
3495 { CHIP_ID_GENESIS, "Genesis" },
3496 { CHIP_ID_YUKON, "Yukon" },
3497 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3498 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3499};
3500
3501static const char *skge_board_name(const struct skge_hw *hw)
3502{
3503 int i;
3504 static char buf[16];
3505
3506 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3507 if (skge_chips[i].id == hw->chip_id)
3508 return skge_chips[i].name;
3509
3510 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3511 return buf;
3512}
3513
3514
3515/*
3516 * Setup the board data structure, but don't bring up
3517 * the port(s)
3518 */
3519static int skge_reset(struct skge_hw *hw)
3520{
3521 u32 reg;
3522 u16 ctst, pci_status;
3523 u8 t8, mac_cfg, pmd_type;
3524 int i;
3525
3526 ctst = skge_read16(hw, B0_CTST);
3527
3528 /* do a SW reset */
3529 skge_write8(hw, B0_CTST, CS_RST_SET);
3530 skge_write8(hw, B0_CTST, CS_RST_CLR);
3531
3532 /* clear PCI errors, if any */
3533 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3534 skge_write8(hw, B2_TST_CTRL2, 0);
3535
3536 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3537 pci_write_config_word(hw->pdev, PCI_STATUS,
3538 pci_status | PCI_STATUS_ERROR_BITS);
3539 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3540 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3541
3542 /* restore CLK_RUN bits (for Yukon-Lite) */
3543 skge_write16(hw, B0_CTST,
3544 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3545
3546 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3547 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3548 pmd_type = skge_read8(hw, B2_PMD_TYP);
3549 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3550
3551 switch (hw->chip_id) {
3552 case CHIP_ID_GENESIS:
3553#ifdef CONFIG_SKGE_GENESIS
3554 switch (hw->phy_type) {
3555 case SK_PHY_XMAC:
3556 hw->phy_addr = PHY_ADDR_XMAC;
3557 break;
3558 case SK_PHY_BCOM:
3559 hw->phy_addr = PHY_ADDR_BCOM;
3560 break;
3561 default:
3562 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3563 hw->phy_type);
3564 return -EOPNOTSUPP;
3565 }
3566 break;
3567#else
3568 dev_err(&hw->pdev->dev, "Genesis chip detected but not configured\n");
3569 return -EOPNOTSUPP;
3570#endif
3571
3572 case CHIP_ID_YUKON:
3573 case CHIP_ID_YUKON_LITE:
3574 case CHIP_ID_YUKON_LP:
3575 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3576 hw->copper = 1;
3577
3578 hw->phy_addr = PHY_ADDR_MARV;
3579 break;
3580
3581 default:
3582 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3583 hw->chip_id);
3584 return -EOPNOTSUPP;
3585 }
3586
3587 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3588 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3589 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3590
3591 /* read the adapters RAM size */
3592 t8 = skge_read8(hw, B2_E_0);
3593 if (is_genesis(hw)) {
3594 if (t8 == 3) {
3595 /* special case: 4 x 64k x 36, offset = 0x80000 */
3596 hw->ram_size = 0x100000;
3597 hw->ram_offset = 0x80000;
3598 } else
3599 hw->ram_size = t8 * 512;
3600 } else if (t8 == 0)
3601 hw->ram_size = 0x20000;
3602 else
3603 hw->ram_size = t8 * 4096;
3604
3605 hw->intr_mask = IS_HW_ERR;
3606
3607 /* Use PHY IRQ for all but fiber based Genesis board */
3608 if (!(is_genesis(hw) && hw->phy_type == SK_PHY_XMAC))
3609 hw->intr_mask |= IS_EXT_REG;
3610
3611 if (is_genesis(hw))
3612 genesis_init(hw);
3613 else {
3614 /* switch power to VCC (WA for VAUX problem) */
3615 skge_write8(hw, B0_POWER_CTRL,
3616 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3617
3618 /* avoid boards with stuck Hardware error bits */
3619 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3620 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3621 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3622 hw->intr_mask &= ~IS_HW_ERR;
3623 }
3624
3625 /* Clear PHY COMA */
3626 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3627 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3628 reg &= ~PCI_PHY_COMA;
3629 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3630 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3631
3632
3633 for (i = 0; i < hw->ports; i++) {
3634 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3635 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3636 }
3637 }
3638
3639 /* turn off hardware timer (unused) */
3640 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3641 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3642 skge_write8(hw, B0_LED, LED_STAT_ON);
3643
3644 /* enable the Tx Arbiters */
3645 for (i = 0; i < hw->ports; i++)
3646 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3647
3648 /* Initialize ram interface */
3649 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3650
3651 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3652 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3653 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3654 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3655 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3656 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3657 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3658 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3659 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3660 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3661 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3662 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3663
3664 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3665
3666 /* Set interrupt moderation for Transmit only
3667 * Receive interrupts avoided by NAPI
3668 */
3669 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3670 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3671 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3672
3673 /* Leave irq disabled until first port is brought up. */
3674 skge_write32(hw, B0_IMSK, 0);
3675
3676 for (i = 0; i < hw->ports; i++) {
3677 if (is_genesis(hw))
3678 genesis_reset(hw, i);
3679 else
3680 yukon_reset(hw, i);
3681 }
3682
3683 return 0;
3684}
3685
3686
3687#ifdef CONFIG_SKGE_DEBUG
3688
3689static struct dentry *skge_debug;
3690
3691static int skge_debug_show(struct seq_file *seq, void *v)
3692{
3693 struct net_device *dev = seq->private;
3694 const struct skge_port *skge = netdev_priv(dev);
3695 const struct skge_hw *hw = skge->hw;
3696 const struct skge_element *e;
3697
3698 if (!netif_running(dev))
3699 return -ENETDOWN;
3700
3701 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3702 skge_read32(hw, B0_IMSK));
3703
3704 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3705 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3706 const struct skge_tx_desc *t = e->desc;
3707 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3708 t->control, t->dma_hi, t->dma_lo, t->status,
3709 t->csum_offs, t->csum_write, t->csum_start);
3710 }
3711
3712 seq_printf(seq, "\nRx Ring:\n");
3713 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3714 const struct skge_rx_desc *r = e->desc;
3715
3716 if (r->control & BMU_OWN)
3717 break;
3718
3719 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3720 r->control, r->dma_hi, r->dma_lo, r->status,
3721 r->timestamp, r->csum1, r->csum1_start);
3722 }
3723
3724 return 0;
3725}
3726
3727static int skge_debug_open(struct inode *inode, struct file *file)
3728{
3729 return single_open(file, skge_debug_show, inode->i_private);
3730}
3731
3732static const struct file_operations skge_debug_fops = {
3733 .owner = THIS_MODULE,
3734 .open = skge_debug_open,
3735 .read = seq_read,
3736 .llseek = seq_lseek,
3737 .release = single_release,
3738};
3739
3740/*
3741 * Use network device events to create/remove/rename
3742 * debugfs file entries
3743 */
3744static int skge_device_event(struct notifier_block *unused,
3745 unsigned long event, void *ptr)
3746{
3747 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
3748 struct skge_port *skge;
3749 struct dentry *d;
3750
3751 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3752 goto done;
3753
3754 skge = netdev_priv(dev);
3755 switch (event) {
3756 case NETDEV_CHANGENAME:
3757 if (skge->debugfs) {
3758 d = debugfs_rename(skge_debug, skge->debugfs,
3759 skge_debug, dev->name);
3760 if (d)
3761 skge->debugfs = d;
3762 else {
3763 netdev_info(dev, "rename failed\n");
3764 debugfs_remove(skge->debugfs);
3765 }
3766 }
3767 break;
3768
3769 case NETDEV_GOING_DOWN:
3770 if (skge->debugfs) {
3771 debugfs_remove(skge->debugfs);
3772 skge->debugfs = NULL;
3773 }
3774 break;
3775
3776 case NETDEV_UP:
3777 d = debugfs_create_file(dev->name, S_IRUGO,
3778 skge_debug, dev,
3779 &skge_debug_fops);
3780 if (!d || IS_ERR(d))
3781 netdev_info(dev, "debugfs create failed\n");
3782 else
3783 skge->debugfs = d;
3784 break;
3785 }
3786
3787done:
3788 return NOTIFY_DONE;
3789}
3790
3791static struct notifier_block skge_notifier = {
3792 .notifier_call = skge_device_event,
3793};
3794
3795
3796static __init void skge_debug_init(void)
3797{
3798 struct dentry *ent;
3799
3800 ent = debugfs_create_dir("skge", NULL);
3801 if (!ent || IS_ERR(ent)) {
3802 pr_info("debugfs create directory failed\n");
3803 return;
3804 }
3805
3806 skge_debug = ent;
3807 register_netdevice_notifier(&skge_notifier);
3808}
3809
3810static __exit void skge_debug_cleanup(void)
3811{
3812 if (skge_debug) {
3813 unregister_netdevice_notifier(&skge_notifier);
3814 debugfs_remove(skge_debug);
3815 skge_debug = NULL;
3816 }
3817}
3818
3819#else
3820#define skge_debug_init()
3821#define skge_debug_cleanup()
3822#endif
3823
3824static const struct net_device_ops skge_netdev_ops = {
3825 .ndo_open = skge_up,
3826 .ndo_stop = skge_down,
3827 .ndo_start_xmit = skge_xmit_frame,
3828 .ndo_do_ioctl = skge_ioctl,
3829 .ndo_get_stats = skge_get_stats,
3830 .ndo_tx_timeout = skge_tx_timeout,
3831 .ndo_change_mtu = skge_change_mtu,
3832 .ndo_validate_addr = eth_validate_addr,
3833 .ndo_set_rx_mode = skge_set_multicast,
3834 .ndo_set_mac_address = skge_set_mac_address,
3835#ifdef CONFIG_NET_POLL_CONTROLLER
3836 .ndo_poll_controller = skge_netpoll,
3837#endif
3838};
3839
3840
3841/* Initialize network device */
3842static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3843 int highmem)
3844{
3845 struct skge_port *skge;
3846 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3847
3848 if (!dev)
3849 return NULL;
3850
3851 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3852 dev->netdev_ops = &skge_netdev_ops;
3853 dev->ethtool_ops = &skge_ethtool_ops;
3854 dev->watchdog_timeo = TX_WATCHDOG;
3855 dev->irq = hw->pdev->irq;
3856
3857 /* MTU range: 60 - 9000 */
3858 dev->min_mtu = ETH_ZLEN;
3859 dev->max_mtu = ETH_JUMBO_MTU;
3860
3861 if (highmem)
3862 dev->features |= NETIF_F_HIGHDMA;
3863
3864 skge = netdev_priv(dev);
3865 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3866 skge->netdev = dev;
3867 skge->hw = hw;
3868 skge->msg_enable = netif_msg_init(debug, default_msg);
3869
3870 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3871 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3872
3873 /* Auto speed and flow control */
3874 skge->autoneg = AUTONEG_ENABLE;
3875 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3876 skge->duplex = -1;
3877 skge->speed = -1;
3878 skge->advertising = skge_supported_modes(hw);
3879
3880 if (device_can_wakeup(&hw->pdev->dev)) {
3881 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3882 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3883 }
3884
3885 hw->dev[port] = dev;
3886
3887 skge->port = port;
3888
3889 /* Only used for Genesis XMAC */
3890 if (is_genesis(hw))
3891 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3892 else {
3893 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3894 NETIF_F_RXCSUM;
3895 dev->features |= dev->hw_features;
3896 }
3897
3898 /* read the mac address */
3899 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3900
3901 return dev;
3902}
3903
3904static void skge_show_addr(struct net_device *dev)
3905{
3906 const struct skge_port *skge = netdev_priv(dev);
3907
3908 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3909}
3910
3911static int only_32bit_dma;
3912
3913static int skge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3914{
3915 struct net_device *dev, *dev1;
3916 struct skge_hw *hw;
3917 int err, using_dac = 0;
3918
3919 err = pci_enable_device(pdev);
3920 if (err) {
3921 dev_err(&pdev->dev, "cannot enable PCI device\n");
3922 goto err_out;
3923 }
3924
3925 err = pci_request_regions(pdev, DRV_NAME);
3926 if (err) {
3927 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3928 goto err_out_disable_pdev;
3929 }
3930
3931 pci_set_master(pdev);
3932
3933 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3934 using_dac = 1;
3935 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3936 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3937 using_dac = 0;
3938 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3939 }
3940
3941 if (err) {
3942 dev_err(&pdev->dev, "no usable DMA configuration\n");
3943 goto err_out_free_regions;
3944 }
3945
3946#ifdef __BIG_ENDIAN
3947 /* byte swap descriptors in hardware */
3948 {
3949 u32 reg;
3950
3951 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3952 reg |= PCI_REV_DESC;
3953 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3954 }
3955#endif
3956
3957 err = -ENOMEM;
3958 /* space for skge@pci:0000:04:00.0 */
3959 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3960 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3961 if (!hw)
3962 goto err_out_free_regions;
3963
3964 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3965
3966 hw->pdev = pdev;
3967 spin_lock_init(&hw->hw_lock);
3968 spin_lock_init(&hw->phy_lock);
3969 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3970
3971 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3972 if (!hw->regs) {
3973 dev_err(&pdev->dev, "cannot map device registers\n");
3974 goto err_out_free_hw;
3975 }
3976
3977 err = skge_reset(hw);
3978 if (err)
3979 goto err_out_iounmap;
3980
3981 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3982 DRV_VERSION,
3983 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3984 skge_board_name(hw), hw->chip_rev);
3985
3986 dev = skge_devinit(hw, 0, using_dac);
3987 if (!dev) {
3988 err = -ENOMEM;
3989 goto err_out_led_off;
3990 }
3991
3992 /* Some motherboards are broken and has zero in ROM. */
3993 if (!is_valid_ether_addr(dev->dev_addr))
3994 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3995
3996 err = register_netdev(dev);
3997 if (err) {
3998 dev_err(&pdev->dev, "cannot register net device\n");
3999 goto err_out_free_netdev;
4000 }
4001
4002 skge_show_addr(dev);
4003
4004 if (hw->ports > 1) {
4005 dev1 = skge_devinit(hw, 1, using_dac);
4006 if (!dev1) {
4007 err = -ENOMEM;
4008 goto err_out_unregister;
4009 }
4010
4011 err = register_netdev(dev1);
4012 if (err) {
4013 dev_err(&pdev->dev, "cannot register second net device\n");
4014 goto err_out_free_dev1;
4015 }
4016
4017 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED,
4018 hw->irq_name, hw);
4019 if (err) {
4020 dev_err(&pdev->dev, "cannot assign irq %d\n",
4021 pdev->irq);
4022 goto err_out_unregister_dev1;
4023 }
4024
4025 skge_show_addr(dev1);
4026 }
4027 pci_set_drvdata(pdev, hw);
4028
4029 return 0;
4030
4031err_out_unregister_dev1:
4032 unregister_netdev(dev1);
4033err_out_free_dev1:
4034 free_netdev(dev1);
4035err_out_unregister:
4036 unregister_netdev(dev);
4037err_out_free_netdev:
4038 free_netdev(dev);
4039err_out_led_off:
4040 skge_write16(hw, B0_LED, LED_STAT_OFF);
4041err_out_iounmap:
4042 iounmap(hw->regs);
4043err_out_free_hw:
4044 kfree(hw);
4045err_out_free_regions:
4046 pci_release_regions(pdev);
4047err_out_disable_pdev:
4048 pci_disable_device(pdev);
4049err_out:
4050 return err;
4051}
4052
4053static void skge_remove(struct pci_dev *pdev)
4054{
4055 struct skge_hw *hw = pci_get_drvdata(pdev);
4056 struct net_device *dev0, *dev1;
4057
4058 if (!hw)
4059 return;
4060
4061 dev1 = hw->dev[1];
4062 if (dev1)
4063 unregister_netdev(dev1);
4064 dev0 = hw->dev[0];
4065 unregister_netdev(dev0);
4066
4067 tasklet_kill(&hw->phy_task);
4068
4069 spin_lock_irq(&hw->hw_lock);
4070 hw->intr_mask = 0;
4071
4072 if (hw->ports > 1) {
4073 skge_write32(hw, B0_IMSK, 0);
4074 skge_read32(hw, B0_IMSK);
4075 free_irq(pdev->irq, hw);
4076 }
4077 spin_unlock_irq(&hw->hw_lock);
4078
4079 skge_write16(hw, B0_LED, LED_STAT_OFF);
4080 skge_write8(hw, B0_CTST, CS_RST_SET);
4081
4082 if (hw->ports > 1)
4083 free_irq(pdev->irq, hw);
4084 pci_release_regions(pdev);
4085 pci_disable_device(pdev);
4086 if (dev1)
4087 free_netdev(dev1);
4088 free_netdev(dev0);
4089
4090 iounmap(hw->regs);
4091 kfree(hw);
4092}
4093
4094#ifdef CONFIG_PM_SLEEP
4095static int skge_suspend(struct device *dev)
4096{
4097 struct pci_dev *pdev = to_pci_dev(dev);
4098 struct skge_hw *hw = pci_get_drvdata(pdev);
4099 int i;
4100
4101 if (!hw)
4102 return 0;
4103
4104 for (i = 0; i < hw->ports; i++) {
4105 struct net_device *dev = hw->dev[i];
4106 struct skge_port *skge = netdev_priv(dev);
4107
4108 if (netif_running(dev))
4109 skge_down(dev);
4110
4111 if (skge->wol)
4112 skge_wol_init(skge);
4113 }
4114
4115 skge_write32(hw, B0_IMSK, 0);
4116
4117 return 0;
4118}
4119
4120static int skge_resume(struct device *dev)
4121{
4122 struct pci_dev *pdev = to_pci_dev(dev);
4123 struct skge_hw *hw = pci_get_drvdata(pdev);
4124 int i, err;
4125
4126 if (!hw)
4127 return 0;
4128
4129 err = skge_reset(hw);
4130 if (err)
4131 goto out;
4132
4133 for (i = 0; i < hw->ports; i++) {
4134 struct net_device *dev = hw->dev[i];
4135
4136 if (netif_running(dev)) {
4137 err = skge_up(dev);
4138
4139 if (err) {
4140 netdev_err(dev, "could not up: %d\n", err);
4141 dev_close(dev);
4142 goto out;
4143 }
4144 }
4145 }
4146out:
4147 return err;
4148}
4149
4150static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4151#define SKGE_PM_OPS (&skge_pm_ops)
4152
4153#else
4154
4155#define SKGE_PM_OPS NULL
4156#endif /* CONFIG_PM_SLEEP */
4157
4158static void skge_shutdown(struct pci_dev *pdev)
4159{
4160 struct skge_hw *hw = pci_get_drvdata(pdev);
4161 int i;
4162
4163 if (!hw)
4164 return;
4165
4166 for (i = 0; i < hw->ports; i++) {
4167 struct net_device *dev = hw->dev[i];
4168 struct skge_port *skge = netdev_priv(dev);
4169
4170 if (skge->wol)
4171 skge_wol_init(skge);
4172 }
4173
4174 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4175 pci_set_power_state(pdev, PCI_D3hot);
4176}
4177
4178static struct pci_driver skge_driver = {
4179 .name = DRV_NAME,
4180 .id_table = skge_id_table,
4181 .probe = skge_probe,
4182 .remove = skge_remove,
4183 .shutdown = skge_shutdown,
4184 .driver.pm = SKGE_PM_OPS,
4185};
4186
4187static struct dmi_system_id skge_32bit_dma_boards[] = {
4188 {
4189 .ident = "Gigabyte nForce boards",
4190 .matches = {
4191 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4192 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4193 },
4194 },
4195 {
4196 .ident = "ASUS P5NSLI",
4197 .matches = {
4198 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
4199 DMI_MATCH(DMI_BOARD_NAME, "P5NSLI")
4200 },
4201 },
4202 {
4203 .ident = "FUJITSU SIEMENS A8NE-FM",
4204 .matches = {
4205 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTek Computer INC."),
4206 DMI_MATCH(DMI_BOARD_NAME, "A8NE-FM")
4207 },
4208 },
4209 {}
4210};
4211
4212static int __init skge_init_module(void)
4213{
4214 if (dmi_check_system(skge_32bit_dma_boards))
4215 only_32bit_dma = 1;
4216 skge_debug_init();
4217 return pci_register_driver(&skge_driver);
4218}
4219
4220static void __exit skge_cleanup_module(void)
4221{
4222 pci_unregister_driver(&skge_driver);
4223 skge_debug_cleanup();
4224}
4225
4226module_init(skge_init_module);
4227module_exit(skge_cleanup_module);