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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4#include "ixgbe_x540.h"
5#include "ixgbe_type.h"
6#include "ixgbe_common.h"
7#include "ixgbe_mbx.h"
8#include "ixgbe_phy.h"
9
10static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
11static int ixgbe_setup_fc_x550em(struct ixgbe_hw *);
12static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
13static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
14static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
15
16static int ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
17{
18 struct ixgbe_mac_info *mac = &hw->mac;
19 struct ixgbe_phy_info *phy = &hw->phy;
20 struct ixgbe_link_info *link = &hw->link;
21
22 /* Start with X540 invariants, since so simular */
23 ixgbe_get_invariants_X540(hw);
24
25 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
26 phy->ops.set_phy_power = NULL;
27
28 link->addr = IXGBE_CS4227;
29
30 return 0;
31}
32
33static int ixgbe_get_invariants_X550_x_fw(struct ixgbe_hw *hw)
34{
35 struct ixgbe_phy_info *phy = &hw->phy;
36
37 /* Start with X540 invariants, since so similar */
38 ixgbe_get_invariants_X540(hw);
39
40 phy->ops.set_phy_power = NULL;
41
42 return 0;
43}
44
45static int ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
46{
47 struct ixgbe_mac_info *mac = &hw->mac;
48 struct ixgbe_phy_info *phy = &hw->phy;
49
50 /* Start with X540 invariants, since so simular */
51 ixgbe_get_invariants_X540(hw);
52
53 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
54 phy->ops.set_phy_power = NULL;
55
56 return 0;
57}
58
59static int ixgbe_get_invariants_X550_a_fw(struct ixgbe_hw *hw)
60{
61 struct ixgbe_phy_info *phy = &hw->phy;
62
63 /* Start with X540 invariants, since so similar */
64 ixgbe_get_invariants_X540(hw);
65
66 phy->ops.set_phy_power = NULL;
67
68 return 0;
69}
70
71/** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
72 * @hw: pointer to hardware structure
73 **/
74static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
75{
76 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
77
78 if (hw->bus.lan_id) {
79 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
80 esdp |= IXGBE_ESDP_SDP1_DIR;
81 }
82 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
83 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
84 IXGBE_WRITE_FLUSH(hw);
85}
86
87/**
88 * ixgbe_read_cs4227 - Read CS4227 register
89 * @hw: pointer to hardware structure
90 * @reg: register number to write
91 * @value: pointer to receive value read
92 *
93 * Returns status code
94 */
95static int ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
96{
97 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
98}
99
100/**
101 * ixgbe_write_cs4227 - Write CS4227 register
102 * @hw: pointer to hardware structure
103 * @reg: register number to write
104 * @value: value to write to register
105 *
106 * Returns status code
107 */
108static int ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
109{
110 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
111}
112
113/**
114 * ixgbe_read_pe - Read register from port expander
115 * @hw: pointer to hardware structure
116 * @reg: register number to read
117 * @value: pointer to receive read value
118 *
119 * Returns status code
120 */
121static int ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
122{
123 int status;
124
125 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
126 if (status)
127 hw_err(hw, "port expander access failed with %d\n", status);
128 return status;
129}
130
131/**
132 * ixgbe_write_pe - Write register to port expander
133 * @hw: pointer to hardware structure
134 * @reg: register number to write
135 * @value: value to write
136 *
137 * Returns status code
138 */
139static int ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
140{
141 int status;
142
143 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
144 value);
145 if (status)
146 hw_err(hw, "port expander access failed with %d\n", status);
147 return status;
148}
149
150/**
151 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
152 * @hw: pointer to hardware structure
153 *
154 * This function assumes that the caller has acquired the proper semaphore.
155 * Returns error code
156 */
157static int ixgbe_reset_cs4227(struct ixgbe_hw *hw)
158{
159 int status;
160 u32 retry;
161 u16 value;
162 u8 reg;
163
164 /* Trigger hard reset. */
165 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
166 if (status)
167 return status;
168 reg |= IXGBE_PE_BIT1;
169 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
170 if (status)
171 return status;
172
173 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
174 if (status)
175 return status;
176 reg &= ~IXGBE_PE_BIT1;
177 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
178 if (status)
179 return status;
180
181 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
182 if (status)
183 return status;
184 reg &= ~IXGBE_PE_BIT1;
185 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
186 if (status)
187 return status;
188
189 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
190
191 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
192 if (status)
193 return status;
194 reg |= IXGBE_PE_BIT1;
195 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
196 if (status)
197 return status;
198
199 /* Wait for the reset to complete. */
200 msleep(IXGBE_CS4227_RESET_DELAY);
201 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
202 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
203 &value);
204 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
205 break;
206 msleep(IXGBE_CS4227_CHECK_DELAY);
207 }
208 if (retry == IXGBE_CS4227_RETRIES) {
209 hw_err(hw, "CS4227 reset did not complete\n");
210 return -EIO;
211 }
212
213 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
214 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
215 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
216 return -EIO;
217 }
218
219 return 0;
220}
221
222/**
223 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
224 * @hw: pointer to hardware structure
225 */
226static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
227{
228 u32 swfw_mask = hw->phy.phy_semaphore_mask;
229 int status;
230 u16 value;
231 u8 retry;
232
233 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
234 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
235 if (status) {
236 hw_err(hw, "semaphore failed with %d\n", status);
237 msleep(IXGBE_CS4227_CHECK_DELAY);
238 continue;
239 }
240
241 /* Get status of reset flow. */
242 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
243 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
244 goto out;
245
246 if (status || value != IXGBE_CS4227_RESET_PENDING)
247 break;
248
249 /* Reset is pending. Wait and check again. */
250 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
251 msleep(IXGBE_CS4227_CHECK_DELAY);
252 }
253 /* If still pending, assume other instance failed. */
254 if (retry == IXGBE_CS4227_RETRIES) {
255 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
256 if (status) {
257 hw_err(hw, "semaphore failed with %d\n", status);
258 return;
259 }
260 }
261
262 /* Reset the CS4227. */
263 status = ixgbe_reset_cs4227(hw);
264 if (status) {
265 hw_err(hw, "CS4227 reset failed: %d", status);
266 goto out;
267 }
268
269 /* Reset takes so long, temporarily release semaphore in case the
270 * other driver instance is waiting for the reset indication.
271 */
272 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
273 IXGBE_CS4227_RESET_PENDING);
274 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
275 usleep_range(10000, 12000);
276 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
277 if (status) {
278 hw_err(hw, "semaphore failed with %d", status);
279 return;
280 }
281
282 /* Record completion for next time. */
283 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
284 IXGBE_CS4227_RESET_COMPLETE);
285
286out:
287 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
288 msleep(hw->eeprom.semaphore_delay);
289}
290
291/** ixgbe_identify_phy_x550em - Get PHY type based on device id
292 * @hw: pointer to hardware structure
293 *
294 * Returns error code
295 */
296static int ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
297{
298 switch (hw->device_id) {
299 case IXGBE_DEV_ID_X550EM_A_SFP:
300 if (hw->bus.lan_id)
301 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
302 else
303 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
304 return ixgbe_identify_module_generic(hw);
305 case IXGBE_DEV_ID_X550EM_X_SFP:
306 /* set up for CS4227 usage */
307 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
308 ixgbe_setup_mux_ctl(hw);
309 ixgbe_check_cs4227(hw);
310 fallthrough;
311 case IXGBE_DEV_ID_X550EM_A_SFP_N:
312 return ixgbe_identify_module_generic(hw);
313 case IXGBE_DEV_ID_X550EM_X_KX4:
314 hw->phy.type = ixgbe_phy_x550em_kx4;
315 break;
316 case IXGBE_DEV_ID_X550EM_X_XFI:
317 hw->phy.type = ixgbe_phy_x550em_xfi;
318 break;
319 case IXGBE_DEV_ID_X550EM_X_KR:
320 case IXGBE_DEV_ID_X550EM_A_KR:
321 case IXGBE_DEV_ID_X550EM_A_KR_L:
322 hw->phy.type = ixgbe_phy_x550em_kr;
323 break;
324 case IXGBE_DEV_ID_X550EM_A_10G_T:
325 if (hw->bus.lan_id)
326 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
327 else
328 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
329 fallthrough;
330 case IXGBE_DEV_ID_X550EM_X_10G_T:
331 return ixgbe_identify_phy_generic(hw);
332 case IXGBE_DEV_ID_X550EM_X_1G_T:
333 hw->phy.type = ixgbe_phy_ext_1g_t;
334 break;
335 case IXGBE_DEV_ID_X550EM_A_1G_T:
336 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
337 hw->phy.type = ixgbe_phy_fw;
338 hw->phy.ops.read_reg = NULL;
339 hw->phy.ops.write_reg = NULL;
340 if (hw->bus.lan_id)
341 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY1_SM;
342 else
343 hw->phy.phy_semaphore_mask |= IXGBE_GSSR_PHY0_SM;
344 break;
345 default:
346 break;
347 }
348 return 0;
349}
350
351static int ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
352 u32 device_type, u16 *phy_data)
353{
354 return -EOPNOTSUPP;
355}
356
357static int ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
358 u32 device_type, u16 phy_data)
359{
360 return -EOPNOTSUPP;
361}
362
363/**
364 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
365 * @hw: pointer to the hardware structure
366 * @addr: I2C bus address to read from
367 * @reg: I2C device register to read from
368 * @val: pointer to location to receive read value
369 *
370 * Returns an error code on error.
371 **/
372static int ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
373 u16 reg, u16 *val)
374{
375 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
376}
377
378/**
379 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
380 * @hw: pointer to the hardware structure
381 * @addr: I2C bus address to read from
382 * @reg: I2C device register to read from
383 * @val: pointer to location to receive read value
384 *
385 * Returns an error code on error.
386 **/
387static int
388ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
389 u16 reg, u16 *val)
390{
391 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
392}
393
394/**
395 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
396 * @hw: pointer to the hardware structure
397 * @addr: I2C bus address to write to
398 * @reg: I2C device register to write to
399 * @val: value to write
400 *
401 * Returns an error code on error.
402 **/
403static int ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
404 u8 addr, u16 reg, u16 val)
405{
406 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
407}
408
409/**
410 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
411 * @hw: pointer to the hardware structure
412 * @addr: I2C bus address to write to
413 * @reg: I2C device register to write to
414 * @val: value to write
415 *
416 * Returns an error code on error.
417 **/
418static int
419ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
420 u8 addr, u16 reg, u16 val)
421{
422 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
423}
424
425/**
426 * ixgbe_fw_phy_activity - Perform an activity on a PHY
427 * @hw: pointer to hardware structure
428 * @activity: activity to perform
429 * @data: Pointer to 4 32-bit words of data
430 */
431int ixgbe_fw_phy_activity(struct ixgbe_hw *hw, u16 activity,
432 u32 (*data)[FW_PHY_ACT_DATA_COUNT])
433{
434 union {
435 struct ixgbe_hic_phy_activity_req cmd;
436 struct ixgbe_hic_phy_activity_resp rsp;
437 } hic;
438 u16 retries = FW_PHY_ACT_RETRIES;
439 int rc;
440 u32 i;
441
442 do {
443 memset(&hic, 0, sizeof(hic));
444 hic.cmd.hdr.cmd = FW_PHY_ACT_REQ_CMD;
445 hic.cmd.hdr.buf_len = FW_PHY_ACT_REQ_LEN;
446 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
447 hic.cmd.port_number = hw->bus.lan_id;
448 hic.cmd.activity_id = cpu_to_le16(activity);
449 for (i = 0; i < ARRAY_SIZE(hic.cmd.data); ++i)
450 hic.cmd.data[i] = cpu_to_be32((*data)[i]);
451
452 rc = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
453 IXGBE_HI_COMMAND_TIMEOUT,
454 true);
455 if (rc)
456 return rc;
457 if (hic.rsp.hdr.cmd_or_resp.ret_status ==
458 FW_CEM_RESP_STATUS_SUCCESS) {
459 for (i = 0; i < FW_PHY_ACT_DATA_COUNT; ++i)
460 (*data)[i] = be32_to_cpu(hic.rsp.data[i]);
461 return 0;
462 }
463 usleep_range(20, 30);
464 --retries;
465 } while (retries > 0);
466
467 return -EIO;
468}
469
470static const struct {
471 u16 fw_speed;
472 ixgbe_link_speed phy_speed;
473} ixgbe_fw_map[] = {
474 { FW_PHY_ACT_LINK_SPEED_10, IXGBE_LINK_SPEED_10_FULL },
475 { FW_PHY_ACT_LINK_SPEED_100, IXGBE_LINK_SPEED_100_FULL },
476 { FW_PHY_ACT_LINK_SPEED_1G, IXGBE_LINK_SPEED_1GB_FULL },
477 { FW_PHY_ACT_LINK_SPEED_2_5G, IXGBE_LINK_SPEED_2_5GB_FULL },
478 { FW_PHY_ACT_LINK_SPEED_5G, IXGBE_LINK_SPEED_5GB_FULL },
479 { FW_PHY_ACT_LINK_SPEED_10G, IXGBE_LINK_SPEED_10GB_FULL },
480};
481
482/**
483 * ixgbe_get_phy_id_fw - Get the phy ID via firmware command
484 * @hw: pointer to hardware structure
485 *
486 * Returns error code
487 */
488static int ixgbe_get_phy_id_fw(struct ixgbe_hw *hw)
489{
490 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
491 u16 phy_speeds;
492 u16 phy_id_lo;
493 int rc;
494 u16 i;
495
496 if (hw->phy.id)
497 return 0;
498
499 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_PHY_INFO, &info);
500 if (rc)
501 return rc;
502
503 hw->phy.speeds_supported = 0;
504 phy_speeds = info[0] & FW_PHY_INFO_SPEED_MASK;
505 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
506 if (phy_speeds & ixgbe_fw_map[i].fw_speed)
507 hw->phy.speeds_supported |= ixgbe_fw_map[i].phy_speed;
508 }
509
510 hw->phy.id = info[0] & FW_PHY_INFO_ID_HI_MASK;
511 phy_id_lo = info[1] & FW_PHY_INFO_ID_LO_MASK;
512 hw->phy.id |= phy_id_lo & IXGBE_PHY_REVISION_MASK;
513 hw->phy.revision = phy_id_lo & ~IXGBE_PHY_REVISION_MASK;
514 if (!hw->phy.id || hw->phy.id == IXGBE_PHY_REVISION_MASK)
515 return -EFAULT;
516
517 hw->phy.autoneg_advertised = hw->phy.speeds_supported;
518 hw->phy.eee_speeds_supported = IXGBE_LINK_SPEED_100_FULL |
519 IXGBE_LINK_SPEED_1GB_FULL;
520 hw->phy.eee_speeds_advertised = hw->phy.eee_speeds_supported;
521 return 0;
522}
523
524/**
525 * ixgbe_identify_phy_fw - Get PHY type based on firmware command
526 * @hw: pointer to hardware structure
527 *
528 * Returns error code
529 */
530static int ixgbe_identify_phy_fw(struct ixgbe_hw *hw)
531{
532 if (hw->bus.lan_id)
533 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
534 else
535 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
536
537 hw->phy.type = ixgbe_phy_fw;
538 hw->phy.ops.read_reg = NULL;
539 hw->phy.ops.write_reg = NULL;
540 return ixgbe_get_phy_id_fw(hw);
541}
542
543/**
544 * ixgbe_shutdown_fw_phy - Shutdown a firmware-controlled PHY
545 * @hw: pointer to hardware structure
546 *
547 * Returns error code
548 */
549static int ixgbe_shutdown_fw_phy(struct ixgbe_hw *hw)
550{
551 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
552
553 setup[0] = FW_PHY_ACT_FORCE_LINK_DOWN_OFF;
554 return ixgbe_fw_phy_activity(hw, FW_PHY_ACT_FORCE_LINK_DOWN, &setup);
555}
556
557/**
558 * ixgbe_setup_fw_link - Setup firmware-controlled PHYs
559 * @hw: pointer to hardware structure
560 */
561static int ixgbe_setup_fw_link(struct ixgbe_hw *hw)
562{
563 u32 setup[FW_PHY_ACT_DATA_COUNT] = { 0 };
564 int rc;
565 u16 i;
566
567 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
568 return 0;
569
570 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
571 hw_err(hw, "rx_pause not valid in strict IEEE mode\n");
572 return -EINVAL;
573 }
574
575 switch (hw->fc.requested_mode) {
576 case ixgbe_fc_full:
577 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX <<
578 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
579 break;
580 case ixgbe_fc_rx_pause:
581 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_RX <<
582 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
583 break;
584 case ixgbe_fc_tx_pause:
585 setup[0] |= FW_PHY_ACT_SETUP_LINK_PAUSE_TX <<
586 FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT;
587 break;
588 default:
589 break;
590 }
591
592 for (i = 0; i < ARRAY_SIZE(ixgbe_fw_map); ++i) {
593 if (hw->phy.autoneg_advertised & ixgbe_fw_map[i].phy_speed)
594 setup[0] |= ixgbe_fw_map[i].fw_speed;
595 }
596 setup[0] |= FW_PHY_ACT_SETUP_LINK_HP | FW_PHY_ACT_SETUP_LINK_AN;
597
598 if (hw->phy.eee_speeds_advertised)
599 setup[0] |= FW_PHY_ACT_SETUP_LINK_EEE;
600
601 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_SETUP_LINK, &setup);
602 if (rc)
603 return rc;
604
605 if (setup[0] == FW_PHY_ACT_SETUP_LINK_RSP_DOWN)
606 return -EIO;
607
608 return 0;
609}
610
611/**
612 * ixgbe_fc_autoneg_fw - Set up flow control for FW-controlled PHYs
613 * @hw: pointer to hardware structure
614 *
615 * Called at init time to set up flow control.
616 */
617static int ixgbe_fc_autoneg_fw(struct ixgbe_hw *hw)
618{
619 if (hw->fc.requested_mode == ixgbe_fc_default)
620 hw->fc.requested_mode = ixgbe_fc_full;
621
622 return ixgbe_setup_fw_link(hw);
623}
624
625/** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
626 * @hw: pointer to hardware structure
627 *
628 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
629 * ixgbe_hw struct in order to set up EEPROM access.
630 **/
631static int ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
632{
633 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
634
635 if (eeprom->type == ixgbe_eeprom_uninitialized) {
636 u16 eeprom_size;
637 u32 eec;
638
639 eeprom->semaphore_delay = 10;
640 eeprom->type = ixgbe_flash;
641
642 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
643 eeprom_size = FIELD_GET(IXGBE_EEC_SIZE, eec);
644 eeprom->word_size = BIT(eeprom_size +
645 IXGBE_EEPROM_WORD_SIZE_SHIFT);
646
647 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
648 eeprom->type, eeprom->word_size);
649 }
650
651 return 0;
652}
653
654/**
655 * ixgbe_iosf_wait - Wait for IOSF command completion
656 * @hw: pointer to hardware structure
657 * @ctrl: pointer to location to receive final IOSF control value
658 *
659 * Return: failing status on timeout
660 *
661 * Note: ctrl can be NULL if the IOSF control register value is not needed
662 */
663static int ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
664{
665 u32 i, command;
666
667 /* Check every 10 usec to see if the address cycle completed.
668 * The SB IOSF BUSY bit will clear when the operation is
669 * complete.
670 */
671 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
672 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
673 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
674 break;
675 udelay(10);
676 }
677 if (ctrl)
678 *ctrl = command;
679 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
680 hw_dbg(hw, "IOSF wait timed out\n");
681 return -EIO;
682 }
683
684 return 0;
685}
686
687/** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
688 * IOSF device
689 * @hw: pointer to hardware structure
690 * @reg_addr: 32 bit PHY register to write
691 * @device_type: 3 bit device type
692 * @phy_data: Pointer to read data from the register
693 **/
694static int ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
695 u32 device_type, u32 *data)
696{
697 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
698 u32 command, error;
699 int ret;
700
701 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
702 if (ret)
703 return ret;
704
705 ret = ixgbe_iosf_wait(hw, NULL);
706 if (ret)
707 goto out;
708
709 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
710 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
711
712 /* Write IOSF control register */
713 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
714
715 ret = ixgbe_iosf_wait(hw, &command);
716
717 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
718 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
719 hw_dbg(hw, "Failed to read, error %x\n", error);
720 ret = -EIO;
721 goto out;
722 }
723
724 if (!ret)
725 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
726
727out:
728 hw->mac.ops.release_swfw_sync(hw, gssr);
729 return ret;
730}
731
732/**
733 * ixgbe_get_phy_token - Get the token for shared PHY access
734 * @hw: Pointer to hardware structure
735 */
736static int ixgbe_get_phy_token(struct ixgbe_hw *hw)
737{
738 struct ixgbe_hic_phy_token_req token_cmd;
739 int status;
740
741 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
742 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
743 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
744 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
745 token_cmd.port_number = hw->bus.lan_id;
746 token_cmd.command_type = FW_PHY_TOKEN_REQ;
747 token_cmd.pad = 0;
748 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
749 IXGBE_HI_COMMAND_TIMEOUT,
750 true);
751 if (status)
752 return status;
753 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
754 return 0;
755 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
756 return -EIO;
757
758 return -EAGAIN;
759}
760
761/**
762 * ixgbe_put_phy_token - Put the token for shared PHY access
763 * @hw: Pointer to hardware structure
764 */
765static int ixgbe_put_phy_token(struct ixgbe_hw *hw)
766{
767 struct ixgbe_hic_phy_token_req token_cmd;
768 int status;
769
770 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
771 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
772 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
773 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
774 token_cmd.port_number = hw->bus.lan_id;
775 token_cmd.command_type = FW_PHY_TOKEN_REL;
776 token_cmd.pad = 0;
777 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
778 IXGBE_HI_COMMAND_TIMEOUT,
779 true);
780 if (status)
781 return status;
782 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
783 return 0;
784 return -EIO;
785}
786
787/**
788 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
789 * @hw: pointer to hardware structure
790 * @reg_addr: 32 bit PHY register to write
791 * @device_type: 3 bit device type
792 * @data: Data to write to the register
793 **/
794static int ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
795 __always_unused u32 device_type,
796 u32 data)
797{
798 struct ixgbe_hic_internal_phy_req write_cmd;
799
800 memset(&write_cmd, 0, sizeof(write_cmd));
801 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
802 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
803 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
804 write_cmd.port_number = hw->bus.lan_id;
805 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
806 write_cmd.address = cpu_to_be16(reg_addr);
807 write_cmd.write_data = cpu_to_be32(data);
808
809 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
810 IXGBE_HI_COMMAND_TIMEOUT, false);
811}
812
813/**
814 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
815 * @hw: pointer to hardware structure
816 * @reg_addr: 32 bit PHY register to write
817 * @device_type: 3 bit device type
818 * @data: Pointer to read data from the register
819 **/
820static int ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
821 __always_unused u32 device_type,
822 u32 *data)
823{
824 union {
825 struct ixgbe_hic_internal_phy_req cmd;
826 struct ixgbe_hic_internal_phy_resp rsp;
827 } hic;
828 int status;
829
830 memset(&hic, 0, sizeof(hic));
831 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
832 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
833 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
834 hic.cmd.port_number = hw->bus.lan_id;
835 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
836 hic.cmd.address = cpu_to_be16(reg_addr);
837
838 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
839 IXGBE_HI_COMMAND_TIMEOUT, true);
840
841 /* Extract the register value from the response. */
842 *data = be32_to_cpu(hic.rsp.read_data);
843
844 return status;
845}
846
847/** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
848 * @hw: pointer to hardware structure
849 * @offset: offset of word in the EEPROM to read
850 * @words: number of words
851 * @data: word(s) read from the EEPROM
852 *
853 * Reads a 16 bit word(s) from the EEPROM using the hostif.
854 **/
855static int ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
856 u16 offset, u16 words, u16 *data)
857{
858 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
859 struct ixgbe_hic_read_shadow_ram buffer;
860 u32 current_word = 0;
861 u16 words_to_read;
862 int status;
863 u32 i;
864
865 /* Take semaphore for the entire operation. */
866 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
867 if (status) {
868 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
869 return status;
870 }
871
872 while (words) {
873 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
874 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
875 else
876 words_to_read = words;
877
878 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
879 buffer.hdr.req.buf_lenh = 0;
880 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
881 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
882
883 /* convert offset from words to bytes */
884 buffer.address = (__force u32)cpu_to_be32((offset +
885 current_word) * 2);
886 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2);
887 buffer.pad2 = 0;
888 buffer.pad3 = 0;
889
890 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
891 IXGBE_HI_COMMAND_TIMEOUT);
892 if (status) {
893 hw_dbg(hw, "Host interface command failed\n");
894 goto out;
895 }
896
897 for (i = 0; i < words_to_read; i++) {
898 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
899 2 * i;
900 u32 value = IXGBE_READ_REG(hw, reg);
901
902 data[current_word] = (u16)(value & 0xffff);
903 current_word++;
904 i++;
905 if (i < words_to_read) {
906 value >>= 16;
907 data[current_word] = (u16)(value & 0xffff);
908 current_word++;
909 }
910 }
911 words -= words_to_read;
912 }
913
914out:
915 hw->mac.ops.release_swfw_sync(hw, mask);
916 return status;
917}
918
919/** ixgbe_checksum_ptr_x550 - Checksum one pointer region
920 * @hw: pointer to hardware structure
921 * @ptr: pointer offset in eeprom
922 * @size: size of section pointed by ptr, if 0 first word will be used as size
923 * @csum: address of checksum to update
924 *
925 * Returns error status for any failure
926 **/
927static int ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
928 u16 size, u16 *csum, u16 *buffer,
929 u32 buffer_size)
930{
931 u16 length, bufsz, i, start;
932 u16 *local_buffer;
933 u16 buf[256];
934 int status;
935
936 bufsz = ARRAY_SIZE(buf);
937
938 /* Read a chunk at the pointer location */
939 if (!buffer) {
940 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
941 if (status) {
942 hw_dbg(hw, "Failed to read EEPROM image\n");
943 return status;
944 }
945 local_buffer = buf;
946 } else {
947 if (buffer_size < ptr)
948 return -EINVAL;
949 local_buffer = &buffer[ptr];
950 }
951
952 if (size) {
953 start = 0;
954 length = size;
955 } else {
956 start = 1;
957 length = local_buffer[0];
958
959 /* Skip pointer section if length is invalid. */
960 if (length == 0xFFFF || length == 0 ||
961 (ptr + length) >= hw->eeprom.word_size)
962 return 0;
963 }
964
965 if (buffer && ((u32)start + (u32)length > buffer_size))
966 return -EINVAL;
967
968 for (i = start; length; i++, length--) {
969 if (i == bufsz && !buffer) {
970 ptr += bufsz;
971 i = 0;
972 if (length < bufsz)
973 bufsz = length;
974
975 /* Read a chunk at the pointer location */
976 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
977 bufsz, buf);
978 if (status) {
979 hw_dbg(hw, "Failed to read EEPROM image\n");
980 return status;
981 }
982 }
983 *csum += local_buffer[i];
984 }
985 return 0;
986}
987
988/** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
989 * @hw: pointer to hardware structure
990 * @buffer: pointer to buffer containing calculated checksum
991 * @buffer_size: size of buffer
992 *
993 * Returns a negative error code on error, or the 16-bit checksum
994 **/
995static int ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
996 u32 buffer_size)
997{
998 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
999 u16 pointer, i, size;
1000 u16 *local_buffer;
1001 u16 checksum = 0;
1002 int status;
1003
1004 hw->eeprom.ops.init_params(hw);
1005
1006 if (!buffer) {
1007 /* Read pointer area */
1008 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
1009 IXGBE_EEPROM_LAST_WORD + 1,
1010 eeprom_ptrs);
1011 if (status) {
1012 hw_dbg(hw, "Failed to read EEPROM image\n");
1013 return status;
1014 }
1015 local_buffer = eeprom_ptrs;
1016 } else {
1017 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
1018 return -EINVAL;
1019 local_buffer = buffer;
1020 }
1021
1022 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
1023 * checksum word itself
1024 */
1025 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
1026 if (i != IXGBE_EEPROM_CHECKSUM)
1027 checksum += local_buffer[i];
1028
1029 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
1030 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
1031 */
1032 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
1033 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
1034 continue;
1035
1036 pointer = local_buffer[i];
1037
1038 /* Skip pointer section if the pointer is invalid. */
1039 if (pointer == 0xFFFF || pointer == 0 ||
1040 pointer >= hw->eeprom.word_size)
1041 continue;
1042
1043 switch (i) {
1044 case IXGBE_PCIE_GENERAL_PTR:
1045 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
1046 break;
1047 case IXGBE_PCIE_CONFIG0_PTR:
1048 case IXGBE_PCIE_CONFIG1_PTR:
1049 size = IXGBE_PCIE_CONFIG_SIZE;
1050 break;
1051 default:
1052 size = 0;
1053 break;
1054 }
1055
1056 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
1057 buffer, buffer_size);
1058 if (status)
1059 return status;
1060 }
1061
1062 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
1063
1064 return (int)checksum;
1065}
1066
1067/** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
1068 * @hw: pointer to hardware structure
1069 *
1070 * Returns a negative error code on error, or the 16-bit checksum
1071 **/
1072static int ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
1073{
1074 return ixgbe_calc_checksum_X550(hw, NULL, 0);
1075}
1076
1077/** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
1078 * @hw: pointer to hardware structure
1079 * @offset: offset of word in the EEPROM to read
1080 * @data: word read from the EEPROM
1081 *
1082 * Reads a 16 bit word from the EEPROM using the hostif.
1083 **/
1084static int ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
1085{
1086 const u32 mask = IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_EEP_SM;
1087 struct ixgbe_hic_read_shadow_ram buffer;
1088 int status;
1089
1090 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
1091 buffer.hdr.req.buf_lenh = 0;
1092 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
1093 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1094
1095 /* convert offset from words to bytes */
1096 buffer.address = (__force u32)cpu_to_be32(offset * 2);
1097 /* one word */
1098 buffer.length = (__force u16)cpu_to_be16(sizeof(u16));
1099
1100 status = hw->mac.ops.acquire_swfw_sync(hw, mask);
1101 if (status)
1102 return status;
1103
1104 status = ixgbe_hic_unlocked(hw, (u32 *)&buffer, sizeof(buffer),
1105 IXGBE_HI_COMMAND_TIMEOUT);
1106 if (!status) {
1107 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
1108 FW_NVM_DATA_OFFSET);
1109 }
1110
1111 hw->mac.ops.release_swfw_sync(hw, mask);
1112 return status;
1113}
1114
1115/** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
1116 * @hw: pointer to hardware structure
1117 * @checksum_val: calculated checksum
1118 *
1119 * Performs checksum calculation and validates the EEPROM checksum. If the
1120 * caller does not need checksum_val, the value can be NULL.
1121 **/
1122static int ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
1123 u16 *checksum_val)
1124{
1125 u16 read_checksum = 0;
1126 u16 checksum;
1127 int status;
1128
1129 /* Read the first word from the EEPROM. If this times out or fails, do
1130 * not continue or we could be in for a very long wait while every
1131 * EEPROM read fails
1132 */
1133 status = hw->eeprom.ops.read(hw, 0, &checksum);
1134 if (status) {
1135 hw_dbg(hw, "EEPROM read failed\n");
1136 return status;
1137 }
1138
1139 status = hw->eeprom.ops.calc_checksum(hw);
1140 if (status < 0)
1141 return status;
1142
1143 checksum = (u16)(status & 0xffff);
1144
1145 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1146 &read_checksum);
1147 if (status)
1148 return status;
1149
1150 /* Verify read checksum from EEPROM is the same as
1151 * calculated checksum
1152 */
1153 if (read_checksum != checksum) {
1154 status = -EIO;
1155 hw_dbg(hw, "Invalid EEPROM checksum");
1156 }
1157
1158 /* If the user cares, return the calculated checksum */
1159 if (checksum_val)
1160 *checksum_val = checksum;
1161
1162 return status;
1163}
1164
1165/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1166 * @hw: pointer to hardware structure
1167 * @offset: offset of word in the EEPROM to write
1168 * @data: word write to the EEPROM
1169 *
1170 * Write a 16 bit word to the EEPROM using the hostif.
1171 **/
1172static int ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
1173 u16 data)
1174{
1175 struct ixgbe_hic_write_shadow_ram buffer;
1176 int status;
1177
1178 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
1179 buffer.hdr.req.buf_lenh = 0;
1180 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
1181 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
1182
1183 /* one word */
1184 buffer.length = cpu_to_be16(sizeof(u16));
1185 buffer.data = data;
1186 buffer.address = cpu_to_be32(offset * 2);
1187
1188 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1189 IXGBE_HI_COMMAND_TIMEOUT, false);
1190 return status;
1191}
1192
1193/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
1194 * @hw: pointer to hardware structure
1195 * @offset: offset of word in the EEPROM to write
1196 * @data: word write to the EEPROM
1197 *
1198 * Write a 16 bit word to the EEPROM using the hostif.
1199 **/
1200static int ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
1201{
1202 int status = 0;
1203
1204 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1205 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1206 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1207 } else {
1208 hw_dbg(hw, "write ee hostif failed to get semaphore");
1209 status = -EBUSY;
1210 }
1211
1212 return status;
1213}
1214
1215/** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1216 * @hw: pointer to hardware structure
1217 *
1218 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1219 **/
1220static int ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1221{
1222 union ixgbe_hic_hdr2 buffer;
1223 int status = 0;
1224
1225 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1226 buffer.req.buf_lenh = 0;
1227 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1228 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1229
1230 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1231 IXGBE_HI_COMMAND_TIMEOUT, false);
1232 return status;
1233}
1234
1235/**
1236 * ixgbe_get_bus_info_X550em - Set PCI bus info
1237 * @hw: pointer to hardware structure
1238 *
1239 * Sets bus link width and speed to unknown because X550em is
1240 * not a PCI device.
1241 **/
1242static int ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1243{
1244 hw->bus.type = ixgbe_bus_type_internal;
1245 hw->bus.width = ixgbe_bus_width_unknown;
1246 hw->bus.speed = ixgbe_bus_speed_unknown;
1247
1248 hw->mac.ops.set_lan_id(hw);
1249
1250 return 0;
1251}
1252
1253/**
1254 * ixgbe_fw_recovery_mode_X550 - Check FW NVM recovery mode
1255 * @hw: pointer t hardware structure
1256 *
1257 * Returns true if in FW NVM recovery mode.
1258 */
1259static bool ixgbe_fw_recovery_mode_X550(struct ixgbe_hw *hw)
1260{
1261 u32 fwsm;
1262
1263 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
1264 return !!(fwsm & IXGBE_FWSM_FW_NVM_RECOVERY_MODE);
1265}
1266
1267/** ixgbe_disable_rx_x550 - Disable RX unit
1268 *
1269 * Enables the Rx DMA unit for x550
1270 **/
1271static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1272{
1273 struct ixgbe_hic_disable_rxen fw_cmd;
1274 u32 rxctrl, pfdtxgswc;
1275 int status;
1276
1277 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1278 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1279 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1280 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1281 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1282 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1283 hw->mac.set_lben = true;
1284 } else {
1285 hw->mac.set_lben = false;
1286 }
1287
1288 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1289 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1290 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1291 fw_cmd.port_number = hw->bus.lan_id;
1292
1293 status = ixgbe_host_interface_command(hw, &fw_cmd,
1294 sizeof(struct ixgbe_hic_disable_rxen),
1295 IXGBE_HI_COMMAND_TIMEOUT, true);
1296
1297 /* If we fail - disable RX using register write */
1298 if (status) {
1299 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1300 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1301 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1302 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1303 }
1304 }
1305 }
1306}
1307
1308/** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1309 * @hw: pointer to hardware structure
1310 *
1311 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1312 * checksum and updates the EEPROM and instructs the hardware to update
1313 * the flash.
1314 **/
1315static int ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1316{
1317 u16 checksum = 0;
1318 int status;
1319
1320 /* Read the first word from the EEPROM. If this times out or fails, do
1321 * not continue or we could be in for a very long wait while every
1322 * EEPROM read fails
1323 */
1324 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1325 if (status) {
1326 hw_dbg(hw, "EEPROM read failed\n");
1327 return status;
1328 }
1329
1330 status = ixgbe_calc_eeprom_checksum_X550(hw);
1331 if (status < 0)
1332 return status;
1333
1334 checksum = (u16)(status & 0xffff);
1335
1336 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1337 checksum);
1338 if (status)
1339 return status;
1340
1341 status = ixgbe_update_flash_X550(hw);
1342
1343 return status;
1344}
1345
1346/** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1347 * @hw: pointer to hardware structure
1348 * @offset: offset of word in the EEPROM to write
1349 * @words: number of words
1350 * @data: word(s) write to the EEPROM
1351 *
1352 *
1353 * Write a 16 bit word(s) to the EEPROM using the hostif.
1354 **/
1355static int ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1356 u16 offset, u16 words,
1357 u16 *data)
1358{
1359 int status = 0;
1360 u32 i = 0;
1361
1362 /* Take semaphore for the entire operation. */
1363 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1364 if (status) {
1365 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1366 return status;
1367 }
1368
1369 for (i = 0; i < words; i++) {
1370 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1371 data[i]);
1372 if (status) {
1373 hw_dbg(hw, "Eeprom buffered write failed\n");
1374 break;
1375 }
1376 }
1377
1378 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1379
1380 return status;
1381}
1382
1383/** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1384 * IOSF device
1385 *
1386 * @hw: pointer to hardware structure
1387 * @reg_addr: 32 bit PHY register to write
1388 * @device_type: 3 bit device type
1389 * @data: Data to write to the register
1390 **/
1391static int ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1392 u32 device_type, u32 data)
1393{
1394 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1395 u32 command, error;
1396 int ret;
1397
1398 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1399 if (ret)
1400 return ret;
1401
1402 ret = ixgbe_iosf_wait(hw, NULL);
1403 if (ret)
1404 goto out;
1405
1406 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1407 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1408
1409 /* Write IOSF control register */
1410 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1411
1412 /* Write IOSF data register */
1413 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1414
1415 ret = ixgbe_iosf_wait(hw, &command);
1416
1417 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1418 error = FIELD_GET(IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK, command);
1419 hw_dbg(hw, "Failed to write, error %x\n", error);
1420 return -EIO;
1421 }
1422
1423out:
1424 hw->mac.ops.release_swfw_sync(hw, gssr);
1425 return ret;
1426}
1427
1428/**
1429 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1430 * @hw: pointer to hardware structure
1431 *
1432 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1433 **/
1434static int ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1435{
1436 u32 reg_val;
1437 int status;
1438
1439 /* Disable training protocol FSM. */
1440 status = ixgbe_read_iosf_sb_reg_x550(hw,
1441 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1442 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1443 if (status)
1444 return status;
1445
1446 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1447 status = ixgbe_write_iosf_sb_reg_x550(hw,
1448 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1449 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1450 if (status)
1451 return status;
1452
1453 /* Disable Flex from training TXFFE. */
1454 status = ixgbe_read_iosf_sb_reg_x550(hw,
1455 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1456 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1457 if (status)
1458 return status;
1459
1460 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1461 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1462 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1463 status = ixgbe_write_iosf_sb_reg_x550(hw,
1464 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1465 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1466 if (status)
1467 return status;
1468
1469 status = ixgbe_read_iosf_sb_reg_x550(hw,
1470 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1471 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1472 if (status)
1473 return status;
1474
1475 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1476 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1477 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1478 status = ixgbe_write_iosf_sb_reg_x550(hw,
1479 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1480 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1481 if (status)
1482 return status;
1483
1484 /* Enable override for coefficients. */
1485 status = ixgbe_read_iosf_sb_reg_x550(hw,
1486 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1487 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1488 if (status)
1489 return status;
1490
1491 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1492 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1493 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1494 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1495 status = ixgbe_write_iosf_sb_reg_x550(hw,
1496 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1497 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1498 return status;
1499}
1500
1501/**
1502 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1503 * internal PHY
1504 * @hw: pointer to hardware structure
1505 **/
1506static int ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1507{
1508 u32 link_ctrl;
1509 int status;
1510
1511 /* Restart auto-negotiation. */
1512 status = hw->mac.ops.read_iosf_sb_reg(hw,
1513 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1514 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1515
1516 if (status) {
1517 hw_dbg(hw, "Auto-negotiation did not complete\n");
1518 return status;
1519 }
1520
1521 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1522 status = hw->mac.ops.write_iosf_sb_reg(hw,
1523 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1524 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1525
1526 if (hw->mac.type == ixgbe_mac_x550em_a) {
1527 u32 flx_mask_st20;
1528
1529 /* Indicate to FW that AN restart has been asserted */
1530 status = hw->mac.ops.read_iosf_sb_reg(hw,
1531 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1532 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1533
1534 if (status) {
1535 hw_dbg(hw, "Auto-negotiation did not complete\n");
1536 return status;
1537 }
1538
1539 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1540 status = hw->mac.ops.write_iosf_sb_reg(hw,
1541 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1542 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1543 }
1544
1545 return status;
1546}
1547
1548/** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1549 * @hw: pointer to hardware structure
1550 * @speed: the link speed to force
1551 *
1552 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1553 * internal and external PHY at a specific speed, without autonegotiation.
1554 **/
1555static int ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1556{
1557 struct ixgbe_mac_info *mac = &hw->mac;
1558 u32 reg_val;
1559 int status;
1560
1561 /* iXFI is only supported with X552 */
1562 if (mac->type != ixgbe_mac_X550EM_x)
1563 return -EIO;
1564
1565 /* Disable AN and force speed to 10G Serial. */
1566 status = ixgbe_read_iosf_sb_reg_x550(hw,
1567 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1568 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1569 if (status)
1570 return status;
1571
1572 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1573 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1574
1575 /* Select forced link speed for internal PHY. */
1576 switch (*speed) {
1577 case IXGBE_LINK_SPEED_10GB_FULL:
1578 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1579 break;
1580 case IXGBE_LINK_SPEED_1GB_FULL:
1581 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1582 break;
1583 default:
1584 /* Other link speeds are not supported by internal KR PHY. */
1585 return -EINVAL;
1586 }
1587
1588 status = ixgbe_write_iosf_sb_reg_x550(hw,
1589 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1590 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1591 if (status)
1592 return status;
1593
1594 /* Additional configuration needed for x550em_x */
1595 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1596 status = ixgbe_setup_ixfi_x550em_x(hw);
1597 if (status)
1598 return status;
1599 }
1600
1601 /* Toggle port SW reset by AN reset. */
1602 status = ixgbe_restart_an_internal_phy_x550em(hw);
1603
1604 return status;
1605}
1606
1607/**
1608 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1609 * @hw: pointer to hardware structure
1610 * @linear: true if SFP module is linear
1611 */
1612static int ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1613{
1614 switch (hw->phy.sfp_type) {
1615 case ixgbe_sfp_type_not_present:
1616 return -ENOENT;
1617 case ixgbe_sfp_type_da_cu_core0:
1618 case ixgbe_sfp_type_da_cu_core1:
1619 *linear = true;
1620 break;
1621 case ixgbe_sfp_type_srlr_core0:
1622 case ixgbe_sfp_type_srlr_core1:
1623 case ixgbe_sfp_type_da_act_lmt_core0:
1624 case ixgbe_sfp_type_da_act_lmt_core1:
1625 case ixgbe_sfp_type_1g_sx_core0:
1626 case ixgbe_sfp_type_1g_sx_core1:
1627 case ixgbe_sfp_type_1g_lx_core0:
1628 case ixgbe_sfp_type_1g_lx_core1:
1629 *linear = false;
1630 break;
1631 case ixgbe_sfp_type_unknown:
1632 case ixgbe_sfp_type_1g_cu_core0:
1633 case ixgbe_sfp_type_1g_cu_core1:
1634 default:
1635 return -EOPNOTSUPP;
1636 }
1637
1638 return 0;
1639}
1640
1641/**
1642 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1643 * @hw: pointer to hardware structure
1644 * @speed: the link speed to force
1645 * @autoneg_wait_to_complete: unused
1646 *
1647 * Configures the extern PHY and the integrated KR PHY for SFP support.
1648 */
1649static int
1650ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1651 ixgbe_link_speed speed,
1652 __always_unused bool autoneg_wait_to_complete)
1653{
1654 bool setup_linear = false;
1655 u16 reg_slice, reg_val;
1656 int status;
1657
1658 /* Check if SFP module is supported and linear */
1659 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1660
1661 /* If no SFP module present, then return success. Return success since
1662 * there is no reason to configure CS4227 and SFP not present error is
1663 * not accepted in the setup MAC link flow.
1664 */
1665 if (status == -ENOENT)
1666 return 0;
1667
1668 if (status)
1669 return status;
1670
1671 /* Configure internal PHY for KR/KX. */
1672 ixgbe_setup_kr_speed_x550em(hw, speed);
1673
1674 /* Configure CS4227 LINE side to proper mode. */
1675 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1676 if (setup_linear)
1677 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1678 else
1679 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1680
1681 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1682 reg_val);
1683
1684 return status;
1685}
1686
1687/**
1688 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1689 * @hw: pointer to hardware structure
1690 * @speed: the link speed to force
1691 *
1692 * Configures the integrated PHY for native SFI mode. Used to connect the
1693 * internal PHY directly to an SFP cage, without autonegotiation.
1694 **/
1695static int ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1696{
1697 struct ixgbe_mac_info *mac = &hw->mac;
1698 u32 reg_val;
1699 int status;
1700
1701 /* Disable all AN and force speed to 10G Serial. */
1702 status = mac->ops.read_iosf_sb_reg(hw,
1703 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1704 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1705 if (status)
1706 return status;
1707
1708 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1709 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1710 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1711 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1712
1713 /* Select forced link speed for internal PHY. */
1714 switch (*speed) {
1715 case IXGBE_LINK_SPEED_10GB_FULL:
1716 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1717 break;
1718 case IXGBE_LINK_SPEED_1GB_FULL:
1719 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1720 break;
1721 default:
1722 /* Other link speeds are not supported by internal PHY. */
1723 return -EINVAL;
1724 }
1725
1726 status = mac->ops.write_iosf_sb_reg(hw,
1727 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1728 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1729
1730 /* Toggle port SW reset by AN reset. */
1731 status = ixgbe_restart_an_internal_phy_x550em(hw);
1732
1733 return status;
1734}
1735
1736/**
1737 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1738 * @hw: pointer to hardware structure
1739 * @speed: link speed
1740 * @autoneg_wait_to_complete: unused
1741 *
1742 * Configure the integrated PHY for native SFP support.
1743 */
1744static int
1745ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1746 __always_unused bool autoneg_wait_to_complete)
1747{
1748 bool setup_linear = false;
1749 u32 reg_phy_int;
1750 int ret_val;
1751
1752 /* Check if SFP module is supported and linear */
1753 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1754
1755 /* If no SFP module present, then return success. Return success since
1756 * SFP not present error is not excepted in the setup MAC link flow.
1757 */
1758 if (ret_val == -ENOENT)
1759 return 0;
1760
1761 if (ret_val)
1762 return ret_val;
1763
1764 /* Configure internal PHY for native SFI based on module type */
1765 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1766 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1767 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
1768 if (ret_val)
1769 return ret_val;
1770
1771 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1772 if (!setup_linear)
1773 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1774
1775 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1776 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1777 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1778 if (ret_val)
1779 return ret_val;
1780
1781 /* Setup SFI internal link. */
1782 return ixgbe_setup_sfi_x550a(hw, &speed);
1783}
1784
1785/**
1786 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1787 * @hw: pointer to hardware structure
1788 * @speed: link speed
1789 * @autoneg_wait_to_complete: unused
1790 *
1791 * Configure the integrated PHY for SFP support.
1792 */
1793static int
1794ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1795 __always_unused bool autoneg_wait_to_complete)
1796{
1797 u32 reg_slice, slice_offset;
1798 bool setup_linear = false;
1799 u16 reg_phy_ext;
1800 int ret_val;
1801
1802 /* Check if SFP module is supported and linear */
1803 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1804
1805 /* If no SFP module present, then return success. Return success since
1806 * SFP not present error is not excepted in the setup MAC link flow.
1807 */
1808 if (ret_val == -ENOENT)
1809 return 0;
1810
1811 if (ret_val)
1812 return ret_val;
1813
1814 /* Configure internal PHY for KR/KX. */
1815 ixgbe_setup_kr_speed_x550em(hw, speed);
1816
1817 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1818 return -EFAULT;
1819
1820 /* Get external PHY SKU id */
1821 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_EFUSE_PDF_SKU,
1822 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1823 if (ret_val)
1824 return ret_val;
1825
1826 /* When configuring quad port CS4223, the MAC instance is part
1827 * of the slice offset.
1828 */
1829 if (reg_phy_ext == IXGBE_CS4223_SKU_ID)
1830 slice_offset = (hw->bus.lan_id +
1831 (hw->bus.instance_id << 1)) << 12;
1832 else
1833 slice_offset = hw->bus.lan_id << 12;
1834
1835 /* Configure CS4227/CS4223 LINE side to proper mode. */
1836 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1837
1838 ret_val = hw->phy.ops.read_reg(hw, reg_slice,
1839 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1840 if (ret_val)
1841 return ret_val;
1842
1843 reg_phy_ext &= ~((IXGBE_CS4227_EDC_MODE_CX1 << 1) |
1844 (IXGBE_CS4227_EDC_MODE_SR << 1));
1845
1846 if (setup_linear)
1847 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1848 else
1849 reg_phy_ext |= (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1850
1851 ret_val = hw->phy.ops.write_reg(hw, reg_slice,
1852 IXGBE_MDIO_ZERO_DEV_TYPE, reg_phy_ext);
1853 if (ret_val)
1854 return ret_val;
1855
1856 /* Flush previous write with a read */
1857 return hw->phy.ops.read_reg(hw, reg_slice,
1858 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1859}
1860
1861/**
1862 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1863 * @hw: pointer to hardware structure
1864 * @speed: new link speed
1865 * @autoneg_wait: true when waiting for completion is needed
1866 *
1867 * Setup internal/external PHY link speed based on link speed, then set
1868 * external PHY auto advertised link speed.
1869 *
1870 * Returns error status for any failure
1871 **/
1872static int ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1873 ixgbe_link_speed speed,
1874 bool autoneg_wait)
1875{
1876 ixgbe_link_speed force_speed;
1877 int status;
1878
1879 /* Setup internal/external PHY link speed to iXFI (10G), unless
1880 * only 1G is auto advertised then setup KX link.
1881 */
1882 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1883 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1884 else
1885 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1886
1887 /* If X552 and internal link mode is XFI, then setup XFI internal link.
1888 */
1889 if (hw->mac.type == ixgbe_mac_X550EM_x &&
1890 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1891 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1892
1893 if (status)
1894 return status;
1895 }
1896
1897 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1898}
1899
1900/** ixgbe_check_link_t_X550em - Determine link and speed status
1901 * @hw: pointer to hardware structure
1902 * @speed: pointer to link speed
1903 * @link_up: true when link is up
1904 * @link_up_wait_to_complete: bool used to wait for link up or not
1905 *
1906 * Check that both the MAC and X557 external PHY have link.
1907 **/
1908static int ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1909 ixgbe_link_speed *speed,
1910 bool *link_up,
1911 bool link_up_wait_to_complete)
1912{
1913 u32 status;
1914 u16 i, autoneg_status;
1915
1916 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1917 return -EIO;
1918
1919 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1920 link_up_wait_to_complete);
1921
1922 /* If check link fails or MAC link is not up, then return */
1923 if (status || !(*link_up))
1924 return status;
1925
1926 /* MAC link is up, so check external PHY link.
1927 * Link status is latching low, and can only be used to detect link
1928 * drop, and not the current status of the link without performing
1929 * back-to-back reads.
1930 */
1931 for (i = 0; i < 2; i++) {
1932 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1933 &autoneg_status);
1934
1935 if (status)
1936 return status;
1937 }
1938
1939 /* If external PHY link is not up, then indicate link not up */
1940 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1941 *link_up = false;
1942
1943 return 0;
1944}
1945
1946/**
1947 * ixgbe_setup_sgmii - Set up link for sgmii
1948 * @hw: pointer to hardware structure
1949 * @speed: unused
1950 * @autoneg_wait_to_complete: unused
1951 */
1952static int
1953ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1954 __always_unused bool autoneg_wait_to_complete)
1955{
1956 struct ixgbe_mac_info *mac = &hw->mac;
1957 u32 lval, sval, flx_val;
1958 int rc;
1959
1960 rc = mac->ops.read_iosf_sb_reg(hw,
1961 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1962 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1963 if (rc)
1964 return rc;
1965
1966 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1967 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1968 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1969 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1970 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1971 rc = mac->ops.write_iosf_sb_reg(hw,
1972 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1973 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1974 if (rc)
1975 return rc;
1976
1977 rc = mac->ops.read_iosf_sb_reg(hw,
1978 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1979 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1980 if (rc)
1981 return rc;
1982
1983 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1984 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1985 rc = mac->ops.write_iosf_sb_reg(hw,
1986 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1987 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1988 if (rc)
1989 return rc;
1990
1991 rc = mac->ops.read_iosf_sb_reg(hw,
1992 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1993 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1994 if (rc)
1995 return rc;
1996
1997 rc = mac->ops.read_iosf_sb_reg(hw,
1998 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1999 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2000 if (rc)
2001 return rc;
2002
2003 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2004 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
2005 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2006 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2007 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2008
2009 rc = mac->ops.write_iosf_sb_reg(hw,
2010 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2011 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2012 if (rc)
2013 return rc;
2014
2015 rc = ixgbe_restart_an_internal_phy_x550em(hw);
2016 return rc;
2017}
2018
2019/**
2020 * ixgbe_setup_sgmii_fw - Set up link for sgmii with firmware-controlled PHYs
2021 * @hw: pointer to hardware structure
2022 * @speed: the link speed to force
2023 * @autoneg_wait: true when waiting for completion is needed
2024 */
2025static int ixgbe_setup_sgmii_fw(struct ixgbe_hw *hw, ixgbe_link_speed speed,
2026 bool autoneg_wait)
2027{
2028 struct ixgbe_mac_info *mac = &hw->mac;
2029 u32 lval, sval, flx_val;
2030 int rc;
2031
2032 rc = mac->ops.read_iosf_sb_reg(hw,
2033 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2034 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
2035 if (rc)
2036 return rc;
2037
2038 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2039 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
2040 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
2041 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
2042 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
2043 rc = mac->ops.write_iosf_sb_reg(hw,
2044 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2045 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2046 if (rc)
2047 return rc;
2048
2049 rc = mac->ops.read_iosf_sb_reg(hw,
2050 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2051 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
2052 if (rc)
2053 return rc;
2054
2055 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
2056 sval &= ~IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
2057 rc = mac->ops.write_iosf_sb_reg(hw,
2058 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
2059 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
2060 if (rc)
2061 return rc;
2062
2063 rc = mac->ops.write_iosf_sb_reg(hw,
2064 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2065 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
2066 if (rc)
2067 return rc;
2068
2069 rc = mac->ops.read_iosf_sb_reg(hw,
2070 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2071 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
2072 if (rc)
2073 return rc;
2074
2075 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2076 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2077 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2078 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2079 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2080
2081 rc = mac->ops.write_iosf_sb_reg(hw,
2082 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2083 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
2084 if (rc)
2085 return rc;
2086
2087 ixgbe_restart_an_internal_phy_x550em(hw);
2088
2089 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
2090}
2091
2092/**
2093 * ixgbe_fc_autoneg_sgmii_x550em_a - Enable flow control IEEE clause 37
2094 * @hw: pointer to hardware structure
2095 *
2096 * Enable flow control according to IEEE clause 37.
2097 */
2098static void ixgbe_fc_autoneg_sgmii_x550em_a(struct ixgbe_hw *hw)
2099{
2100 u32 info[FW_PHY_ACT_DATA_COUNT] = { 0 };
2101 ixgbe_link_speed speed;
2102 int status = -EIO;
2103 bool link_up;
2104
2105 /* AN should have completed when the cable was plugged in.
2106 * Look for reasons to bail out. Bail out if:
2107 * - FC autoneg is disabled, or if
2108 * - link is not up.
2109 */
2110 if (hw->fc.disable_fc_autoneg)
2111 goto out;
2112
2113 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2114 if (!link_up)
2115 goto out;
2116
2117 /* Check if auto-negotiation has completed */
2118 status = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &info);
2119 if (status || !(info[0] & FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE)) {
2120 status = -EIO;
2121 goto out;
2122 }
2123
2124 /* Negotiate the flow control */
2125 status = ixgbe_negotiate_fc(hw, info[0], info[0],
2126 FW_PHY_ACT_GET_LINK_INFO_FC_RX,
2127 FW_PHY_ACT_GET_LINK_INFO_FC_TX,
2128 FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX,
2129 FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX);
2130
2131out:
2132 if (!status) {
2133 hw->fc.fc_was_autonegged = true;
2134 } else {
2135 hw->fc.fc_was_autonegged = false;
2136 hw->fc.current_mode = hw->fc.requested_mode;
2137 }
2138}
2139
2140/** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
2141 * @hw: pointer to hardware structure
2142 **/
2143static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
2144{
2145 struct ixgbe_mac_info *mac = &hw->mac;
2146
2147 switch (mac->ops.get_media_type(hw)) {
2148 case ixgbe_media_type_fiber:
2149 mac->ops.setup_fc = NULL;
2150 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
2151 break;
2152 case ixgbe_media_type_copper:
2153 if (hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T &&
2154 hw->device_id != IXGBE_DEV_ID_X550EM_A_1G_T_L) {
2155 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2156 break;
2157 }
2158 mac->ops.fc_autoneg = ixgbe_fc_autoneg_sgmii_x550em_a;
2159 mac->ops.setup_fc = ixgbe_fc_autoneg_fw;
2160 mac->ops.setup_link = ixgbe_setup_sgmii_fw;
2161 mac->ops.check_link = ixgbe_check_mac_link_generic;
2162 break;
2163 case ixgbe_media_type_backplane:
2164 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
2165 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
2166 break;
2167 default:
2168 break;
2169 }
2170}
2171
2172/** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
2173 * @hw: pointer to hardware structure
2174 **/
2175static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
2176{
2177 struct ixgbe_mac_info *mac = &hw->mac;
2178
2179 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
2180
2181 switch (mac->ops.get_media_type(hw)) {
2182 case ixgbe_media_type_fiber:
2183 /* CS4227 does not support autoneg, so disable the laser control
2184 * functions for SFP+ fiber
2185 */
2186 mac->ops.disable_tx_laser = NULL;
2187 mac->ops.enable_tx_laser = NULL;
2188 mac->ops.flap_tx_laser = NULL;
2189 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
2190 switch (hw->device_id) {
2191 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2192 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
2193 break;
2194 case IXGBE_DEV_ID_X550EM_A_SFP:
2195 mac->ops.setup_mac_link =
2196 ixgbe_setup_mac_link_sfp_x550a;
2197 break;
2198 default:
2199 mac->ops.setup_mac_link =
2200 ixgbe_setup_mac_link_sfp_x550em;
2201 break;
2202 }
2203 mac->ops.set_rate_select_speed =
2204 ixgbe_set_soft_rate_select_speed;
2205 break;
2206 case ixgbe_media_type_copper:
2207 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_1G_T)
2208 break;
2209 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
2210 mac->ops.setup_fc = ixgbe_setup_fc_generic;
2211 mac->ops.check_link = ixgbe_check_link_t_X550em;
2212 break;
2213 case ixgbe_media_type_backplane:
2214 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
2215 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
2216 mac->ops.setup_link = ixgbe_setup_sgmii;
2217 break;
2218 default:
2219 break;
2220 }
2221
2222 /* Additional modification for X550em_a devices */
2223 if (hw->mac.type == ixgbe_mac_x550em_a)
2224 ixgbe_init_mac_link_ops_X550em_a(hw);
2225}
2226
2227/** ixgbe_setup_sfp_modules_X550em - Setup SFP module
2228 * @hw: pointer to hardware structure
2229 */
2230static int ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
2231{
2232 bool linear;
2233 int status;
2234
2235 /* Check if SFP module is supported */
2236 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
2237 if (status)
2238 return status;
2239
2240 ixgbe_init_mac_link_ops_X550em(hw);
2241 hw->phy.ops.reset = NULL;
2242
2243 return 0;
2244}
2245
2246/** ixgbe_get_link_capabilities_x550em - Determines link capabilities
2247 * @hw: pointer to hardware structure
2248 * @speed: pointer to link speed
2249 * @autoneg: true when autoneg or autotry is enabled
2250 **/
2251static int ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
2252 ixgbe_link_speed *speed,
2253 bool *autoneg)
2254{
2255 if (hw->phy.type == ixgbe_phy_fw) {
2256 *autoneg = true;
2257 *speed = hw->phy.speeds_supported;
2258 return 0;
2259 }
2260
2261 /* SFP */
2262 if (hw->phy.media_type == ixgbe_media_type_fiber) {
2263 /* CS4227 SFP must not enable auto-negotiation */
2264 *autoneg = false;
2265
2266 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
2267 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 ||
2268 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
2269 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) {
2270 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2271 return 0;
2272 }
2273
2274 /* Link capabilities are based on SFP */
2275 if (hw->phy.multispeed_fiber)
2276 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2277 IXGBE_LINK_SPEED_1GB_FULL;
2278 else
2279 *speed = IXGBE_LINK_SPEED_10GB_FULL;
2280 } else {
2281 switch (hw->phy.type) {
2282 case ixgbe_phy_x550em_kx4:
2283 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2284 IXGBE_LINK_SPEED_2_5GB_FULL |
2285 IXGBE_LINK_SPEED_10GB_FULL;
2286 break;
2287 case ixgbe_phy_x550em_xfi:
2288 *speed = IXGBE_LINK_SPEED_1GB_FULL |
2289 IXGBE_LINK_SPEED_10GB_FULL;
2290 break;
2291 case ixgbe_phy_ext_1g_t:
2292 case ixgbe_phy_sgmii:
2293 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2294 break;
2295 case ixgbe_phy_x550em_kr:
2296 if (hw->mac.type == ixgbe_mac_x550em_a) {
2297 /* check different backplane modes */
2298 if (hw->phy.nw_mng_if_sel &
2299 IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G) {
2300 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
2301 break;
2302 } else if (hw->device_id ==
2303 IXGBE_DEV_ID_X550EM_A_KR_L) {
2304 *speed = IXGBE_LINK_SPEED_1GB_FULL;
2305 break;
2306 }
2307 }
2308 fallthrough;
2309 default:
2310 *speed = IXGBE_LINK_SPEED_10GB_FULL |
2311 IXGBE_LINK_SPEED_1GB_FULL;
2312 break;
2313 }
2314 *autoneg = true;
2315 }
2316 return 0;
2317}
2318
2319/**
2320 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
2321 * @hw: pointer to hardware structure
2322 * @lsc: pointer to boolean flag which indicates whether external Base T
2323 * PHY interrupt is lsc
2324 * @is_overtemp: indicate whether an overtemp event encountered
2325 *
2326 * Determime if external Base T PHY interrupt cause is high temperature
2327 * failure alarm or link status change.
2328 **/
2329static int ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc,
2330 bool *is_overtemp)
2331{
2332 u32 status;
2333 u16 reg;
2334
2335 *is_overtemp = false;
2336 *lsc = false;
2337
2338 /* Vendor alarm triggered */
2339 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2340 MDIO_MMD_VEND1,
2341 ®);
2342
2343 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
2344 return status;
2345
2346 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
2347 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
2348 MDIO_MMD_VEND1,
2349 ®);
2350
2351 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2352 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
2353 return status;
2354
2355 /* Global alarm triggered */
2356 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
2357 MDIO_MMD_VEND1,
2358 ®);
2359
2360 if (status)
2361 return status;
2362
2363 /* If high temperature failure, then return over temp error and exit */
2364 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
2365 /* power down the PHY in case the PHY FW didn't already */
2366 ixgbe_set_copper_phy_power(hw, false);
2367 *is_overtemp = true;
2368 return -EIO;
2369 }
2370 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
2371 /* device fault alarm triggered */
2372 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
2373 MDIO_MMD_VEND1,
2374 ®);
2375 if (status)
2376 return status;
2377
2378 /* if device fault was due to high temp alarm handle and exit */
2379 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
2380 /* power down the PHY in case the PHY FW didn't */
2381 ixgbe_set_copper_phy_power(hw, false);
2382 *is_overtemp = true;
2383 return -EIO;
2384 }
2385 }
2386
2387 /* Vendor alarm 2 triggered */
2388 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
2389 MDIO_MMD_AN, ®);
2390
2391 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
2392 return status;
2393
2394 /* link connect/disconnect event occurred */
2395 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
2396 MDIO_MMD_AN, ®);
2397
2398 if (status)
2399 return status;
2400
2401 /* Indicate LSC */
2402 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
2403 *lsc = true;
2404
2405 return 0;
2406}
2407
2408/**
2409 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
2410 * @hw: pointer to hardware structure
2411 *
2412 * Enable link status change and temperature failure alarm for the external
2413 * Base T PHY
2414 *
2415 * Returns PHY access status
2416 **/
2417static int ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2418{
2419 bool lsc, overtemp;
2420 u32 status;
2421 u16 reg;
2422
2423 /* Clear interrupt flags */
2424 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, &overtemp);
2425
2426 /* Enable link status change alarm */
2427
2428 /* Enable the LASI interrupts on X552 devices to receive notifications
2429 * of the link configurations of the external PHY and correspondingly
2430 * support the configuration of the internal iXFI link, since iXFI does
2431 * not support auto-negotiation. This is not required for X553 devices
2432 * having KR support, which performs auto-negotiations and which is used
2433 * as the internal link to the external PHY. Hence adding a check here
2434 * to avoid enabling LASI interrupts for X553 devices.
2435 */
2436 if (hw->mac.type != ixgbe_mac_x550em_a) {
2437 status = hw->phy.ops.read_reg(hw,
2438 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2439 MDIO_MMD_AN, ®);
2440 if (status)
2441 return status;
2442
2443 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2444
2445 status = hw->phy.ops.write_reg(hw,
2446 IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2447 MDIO_MMD_AN, reg);
2448 if (status)
2449 return status;
2450 }
2451
2452 /* Enable high temperature failure and global fault alarms */
2453 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2454 MDIO_MMD_VEND1,
2455 ®);
2456 if (status)
2457 return status;
2458
2459 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2460 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2461
2462 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2463 MDIO_MMD_VEND1,
2464 reg);
2465 if (status)
2466 return status;
2467
2468 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2469 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2470 MDIO_MMD_VEND1,
2471 ®);
2472 if (status)
2473 return status;
2474
2475 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2476 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2477
2478 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2479 MDIO_MMD_VEND1,
2480 reg);
2481 if (status)
2482 return status;
2483
2484 /* Enable chip-wide vendor alarm */
2485 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2486 MDIO_MMD_VEND1,
2487 ®);
2488 if (status)
2489 return status;
2490
2491 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2492
2493 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2494 MDIO_MMD_VEND1,
2495 reg);
2496
2497 return status;
2498}
2499
2500/**
2501 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2502 * @hw: pointer to hardware structure
2503 * @is_overtemp: indicate whether an overtemp event encountered
2504 *
2505 * Handle external Base T PHY interrupt. If high temperature
2506 * failure alarm then return error, else if link status change
2507 * then setup internal/external PHY link
2508 **/
2509static int ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw,
2510 bool *is_overtemp)
2511{
2512 struct ixgbe_phy_info *phy = &hw->phy;
2513 bool lsc;
2514 u32 status;
2515
2516 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc, is_overtemp);
2517 if (status)
2518 return status;
2519
2520 if (lsc && phy->ops.setup_internal_link)
2521 return phy->ops.setup_internal_link(hw);
2522
2523 return 0;
2524}
2525
2526/**
2527 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2528 * @hw: pointer to hardware structure
2529 * @speed: link speed
2530 *
2531 * Configures the integrated KR PHY.
2532 **/
2533static int ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2534 ixgbe_link_speed speed)
2535{
2536 u32 reg_val;
2537 int status;
2538
2539 status = hw->mac.ops.read_iosf_sb_reg(hw,
2540 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2541 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2542 if (status)
2543 return status;
2544
2545 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2546 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2547 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2548
2549 /* Advertise 10G support. */
2550 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2551 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2552
2553 /* Advertise 1G support. */
2554 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2555 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2556
2557 status = hw->mac.ops.write_iosf_sb_reg(hw,
2558 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2559 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2560
2561 if (hw->mac.type == ixgbe_mac_x550em_a) {
2562 /* Set lane mode to KR auto negotiation */
2563 status = hw->mac.ops.read_iosf_sb_reg(hw,
2564 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2565 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2566
2567 if (status)
2568 return status;
2569
2570 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2571 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2572 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2573 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2574 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2575
2576 status = hw->mac.ops.write_iosf_sb_reg(hw,
2577 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2578 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2579 }
2580
2581 return ixgbe_restart_an_internal_phy_x550em(hw);
2582}
2583
2584/**
2585 * ixgbe_setup_kr_x550em - Configure the KR PHY
2586 * @hw: pointer to hardware structure
2587 **/
2588static int ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2589{
2590 /* leave link alone for 2.5G */
2591 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL)
2592 return 0;
2593
2594 if (ixgbe_check_reset_blocked(hw))
2595 return 0;
2596
2597 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2598}
2599
2600/** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2601 * @hw: address of hardware structure
2602 * @link_up: address of boolean to indicate link status
2603 *
2604 * Returns error code if unable to get link status.
2605 **/
2606static int ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2607{
2608 u32 ret;
2609 u16 autoneg_status;
2610
2611 *link_up = false;
2612
2613 /* read this twice back to back to indicate current status */
2614 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2615 &autoneg_status);
2616 if (ret)
2617 return ret;
2618
2619 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2620 &autoneg_status);
2621 if (ret)
2622 return ret;
2623
2624 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2625
2626 return 0;
2627}
2628
2629/** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2630 * @hw: point to hardware structure
2631 *
2632 * Configures the link between the integrated KR PHY and the external X557 PHY
2633 * The driver will call this function when it gets a link status change
2634 * interrupt from the X557 PHY. This function configures the link speed
2635 * between the PHYs to match the link speed of the BASE-T link.
2636 *
2637 * A return of a non-zero value indicates an error, and the base driver should
2638 * not report link up.
2639 **/
2640static int ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2641{
2642 ixgbe_link_speed force_speed;
2643 bool link_up;
2644 u32 status;
2645 u16 speed;
2646
2647 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2648 return -EIO;
2649
2650 if (!(hw->mac.type == ixgbe_mac_X550EM_x &&
2651 !(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE))) {
2652 speed = IXGBE_LINK_SPEED_10GB_FULL |
2653 IXGBE_LINK_SPEED_1GB_FULL;
2654 return ixgbe_setup_kr_speed_x550em(hw, speed);
2655 }
2656
2657 /* If link is not up, then there is no setup necessary so return */
2658 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2659 if (status)
2660 return status;
2661
2662 if (!link_up)
2663 return 0;
2664
2665 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2666 MDIO_MMD_AN,
2667 &speed);
2668 if (status)
2669 return status;
2670
2671 /* If link is not still up, then no setup is necessary so return */
2672 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2673 if (status)
2674 return status;
2675
2676 if (!link_up)
2677 return 0;
2678
2679 /* clear everything but the speed and duplex bits */
2680 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2681
2682 switch (speed) {
2683 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2684 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2685 break;
2686 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2687 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2688 break;
2689 default:
2690 /* Internal PHY does not support anything else */
2691 return -EINVAL;
2692 }
2693
2694 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2695}
2696
2697/** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2698 * @hw: pointer to hardware structure
2699 **/
2700static int ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2701{
2702 int status;
2703
2704 status = ixgbe_reset_phy_generic(hw);
2705
2706 if (status)
2707 return status;
2708
2709 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2710 return ixgbe_enable_lasi_ext_t_x550em(hw);
2711}
2712
2713/**
2714 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2715 * @hw: pointer to hardware structure
2716 * @led_idx: led number to turn on
2717 **/
2718static int ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2719{
2720 u16 phy_data;
2721
2722 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2723 return -EINVAL;
2724
2725 /* To turn on the LED, set mode to ON. */
2726 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2727 MDIO_MMD_VEND1, &phy_data);
2728 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2729 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2730 MDIO_MMD_VEND1, phy_data);
2731
2732 return 0;
2733}
2734
2735/**
2736 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2737 * @hw: pointer to hardware structure
2738 * @led_idx: led number to turn off
2739 **/
2740static int ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2741{
2742 u16 phy_data;
2743
2744 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2745 return -EINVAL;
2746
2747 /* To turn on the LED, set mode to ON. */
2748 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2749 MDIO_MMD_VEND1, &phy_data);
2750 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2751 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2752 MDIO_MMD_VEND1, phy_data);
2753
2754 return 0;
2755}
2756
2757/**
2758 * ixgbe_set_fw_drv_ver_x550 - Sends driver version to firmware
2759 * @hw: pointer to the HW structure
2760 * @maj: driver version major number
2761 * @min: driver version minor number
2762 * @build: driver version build number
2763 * @sub: driver version sub build number
2764 * @len: length of driver_ver string
2765 * @driver_ver: driver string
2766 *
2767 * Sends driver version number to firmware through the manageability
2768 * block. On success return 0
2769 * else returns -EBUSY when encountering an error acquiring
2770 * semaphore, -EIO when command fails or -ENIVAL when incorrect
2771 * params passed.
2772 **/
2773static int ixgbe_set_fw_drv_ver_x550(struct ixgbe_hw *hw, u8 maj, u8 min,
2774 u8 build, u8 sub, u16 len,
2775 const char *driver_ver)
2776{
2777 struct ixgbe_hic_drv_info2 fw_cmd;
2778 int ret_val;
2779 int i;
2780
2781 if (!len || !driver_ver || (len > sizeof(fw_cmd.driver_string)))
2782 return -EINVAL;
2783
2784 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
2785 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN + len;
2786 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
2787 fw_cmd.port_num = (u8)hw->bus.func;
2788 fw_cmd.ver_maj = maj;
2789 fw_cmd.ver_min = min;
2790 fw_cmd.ver_build = build;
2791 fw_cmd.ver_sub = sub;
2792 fw_cmd.hdr.checksum = 0;
2793 memcpy(fw_cmd.driver_string, driver_ver, len);
2794 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
2795 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
2796
2797 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
2798 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
2799 sizeof(fw_cmd),
2800 IXGBE_HI_COMMAND_TIMEOUT,
2801 true);
2802 if (ret_val)
2803 continue;
2804
2805 if (fw_cmd.hdr.cmd_or_resp.ret_status !=
2806 FW_CEM_RESP_STATUS_SUCCESS)
2807 return -EIO;
2808 return 0;
2809 }
2810
2811 return ret_val;
2812}
2813
2814/** ixgbe_get_lcd_x550em - Determine lowest common denominator
2815 * @hw: pointer to hardware structure
2816 * @lcd_speed: pointer to lowest common link speed
2817 *
2818 * Determine lowest common link speed with link partner.
2819 **/
2820static int ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2821 ixgbe_link_speed *lcd_speed)
2822{
2823 u16 word = hw->eeprom.ctrl_word_3;
2824 u16 an_lp_status;
2825 int status;
2826
2827 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2828
2829 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2830 MDIO_MMD_AN,
2831 &an_lp_status);
2832 if (status)
2833 return status;
2834
2835 /* If link partner advertised 1G, return 1G */
2836 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2837 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2838 return 0;
2839 }
2840
2841 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2842 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2843 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2844 return 0;
2845
2846 /* Link partner not capable of lower speeds, return 10G */
2847 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2848 return 0;
2849}
2850
2851/**
2852 * ixgbe_setup_fc_x550em - Set up flow control
2853 * @hw: pointer to hardware structure
2854 */
2855static int ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2856{
2857 bool pause, asm_dir;
2858 u32 reg_val;
2859 int rc = 0;
2860
2861 /* Validate the requested mode */
2862 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2863 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2864 return -EINVAL;
2865 }
2866
2867 /* 10gig parts do not have a word in the EEPROM to determine the
2868 * default flow control setting, so we explicitly set it to full.
2869 */
2870 if (hw->fc.requested_mode == ixgbe_fc_default)
2871 hw->fc.requested_mode = ixgbe_fc_full;
2872
2873 /* Determine PAUSE and ASM_DIR bits. */
2874 switch (hw->fc.requested_mode) {
2875 case ixgbe_fc_none:
2876 pause = false;
2877 asm_dir = false;
2878 break;
2879 case ixgbe_fc_tx_pause:
2880 pause = false;
2881 asm_dir = true;
2882 break;
2883 case ixgbe_fc_rx_pause:
2884 /* Rx Flow control is enabled and Tx Flow control is
2885 * disabled by software override. Since there really
2886 * isn't a way to advertise that we are capable of RX
2887 * Pause ONLY, we will advertise that we support both
2888 * symmetric and asymmetric Rx PAUSE, as such we fall
2889 * through to the fc_full statement. Later, we will
2890 * disable the adapter's ability to send PAUSE frames.
2891 */
2892 fallthrough;
2893 case ixgbe_fc_full:
2894 pause = true;
2895 asm_dir = true;
2896 break;
2897 default:
2898 hw_err(hw, "Flow control param set incorrectly\n");
2899 return -EIO;
2900 }
2901
2902 switch (hw->device_id) {
2903 case IXGBE_DEV_ID_X550EM_X_KR:
2904 case IXGBE_DEV_ID_X550EM_A_KR:
2905 case IXGBE_DEV_ID_X550EM_A_KR_L:
2906 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2907 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2908 IXGBE_SB_IOSF_TARGET_KR_PHY,
2909 ®_val);
2910 if (rc)
2911 return rc;
2912
2913 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2914 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2915 if (pause)
2916 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2917 if (asm_dir)
2918 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2919 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2920 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2921 IXGBE_SB_IOSF_TARGET_KR_PHY,
2922 reg_val);
2923
2924 /* This device does not fully support AN. */
2925 hw->fc.disable_fc_autoneg = true;
2926 break;
2927 case IXGBE_DEV_ID_X550EM_X_XFI:
2928 hw->fc.disable_fc_autoneg = true;
2929 break;
2930 default:
2931 break;
2932 }
2933 return rc;
2934}
2935
2936/**
2937 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2938 * @hw: pointer to hardware structure
2939 **/
2940static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2941{
2942 u32 link_s1, lp_an_page_low, an_cntl_1;
2943 ixgbe_link_speed speed;
2944 int status = -EIO;
2945 bool link_up;
2946
2947 /* AN should have completed when the cable was plugged in.
2948 * Look for reasons to bail out. Bail out if:
2949 * - FC autoneg is disabled, or if
2950 * - link is not up.
2951 */
2952 if (hw->fc.disable_fc_autoneg) {
2953 hw_err(hw, "Flow control autoneg is disabled");
2954 goto out;
2955 }
2956
2957 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2958 if (!link_up) {
2959 hw_err(hw, "The link is down");
2960 goto out;
2961 }
2962
2963 /* Check at auto-negotiation has completed */
2964 status = hw->mac.ops.read_iosf_sb_reg(hw,
2965 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2966 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2967
2968 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2969 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2970 status = -EIO;
2971 goto out;
2972 }
2973
2974 /* Read the 10g AN autoc and LP ability registers and resolve
2975 * local flow control settings accordingly
2976 */
2977 status = hw->mac.ops.read_iosf_sb_reg(hw,
2978 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2979 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2980
2981 if (status) {
2982 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2983 goto out;
2984 }
2985
2986 status = hw->mac.ops.read_iosf_sb_reg(hw,
2987 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2988 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2989
2990 if (status) {
2991 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2992 goto out;
2993 }
2994
2995 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2996 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2997 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2998 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2999 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
3000
3001out:
3002 if (!status) {
3003 hw->fc.fc_was_autonegged = true;
3004 } else {
3005 hw->fc.fc_was_autonegged = false;
3006 hw->fc.current_mode = hw->fc.requested_mode;
3007 }
3008}
3009
3010/**
3011 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
3012 * @hw: pointer to hardware structure
3013 **/
3014static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
3015{
3016 hw->fc.fc_was_autonegged = false;
3017 hw->fc.current_mode = hw->fc.requested_mode;
3018}
3019
3020/** ixgbe_enter_lplu_x550em - Transition to low power states
3021 * @hw: pointer to hardware structure
3022 *
3023 * Configures Low Power Link Up on transition to low power states
3024 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
3025 * the X557 PHY immediately prior to entering LPLU.
3026 **/
3027static int ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
3028{
3029 u16 an_10g_cntl_reg, autoneg_reg, speed;
3030 ixgbe_link_speed lcd_speed;
3031 u32 save_autoneg;
3032 bool link_up;
3033 int status;
3034
3035 /* If blocked by MNG FW, then don't restart AN */
3036 if (ixgbe_check_reset_blocked(hw))
3037 return 0;
3038
3039 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3040 if (status)
3041 return status;
3042
3043 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
3044 &hw->eeprom.ctrl_word_3);
3045 if (status)
3046 return status;
3047
3048 /* If link is down, LPLU disabled in NVM, WoL disabled, or
3049 * manageability disabled, then force link down by entering
3050 * low power mode.
3051 */
3052 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
3053 !(hw->wol_enabled || ixgbe_mng_present(hw)))
3054 return ixgbe_set_copper_phy_power(hw, false);
3055
3056 /* Determine LCD */
3057 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
3058 if (status)
3059 return status;
3060
3061 /* If no valid LCD link speed, then force link down and exit. */
3062 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
3063 return ixgbe_set_copper_phy_power(hw, false);
3064
3065 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
3066 MDIO_MMD_AN,
3067 &speed);
3068 if (status)
3069 return status;
3070
3071 /* If no link now, speed is invalid so take link down */
3072 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
3073 if (status)
3074 return ixgbe_set_copper_phy_power(hw, false);
3075
3076 /* clear everything but the speed bits */
3077 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
3078
3079 /* If current speed is already LCD, then exit. */
3080 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
3081 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
3082 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
3083 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
3084 return 0;
3085
3086 /* Clear AN completed indication */
3087 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
3088 MDIO_MMD_AN,
3089 &autoneg_reg);
3090 if (status)
3091 return status;
3092
3093 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
3094 MDIO_MMD_AN,
3095 &an_10g_cntl_reg);
3096 if (status)
3097 return status;
3098
3099 status = hw->phy.ops.read_reg(hw,
3100 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
3101 MDIO_MMD_AN,
3102 &autoneg_reg);
3103 if (status)
3104 return status;
3105
3106 save_autoneg = hw->phy.autoneg_advertised;
3107
3108 /* Setup link at least common link speed */
3109 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
3110
3111 /* restore autoneg from before setting lplu speed */
3112 hw->phy.autoneg_advertised = save_autoneg;
3113
3114 return status;
3115}
3116
3117/**
3118 * ixgbe_reset_phy_fw - Reset firmware-controlled PHYs
3119 * @hw: pointer to hardware structure
3120 */
3121static int ixgbe_reset_phy_fw(struct ixgbe_hw *hw)
3122{
3123 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3124 int rc;
3125
3126 if (hw->phy.reset_disable || ixgbe_check_reset_blocked(hw))
3127 return 0;
3128
3129 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_PHY_SW_RESET, &store);
3130 if (rc)
3131 return rc;
3132 memset(store, 0, sizeof(store));
3133
3134 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_INIT_PHY, &store);
3135 if (rc)
3136 return rc;
3137
3138 return ixgbe_setup_fw_link(hw);
3139}
3140
3141/**
3142 * ixgbe_check_overtemp_fw - Check firmware-controlled PHYs for overtemp
3143 * @hw: pointer to hardware structure
3144 *
3145 * Return true when an overtemp event detected, otherwise false.
3146 */
3147static bool ixgbe_check_overtemp_fw(struct ixgbe_hw *hw)
3148{
3149 u32 store[FW_PHY_ACT_DATA_COUNT] = { 0 };
3150 int rc;
3151
3152 rc = ixgbe_fw_phy_activity(hw, FW_PHY_ACT_GET_LINK_INFO, &store);
3153 if (rc)
3154 return false;
3155
3156 if (store[0] & FW_PHY_ACT_GET_LINK_INFO_TEMP) {
3157 ixgbe_shutdown_fw_phy(hw);
3158 return true;
3159 }
3160 return false;
3161}
3162
3163/**
3164 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
3165 * @hw: pointer to hardware structure
3166 *
3167 * Read NW_MNG_IF_SEL register and save field values.
3168 */
3169static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
3170{
3171 /* Save NW management interface connected on board. This is used
3172 * to determine internal PHY mode.
3173 */
3174 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3175
3176 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
3177 * PHY address. This register field was has only been used for X552.
3178 */
3179 if (hw->mac.type == ixgbe_mac_x550em_a &&
3180 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
3181 hw->phy.mdio.prtad = FIELD_GET(IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD,
3182 hw->phy.nw_mng_if_sel);
3183 }
3184}
3185
3186/** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
3187 * @hw: pointer to hardware structure
3188 *
3189 * Initialize any function pointers that were not able to be
3190 * set during init_shared_code because the PHY/SFP type was
3191 * not known. Perform the SFP init if necessary.
3192 **/
3193static int ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
3194{
3195 struct ixgbe_phy_info *phy = &hw->phy;
3196 int ret_val;
3197
3198 hw->mac.ops.set_lan_id(hw);
3199
3200 ixgbe_read_mng_if_sel_x550em(hw);
3201
3202 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
3203 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
3204 ixgbe_setup_mux_ctl(hw);
3205 }
3206
3207 /* Identify the PHY or SFP module */
3208 ret_val = phy->ops.identify(hw);
3209 if (ret_val == -EOPNOTSUPP || ret_val == -EFAULT)
3210 return ret_val;
3211
3212 /* Setup function pointers based on detected hardware */
3213 ixgbe_init_mac_link_ops_X550em(hw);
3214 if (phy->sfp_type != ixgbe_sfp_type_unknown)
3215 phy->ops.reset = NULL;
3216
3217 /* Set functions pointers based on phy type */
3218 switch (hw->phy.type) {
3219 case ixgbe_phy_x550em_kx4:
3220 phy->ops.setup_link = NULL;
3221 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3222 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3223 break;
3224 case ixgbe_phy_x550em_kr:
3225 phy->ops.setup_link = ixgbe_setup_kr_x550em;
3226 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3227 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3228 break;
3229 case ixgbe_phy_x550em_xfi:
3230 /* link is managed by HW */
3231 phy->ops.setup_link = NULL;
3232 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
3233 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
3234 break;
3235 case ixgbe_phy_x550em_ext_t:
3236 /* Save NW management interface connected on board. This is used
3237 * to determine internal PHY mode
3238 */
3239 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
3240
3241 /* If internal link mode is XFI, then setup iXFI internal link,
3242 * else setup KR now.
3243 */
3244 phy->ops.setup_internal_link =
3245 ixgbe_setup_internal_phy_t_x550em;
3246
3247 /* setup SW LPLU only for first revision */
3248 if (hw->mac.type == ixgbe_mac_X550EM_x &&
3249 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
3250 IXGBE_FUSES0_REV_MASK))
3251 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
3252
3253 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
3254 phy->ops.reset = ixgbe_reset_phy_t_X550em;
3255 break;
3256 case ixgbe_phy_sgmii:
3257 phy->ops.setup_link = NULL;
3258 break;
3259 case ixgbe_phy_fw:
3260 phy->ops.setup_link = ixgbe_setup_fw_link;
3261 phy->ops.reset = ixgbe_reset_phy_fw;
3262 break;
3263 case ixgbe_phy_ext_1g_t:
3264 phy->ops.setup_link = NULL;
3265 phy->ops.read_reg = NULL;
3266 phy->ops.write_reg = NULL;
3267 phy->ops.reset = NULL;
3268 break;
3269 default:
3270 break;
3271 }
3272
3273 return ret_val;
3274}
3275
3276/** ixgbe_get_media_type_X550em - Get media type
3277 * @hw: pointer to hardware structure
3278 *
3279 * Returns the media type (fiber, copper, backplane)
3280 *
3281 */
3282static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
3283{
3284 enum ixgbe_media_type media_type;
3285
3286 /* Detect if there is a copper PHY attached. */
3287 switch (hw->device_id) {
3288 case IXGBE_DEV_ID_X550EM_A_SGMII:
3289 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3290 hw->phy.type = ixgbe_phy_sgmii;
3291 fallthrough;
3292 case IXGBE_DEV_ID_X550EM_X_KR:
3293 case IXGBE_DEV_ID_X550EM_X_KX4:
3294 case IXGBE_DEV_ID_X550EM_X_XFI:
3295 case IXGBE_DEV_ID_X550EM_A_KR:
3296 case IXGBE_DEV_ID_X550EM_A_KR_L:
3297 media_type = ixgbe_media_type_backplane;
3298 break;
3299 case IXGBE_DEV_ID_X550EM_X_SFP:
3300 case IXGBE_DEV_ID_X550EM_A_SFP:
3301 case IXGBE_DEV_ID_X550EM_A_SFP_N:
3302 media_type = ixgbe_media_type_fiber;
3303 break;
3304 case IXGBE_DEV_ID_X550EM_X_1G_T:
3305 case IXGBE_DEV_ID_X550EM_X_10G_T:
3306 case IXGBE_DEV_ID_X550EM_A_10G_T:
3307 case IXGBE_DEV_ID_X550EM_A_1G_T:
3308 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3309 media_type = ixgbe_media_type_copper;
3310 break;
3311 default:
3312 media_type = ixgbe_media_type_unknown;
3313 break;
3314 }
3315 return media_type;
3316}
3317
3318/** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
3319 ** @hw: pointer to hardware structure
3320 **/
3321static int ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
3322{
3323 int status;
3324 u16 reg;
3325
3326 status = hw->phy.ops.read_reg(hw,
3327 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
3328 MDIO_MMD_PMAPMD,
3329 ®);
3330 if (status)
3331 return status;
3332
3333 /* If PHY FW reset completed bit is set then this is the first
3334 * SW instance after a power on so the PHY FW must be un-stalled.
3335 */
3336 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
3337 status = hw->phy.ops.read_reg(hw,
3338 IXGBE_MDIO_GLOBAL_RES_PR_10,
3339 MDIO_MMD_VEND1,
3340 ®);
3341 if (status)
3342 return status;
3343
3344 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
3345
3346 status = hw->phy.ops.write_reg(hw,
3347 IXGBE_MDIO_GLOBAL_RES_PR_10,
3348 MDIO_MMD_VEND1,
3349 reg);
3350 if (status)
3351 return status;
3352 }
3353
3354 return status;
3355}
3356
3357/**
3358 * ixgbe_set_mdio_speed - Set MDIO clock speed
3359 * @hw: pointer to hardware structure
3360 */
3361static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
3362{
3363 u32 hlreg0;
3364
3365 switch (hw->device_id) {
3366 case IXGBE_DEV_ID_X550EM_X_10G_T:
3367 case IXGBE_DEV_ID_X550EM_A_SGMII:
3368 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
3369 case IXGBE_DEV_ID_X550EM_A_10G_T:
3370 case IXGBE_DEV_ID_X550EM_A_SFP:
3371 /* Config MDIO clock speed before the first MDIO PHY access */
3372 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3373 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
3374 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3375 break;
3376 case IXGBE_DEV_ID_X550EM_A_1G_T:
3377 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
3378 /* Select fast MDIO clock speed for these devices */
3379 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3380 hlreg0 |= IXGBE_HLREG0_MDCSPD;
3381 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3382 break;
3383 default:
3384 break;
3385 }
3386}
3387
3388/** ixgbe_reset_hw_X550em - Perform hardware reset
3389 ** @hw: pointer to hardware structure
3390 **
3391 ** Resets the hardware by resetting the transmit and receive units, masks
3392 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
3393 ** reset.
3394 **/
3395static int ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
3396{
3397 u32 swfw_mask = hw->phy.phy_semaphore_mask;
3398 ixgbe_link_speed link_speed;
3399 bool link_up = false;
3400 u32 ctrl = 0;
3401 int status;
3402 u32 i;
3403
3404 /* Call adapter stop to disable Tx/Rx and clear interrupts */
3405 status = hw->mac.ops.stop_adapter(hw);
3406 if (status)
3407 return status;
3408
3409 /* flush pending Tx transactions */
3410 ixgbe_clear_tx_pending(hw);
3411
3412 /* set MDIO speed before talking to the PHY in case it's the 1st time */
3413 ixgbe_set_mdio_speed(hw);
3414
3415 /* PHY ops must be identified and initialized prior to reset */
3416 status = hw->phy.ops.init(hw);
3417 if (status == -EOPNOTSUPP || status == -EFAULT)
3418 return status;
3419
3420 /* start the external PHY */
3421 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
3422 status = ixgbe_init_ext_t_x550em(hw);
3423 if (status)
3424 return status;
3425 }
3426
3427 /* Setup SFP module if there is one present. */
3428 if (hw->phy.sfp_setup_needed) {
3429 status = hw->mac.ops.setup_sfp(hw);
3430 hw->phy.sfp_setup_needed = false;
3431 }
3432
3433 if (status == -EOPNOTSUPP)
3434 return status;
3435
3436 /* Reset PHY */
3437 if (!hw->phy.reset_disable && hw->phy.ops.reset)
3438 hw->phy.ops.reset(hw);
3439
3440mac_reset_top:
3441 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
3442 * If link reset is used when link is up, it might reset the PHY when
3443 * mng is using it. If link is down or the flag to force full link
3444 * reset is set, then perform link reset.
3445 */
3446 ctrl = IXGBE_CTRL_LNK_RST;
3447
3448 if (!hw->force_full_reset) {
3449 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
3450 if (link_up)
3451 ctrl = IXGBE_CTRL_RST;
3452 }
3453
3454 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
3455 if (status) {
3456 hw_dbg(hw, "semaphore failed with %d", status);
3457 return -EBUSY;
3458 }
3459
3460 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
3461 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
3462 IXGBE_WRITE_FLUSH(hw);
3463 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3464 usleep_range(1000, 1200);
3465
3466 /* Poll for reset bit to self-clear meaning reset is complete */
3467 for (i = 0; i < 10; i++) {
3468 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
3469 if (!(ctrl & IXGBE_CTRL_RST_MASK))
3470 break;
3471 udelay(1);
3472 }
3473
3474 if (ctrl & IXGBE_CTRL_RST_MASK) {
3475 status = -EIO;
3476 hw_dbg(hw, "Reset polling failed to complete.\n");
3477 }
3478
3479 msleep(50);
3480
3481 /* Double resets are required for recovery from certain error
3482 * clear the multicast table. Also reset num_rar_entries to 128,
3483 * since we modify this value when programming the SAN MAC address.
3484 */
3485 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
3486 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3487 goto mac_reset_top;
3488 }
3489
3490 /* Store the permanent mac address */
3491 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
3492
3493 /* Store MAC address from RAR0, clear receive address registers, and
3494 * clear the multicast table. Also reset num_rar_entries to 128,
3495 * since we modify this value when programming the SAN MAC address.
3496 */
3497 hw->mac.num_rar_entries = 128;
3498 hw->mac.ops.init_rx_addrs(hw);
3499
3500 ixgbe_set_mdio_speed(hw);
3501
3502 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
3503 ixgbe_setup_mux_ctl(hw);
3504
3505 return status;
3506}
3507
3508/** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
3509 * anti-spoofing
3510 * @hw: pointer to hardware structure
3511 * @enable: enable or disable switch for Ethertype anti-spoofing
3512 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
3513 **/
3514static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
3515 bool enable, int vf)
3516{
3517 int vf_target_reg = vf >> 3;
3518 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
3519 u32 pfvfspoof;
3520
3521 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
3522 if (enable)
3523 pfvfspoof |= BIT(vf_target_shift);
3524 else
3525 pfvfspoof &= ~BIT(vf_target_shift);
3526
3527 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
3528}
3529
3530/** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
3531 * @hw: pointer to hardware structure
3532 * @enable: enable or disable source address pruning
3533 * @pool: Rx pool to set source address pruning for
3534 **/
3535static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
3536 bool enable,
3537 unsigned int pool)
3538{
3539 u64 pfflp;
3540
3541 /* max rx pool is 63 */
3542 if (pool > 63)
3543 return;
3544
3545 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
3546 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
3547
3548 if (enable)
3549 pfflp |= (1ULL << pool);
3550 else
3551 pfflp &= ~(1ULL << pool);
3552
3553 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3554 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3555}
3556
3557/**
3558 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3559 * @hw: pointer to hardware structure
3560 *
3561 * Called at init time to set up flow control.
3562 **/
3563static int ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3564{
3565 u32 an_cntl = 0;
3566 int status = 0;
3567
3568 /* Validate the requested mode */
3569 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3570 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3571 return -EINVAL;
3572 }
3573
3574 if (hw->fc.requested_mode == ixgbe_fc_default)
3575 hw->fc.requested_mode = ixgbe_fc_full;
3576
3577 /* Set up the 1G and 10G flow control advertisement registers so the
3578 * HW will be able to do FC autoneg once the cable is plugged in. If
3579 * we link at 10G, the 1G advertisement is harmless and vice versa.
3580 */
3581 status = hw->mac.ops.read_iosf_sb_reg(hw,
3582 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3583 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3584
3585 if (status) {
3586 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3587 return status;
3588 }
3589
3590 /* The possible values of fc.requested_mode are:
3591 * 0: Flow control is completely disabled
3592 * 1: Rx flow control is enabled (we can receive pause frames,
3593 * but not send pause frames).
3594 * 2: Tx flow control is enabled (we can send pause frames but
3595 * we do not support receiving pause frames).
3596 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3597 * other: Invalid.
3598 */
3599 switch (hw->fc.requested_mode) {
3600 case ixgbe_fc_none:
3601 /* Flow control completely disabled by software override. */
3602 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3603 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3604 break;
3605 case ixgbe_fc_tx_pause:
3606 /* Tx Flow control is enabled, and Rx Flow control is
3607 * disabled by software override.
3608 */
3609 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3610 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3611 break;
3612 case ixgbe_fc_rx_pause:
3613 /* Rx Flow control is enabled and Tx Flow control is
3614 * disabled by software override. Since there really
3615 * isn't a way to advertise that we are capable of RX
3616 * Pause ONLY, we will advertise that we support both
3617 * symmetric and asymmetric Rx PAUSE, as such we fall
3618 * through to the fc_full statement. Later, we will
3619 * disable the adapter's ability to send PAUSE frames.
3620 */
3621 case ixgbe_fc_full:
3622 /* Flow control (both Rx and Tx) is enabled by SW override. */
3623 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3624 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3625 break;
3626 default:
3627 hw_err(hw, "Flow control param set incorrectly\n");
3628 return -EIO;
3629 }
3630
3631 status = hw->mac.ops.write_iosf_sb_reg(hw,
3632 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3633 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3634
3635 /* Restart auto-negotiation. */
3636 status = ixgbe_restart_an_internal_phy_x550em(hw);
3637
3638 return status;
3639}
3640
3641/**
3642 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3643 * @hw: pointer to hardware structure
3644 * @state: set mux if 1, clear if 0
3645 */
3646static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3647{
3648 u32 esdp;
3649
3650 if (!hw->bus.lan_id)
3651 return;
3652 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3653 if (state)
3654 esdp |= IXGBE_ESDP_SDP1;
3655 else
3656 esdp &= ~IXGBE_ESDP_SDP1;
3657 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3658 IXGBE_WRITE_FLUSH(hw);
3659}
3660
3661/**
3662 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3663 * @hw: pointer to hardware structure
3664 * @mask: Mask to specify which semaphore to acquire
3665 *
3666 * Acquires the SWFW semaphore and sets the I2C MUX
3667 */
3668static int ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3669{
3670 int status;
3671
3672 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3673 if (status)
3674 return status;
3675
3676 if (mask & IXGBE_GSSR_I2C_MASK)
3677 ixgbe_set_mux(hw, 1);
3678
3679 return 0;
3680}
3681
3682/**
3683 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3684 * @hw: pointer to hardware structure
3685 * @mask: Mask to specify which semaphore to release
3686 *
3687 * Releases the SWFW semaphore and sets the I2C MUX
3688 */
3689static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3690{
3691 if (mask & IXGBE_GSSR_I2C_MASK)
3692 ixgbe_set_mux(hw, 0);
3693
3694 ixgbe_release_swfw_sync_X540(hw, mask);
3695}
3696
3697/**
3698 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3699 * @hw: pointer to hardware structure
3700 * @mask: Mask to specify which semaphore to acquire
3701 *
3702 * Acquires the SWFW semaphore and get the shared PHY token as needed
3703 */
3704static int ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3705{
3706 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3707 int retries = FW_PHY_TOKEN_RETRIES;
3708 int status;
3709
3710 while (--retries) {
3711 status = 0;
3712 if (hmask)
3713 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3714 if (status)
3715 return status;
3716 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3717 return 0;
3718
3719 status = ixgbe_get_phy_token(hw);
3720 if (!status)
3721 return 0;
3722 if (hmask)
3723 ixgbe_release_swfw_sync_X540(hw, hmask);
3724 if (status != -EAGAIN)
3725 return status;
3726 msleep(FW_PHY_TOKEN_DELAY);
3727 }
3728
3729 return status;
3730}
3731
3732/**
3733 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3734 * @hw: pointer to hardware structure
3735 * @mask: Mask to specify which semaphore to release
3736 *
3737 * Release the SWFW semaphore and puts the shared PHY token as needed
3738 */
3739static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3740{
3741 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3742
3743 if (mask & IXGBE_GSSR_TOKEN_SM)
3744 ixgbe_put_phy_token(hw);
3745
3746 if (hmask)
3747 ixgbe_release_swfw_sync_X540(hw, hmask);
3748}
3749
3750/**
3751 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3752 * @hw: pointer to hardware structure
3753 * @reg_addr: 32 bit address of PHY register to read
3754 * @device_type: 5 bit device type
3755 * @phy_data: Pointer to read data from PHY register
3756 *
3757 * Reads a value from a specified PHY register using the SWFW lock and PHY
3758 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3759 * instances.
3760 */
3761static int ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3762 u32 device_type, u16 *phy_data)
3763{
3764 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3765 int status;
3766
3767 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3768 return -EBUSY;
3769
3770 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3771
3772 hw->mac.ops.release_swfw_sync(hw, mask);
3773
3774 return status;
3775}
3776
3777/**
3778 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3779 * @hw: pointer to hardware structure
3780 * @reg_addr: 32 bit PHY register to write
3781 * @device_type: 5 bit device type
3782 * @phy_data: Data to write to the PHY register
3783 *
3784 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3785 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3786 */
3787static int ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3788 u32 device_type, u16 phy_data)
3789{
3790 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3791 int status;
3792
3793 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3794 return -EBUSY;
3795
3796 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3797 hw->mac.ops.release_swfw_sync(hw, mask);
3798
3799 return status;
3800}
3801
3802#define X550_COMMON_MAC \
3803 .init_hw = &ixgbe_init_hw_generic, \
3804 .start_hw = &ixgbe_start_hw_X540, \
3805 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3806 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3807 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3808 .get_device_caps = &ixgbe_get_device_caps_generic, \
3809 .stop_adapter = &ixgbe_stop_adapter_generic, \
3810 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3811 .read_analog_reg8 = NULL, \
3812 .write_analog_reg8 = NULL, \
3813 .set_rxpba = &ixgbe_set_rxpba_generic, \
3814 .check_link = &ixgbe_check_mac_link_generic, \
3815 .blink_led_start = &ixgbe_blink_led_start_X540, \
3816 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3817 .set_rar = &ixgbe_set_rar_generic, \
3818 .clear_rar = &ixgbe_clear_rar_generic, \
3819 .set_vmdq = &ixgbe_set_vmdq_generic, \
3820 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3821 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3822 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3823 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3824 .enable_mc = &ixgbe_enable_mc_generic, \
3825 .disable_mc = &ixgbe_disable_mc_generic, \
3826 .clear_vfta = &ixgbe_clear_vfta_generic, \
3827 .set_vfta = &ixgbe_set_vfta_generic, \
3828 .fc_enable = &ixgbe_fc_enable_generic, \
3829 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_x550, \
3830 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3831 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3832 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3833 .set_source_address_pruning = \
3834 &ixgbe_set_source_address_pruning_X550, \
3835 .set_ethertype_anti_spoofing = \
3836 &ixgbe_set_ethertype_anti_spoofing_X550, \
3837 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3838 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3839 .get_thermal_sensor_data = NULL, \
3840 .init_thermal_sensor_thresh = NULL, \
3841 .fw_recovery_mode = &ixgbe_fw_recovery_mode_X550, \
3842 .enable_rx = &ixgbe_enable_rx_generic, \
3843 .disable_rx = &ixgbe_disable_rx_x550, \
3844
3845static const struct ixgbe_mac_operations mac_ops_X550 = {
3846 X550_COMMON_MAC
3847 .led_on = ixgbe_led_on_generic,
3848 .led_off = ixgbe_led_off_generic,
3849 .init_led_link_act = ixgbe_init_led_link_act_generic,
3850 .reset_hw = &ixgbe_reset_hw_X540,
3851 .get_media_type = &ixgbe_get_media_type_X540,
3852 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3853 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3854 .setup_link = &ixgbe_setup_mac_link_X540,
3855 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3856 .get_bus_info = &ixgbe_get_bus_info_generic,
3857 .setup_sfp = NULL,
3858 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3859 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3860 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3861 .prot_autoc_read = prot_autoc_read_generic,
3862 .prot_autoc_write = prot_autoc_write_generic,
3863 .setup_fc = ixgbe_setup_fc_generic,
3864 .fc_autoneg = ixgbe_fc_autoneg,
3865};
3866
3867static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3868 X550_COMMON_MAC
3869 .led_on = ixgbe_led_on_t_x550em,
3870 .led_off = ixgbe_led_off_t_x550em,
3871 .init_led_link_act = ixgbe_init_led_link_act_generic,
3872 .reset_hw = &ixgbe_reset_hw_X550em,
3873 .get_media_type = &ixgbe_get_media_type_X550em,
3874 .get_san_mac_addr = NULL,
3875 .get_wwn_prefix = NULL,
3876 .setup_link = &ixgbe_setup_mac_link_X540,
3877 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3878 .get_bus_info = &ixgbe_get_bus_info_X550em,
3879 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3880 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3881 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3882 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3883 .setup_fc = NULL, /* defined later */
3884 .fc_autoneg = ixgbe_fc_autoneg,
3885 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3886 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3887};
3888
3889static const struct ixgbe_mac_operations mac_ops_X550EM_x_fw = {
3890 X550_COMMON_MAC
3891 .led_on = NULL,
3892 .led_off = NULL,
3893 .init_led_link_act = NULL,
3894 .reset_hw = &ixgbe_reset_hw_X550em,
3895 .get_media_type = &ixgbe_get_media_type_X550em,
3896 .get_san_mac_addr = NULL,
3897 .get_wwn_prefix = NULL,
3898 .setup_link = &ixgbe_setup_mac_link_X540,
3899 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3900 .get_bus_info = &ixgbe_get_bus_info_X550em,
3901 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3902 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3903 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3904 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3905 .setup_fc = NULL,
3906 .fc_autoneg = ixgbe_fc_autoneg,
3907 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3908 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3909};
3910
3911static const struct ixgbe_mac_operations mac_ops_x550em_a = {
3912 X550_COMMON_MAC
3913 .led_on = ixgbe_led_on_t_x550em,
3914 .led_off = ixgbe_led_off_t_x550em,
3915 .init_led_link_act = ixgbe_init_led_link_act_generic,
3916 .reset_hw = ixgbe_reset_hw_X550em,
3917 .get_media_type = ixgbe_get_media_type_X550em,
3918 .get_san_mac_addr = NULL,
3919 .get_wwn_prefix = NULL,
3920 .setup_link = &ixgbe_setup_mac_link_X540,
3921 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3922 .get_bus_info = ixgbe_get_bus_info_X550em,
3923 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3924 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3925 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3926 .setup_fc = ixgbe_setup_fc_x550em,
3927 .fc_autoneg = ixgbe_fc_autoneg,
3928 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3929 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3930};
3931
3932static const struct ixgbe_mac_operations mac_ops_x550em_a_fw = {
3933 X550_COMMON_MAC
3934 .led_on = ixgbe_led_on_generic,
3935 .led_off = ixgbe_led_off_generic,
3936 .init_led_link_act = ixgbe_init_led_link_act_generic,
3937 .reset_hw = ixgbe_reset_hw_X550em,
3938 .get_media_type = ixgbe_get_media_type_X550em,
3939 .get_san_mac_addr = NULL,
3940 .get_wwn_prefix = NULL,
3941 .setup_link = NULL, /* defined later */
3942 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3943 .get_bus_info = ixgbe_get_bus_info_X550em,
3944 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3945 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3946 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3947 .setup_fc = ixgbe_setup_fc_x550em,
3948 .fc_autoneg = ixgbe_fc_autoneg,
3949 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3950 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3951};
3952
3953#define X550_COMMON_EEP \
3954 .read = &ixgbe_read_ee_hostif_X550, \
3955 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3956 .write = &ixgbe_write_ee_hostif_X550, \
3957 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3958 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3959 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3960 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3961
3962static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3963 X550_COMMON_EEP
3964 .init_params = &ixgbe_init_eeprom_params_X550,
3965};
3966
3967static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3968 X550_COMMON_EEP
3969 .init_params = &ixgbe_init_eeprom_params_X540,
3970};
3971
3972#define X550_COMMON_PHY \
3973 .identify_sfp = &ixgbe_identify_module_generic, \
3974 .reset = NULL, \
3975 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3976 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3977 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3978 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3979 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3980 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3981 .setup_link = &ixgbe_setup_phy_link_generic, \
3982 .set_phy_power = NULL,
3983
3984static const struct ixgbe_phy_operations phy_ops_X550 = {
3985 X550_COMMON_PHY
3986 .check_overtemp = &ixgbe_tn_check_overtemp,
3987 .init = NULL,
3988 .identify = &ixgbe_identify_phy_generic,
3989 .read_reg = &ixgbe_read_phy_reg_generic,
3990 .write_reg = &ixgbe_write_phy_reg_generic,
3991};
3992
3993static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3994 X550_COMMON_PHY
3995 .check_overtemp = &ixgbe_tn_check_overtemp,
3996 .init = &ixgbe_init_phy_ops_X550em,
3997 .identify = &ixgbe_identify_phy_x550em,
3998 .read_reg = &ixgbe_read_phy_reg_generic,
3999 .write_reg = &ixgbe_write_phy_reg_generic,
4000};
4001
4002static const struct ixgbe_phy_operations phy_ops_x550em_x_fw = {
4003 X550_COMMON_PHY
4004 .check_overtemp = NULL,
4005 .init = ixgbe_init_phy_ops_X550em,
4006 .identify = ixgbe_identify_phy_x550em,
4007 .read_reg = NULL,
4008 .write_reg = NULL,
4009 .read_reg_mdi = NULL,
4010 .write_reg_mdi = NULL,
4011};
4012
4013static const struct ixgbe_phy_operations phy_ops_x550em_a = {
4014 X550_COMMON_PHY
4015 .check_overtemp = &ixgbe_tn_check_overtemp,
4016 .init = &ixgbe_init_phy_ops_X550em,
4017 .identify = &ixgbe_identify_phy_x550em,
4018 .read_reg = &ixgbe_read_phy_reg_x550a,
4019 .write_reg = &ixgbe_write_phy_reg_x550a,
4020 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
4021 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
4022};
4023
4024static const struct ixgbe_phy_operations phy_ops_x550em_a_fw = {
4025 X550_COMMON_PHY
4026 .check_overtemp = ixgbe_check_overtemp_fw,
4027 .init = ixgbe_init_phy_ops_X550em,
4028 .identify = ixgbe_identify_phy_fw,
4029 .read_reg = NULL,
4030 .write_reg = NULL,
4031 .read_reg_mdi = NULL,
4032 .write_reg_mdi = NULL,
4033};
4034
4035static const struct ixgbe_link_operations link_ops_x550em_x = {
4036 .read_link = &ixgbe_read_i2c_combined_generic,
4037 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
4038 .write_link = &ixgbe_write_i2c_combined_generic,
4039 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
4040};
4041
4042static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
4043 IXGBE_MVALS_INIT(X550)
4044};
4045
4046static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
4047 IXGBE_MVALS_INIT(X550EM_x)
4048};
4049
4050static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
4051 IXGBE_MVALS_INIT(X550EM_a)
4052};
4053
4054const struct ixgbe_info ixgbe_X550_info = {
4055 .mac = ixgbe_mac_X550,
4056 .get_invariants = &ixgbe_get_invariants_X540,
4057 .mac_ops = &mac_ops_X550,
4058 .eeprom_ops = &eeprom_ops_X550,
4059 .phy_ops = &phy_ops_X550,
4060 .mbx_ops = &mbx_ops_generic,
4061 .mvals = ixgbe_mvals_X550,
4062};
4063
4064const struct ixgbe_info ixgbe_X550EM_x_info = {
4065 .mac = ixgbe_mac_X550EM_x,
4066 .get_invariants = &ixgbe_get_invariants_X550_x,
4067 .mac_ops = &mac_ops_X550EM_x,
4068 .eeprom_ops = &eeprom_ops_X550EM_x,
4069 .phy_ops = &phy_ops_X550EM_x,
4070 .mbx_ops = &mbx_ops_generic,
4071 .mvals = ixgbe_mvals_X550EM_x,
4072 .link_ops = &link_ops_x550em_x,
4073};
4074
4075const struct ixgbe_info ixgbe_x550em_x_fw_info = {
4076 .mac = ixgbe_mac_X550EM_x,
4077 .get_invariants = ixgbe_get_invariants_X550_x_fw,
4078 .mac_ops = &mac_ops_X550EM_x_fw,
4079 .eeprom_ops = &eeprom_ops_X550EM_x,
4080 .phy_ops = &phy_ops_x550em_x_fw,
4081 .mbx_ops = &mbx_ops_generic,
4082 .mvals = ixgbe_mvals_X550EM_x,
4083};
4084
4085const struct ixgbe_info ixgbe_x550em_a_info = {
4086 .mac = ixgbe_mac_x550em_a,
4087 .get_invariants = &ixgbe_get_invariants_X550_a,
4088 .mac_ops = &mac_ops_x550em_a,
4089 .eeprom_ops = &eeprom_ops_X550EM_x,
4090 .phy_ops = &phy_ops_x550em_a,
4091 .mbx_ops = &mbx_ops_generic,
4092 .mvals = ixgbe_mvals_x550em_a,
4093};
4094
4095const struct ixgbe_info ixgbe_x550em_a_fw_info = {
4096 .mac = ixgbe_mac_x550em_a,
4097 .get_invariants = ixgbe_get_invariants_X550_a_fw,
4098 .mac_ops = &mac_ops_x550em_a_fw,
4099 .eeprom_ops = &eeprom_ops_X550EM_x,
4100 .phy_ops = &phy_ops_x550em_a_fw,
4101 .mbx_ops = &mbx_ops_generic,
4102 .mvals = ixgbe_mvals_x550em_a,
4103};
1/*******************************************************************************
2 *
3 * Intel 10 Gigabit PCI Express Linux driver
4 * Copyright(c) 1999 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * The full GNU General Public License is included in this distribution in
16 * the file called "COPYING".
17 *
18 * Contact Information:
19 * Linux NICS <linux.nics@intel.com>
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 *
23 ******************************************************************************/
24#include "ixgbe_x540.h"
25#include "ixgbe_type.h"
26#include "ixgbe_common.h"
27#include "ixgbe_phy.h"
28
29static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *, ixgbe_link_speed);
30static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *);
31static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *);
32static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *);
33static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *);
34
35static s32 ixgbe_get_invariants_X550_x(struct ixgbe_hw *hw)
36{
37 struct ixgbe_mac_info *mac = &hw->mac;
38 struct ixgbe_phy_info *phy = &hw->phy;
39 struct ixgbe_link_info *link = &hw->link;
40
41 /* Start with X540 invariants, since so simular */
42 ixgbe_get_invariants_X540(hw);
43
44 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
45 phy->ops.set_phy_power = NULL;
46
47 link->addr = IXGBE_CS4227;
48
49 return 0;
50}
51
52static s32 ixgbe_get_invariants_X550_a(struct ixgbe_hw *hw)
53{
54 struct ixgbe_mac_info *mac = &hw->mac;
55 struct ixgbe_phy_info *phy = &hw->phy;
56
57 /* Start with X540 invariants, since so simular */
58 ixgbe_get_invariants_X540(hw);
59
60 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper)
61 phy->ops.set_phy_power = NULL;
62
63 return 0;
64}
65
66/** ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control
67 * @hw: pointer to hardware structure
68 **/
69static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw)
70{
71 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
72
73 if (hw->bus.lan_id) {
74 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1);
75 esdp |= IXGBE_ESDP_SDP1_DIR;
76 }
77 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR);
78 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
79 IXGBE_WRITE_FLUSH(hw);
80}
81
82/**
83 * ixgbe_read_cs4227 - Read CS4227 register
84 * @hw: pointer to hardware structure
85 * @reg: register number to write
86 * @value: pointer to receive value read
87 *
88 * Returns status code
89 */
90static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value)
91{
92 return hw->link.ops.read_link_unlocked(hw, hw->link.addr, reg, value);
93}
94
95/**
96 * ixgbe_write_cs4227 - Write CS4227 register
97 * @hw: pointer to hardware structure
98 * @reg: register number to write
99 * @value: value to write to register
100 *
101 * Returns status code
102 */
103static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value)
104{
105 return hw->link.ops.write_link_unlocked(hw, hw->link.addr, reg, value);
106}
107
108/**
109 * ixgbe_read_pe - Read register from port expander
110 * @hw: pointer to hardware structure
111 * @reg: register number to read
112 * @value: pointer to receive read value
113 *
114 * Returns status code
115 */
116static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value)
117{
118 s32 status;
119
120 status = ixgbe_read_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE, value);
121 if (status)
122 hw_err(hw, "port expander access failed with %d\n", status);
123 return status;
124}
125
126/**
127 * ixgbe_write_pe - Write register to port expander
128 * @hw: pointer to hardware structure
129 * @reg: register number to write
130 * @value: value to write
131 *
132 * Returns status code
133 */
134static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value)
135{
136 s32 status;
137
138 status = ixgbe_write_i2c_byte_generic_unlocked(hw, reg, IXGBE_PE,
139 value);
140 if (status)
141 hw_err(hw, "port expander access failed with %d\n", status);
142 return status;
143}
144
145/**
146 * ixgbe_reset_cs4227 - Reset CS4227 using port expander
147 * @hw: pointer to hardware structure
148 *
149 * This function assumes that the caller has acquired the proper semaphore.
150 * Returns error code
151 */
152static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw)
153{
154 s32 status;
155 u32 retry;
156 u16 value;
157 u8 reg;
158
159 /* Trigger hard reset. */
160 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
161 if (status)
162 return status;
163 reg |= IXGBE_PE_BIT1;
164 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
165 if (status)
166 return status;
167
168 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®);
169 if (status)
170 return status;
171 reg &= ~IXGBE_PE_BIT1;
172 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg);
173 if (status)
174 return status;
175
176 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
177 if (status)
178 return status;
179 reg &= ~IXGBE_PE_BIT1;
180 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
181 if (status)
182 return status;
183
184 usleep_range(IXGBE_CS4227_RESET_HOLD, IXGBE_CS4227_RESET_HOLD + 100);
185
186 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®);
187 if (status)
188 return status;
189 reg |= IXGBE_PE_BIT1;
190 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg);
191 if (status)
192 return status;
193
194 /* Wait for the reset to complete. */
195 msleep(IXGBE_CS4227_RESET_DELAY);
196 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
197 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EFUSE_STATUS,
198 &value);
199 if (!status && value == IXGBE_CS4227_EEPROM_LOAD_OK)
200 break;
201 msleep(IXGBE_CS4227_CHECK_DELAY);
202 }
203 if (retry == IXGBE_CS4227_RETRIES) {
204 hw_err(hw, "CS4227 reset did not complete\n");
205 return IXGBE_ERR_PHY;
206 }
207
208 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_EEPROM_STATUS, &value);
209 if (status || !(value & IXGBE_CS4227_EEPROM_LOAD_OK)) {
210 hw_err(hw, "CS4227 EEPROM did not load successfully\n");
211 return IXGBE_ERR_PHY;
212 }
213
214 return 0;
215}
216
217/**
218 * ixgbe_check_cs4227 - Check CS4227 and reset as needed
219 * @hw: pointer to hardware structure
220 */
221static void ixgbe_check_cs4227(struct ixgbe_hw *hw)
222{
223 u32 swfw_mask = hw->phy.phy_semaphore_mask;
224 s32 status;
225 u16 value;
226 u8 retry;
227
228 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) {
229 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
230 if (status) {
231 hw_err(hw, "semaphore failed with %d\n", status);
232 msleep(IXGBE_CS4227_CHECK_DELAY);
233 continue;
234 }
235
236 /* Get status of reset flow. */
237 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value);
238 if (!status && value == IXGBE_CS4227_RESET_COMPLETE)
239 goto out;
240
241 if (status || value != IXGBE_CS4227_RESET_PENDING)
242 break;
243
244 /* Reset is pending. Wait and check again. */
245 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
246 msleep(IXGBE_CS4227_CHECK_DELAY);
247 }
248 /* If still pending, assume other instance failed. */
249 if (retry == IXGBE_CS4227_RETRIES) {
250 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
251 if (status) {
252 hw_err(hw, "semaphore failed with %d\n", status);
253 return;
254 }
255 }
256
257 /* Reset the CS4227. */
258 status = ixgbe_reset_cs4227(hw);
259 if (status) {
260 hw_err(hw, "CS4227 reset failed: %d", status);
261 goto out;
262 }
263
264 /* Reset takes so long, temporarily release semaphore in case the
265 * other driver instance is waiting for the reset indication.
266 */
267 ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
268 IXGBE_CS4227_RESET_PENDING);
269 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
270 usleep_range(10000, 12000);
271 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
272 if (status) {
273 hw_err(hw, "semaphore failed with %d", status);
274 return;
275 }
276
277 /* Record completion for next time. */
278 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH,
279 IXGBE_CS4227_RESET_COMPLETE);
280
281out:
282 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
283 msleep(hw->eeprom.semaphore_delay);
284}
285
286/** ixgbe_identify_phy_x550em - Get PHY type based on device id
287 * @hw: pointer to hardware structure
288 *
289 * Returns error code
290 */
291static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw)
292{
293 switch (hw->device_id) {
294 case IXGBE_DEV_ID_X550EM_A_SFP:
295 if (hw->bus.lan_id)
296 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
297 else
298 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
299 return ixgbe_identify_module_generic(hw);
300 case IXGBE_DEV_ID_X550EM_X_SFP:
301 /* set up for CS4227 usage */
302 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
303 ixgbe_setup_mux_ctl(hw);
304 ixgbe_check_cs4227(hw);
305 /* Fallthrough */
306 case IXGBE_DEV_ID_X550EM_A_SFP_N:
307 return ixgbe_identify_module_generic(hw);
308 case IXGBE_DEV_ID_X550EM_X_KX4:
309 hw->phy.type = ixgbe_phy_x550em_kx4;
310 break;
311 case IXGBE_DEV_ID_X550EM_X_KR:
312 case IXGBE_DEV_ID_X550EM_A_KR:
313 case IXGBE_DEV_ID_X550EM_A_KR_L:
314 hw->phy.type = ixgbe_phy_x550em_kr;
315 break;
316 case IXGBE_DEV_ID_X550EM_A_10G_T:
317 if (hw->bus.lan_id)
318 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
319 else
320 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
321 /* Fallthrough */
322 case IXGBE_DEV_ID_X550EM_X_1G_T:
323 case IXGBE_DEV_ID_X550EM_X_10G_T:
324 return ixgbe_identify_phy_generic(hw);
325 default:
326 break;
327 }
328 return 0;
329}
330
331static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
332 u32 device_type, u16 *phy_data)
333{
334 return IXGBE_NOT_IMPLEMENTED;
335}
336
337static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr,
338 u32 device_type, u16 phy_data)
339{
340 return IXGBE_NOT_IMPLEMENTED;
341}
342
343/**
344 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
345 * @hw: pointer to the hardware structure
346 * @addr: I2C bus address to read from
347 * @reg: I2C device register to read from
348 * @val: pointer to location to receive read value
349 *
350 * Returns an error code on error.
351 **/
352static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
353 u16 reg, u16 *val)
354{
355 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, true);
356}
357
358/**
359 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation
360 * @hw: pointer to the hardware structure
361 * @addr: I2C bus address to read from
362 * @reg: I2C device register to read from
363 * @val: pointer to location to receive read value
364 *
365 * Returns an error code on error.
366 **/
367static s32
368ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr,
369 u16 reg, u16 *val)
370{
371 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, false);
372}
373
374/**
375 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
376 * @hw: pointer to the hardware structure
377 * @addr: I2C bus address to write to
378 * @reg: I2C device register to write to
379 * @val: value to write
380 *
381 * Returns an error code on error.
382 **/
383static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
384 u8 addr, u16 reg, u16 val)
385{
386 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, true);
387}
388
389/**
390 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation
391 * @hw: pointer to the hardware structure
392 * @addr: I2C bus address to write to
393 * @reg: I2C device register to write to
394 * @val: value to write
395 *
396 * Returns an error code on error.
397 **/
398static s32
399ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw,
400 u8 addr, u16 reg, u16 val)
401{
402 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, false);
403}
404
405/** ixgbe_init_eeprom_params_X550 - Initialize EEPROM params
406 * @hw: pointer to hardware structure
407 *
408 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
409 * ixgbe_hw struct in order to set up EEPROM access.
410 **/
411static s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw)
412{
413 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
414 u32 eec;
415 u16 eeprom_size;
416
417 if (eeprom->type == ixgbe_eeprom_uninitialized) {
418 eeprom->semaphore_delay = 10;
419 eeprom->type = ixgbe_flash;
420
421 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
422 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
423 IXGBE_EEC_SIZE_SHIFT);
424 eeprom->word_size = BIT(eeprom_size +
425 IXGBE_EEPROM_WORD_SIZE_SHIFT);
426
427 hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
428 eeprom->type, eeprom->word_size);
429 }
430
431 return 0;
432}
433
434/**
435 * ixgbe_iosf_wait - Wait for IOSF command completion
436 * @hw: pointer to hardware structure
437 * @ctrl: pointer to location to receive final IOSF control value
438 *
439 * Return: failing status on timeout
440 *
441 * Note: ctrl can be NULL if the IOSF control register value is not needed
442 */
443static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl)
444{
445 u32 i, command;
446
447 /* Check every 10 usec to see if the address cycle completed.
448 * The SB IOSF BUSY bit will clear when the operation is
449 * complete.
450 */
451 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
452 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL);
453 if (!(command & IXGBE_SB_IOSF_CTRL_BUSY))
454 break;
455 udelay(10);
456 }
457 if (ctrl)
458 *ctrl = command;
459 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) {
460 hw_dbg(hw, "IOSF wait timed out\n");
461 return IXGBE_ERR_PHY;
462 }
463
464 return 0;
465}
466
467/** ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the
468 * IOSF device
469 * @hw: pointer to hardware structure
470 * @reg_addr: 32 bit PHY register to write
471 * @device_type: 3 bit device type
472 * @phy_data: Pointer to read data from the register
473 **/
474static s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
475 u32 device_type, u32 *data)
476{
477 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
478 u32 command, error;
479 s32 ret;
480
481 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
482 if (ret)
483 return ret;
484
485 ret = ixgbe_iosf_wait(hw, NULL);
486 if (ret)
487 goto out;
488
489 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
490 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
491
492 /* Write IOSF control register */
493 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
494
495 ret = ixgbe_iosf_wait(hw, &command);
496
497 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
498 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
499 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
500 hw_dbg(hw, "Failed to read, error %x\n", error);
501 return IXGBE_ERR_PHY;
502 }
503
504 if (!ret)
505 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA);
506
507out:
508 hw->mac.ops.release_swfw_sync(hw, gssr);
509 return ret;
510}
511
512/**
513 * ixgbe_get_phy_token - Get the token for shared PHY access
514 * @hw: Pointer to hardware structure
515 */
516static s32 ixgbe_get_phy_token(struct ixgbe_hw *hw)
517{
518 struct ixgbe_hic_phy_token_req token_cmd;
519 s32 status;
520
521 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
522 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
523 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
524 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
525 token_cmd.port_number = hw->bus.lan_id;
526 token_cmd.command_type = FW_PHY_TOKEN_REQ;
527 token_cmd.pad = 0;
528 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
529 IXGBE_HI_COMMAND_TIMEOUT,
530 true);
531 if (status)
532 return status;
533 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
534 return 0;
535 if (token_cmd.hdr.cmd_or_resp.ret_status != FW_PHY_TOKEN_RETRY)
536 return IXGBE_ERR_FW_RESP_INVALID;
537
538 return IXGBE_ERR_TOKEN_RETRY;
539}
540
541/**
542 * ixgbe_put_phy_token - Put the token for shared PHY access
543 * @hw: Pointer to hardware structure
544 */
545static s32 ixgbe_put_phy_token(struct ixgbe_hw *hw)
546{
547 struct ixgbe_hic_phy_token_req token_cmd;
548 s32 status;
549
550 token_cmd.hdr.cmd = FW_PHY_TOKEN_REQ_CMD;
551 token_cmd.hdr.buf_len = FW_PHY_TOKEN_REQ_LEN;
552 token_cmd.hdr.cmd_or_resp.cmd_resv = 0;
553 token_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
554 token_cmd.port_number = hw->bus.lan_id;
555 token_cmd.command_type = FW_PHY_TOKEN_REL;
556 token_cmd.pad = 0;
557 status = ixgbe_host_interface_command(hw, &token_cmd, sizeof(token_cmd),
558 IXGBE_HI_COMMAND_TIMEOUT,
559 true);
560 if (status)
561 return status;
562 if (token_cmd.hdr.cmd_or_resp.ret_status == FW_PHY_TOKEN_OK)
563 return 0;
564 return IXGBE_ERR_FW_RESP_INVALID;
565}
566
567/**
568 * ixgbe_write_iosf_sb_reg_x550a - Write to IOSF PHY register
569 * @hw: pointer to hardware structure
570 * @reg_addr: 32 bit PHY register to write
571 * @device_type: 3 bit device type
572 * @data: Data to write to the register
573 **/
574static s32 ixgbe_write_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
575 __always_unused u32 device_type,
576 u32 data)
577{
578 struct ixgbe_hic_internal_phy_req write_cmd;
579
580 memset(&write_cmd, 0, sizeof(write_cmd));
581 write_cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
582 write_cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
583 write_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
584 write_cmd.port_number = hw->bus.lan_id;
585 write_cmd.command_type = FW_INT_PHY_REQ_WRITE;
586 write_cmd.address = cpu_to_be16(reg_addr);
587 write_cmd.write_data = cpu_to_be32(data);
588
589 return ixgbe_host_interface_command(hw, &write_cmd, sizeof(write_cmd),
590 IXGBE_HI_COMMAND_TIMEOUT, false);
591}
592
593/**
594 * ixgbe_read_iosf_sb_reg_x550a - Read from IOSF PHY register
595 * @hw: pointer to hardware structure
596 * @reg_addr: 32 bit PHY register to write
597 * @device_type: 3 bit device type
598 * @data: Pointer to read data from the register
599 **/
600static s32 ixgbe_read_iosf_sb_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
601 __always_unused u32 device_type,
602 u32 *data)
603{
604 union {
605 struct ixgbe_hic_internal_phy_req cmd;
606 struct ixgbe_hic_internal_phy_resp rsp;
607 } hic;
608 s32 status;
609
610 memset(&hic, 0, sizeof(hic));
611 hic.cmd.hdr.cmd = FW_INT_PHY_REQ_CMD;
612 hic.cmd.hdr.buf_len = FW_INT_PHY_REQ_LEN;
613 hic.cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
614 hic.cmd.port_number = hw->bus.lan_id;
615 hic.cmd.command_type = FW_INT_PHY_REQ_READ;
616 hic.cmd.address = cpu_to_be16(reg_addr);
617
618 status = ixgbe_host_interface_command(hw, &hic.cmd, sizeof(hic.cmd),
619 IXGBE_HI_COMMAND_TIMEOUT, true);
620
621 /* Extract the register value from the response. */
622 *data = be32_to_cpu(hic.rsp.read_data);
623
624 return status;
625}
626
627/** ixgbe_read_ee_hostif_data_X550 - Read EEPROM word using a host interface
628 * command assuming that the semaphore is already obtained.
629 * @hw: pointer to hardware structure
630 * @offset: offset of word in the EEPROM to read
631 * @data: word read from the EEPROM
632 *
633 * Reads a 16 bit word from the EEPROM using the hostif.
634 **/
635static s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
636 u16 *data)
637{
638 s32 status;
639 struct ixgbe_hic_read_shadow_ram buffer;
640
641 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
642 buffer.hdr.req.buf_lenh = 0;
643 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
644 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
645
646 /* convert offset from words to bytes */
647 buffer.address = cpu_to_be32(offset * 2);
648 /* one word */
649 buffer.length = cpu_to_be16(sizeof(u16));
650
651 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
652 IXGBE_HI_COMMAND_TIMEOUT, false);
653 if (status)
654 return status;
655
656 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
657 FW_NVM_DATA_OFFSET);
658
659 return 0;
660}
661
662/** ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif
663 * @hw: pointer to hardware structure
664 * @offset: offset of word in the EEPROM to read
665 * @words: number of words
666 * @data: word(s) read from the EEPROM
667 *
668 * Reads a 16 bit word(s) from the EEPROM using the hostif.
669 **/
670static s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
671 u16 offset, u16 words, u16 *data)
672{
673 struct ixgbe_hic_read_shadow_ram buffer;
674 u32 current_word = 0;
675 u16 words_to_read;
676 s32 status;
677 u32 i;
678
679 /* Take semaphore for the entire operation. */
680 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
681 if (status) {
682 hw_dbg(hw, "EEPROM read buffer - semaphore failed\n");
683 return status;
684 }
685
686 while (words) {
687 if (words > FW_MAX_READ_BUFFER_SIZE / 2)
688 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2;
689 else
690 words_to_read = words;
691
692 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD;
693 buffer.hdr.req.buf_lenh = 0;
694 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN;
695 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
696
697 /* convert offset from words to bytes */
698 buffer.address = cpu_to_be32((offset + current_word) * 2);
699 buffer.length = cpu_to_be16(words_to_read * 2);
700
701 status = ixgbe_host_interface_command(hw, &buffer,
702 sizeof(buffer),
703 IXGBE_HI_COMMAND_TIMEOUT,
704 false);
705 if (status) {
706 hw_dbg(hw, "Host interface command failed\n");
707 goto out;
708 }
709
710 for (i = 0; i < words_to_read; i++) {
711 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) +
712 2 * i;
713 u32 value = IXGBE_READ_REG(hw, reg);
714
715 data[current_word] = (u16)(value & 0xffff);
716 current_word++;
717 i++;
718 if (i < words_to_read) {
719 value >>= 16;
720 data[current_word] = (u16)(value & 0xffff);
721 current_word++;
722 }
723 }
724 words -= words_to_read;
725 }
726
727out:
728 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
729 return status;
730}
731
732/** ixgbe_checksum_ptr_x550 - Checksum one pointer region
733 * @hw: pointer to hardware structure
734 * @ptr: pointer offset in eeprom
735 * @size: size of section pointed by ptr, if 0 first word will be used as size
736 * @csum: address of checksum to update
737 *
738 * Returns error status for any failure
739 **/
740static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr,
741 u16 size, u16 *csum, u16 *buffer,
742 u32 buffer_size)
743{
744 u16 buf[256];
745 s32 status;
746 u16 length, bufsz, i, start;
747 u16 *local_buffer;
748
749 bufsz = sizeof(buf) / sizeof(buf[0]);
750
751 /* Read a chunk at the pointer location */
752 if (!buffer) {
753 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf);
754 if (status) {
755 hw_dbg(hw, "Failed to read EEPROM image\n");
756 return status;
757 }
758 local_buffer = buf;
759 } else {
760 if (buffer_size < ptr)
761 return IXGBE_ERR_PARAM;
762 local_buffer = &buffer[ptr];
763 }
764
765 if (size) {
766 start = 0;
767 length = size;
768 } else {
769 start = 1;
770 length = local_buffer[0];
771
772 /* Skip pointer section if length is invalid. */
773 if (length == 0xFFFF || length == 0 ||
774 (ptr + length) >= hw->eeprom.word_size)
775 return 0;
776 }
777
778 if (buffer && ((u32)start + (u32)length > buffer_size))
779 return IXGBE_ERR_PARAM;
780
781 for (i = start; length; i++, length--) {
782 if (i == bufsz && !buffer) {
783 ptr += bufsz;
784 i = 0;
785 if (length < bufsz)
786 bufsz = length;
787
788 /* Read a chunk at the pointer location */
789 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr,
790 bufsz, buf);
791 if (status) {
792 hw_dbg(hw, "Failed to read EEPROM image\n");
793 return status;
794 }
795 }
796 *csum += local_buffer[i];
797 }
798 return 0;
799}
800
801/** ixgbe_calc_checksum_X550 - Calculates and returns the checksum
802 * @hw: pointer to hardware structure
803 * @buffer: pointer to buffer containing calculated checksum
804 * @buffer_size: size of buffer
805 *
806 * Returns a negative error code on error, or the 16-bit checksum
807 **/
808static s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer,
809 u32 buffer_size)
810{
811 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1];
812 u16 *local_buffer;
813 s32 status;
814 u16 checksum = 0;
815 u16 pointer, i, size;
816
817 hw->eeprom.ops.init_params(hw);
818
819 if (!buffer) {
820 /* Read pointer area */
821 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0,
822 IXGBE_EEPROM_LAST_WORD + 1,
823 eeprom_ptrs);
824 if (status) {
825 hw_dbg(hw, "Failed to read EEPROM image\n");
826 return status;
827 }
828 local_buffer = eeprom_ptrs;
829 } else {
830 if (buffer_size < IXGBE_EEPROM_LAST_WORD)
831 return IXGBE_ERR_PARAM;
832 local_buffer = buffer;
833 }
834
835 /* For X550 hardware include 0x0-0x41 in the checksum, skip the
836 * checksum word itself
837 */
838 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++)
839 if (i != IXGBE_EEPROM_CHECKSUM)
840 checksum += local_buffer[i];
841
842 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the
843 * FW, PHY module, and PCIe Expansion/Option ROM pointers.
844 */
845 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) {
846 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
847 continue;
848
849 pointer = local_buffer[i];
850
851 /* Skip pointer section if the pointer is invalid. */
852 if (pointer == 0xFFFF || pointer == 0 ||
853 pointer >= hw->eeprom.word_size)
854 continue;
855
856 switch (i) {
857 case IXGBE_PCIE_GENERAL_PTR:
858 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE;
859 break;
860 case IXGBE_PCIE_CONFIG0_PTR:
861 case IXGBE_PCIE_CONFIG1_PTR:
862 size = IXGBE_PCIE_CONFIG_SIZE;
863 break;
864 default:
865 size = 0;
866 break;
867 }
868
869 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum,
870 buffer, buffer_size);
871 if (status)
872 return status;
873 }
874
875 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
876
877 return (s32)checksum;
878}
879
880/** ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum
881 * @hw: pointer to hardware structure
882 *
883 * Returns a negative error code on error, or the 16-bit checksum
884 **/
885static s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw)
886{
887 return ixgbe_calc_checksum_X550(hw, NULL, 0);
888}
889
890/** ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command
891 * @hw: pointer to hardware structure
892 * @offset: offset of word in the EEPROM to read
893 * @data: word read from the EEPROM
894 *
895 * Reads a 16 bit word from the EEPROM using the hostif.
896 **/
897static s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 *data)
898{
899 s32 status = 0;
900
901 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
902 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data);
903 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
904 } else {
905 status = IXGBE_ERR_SWFW_SYNC;
906 }
907
908 return status;
909}
910
911/** ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum
912 * @hw: pointer to hardware structure
913 * @checksum_val: calculated checksum
914 *
915 * Performs checksum calculation and validates the EEPROM checksum. If the
916 * caller does not need checksum_val, the value can be NULL.
917 **/
918static s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw,
919 u16 *checksum_val)
920{
921 s32 status;
922 u16 checksum;
923 u16 read_checksum = 0;
924
925 /* Read the first word from the EEPROM. If this times out or fails, do
926 * not continue or we could be in for a very long wait while every
927 * EEPROM read fails
928 */
929 status = hw->eeprom.ops.read(hw, 0, &checksum);
930 if (status) {
931 hw_dbg(hw, "EEPROM read failed\n");
932 return status;
933 }
934
935 status = hw->eeprom.ops.calc_checksum(hw);
936 if (status < 0)
937 return status;
938
939 checksum = (u16)(status & 0xffff);
940
941 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
942 &read_checksum);
943 if (status)
944 return status;
945
946 /* Verify read checksum from EEPROM is the same as
947 * calculated checksum
948 */
949 if (read_checksum != checksum) {
950 status = IXGBE_ERR_EEPROM_CHECKSUM;
951 hw_dbg(hw, "Invalid EEPROM checksum");
952 }
953
954 /* If the user cares, return the calculated checksum */
955 if (checksum_val)
956 *checksum_val = checksum;
957
958 return status;
959}
960
961/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
962 * @hw: pointer to hardware structure
963 * @offset: offset of word in the EEPROM to write
964 * @data: word write to the EEPROM
965 *
966 * Write a 16 bit word to the EEPROM using the hostif.
967 **/
968static s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset,
969 u16 data)
970{
971 s32 status;
972 struct ixgbe_hic_write_shadow_ram buffer;
973
974 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD;
975 buffer.hdr.req.buf_lenh = 0;
976 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN;
977 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM;
978
979 /* one word */
980 buffer.length = cpu_to_be16(sizeof(u16));
981 buffer.data = data;
982 buffer.address = cpu_to_be32(offset * 2);
983
984 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
985 IXGBE_HI_COMMAND_TIMEOUT, false);
986 return status;
987}
988
989/** ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif
990 * @hw: pointer to hardware structure
991 * @offset: offset of word in the EEPROM to write
992 * @data: word write to the EEPROM
993 *
994 * Write a 16 bit word to the EEPROM using the hostif.
995 **/
996static s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, u16 data)
997{
998 s32 status = 0;
999
1000 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 0) {
1001 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data);
1002 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1003 } else {
1004 hw_dbg(hw, "write ee hostif failed to get semaphore");
1005 status = IXGBE_ERR_SWFW_SYNC;
1006 }
1007
1008 return status;
1009}
1010
1011/** ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device
1012 * @hw: pointer to hardware structure
1013 *
1014 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash.
1015 **/
1016static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
1017{
1018 s32 status = 0;
1019 union ixgbe_hic_hdr2 buffer;
1020
1021 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD;
1022 buffer.req.buf_lenh = 0;
1023 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN;
1024 buffer.req.checksum = FW_DEFAULT_CHECKSUM;
1025
1026 status = ixgbe_host_interface_command(hw, &buffer, sizeof(buffer),
1027 IXGBE_HI_COMMAND_TIMEOUT, false);
1028 return status;
1029}
1030
1031/**
1032 * ixgbe_get_bus_info_X550em - Set PCI bus info
1033 * @hw: pointer to hardware structure
1034 *
1035 * Sets bus link width and speed to unknown because X550em is
1036 * not a PCI device.
1037 **/
1038static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
1039{
1040 hw->bus.type = ixgbe_bus_type_internal;
1041 hw->bus.width = ixgbe_bus_width_unknown;
1042 hw->bus.speed = ixgbe_bus_speed_unknown;
1043
1044 hw->mac.ops.set_lan_id(hw);
1045
1046 return 0;
1047}
1048
1049/** ixgbe_disable_rx_x550 - Disable RX unit
1050 *
1051 * Enables the Rx DMA unit for x550
1052 **/
1053static void ixgbe_disable_rx_x550(struct ixgbe_hw *hw)
1054{
1055 u32 rxctrl, pfdtxgswc;
1056 s32 status;
1057 struct ixgbe_hic_disable_rxen fw_cmd;
1058
1059 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1060 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1061 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
1062 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
1063 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
1064 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
1065 hw->mac.set_lben = true;
1066 } else {
1067 hw->mac.set_lben = false;
1068 }
1069
1070 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD;
1071 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN;
1072 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM;
1073 fw_cmd.port_number = hw->bus.lan_id;
1074
1075 status = ixgbe_host_interface_command(hw, &fw_cmd,
1076 sizeof(struct ixgbe_hic_disable_rxen),
1077 IXGBE_HI_COMMAND_TIMEOUT, true);
1078
1079 /* If we fail - disable RX using register write */
1080 if (status) {
1081 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
1082 if (rxctrl & IXGBE_RXCTRL_RXEN) {
1083 rxctrl &= ~IXGBE_RXCTRL_RXEN;
1084 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
1085 }
1086 }
1087 }
1088}
1089
1090/** ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash
1091 * @hw: pointer to hardware structure
1092 *
1093 * After writing EEPROM to shadow RAM using EEWR register, software calculates
1094 * checksum and updates the EEPROM and instructs the hardware to update
1095 * the flash.
1096 **/
1097static s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw)
1098{
1099 s32 status;
1100 u16 checksum = 0;
1101
1102 /* Read the first word from the EEPROM. If this times out or fails, do
1103 * not continue or we could be in for a very long wait while every
1104 * EEPROM read fails
1105 */
1106 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum);
1107 if (status) {
1108 hw_dbg(hw, "EEPROM read failed\n");
1109 return status;
1110 }
1111
1112 status = ixgbe_calc_eeprom_checksum_X550(hw);
1113 if (status < 0)
1114 return status;
1115
1116 checksum = (u16)(status & 0xffff);
1117
1118 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM,
1119 checksum);
1120 if (status)
1121 return status;
1122
1123 status = ixgbe_update_flash_X550(hw);
1124
1125 return status;
1126}
1127
1128/** ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif
1129 * @hw: pointer to hardware structure
1130 * @offset: offset of word in the EEPROM to write
1131 * @words: number of words
1132 * @data: word(s) write to the EEPROM
1133 *
1134 *
1135 * Write a 16 bit word(s) to the EEPROM using the hostif.
1136 **/
1137static s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw,
1138 u16 offset, u16 words,
1139 u16 *data)
1140{
1141 s32 status = 0;
1142 u32 i = 0;
1143
1144 /* Take semaphore for the entire operation. */
1145 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1146 if (status) {
1147 hw_dbg(hw, "EEPROM write buffer - semaphore failed\n");
1148 return status;
1149 }
1150
1151 for (i = 0; i < words; i++) {
1152 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i,
1153 data[i]);
1154 if (status) {
1155 hw_dbg(hw, "Eeprom buffered write failed\n");
1156 break;
1157 }
1158 }
1159
1160 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1161
1162 return status;
1163}
1164
1165/** ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the
1166 * IOSF device
1167 *
1168 * @hw: pointer to hardware structure
1169 * @reg_addr: 32 bit PHY register to write
1170 * @device_type: 3 bit device type
1171 * @data: Data to write to the register
1172 **/
1173static s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr,
1174 u32 device_type, u32 data)
1175{
1176 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM;
1177 u32 command, error;
1178 s32 ret;
1179
1180 ret = hw->mac.ops.acquire_swfw_sync(hw, gssr);
1181 if (ret)
1182 return ret;
1183
1184 ret = ixgbe_iosf_wait(hw, NULL);
1185 if (ret)
1186 goto out;
1187
1188 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) |
1189 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT));
1190
1191 /* Write IOSF control register */
1192 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command);
1193
1194 /* Write IOSF data register */
1195 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data);
1196
1197 ret = ixgbe_iosf_wait(hw, &command);
1198
1199 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) {
1200 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >>
1201 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT;
1202 hw_dbg(hw, "Failed to write, error %x\n", error);
1203 return IXGBE_ERR_PHY;
1204 }
1205
1206out:
1207 hw->mac.ops.release_swfw_sync(hw, gssr);
1208 return ret;
1209}
1210
1211/**
1212 * ixgbe_setup_ixfi_x550em_x - MAC specific iXFI configuration
1213 * @hw: pointer to hardware structure
1214 *
1215 * iXfI configuration needed for ixgbe_mac_X550EM_x devices.
1216 **/
1217static s32 ixgbe_setup_ixfi_x550em_x(struct ixgbe_hw *hw)
1218{
1219 s32 status;
1220 u32 reg_val;
1221
1222 /* Disable training protocol FSM. */
1223 status = ixgbe_read_iosf_sb_reg_x550(hw,
1224 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1225 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1226 if (status)
1227 return status;
1228
1229 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL;
1230 status = ixgbe_write_iosf_sb_reg_x550(hw,
1231 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id),
1232 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1233 if (status)
1234 return status;
1235
1236 /* Disable Flex from training TXFFE. */
1237 status = ixgbe_read_iosf_sb_reg_x550(hw,
1238 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1239 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1240 if (status)
1241 return status;
1242
1243 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1244 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1245 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1246 status = ixgbe_write_iosf_sb_reg_x550(hw,
1247 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id),
1248 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1249 if (status)
1250 return status;
1251
1252 status = ixgbe_read_iosf_sb_reg_x550(hw,
1253 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1254 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1255 if (status)
1256 return status;
1257
1258 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN;
1259 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN;
1260 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN;
1261 status = ixgbe_write_iosf_sb_reg_x550(hw,
1262 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id),
1263 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1264 if (status)
1265 return status;
1266
1267 /* Enable override for coefficients. */
1268 status = ixgbe_read_iosf_sb_reg_x550(hw,
1269 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1270 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1271 if (status)
1272 return status;
1273
1274 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN;
1275 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN;
1276 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN;
1277 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN;
1278 status = ixgbe_write_iosf_sb_reg_x550(hw,
1279 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id),
1280 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1281 return status;
1282}
1283
1284/**
1285 * ixgbe_restart_an_internal_phy_x550em - restart autonegotiation for the
1286 * internal PHY
1287 * @hw: pointer to hardware structure
1288 **/
1289static s32 ixgbe_restart_an_internal_phy_x550em(struct ixgbe_hw *hw)
1290{
1291 s32 status;
1292 u32 link_ctrl;
1293
1294 /* Restart auto-negotiation. */
1295 status = hw->mac.ops.read_iosf_sb_reg(hw,
1296 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1297 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_ctrl);
1298
1299 if (status) {
1300 hw_dbg(hw, "Auto-negotiation did not complete\n");
1301 return status;
1302 }
1303
1304 link_ctrl |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART;
1305 status = hw->mac.ops.write_iosf_sb_reg(hw,
1306 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1307 IXGBE_SB_IOSF_TARGET_KR_PHY, link_ctrl);
1308
1309 if (hw->mac.type == ixgbe_mac_x550em_a) {
1310 u32 flx_mask_st20;
1311
1312 /* Indicate to FW that AN restart has been asserted */
1313 status = hw->mac.ops.read_iosf_sb_reg(hw,
1314 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1315 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_mask_st20);
1316
1317 if (status) {
1318 hw_dbg(hw, "Auto-negotiation did not complete\n");
1319 return status;
1320 }
1321
1322 flx_mask_st20 |= IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART;
1323 status = hw->mac.ops.write_iosf_sb_reg(hw,
1324 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1325 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_mask_st20);
1326 }
1327
1328 return status;
1329}
1330
1331/** ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode.
1332 * @hw: pointer to hardware structure
1333 * @speed: the link speed to force
1334 *
1335 * Configures the integrated KR PHY to use iXFI mode. Used to connect an
1336 * internal and external PHY at a specific speed, without autonegotiation.
1337 **/
1338static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1339{
1340 s32 status;
1341 u32 reg_val;
1342
1343 /* Disable AN and force speed to 10G Serial. */
1344 status = ixgbe_read_iosf_sb_reg_x550(hw,
1345 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1346 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1347 if (status)
1348 return status;
1349
1350 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1351 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1352
1353 /* Select forced link speed for internal PHY. */
1354 switch (*speed) {
1355 case IXGBE_LINK_SPEED_10GB_FULL:
1356 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G;
1357 break;
1358 case IXGBE_LINK_SPEED_1GB_FULL:
1359 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1360 break;
1361 default:
1362 /* Other link speeds are not supported by internal KR PHY. */
1363 return IXGBE_ERR_LINK_SETUP;
1364 }
1365
1366 status = ixgbe_write_iosf_sb_reg_x550(hw,
1367 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1368 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1369 if (status)
1370 return status;
1371
1372 /* Additional configuration needed for x550em_x */
1373 if (hw->mac.type == ixgbe_mac_X550EM_x) {
1374 status = ixgbe_setup_ixfi_x550em_x(hw);
1375 if (status)
1376 return status;
1377 }
1378
1379 /* Toggle port SW reset by AN reset. */
1380 status = ixgbe_restart_an_internal_phy_x550em(hw);
1381
1382 return status;
1383}
1384
1385/**
1386 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported
1387 * @hw: pointer to hardware structure
1388 * @linear: true if SFP module is linear
1389 */
1390static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear)
1391{
1392 switch (hw->phy.sfp_type) {
1393 case ixgbe_sfp_type_not_present:
1394 return IXGBE_ERR_SFP_NOT_PRESENT;
1395 case ixgbe_sfp_type_da_cu_core0:
1396 case ixgbe_sfp_type_da_cu_core1:
1397 *linear = true;
1398 break;
1399 case ixgbe_sfp_type_srlr_core0:
1400 case ixgbe_sfp_type_srlr_core1:
1401 case ixgbe_sfp_type_da_act_lmt_core0:
1402 case ixgbe_sfp_type_da_act_lmt_core1:
1403 case ixgbe_sfp_type_1g_sx_core0:
1404 case ixgbe_sfp_type_1g_sx_core1:
1405 case ixgbe_sfp_type_1g_lx_core0:
1406 case ixgbe_sfp_type_1g_lx_core1:
1407 *linear = false;
1408 break;
1409 case ixgbe_sfp_type_unknown:
1410 case ixgbe_sfp_type_1g_cu_core0:
1411 case ixgbe_sfp_type_1g_cu_core1:
1412 default:
1413 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1414 }
1415
1416 return 0;
1417}
1418
1419/**
1420 * ixgbe_setup_mac_link_sfp_x550em - Configure the KR PHY for SFP.
1421 * @hw: pointer to hardware structure
1422 *
1423 * Configures the extern PHY and the integrated KR PHY for SFP support.
1424 */
1425static s32
1426ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw,
1427 ixgbe_link_speed speed,
1428 __always_unused bool autoneg_wait_to_complete)
1429{
1430 s32 status;
1431 u16 reg_slice, reg_val;
1432 bool setup_linear = false;
1433
1434 /* Check if SFP module is supported and linear */
1435 status = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1436
1437 /* If no SFP module present, then return success. Return success since
1438 * there is no reason to configure CS4227 and SFP not present error is
1439 * not accepted in the setup MAC link flow.
1440 */
1441 if (status == IXGBE_ERR_SFP_NOT_PRESENT)
1442 return 0;
1443
1444 if (status)
1445 return status;
1446
1447 /* Configure internal PHY for KR/KX. */
1448 ixgbe_setup_kr_speed_x550em(hw, speed);
1449
1450 /* Configure CS4227 LINE side to proper mode. */
1451 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12);
1452 if (setup_linear)
1453 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1;
1454 else
1455 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1;
1456
1457 status = hw->link.ops.write_link(hw, hw->link.addr, reg_slice,
1458 reg_val);
1459
1460 return status;
1461}
1462
1463/**
1464 * ixgbe_setup_sfi_x550a - Configure the internal PHY for native SFI mode
1465 * @hw: pointer to hardware structure
1466 * @speed: the link speed to force
1467 *
1468 * Configures the integrated PHY for native SFI mode. Used to connect the
1469 * internal PHY directly to an SFP cage, without autonegotiation.
1470 **/
1471static s32 ixgbe_setup_sfi_x550a(struct ixgbe_hw *hw, ixgbe_link_speed *speed)
1472{
1473 struct ixgbe_mac_info *mac = &hw->mac;
1474 s32 status;
1475 u32 reg_val;
1476
1477 /* Disable all AN and force speed to 10G Serial. */
1478 status = mac->ops.read_iosf_sb_reg(hw,
1479 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1480 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
1481 if (status)
1482 return status;
1483
1484 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1485 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1486 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1487 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1488
1489 /* Select forced link speed for internal PHY. */
1490 switch (*speed) {
1491 case IXGBE_LINK_SPEED_10GB_FULL:
1492 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G;
1493 break;
1494 case IXGBE_LINK_SPEED_1GB_FULL:
1495 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1496 break;
1497 default:
1498 /* Other link speeds are not supported by internal PHY. */
1499 return IXGBE_ERR_LINK_SETUP;
1500 }
1501
1502 status = mac->ops.write_iosf_sb_reg(hw,
1503 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1504 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
1505
1506 /* Toggle port SW reset by AN reset. */
1507 status = ixgbe_restart_an_internal_phy_x550em(hw);
1508
1509 return status;
1510}
1511
1512/**
1513 * ixgbe_setup_mac_link_sfp_n - Setup internal PHY for native SFP
1514 * @hw: pointer to hardware structure
1515 *
1516 * Configure the the integrated PHY for native SFP support.
1517 */
1518static s32
1519ixgbe_setup_mac_link_sfp_n(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1520 __always_unused bool autoneg_wait_to_complete)
1521{
1522 bool setup_linear = false;
1523 u32 reg_phy_int;
1524 s32 ret_val;
1525
1526 /* Check if SFP module is supported and linear */
1527 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1528
1529 /* If no SFP module present, then return success. Return success since
1530 * SFP not present error is not excepted in the setup MAC link flow.
1531 */
1532 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1533 return 0;
1534
1535 if (!ret_val)
1536 return ret_val;
1537
1538 /* Configure internal PHY for native SFI based on module type */
1539 ret_val = hw->mac.ops.read_iosf_sb_reg(hw,
1540 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1541 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_phy_int);
1542 if (!ret_val)
1543 return ret_val;
1544
1545 reg_phy_int &= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA;
1546 if (!setup_linear)
1547 reg_phy_int |= IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR;
1548
1549 ret_val = hw->mac.ops.write_iosf_sb_reg(hw,
1550 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1551 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_phy_int);
1552 if (!ret_val)
1553 return ret_val;
1554
1555 /* Setup SFI internal link. */
1556 return ixgbe_setup_sfi_x550a(hw, &speed);
1557}
1558
1559/**
1560 * ixgbe_setup_mac_link_sfp_x550a - Setup internal PHY for SFP
1561 * @hw: pointer to hardware structure
1562 *
1563 * Configure the the integrated PHY for SFP support.
1564 */
1565static s32
1566ixgbe_setup_mac_link_sfp_x550a(struct ixgbe_hw *hw, ixgbe_link_speed speed,
1567 __always_unused bool autoneg_wait_to_complete)
1568{
1569 u32 reg_slice, slice_offset;
1570 bool setup_linear = false;
1571 u16 reg_phy_ext;
1572 s32 ret_val;
1573
1574 /* Check if SFP module is supported and linear */
1575 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear);
1576
1577 /* If no SFP module present, then return success. Return success since
1578 * SFP not present error is not excepted in the setup MAC link flow.
1579 */
1580 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT)
1581 return 0;
1582
1583 if (!ret_val)
1584 return ret_val;
1585
1586 /* Configure internal PHY for KR/KX. */
1587 ixgbe_setup_kr_speed_x550em(hw, speed);
1588
1589 if (hw->phy.mdio.prtad == MDIO_PRTAD_NONE)
1590 return IXGBE_ERR_PHY_ADDR_INVALID;
1591
1592 /* Get external PHY device id */
1593 ret_val = hw->phy.ops.read_reg(hw, IXGBE_CS4227_GLOBAL_ID_MSB,
1594 IXGBE_MDIO_ZERO_DEV_TYPE, ®_phy_ext);
1595 if (ret_val)
1596 return ret_val;
1597
1598 /* When configuring quad port CS4223, the MAC instance is part
1599 * of the slice offset.
1600 */
1601 if (reg_phy_ext == IXGBE_CS4223_PHY_ID)
1602 slice_offset = (hw->bus.lan_id +
1603 (hw->bus.instance_id << 1)) << 12;
1604 else
1605 slice_offset = hw->bus.lan_id << 12;
1606
1607 /* Configure CS4227/CS4223 LINE side to proper mode. */
1608 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + slice_offset;
1609 if (setup_linear)
1610 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 1;
1611 else
1612 reg_phy_ext = (IXGBE_CS4227_EDC_MODE_SR << 1) | 1;
1613 return hw->phy.ops.write_reg(hw, reg_slice, IXGBE_MDIO_ZERO_DEV_TYPE,
1614 reg_phy_ext);
1615}
1616
1617/**
1618 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed
1619 * @hw: pointer to hardware structure
1620 * @speed: new link speed
1621 * @autoneg_wait_to_complete: true when waiting for completion is needed
1622 *
1623 * Setup internal/external PHY link speed based on link speed, then set
1624 * external PHY auto advertised link speed.
1625 *
1626 * Returns error status for any failure
1627 **/
1628static s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw,
1629 ixgbe_link_speed speed,
1630 bool autoneg_wait)
1631{
1632 s32 status;
1633 ixgbe_link_speed force_speed;
1634
1635 /* Setup internal/external PHY link speed to iXFI (10G), unless
1636 * only 1G is auto advertised then setup KX link.
1637 */
1638 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
1639 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
1640 else
1641 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
1642
1643 /* If internal link mode is XFI, then setup XFI internal link. */
1644 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) {
1645 status = ixgbe_setup_ixfi_x550em(hw, &force_speed);
1646
1647 if (status)
1648 return status;
1649 }
1650
1651 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);
1652}
1653
1654/** ixgbe_check_link_t_X550em - Determine link and speed status
1655 * @hw: pointer to hardware structure
1656 * @speed: pointer to link speed
1657 * @link_up: true when link is up
1658 * @link_up_wait_to_complete: bool used to wait for link up or not
1659 *
1660 * Check that both the MAC and X557 external PHY have link.
1661 **/
1662static s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw,
1663 ixgbe_link_speed *speed,
1664 bool *link_up,
1665 bool link_up_wait_to_complete)
1666{
1667 u32 status;
1668 u16 i, autoneg_status;
1669
1670 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
1671 return IXGBE_ERR_CONFIG;
1672
1673 status = ixgbe_check_mac_link_generic(hw, speed, link_up,
1674 link_up_wait_to_complete);
1675
1676 /* If check link fails or MAC link is not up, then return */
1677 if (status || !(*link_up))
1678 return status;
1679
1680 /* MAC link is up, so check external PHY link.
1681 * Link status is latching low, and can only be used to detect link
1682 * drop, and not the current status of the link without performing
1683 * back-to-back reads.
1684 */
1685 for (i = 0; i < 2; i++) {
1686 status = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
1687 &autoneg_status);
1688
1689 if (status)
1690 return status;
1691 }
1692
1693 /* If external PHY link is not up, then indicate link not up */
1694 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS))
1695 *link_up = false;
1696
1697 return 0;
1698}
1699
1700/**
1701 * ixgbe_setup_sgmii - Set up link for sgmii
1702 * @hw: pointer to hardware structure
1703 */
1704static s32
1705ixgbe_setup_sgmii(struct ixgbe_hw *hw, __always_unused ixgbe_link_speed speed,
1706 __always_unused bool autoneg_wait_to_complete)
1707{
1708 struct ixgbe_mac_info *mac = &hw->mac;
1709 u32 lval, sval, flx_val;
1710 s32 rc;
1711
1712 rc = mac->ops.read_iosf_sb_reg(hw,
1713 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1714 IXGBE_SB_IOSF_TARGET_KR_PHY, &lval);
1715 if (rc)
1716 return rc;
1717
1718 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
1719 lval &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK;
1720 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN;
1721 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN;
1722 lval |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G;
1723 rc = mac->ops.write_iosf_sb_reg(hw,
1724 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
1725 IXGBE_SB_IOSF_TARGET_KR_PHY, lval);
1726 if (rc)
1727 return rc;
1728
1729 rc = mac->ops.read_iosf_sb_reg(hw,
1730 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1731 IXGBE_SB_IOSF_TARGET_KR_PHY, &sval);
1732 if (rc)
1733 return rc;
1734
1735 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D;
1736 sval |= IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D;
1737 rc = mac->ops.write_iosf_sb_reg(hw,
1738 IXGBE_KRM_SGMII_CTRL(hw->bus.lan_id),
1739 IXGBE_SB_IOSF_TARGET_KR_PHY, sval);
1740 if (rc)
1741 return rc;
1742
1743 rc = mac->ops.read_iosf_sb_reg(hw,
1744 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1745 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1746 if (rc)
1747 return rc;
1748
1749 rc = mac->ops.read_iosf_sb_reg(hw,
1750 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1751 IXGBE_SB_IOSF_TARGET_KR_PHY, &flx_val);
1752 if (rc)
1753 return rc;
1754
1755 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
1756 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G;
1757 flx_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
1758 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
1759 flx_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
1760
1761 rc = mac->ops.write_iosf_sb_reg(hw,
1762 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
1763 IXGBE_SB_IOSF_TARGET_KR_PHY, flx_val);
1764 if (rc)
1765 return rc;
1766
1767 rc = ixgbe_restart_an_internal_phy_x550em(hw);
1768 return rc;
1769}
1770
1771/** ixgbe_init_mac_link_ops_X550em_a - Init mac link function pointers
1772 * @hw: pointer to hardware structure
1773 **/
1774static void ixgbe_init_mac_link_ops_X550em_a(struct ixgbe_hw *hw)
1775{
1776 struct ixgbe_mac_info *mac = &hw->mac;
1777
1778 switch (mac->ops.get_media_type(hw)) {
1779 case ixgbe_media_type_fiber:
1780 mac->ops.setup_fc = NULL;
1781 mac->ops.fc_autoneg = ixgbe_fc_autoneg_fiber_x550em_a;
1782 break;
1783 case ixgbe_media_type_backplane:
1784 mac->ops.fc_autoneg = ixgbe_fc_autoneg_backplane_x550em_a;
1785 mac->ops.setup_fc = ixgbe_setup_fc_backplane_x550em_a;
1786 break;
1787 default:
1788 break;
1789 }
1790}
1791
1792/** ixgbe_init_mac_link_ops_X550em - init mac link function pointers
1793 * @hw: pointer to hardware structure
1794 **/
1795static void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw)
1796{
1797 struct ixgbe_mac_info *mac = &hw->mac;
1798
1799 mac->ops.setup_fc = ixgbe_setup_fc_x550em;
1800
1801 switch (mac->ops.get_media_type(hw)) {
1802 case ixgbe_media_type_fiber:
1803 /* CS4227 does not support autoneg, so disable the laser control
1804 * functions for SFP+ fiber
1805 */
1806 mac->ops.disable_tx_laser = NULL;
1807 mac->ops.enable_tx_laser = NULL;
1808 mac->ops.flap_tx_laser = NULL;
1809 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber;
1810 switch (hw->device_id) {
1811 case IXGBE_DEV_ID_X550EM_A_SFP_N:
1812 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_n;
1813 break;
1814 case IXGBE_DEV_ID_X550EM_A_SFP:
1815 mac->ops.setup_mac_link =
1816 ixgbe_setup_mac_link_sfp_x550a;
1817 break;
1818 default:
1819 mac->ops.setup_mac_link =
1820 ixgbe_setup_mac_link_sfp_x550em;
1821 break;
1822 }
1823 mac->ops.set_rate_select_speed =
1824 ixgbe_set_soft_rate_select_speed;
1825 break;
1826 case ixgbe_media_type_copper:
1827 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em;
1828 mac->ops.setup_fc = ixgbe_setup_fc_generic;
1829 mac->ops.check_link = ixgbe_check_link_t_X550em;
1830 return;
1831 case ixgbe_media_type_backplane:
1832 if (hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII ||
1833 hw->device_id == IXGBE_DEV_ID_X550EM_A_SGMII_L)
1834 mac->ops.setup_link = ixgbe_setup_sgmii;
1835 break;
1836 default:
1837 break;
1838 }
1839
1840 /* Additional modification for X550em_a devices */
1841 if (hw->mac.type == ixgbe_mac_x550em_a)
1842 ixgbe_init_mac_link_ops_X550em_a(hw);
1843}
1844
1845/** ixgbe_setup_sfp_modules_X550em - Setup SFP module
1846 * @hw: pointer to hardware structure
1847 */
1848static s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw)
1849{
1850 s32 status;
1851 bool linear;
1852
1853 /* Check if SFP module is supported */
1854 status = ixgbe_supported_sfp_modules_X550em(hw, &linear);
1855 if (status)
1856 return status;
1857
1858 ixgbe_init_mac_link_ops_X550em(hw);
1859 hw->phy.ops.reset = NULL;
1860
1861 return 0;
1862}
1863
1864/** ixgbe_get_link_capabilities_x550em - Determines link capabilities
1865 * @hw: pointer to hardware structure
1866 * @speed: pointer to link speed
1867 * @autoneg: true when autoneg or autotry is enabled
1868 **/
1869static s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw,
1870 ixgbe_link_speed *speed,
1871 bool *autoneg)
1872{
1873 /* SFP */
1874 if (hw->phy.media_type == ixgbe_media_type_fiber) {
1875 /* CS4227 SFP must not enable auto-negotiation */
1876 *autoneg = false;
1877
1878 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1879 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
1880 *speed = IXGBE_LINK_SPEED_1GB_FULL;
1881 return 0;
1882 }
1883
1884 /* Link capabilities are based on SFP */
1885 if (hw->phy.multispeed_fiber)
1886 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1887 IXGBE_LINK_SPEED_1GB_FULL;
1888 else
1889 *speed = IXGBE_LINK_SPEED_10GB_FULL;
1890 } else {
1891 *speed = IXGBE_LINK_SPEED_10GB_FULL |
1892 IXGBE_LINK_SPEED_1GB_FULL;
1893 *autoneg = true;
1894 }
1895 return 0;
1896}
1897
1898/**
1899 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause
1900 * @hw: pointer to hardware structure
1901 * @lsc: pointer to boolean flag which indicates whether external Base T
1902 * PHY interrupt is lsc
1903 *
1904 * Determime if external Base T PHY interrupt cause is high temperature
1905 * failure alarm or link status change.
1906 *
1907 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
1908 * failure alarm, else return PHY access status.
1909 **/
1910static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc)
1911{
1912 u32 status;
1913 u16 reg;
1914
1915 *lsc = false;
1916
1917 /* Vendor alarm triggered */
1918 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1919 MDIO_MMD_VEND1,
1920 ®);
1921
1922 if (status || !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN))
1923 return status;
1924
1925 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */
1926 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG,
1927 MDIO_MMD_VEND1,
1928 ®);
1929
1930 if (status || !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
1931 IXGBE_MDIO_GLOBAL_ALARM_1_INT)))
1932 return status;
1933
1934 /* Global alarm triggered */
1935 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1,
1936 MDIO_MMD_VEND1,
1937 ®);
1938
1939 if (status)
1940 return status;
1941
1942 /* If high temperature failure, then return over temp error and exit */
1943 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) {
1944 /* power down the PHY in case the PHY FW didn't already */
1945 ixgbe_set_copper_phy_power(hw, false);
1946 return IXGBE_ERR_OVERTEMP;
1947 }
1948 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT) {
1949 /* device fault alarm triggered */
1950 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_FAULT_MSG,
1951 MDIO_MMD_VEND1,
1952 ®);
1953 if (status)
1954 return status;
1955
1956 /* if device fault was due to high temp alarm handle and exit */
1957 if (reg == IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP) {
1958 /* power down the PHY in case the PHY FW didn't */
1959 ixgbe_set_copper_phy_power(hw, false);
1960 return IXGBE_ERR_OVERTEMP;
1961 }
1962 }
1963
1964 /* Vendor alarm 2 triggered */
1965 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG,
1966 MDIO_MMD_AN, ®);
1967
1968 if (status || !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT))
1969 return status;
1970
1971 /* link connect/disconnect event occurred */
1972 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2,
1973 MDIO_MMD_AN, ®);
1974
1975 if (status)
1976 return status;
1977
1978 /* Indicate LSC */
1979 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC)
1980 *lsc = true;
1981
1982 return 0;
1983}
1984
1985/**
1986 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts
1987 * @hw: pointer to hardware structure
1988 *
1989 * Enable link status change and temperature failure alarm for the external
1990 * Base T PHY
1991 *
1992 * Returns PHY access status
1993 **/
1994static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw)
1995{
1996 u32 status;
1997 u16 reg;
1998 bool lsc;
1999
2000 /* Clear interrupt flags */
2001 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2002
2003 /* Enable link status change alarm */
2004 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2005 MDIO_MMD_AN, ®);
2006 if (status)
2007 return status;
2008
2009 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN;
2010
2011 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK,
2012 MDIO_MMD_AN, reg);
2013 if (status)
2014 return status;
2015
2016 /* Enable high temperature failure and global fault alarms */
2017 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2018 MDIO_MMD_VEND1,
2019 ®);
2020 if (status)
2021 return status;
2022
2023 reg |= (IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN |
2024 IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN);
2025
2026 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK,
2027 MDIO_MMD_VEND1,
2028 reg);
2029 if (status)
2030 return status;
2031
2032 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */
2033 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2034 MDIO_MMD_VEND1,
2035 ®);
2036 if (status)
2037 return status;
2038
2039 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN |
2040 IXGBE_MDIO_GLOBAL_ALARM_1_INT);
2041
2042 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK,
2043 MDIO_MMD_VEND1,
2044 reg);
2045 if (status)
2046 return status;
2047
2048 /* Enable chip-wide vendor alarm */
2049 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2050 MDIO_MMD_VEND1,
2051 ®);
2052 if (status)
2053 return status;
2054
2055 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN;
2056
2057 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK,
2058 MDIO_MMD_VEND1,
2059 reg);
2060
2061 return status;
2062}
2063
2064/**
2065 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt
2066 * @hw: pointer to hardware structure
2067 *
2068 * Handle external Base T PHY interrupt. If high temperature
2069 * failure alarm then return error, else if link status change
2070 * then setup internal/external PHY link
2071 *
2072 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature
2073 * failure alarm, else return PHY access status.
2074 **/
2075static s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw)
2076{
2077 struct ixgbe_phy_info *phy = &hw->phy;
2078 bool lsc;
2079 u32 status;
2080
2081 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc);
2082 if (status)
2083 return status;
2084
2085 if (lsc && phy->ops.setup_internal_link)
2086 return phy->ops.setup_internal_link(hw);
2087
2088 return 0;
2089}
2090
2091/**
2092 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed.
2093 * @hw: pointer to hardware structure
2094 * @speed: link speed
2095 *
2096 * Configures the integrated KR PHY.
2097 **/
2098static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw,
2099 ixgbe_link_speed speed)
2100{
2101 s32 status;
2102 u32 reg_val;
2103
2104 status = hw->mac.ops.read_iosf_sb_reg(hw,
2105 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2106 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2107 if (status)
2108 return status;
2109
2110 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE;
2111 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ |
2112 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC);
2113 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR |
2114 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX);
2115
2116 /* Advertise 10G support. */
2117 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
2118 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR;
2119
2120 /* Advertise 1G support. */
2121 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
2122 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX;
2123
2124 status = hw->mac.ops.write_iosf_sb_reg(hw,
2125 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id),
2126 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2127
2128 if (hw->mac.type == ixgbe_mac_x550em_a) {
2129 /* Set lane mode to KR auto negotiation */
2130 status = hw->mac.ops.read_iosf_sb_reg(hw,
2131 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2132 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val);
2133
2134 if (status)
2135 return status;
2136
2137 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK;
2138 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN;
2139 reg_val |= IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN;
2140 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN;
2141 reg_val &= ~IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN;
2142
2143 status = hw->mac.ops.write_iosf_sb_reg(hw,
2144 IXGBE_KRM_PMD_FLX_MASK_ST20(hw->bus.lan_id),
2145 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val);
2146 }
2147
2148 return ixgbe_restart_an_internal_phy_x550em(hw);
2149}
2150
2151/** ixgbe_setup_kx4_x550em - Configure the KX4 PHY.
2152 * @hw: pointer to hardware structure
2153 *
2154 * Configures the integrated KX4 PHY.
2155 **/
2156static s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw)
2157{
2158 s32 status;
2159 u32 reg_val;
2160
2161 status = hw->mac.ops.read_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
2162 IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
2163 hw->bus.lan_id, ®_val);
2164 if (status)
2165 return status;
2166
2167 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 |
2168 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX);
2169
2170 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE;
2171
2172 /* Advertise 10G support. */
2173 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
2174 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4;
2175
2176 /* Advertise 1G support. */
2177 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
2178 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX;
2179
2180 /* Restart auto-negotiation. */
2181 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART;
2182 status = hw->mac.ops.write_iosf_sb_reg(hw, IXGBE_KX4_LINK_CNTL_1,
2183 IXGBE_SB_IOSF_TARGET_KX4_PCS0 +
2184 hw->bus.lan_id, reg_val);
2185
2186 return status;
2187}
2188
2189/**
2190 * ixgbe_setup_kr_x550em - Configure the KR PHY
2191 * @hw: pointer to hardware structure
2192 *
2193 * Configures the integrated KR PHY for X550EM_x.
2194 **/
2195static s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw)
2196{
2197 if (hw->mac.type != ixgbe_mac_X550EM_x)
2198 return 0;
2199
2200 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised);
2201}
2202
2203/** ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status
2204 * @hw: address of hardware structure
2205 * @link_up: address of boolean to indicate link status
2206 *
2207 * Returns error code if unable to get link status.
2208 **/
2209static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up)
2210{
2211 u32 ret;
2212 u16 autoneg_status;
2213
2214 *link_up = false;
2215
2216 /* read this twice back to back to indicate current status */
2217 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2218 &autoneg_status);
2219 if (ret)
2220 return ret;
2221
2222 ret = hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN,
2223 &autoneg_status);
2224 if (ret)
2225 return ret;
2226
2227 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS);
2228
2229 return 0;
2230}
2231
2232/** ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link
2233 * @hw: point to hardware structure
2234 *
2235 * Configures the link between the integrated KR PHY and the external X557 PHY
2236 * The driver will call this function when it gets a link status change
2237 * interrupt from the X557 PHY. This function configures the link speed
2238 * between the PHYs to match the link speed of the BASE-T link.
2239 *
2240 * A return of a non-zero value indicates an error, and the base driver should
2241 * not report link up.
2242 **/
2243static s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw)
2244{
2245 ixgbe_link_speed force_speed;
2246 bool link_up;
2247 u32 status;
2248 u16 speed;
2249
2250 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper)
2251 return IXGBE_ERR_CONFIG;
2252
2253 if (hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) {
2254 speed = IXGBE_LINK_SPEED_10GB_FULL |
2255 IXGBE_LINK_SPEED_1GB_FULL;
2256 return ixgbe_setup_kr_speed_x550em(hw, speed);
2257 }
2258
2259 /* If link is not up, then there is no setup necessary so return */
2260 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2261 if (status)
2262 return status;
2263
2264 if (!link_up)
2265 return 0;
2266
2267 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2268 MDIO_MMD_AN,
2269 &speed);
2270 if (status)
2271 return status;
2272
2273 /* If link is not still up, then no setup is necessary so return */
2274 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2275 if (status)
2276 return status;
2277
2278 if (!link_up)
2279 return 0;
2280
2281 /* clear everything but the speed and duplex bits */
2282 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK;
2283
2284 switch (speed) {
2285 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL:
2286 force_speed = IXGBE_LINK_SPEED_10GB_FULL;
2287 break;
2288 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL:
2289 force_speed = IXGBE_LINK_SPEED_1GB_FULL;
2290 break;
2291 default:
2292 /* Internal PHY does not support anything else */
2293 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2294 }
2295
2296 return ixgbe_setup_ixfi_x550em(hw, &force_speed);
2297}
2298
2299/** ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI
2300 * @hw: pointer to hardware structure
2301 **/
2302static s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw)
2303{
2304 s32 status;
2305
2306 status = ixgbe_reset_phy_generic(hw);
2307
2308 if (status)
2309 return status;
2310
2311 /* Configure Link Status Alarm and Temperature Threshold interrupts */
2312 return ixgbe_enable_lasi_ext_t_x550em(hw);
2313}
2314
2315/**
2316 * ixgbe_led_on_t_x550em - Turns on the software controllable LEDs.
2317 * @hw: pointer to hardware structure
2318 * @led_idx: led number to turn on
2319 **/
2320static s32 ixgbe_led_on_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2321{
2322 u16 phy_data;
2323
2324 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2325 return IXGBE_ERR_PARAM;
2326
2327 /* To turn on the LED, set mode to ON. */
2328 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2329 MDIO_MMD_VEND1, &phy_data);
2330 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK;
2331 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2332 MDIO_MMD_VEND1, phy_data);
2333
2334 return 0;
2335}
2336
2337/**
2338 * ixgbe_led_off_t_x550em - Turns off the software controllable LEDs.
2339 * @hw: pointer to hardware structure
2340 * @led_idx: led number to turn off
2341 **/
2342static s32 ixgbe_led_off_t_x550em(struct ixgbe_hw *hw, u32 led_idx)
2343{
2344 u16 phy_data;
2345
2346 if (led_idx >= IXGBE_X557_MAX_LED_INDEX)
2347 return IXGBE_ERR_PARAM;
2348
2349 /* To turn on the LED, set mode to ON. */
2350 hw->phy.ops.read_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2351 MDIO_MMD_VEND1, &phy_data);
2352 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK;
2353 hw->phy.ops.write_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx,
2354 MDIO_MMD_VEND1, phy_data);
2355
2356 return 0;
2357}
2358
2359/** ixgbe_get_lcd_x550em - Determine lowest common denominator
2360 * @hw: pointer to hardware structure
2361 * @lcd_speed: pointer to lowest common link speed
2362 *
2363 * Determine lowest common link speed with link partner.
2364 **/
2365static s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw,
2366 ixgbe_link_speed *lcd_speed)
2367{
2368 u16 an_lp_status;
2369 s32 status;
2370 u16 word = hw->eeprom.ctrl_word_3;
2371
2372 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN;
2373
2374 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS,
2375 MDIO_MMD_AN,
2376 &an_lp_status);
2377 if (status)
2378 return status;
2379
2380 /* If link partner advertised 1G, return 1G */
2381 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) {
2382 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL;
2383 return status;
2384 }
2385
2386 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */
2387 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) ||
2388 (word & NVM_INIT_CTRL_3_D10GMP_PORT0))
2389 return status;
2390
2391 /* Link partner not capable of lower speeds, return 10G */
2392 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL;
2393 return status;
2394}
2395
2396/**
2397 * ixgbe_setup_fc_x550em - Set up flow control
2398 * @hw: pointer to hardware structure
2399 */
2400static s32 ixgbe_setup_fc_x550em(struct ixgbe_hw *hw)
2401{
2402 bool pause, asm_dir;
2403 u32 reg_val;
2404 s32 rc;
2405
2406 /* Validate the requested mode */
2407 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
2408 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
2409 return IXGBE_ERR_INVALID_LINK_SETTINGS;
2410 }
2411
2412 /* 10gig parts do not have a word in the EEPROM to determine the
2413 * default flow control setting, so we explicitly set it to full.
2414 */
2415 if (hw->fc.requested_mode == ixgbe_fc_default)
2416 hw->fc.requested_mode = ixgbe_fc_full;
2417
2418 /* Determine PAUSE and ASM_DIR bits. */
2419 switch (hw->fc.requested_mode) {
2420 case ixgbe_fc_none:
2421 pause = false;
2422 asm_dir = false;
2423 break;
2424 case ixgbe_fc_tx_pause:
2425 pause = false;
2426 asm_dir = true;
2427 break;
2428 case ixgbe_fc_rx_pause:
2429 /* Rx Flow control is enabled and Tx Flow control is
2430 * disabled by software override. Since there really
2431 * isn't a way to advertise that we are capable of RX
2432 * Pause ONLY, we will advertise that we support both
2433 * symmetric and asymmetric Rx PAUSE, as such we fall
2434 * through to the fc_full statement. Later, we will
2435 * disable the adapter's ability to send PAUSE frames.
2436 */
2437 /* Fallthrough */
2438 case ixgbe_fc_full:
2439 pause = true;
2440 asm_dir = true;
2441 break;
2442 default:
2443 hw_err(hw, "Flow control param set incorrectly\n");
2444 return IXGBE_ERR_CONFIG;
2445 }
2446
2447 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR &&
2448 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR &&
2449 hw->device_id != IXGBE_DEV_ID_X550EM_A_KR_L)
2450 return 0;
2451
2452 rc = hw->mac.ops.read_iosf_sb_reg(hw,
2453 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2454 IXGBE_SB_IOSF_TARGET_KR_PHY,
2455 ®_val);
2456 if (rc)
2457 return rc;
2458
2459 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
2460 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
2461 if (pause)
2462 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
2463 if (asm_dir)
2464 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
2465 rc = hw->mac.ops.write_iosf_sb_reg(hw,
2466 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2467 IXGBE_SB_IOSF_TARGET_KR_PHY,
2468 reg_val);
2469
2470 /* This device does not fully support AN. */
2471 hw->fc.disable_fc_autoneg = true;
2472
2473 return rc;
2474}
2475
2476/**
2477 * ixgbe_fc_autoneg_backplane_x550em_a - Enable flow control IEEE clause 37
2478 * @hw: pointer to hardware structure
2479 **/
2480static void ixgbe_fc_autoneg_backplane_x550em_a(struct ixgbe_hw *hw)
2481{
2482 u32 link_s1, lp_an_page_low, an_cntl_1;
2483 s32 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2484 ixgbe_link_speed speed;
2485 bool link_up;
2486
2487 /* AN should have completed when the cable was plugged in.
2488 * Look for reasons to bail out. Bail out if:
2489 * - FC autoneg is disabled, or if
2490 * - link is not up.
2491 */
2492 if (hw->fc.disable_fc_autoneg) {
2493 hw_err(hw, "Flow control autoneg is disabled");
2494 goto out;
2495 }
2496
2497 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2498 if (!link_up) {
2499 hw_err(hw, "The link is down");
2500 goto out;
2501 }
2502
2503 /* Check at auto-negotiation has completed */
2504 status = hw->mac.ops.read_iosf_sb_reg(hw,
2505 IXGBE_KRM_LINK_S1(hw->bus.lan_id),
2506 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_s1);
2507
2508 if (status || (link_s1 & IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE) == 0) {
2509 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2510 status = IXGBE_ERR_FC_NOT_NEGOTIATED;
2511 goto out;
2512 }
2513
2514 /* Read the 10g AN autoc and LP ability registers and resolve
2515 * local flow control settings accordingly
2516 */
2517 status = hw->mac.ops.read_iosf_sb_reg(hw,
2518 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
2519 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl_1);
2520
2521 if (status) {
2522 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2523 goto out;
2524 }
2525
2526 status = hw->mac.ops.read_iosf_sb_reg(hw,
2527 IXGBE_KRM_LP_BASE_PAGE_HIGH(hw->bus.lan_id),
2528 IXGBE_SB_IOSF_TARGET_KR_PHY, &lp_an_page_low);
2529
2530 if (status) {
2531 hw_dbg(hw, "Auto-Negotiation did not complete\n");
2532 goto out;
2533 }
2534
2535 status = ixgbe_negotiate_fc(hw, an_cntl_1, lp_an_page_low,
2536 IXGBE_KRM_AN_CNTL_1_SYM_PAUSE,
2537 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE,
2538 IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE,
2539 IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE);
2540
2541out:
2542 if (!status) {
2543 hw->fc.fc_was_autonegged = true;
2544 } else {
2545 hw->fc.fc_was_autonegged = false;
2546 hw->fc.current_mode = hw->fc.requested_mode;
2547 }
2548}
2549
2550/**
2551 * ixgbe_fc_autoneg_fiber_x550em_a - passthrough FC settings
2552 * @hw: pointer to hardware structure
2553 **/
2554static void ixgbe_fc_autoneg_fiber_x550em_a(struct ixgbe_hw *hw)
2555{
2556 hw->fc.fc_was_autonegged = false;
2557 hw->fc.current_mode = hw->fc.requested_mode;
2558}
2559
2560/** ixgbe_enter_lplu_x550em - Transition to low power states
2561 * @hw: pointer to hardware structure
2562 *
2563 * Configures Low Power Link Up on transition to low power states
2564 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting
2565 * the X557 PHY immediately prior to entering LPLU.
2566 **/
2567static s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw)
2568{
2569 u16 an_10g_cntl_reg, autoneg_reg, speed;
2570 s32 status;
2571 ixgbe_link_speed lcd_speed;
2572 u32 save_autoneg;
2573 bool link_up;
2574
2575 /* If blocked by MNG FW, then don't restart AN */
2576 if (ixgbe_check_reset_blocked(hw))
2577 return 0;
2578
2579 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2580 if (status)
2581 return status;
2582
2583 status = hw->eeprom.ops.read(hw, NVM_INIT_CTRL_3,
2584 &hw->eeprom.ctrl_word_3);
2585 if (status)
2586 return status;
2587
2588 /* If link is down, LPLU disabled in NVM, WoL disabled, or
2589 * manageability disabled, then force link down by entering
2590 * low power mode.
2591 */
2592 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) ||
2593 !(hw->wol_enabled || ixgbe_mng_present(hw)))
2594 return ixgbe_set_copper_phy_power(hw, false);
2595
2596 /* Determine LCD */
2597 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed);
2598 if (status)
2599 return status;
2600
2601 /* If no valid LCD link speed, then force link down and exit. */
2602 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN)
2603 return ixgbe_set_copper_phy_power(hw, false);
2604
2605 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT,
2606 MDIO_MMD_AN,
2607 &speed);
2608 if (status)
2609 return status;
2610
2611 /* If no link now, speed is invalid so take link down */
2612 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up);
2613 if (status)
2614 return ixgbe_set_copper_phy_power(hw, false);
2615
2616 /* clear everything but the speed bits */
2617 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK;
2618
2619 /* If current speed is already LCD, then exit. */
2620 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) &&
2621 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) ||
2622 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) &&
2623 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL)))
2624 return status;
2625
2626 /* Clear AN completed indication */
2627 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM,
2628 MDIO_MMD_AN,
2629 &autoneg_reg);
2630 if (status)
2631 return status;
2632
2633 status = hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL,
2634 MDIO_MMD_AN,
2635 &an_10g_cntl_reg);
2636 if (status)
2637 return status;
2638
2639 status = hw->phy.ops.read_reg(hw,
2640 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
2641 MDIO_MMD_AN,
2642 &autoneg_reg);
2643 if (status)
2644 return status;
2645
2646 save_autoneg = hw->phy.autoneg_advertised;
2647
2648 /* Setup link at least common link speed */
2649 status = hw->mac.ops.setup_link(hw, lcd_speed, false);
2650
2651 /* restore autoneg from before setting lplu speed */
2652 hw->phy.autoneg_advertised = save_autoneg;
2653
2654 return status;
2655}
2656
2657/**
2658 * ixgbe_read_mng_if_sel_x550em - Read NW_MNG_IF_SEL register
2659 * @hw: pointer to hardware structure
2660 *
2661 * Read NW_MNG_IF_SEL register and save field values.
2662 */
2663static void ixgbe_read_mng_if_sel_x550em(struct ixgbe_hw *hw)
2664{
2665 /* Save NW management interface connected on board. This is used
2666 * to determine internal PHY mode.
2667 */
2668 hw->phy.nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2669
2670 /* If X552 (X550EM_a) and MDIO is connected to external PHY, then set
2671 * PHY address. This register field was has only been used for X552.
2672 */
2673 if (hw->mac.type == ixgbe_mac_x550em_a &&
2674 hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_MDIO_ACT) {
2675 hw->phy.mdio.prtad = (hw->phy.nw_mng_if_sel &
2676 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
2677 IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
2678 }
2679}
2680
2681/** ixgbe_init_phy_ops_X550em - PHY/SFP specific init
2682 * @hw: pointer to hardware structure
2683 *
2684 * Initialize any function pointers that were not able to be
2685 * set during init_shared_code because the PHY/SFP type was
2686 * not known. Perform the SFP init if necessary.
2687 **/
2688static s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw)
2689{
2690 struct ixgbe_phy_info *phy = &hw->phy;
2691 s32 ret_val;
2692
2693 hw->mac.ops.set_lan_id(hw);
2694
2695 ixgbe_read_mng_if_sel_x550em(hw);
2696
2697 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) {
2698 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM;
2699 ixgbe_setup_mux_ctl(hw);
2700 }
2701
2702 /* Identify the PHY or SFP module */
2703 ret_val = phy->ops.identify(hw);
2704
2705 /* Setup function pointers based on detected hardware */
2706 ixgbe_init_mac_link_ops_X550em(hw);
2707 if (phy->sfp_type != ixgbe_sfp_type_unknown)
2708 phy->ops.reset = NULL;
2709
2710 /* Set functions pointers based on phy type */
2711 switch (hw->phy.type) {
2712 case ixgbe_phy_x550em_kx4:
2713 phy->ops.setup_link = ixgbe_setup_kx4_x550em;
2714 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2715 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2716 break;
2717 case ixgbe_phy_x550em_kr:
2718 phy->ops.setup_link = ixgbe_setup_kr_x550em;
2719 phy->ops.read_reg = ixgbe_read_phy_reg_x550em;
2720 phy->ops.write_reg = ixgbe_write_phy_reg_x550em;
2721 break;
2722 case ixgbe_phy_x550em_ext_t:
2723 /* Save NW management interface connected on board. This is used
2724 * to determine internal PHY mode
2725 */
2726 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL);
2727
2728 /* If internal link mode is XFI, then setup iXFI internal link,
2729 * else setup KR now.
2730 */
2731 phy->ops.setup_internal_link =
2732 ixgbe_setup_internal_phy_t_x550em;
2733
2734 /* setup SW LPLU only for first revision */
2735 if (hw->mac.type == ixgbe_mac_X550EM_x &&
2736 !(IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)) &
2737 IXGBE_FUSES0_REV_MASK))
2738 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em;
2739
2740 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em;
2741 phy->ops.reset = ixgbe_reset_phy_t_X550em;
2742 break;
2743 default:
2744 break;
2745 }
2746
2747 return ret_val;
2748}
2749
2750/** ixgbe_get_media_type_X550em - Get media type
2751 * @hw: pointer to hardware structure
2752 *
2753 * Returns the media type (fiber, copper, backplane)
2754 *
2755 */
2756static enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw)
2757{
2758 enum ixgbe_media_type media_type;
2759
2760 /* Detect if there is a copper PHY attached. */
2761 switch (hw->device_id) {
2762 case IXGBE_DEV_ID_X550EM_A_SGMII:
2763 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2764 hw->phy.type = ixgbe_phy_sgmii;
2765 /* Fallthrough */
2766 case IXGBE_DEV_ID_X550EM_X_KR:
2767 case IXGBE_DEV_ID_X550EM_X_KX4:
2768 case IXGBE_DEV_ID_X550EM_A_KR:
2769 case IXGBE_DEV_ID_X550EM_A_KR_L:
2770 media_type = ixgbe_media_type_backplane;
2771 break;
2772 case IXGBE_DEV_ID_X550EM_X_SFP:
2773 case IXGBE_DEV_ID_X550EM_A_SFP:
2774 case IXGBE_DEV_ID_X550EM_A_SFP_N:
2775 media_type = ixgbe_media_type_fiber;
2776 break;
2777 case IXGBE_DEV_ID_X550EM_X_1G_T:
2778 case IXGBE_DEV_ID_X550EM_X_10G_T:
2779 case IXGBE_DEV_ID_X550EM_A_10G_T:
2780 media_type = ixgbe_media_type_copper;
2781 break;
2782 default:
2783 media_type = ixgbe_media_type_unknown;
2784 break;
2785 }
2786 return media_type;
2787}
2788
2789/** ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY.
2790 ** @hw: pointer to hardware structure
2791 **/
2792static s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw)
2793{
2794 s32 status;
2795 u16 reg;
2796
2797 status = hw->phy.ops.read_reg(hw,
2798 IXGBE_MDIO_TX_VENDOR_ALARMS_3,
2799 MDIO_MMD_PMAPMD,
2800 ®);
2801 if (status)
2802 return status;
2803
2804 /* If PHY FW reset completed bit is set then this is the first
2805 * SW instance after a power on so the PHY FW must be un-stalled.
2806 */
2807 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
2808 status = hw->phy.ops.read_reg(hw,
2809 IXGBE_MDIO_GLOBAL_RES_PR_10,
2810 MDIO_MMD_VEND1,
2811 ®);
2812 if (status)
2813 return status;
2814
2815 reg &= ~IXGBE_MDIO_POWER_UP_STALL;
2816
2817 status = hw->phy.ops.write_reg(hw,
2818 IXGBE_MDIO_GLOBAL_RES_PR_10,
2819 MDIO_MMD_VEND1,
2820 reg);
2821 if (status)
2822 return status;
2823 }
2824
2825 return status;
2826}
2827
2828/**
2829 * ixgbe_set_mdio_speed - Set MDIO clock speed
2830 * @hw: pointer to hardware structure
2831 */
2832static void ixgbe_set_mdio_speed(struct ixgbe_hw *hw)
2833{
2834 u32 hlreg0;
2835
2836 switch (hw->device_id) {
2837 case IXGBE_DEV_ID_X550EM_X_10G_T:
2838 case IXGBE_DEV_ID_X550EM_A_SGMII:
2839 case IXGBE_DEV_ID_X550EM_A_SGMII_L:
2840 case IXGBE_DEV_ID_X550EM_A_10G_T:
2841 case IXGBE_DEV_ID_X550EM_A_SFP:
2842 /* Config MDIO clock speed before the first MDIO PHY access */
2843 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2844 hlreg0 &= ~IXGBE_HLREG0_MDCSPD;
2845 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2846 break;
2847 default:
2848 break;
2849 }
2850}
2851
2852/** ixgbe_reset_hw_X550em - Perform hardware reset
2853 ** @hw: pointer to hardware structure
2854 **
2855 ** Resets the hardware by resetting the transmit and receive units, masks
2856 ** and clears all interrupts, perform a PHY reset, and perform a link (MAC)
2857 ** reset.
2858 **/
2859static s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw)
2860{
2861 ixgbe_link_speed link_speed;
2862 s32 status;
2863 u32 ctrl = 0;
2864 u32 i;
2865 bool link_up = false;
2866
2867 /* Call adapter stop to disable Tx/Rx and clear interrupts */
2868 status = hw->mac.ops.stop_adapter(hw);
2869 if (status)
2870 return status;
2871
2872 /* flush pending Tx transactions */
2873 ixgbe_clear_tx_pending(hw);
2874
2875 /* PHY ops must be identified and initialized prior to reset */
2876
2877 /* Identify PHY and related function pointers */
2878 status = hw->phy.ops.init(hw);
2879
2880 /* start the external PHY */
2881 if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
2882 status = ixgbe_init_ext_t_x550em(hw);
2883 if (status)
2884 return status;
2885 }
2886
2887 /* Setup SFP module if there is one present. */
2888 if (hw->phy.sfp_setup_needed) {
2889 status = hw->mac.ops.setup_sfp(hw);
2890 hw->phy.sfp_setup_needed = false;
2891 }
2892
2893 /* Reset PHY */
2894 if (!hw->phy.reset_disable && hw->phy.ops.reset)
2895 hw->phy.ops.reset(hw);
2896
2897mac_reset_top:
2898 /* Issue global reset to the MAC. Needs to be SW reset if link is up.
2899 * If link reset is used when link is up, it might reset the PHY when
2900 * mng is using it. If link is down or the flag to force full link
2901 * reset is set, then perform link reset.
2902 */
2903 ctrl = IXGBE_CTRL_LNK_RST;
2904
2905 if (!hw->force_full_reset) {
2906 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
2907 if (link_up)
2908 ctrl = IXGBE_CTRL_RST;
2909 }
2910
2911 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
2912 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
2913 IXGBE_WRITE_FLUSH(hw);
2914 usleep_range(1000, 1200);
2915
2916 /* Poll for reset bit to self-clear meaning reset is complete */
2917 for (i = 0; i < 10; i++) {
2918 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
2919 if (!(ctrl & IXGBE_CTRL_RST_MASK))
2920 break;
2921 udelay(1);
2922 }
2923
2924 if (ctrl & IXGBE_CTRL_RST_MASK) {
2925 status = IXGBE_ERR_RESET_FAILED;
2926 hw_dbg(hw, "Reset polling failed to complete.\n");
2927 }
2928
2929 msleep(50);
2930
2931 /* Double resets are required for recovery from certain error
2932 * clear the multicast table. Also reset num_rar_entries to 128,
2933 * since we modify this value when programming the SAN MAC address.
2934 */
2935 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
2936 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
2937 goto mac_reset_top;
2938 }
2939
2940 /* Store the permanent mac address */
2941 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
2942
2943 /* Store MAC address from RAR0, clear receive address registers, and
2944 * clear the multicast table. Also reset num_rar_entries to 128,
2945 * since we modify this value when programming the SAN MAC address.
2946 */
2947 hw->mac.num_rar_entries = 128;
2948 hw->mac.ops.init_rx_addrs(hw);
2949
2950 ixgbe_set_mdio_speed(hw);
2951
2952 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP)
2953 ixgbe_setup_mux_ctl(hw);
2954
2955 return status;
2956}
2957
2958/** ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype
2959 * anti-spoofing
2960 * @hw: pointer to hardware structure
2961 * @enable: enable or disable switch for Ethertype anti-spoofing
2962 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing
2963 **/
2964static void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw,
2965 bool enable, int vf)
2966{
2967 int vf_target_reg = vf >> 3;
2968 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT;
2969 u32 pfvfspoof;
2970
2971 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
2972 if (enable)
2973 pfvfspoof |= BIT(vf_target_shift);
2974 else
2975 pfvfspoof &= ~BIT(vf_target_shift);
2976
2977 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
2978}
2979
2980/** ixgbe_set_source_address_pruning_X550 - Enable/Disbale src address pruning
2981 * @hw: pointer to hardware structure
2982 * @enable: enable or disable source address pruning
2983 * @pool: Rx pool to set source address pruning for
2984 **/
2985static void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw,
2986 bool enable,
2987 unsigned int pool)
2988{
2989 u64 pfflp;
2990
2991 /* max rx pool is 63 */
2992 if (pool > 63)
2993 return;
2994
2995 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL);
2996 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32;
2997
2998 if (enable)
2999 pfflp |= (1ULL << pool);
3000 else
3001 pfflp &= ~(1ULL << pool);
3002
3003 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp);
3004 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32));
3005}
3006
3007/**
3008 * ixgbe_setup_fc_backplane_x550em_a - Set up flow control
3009 * @hw: pointer to hardware structure
3010 *
3011 * Called at init time to set up flow control.
3012 **/
3013static s32 ixgbe_setup_fc_backplane_x550em_a(struct ixgbe_hw *hw)
3014{
3015 s32 status = 0;
3016 u32 an_cntl = 0;
3017
3018 /* Validate the requested mode */
3019 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
3020 hw_err(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
3021 return IXGBE_ERR_INVALID_LINK_SETTINGS;
3022 }
3023
3024 if (hw->fc.requested_mode == ixgbe_fc_default)
3025 hw->fc.requested_mode = ixgbe_fc_full;
3026
3027 /* Set up the 1G and 10G flow control advertisement registers so the
3028 * HW will be able to do FC autoneg once the cable is plugged in. If
3029 * we link at 10G, the 1G advertisement is harmless and vice versa.
3030 */
3031 status = hw->mac.ops.read_iosf_sb_reg(hw,
3032 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3033 IXGBE_SB_IOSF_TARGET_KR_PHY, &an_cntl);
3034
3035 if (status) {
3036 hw_dbg(hw, "Auto-Negotiation did not complete\n");
3037 return status;
3038 }
3039
3040 /* The possible values of fc.requested_mode are:
3041 * 0: Flow control is completely disabled
3042 * 1: Rx flow control is enabled (we can receive pause frames,
3043 * but not send pause frames).
3044 * 2: Tx flow control is enabled (we can send pause frames but
3045 * we do not support receiving pause frames).
3046 * 3: Both Rx and Tx flow control (symmetric) are enabled.
3047 * other: Invalid.
3048 */
3049 switch (hw->fc.requested_mode) {
3050 case ixgbe_fc_none:
3051 /* Flow control completely disabled by software override. */
3052 an_cntl &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3053 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE);
3054 break;
3055 case ixgbe_fc_tx_pause:
3056 /* Tx Flow control is enabled, and Rx Flow control is
3057 * disabled by software override.
3058 */
3059 an_cntl |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3060 an_cntl &= ~IXGBE_KRM_AN_CNTL_1_SYM_PAUSE;
3061 break;
3062 case ixgbe_fc_rx_pause:
3063 /* Rx Flow control is enabled and Tx Flow control is
3064 * disabled by software override. Since there really
3065 * isn't a way to advertise that we are capable of RX
3066 * Pause ONLY, we will advertise that we support both
3067 * symmetric and asymmetric Rx PAUSE, as such we fall
3068 * through to the fc_full statement. Later, we will
3069 * disable the adapter's ability to send PAUSE frames.
3070 */
3071 case ixgbe_fc_full:
3072 /* Flow control (both Rx and Tx) is enabled by SW override. */
3073 an_cntl |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE |
3074 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE;
3075 break;
3076 default:
3077 hw_err(hw, "Flow control param set incorrectly\n");
3078 return IXGBE_ERR_CONFIG;
3079 }
3080
3081 status = hw->mac.ops.write_iosf_sb_reg(hw,
3082 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id),
3083 IXGBE_SB_IOSF_TARGET_KR_PHY, an_cntl);
3084
3085 /* Restart auto-negotiation. */
3086 status = ixgbe_restart_an_internal_phy_x550em(hw);
3087
3088 return status;
3089}
3090
3091/**
3092 * ixgbe_set_mux - Set mux for port 1 access with CS4227
3093 * @hw: pointer to hardware structure
3094 * @state: set mux if 1, clear if 0
3095 */
3096static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state)
3097{
3098 u32 esdp;
3099
3100 if (!hw->bus.lan_id)
3101 return;
3102 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3103 if (state)
3104 esdp |= IXGBE_ESDP_SDP1;
3105 else
3106 esdp &= ~IXGBE_ESDP_SDP1;
3107 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
3108 IXGBE_WRITE_FLUSH(hw);
3109}
3110
3111/**
3112 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore
3113 * @hw: pointer to hardware structure
3114 * @mask: Mask to specify which semaphore to acquire
3115 *
3116 * Acquires the SWFW semaphore and sets the I2C MUX
3117 */
3118static s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3119{
3120 s32 status;
3121
3122 status = ixgbe_acquire_swfw_sync_X540(hw, mask);
3123 if (status)
3124 return status;
3125
3126 if (mask & IXGBE_GSSR_I2C_MASK)
3127 ixgbe_set_mux(hw, 1);
3128
3129 return 0;
3130}
3131
3132/**
3133 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore
3134 * @hw: pointer to hardware structure
3135 * @mask: Mask to specify which semaphore to release
3136 *
3137 * Releases the SWFW semaphore and sets the I2C MUX
3138 */
3139static void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask)
3140{
3141 if (mask & IXGBE_GSSR_I2C_MASK)
3142 ixgbe_set_mux(hw, 0);
3143
3144 ixgbe_release_swfw_sync_X540(hw, mask);
3145}
3146
3147/**
3148 * ixgbe_acquire_swfw_sync_x550em_a - Acquire SWFW semaphore
3149 * @hw: pointer to hardware structure
3150 * @mask: Mask to specify which semaphore to acquire
3151 *
3152 * Acquires the SWFW semaphore and get the shared PHY token as needed
3153 */
3154static s32 ixgbe_acquire_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3155{
3156 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3157 int retries = FW_PHY_TOKEN_RETRIES;
3158 s32 status;
3159
3160 while (--retries) {
3161 status = 0;
3162 if (hmask)
3163 status = ixgbe_acquire_swfw_sync_X540(hw, hmask);
3164 if (status)
3165 return status;
3166 if (!(mask & IXGBE_GSSR_TOKEN_SM))
3167 return 0;
3168
3169 status = ixgbe_get_phy_token(hw);
3170 if (!status)
3171 return 0;
3172 if (hmask)
3173 ixgbe_release_swfw_sync_X540(hw, hmask);
3174 if (status != IXGBE_ERR_TOKEN_RETRY)
3175 return status;
3176 msleep(FW_PHY_TOKEN_DELAY);
3177 }
3178
3179 return status;
3180}
3181
3182/**
3183 * ixgbe_release_swfw_sync_x550em_a - Release SWFW semaphore
3184 * @hw: pointer to hardware structure
3185 * @mask: Mask to specify which semaphore to release
3186 *
3187 * Release the SWFW semaphore and puts the shared PHY token as needed
3188 */
3189static void ixgbe_release_swfw_sync_x550em_a(struct ixgbe_hw *hw, u32 mask)
3190{
3191 u32 hmask = mask & ~IXGBE_GSSR_TOKEN_SM;
3192
3193 if (mask & IXGBE_GSSR_TOKEN_SM)
3194 ixgbe_put_phy_token(hw);
3195
3196 if (hmask)
3197 ixgbe_release_swfw_sync_X540(hw, hmask);
3198}
3199
3200/**
3201 * ixgbe_read_phy_reg_x550a - Reads specified PHY register
3202 * @hw: pointer to hardware structure
3203 * @reg_addr: 32 bit address of PHY register to read
3204 * @phy_data: Pointer to read data from PHY register
3205 *
3206 * Reads a value from a specified PHY register using the SWFW lock and PHY
3207 * Token. The PHY Token is needed since the MDIO is shared between to MAC
3208 * instances.
3209 */
3210static s32 ixgbe_read_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3211 u32 device_type, u16 *phy_data)
3212{
3213 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3214 s32 status;
3215
3216 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3217 return IXGBE_ERR_SWFW_SYNC;
3218
3219 status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
3220
3221 hw->mac.ops.release_swfw_sync(hw, mask);
3222
3223 return status;
3224}
3225
3226/**
3227 * ixgbe_write_phy_reg_x550a - Writes specified PHY register
3228 * @hw: pointer to hardware structure
3229 * @reg_addr: 32 bit PHY register to write
3230 * @device_type: 5 bit device type
3231 * @phy_data: Data to write to the PHY register
3232 *
3233 * Writes a value to specified PHY register using the SWFW lock and PHY Token.
3234 * The PHY Token is needed since the MDIO is shared between to MAC instances.
3235 */
3236static s32 ixgbe_write_phy_reg_x550a(struct ixgbe_hw *hw, u32 reg_addr,
3237 u32 device_type, u16 phy_data)
3238{
3239 u32 mask = hw->phy.phy_semaphore_mask | IXGBE_GSSR_TOKEN_SM;
3240 s32 status;
3241
3242 if (hw->mac.ops.acquire_swfw_sync(hw, mask))
3243 return IXGBE_ERR_SWFW_SYNC;
3244
3245 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, phy_data);
3246 hw->mac.ops.release_swfw_sync(hw, mask);
3247
3248 return status;
3249}
3250
3251#define X550_COMMON_MAC \
3252 .init_hw = &ixgbe_init_hw_generic, \
3253 .start_hw = &ixgbe_start_hw_X540, \
3254 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic, \
3255 .enable_rx_dma = &ixgbe_enable_rx_dma_generic, \
3256 .get_mac_addr = &ixgbe_get_mac_addr_generic, \
3257 .get_device_caps = &ixgbe_get_device_caps_generic, \
3258 .stop_adapter = &ixgbe_stop_adapter_generic, \
3259 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie, \
3260 .read_analog_reg8 = NULL, \
3261 .write_analog_reg8 = NULL, \
3262 .set_rxpba = &ixgbe_set_rxpba_generic, \
3263 .check_link = &ixgbe_check_mac_link_generic, \
3264 .blink_led_start = &ixgbe_blink_led_start_X540, \
3265 .blink_led_stop = &ixgbe_blink_led_stop_X540, \
3266 .set_rar = &ixgbe_set_rar_generic, \
3267 .clear_rar = &ixgbe_clear_rar_generic, \
3268 .set_vmdq = &ixgbe_set_vmdq_generic, \
3269 .set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic, \
3270 .clear_vmdq = &ixgbe_clear_vmdq_generic, \
3271 .init_rx_addrs = &ixgbe_init_rx_addrs_generic, \
3272 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic, \
3273 .enable_mc = &ixgbe_enable_mc_generic, \
3274 .disable_mc = &ixgbe_disable_mc_generic, \
3275 .clear_vfta = &ixgbe_clear_vfta_generic, \
3276 .set_vfta = &ixgbe_set_vfta_generic, \
3277 .fc_enable = &ixgbe_fc_enable_generic, \
3278 .set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic, \
3279 .init_uta_tables = &ixgbe_init_uta_tables_generic, \
3280 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing, \
3281 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing, \
3282 .set_source_address_pruning = \
3283 &ixgbe_set_source_address_pruning_X550, \
3284 .set_ethertype_anti_spoofing = \
3285 &ixgbe_set_ethertype_anti_spoofing_X550, \
3286 .disable_rx_buff = &ixgbe_disable_rx_buff_generic, \
3287 .enable_rx_buff = &ixgbe_enable_rx_buff_generic, \
3288 .get_thermal_sensor_data = NULL, \
3289 .init_thermal_sensor_thresh = NULL, \
3290 .enable_rx = &ixgbe_enable_rx_generic, \
3291 .disable_rx = &ixgbe_disable_rx_x550, \
3292
3293static const struct ixgbe_mac_operations mac_ops_X550 = {
3294 X550_COMMON_MAC
3295 .led_on = ixgbe_led_on_generic,
3296 .led_off = ixgbe_led_off_generic,
3297 .init_led_link_act = ixgbe_init_led_link_act_generic,
3298 .reset_hw = &ixgbe_reset_hw_X540,
3299 .get_media_type = &ixgbe_get_media_type_X540,
3300 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
3301 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
3302 .setup_link = &ixgbe_setup_mac_link_X540,
3303 .get_link_capabilities = &ixgbe_get_copper_link_capabilities_generic,
3304 .get_bus_info = &ixgbe_get_bus_info_generic,
3305 .setup_sfp = NULL,
3306 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X540,
3307 .release_swfw_sync = &ixgbe_release_swfw_sync_X540,
3308 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3309 .prot_autoc_read = prot_autoc_read_generic,
3310 .prot_autoc_write = prot_autoc_write_generic,
3311 .setup_fc = ixgbe_setup_fc_generic,
3312 .fc_autoneg = ixgbe_fc_autoneg,
3313};
3314
3315static const struct ixgbe_mac_operations mac_ops_X550EM_x = {
3316 X550_COMMON_MAC
3317 .led_on = ixgbe_led_on_t_x550em,
3318 .led_off = ixgbe_led_off_t_x550em,
3319 .init_led_link_act = ixgbe_init_led_link_act_generic,
3320 .reset_hw = &ixgbe_reset_hw_X550em,
3321 .get_media_type = &ixgbe_get_media_type_X550em,
3322 .get_san_mac_addr = NULL,
3323 .get_wwn_prefix = NULL,
3324 .setup_link = &ixgbe_setup_mac_link_X540,
3325 .get_link_capabilities = &ixgbe_get_link_capabilities_X550em,
3326 .get_bus_info = &ixgbe_get_bus_info_X550em,
3327 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3328 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync_X550em,
3329 .release_swfw_sync = &ixgbe_release_swfw_sync_X550em,
3330 .init_swfw_sync = &ixgbe_init_swfw_sync_X540,
3331 .setup_fc = NULL, /* defined later */
3332 .fc_autoneg = ixgbe_fc_autoneg,
3333 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550,
3334 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550,
3335};
3336
3337static struct ixgbe_mac_operations mac_ops_x550em_a = {
3338 X550_COMMON_MAC
3339 .led_on = ixgbe_led_on_t_x550em,
3340 .led_off = ixgbe_led_off_t_x550em,
3341 .init_led_link_act = ixgbe_init_led_link_act_generic,
3342 .reset_hw = ixgbe_reset_hw_X550em,
3343 .get_media_type = ixgbe_get_media_type_X550em,
3344 .get_san_mac_addr = NULL,
3345 .get_wwn_prefix = NULL,
3346 .setup_link = NULL, /* defined later */
3347 .get_link_capabilities = ixgbe_get_link_capabilities_X550em,
3348 .get_bus_info = ixgbe_get_bus_info_X550em,
3349 .setup_sfp = ixgbe_setup_sfp_modules_X550em,
3350 .acquire_swfw_sync = ixgbe_acquire_swfw_sync_x550em_a,
3351 .release_swfw_sync = ixgbe_release_swfw_sync_x550em_a,
3352 .setup_fc = ixgbe_setup_fc_x550em,
3353 .fc_autoneg = ixgbe_fc_autoneg,
3354 .read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550a,
3355 .write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550a,
3356};
3357
3358#define X550_COMMON_EEP \
3359 .read = &ixgbe_read_ee_hostif_X550, \
3360 .read_buffer = &ixgbe_read_ee_hostif_buffer_X550, \
3361 .write = &ixgbe_write_ee_hostif_X550, \
3362 .write_buffer = &ixgbe_write_ee_hostif_buffer_X550, \
3363 .validate_checksum = &ixgbe_validate_eeprom_checksum_X550, \
3364 .update_checksum = &ixgbe_update_eeprom_checksum_X550, \
3365 .calc_checksum = &ixgbe_calc_eeprom_checksum_X550, \
3366
3367static const struct ixgbe_eeprom_operations eeprom_ops_X550 = {
3368 X550_COMMON_EEP
3369 .init_params = &ixgbe_init_eeprom_params_X550,
3370};
3371
3372static const struct ixgbe_eeprom_operations eeprom_ops_X550EM_x = {
3373 X550_COMMON_EEP
3374 .init_params = &ixgbe_init_eeprom_params_X540,
3375};
3376
3377#define X550_COMMON_PHY \
3378 .identify_sfp = &ixgbe_identify_module_generic, \
3379 .reset = NULL, \
3380 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic, \
3381 .read_i2c_byte = &ixgbe_read_i2c_byte_generic, \
3382 .write_i2c_byte = &ixgbe_write_i2c_byte_generic, \
3383 .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic, \
3384 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic, \
3385 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic, \
3386 .setup_link = &ixgbe_setup_phy_link_generic, \
3387 .set_phy_power = NULL, \
3388 .check_overtemp = &ixgbe_tn_check_overtemp, \
3389 .get_firmware_version = &ixgbe_get_phy_firmware_version_generic,
3390
3391static const struct ixgbe_phy_operations phy_ops_X550 = {
3392 X550_COMMON_PHY
3393 .init = NULL,
3394 .identify = &ixgbe_identify_phy_generic,
3395 .read_reg = &ixgbe_read_phy_reg_generic,
3396 .write_reg = &ixgbe_write_phy_reg_generic,
3397};
3398
3399static const struct ixgbe_phy_operations phy_ops_X550EM_x = {
3400 X550_COMMON_PHY
3401 .init = &ixgbe_init_phy_ops_X550em,
3402 .identify = &ixgbe_identify_phy_x550em,
3403 .read_reg = &ixgbe_read_phy_reg_generic,
3404 .write_reg = &ixgbe_write_phy_reg_generic,
3405};
3406
3407static const struct ixgbe_phy_operations phy_ops_x550em_a = {
3408 X550_COMMON_PHY
3409 .init = &ixgbe_init_phy_ops_X550em,
3410 .identify = &ixgbe_identify_phy_x550em,
3411 .read_reg = &ixgbe_read_phy_reg_x550a,
3412 .write_reg = &ixgbe_write_phy_reg_x550a,
3413 .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
3414 .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
3415};
3416
3417static const struct ixgbe_link_operations link_ops_x550em_x = {
3418 .read_link = &ixgbe_read_i2c_combined_generic,
3419 .read_link_unlocked = &ixgbe_read_i2c_combined_generic_unlocked,
3420 .write_link = &ixgbe_write_i2c_combined_generic,
3421 .write_link_unlocked = &ixgbe_write_i2c_combined_generic_unlocked,
3422};
3423
3424static const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = {
3425 IXGBE_MVALS_INIT(X550)
3426};
3427
3428static const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = {
3429 IXGBE_MVALS_INIT(X550EM_x)
3430};
3431
3432static const u32 ixgbe_mvals_x550em_a[IXGBE_MVALS_IDX_LIMIT] = {
3433 IXGBE_MVALS_INIT(X550EM_a)
3434};
3435
3436const struct ixgbe_info ixgbe_X550_info = {
3437 .mac = ixgbe_mac_X550,
3438 .get_invariants = &ixgbe_get_invariants_X540,
3439 .mac_ops = &mac_ops_X550,
3440 .eeprom_ops = &eeprom_ops_X550,
3441 .phy_ops = &phy_ops_X550,
3442 .mbx_ops = &mbx_ops_generic,
3443 .mvals = ixgbe_mvals_X550,
3444};
3445
3446const struct ixgbe_info ixgbe_X550EM_x_info = {
3447 .mac = ixgbe_mac_X550EM_x,
3448 .get_invariants = &ixgbe_get_invariants_X550_x,
3449 .mac_ops = &mac_ops_X550EM_x,
3450 .eeprom_ops = &eeprom_ops_X550EM_x,
3451 .phy_ops = &phy_ops_X550EM_x,
3452 .mbx_ops = &mbx_ops_generic,
3453 .mvals = ixgbe_mvals_X550EM_x,
3454 .link_ops = &link_ops_x550em_x,
3455};
3456
3457const struct ixgbe_info ixgbe_x550em_a_info = {
3458 .mac = ixgbe_mac_x550em_a,
3459 .get_invariants = &ixgbe_get_invariants_X550_a,
3460 .mac_ops = &mac_ops_x550em_a,
3461 .eeprom_ops = &eeprom_ops_X550EM_x,
3462 .phy_ops = &phy_ops_x550em_a,
3463 .mbx_ops = &mbx_ops_generic,
3464 .mvals = ixgbe_mvals_x550em_a,
3465};