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1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include <linux/prefetch.h>
28#include <net/busy_poll.h>
29
30#include "i40evf.h"
31#include "i40e_prototype.h"
32
33static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
34 u32 td_tag)
35{
36 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
37 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
38 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
39 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
40 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
41}
42
43#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
44
45/**
46 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
47 * @ring: the ring that owns the buffer
48 * @tx_buffer: the buffer to free
49 **/
50static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
51 struct i40e_tx_buffer *tx_buffer)
52{
53 if (tx_buffer->skb) {
54 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
55 kfree(tx_buffer->raw_buf);
56 else
57 dev_kfree_skb_any(tx_buffer->skb);
58 if (dma_unmap_len(tx_buffer, len))
59 dma_unmap_single(ring->dev,
60 dma_unmap_addr(tx_buffer, dma),
61 dma_unmap_len(tx_buffer, len),
62 DMA_TO_DEVICE);
63 } else if (dma_unmap_len(tx_buffer, len)) {
64 dma_unmap_page(ring->dev,
65 dma_unmap_addr(tx_buffer, dma),
66 dma_unmap_len(tx_buffer, len),
67 DMA_TO_DEVICE);
68 }
69
70 tx_buffer->next_to_watch = NULL;
71 tx_buffer->skb = NULL;
72 dma_unmap_len_set(tx_buffer, len, 0);
73 /* tx_buffer must be completely set up in the transmit path */
74}
75
76/**
77 * i40evf_clean_tx_ring - Free any empty Tx buffers
78 * @tx_ring: ring to be cleaned
79 **/
80void i40evf_clean_tx_ring(struct i40e_ring *tx_ring)
81{
82 unsigned long bi_size;
83 u16 i;
84
85 /* ring already cleared, nothing to do */
86 if (!tx_ring->tx_bi)
87 return;
88
89 /* Free all the Tx ring sk_buffs */
90 for (i = 0; i < tx_ring->count; i++)
91 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
92
93 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
94 memset(tx_ring->tx_bi, 0, bi_size);
95
96 /* Zero out the descriptor ring */
97 memset(tx_ring->desc, 0, tx_ring->size);
98
99 tx_ring->next_to_use = 0;
100 tx_ring->next_to_clean = 0;
101
102 if (!tx_ring->netdev)
103 return;
104
105 /* cleanup Tx queue statistics */
106 netdev_tx_reset_queue(txring_txq(tx_ring));
107}
108
109/**
110 * i40evf_free_tx_resources - Free Tx resources per queue
111 * @tx_ring: Tx descriptor ring for a specific queue
112 *
113 * Free all transmit software resources
114 **/
115void i40evf_free_tx_resources(struct i40e_ring *tx_ring)
116{
117 i40evf_clean_tx_ring(tx_ring);
118 kfree(tx_ring->tx_bi);
119 tx_ring->tx_bi = NULL;
120
121 if (tx_ring->desc) {
122 dma_free_coherent(tx_ring->dev, tx_ring->size,
123 tx_ring->desc, tx_ring->dma);
124 tx_ring->desc = NULL;
125 }
126}
127
128/**
129 * i40evf_get_tx_pending - how many Tx descriptors not processed
130 * @tx_ring: the ring of descriptors
131 * @in_sw: is tx_pending being checked in SW or HW
132 *
133 * Since there is no access to the ring head register
134 * in XL710, we need to use our local copies
135 **/
136u32 i40evf_get_tx_pending(struct i40e_ring *ring, bool in_sw)
137{
138 u32 head, tail;
139
140 if (!in_sw)
141 head = i40e_get_head(ring);
142 else
143 head = ring->next_to_clean;
144 tail = readl(ring->tail);
145
146 if (head != tail)
147 return (head < tail) ?
148 tail - head : (tail + ring->count - head);
149
150 return 0;
151}
152
153#define WB_STRIDE 4
154
155/**
156 * i40e_clean_tx_irq - Reclaim resources after transmit completes
157 * @vsi: the VSI we care about
158 * @tx_ring: Tx ring to clean
159 * @napi_budget: Used to determine if we are in netpoll
160 *
161 * Returns true if there's any budget left (e.g. the clean is finished)
162 **/
163static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
164 struct i40e_ring *tx_ring, int napi_budget)
165{
166 u16 i = tx_ring->next_to_clean;
167 struct i40e_tx_buffer *tx_buf;
168 struct i40e_tx_desc *tx_head;
169 struct i40e_tx_desc *tx_desc;
170 unsigned int total_bytes = 0, total_packets = 0;
171 unsigned int budget = vsi->work_limit;
172
173 tx_buf = &tx_ring->tx_bi[i];
174 tx_desc = I40E_TX_DESC(tx_ring, i);
175 i -= tx_ring->count;
176
177 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
178
179 do {
180 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
181
182 /* if next_to_watch is not set then there is no work pending */
183 if (!eop_desc)
184 break;
185
186 /* prevent any other reads prior to eop_desc */
187 read_barrier_depends();
188
189 /* we have caught up to head, no work left to do */
190 if (tx_head == tx_desc)
191 break;
192
193 /* clear next_to_watch to prevent false hangs */
194 tx_buf->next_to_watch = NULL;
195
196 /* update the statistics for this packet */
197 total_bytes += tx_buf->bytecount;
198 total_packets += tx_buf->gso_segs;
199
200 /* free the skb */
201 napi_consume_skb(tx_buf->skb, napi_budget);
202
203 /* unmap skb header data */
204 dma_unmap_single(tx_ring->dev,
205 dma_unmap_addr(tx_buf, dma),
206 dma_unmap_len(tx_buf, len),
207 DMA_TO_DEVICE);
208
209 /* clear tx_buffer data */
210 tx_buf->skb = NULL;
211 dma_unmap_len_set(tx_buf, len, 0);
212
213 /* unmap remaining buffers */
214 while (tx_desc != eop_desc) {
215
216 tx_buf++;
217 tx_desc++;
218 i++;
219 if (unlikely(!i)) {
220 i -= tx_ring->count;
221 tx_buf = tx_ring->tx_bi;
222 tx_desc = I40E_TX_DESC(tx_ring, 0);
223 }
224
225 /* unmap any remaining paged data */
226 if (dma_unmap_len(tx_buf, len)) {
227 dma_unmap_page(tx_ring->dev,
228 dma_unmap_addr(tx_buf, dma),
229 dma_unmap_len(tx_buf, len),
230 DMA_TO_DEVICE);
231 dma_unmap_len_set(tx_buf, len, 0);
232 }
233 }
234
235 /* move us one more past the eop_desc for start of next pkt */
236 tx_buf++;
237 tx_desc++;
238 i++;
239 if (unlikely(!i)) {
240 i -= tx_ring->count;
241 tx_buf = tx_ring->tx_bi;
242 tx_desc = I40E_TX_DESC(tx_ring, 0);
243 }
244
245 prefetch(tx_desc);
246
247 /* update budget accounting */
248 budget--;
249 } while (likely(budget));
250
251 i += tx_ring->count;
252 tx_ring->next_to_clean = i;
253 u64_stats_update_begin(&tx_ring->syncp);
254 tx_ring->stats.bytes += total_bytes;
255 tx_ring->stats.packets += total_packets;
256 u64_stats_update_end(&tx_ring->syncp);
257 tx_ring->q_vector->tx.total_bytes += total_bytes;
258 tx_ring->q_vector->tx.total_packets += total_packets;
259
260 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
261 /* check to see if there are < 4 descriptors
262 * waiting to be written back, then kick the hardware to force
263 * them to be written back in case we stay in NAPI.
264 * In this mode on X722 we do not enable Interrupt.
265 */
266 unsigned int j = i40evf_get_tx_pending(tx_ring, false);
267
268 if (budget &&
269 ((j / WB_STRIDE) == 0) && (j > 0) &&
270 !test_bit(__I40E_DOWN, &vsi->state) &&
271 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
272 tx_ring->arm_wb = true;
273 }
274
275 /* notify netdev of completed buffers */
276 netdev_tx_completed_queue(txring_txq(tx_ring),
277 total_packets, total_bytes);
278
279#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
280 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
281 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
282 /* Make sure that anybody stopping the queue after this
283 * sees the new next_to_clean.
284 */
285 smp_mb();
286 if (__netif_subqueue_stopped(tx_ring->netdev,
287 tx_ring->queue_index) &&
288 !test_bit(__I40E_DOWN, &vsi->state)) {
289 netif_wake_subqueue(tx_ring->netdev,
290 tx_ring->queue_index);
291 ++tx_ring->tx_stats.restart_queue;
292 }
293 }
294
295 return !!budget;
296}
297
298/**
299 * i40evf_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
300 * @vsi: the VSI we care about
301 * @q_vector: the vector on which to enable writeback
302 *
303 **/
304static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
305 struct i40e_q_vector *q_vector)
306{
307 u16 flags = q_vector->tx.ring[0].flags;
308 u32 val;
309
310 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
311 return;
312
313 if (q_vector->arm_wb_state)
314 return;
315
316 val = I40E_VFINT_DYN_CTLN1_WB_ON_ITR_MASK |
317 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK; /* set noitr */
318
319 wr32(&vsi->back->hw,
320 I40E_VFINT_DYN_CTLN1(q_vector->v_idx +
321 vsi->base_vector - 1), val);
322 q_vector->arm_wb_state = true;
323}
324
325/**
326 * i40evf_force_wb - Issue SW Interrupt so HW does a wb
327 * @vsi: the VSI we care about
328 * @q_vector: the vector on which to force writeback
329 *
330 **/
331void i40evf_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
332{
333 u32 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
334 I40E_VFINT_DYN_CTLN1_ITR_INDX_MASK | /* set noitr */
335 I40E_VFINT_DYN_CTLN1_SWINT_TRIG_MASK |
336 I40E_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK
337 /* allow 00 to be written to the index */;
338
339 wr32(&vsi->back->hw,
340 I40E_VFINT_DYN_CTLN1(q_vector->v_idx + vsi->base_vector - 1),
341 val);
342}
343
344/**
345 * i40e_set_new_dynamic_itr - Find new ITR level
346 * @rc: structure containing ring performance data
347 *
348 * Returns true if ITR changed, false if not
349 *
350 * Stores a new ITR value based on packets and byte counts during
351 * the last interrupt. The advantage of per interrupt computation
352 * is faster updates and more accurate ITR for the current traffic
353 * pattern. Constants in this function were computed based on
354 * theoretical maximum wire speed and thresholds were set based on
355 * testing data as well as attempting to minimize response time
356 * while increasing bulk throughput.
357 **/
358static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
359{
360 enum i40e_latency_range new_latency_range = rc->latency_range;
361 struct i40e_q_vector *qv = rc->ring->q_vector;
362 u32 new_itr = rc->itr;
363 int bytes_per_int;
364 int usecs;
365
366 if (rc->total_packets == 0 || !rc->itr)
367 return false;
368
369 /* simple throttlerate management
370 * 0-10MB/s lowest (50000 ints/s)
371 * 10-20MB/s low (20000 ints/s)
372 * 20-1249MB/s bulk (18000 ints/s)
373 * > 40000 Rx packets per second (8000 ints/s)
374 *
375 * The math works out because the divisor is in 10^(-6) which
376 * turns the bytes/us input value into MB/s values, but
377 * make sure to use usecs, as the register values written
378 * are in 2 usec increments in the ITR registers, and make sure
379 * to use the smoothed values that the countdown timer gives us.
380 */
381 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
382 bytes_per_int = rc->total_bytes / usecs;
383
384 switch (new_latency_range) {
385 case I40E_LOWEST_LATENCY:
386 if (bytes_per_int > 10)
387 new_latency_range = I40E_LOW_LATENCY;
388 break;
389 case I40E_LOW_LATENCY:
390 if (bytes_per_int > 20)
391 new_latency_range = I40E_BULK_LATENCY;
392 else if (bytes_per_int <= 10)
393 new_latency_range = I40E_LOWEST_LATENCY;
394 break;
395 case I40E_BULK_LATENCY:
396 case I40E_ULTRA_LATENCY:
397 default:
398 if (bytes_per_int <= 20)
399 new_latency_range = I40E_LOW_LATENCY;
400 break;
401 }
402
403 /* this is to adjust RX more aggressively when streaming small
404 * packets. The value of 40000 was picked as it is just beyond
405 * what the hardware can receive per second if in low latency
406 * mode.
407 */
408#define RX_ULTRA_PACKET_RATE 40000
409
410 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
411 (&qv->rx == rc))
412 new_latency_range = I40E_ULTRA_LATENCY;
413
414 rc->latency_range = new_latency_range;
415
416 switch (new_latency_range) {
417 case I40E_LOWEST_LATENCY:
418 new_itr = I40E_ITR_50K;
419 break;
420 case I40E_LOW_LATENCY:
421 new_itr = I40E_ITR_20K;
422 break;
423 case I40E_BULK_LATENCY:
424 new_itr = I40E_ITR_18K;
425 break;
426 case I40E_ULTRA_LATENCY:
427 new_itr = I40E_ITR_8K;
428 break;
429 default:
430 break;
431 }
432
433 rc->total_bytes = 0;
434 rc->total_packets = 0;
435
436 if (new_itr != rc->itr) {
437 rc->itr = new_itr;
438 return true;
439 }
440
441 return false;
442}
443
444/**
445 * i40evf_setup_tx_descriptors - Allocate the Tx descriptors
446 * @tx_ring: the tx ring to set up
447 *
448 * Return 0 on success, negative on error
449 **/
450int i40evf_setup_tx_descriptors(struct i40e_ring *tx_ring)
451{
452 struct device *dev = tx_ring->dev;
453 int bi_size;
454
455 if (!dev)
456 return -ENOMEM;
457
458 /* warn if we are about to overwrite the pointer */
459 WARN_ON(tx_ring->tx_bi);
460 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
461 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
462 if (!tx_ring->tx_bi)
463 goto err;
464
465 /* round up to nearest 4K */
466 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
467 /* add u32 for head writeback, align after this takes care of
468 * guaranteeing this is at least one cache line in size
469 */
470 tx_ring->size += sizeof(u32);
471 tx_ring->size = ALIGN(tx_ring->size, 4096);
472 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
473 &tx_ring->dma, GFP_KERNEL);
474 if (!tx_ring->desc) {
475 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
476 tx_ring->size);
477 goto err;
478 }
479
480 tx_ring->next_to_use = 0;
481 tx_ring->next_to_clean = 0;
482 return 0;
483
484err:
485 kfree(tx_ring->tx_bi);
486 tx_ring->tx_bi = NULL;
487 return -ENOMEM;
488}
489
490/**
491 * i40evf_clean_rx_ring - Free Rx buffers
492 * @rx_ring: ring to be cleaned
493 **/
494void i40evf_clean_rx_ring(struct i40e_ring *rx_ring)
495{
496 struct device *dev = rx_ring->dev;
497 unsigned long bi_size;
498 u16 i;
499
500 /* ring already cleared, nothing to do */
501 if (!rx_ring->rx_bi)
502 return;
503
504 /* Free all the Rx ring sk_buffs */
505 for (i = 0; i < rx_ring->count; i++) {
506 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i];
507
508 if (rx_bi->skb) {
509 dev_kfree_skb(rx_bi->skb);
510 rx_bi->skb = NULL;
511 }
512 if (!rx_bi->page)
513 continue;
514
515 dma_unmap_page(dev, rx_bi->dma, PAGE_SIZE, DMA_FROM_DEVICE);
516 __free_pages(rx_bi->page, 0);
517
518 rx_bi->page = NULL;
519 rx_bi->page_offset = 0;
520 }
521
522 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
523 memset(rx_ring->rx_bi, 0, bi_size);
524
525 /* Zero out the descriptor ring */
526 memset(rx_ring->desc, 0, rx_ring->size);
527
528 rx_ring->next_to_alloc = 0;
529 rx_ring->next_to_clean = 0;
530 rx_ring->next_to_use = 0;
531}
532
533/**
534 * i40evf_free_rx_resources - Free Rx resources
535 * @rx_ring: ring to clean the resources from
536 *
537 * Free all receive software resources
538 **/
539void i40evf_free_rx_resources(struct i40e_ring *rx_ring)
540{
541 i40evf_clean_rx_ring(rx_ring);
542 kfree(rx_ring->rx_bi);
543 rx_ring->rx_bi = NULL;
544
545 if (rx_ring->desc) {
546 dma_free_coherent(rx_ring->dev, rx_ring->size,
547 rx_ring->desc, rx_ring->dma);
548 rx_ring->desc = NULL;
549 }
550}
551
552/**
553 * i40evf_setup_rx_descriptors - Allocate Rx descriptors
554 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
555 *
556 * Returns 0 on success, negative on failure
557 **/
558int i40evf_setup_rx_descriptors(struct i40e_ring *rx_ring)
559{
560 struct device *dev = rx_ring->dev;
561 int bi_size;
562
563 /* warn if we are about to overwrite the pointer */
564 WARN_ON(rx_ring->rx_bi);
565 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
566 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
567 if (!rx_ring->rx_bi)
568 goto err;
569
570 u64_stats_init(&rx_ring->syncp);
571
572 /* Round up to nearest 4K */
573 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
574 rx_ring->size = ALIGN(rx_ring->size, 4096);
575 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
576 &rx_ring->dma, GFP_KERNEL);
577
578 if (!rx_ring->desc) {
579 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
580 rx_ring->size);
581 goto err;
582 }
583
584 rx_ring->next_to_alloc = 0;
585 rx_ring->next_to_clean = 0;
586 rx_ring->next_to_use = 0;
587
588 return 0;
589err:
590 kfree(rx_ring->rx_bi);
591 rx_ring->rx_bi = NULL;
592 return -ENOMEM;
593}
594
595/**
596 * i40e_release_rx_desc - Store the new tail and head values
597 * @rx_ring: ring to bump
598 * @val: new head index
599 **/
600static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
601{
602 rx_ring->next_to_use = val;
603
604 /* update next to alloc since we have filled the ring */
605 rx_ring->next_to_alloc = val;
606
607 /* Force memory writes to complete before letting h/w
608 * know there are new descriptors to fetch. (Only
609 * applicable for weak-ordered memory model archs,
610 * such as IA-64).
611 */
612 wmb();
613 writel(val, rx_ring->tail);
614}
615
616/**
617 * i40e_alloc_mapped_page - recycle or make a new page
618 * @rx_ring: ring to use
619 * @bi: rx_buffer struct to modify
620 *
621 * Returns true if the page was successfully allocated or
622 * reused.
623 **/
624static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
625 struct i40e_rx_buffer *bi)
626{
627 struct page *page = bi->page;
628 dma_addr_t dma;
629
630 /* since we are recycling buffers we should seldom need to alloc */
631 if (likely(page)) {
632 rx_ring->rx_stats.page_reuse_count++;
633 return true;
634 }
635
636 /* alloc new page for storage */
637 page = dev_alloc_page();
638 if (unlikely(!page)) {
639 rx_ring->rx_stats.alloc_page_failed++;
640 return false;
641 }
642
643 /* map page for use */
644 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
645
646 /* if mapping failed free memory back to system since
647 * there isn't much point in holding memory we can't use
648 */
649 if (dma_mapping_error(rx_ring->dev, dma)) {
650 __free_pages(page, 0);
651 rx_ring->rx_stats.alloc_page_failed++;
652 return false;
653 }
654
655 bi->dma = dma;
656 bi->page = page;
657 bi->page_offset = 0;
658
659 return true;
660}
661
662/**
663 * i40e_receive_skb - Send a completed packet up the stack
664 * @rx_ring: rx ring in play
665 * @skb: packet to send up
666 * @vlan_tag: vlan tag for packet
667 **/
668static void i40e_receive_skb(struct i40e_ring *rx_ring,
669 struct sk_buff *skb, u16 vlan_tag)
670{
671 struct i40e_q_vector *q_vector = rx_ring->q_vector;
672
673 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
674 (vlan_tag & VLAN_VID_MASK))
675 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
676
677 napi_gro_receive(&q_vector->napi, skb);
678}
679
680/**
681 * i40evf_alloc_rx_buffers - Replace used receive buffers
682 * @rx_ring: ring to place buffers on
683 * @cleaned_count: number of buffers to replace
684 *
685 * Returns false if all allocations were successful, true if any fail
686 **/
687bool i40evf_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
688{
689 u16 ntu = rx_ring->next_to_use;
690 union i40e_rx_desc *rx_desc;
691 struct i40e_rx_buffer *bi;
692
693 /* do nothing if no valid netdev defined */
694 if (!rx_ring->netdev || !cleaned_count)
695 return false;
696
697 rx_desc = I40E_RX_DESC(rx_ring, ntu);
698 bi = &rx_ring->rx_bi[ntu];
699
700 do {
701 if (!i40e_alloc_mapped_page(rx_ring, bi))
702 goto no_buffers;
703
704 /* Refresh the desc even if buffer_addrs didn't change
705 * because each write-back erases this info.
706 */
707 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
708
709 rx_desc++;
710 bi++;
711 ntu++;
712 if (unlikely(ntu == rx_ring->count)) {
713 rx_desc = I40E_RX_DESC(rx_ring, 0);
714 bi = rx_ring->rx_bi;
715 ntu = 0;
716 }
717
718 /* clear the status bits for the next_to_use descriptor */
719 rx_desc->wb.qword1.status_error_len = 0;
720
721 cleaned_count--;
722 } while (cleaned_count);
723
724 if (rx_ring->next_to_use != ntu)
725 i40e_release_rx_desc(rx_ring, ntu);
726
727 return false;
728
729no_buffers:
730 if (rx_ring->next_to_use != ntu)
731 i40e_release_rx_desc(rx_ring, ntu);
732
733 /* make sure to come back via polling to try again after
734 * allocation failure
735 */
736 return true;
737}
738
739/**
740 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
741 * @vsi: the VSI we care about
742 * @skb: skb currently being received and modified
743 * @rx_desc: the receive descriptor
744 *
745 * skb->protocol must be set before this function is called
746 **/
747static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
748 struct sk_buff *skb,
749 union i40e_rx_desc *rx_desc)
750{
751 struct i40e_rx_ptype_decoded decoded;
752 u32 rx_error, rx_status;
753 bool ipv4, ipv6;
754 u8 ptype;
755 u64 qword;
756
757 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
758 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
759 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
760 I40E_RXD_QW1_ERROR_SHIFT;
761 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
762 I40E_RXD_QW1_STATUS_SHIFT;
763 decoded = decode_rx_desc_ptype(ptype);
764
765 skb->ip_summed = CHECKSUM_NONE;
766
767 skb_checksum_none_assert(skb);
768
769 /* Rx csum enabled and ip headers found? */
770 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
771 return;
772
773 /* did the hardware decode the packet and checksum? */
774 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
775 return;
776
777 /* both known and outer_ip must be set for the below code to work */
778 if (!(decoded.known && decoded.outer_ip))
779 return;
780
781 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
782 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
783 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
784 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
785
786 if (ipv4 &&
787 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
788 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
789 goto checksum_fail;
790
791 /* likely incorrect csum if alternate IP extension headers found */
792 if (ipv6 &&
793 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
794 /* don't increment checksum err here, non-fatal err */
795 return;
796
797 /* there was some L4 error, count error and punt packet to the stack */
798 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
799 goto checksum_fail;
800
801 /* handle packets that were not able to be checksummed due
802 * to arrival speed, in this case the stack can compute
803 * the csum.
804 */
805 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
806 return;
807
808 /* If there is an outer header present that might contain a checksum
809 * we need to bump the checksum level by 1 to reflect the fact that
810 * we are indicating we validated the inner checksum.
811 */
812 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
813 skb->csum_level = 1;
814
815 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
816 switch (decoded.inner_prot) {
817 case I40E_RX_PTYPE_INNER_PROT_TCP:
818 case I40E_RX_PTYPE_INNER_PROT_UDP:
819 case I40E_RX_PTYPE_INNER_PROT_SCTP:
820 skb->ip_summed = CHECKSUM_UNNECESSARY;
821 /* fall though */
822 default:
823 break;
824 }
825
826 return;
827
828checksum_fail:
829 vsi->back->hw_csum_rx_error++;
830}
831
832/**
833 * i40e_ptype_to_htype - get a hash type
834 * @ptype: the ptype value from the descriptor
835 *
836 * Returns a hash type to be used by skb_set_hash
837 **/
838static inline int i40e_ptype_to_htype(u8 ptype)
839{
840 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
841
842 if (!decoded.known)
843 return PKT_HASH_TYPE_NONE;
844
845 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
846 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
847 return PKT_HASH_TYPE_L4;
848 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
849 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
850 return PKT_HASH_TYPE_L3;
851 else
852 return PKT_HASH_TYPE_L2;
853}
854
855/**
856 * i40e_rx_hash - set the hash value in the skb
857 * @ring: descriptor ring
858 * @rx_desc: specific descriptor
859 **/
860static inline void i40e_rx_hash(struct i40e_ring *ring,
861 union i40e_rx_desc *rx_desc,
862 struct sk_buff *skb,
863 u8 rx_ptype)
864{
865 u32 hash;
866 const __le64 rss_mask =
867 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
868 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
869
870 if (ring->netdev->features & NETIF_F_RXHASH)
871 return;
872
873 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
874 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
875 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
876 }
877}
878
879/**
880 * i40evf_process_skb_fields - Populate skb header fields from Rx descriptor
881 * @rx_ring: rx descriptor ring packet is being transacted on
882 * @rx_desc: pointer to the EOP Rx descriptor
883 * @skb: pointer to current skb being populated
884 * @rx_ptype: the packet type decoded by hardware
885 *
886 * This function checks the ring, descriptor, and packet information in
887 * order to populate the hash, checksum, VLAN, protocol, and
888 * other fields within the skb.
889 **/
890static inline
891void i40evf_process_skb_fields(struct i40e_ring *rx_ring,
892 union i40e_rx_desc *rx_desc, struct sk_buff *skb,
893 u8 rx_ptype)
894{
895 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
896
897 /* modifies the skb - consumes the enet header */
898 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
899
900 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
901
902 skb_record_rx_queue(skb, rx_ring->queue_index);
903}
904
905/**
906 * i40e_pull_tail - i40e specific version of skb_pull_tail
907 * @rx_ring: rx descriptor ring packet is being transacted on
908 * @skb: pointer to current skb being adjusted
909 *
910 * This function is an i40e specific version of __pskb_pull_tail. The
911 * main difference between this version and the original function is that
912 * this function can make several assumptions about the state of things
913 * that allow for significant optimizations versus the standard function.
914 * As a result we can do things like drop a frag and maintain an accurate
915 * truesize for the skb.
916 */
917static void i40e_pull_tail(struct i40e_ring *rx_ring, struct sk_buff *skb)
918{
919 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
920 unsigned char *va;
921 unsigned int pull_len;
922
923 /* it is valid to use page_address instead of kmap since we are
924 * working with pages allocated out of the lomem pool per
925 * alloc_page(GFP_ATOMIC)
926 */
927 va = skb_frag_address(frag);
928
929 /* we need the header to contain the greater of either ETH_HLEN or
930 * 60 bytes if the skb->len is less than 60 for skb_pad.
931 */
932 pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE);
933
934 /* align pull length to size of long to optimize memcpy performance */
935 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
936
937 /* update all of the pointers */
938 skb_frag_size_sub(frag, pull_len);
939 frag->page_offset += pull_len;
940 skb->data_len -= pull_len;
941 skb->tail += pull_len;
942}
943
944/**
945 * i40e_cleanup_headers - Correct empty headers
946 * @rx_ring: rx descriptor ring packet is being transacted on
947 * @skb: pointer to current skb being fixed
948 *
949 * Also address the case where we are pulling data in on pages only
950 * and as such no data is present in the skb header.
951 *
952 * In addition if skb is not at least 60 bytes we need to pad it so that
953 * it is large enough to qualify as a valid Ethernet frame.
954 *
955 * Returns true if an error was encountered and skb was freed.
956 **/
957static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb)
958{
959 /* place header in linear portion of buffer */
960 if (skb_is_nonlinear(skb))
961 i40e_pull_tail(rx_ring, skb);
962
963 /* if eth_skb_pad returns an error the skb was freed */
964 if (eth_skb_pad(skb))
965 return true;
966
967 return false;
968}
969
970/**
971 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
972 * @rx_ring: rx descriptor ring to store buffers on
973 * @old_buff: donor buffer to have page reused
974 *
975 * Synchronizes page for reuse by the adapter
976 **/
977static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
978 struct i40e_rx_buffer *old_buff)
979{
980 struct i40e_rx_buffer *new_buff;
981 u16 nta = rx_ring->next_to_alloc;
982
983 new_buff = &rx_ring->rx_bi[nta];
984
985 /* update, and store next to alloc */
986 nta++;
987 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
988
989 /* transfer page from old buffer to new buffer */
990 *new_buff = *old_buff;
991}
992
993/**
994 * i40e_page_is_reserved - check if reuse is possible
995 * @page: page struct to check
996 */
997static inline bool i40e_page_is_reserved(struct page *page)
998{
999 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1000}
1001
1002/**
1003 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1004 * @rx_ring: rx descriptor ring to transact packets on
1005 * @rx_buffer: buffer containing page to add
1006 * @rx_desc: descriptor containing length of buffer written by hardware
1007 * @skb: sk_buff to place the data into
1008 *
1009 * This function will add the data contained in rx_buffer->page to the skb.
1010 * This is done either through a direct copy if the data in the buffer is
1011 * less than the skb header size, otherwise it will just attach the page as
1012 * a frag to the skb.
1013 *
1014 * The function will then update the page offset if necessary and return
1015 * true if the buffer can be reused by the adapter.
1016 **/
1017static bool i40e_add_rx_frag(struct i40e_ring *rx_ring,
1018 struct i40e_rx_buffer *rx_buffer,
1019 union i40e_rx_desc *rx_desc,
1020 struct sk_buff *skb)
1021{
1022 struct page *page = rx_buffer->page;
1023 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1024 unsigned int size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1025 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1026#if (PAGE_SIZE < 8192)
1027 unsigned int truesize = I40E_RXBUFFER_2048;
1028#else
1029 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1030 unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048;
1031#endif
1032
1033 /* will the data fit in the skb we allocated? if so, just
1034 * copy it as it is pretty small anyway
1035 */
1036 if ((size <= I40E_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1037 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1038
1039 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1040
1041 /* page is not reserved, we can reuse buffer as-is */
1042 if (likely(!i40e_page_is_reserved(page)))
1043 return true;
1044
1045 /* this page cannot be reused so discard it */
1046 __free_pages(page, 0);
1047 return false;
1048 }
1049
1050 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1051 rx_buffer->page_offset, size, truesize);
1052
1053 /* avoid re-using remote pages */
1054 if (unlikely(i40e_page_is_reserved(page)))
1055 return false;
1056
1057#if (PAGE_SIZE < 8192)
1058 /* if we are only owner of page we can reuse it */
1059 if (unlikely(page_count(page) != 1))
1060 return false;
1061
1062 /* flip page offset to other buffer */
1063 rx_buffer->page_offset ^= truesize;
1064#else
1065 /* move offset up to the next cache line */
1066 rx_buffer->page_offset += truesize;
1067
1068 if (rx_buffer->page_offset > last_offset)
1069 return false;
1070#endif
1071
1072 /* Even if we own the page, we are not allowed to use atomic_set()
1073 * This would break get_page_unless_zero() users.
1074 */
1075 get_page(rx_buffer->page);
1076
1077 return true;
1078}
1079
1080/**
1081 * i40evf_fetch_rx_buffer - Allocate skb and populate it
1082 * @rx_ring: rx descriptor ring to transact packets on
1083 * @rx_desc: descriptor containing info written by hardware
1084 *
1085 * This function allocates an skb on the fly, and populates it with the page
1086 * data from the current receive descriptor, taking care to set up the skb
1087 * correctly, as well as handling calling the page recycle function if
1088 * necessary.
1089 */
1090static inline
1091struct sk_buff *i40evf_fetch_rx_buffer(struct i40e_ring *rx_ring,
1092 union i40e_rx_desc *rx_desc)
1093{
1094 struct i40e_rx_buffer *rx_buffer;
1095 struct sk_buff *skb;
1096 struct page *page;
1097
1098 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
1099 page = rx_buffer->page;
1100 prefetchw(page);
1101
1102 skb = rx_buffer->skb;
1103
1104 if (likely(!skb)) {
1105 void *page_addr = page_address(page) + rx_buffer->page_offset;
1106
1107 /* prefetch first cache line of first page */
1108 prefetch(page_addr);
1109#if L1_CACHE_BYTES < 128
1110 prefetch(page_addr + L1_CACHE_BYTES);
1111#endif
1112
1113 /* allocate a skb to store the frags */
1114 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
1115 I40E_RX_HDR_SIZE,
1116 GFP_ATOMIC | __GFP_NOWARN);
1117 if (unlikely(!skb)) {
1118 rx_ring->rx_stats.alloc_buff_failed++;
1119 return NULL;
1120 }
1121
1122 /* we will be copying header into skb->data in
1123 * pskb_may_pull so it is in our interest to prefetch
1124 * it now to avoid a possible cache miss
1125 */
1126 prefetchw(skb->data);
1127 } else {
1128 rx_buffer->skb = NULL;
1129 }
1130
1131 /* we are reusing so sync this buffer for CPU use */
1132 dma_sync_single_range_for_cpu(rx_ring->dev,
1133 rx_buffer->dma,
1134 rx_buffer->page_offset,
1135 I40E_RXBUFFER_2048,
1136 DMA_FROM_DEVICE);
1137
1138 /* pull page into skb */
1139 if (i40e_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1140 /* hand second half of page back to the ring */
1141 i40e_reuse_rx_page(rx_ring, rx_buffer);
1142 rx_ring->rx_stats.page_reuse_count++;
1143 } else {
1144 /* we are not reusing the buffer so unmap it */
1145 dma_unmap_page(rx_ring->dev, rx_buffer->dma, PAGE_SIZE,
1146 DMA_FROM_DEVICE);
1147 }
1148
1149 /* clear contents of buffer_info */
1150 rx_buffer->page = NULL;
1151
1152 return skb;
1153}
1154
1155/**
1156 * i40e_is_non_eop - process handling of non-EOP buffers
1157 * @rx_ring: Rx ring being processed
1158 * @rx_desc: Rx descriptor for current buffer
1159 * @skb: Current socket buffer containing buffer in progress
1160 *
1161 * This function updates next to clean. If the buffer is an EOP buffer
1162 * this function exits returning false, otherwise it will place the
1163 * sk_buff in the next buffer to be chained and return true indicating
1164 * that this is in fact a non-EOP buffer.
1165 **/
1166static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
1167 union i40e_rx_desc *rx_desc,
1168 struct sk_buff *skb)
1169{
1170 u32 ntc = rx_ring->next_to_clean + 1;
1171
1172 /* fetch, update, and store next to clean */
1173 ntc = (ntc < rx_ring->count) ? ntc : 0;
1174 rx_ring->next_to_clean = ntc;
1175
1176 prefetch(I40E_RX_DESC(rx_ring, ntc));
1177
1178 /* if we are the last buffer then there is nothing else to do */
1179#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
1180 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
1181 return false;
1182
1183 /* place skb in next buffer to be received */
1184 rx_ring->rx_bi[ntc].skb = skb;
1185 rx_ring->rx_stats.non_eop_descs++;
1186
1187 return true;
1188}
1189
1190/**
1191 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1192 * @rx_ring: rx descriptor ring to transact packets on
1193 * @budget: Total limit on number of packets to process
1194 *
1195 * This function provides a "bounce buffer" approach to Rx interrupt
1196 * processing. The advantage to this is that on systems that have
1197 * expensive overhead for IOMMU access this provides a means of avoiding
1198 * it by maintaining the mapping of the page to the system.
1199 *
1200 * Returns amount of work completed
1201 **/
1202static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
1203{
1204 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1205 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1206 bool failure = false;
1207
1208 while (likely(total_rx_packets < budget)) {
1209 union i40e_rx_desc *rx_desc;
1210 struct sk_buff *skb;
1211 u16 vlan_tag;
1212 u8 rx_ptype;
1213 u64 qword;
1214
1215 /* return some buffers to hardware, one at a time is too slow */
1216 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1217 failure = failure ||
1218 i40evf_alloc_rx_buffers(rx_ring, cleaned_count);
1219 cleaned_count = 0;
1220 }
1221
1222 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
1223
1224 /* status_error_len will always be zero for unused descriptors
1225 * because it's cleared in cleanup, and overlaps with hdr_addr
1226 * which is always zero because packet split isn't used, if the
1227 * hardware wrote DD then it will be non-zero
1228 */
1229 if (!i40e_test_staterr(rx_desc,
1230 BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1231 break;
1232
1233 /* This memory barrier is needed to keep us from reading
1234 * any other fields out of the rx_desc until we know the
1235 * DD bit is set.
1236 */
1237 dma_rmb();
1238
1239 skb = i40evf_fetch_rx_buffer(rx_ring, rx_desc);
1240 if (!skb)
1241 break;
1242
1243 cleaned_count++;
1244
1245 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
1246 continue;
1247
1248 /* ERR_MASK will only have valid bits if EOP set, and
1249 * what we are doing here is actually checking
1250 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1251 * the error field
1252 */
1253 if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1254 dev_kfree_skb_any(skb);
1255 continue;
1256 }
1257
1258 if (i40e_cleanup_headers(rx_ring, skb))
1259 continue;
1260
1261 /* probably a little skewed due to removing CRC */
1262 total_rx_bytes += skb->len;
1263
1264 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1265 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1266 I40E_RXD_QW1_PTYPE_SHIFT;
1267
1268 /* populate checksum, VLAN, and protocol */
1269 i40evf_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
1270
1271
1272 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1273 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0;
1274
1275 i40e_receive_skb(rx_ring, skb, vlan_tag);
1276
1277 /* update budget accounting */
1278 total_rx_packets++;
1279 }
1280
1281 u64_stats_update_begin(&rx_ring->syncp);
1282 rx_ring->stats.packets += total_rx_packets;
1283 rx_ring->stats.bytes += total_rx_bytes;
1284 u64_stats_update_end(&rx_ring->syncp);
1285 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1286 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1287
1288 /* guarantee a trip back through this routine if there was a failure */
1289 return failure ? budget : total_rx_packets;
1290}
1291
1292static u32 i40e_buildreg_itr(const int type, const u16 itr)
1293{
1294 u32 val;
1295
1296 val = I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1297 /* Don't clear PBA because that can cause lost interrupts that
1298 * came in while we were cleaning/polling
1299 */
1300 (type << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1301 (itr << I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT);
1302
1303 return val;
1304}
1305
1306/* a small macro to shorten up some long lines */
1307#define INTREG I40E_VFINT_DYN_CTLN1
1308static inline int get_rx_itr_enabled(struct i40e_vsi *vsi, int idx)
1309{
1310 struct i40evf_adapter *adapter = vsi->back;
1311
1312 return !!(adapter->rx_rings[idx].rx_itr_setting);
1313}
1314
1315static inline int get_tx_itr_enabled(struct i40e_vsi *vsi, int idx)
1316{
1317 struct i40evf_adapter *adapter = vsi->back;
1318
1319 return !!(adapter->tx_rings[idx].tx_itr_setting);
1320}
1321
1322/**
1323 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1324 * @vsi: the VSI we care about
1325 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1326 *
1327 **/
1328static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1329 struct i40e_q_vector *q_vector)
1330{
1331 struct i40e_hw *hw = &vsi->back->hw;
1332 bool rx = false, tx = false;
1333 u32 rxval, txval;
1334 int vector;
1335 int idx = q_vector->v_idx;
1336 int rx_itr_setting, tx_itr_setting;
1337
1338 vector = (q_vector->v_idx + vsi->base_vector);
1339
1340 /* avoid dynamic calculation if in countdown mode OR if
1341 * all dynamic is disabled
1342 */
1343 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1344
1345 rx_itr_setting = get_rx_itr_enabled(vsi, idx);
1346 tx_itr_setting = get_tx_itr_enabled(vsi, idx);
1347
1348 if (q_vector->itr_countdown > 0 ||
1349 (!ITR_IS_DYNAMIC(rx_itr_setting) &&
1350 !ITR_IS_DYNAMIC(tx_itr_setting))) {
1351 goto enable_int;
1352 }
1353
1354 if (ITR_IS_DYNAMIC(rx_itr_setting)) {
1355 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1356 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1357 }
1358
1359 if (ITR_IS_DYNAMIC(tx_itr_setting)) {
1360 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1361 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1362 }
1363
1364 if (rx || tx) {
1365 /* get the higher of the two ITR adjustments and
1366 * use the same value for both ITR registers
1367 * when in adaptive mode (Rx and/or Tx)
1368 */
1369 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1370
1371 q_vector->tx.itr = q_vector->rx.itr = itr;
1372 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1373 tx = true;
1374 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1375 rx = true;
1376 }
1377
1378 /* only need to enable the interrupt once, but need
1379 * to possibly update both ITR values
1380 */
1381 if (rx) {
1382 /* set the INTENA_MSK_MASK so that this first write
1383 * won't actually enable the interrupt, instead just
1384 * updating the ITR (it's bit 31 PF and VF)
1385 */
1386 rxval |= BIT(31);
1387 /* don't check _DOWN because interrupt isn't being enabled */
1388 wr32(hw, INTREG(vector - 1), rxval);
1389 }
1390
1391enable_int:
1392 if (!test_bit(__I40E_DOWN, &vsi->state))
1393 wr32(hw, INTREG(vector - 1), txval);
1394
1395 if (q_vector->itr_countdown)
1396 q_vector->itr_countdown--;
1397 else
1398 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1399}
1400
1401/**
1402 * i40evf_napi_poll - NAPI polling Rx/Tx cleanup routine
1403 * @napi: napi struct with our devices info in it
1404 * @budget: amount of work driver is allowed to do this pass, in packets
1405 *
1406 * This function will clean all queues associated with a q_vector.
1407 *
1408 * Returns the amount of work done
1409 **/
1410int i40evf_napi_poll(struct napi_struct *napi, int budget)
1411{
1412 struct i40e_q_vector *q_vector =
1413 container_of(napi, struct i40e_q_vector, napi);
1414 struct i40e_vsi *vsi = q_vector->vsi;
1415 struct i40e_ring *ring;
1416 bool clean_complete = true;
1417 bool arm_wb = false;
1418 int budget_per_ring;
1419 int work_done = 0;
1420
1421 if (test_bit(__I40E_DOWN, &vsi->state)) {
1422 napi_complete(napi);
1423 return 0;
1424 }
1425
1426 /* Since the actual Tx work is minimal, we can give the Tx a larger
1427 * budget and be more aggressive about cleaning up the Tx descriptors.
1428 */
1429 i40e_for_each_ring(ring, q_vector->tx) {
1430 if (!i40e_clean_tx_irq(vsi, ring, budget)) {
1431 clean_complete = false;
1432 continue;
1433 }
1434 arm_wb |= ring->arm_wb;
1435 ring->arm_wb = false;
1436 }
1437
1438 /* Handle case where we are called by netpoll with a budget of 0 */
1439 if (budget <= 0)
1440 goto tx_only;
1441
1442 /* We attempt to distribute budget to each Rx queue fairly, but don't
1443 * allow the budget to go below 1 because that would exit polling early.
1444 */
1445 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1446
1447 i40e_for_each_ring(ring, q_vector->rx) {
1448 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring);
1449
1450 work_done += cleaned;
1451 /* if we clean as many as budgeted, we must not be done */
1452 if (cleaned >= budget_per_ring)
1453 clean_complete = false;
1454 }
1455
1456 /* If work not completed, return budget and polling will return */
1457 if (!clean_complete) {
1458 const cpumask_t *aff_mask = &q_vector->affinity_mask;
1459 int cpu_id = smp_processor_id();
1460
1461 /* It is possible that the interrupt affinity has changed but,
1462 * if the cpu is pegged at 100%, polling will never exit while
1463 * traffic continues and the interrupt will be stuck on this
1464 * cpu. We check to make sure affinity is correct before we
1465 * continue to poll, otherwise we must stop polling so the
1466 * interrupt can move to the correct cpu.
1467 */
1468 if (likely(cpumask_test_cpu(cpu_id, aff_mask))) {
1469tx_only:
1470 if (arm_wb) {
1471 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
1472 i40e_enable_wb_on_itr(vsi, q_vector);
1473 }
1474 return budget;
1475 }
1476 }
1477
1478 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
1479 q_vector->arm_wb_state = false;
1480
1481 /* Work is done so exit the polling mode and re-enable the interrupt */
1482 napi_complete_done(napi, work_done);
1483
1484 /* If we're prematurely stopping polling to fix the interrupt
1485 * affinity we want to make sure polling starts back up so we
1486 * issue a call to i40evf_force_wb which triggers a SW interrupt.
1487 */
1488 if (!clean_complete)
1489 i40evf_force_wb(vsi, q_vector);
1490 else
1491 i40e_update_enable_itr(vsi, q_vector);
1492
1493 return min(work_done, budget - 1);
1494}
1495
1496/**
1497 * i40evf_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
1498 * @skb: send buffer
1499 * @tx_ring: ring to send buffer on
1500 * @flags: the tx flags to be set
1501 *
1502 * Checks the skb and set up correspondingly several generic transmit flags
1503 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
1504 *
1505 * Returns error code indicate the frame should be dropped upon error and the
1506 * otherwise returns 0 to indicate the flags has been set properly.
1507 **/
1508static inline int i40evf_tx_prepare_vlan_flags(struct sk_buff *skb,
1509 struct i40e_ring *tx_ring,
1510 u32 *flags)
1511{
1512 __be16 protocol = skb->protocol;
1513 u32 tx_flags = 0;
1514
1515 if (protocol == htons(ETH_P_8021Q) &&
1516 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
1517 /* When HW VLAN acceleration is turned off by the user the
1518 * stack sets the protocol to 8021q so that the driver
1519 * can take any steps required to support the SW only
1520 * VLAN handling. In our case the driver doesn't need
1521 * to take any further steps so just set the protocol
1522 * to the encapsulated ethertype.
1523 */
1524 skb->protocol = vlan_get_protocol(skb);
1525 goto out;
1526 }
1527
1528 /* if we have a HW VLAN tag being added, default to the HW one */
1529 if (skb_vlan_tag_present(skb)) {
1530 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
1531 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
1532 /* else if it is a SW VLAN, check the next protocol and store the tag */
1533 } else if (protocol == htons(ETH_P_8021Q)) {
1534 struct vlan_hdr *vhdr, _vhdr;
1535
1536 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
1537 if (!vhdr)
1538 return -EINVAL;
1539
1540 protocol = vhdr->h_vlan_encapsulated_proto;
1541 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
1542 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
1543 }
1544
1545out:
1546 *flags = tx_flags;
1547 return 0;
1548}
1549
1550/**
1551 * i40e_tso - set up the tso context descriptor
1552 * @skb: ptr to the skb we're sending
1553 * @hdr_len: ptr to the size of the packet header
1554 * @cd_type_cmd_tso_mss: Quad Word 1
1555 *
1556 * Returns 0 if no TSO can happen, 1 if tso is going, or error
1557 **/
1558static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
1559{
1560 u64 cd_cmd, cd_tso_len, cd_mss;
1561 union {
1562 struct iphdr *v4;
1563 struct ipv6hdr *v6;
1564 unsigned char *hdr;
1565 } ip;
1566 union {
1567 struct tcphdr *tcp;
1568 struct udphdr *udp;
1569 unsigned char *hdr;
1570 } l4;
1571 u32 paylen, l4_offset;
1572 int err;
1573
1574 if (skb->ip_summed != CHECKSUM_PARTIAL)
1575 return 0;
1576
1577 if (!skb_is_gso(skb))
1578 return 0;
1579
1580 err = skb_cow_head(skb, 0);
1581 if (err < 0)
1582 return err;
1583
1584 ip.hdr = skb_network_header(skb);
1585 l4.hdr = skb_transport_header(skb);
1586
1587 /* initialize outer IP header fields */
1588 if (ip.v4->version == 4) {
1589 ip.v4->tot_len = 0;
1590 ip.v4->check = 0;
1591 } else {
1592 ip.v6->payload_len = 0;
1593 }
1594
1595 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
1596 SKB_GSO_GRE_CSUM |
1597 SKB_GSO_IPXIP4 |
1598 SKB_GSO_IPXIP6 |
1599 SKB_GSO_UDP_TUNNEL |
1600 SKB_GSO_UDP_TUNNEL_CSUM)) {
1601 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1602 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
1603 l4.udp->len = 0;
1604
1605 /* determine offset of outer transport header */
1606 l4_offset = l4.hdr - skb->data;
1607
1608 /* remove payload length from outer checksum */
1609 paylen = skb->len - l4_offset;
1610 csum_replace_by_diff(&l4.udp->check, htonl(paylen));
1611 }
1612
1613 /* reset pointers to inner headers */
1614 ip.hdr = skb_inner_network_header(skb);
1615 l4.hdr = skb_inner_transport_header(skb);
1616
1617 /* initialize inner IP header fields */
1618 if (ip.v4->version == 4) {
1619 ip.v4->tot_len = 0;
1620 ip.v4->check = 0;
1621 } else {
1622 ip.v6->payload_len = 0;
1623 }
1624 }
1625
1626 /* determine offset of inner transport header */
1627 l4_offset = l4.hdr - skb->data;
1628
1629 /* remove payload length from inner checksum */
1630 paylen = skb->len - l4_offset;
1631 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
1632
1633 /* compute length of segmentation header */
1634 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
1635
1636 /* find the field values */
1637 cd_cmd = I40E_TX_CTX_DESC_TSO;
1638 cd_tso_len = skb->len - *hdr_len;
1639 cd_mss = skb_shinfo(skb)->gso_size;
1640 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1641 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1642 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
1643 return 1;
1644}
1645
1646/**
1647 * i40e_tx_enable_csum - Enable Tx checksum offloads
1648 * @skb: send buffer
1649 * @tx_flags: pointer to Tx flags currently set
1650 * @td_cmd: Tx descriptor command bits to set
1651 * @td_offset: Tx descriptor header offsets to set
1652 * @tx_ring: Tx descriptor ring
1653 * @cd_tunneling: ptr to context desc bits
1654 **/
1655static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
1656 u32 *td_cmd, u32 *td_offset,
1657 struct i40e_ring *tx_ring,
1658 u32 *cd_tunneling)
1659{
1660 union {
1661 struct iphdr *v4;
1662 struct ipv6hdr *v6;
1663 unsigned char *hdr;
1664 } ip;
1665 union {
1666 struct tcphdr *tcp;
1667 struct udphdr *udp;
1668 unsigned char *hdr;
1669 } l4;
1670 unsigned char *exthdr;
1671 u32 offset, cmd = 0;
1672 __be16 frag_off;
1673 u8 l4_proto = 0;
1674
1675 if (skb->ip_summed != CHECKSUM_PARTIAL)
1676 return 0;
1677
1678 ip.hdr = skb_network_header(skb);
1679 l4.hdr = skb_transport_header(skb);
1680
1681 /* compute outer L2 header size */
1682 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
1683
1684 if (skb->encapsulation) {
1685 u32 tunnel = 0;
1686 /* define outer network header type */
1687 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1688 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1689 I40E_TX_CTX_EXT_IP_IPV4 :
1690 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
1691
1692 l4_proto = ip.v4->protocol;
1693 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1694 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
1695
1696 exthdr = ip.hdr + sizeof(*ip.v6);
1697 l4_proto = ip.v6->nexthdr;
1698 if (l4.hdr != exthdr)
1699 ipv6_skip_exthdr(skb, exthdr - skb->data,
1700 &l4_proto, &frag_off);
1701 }
1702
1703 /* define outer transport */
1704 switch (l4_proto) {
1705 case IPPROTO_UDP:
1706 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
1707 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1708 break;
1709 case IPPROTO_GRE:
1710 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
1711 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1712 break;
1713 case IPPROTO_IPIP:
1714 case IPPROTO_IPV6:
1715 *tx_flags |= I40E_TX_FLAGS_VXLAN_TUNNEL;
1716 l4.hdr = skb_inner_network_header(skb);
1717 break;
1718 default:
1719 if (*tx_flags & I40E_TX_FLAGS_TSO)
1720 return -1;
1721
1722 skb_checksum_help(skb);
1723 return 0;
1724 }
1725
1726 /* compute outer L3 header size */
1727 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
1728 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
1729
1730 /* switch IP header pointer from outer to inner header */
1731 ip.hdr = skb_inner_network_header(skb);
1732
1733 /* compute tunnel header size */
1734 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
1735 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
1736
1737 /* indicate if we need to offload outer UDP header */
1738 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
1739 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
1740 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
1741 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
1742
1743 /* record tunnel offload values */
1744 *cd_tunneling |= tunnel;
1745
1746 /* switch L4 header pointer from outer to inner */
1747 l4.hdr = skb_inner_transport_header(skb);
1748 l4_proto = 0;
1749
1750 /* reset type as we transition from outer to inner headers */
1751 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
1752 if (ip.v4->version == 4)
1753 *tx_flags |= I40E_TX_FLAGS_IPV4;
1754 if (ip.v6->version == 6)
1755 *tx_flags |= I40E_TX_FLAGS_IPV6;
1756 }
1757
1758 /* Enable IP checksum offloads */
1759 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
1760 l4_proto = ip.v4->protocol;
1761 /* the stack computes the IP header already, the only time we
1762 * need the hardware to recompute it is in the case of TSO.
1763 */
1764 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
1765 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
1766 I40E_TX_DESC_CMD_IIPT_IPV4;
1767 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
1768 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
1769
1770 exthdr = ip.hdr + sizeof(*ip.v6);
1771 l4_proto = ip.v6->nexthdr;
1772 if (l4.hdr != exthdr)
1773 ipv6_skip_exthdr(skb, exthdr - skb->data,
1774 &l4_proto, &frag_off);
1775 }
1776
1777 /* compute inner L3 header size */
1778 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
1779
1780 /* Enable L4 checksum offloads */
1781 switch (l4_proto) {
1782 case IPPROTO_TCP:
1783 /* enable checksum offloads */
1784 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
1785 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1786 break;
1787 case IPPROTO_SCTP:
1788 /* enable SCTP checksum offload */
1789 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
1790 offset |= (sizeof(struct sctphdr) >> 2) <<
1791 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1792 break;
1793 case IPPROTO_UDP:
1794 /* enable UDP checksum offload */
1795 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
1796 offset |= (sizeof(struct udphdr) >> 2) <<
1797 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1798 break;
1799 default:
1800 if (*tx_flags & I40E_TX_FLAGS_TSO)
1801 return -1;
1802 skb_checksum_help(skb);
1803 return 0;
1804 }
1805
1806 *td_cmd |= cmd;
1807 *td_offset |= offset;
1808
1809 return 1;
1810}
1811
1812/**
1813 * i40e_create_tx_ctx Build the Tx context descriptor
1814 * @tx_ring: ring to create the descriptor on
1815 * @cd_type_cmd_tso_mss: Quad Word 1
1816 * @cd_tunneling: Quad Word 0 - bits 0-31
1817 * @cd_l2tag2: Quad Word 0 - bits 32-63
1818 **/
1819static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
1820 const u64 cd_type_cmd_tso_mss,
1821 const u32 cd_tunneling, const u32 cd_l2tag2)
1822{
1823 struct i40e_tx_context_desc *context_desc;
1824 int i = tx_ring->next_to_use;
1825
1826 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
1827 !cd_tunneling && !cd_l2tag2)
1828 return;
1829
1830 /* grab the next descriptor */
1831 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
1832
1833 i++;
1834 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
1835
1836 /* cpu_to_le32 and assign to struct fields */
1837 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
1838 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
1839 context_desc->rsvd = cpu_to_le16(0);
1840 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
1841}
1842
1843/**
1844 * __i40evf_chk_linearize - Check if there are more than 8 buffers per packet
1845 * @skb: send buffer
1846 *
1847 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
1848 * and so we need to figure out the cases where we need to linearize the skb.
1849 *
1850 * For TSO we need to count the TSO header and segment payload separately.
1851 * As such we need to check cases where we have 7 fragments or more as we
1852 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
1853 * the segment payload in the first descriptor, and another 7 for the
1854 * fragments.
1855 **/
1856bool __i40evf_chk_linearize(struct sk_buff *skb)
1857{
1858 const struct skb_frag_struct *frag, *stale;
1859 int nr_frags, sum;
1860
1861 /* no need to check if number of frags is less than 7 */
1862 nr_frags = skb_shinfo(skb)->nr_frags;
1863 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
1864 return false;
1865
1866 /* We need to walk through the list and validate that each group
1867 * of 6 fragments totals at least gso_size.
1868 */
1869 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
1870 frag = &skb_shinfo(skb)->frags[0];
1871
1872 /* Initialize size to the negative value of gso_size minus 1. We
1873 * use this as the worst case scenerio in which the frag ahead
1874 * of us only provides one byte which is why we are limited to 6
1875 * descriptors for a single transmit as the header and previous
1876 * fragment are already consuming 2 descriptors.
1877 */
1878 sum = 1 - skb_shinfo(skb)->gso_size;
1879
1880 /* Add size of frags 0 through 4 to create our initial sum */
1881 sum += skb_frag_size(frag++);
1882 sum += skb_frag_size(frag++);
1883 sum += skb_frag_size(frag++);
1884 sum += skb_frag_size(frag++);
1885 sum += skb_frag_size(frag++);
1886
1887 /* Walk through fragments adding latest fragment, testing it, and
1888 * then removing stale fragments from the sum.
1889 */
1890 stale = &skb_shinfo(skb)->frags[0];
1891 for (;;) {
1892 sum += skb_frag_size(frag++);
1893
1894 /* if sum is negative we failed to make sufficient progress */
1895 if (sum < 0)
1896 return true;
1897
1898 if (!nr_frags--)
1899 break;
1900
1901 sum -= skb_frag_size(stale++);
1902 }
1903
1904 return false;
1905}
1906
1907/**
1908 * __i40evf_maybe_stop_tx - 2nd level check for tx stop conditions
1909 * @tx_ring: the ring to be checked
1910 * @size: the size buffer we want to assure is available
1911 *
1912 * Returns -EBUSY if a stop is needed, else 0
1913 **/
1914int __i40evf_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
1915{
1916 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
1917 /* Memory barrier before checking head and tail */
1918 smp_mb();
1919
1920 /* Check again in a case another CPU has just made room available. */
1921 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
1922 return -EBUSY;
1923
1924 /* A reprieve! - use start_queue because it doesn't call schedule */
1925 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
1926 ++tx_ring->tx_stats.restart_queue;
1927 return 0;
1928}
1929
1930/**
1931 * i40evf_tx_map - Build the Tx descriptor
1932 * @tx_ring: ring to send buffer on
1933 * @skb: send buffer
1934 * @first: first buffer info buffer to use
1935 * @tx_flags: collected send information
1936 * @hdr_len: size of the packet header
1937 * @td_cmd: the command field in the descriptor
1938 * @td_offset: offset for checksum or crc
1939 **/
1940static inline void i40evf_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
1941 struct i40e_tx_buffer *first, u32 tx_flags,
1942 const u8 hdr_len, u32 td_cmd, u32 td_offset)
1943{
1944 unsigned int data_len = skb->data_len;
1945 unsigned int size = skb_headlen(skb);
1946 struct skb_frag_struct *frag;
1947 struct i40e_tx_buffer *tx_bi;
1948 struct i40e_tx_desc *tx_desc;
1949 u16 i = tx_ring->next_to_use;
1950 u32 td_tag = 0;
1951 dma_addr_t dma;
1952 u16 gso_segs;
1953 u16 desc_count = 1;
1954
1955 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
1956 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1957 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
1958 I40E_TX_FLAGS_VLAN_SHIFT;
1959 }
1960
1961 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
1962 gso_segs = skb_shinfo(skb)->gso_segs;
1963 else
1964 gso_segs = 1;
1965
1966 /* multiply data chunks by size of headers */
1967 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
1968 first->gso_segs = gso_segs;
1969 first->skb = skb;
1970 first->tx_flags = tx_flags;
1971
1972 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
1973
1974 tx_desc = I40E_TX_DESC(tx_ring, i);
1975 tx_bi = first;
1976
1977 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
1978 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
1979
1980 if (dma_mapping_error(tx_ring->dev, dma))
1981 goto dma_error;
1982
1983 /* record length, and DMA address */
1984 dma_unmap_len_set(tx_bi, len, size);
1985 dma_unmap_addr_set(tx_bi, dma, dma);
1986
1987 /* align size to end of page */
1988 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
1989 tx_desc->buffer_addr = cpu_to_le64(dma);
1990
1991 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
1992 tx_desc->cmd_type_offset_bsz =
1993 build_ctob(td_cmd, td_offset,
1994 max_data, td_tag);
1995
1996 tx_desc++;
1997 i++;
1998 desc_count++;
1999
2000 if (i == tx_ring->count) {
2001 tx_desc = I40E_TX_DESC(tx_ring, 0);
2002 i = 0;
2003 }
2004
2005 dma += max_data;
2006 size -= max_data;
2007
2008 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
2009 tx_desc->buffer_addr = cpu_to_le64(dma);
2010 }
2011
2012 if (likely(!data_len))
2013 break;
2014
2015 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2016 size, td_tag);
2017
2018 tx_desc++;
2019 i++;
2020 desc_count++;
2021
2022 if (i == tx_ring->count) {
2023 tx_desc = I40E_TX_DESC(tx_ring, 0);
2024 i = 0;
2025 }
2026
2027 size = skb_frag_size(frag);
2028 data_len -= size;
2029
2030 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2031 DMA_TO_DEVICE);
2032
2033 tx_bi = &tx_ring->tx_bi[i];
2034 }
2035
2036 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
2037
2038 i++;
2039 if (i == tx_ring->count)
2040 i = 0;
2041
2042 tx_ring->next_to_use = i;
2043
2044 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2045
2046 /* write last descriptor with EOP bit */
2047 td_cmd |= I40E_TX_DESC_CMD_EOP;
2048
2049 /* We can OR these values together as they both are checked against
2050 * 4 below and at this point desc_count will be used as a boolean value
2051 * after this if/else block.
2052 */
2053 desc_count |= ++tx_ring->packet_stride;
2054
2055 /* Algorithm to optimize tail and RS bit setting:
2056 * if queue is stopped
2057 * mark RS bit
2058 * reset packet counter
2059 * else if xmit_more is supported and is true
2060 * advance packet counter to 4
2061 * reset desc_count to 0
2062 *
2063 * if desc_count >= 4
2064 * mark RS bit
2065 * reset packet counter
2066 * if desc_count > 0
2067 * update tail
2068 *
2069 * Note: If there are less than 4 descriptors
2070 * pending and interrupts were disabled the service task will
2071 * trigger a force WB.
2072 */
2073 if (netif_xmit_stopped(txring_txq(tx_ring))) {
2074 goto do_rs;
2075 } else if (skb->xmit_more) {
2076 /* set stride to arm on next packet and reset desc_count */
2077 tx_ring->packet_stride = WB_STRIDE;
2078 desc_count = 0;
2079 } else if (desc_count >= WB_STRIDE) {
2080do_rs:
2081 /* write last descriptor with RS bit set */
2082 td_cmd |= I40E_TX_DESC_CMD_RS;
2083 tx_ring->packet_stride = 0;
2084 }
2085
2086 tx_desc->cmd_type_offset_bsz =
2087 build_ctob(td_cmd, td_offset, size, td_tag);
2088
2089 /* Force memory writes to complete before letting h/w know there
2090 * are new descriptors to fetch.
2091 *
2092 * We also use this memory barrier to make certain all of the
2093 * status bits have been updated before next_to_watch is written.
2094 */
2095 wmb();
2096
2097 /* set next_to_watch value indicating a packet is present */
2098 first->next_to_watch = tx_desc;
2099
2100 /* notify HW of packet */
2101 if (desc_count) {
2102 writel(i, tx_ring->tail);
2103
2104 /* we need this if more than one processor can write to our tail
2105 * at a time, it synchronizes IO on IA64/Altix systems
2106 */
2107 mmiowb();
2108 }
2109
2110 return;
2111
2112dma_error:
2113 dev_info(tx_ring->dev, "TX DMA map failed\n");
2114
2115 /* clear dma mappings for failed tx_bi map */
2116 for (;;) {
2117 tx_bi = &tx_ring->tx_bi[i];
2118 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2119 if (tx_bi == first)
2120 break;
2121 if (i == 0)
2122 i = tx_ring->count;
2123 i--;
2124 }
2125
2126 tx_ring->next_to_use = i;
2127}
2128
2129/**
2130 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2131 * @skb: send buffer
2132 * @tx_ring: ring to send buffer on
2133 *
2134 * Returns NETDEV_TX_OK if sent, else an error code
2135 **/
2136static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2137 struct i40e_ring *tx_ring)
2138{
2139 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2140 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2141 struct i40e_tx_buffer *first;
2142 u32 td_offset = 0;
2143 u32 tx_flags = 0;
2144 __be16 protocol;
2145 u32 td_cmd = 0;
2146 u8 hdr_len = 0;
2147 int tso, count;
2148
2149 /* prefetch the data, we'll need it later */
2150 prefetch(skb->data);
2151
2152 count = i40e_xmit_descriptor_count(skb);
2153 if (i40e_chk_linearize(skb, count)) {
2154 if (__skb_linearize(skb))
2155 goto out_drop;
2156 count = i40e_txd_use_count(skb->len);
2157 tx_ring->tx_stats.tx_linearize++;
2158 }
2159
2160 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2161 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2162 * + 4 desc gap to avoid the cache line where head is,
2163 * + 1 desc for context descriptor,
2164 * otherwise try next time
2165 */
2166 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2167 tx_ring->tx_stats.tx_busy++;
2168 return NETDEV_TX_BUSY;
2169 }
2170
2171 /* prepare the xmit flags */
2172 if (i40evf_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2173 goto out_drop;
2174
2175 /* obtain protocol of skb */
2176 protocol = vlan_get_protocol(skb);
2177
2178 /* record the location of the first descriptor for this packet */
2179 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2180
2181 /* setup IPv4/IPv6 offloads */
2182 if (protocol == htons(ETH_P_IP))
2183 tx_flags |= I40E_TX_FLAGS_IPV4;
2184 else if (protocol == htons(ETH_P_IPV6))
2185 tx_flags |= I40E_TX_FLAGS_IPV6;
2186
2187 tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss);
2188
2189 if (tso < 0)
2190 goto out_drop;
2191 else if (tso)
2192 tx_flags |= I40E_TX_FLAGS_TSO;
2193
2194 /* Always offload the checksum, since it's in the data descriptor */
2195 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2196 tx_ring, &cd_tunneling);
2197 if (tso < 0)
2198 goto out_drop;
2199
2200 skb_tx_timestamp(skb);
2201
2202 /* always enable CRC insertion offload */
2203 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2204
2205 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2206 cd_tunneling, cd_l2tag2);
2207
2208 i40evf_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2209 td_cmd, td_offset);
2210
2211 return NETDEV_TX_OK;
2212
2213out_drop:
2214 dev_kfree_skb_any(skb);
2215 return NETDEV_TX_OK;
2216}
2217
2218/**
2219 * i40evf_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2220 * @skb: send buffer
2221 * @netdev: network interface device structure
2222 *
2223 * Returns NETDEV_TX_OK if sent, else an error code
2224 **/
2225netdev_tx_t i40evf_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2226{
2227 struct i40evf_adapter *adapter = netdev_priv(netdev);
2228 struct i40e_ring *tx_ring = &adapter->tx_rings[skb->queue_mapping];
2229
2230 /* hardware can't handle really short frames, hardware padding works
2231 * beyond this point
2232 */
2233 if (unlikely(skb->len < I40E_MIN_TX_LEN)) {
2234 if (skb_pad(skb, I40E_MIN_TX_LEN - skb->len))
2235 return NETDEV_TX_OK;
2236 skb->len = I40E_MIN_TX_LEN;
2237 skb_set_tail_pointer(skb, I40E_MIN_TX_LEN);
2238 }
2239
2240 return i40e_xmit_frame_ring(skb, tx_ring);
2241}