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1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29
30#include <drm/radeon_drm.h>
31
32#include "atom.h"
33#include "cayman_blit_shaders.h"
34#include "clearstate_cayman.h"
35#include "evergreen.h"
36#include "ni.h"
37#include "ni_reg.h"
38#include "nid.h"
39#include "radeon.h"
40#include "radeon_asic.h"
41#include "radeon_audio.h"
42#include "radeon_ucode.h"
43
44/*
45 * Indirect registers accessor
46 */
47u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
48{
49 unsigned long flags;
50 u32 r;
51
52 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
53 WREG32(TN_SMC_IND_INDEX_0, (reg));
54 r = RREG32(TN_SMC_IND_DATA_0);
55 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
56 return r;
57}
58
59void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
60{
61 unsigned long flags;
62
63 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
64 WREG32(TN_SMC_IND_INDEX_0, (reg));
65 WREG32(TN_SMC_IND_DATA_0, (v));
66 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
67}
68
69static const u32 tn_rlc_save_restore_register_list[] = {
70 0x98fc,
71 0x98f0,
72 0x9834,
73 0x9838,
74 0x9870,
75 0x9874,
76 0x8a14,
77 0x8b24,
78 0x8bcc,
79 0x8b10,
80 0x8c30,
81 0x8d00,
82 0x8d04,
83 0x8c00,
84 0x8c04,
85 0x8c10,
86 0x8c14,
87 0x8d8c,
88 0x8cf0,
89 0x8e38,
90 0x9508,
91 0x9688,
92 0x9608,
93 0x960c,
94 0x9610,
95 0x9614,
96 0x88c4,
97 0x8978,
98 0x88d4,
99 0x900c,
100 0x9100,
101 0x913c,
102 0x90e8,
103 0x9354,
104 0xa008,
105 0x98f8,
106 0x9148,
107 0x914c,
108 0x3f94,
109 0x98f4,
110 0x9b7c,
111 0x3f8c,
112 0x8950,
113 0x8954,
114 0x8a18,
115 0x8b28,
116 0x9144,
117 0x3f90,
118 0x915c,
119 0x9160,
120 0x9178,
121 0x917c,
122 0x9180,
123 0x918c,
124 0x9190,
125 0x9194,
126 0x9198,
127 0x919c,
128 0x91a8,
129 0x91ac,
130 0x91b0,
131 0x91b4,
132 0x91b8,
133 0x91c4,
134 0x91c8,
135 0x91cc,
136 0x91d0,
137 0x91d4,
138 0x91e0,
139 0x91e4,
140 0x91ec,
141 0x91f0,
142 0x91f4,
143 0x9200,
144 0x9204,
145 0x929c,
146 0x8030,
147 0x9150,
148 0x9a60,
149 0x920c,
150 0x9210,
151 0x9228,
152 0x922c,
153 0x9244,
154 0x9248,
155 0x91e8,
156 0x9294,
157 0x9208,
158 0x9224,
159 0x9240,
160 0x9220,
161 0x923c,
162 0x9258,
163 0x9744,
164 0xa200,
165 0xa204,
166 0xa208,
167 0xa20c,
168 0x8d58,
169 0x9030,
170 0x9034,
171 0x9038,
172 0x903c,
173 0x9040,
174 0x9654,
175 0x897c,
176 0xa210,
177 0xa214,
178 0x9868,
179 0xa02c,
180 0x9664,
181 0x9698,
182 0x949c,
183 0x8e10,
184 0x8e18,
185 0x8c50,
186 0x8c58,
187 0x8c60,
188 0x8c68,
189 0x89b4,
190 0x9830,
191 0x802c,
192};
193
194/* Firmware Names */
195MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
196MODULE_FIRMWARE("radeon/BARTS_me.bin");
197MODULE_FIRMWARE("radeon/BARTS_mc.bin");
198MODULE_FIRMWARE("radeon/BARTS_smc.bin");
199MODULE_FIRMWARE("radeon/BTC_rlc.bin");
200MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
201MODULE_FIRMWARE("radeon/TURKS_me.bin");
202MODULE_FIRMWARE("radeon/TURKS_mc.bin");
203MODULE_FIRMWARE("radeon/TURKS_smc.bin");
204MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
205MODULE_FIRMWARE("radeon/CAICOS_me.bin");
206MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
207MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
208MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
209MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
210MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
211MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
212MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
213MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
214MODULE_FIRMWARE("radeon/ARUBA_me.bin");
215MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
216
217
218static const u32 cayman_golden_registers2[] = {
219 0x3e5c, 0xffffffff, 0x00000000,
220 0x3e48, 0xffffffff, 0x00000000,
221 0x3e4c, 0xffffffff, 0x00000000,
222 0x3e64, 0xffffffff, 0x00000000,
223 0x3e50, 0xffffffff, 0x00000000,
224 0x3e60, 0xffffffff, 0x00000000
225};
226
227static const u32 cayman_golden_registers[] = {
228 0x5eb4, 0xffffffff, 0x00000002,
229 0x5e78, 0x8f311ff1, 0x001000f0,
230 0x3f90, 0xffff0000, 0xff000000,
231 0x9148, 0xffff0000, 0xff000000,
232 0x3f94, 0xffff0000, 0xff000000,
233 0x914c, 0xffff0000, 0xff000000,
234 0xc78, 0x00000080, 0x00000080,
235 0xbd4, 0x70073777, 0x00011003,
236 0xd02c, 0xbfffff1f, 0x08421000,
237 0xd0b8, 0x73773777, 0x02011003,
238 0x5bc0, 0x00200000, 0x50100000,
239 0x98f8, 0x33773777, 0x02011003,
240 0x98fc, 0xffffffff, 0x76541032,
241 0x7030, 0x31000311, 0x00000011,
242 0x2f48, 0x33773777, 0x42010001,
243 0x6b28, 0x00000010, 0x00000012,
244 0x7728, 0x00000010, 0x00000012,
245 0x10328, 0x00000010, 0x00000012,
246 0x10f28, 0x00000010, 0x00000012,
247 0x11b28, 0x00000010, 0x00000012,
248 0x12728, 0x00000010, 0x00000012,
249 0x240c, 0x000007ff, 0x00000000,
250 0x8a14, 0xf000001f, 0x00000007,
251 0x8b24, 0x3fff3fff, 0x00ff0fff,
252 0x8b10, 0x0000ff0f, 0x00000000,
253 0x28a4c, 0x07ffffff, 0x06000000,
254 0x10c, 0x00000001, 0x00010003,
255 0xa02c, 0xffffffff, 0x0000009b,
256 0x913c, 0x0000010f, 0x01000100,
257 0x8c04, 0xf8ff00ff, 0x40600060,
258 0x28350, 0x00000f01, 0x00000000,
259 0x9508, 0x3700001f, 0x00000002,
260 0x960c, 0xffffffff, 0x54763210,
261 0x88c4, 0x001f3ae3, 0x00000082,
262 0x88d0, 0xffffffff, 0x0f40df40,
263 0x88d4, 0x0000001f, 0x00000010,
264 0x8974, 0xffffffff, 0x00000000
265};
266
267static const u32 dvst_golden_registers2[] = {
268 0x8f8, 0xffffffff, 0,
269 0x8fc, 0x00380000, 0,
270 0x8f8, 0xffffffff, 1,
271 0x8fc, 0x0e000000, 0
272};
273
274static const u32 dvst_golden_registers[] = {
275 0x690, 0x3fff3fff, 0x20c00033,
276 0x918c, 0x0fff0fff, 0x00010006,
277 0x91a8, 0x0fff0fff, 0x00010006,
278 0x9150, 0xffffdfff, 0x6e944040,
279 0x917c, 0x0fff0fff, 0x00030002,
280 0x9198, 0x0fff0fff, 0x00030002,
281 0x915c, 0x0fff0fff, 0x00010000,
282 0x3f90, 0xffff0001, 0xff000000,
283 0x9178, 0x0fff0fff, 0x00070000,
284 0x9194, 0x0fff0fff, 0x00070000,
285 0x9148, 0xffff0001, 0xff000000,
286 0x9190, 0x0fff0fff, 0x00090008,
287 0x91ac, 0x0fff0fff, 0x00090008,
288 0x3f94, 0xffff0000, 0xff000000,
289 0x914c, 0xffff0000, 0xff000000,
290 0x929c, 0x00000fff, 0x00000001,
291 0x55e4, 0xff607fff, 0xfc000100,
292 0x8a18, 0xff000fff, 0x00000100,
293 0x8b28, 0xff000fff, 0x00000100,
294 0x9144, 0xfffc0fff, 0x00000100,
295 0x6ed8, 0x00010101, 0x00010000,
296 0x9830, 0xffffffff, 0x00000000,
297 0x9834, 0xf00fffff, 0x00000400,
298 0x9838, 0xfffffffe, 0x00000000,
299 0xd0c0, 0xff000fff, 0x00000100,
300 0xd02c, 0xbfffff1f, 0x08421000,
301 0xd0b8, 0x73773777, 0x12010001,
302 0x5bb0, 0x000000f0, 0x00000070,
303 0x98f8, 0x73773777, 0x12010001,
304 0x98fc, 0xffffffff, 0x00000010,
305 0x9b7c, 0x00ff0000, 0x00fc0000,
306 0x8030, 0x00001f0f, 0x0000100a,
307 0x2f48, 0x73773777, 0x12010001,
308 0x2408, 0x00030000, 0x000c007f,
309 0x8a14, 0xf000003f, 0x00000007,
310 0x8b24, 0x3fff3fff, 0x00ff0fff,
311 0x8b10, 0x0000ff0f, 0x00000000,
312 0x28a4c, 0x07ffffff, 0x06000000,
313 0x4d8, 0x00000fff, 0x00000100,
314 0xa008, 0xffffffff, 0x00010000,
315 0x913c, 0xffff03ff, 0x01000100,
316 0x8c00, 0x000000ff, 0x00000003,
317 0x8c04, 0xf8ff00ff, 0x40600060,
318 0x8cf0, 0x1fff1fff, 0x08e00410,
319 0x28350, 0x00000f01, 0x00000000,
320 0x9508, 0xf700071f, 0x00000002,
321 0x960c, 0xffffffff, 0x54763210,
322 0x20ef8, 0x01ff01ff, 0x00000002,
323 0x20e98, 0xfffffbff, 0x00200000,
324 0x2015c, 0xffffffff, 0x00000f40,
325 0x88c4, 0x001f3ae3, 0x00000082,
326 0x8978, 0x3fffffff, 0x04050140,
327 0x88d4, 0x0000001f, 0x00000010,
328 0x8974, 0xffffffff, 0x00000000
329};
330
331static const u32 scrapper_golden_registers[] = {
332 0x690, 0x3fff3fff, 0x20c00033,
333 0x918c, 0x0fff0fff, 0x00010006,
334 0x918c, 0x0fff0fff, 0x00010006,
335 0x91a8, 0x0fff0fff, 0x00010006,
336 0x91a8, 0x0fff0fff, 0x00010006,
337 0x9150, 0xffffdfff, 0x6e944040,
338 0x9150, 0xffffdfff, 0x6e944040,
339 0x917c, 0x0fff0fff, 0x00030002,
340 0x917c, 0x0fff0fff, 0x00030002,
341 0x9198, 0x0fff0fff, 0x00030002,
342 0x9198, 0x0fff0fff, 0x00030002,
343 0x915c, 0x0fff0fff, 0x00010000,
344 0x915c, 0x0fff0fff, 0x00010000,
345 0x3f90, 0xffff0001, 0xff000000,
346 0x3f90, 0xffff0001, 0xff000000,
347 0x9178, 0x0fff0fff, 0x00070000,
348 0x9178, 0x0fff0fff, 0x00070000,
349 0x9194, 0x0fff0fff, 0x00070000,
350 0x9194, 0x0fff0fff, 0x00070000,
351 0x9148, 0xffff0001, 0xff000000,
352 0x9148, 0xffff0001, 0xff000000,
353 0x9190, 0x0fff0fff, 0x00090008,
354 0x9190, 0x0fff0fff, 0x00090008,
355 0x91ac, 0x0fff0fff, 0x00090008,
356 0x91ac, 0x0fff0fff, 0x00090008,
357 0x3f94, 0xffff0000, 0xff000000,
358 0x3f94, 0xffff0000, 0xff000000,
359 0x914c, 0xffff0000, 0xff000000,
360 0x914c, 0xffff0000, 0xff000000,
361 0x929c, 0x00000fff, 0x00000001,
362 0x929c, 0x00000fff, 0x00000001,
363 0x55e4, 0xff607fff, 0xfc000100,
364 0x8a18, 0xff000fff, 0x00000100,
365 0x8a18, 0xff000fff, 0x00000100,
366 0x8b28, 0xff000fff, 0x00000100,
367 0x8b28, 0xff000fff, 0x00000100,
368 0x9144, 0xfffc0fff, 0x00000100,
369 0x9144, 0xfffc0fff, 0x00000100,
370 0x6ed8, 0x00010101, 0x00010000,
371 0x9830, 0xffffffff, 0x00000000,
372 0x9830, 0xffffffff, 0x00000000,
373 0x9834, 0xf00fffff, 0x00000400,
374 0x9834, 0xf00fffff, 0x00000400,
375 0x9838, 0xfffffffe, 0x00000000,
376 0x9838, 0xfffffffe, 0x00000000,
377 0xd0c0, 0xff000fff, 0x00000100,
378 0xd02c, 0xbfffff1f, 0x08421000,
379 0xd02c, 0xbfffff1f, 0x08421000,
380 0xd0b8, 0x73773777, 0x12010001,
381 0xd0b8, 0x73773777, 0x12010001,
382 0x5bb0, 0x000000f0, 0x00000070,
383 0x98f8, 0x73773777, 0x12010001,
384 0x98f8, 0x73773777, 0x12010001,
385 0x98fc, 0xffffffff, 0x00000010,
386 0x98fc, 0xffffffff, 0x00000010,
387 0x9b7c, 0x00ff0000, 0x00fc0000,
388 0x9b7c, 0x00ff0000, 0x00fc0000,
389 0x8030, 0x00001f0f, 0x0000100a,
390 0x8030, 0x00001f0f, 0x0000100a,
391 0x2f48, 0x73773777, 0x12010001,
392 0x2f48, 0x73773777, 0x12010001,
393 0x2408, 0x00030000, 0x000c007f,
394 0x8a14, 0xf000003f, 0x00000007,
395 0x8a14, 0xf000003f, 0x00000007,
396 0x8b24, 0x3fff3fff, 0x00ff0fff,
397 0x8b24, 0x3fff3fff, 0x00ff0fff,
398 0x8b10, 0x0000ff0f, 0x00000000,
399 0x8b10, 0x0000ff0f, 0x00000000,
400 0x28a4c, 0x07ffffff, 0x06000000,
401 0x28a4c, 0x07ffffff, 0x06000000,
402 0x4d8, 0x00000fff, 0x00000100,
403 0x4d8, 0x00000fff, 0x00000100,
404 0xa008, 0xffffffff, 0x00010000,
405 0xa008, 0xffffffff, 0x00010000,
406 0x913c, 0xffff03ff, 0x01000100,
407 0x913c, 0xffff03ff, 0x01000100,
408 0x90e8, 0x001fffff, 0x010400c0,
409 0x8c00, 0x000000ff, 0x00000003,
410 0x8c00, 0x000000ff, 0x00000003,
411 0x8c04, 0xf8ff00ff, 0x40600060,
412 0x8c04, 0xf8ff00ff, 0x40600060,
413 0x8c30, 0x0000000f, 0x00040005,
414 0x8cf0, 0x1fff1fff, 0x08e00410,
415 0x8cf0, 0x1fff1fff, 0x08e00410,
416 0x900c, 0x00ffffff, 0x0017071f,
417 0x28350, 0x00000f01, 0x00000000,
418 0x28350, 0x00000f01, 0x00000000,
419 0x9508, 0xf700071f, 0x00000002,
420 0x9508, 0xf700071f, 0x00000002,
421 0x9688, 0x00300000, 0x0017000f,
422 0x960c, 0xffffffff, 0x54763210,
423 0x960c, 0xffffffff, 0x54763210,
424 0x20ef8, 0x01ff01ff, 0x00000002,
425 0x20e98, 0xfffffbff, 0x00200000,
426 0x2015c, 0xffffffff, 0x00000f40,
427 0x88c4, 0x001f3ae3, 0x00000082,
428 0x88c4, 0x001f3ae3, 0x00000082,
429 0x8978, 0x3fffffff, 0x04050140,
430 0x8978, 0x3fffffff, 0x04050140,
431 0x88d4, 0x0000001f, 0x00000010,
432 0x88d4, 0x0000001f, 0x00000010,
433 0x8974, 0xffffffff, 0x00000000,
434 0x8974, 0xffffffff, 0x00000000
435};
436
437static void ni_init_golden_registers(struct radeon_device *rdev)
438{
439 switch (rdev->family) {
440 case CHIP_CAYMAN:
441 radeon_program_register_sequence(rdev,
442 cayman_golden_registers,
443 (const u32)ARRAY_SIZE(cayman_golden_registers));
444 radeon_program_register_sequence(rdev,
445 cayman_golden_registers2,
446 (const u32)ARRAY_SIZE(cayman_golden_registers2));
447 break;
448 case CHIP_ARUBA:
449 if ((rdev->pdev->device == 0x9900) ||
450 (rdev->pdev->device == 0x9901) ||
451 (rdev->pdev->device == 0x9903) ||
452 (rdev->pdev->device == 0x9904) ||
453 (rdev->pdev->device == 0x9905) ||
454 (rdev->pdev->device == 0x9906) ||
455 (rdev->pdev->device == 0x9907) ||
456 (rdev->pdev->device == 0x9908) ||
457 (rdev->pdev->device == 0x9909) ||
458 (rdev->pdev->device == 0x990A) ||
459 (rdev->pdev->device == 0x990B) ||
460 (rdev->pdev->device == 0x990C) ||
461 (rdev->pdev->device == 0x990D) ||
462 (rdev->pdev->device == 0x990E) ||
463 (rdev->pdev->device == 0x990F) ||
464 (rdev->pdev->device == 0x9910) ||
465 (rdev->pdev->device == 0x9913) ||
466 (rdev->pdev->device == 0x9917) ||
467 (rdev->pdev->device == 0x9918)) {
468 radeon_program_register_sequence(rdev,
469 dvst_golden_registers,
470 (const u32)ARRAY_SIZE(dvst_golden_registers));
471 radeon_program_register_sequence(rdev,
472 dvst_golden_registers2,
473 (const u32)ARRAY_SIZE(dvst_golden_registers2));
474 } else {
475 radeon_program_register_sequence(rdev,
476 scrapper_golden_registers,
477 (const u32)ARRAY_SIZE(scrapper_golden_registers));
478 radeon_program_register_sequence(rdev,
479 dvst_golden_registers2,
480 (const u32)ARRAY_SIZE(dvst_golden_registers2));
481 }
482 break;
483 default:
484 break;
485 }
486}
487
488#define BTC_IO_MC_REGS_SIZE 29
489
490static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
491 {0x00000077, 0xff010100},
492 {0x00000078, 0x00000000},
493 {0x00000079, 0x00001434},
494 {0x0000007a, 0xcc08ec08},
495 {0x0000007b, 0x00040000},
496 {0x0000007c, 0x000080c0},
497 {0x0000007d, 0x09000000},
498 {0x0000007e, 0x00210404},
499 {0x00000081, 0x08a8e800},
500 {0x00000082, 0x00030444},
501 {0x00000083, 0x00000000},
502 {0x00000085, 0x00000001},
503 {0x00000086, 0x00000002},
504 {0x00000087, 0x48490000},
505 {0x00000088, 0x20244647},
506 {0x00000089, 0x00000005},
507 {0x0000008b, 0x66030000},
508 {0x0000008c, 0x00006603},
509 {0x0000008d, 0x00000100},
510 {0x0000008f, 0x00001c0a},
511 {0x00000090, 0xff000001},
512 {0x00000094, 0x00101101},
513 {0x00000095, 0x00000fff},
514 {0x00000096, 0x00116fff},
515 {0x00000097, 0x60010000},
516 {0x00000098, 0x10010000},
517 {0x00000099, 0x00006000},
518 {0x0000009a, 0x00001000},
519 {0x0000009f, 0x00946a00}
520};
521
522static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
523 {0x00000077, 0xff010100},
524 {0x00000078, 0x00000000},
525 {0x00000079, 0x00001434},
526 {0x0000007a, 0xcc08ec08},
527 {0x0000007b, 0x00040000},
528 {0x0000007c, 0x000080c0},
529 {0x0000007d, 0x09000000},
530 {0x0000007e, 0x00210404},
531 {0x00000081, 0x08a8e800},
532 {0x00000082, 0x00030444},
533 {0x00000083, 0x00000000},
534 {0x00000085, 0x00000001},
535 {0x00000086, 0x00000002},
536 {0x00000087, 0x48490000},
537 {0x00000088, 0x20244647},
538 {0x00000089, 0x00000005},
539 {0x0000008b, 0x66030000},
540 {0x0000008c, 0x00006603},
541 {0x0000008d, 0x00000100},
542 {0x0000008f, 0x00001c0a},
543 {0x00000090, 0xff000001},
544 {0x00000094, 0x00101101},
545 {0x00000095, 0x00000fff},
546 {0x00000096, 0x00116fff},
547 {0x00000097, 0x60010000},
548 {0x00000098, 0x10010000},
549 {0x00000099, 0x00006000},
550 {0x0000009a, 0x00001000},
551 {0x0000009f, 0x00936a00}
552};
553
554static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
555 {0x00000077, 0xff010100},
556 {0x00000078, 0x00000000},
557 {0x00000079, 0x00001434},
558 {0x0000007a, 0xcc08ec08},
559 {0x0000007b, 0x00040000},
560 {0x0000007c, 0x000080c0},
561 {0x0000007d, 0x09000000},
562 {0x0000007e, 0x00210404},
563 {0x00000081, 0x08a8e800},
564 {0x00000082, 0x00030444},
565 {0x00000083, 0x00000000},
566 {0x00000085, 0x00000001},
567 {0x00000086, 0x00000002},
568 {0x00000087, 0x48490000},
569 {0x00000088, 0x20244647},
570 {0x00000089, 0x00000005},
571 {0x0000008b, 0x66030000},
572 {0x0000008c, 0x00006603},
573 {0x0000008d, 0x00000100},
574 {0x0000008f, 0x00001c0a},
575 {0x00000090, 0xff000001},
576 {0x00000094, 0x00101101},
577 {0x00000095, 0x00000fff},
578 {0x00000096, 0x00116fff},
579 {0x00000097, 0x60010000},
580 {0x00000098, 0x10010000},
581 {0x00000099, 0x00006000},
582 {0x0000009a, 0x00001000},
583 {0x0000009f, 0x00916a00}
584};
585
586static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
587 {0x00000077, 0xff010100},
588 {0x00000078, 0x00000000},
589 {0x00000079, 0x00001434},
590 {0x0000007a, 0xcc08ec08},
591 {0x0000007b, 0x00040000},
592 {0x0000007c, 0x000080c0},
593 {0x0000007d, 0x09000000},
594 {0x0000007e, 0x00210404},
595 {0x00000081, 0x08a8e800},
596 {0x00000082, 0x00030444},
597 {0x00000083, 0x00000000},
598 {0x00000085, 0x00000001},
599 {0x00000086, 0x00000002},
600 {0x00000087, 0x48490000},
601 {0x00000088, 0x20244647},
602 {0x00000089, 0x00000005},
603 {0x0000008b, 0x66030000},
604 {0x0000008c, 0x00006603},
605 {0x0000008d, 0x00000100},
606 {0x0000008f, 0x00001c0a},
607 {0x00000090, 0xff000001},
608 {0x00000094, 0x00101101},
609 {0x00000095, 0x00000fff},
610 {0x00000096, 0x00116fff},
611 {0x00000097, 0x60010000},
612 {0x00000098, 0x10010000},
613 {0x00000099, 0x00006000},
614 {0x0000009a, 0x00001000},
615 {0x0000009f, 0x00976b00}
616};
617
618int ni_mc_load_microcode(struct radeon_device *rdev)
619{
620 const __be32 *fw_data;
621 u32 mem_type, running;
622 u32 *io_mc_regs;
623 int i, ucode_size, regs_size;
624
625 if (!rdev->mc_fw)
626 return -EINVAL;
627
628 switch (rdev->family) {
629 case CHIP_BARTS:
630 io_mc_regs = (u32 *)&barts_io_mc_regs;
631 ucode_size = BTC_MC_UCODE_SIZE;
632 regs_size = BTC_IO_MC_REGS_SIZE;
633 break;
634 case CHIP_TURKS:
635 io_mc_regs = (u32 *)&turks_io_mc_regs;
636 ucode_size = BTC_MC_UCODE_SIZE;
637 regs_size = BTC_IO_MC_REGS_SIZE;
638 break;
639 case CHIP_CAICOS:
640 default:
641 io_mc_regs = (u32 *)&caicos_io_mc_regs;
642 ucode_size = BTC_MC_UCODE_SIZE;
643 regs_size = BTC_IO_MC_REGS_SIZE;
644 break;
645 case CHIP_CAYMAN:
646 io_mc_regs = (u32 *)&cayman_io_mc_regs;
647 ucode_size = CAYMAN_MC_UCODE_SIZE;
648 regs_size = BTC_IO_MC_REGS_SIZE;
649 break;
650 }
651
652 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
653 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
654
655 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
656 /* reset the engine and set to writable */
657 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
658 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
659
660 /* load mc io regs */
661 for (i = 0; i < regs_size; i++) {
662 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
663 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
664 }
665 /* load the MC ucode */
666 fw_data = (const __be32 *)rdev->mc_fw->data;
667 for (i = 0; i < ucode_size; i++)
668 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
669
670 /* put the engine back into the active state */
671 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
672 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
673 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
674
675 /* wait for training to complete */
676 for (i = 0; i < rdev->usec_timeout; i++) {
677 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
678 break;
679 udelay(1);
680 }
681 }
682
683 return 0;
684}
685
686int ni_init_microcode(struct radeon_device *rdev)
687{
688 const char *chip_name;
689 const char *rlc_chip_name;
690 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
691 size_t smc_req_size = 0;
692 char fw_name[30];
693 int err;
694
695 DRM_DEBUG("\n");
696
697 switch (rdev->family) {
698 case CHIP_BARTS:
699 chip_name = "BARTS";
700 rlc_chip_name = "BTC";
701 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
702 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
703 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
704 mc_req_size = BTC_MC_UCODE_SIZE * 4;
705 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
706 break;
707 case CHIP_TURKS:
708 chip_name = "TURKS";
709 rlc_chip_name = "BTC";
710 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
711 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
712 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
713 mc_req_size = BTC_MC_UCODE_SIZE * 4;
714 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
715 break;
716 case CHIP_CAICOS:
717 chip_name = "CAICOS";
718 rlc_chip_name = "BTC";
719 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
720 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
721 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
722 mc_req_size = BTC_MC_UCODE_SIZE * 4;
723 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
724 break;
725 case CHIP_CAYMAN:
726 chip_name = "CAYMAN";
727 rlc_chip_name = "CAYMAN";
728 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
729 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
730 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
731 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
732 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
733 break;
734 case CHIP_ARUBA:
735 chip_name = "ARUBA";
736 rlc_chip_name = "ARUBA";
737 /* pfp/me same size as CAYMAN */
738 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
739 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
740 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
741 mc_req_size = 0;
742 break;
743 default:
744 BUG();
745 }
746
747 DRM_INFO("Loading %s Microcode\n", chip_name);
748
749 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
750 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
751 if (err)
752 goto out;
753 if (rdev->pfp_fw->size != pfp_req_size) {
754 pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n",
755 rdev->pfp_fw->size, fw_name);
756 err = -EINVAL;
757 goto out;
758 }
759
760 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
761 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
762 if (err)
763 goto out;
764 if (rdev->me_fw->size != me_req_size) {
765 pr_err("ni_cp: Bogus length %zu in firmware \"%s\"\n",
766 rdev->me_fw->size, fw_name);
767 err = -EINVAL;
768 }
769
770 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
771 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
772 if (err)
773 goto out;
774 if (rdev->rlc_fw->size != rlc_req_size) {
775 pr_err("ni_rlc: Bogus length %zu in firmware \"%s\"\n",
776 rdev->rlc_fw->size, fw_name);
777 err = -EINVAL;
778 }
779
780 /* no MC ucode on TN */
781 if (!(rdev->flags & RADEON_IS_IGP)) {
782 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
783 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
784 if (err)
785 goto out;
786 if (rdev->mc_fw->size != mc_req_size) {
787 pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n",
788 rdev->mc_fw->size, fw_name);
789 err = -EINVAL;
790 }
791 }
792
793 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
794 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
795 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
796 if (err) {
797 pr_err("smc: error loading firmware \"%s\"\n", fw_name);
798 release_firmware(rdev->smc_fw);
799 rdev->smc_fw = NULL;
800 err = 0;
801 } else if (rdev->smc_fw->size != smc_req_size) {
802 pr_err("ni_mc: Bogus length %zu in firmware \"%s\"\n",
803 rdev->smc_fw->size, fw_name);
804 err = -EINVAL;
805 }
806 }
807
808out:
809 if (err) {
810 if (err != -EINVAL)
811 pr_err("ni_cp: Failed to load firmware \"%s\"\n",
812 fw_name);
813 release_firmware(rdev->pfp_fw);
814 rdev->pfp_fw = NULL;
815 release_firmware(rdev->me_fw);
816 rdev->me_fw = NULL;
817 release_firmware(rdev->rlc_fw);
818 rdev->rlc_fw = NULL;
819 release_firmware(rdev->mc_fw);
820 rdev->mc_fw = NULL;
821 }
822 return err;
823}
824
825/**
826 * cayman_get_allowed_info_register - fetch the register for the info ioctl
827 *
828 * @rdev: radeon_device pointer
829 * @reg: register offset in bytes
830 * @val: register value
831 *
832 * Returns 0 for success or -EINVAL for an invalid register
833 *
834 */
835int cayman_get_allowed_info_register(struct radeon_device *rdev,
836 u32 reg, u32 *val)
837{
838 switch (reg) {
839 case GRBM_STATUS:
840 case GRBM_STATUS_SE0:
841 case GRBM_STATUS_SE1:
842 case SRBM_STATUS:
843 case SRBM_STATUS2:
844 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
845 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
846 case UVD_STATUS:
847 *val = RREG32(reg);
848 return 0;
849 default:
850 return -EINVAL;
851 }
852}
853
854int tn_get_temp(struct radeon_device *rdev)
855{
856 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
857 int actual_temp = (temp / 8) - 49;
858
859 return actual_temp * 1000;
860}
861
862/*
863 * Core functions
864 */
865static void cayman_gpu_init(struct radeon_device *rdev)
866{
867 u32 gb_addr_config = 0;
868 u32 mc_arb_ramcfg;
869 u32 cgts_tcc_disable;
870 u32 sx_debug_1;
871 u32 smx_dc_ctl0;
872 u32 cgts_sm_ctrl_reg;
873 u32 hdp_host_path_cntl;
874 u32 tmp;
875 u32 disabled_rb_mask;
876 int i, j;
877
878 switch (rdev->family) {
879 case CHIP_CAYMAN:
880 rdev->config.cayman.max_shader_engines = 2;
881 rdev->config.cayman.max_pipes_per_simd = 4;
882 rdev->config.cayman.max_tile_pipes = 8;
883 rdev->config.cayman.max_simds_per_se = 12;
884 rdev->config.cayman.max_backends_per_se = 4;
885 rdev->config.cayman.max_texture_channel_caches = 8;
886 rdev->config.cayman.max_gprs = 256;
887 rdev->config.cayman.max_threads = 256;
888 rdev->config.cayman.max_gs_threads = 32;
889 rdev->config.cayman.max_stack_entries = 512;
890 rdev->config.cayman.sx_num_of_sets = 8;
891 rdev->config.cayman.sx_max_export_size = 256;
892 rdev->config.cayman.sx_max_export_pos_size = 64;
893 rdev->config.cayman.sx_max_export_smx_size = 192;
894 rdev->config.cayman.max_hw_contexts = 8;
895 rdev->config.cayman.sq_num_cf_insts = 2;
896
897 rdev->config.cayman.sc_prim_fifo_size = 0x100;
898 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
899 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
900 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
901 break;
902 case CHIP_ARUBA:
903 default:
904 rdev->config.cayman.max_shader_engines = 1;
905 rdev->config.cayman.max_pipes_per_simd = 4;
906 rdev->config.cayman.max_tile_pipes = 2;
907 if ((rdev->pdev->device == 0x9900) ||
908 (rdev->pdev->device == 0x9901) ||
909 (rdev->pdev->device == 0x9905) ||
910 (rdev->pdev->device == 0x9906) ||
911 (rdev->pdev->device == 0x9907) ||
912 (rdev->pdev->device == 0x9908) ||
913 (rdev->pdev->device == 0x9909) ||
914 (rdev->pdev->device == 0x990B) ||
915 (rdev->pdev->device == 0x990C) ||
916 (rdev->pdev->device == 0x990F) ||
917 (rdev->pdev->device == 0x9910) ||
918 (rdev->pdev->device == 0x9917) ||
919 (rdev->pdev->device == 0x9999) ||
920 (rdev->pdev->device == 0x999C)) {
921 rdev->config.cayman.max_simds_per_se = 6;
922 rdev->config.cayman.max_backends_per_se = 2;
923 rdev->config.cayman.max_hw_contexts = 8;
924 rdev->config.cayman.sx_max_export_size = 256;
925 rdev->config.cayman.sx_max_export_pos_size = 64;
926 rdev->config.cayman.sx_max_export_smx_size = 192;
927 } else if ((rdev->pdev->device == 0x9903) ||
928 (rdev->pdev->device == 0x9904) ||
929 (rdev->pdev->device == 0x990A) ||
930 (rdev->pdev->device == 0x990D) ||
931 (rdev->pdev->device == 0x990E) ||
932 (rdev->pdev->device == 0x9913) ||
933 (rdev->pdev->device == 0x9918) ||
934 (rdev->pdev->device == 0x999D)) {
935 rdev->config.cayman.max_simds_per_se = 4;
936 rdev->config.cayman.max_backends_per_se = 2;
937 rdev->config.cayman.max_hw_contexts = 8;
938 rdev->config.cayman.sx_max_export_size = 256;
939 rdev->config.cayman.sx_max_export_pos_size = 64;
940 rdev->config.cayman.sx_max_export_smx_size = 192;
941 } else if ((rdev->pdev->device == 0x9919) ||
942 (rdev->pdev->device == 0x9990) ||
943 (rdev->pdev->device == 0x9991) ||
944 (rdev->pdev->device == 0x9994) ||
945 (rdev->pdev->device == 0x9995) ||
946 (rdev->pdev->device == 0x9996) ||
947 (rdev->pdev->device == 0x999A) ||
948 (rdev->pdev->device == 0x99A0)) {
949 rdev->config.cayman.max_simds_per_se = 3;
950 rdev->config.cayman.max_backends_per_se = 1;
951 rdev->config.cayman.max_hw_contexts = 4;
952 rdev->config.cayman.sx_max_export_size = 128;
953 rdev->config.cayman.sx_max_export_pos_size = 32;
954 rdev->config.cayman.sx_max_export_smx_size = 96;
955 } else {
956 rdev->config.cayman.max_simds_per_se = 2;
957 rdev->config.cayman.max_backends_per_se = 1;
958 rdev->config.cayman.max_hw_contexts = 4;
959 rdev->config.cayman.sx_max_export_size = 128;
960 rdev->config.cayman.sx_max_export_pos_size = 32;
961 rdev->config.cayman.sx_max_export_smx_size = 96;
962 }
963 rdev->config.cayman.max_texture_channel_caches = 2;
964 rdev->config.cayman.max_gprs = 256;
965 rdev->config.cayman.max_threads = 256;
966 rdev->config.cayman.max_gs_threads = 32;
967 rdev->config.cayman.max_stack_entries = 512;
968 rdev->config.cayman.sx_num_of_sets = 8;
969 rdev->config.cayman.sq_num_cf_insts = 2;
970
971 rdev->config.cayman.sc_prim_fifo_size = 0x40;
972 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
973 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
974 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
975 break;
976 }
977
978 /* Initialize HDP */
979 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
980 WREG32((0x2c14 + j), 0x00000000);
981 WREG32((0x2c18 + j), 0x00000000);
982 WREG32((0x2c1c + j), 0x00000000);
983 WREG32((0x2c20 + j), 0x00000000);
984 WREG32((0x2c24 + j), 0x00000000);
985 }
986
987 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
988 WREG32(SRBM_INT_CNTL, 0x1);
989 WREG32(SRBM_INT_ACK, 0x1);
990
991 evergreen_fix_pci_max_read_req_size(rdev);
992
993 RREG32(MC_SHARED_CHMAP);
994 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
995
996 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
997 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
998 if (rdev->config.cayman.mem_row_size_in_kb > 4)
999 rdev->config.cayman.mem_row_size_in_kb = 4;
1000 /* XXX use MC settings? */
1001 rdev->config.cayman.shader_engine_tile_size = 32;
1002 rdev->config.cayman.num_gpus = 1;
1003 rdev->config.cayman.multi_gpu_tile_size = 64;
1004
1005 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1006 rdev->config.cayman.num_tile_pipes = (1 << tmp);
1007 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1008 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
1009 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1010 rdev->config.cayman.num_shader_engines = tmp + 1;
1011 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1012 rdev->config.cayman.num_gpus = tmp + 1;
1013 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1014 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
1015 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1016 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
1017
1018
1019 /* setup tiling info dword. gb_addr_config is not adequate since it does
1020 * not have bank info, so create a custom tiling dword.
1021 * bits 3:0 num_pipes
1022 * bits 7:4 num_banks
1023 * bits 11:8 group_size
1024 * bits 15:12 row_size
1025 */
1026 rdev->config.cayman.tile_config = 0;
1027 switch (rdev->config.cayman.num_tile_pipes) {
1028 case 1:
1029 default:
1030 rdev->config.cayman.tile_config |= (0 << 0);
1031 break;
1032 case 2:
1033 rdev->config.cayman.tile_config |= (1 << 0);
1034 break;
1035 case 4:
1036 rdev->config.cayman.tile_config |= (2 << 0);
1037 break;
1038 case 8:
1039 rdev->config.cayman.tile_config |= (3 << 0);
1040 break;
1041 }
1042
1043 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1044 if (rdev->flags & RADEON_IS_IGP)
1045 rdev->config.cayman.tile_config |= 1 << 4;
1046 else {
1047 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1048 case 0: /* four banks */
1049 rdev->config.cayman.tile_config |= 0 << 4;
1050 break;
1051 case 1: /* eight banks */
1052 rdev->config.cayman.tile_config |= 1 << 4;
1053 break;
1054 case 2: /* sixteen banks */
1055 default:
1056 rdev->config.cayman.tile_config |= 2 << 4;
1057 break;
1058 }
1059 }
1060 rdev->config.cayman.tile_config |=
1061 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1062 rdev->config.cayman.tile_config |=
1063 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1064
1065 tmp = 0;
1066 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1067 u32 rb_disable_bitmap;
1068
1069 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1070 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1071 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1072 tmp <<= 4;
1073 tmp |= rb_disable_bitmap;
1074 }
1075 /* enabled rb are just the one not disabled :) */
1076 disabled_rb_mask = tmp;
1077 tmp = 0;
1078 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1079 tmp |= (1 << i);
1080 /* if all the backends are disabled, fix it up here */
1081 if ((disabled_rb_mask & tmp) == tmp) {
1082 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1083 disabled_rb_mask &= ~(1 << i);
1084 }
1085
1086 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {
1087 u32 simd_disable_bitmap;
1088
1089 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1090 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1091 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
1092 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
1093 tmp <<= 16;
1094 tmp |= simd_disable_bitmap;
1095 }
1096 rdev->config.cayman.active_simds = hweight32(~tmp);
1097
1098 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1099 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1100
1101 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1102 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1103 if (ASIC_IS_DCE6(rdev))
1104 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1105 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1106 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1107 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1108 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1109 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1110 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1111
1112 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1113 (rdev->flags & RADEON_IS_IGP)) {
1114 if ((disabled_rb_mask & 3) == 2) {
1115 /* RB1 disabled, RB0 enabled */
1116 tmp = 0x00000000;
1117 } else {
1118 /* RB0 disabled, RB1 enabled */
1119 tmp = 0x11111111;
1120 }
1121 } else {
1122 tmp = gb_addr_config & NUM_PIPES_MASK;
1123 tmp = r6xx_remap_render_backend(rdev, tmp,
1124 rdev->config.cayman.max_backends_per_se *
1125 rdev->config.cayman.max_shader_engines,
1126 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1127 }
1128 rdev->config.cayman.backend_map = tmp;
1129 WREG32(GB_BACKEND_MAP, tmp);
1130
1131 cgts_tcc_disable = 0xffff0000;
1132 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1133 cgts_tcc_disable &= ~(1 << (16 + i));
1134 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1135 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1136 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1137 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1138
1139 /* reprogram the shader complex */
1140 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1141 for (i = 0; i < 16; i++)
1142 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1143 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1144
1145 /* set HW defaults for 3D engine */
1146 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1147
1148 sx_debug_1 = RREG32(SX_DEBUG_1);
1149 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1150 WREG32(SX_DEBUG_1, sx_debug_1);
1151
1152 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1153 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1154 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1155 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1156
1157 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1158
1159 /* need to be explicitly zero-ed */
1160 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1161 WREG32(SQ_LSTMP_RING_BASE, 0);
1162 WREG32(SQ_HSTMP_RING_BASE, 0);
1163 WREG32(SQ_ESTMP_RING_BASE, 0);
1164 WREG32(SQ_GSTMP_RING_BASE, 0);
1165 WREG32(SQ_VSTMP_RING_BASE, 0);
1166 WREG32(SQ_PSTMP_RING_BASE, 0);
1167
1168 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1169
1170 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1171 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1172 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1173
1174 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1175 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1176 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1177
1178
1179 WREG32(VGT_NUM_INSTANCES, 1);
1180
1181 WREG32(CP_PERFMON_CNTL, 0);
1182
1183 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1184 FETCH_FIFO_HIWATER(0x4) |
1185 DONE_FIFO_HIWATER(0xe0) |
1186 ALU_UPDATE_FIFO_HIWATER(0x8)));
1187
1188 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1189 WREG32(SQ_CONFIG, (VC_ENABLE |
1190 EXPORT_SRC_C |
1191 GFX_PRIO(0) |
1192 CS1_PRIO(0) |
1193 CS2_PRIO(1)));
1194 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1195
1196 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1197 FORCE_EOV_MAX_REZ_CNT(255)));
1198
1199 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1200 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1201
1202 WREG32(VGT_GS_VERTEX_REUSE, 16);
1203 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1204
1205 WREG32(CB_PERF_CTR0_SEL_0, 0);
1206 WREG32(CB_PERF_CTR0_SEL_1, 0);
1207 WREG32(CB_PERF_CTR1_SEL_0, 0);
1208 WREG32(CB_PERF_CTR1_SEL_1, 0);
1209 WREG32(CB_PERF_CTR2_SEL_0, 0);
1210 WREG32(CB_PERF_CTR2_SEL_1, 0);
1211 WREG32(CB_PERF_CTR3_SEL_0, 0);
1212 WREG32(CB_PERF_CTR3_SEL_1, 0);
1213
1214 tmp = RREG32(HDP_MISC_CNTL);
1215 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1216 WREG32(HDP_MISC_CNTL, tmp);
1217
1218 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1219 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1220
1221 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1222
1223 udelay(50);
1224
1225 /* set clockgating golden values on TN */
1226 if (rdev->family == CHIP_ARUBA) {
1227 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1228 tmp &= ~0x00380000;
1229 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1230 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1231 tmp &= ~0x0e000000;
1232 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1233 }
1234}
1235
1236/*
1237 * GART
1238 */
1239void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1240{
1241 /* flush hdp cache */
1242 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1243
1244 /* bits 0-7 are the VM contexts0-7 */
1245 WREG32(VM_INVALIDATE_REQUEST, 1);
1246}
1247
1248static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1249{
1250 int i, r;
1251
1252 if (rdev->gart.robj == NULL) {
1253 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1254 return -EINVAL;
1255 }
1256 r = radeon_gart_table_vram_pin(rdev);
1257 if (r)
1258 return r;
1259 /* Setup TLB control */
1260 WREG32(MC_VM_MX_L1_TLB_CNTL,
1261 (0xA << 7) |
1262 ENABLE_L1_TLB |
1263 ENABLE_L1_FRAGMENT_PROCESSING |
1264 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1265 ENABLE_ADVANCED_DRIVER_MODEL |
1266 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1267 /* Setup L2 cache */
1268 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1269 ENABLE_L2_FRAGMENT_PROCESSING |
1270 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1271 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1272 EFFECTIVE_L2_QUEUE_SIZE(7) |
1273 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1274 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1275 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1276 BANK_SELECT(6) |
1277 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1278 /* setup context0 */
1279 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1280 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1281 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1282 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1283 (u32)(rdev->dummy_page.addr >> 12));
1284 WREG32(VM_CONTEXT0_CNTL2, 0);
1285 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1286 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1287
1288 WREG32(0x15D4, 0);
1289 WREG32(0x15D8, 0);
1290 WREG32(0x15DC, 0);
1291
1292 /* empty context1-7 */
1293 /* Assign the pt base to something valid for now; the pts used for
1294 * the VMs are determined by the application and setup and assigned
1295 * on the fly in the vm part of radeon_gart.c
1296 */
1297 for (i = 1; i < 8; i++) {
1298 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1299 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
1300 rdev->vm_manager.max_pfn - 1);
1301 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1302 rdev->vm_manager.saved_table_addr[i]);
1303 }
1304
1305 /* enable context1-7 */
1306 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1307 (u32)(rdev->dummy_page.addr >> 12));
1308 WREG32(VM_CONTEXT1_CNTL2, 4);
1309 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1310 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
1311 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1312 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1313 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1314 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1315 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1316 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1317 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1318 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1319 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1320 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1321 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1322 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1323
1324 cayman_pcie_gart_tlb_flush(rdev);
1325 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1326 (unsigned)(rdev->mc.gtt_size >> 20),
1327 (unsigned long long)rdev->gart.table_addr);
1328 rdev->gart.ready = true;
1329 return 0;
1330}
1331
1332static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1333{
1334 unsigned i;
1335
1336 for (i = 1; i < 8; ++i) {
1337 rdev->vm_manager.saved_table_addr[i] = RREG32(
1338 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2));
1339 }
1340
1341 /* Disable all tables */
1342 WREG32(VM_CONTEXT0_CNTL, 0);
1343 WREG32(VM_CONTEXT1_CNTL, 0);
1344 /* Setup TLB control */
1345 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1346 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1347 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1348 /* Setup L2 cache */
1349 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1350 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1351 EFFECTIVE_L2_QUEUE_SIZE(7) |
1352 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1353 WREG32(VM_L2_CNTL2, 0);
1354 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1355 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1356 radeon_gart_table_vram_unpin(rdev);
1357}
1358
1359static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1360{
1361 cayman_pcie_gart_disable(rdev);
1362 radeon_gart_table_vram_free(rdev);
1363 radeon_gart_fini(rdev);
1364}
1365
1366void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1367 int ring, u32 cp_int_cntl)
1368{
1369 WREG32(SRBM_GFX_CNTL, RINGID(ring));
1370 WREG32(CP_INT_CNTL, cp_int_cntl);
1371}
1372
1373/*
1374 * CP.
1375 */
1376void cayman_fence_ring_emit(struct radeon_device *rdev,
1377 struct radeon_fence *fence)
1378{
1379 struct radeon_ring *ring = &rdev->ring[fence->ring];
1380 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1381 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1382 PACKET3_SH_ACTION_ENA;
1383
1384 /* flush read cache over gart for this vmid */
1385 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1386 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1387 radeon_ring_write(ring, 0xFFFFFFFF);
1388 radeon_ring_write(ring, 0);
1389 radeon_ring_write(ring, 10); /* poll interval */
1390 /* EVENT_WRITE_EOP - flush caches, send int */
1391 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1392 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1393 radeon_ring_write(ring, lower_32_bits(addr));
1394 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1395 radeon_ring_write(ring, fence->seq);
1396 radeon_ring_write(ring, 0);
1397}
1398
1399void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1400{
1401 struct radeon_ring *ring = &rdev->ring[ib->ring];
1402 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
1403 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1404 PACKET3_SH_ACTION_ENA;
1405
1406 /* set to DX10/11 mode */
1407 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1408 radeon_ring_write(ring, 1);
1409
1410 if (ring->rptr_save_reg) {
1411 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1412 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1413 radeon_ring_write(ring, ((ring->rptr_save_reg -
1414 PACKET3_SET_CONFIG_REG_START) >> 2));
1415 radeon_ring_write(ring, next_rptr);
1416 }
1417
1418 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1419 radeon_ring_write(ring,
1420#ifdef __BIG_ENDIAN
1421 (2 << 0) |
1422#endif
1423 (ib->gpu_addr & 0xFFFFFFFC));
1424 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1425 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
1426
1427 /* flush read cache over gart for this vmid */
1428 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1429 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1430 radeon_ring_write(ring, 0xFFFFFFFF);
1431 radeon_ring_write(ring, 0);
1432 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */
1433}
1434
1435static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1436{
1437 if (enable)
1438 WREG32(CP_ME_CNTL, 0);
1439 else {
1440 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1441 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1442 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1443 WREG32(SCRATCH_UMSK, 0);
1444 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1445 }
1446}
1447
1448u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1449 struct radeon_ring *ring)
1450{
1451 u32 rptr;
1452
1453 if (rdev->wb.enabled)
1454 rptr = rdev->wb.wb[ring->rptr_offs/4];
1455 else {
1456 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1457 rptr = RREG32(CP_RB0_RPTR);
1458 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1459 rptr = RREG32(CP_RB1_RPTR);
1460 else
1461 rptr = RREG32(CP_RB2_RPTR);
1462 }
1463
1464 return rptr;
1465}
1466
1467u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1468 struct radeon_ring *ring)
1469{
1470 u32 wptr;
1471
1472 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1473 wptr = RREG32(CP_RB0_WPTR);
1474 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1475 wptr = RREG32(CP_RB1_WPTR);
1476 else
1477 wptr = RREG32(CP_RB2_WPTR);
1478
1479 return wptr;
1480}
1481
1482void cayman_gfx_set_wptr(struct radeon_device *rdev,
1483 struct radeon_ring *ring)
1484{
1485 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1486 WREG32(CP_RB0_WPTR, ring->wptr);
1487 (void)RREG32(CP_RB0_WPTR);
1488 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1489 WREG32(CP_RB1_WPTR, ring->wptr);
1490 (void)RREG32(CP_RB1_WPTR);
1491 } else {
1492 WREG32(CP_RB2_WPTR, ring->wptr);
1493 (void)RREG32(CP_RB2_WPTR);
1494 }
1495}
1496
1497static int cayman_cp_load_microcode(struct radeon_device *rdev)
1498{
1499 const __be32 *fw_data;
1500 int i;
1501
1502 if (!rdev->me_fw || !rdev->pfp_fw)
1503 return -EINVAL;
1504
1505 cayman_cp_enable(rdev, false);
1506
1507 fw_data = (const __be32 *)rdev->pfp_fw->data;
1508 WREG32(CP_PFP_UCODE_ADDR, 0);
1509 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1510 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1511 WREG32(CP_PFP_UCODE_ADDR, 0);
1512
1513 fw_data = (const __be32 *)rdev->me_fw->data;
1514 WREG32(CP_ME_RAM_WADDR, 0);
1515 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1516 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1517
1518 WREG32(CP_PFP_UCODE_ADDR, 0);
1519 WREG32(CP_ME_RAM_WADDR, 0);
1520 WREG32(CP_ME_RAM_RADDR, 0);
1521 return 0;
1522}
1523
1524static int cayman_cp_start(struct radeon_device *rdev)
1525{
1526 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1527 int r, i;
1528
1529 r = radeon_ring_lock(rdev, ring, 7);
1530 if (r) {
1531 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1532 return r;
1533 }
1534 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1535 radeon_ring_write(ring, 0x1);
1536 radeon_ring_write(ring, 0x0);
1537 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1538 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1539 radeon_ring_write(ring, 0);
1540 radeon_ring_write(ring, 0);
1541 radeon_ring_unlock_commit(rdev, ring, false);
1542
1543 cayman_cp_enable(rdev, true);
1544
1545 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1546 if (r) {
1547 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1548 return r;
1549 }
1550
1551 /* setup clear context state */
1552 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1553 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1554
1555 for (i = 0; i < cayman_default_size; i++)
1556 radeon_ring_write(ring, cayman_default_state[i]);
1557
1558 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1559 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1560
1561 /* set clear context state */
1562 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1563 radeon_ring_write(ring, 0);
1564
1565 /* SQ_VTX_BASE_VTX_LOC */
1566 radeon_ring_write(ring, 0xc0026f00);
1567 radeon_ring_write(ring, 0x00000000);
1568 radeon_ring_write(ring, 0x00000000);
1569 radeon_ring_write(ring, 0x00000000);
1570
1571 /* Clear consts */
1572 radeon_ring_write(ring, 0xc0036f00);
1573 radeon_ring_write(ring, 0x00000bc4);
1574 radeon_ring_write(ring, 0xffffffff);
1575 radeon_ring_write(ring, 0xffffffff);
1576 radeon_ring_write(ring, 0xffffffff);
1577
1578 radeon_ring_write(ring, 0xc0026900);
1579 radeon_ring_write(ring, 0x00000316);
1580 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1581 radeon_ring_write(ring, 0x00000010); /* */
1582
1583 radeon_ring_unlock_commit(rdev, ring, false);
1584
1585 /* XXX init other rings */
1586
1587 return 0;
1588}
1589
1590static void cayman_cp_fini(struct radeon_device *rdev)
1591{
1592 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1593 cayman_cp_enable(rdev, false);
1594 radeon_ring_fini(rdev, ring);
1595 radeon_scratch_free(rdev, ring->rptr_save_reg);
1596}
1597
1598static int cayman_cp_resume(struct radeon_device *rdev)
1599{
1600 static const int ridx[] = {
1601 RADEON_RING_TYPE_GFX_INDEX,
1602 CAYMAN_RING_TYPE_CP1_INDEX,
1603 CAYMAN_RING_TYPE_CP2_INDEX
1604 };
1605 static const unsigned cp_rb_cntl[] = {
1606 CP_RB0_CNTL,
1607 CP_RB1_CNTL,
1608 CP_RB2_CNTL,
1609 };
1610 static const unsigned cp_rb_rptr_addr[] = {
1611 CP_RB0_RPTR_ADDR,
1612 CP_RB1_RPTR_ADDR,
1613 CP_RB2_RPTR_ADDR
1614 };
1615 static const unsigned cp_rb_rptr_addr_hi[] = {
1616 CP_RB0_RPTR_ADDR_HI,
1617 CP_RB1_RPTR_ADDR_HI,
1618 CP_RB2_RPTR_ADDR_HI
1619 };
1620 static const unsigned cp_rb_base[] = {
1621 CP_RB0_BASE,
1622 CP_RB1_BASE,
1623 CP_RB2_BASE
1624 };
1625 static const unsigned cp_rb_rptr[] = {
1626 CP_RB0_RPTR,
1627 CP_RB1_RPTR,
1628 CP_RB2_RPTR
1629 };
1630 static const unsigned cp_rb_wptr[] = {
1631 CP_RB0_WPTR,
1632 CP_RB1_WPTR,
1633 CP_RB2_WPTR
1634 };
1635 struct radeon_ring *ring;
1636 int i, r;
1637
1638 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1639 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1640 SOFT_RESET_PA |
1641 SOFT_RESET_SH |
1642 SOFT_RESET_VGT |
1643 SOFT_RESET_SPI |
1644 SOFT_RESET_SX));
1645 RREG32(GRBM_SOFT_RESET);
1646 mdelay(15);
1647 WREG32(GRBM_SOFT_RESET, 0);
1648 RREG32(GRBM_SOFT_RESET);
1649
1650 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1651 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1652
1653 /* Set the write pointer delay */
1654 WREG32(CP_RB_WPTR_DELAY, 0);
1655
1656 WREG32(CP_DEBUG, (1 << 27));
1657
1658 /* set the wb address whether it's enabled or not */
1659 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1660 WREG32(SCRATCH_UMSK, 0xff);
1661
1662 for (i = 0; i < 3; ++i) {
1663 uint32_t rb_cntl;
1664 uint64_t addr;
1665
1666 /* Set ring buffer size */
1667 ring = &rdev->ring[ridx[i]];
1668 rb_cntl = order_base_2(ring->ring_size / 8);
1669 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1670#ifdef __BIG_ENDIAN
1671 rb_cntl |= BUF_SWAP_32BIT;
1672#endif
1673 WREG32(cp_rb_cntl[i], rb_cntl);
1674
1675 /* set the wb address whether it's enabled or not */
1676 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1677 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1678 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1679 }
1680
1681 /* set the rb base addr, this causes an internal reset of ALL rings */
1682 for (i = 0; i < 3; ++i) {
1683 ring = &rdev->ring[ridx[i]];
1684 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1685 }
1686
1687 for (i = 0; i < 3; ++i) {
1688 /* Initialize the ring buffer's read and write pointers */
1689 ring = &rdev->ring[ridx[i]];
1690 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1691
1692 ring->wptr = 0;
1693 WREG32(cp_rb_rptr[i], 0);
1694 WREG32(cp_rb_wptr[i], ring->wptr);
1695
1696 mdelay(1);
1697 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1698 }
1699
1700 /* start the rings */
1701 cayman_cp_start(rdev);
1702 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1703 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1704 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1705 /* this only test cp0 */
1706 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1707 if (r) {
1708 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1709 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1710 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1711 return r;
1712 }
1713
1714 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1715 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1716
1717 return 0;
1718}
1719
1720u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1721{
1722 u32 reset_mask = 0;
1723 u32 tmp;
1724
1725 /* GRBM_STATUS */
1726 tmp = RREG32(GRBM_STATUS);
1727 if (tmp & (PA_BUSY | SC_BUSY |
1728 SH_BUSY | SX_BUSY |
1729 TA_BUSY | VGT_BUSY |
1730 DB_BUSY | CB_BUSY |
1731 GDS_BUSY | SPI_BUSY |
1732 IA_BUSY | IA_BUSY_NO_DMA))
1733 reset_mask |= RADEON_RESET_GFX;
1734
1735 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1736 CP_BUSY | CP_COHERENCY_BUSY))
1737 reset_mask |= RADEON_RESET_CP;
1738
1739 if (tmp & GRBM_EE_BUSY)
1740 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1741
1742 /* DMA_STATUS_REG 0 */
1743 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1744 if (!(tmp & DMA_IDLE))
1745 reset_mask |= RADEON_RESET_DMA;
1746
1747 /* DMA_STATUS_REG 1 */
1748 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1749 if (!(tmp & DMA_IDLE))
1750 reset_mask |= RADEON_RESET_DMA1;
1751
1752 /* SRBM_STATUS2 */
1753 tmp = RREG32(SRBM_STATUS2);
1754 if (tmp & DMA_BUSY)
1755 reset_mask |= RADEON_RESET_DMA;
1756
1757 if (tmp & DMA1_BUSY)
1758 reset_mask |= RADEON_RESET_DMA1;
1759
1760 /* SRBM_STATUS */
1761 tmp = RREG32(SRBM_STATUS);
1762 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1763 reset_mask |= RADEON_RESET_RLC;
1764
1765 if (tmp & IH_BUSY)
1766 reset_mask |= RADEON_RESET_IH;
1767
1768 if (tmp & SEM_BUSY)
1769 reset_mask |= RADEON_RESET_SEM;
1770
1771 if (tmp & GRBM_RQ_PENDING)
1772 reset_mask |= RADEON_RESET_GRBM;
1773
1774 if (tmp & VMC_BUSY)
1775 reset_mask |= RADEON_RESET_VMC;
1776
1777 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1778 MCC_BUSY | MCD_BUSY))
1779 reset_mask |= RADEON_RESET_MC;
1780
1781 if (evergreen_is_display_hung(rdev))
1782 reset_mask |= RADEON_RESET_DISPLAY;
1783
1784 /* VM_L2_STATUS */
1785 tmp = RREG32(VM_L2_STATUS);
1786 if (tmp & L2_BUSY)
1787 reset_mask |= RADEON_RESET_VMC;
1788
1789 /* Skip MC reset as it's mostly likely not hung, just busy */
1790 if (reset_mask & RADEON_RESET_MC) {
1791 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1792 reset_mask &= ~RADEON_RESET_MC;
1793 }
1794
1795 return reset_mask;
1796}
1797
1798static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1799{
1800 struct evergreen_mc_save save;
1801 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1802 u32 tmp;
1803
1804 if (reset_mask == 0)
1805 return;
1806
1807 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1808
1809 evergreen_print_gpu_status_regs(rdev);
1810 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1811 RREG32(0x14F8));
1812 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1813 RREG32(0x14D8));
1814 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1815 RREG32(0x14FC));
1816 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1817 RREG32(0x14DC));
1818
1819 /* Disable CP parsing/prefetching */
1820 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1821
1822 if (reset_mask & RADEON_RESET_DMA) {
1823 /* dma0 */
1824 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1825 tmp &= ~DMA_RB_ENABLE;
1826 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1827 }
1828
1829 if (reset_mask & RADEON_RESET_DMA1) {
1830 /* dma1 */
1831 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1832 tmp &= ~DMA_RB_ENABLE;
1833 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1834 }
1835
1836 udelay(50);
1837
1838 evergreen_mc_stop(rdev, &save);
1839 if (evergreen_mc_wait_for_idle(rdev)) {
1840 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1841 }
1842
1843 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1844 grbm_soft_reset = SOFT_RESET_CB |
1845 SOFT_RESET_DB |
1846 SOFT_RESET_GDS |
1847 SOFT_RESET_PA |
1848 SOFT_RESET_SC |
1849 SOFT_RESET_SPI |
1850 SOFT_RESET_SH |
1851 SOFT_RESET_SX |
1852 SOFT_RESET_TC |
1853 SOFT_RESET_TA |
1854 SOFT_RESET_VGT |
1855 SOFT_RESET_IA;
1856 }
1857
1858 if (reset_mask & RADEON_RESET_CP) {
1859 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1860
1861 srbm_soft_reset |= SOFT_RESET_GRBM;
1862 }
1863
1864 if (reset_mask & RADEON_RESET_DMA)
1865 srbm_soft_reset |= SOFT_RESET_DMA;
1866
1867 if (reset_mask & RADEON_RESET_DMA1)
1868 srbm_soft_reset |= SOFT_RESET_DMA1;
1869
1870 if (reset_mask & RADEON_RESET_DISPLAY)
1871 srbm_soft_reset |= SOFT_RESET_DC;
1872
1873 if (reset_mask & RADEON_RESET_RLC)
1874 srbm_soft_reset |= SOFT_RESET_RLC;
1875
1876 if (reset_mask & RADEON_RESET_SEM)
1877 srbm_soft_reset |= SOFT_RESET_SEM;
1878
1879 if (reset_mask & RADEON_RESET_IH)
1880 srbm_soft_reset |= SOFT_RESET_IH;
1881
1882 if (reset_mask & RADEON_RESET_GRBM)
1883 srbm_soft_reset |= SOFT_RESET_GRBM;
1884
1885 if (reset_mask & RADEON_RESET_VMC)
1886 srbm_soft_reset |= SOFT_RESET_VMC;
1887
1888 if (!(rdev->flags & RADEON_IS_IGP)) {
1889 if (reset_mask & RADEON_RESET_MC)
1890 srbm_soft_reset |= SOFT_RESET_MC;
1891 }
1892
1893 if (grbm_soft_reset) {
1894 tmp = RREG32(GRBM_SOFT_RESET);
1895 tmp |= grbm_soft_reset;
1896 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1897 WREG32(GRBM_SOFT_RESET, tmp);
1898 tmp = RREG32(GRBM_SOFT_RESET);
1899
1900 udelay(50);
1901
1902 tmp &= ~grbm_soft_reset;
1903 WREG32(GRBM_SOFT_RESET, tmp);
1904 tmp = RREG32(GRBM_SOFT_RESET);
1905 }
1906
1907 if (srbm_soft_reset) {
1908 tmp = RREG32(SRBM_SOFT_RESET);
1909 tmp |= srbm_soft_reset;
1910 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1911 WREG32(SRBM_SOFT_RESET, tmp);
1912 tmp = RREG32(SRBM_SOFT_RESET);
1913
1914 udelay(50);
1915
1916 tmp &= ~srbm_soft_reset;
1917 WREG32(SRBM_SOFT_RESET, tmp);
1918 tmp = RREG32(SRBM_SOFT_RESET);
1919 }
1920
1921 /* Wait a little for things to settle down */
1922 udelay(50);
1923
1924 evergreen_mc_resume(rdev, &save);
1925 udelay(50);
1926
1927 evergreen_print_gpu_status_regs(rdev);
1928}
1929
1930int cayman_asic_reset(struct radeon_device *rdev, bool hard)
1931{
1932 u32 reset_mask;
1933
1934 if (hard) {
1935 evergreen_gpu_pci_config_reset(rdev);
1936 return 0;
1937 }
1938
1939 reset_mask = cayman_gpu_check_soft_reset(rdev);
1940
1941 if (reset_mask)
1942 r600_set_bios_scratch_engine_hung(rdev, true);
1943
1944 cayman_gpu_soft_reset(rdev, reset_mask);
1945
1946 reset_mask = cayman_gpu_check_soft_reset(rdev);
1947
1948 if (reset_mask)
1949 evergreen_gpu_pci_config_reset(rdev);
1950
1951 r600_set_bios_scratch_engine_hung(rdev, false);
1952
1953 return 0;
1954}
1955
1956/**
1957 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1958 *
1959 * @rdev: radeon_device pointer
1960 * @ring: radeon_ring structure holding ring information
1961 *
1962 * Check if the GFX engine is locked up.
1963 * Returns true if the engine appears to be locked up, false if not.
1964 */
1965bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1966{
1967 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1968
1969 if (!(reset_mask & (RADEON_RESET_GFX |
1970 RADEON_RESET_COMPUTE |
1971 RADEON_RESET_CP))) {
1972 radeon_ring_lockup_update(rdev, ring);
1973 return false;
1974 }
1975 return radeon_ring_test_lockup(rdev, ring);
1976}
1977
1978static void cayman_uvd_init(struct radeon_device *rdev)
1979{
1980 int r;
1981
1982 if (!rdev->has_uvd)
1983 return;
1984
1985 r = radeon_uvd_init(rdev);
1986 if (r) {
1987 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
1988 /*
1989 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
1990 * to early fails uvd_v2_2_resume() and thus nothing happens
1991 * there. So it is pointless to try to go through that code
1992 * hence why we disable uvd here.
1993 */
1994 rdev->has_uvd = false;
1995 return;
1996 }
1997 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
1998 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
1999}
2000
2001static void cayman_uvd_start(struct radeon_device *rdev)
2002{
2003 int r;
2004
2005 if (!rdev->has_uvd)
2006 return;
2007
2008 r = uvd_v2_2_resume(rdev);
2009 if (r) {
2010 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
2011 goto error;
2012 }
2013 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
2014 if (r) {
2015 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
2016 goto error;
2017 }
2018 return;
2019
2020error:
2021 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2022}
2023
2024static void cayman_uvd_resume(struct radeon_device *rdev)
2025{
2026 struct radeon_ring *ring;
2027 int r;
2028
2029 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
2030 return;
2031
2032 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2033 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
2034 if (r) {
2035 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
2036 return;
2037 }
2038 r = uvd_v1_0_init(rdev);
2039 if (r) {
2040 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
2041 return;
2042 }
2043}
2044
2045static void cayman_vce_init(struct radeon_device *rdev)
2046{
2047 int r;
2048
2049 /* Only set for CHIP_ARUBA */
2050 if (!rdev->has_vce)
2051 return;
2052
2053 r = radeon_vce_init(rdev);
2054 if (r) {
2055 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
2056 /*
2057 * At this point rdev->vce.vcpu_bo is NULL which trickles down
2058 * to early fails cayman_vce_start() and thus nothing happens
2059 * there. So it is pointless to try to go through that code
2060 * hence why we disable vce here.
2061 */
2062 rdev->has_vce = false;
2063 return;
2064 }
2065 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
2066 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
2067 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
2068 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
2069}
2070
2071static void cayman_vce_start(struct radeon_device *rdev)
2072{
2073 int r;
2074
2075 if (!rdev->has_vce)
2076 return;
2077
2078 r = radeon_vce_resume(rdev);
2079 if (r) {
2080 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2081 goto error;
2082 }
2083 r = vce_v1_0_resume(rdev);
2084 if (r) {
2085 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2086 goto error;
2087 }
2088 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
2089 if (r) {
2090 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
2091 goto error;
2092 }
2093 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
2094 if (r) {
2095 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
2096 goto error;
2097 }
2098 return;
2099
2100error:
2101 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
2102 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
2103}
2104
2105static void cayman_vce_resume(struct radeon_device *rdev)
2106{
2107 struct radeon_ring *ring;
2108 int r;
2109
2110 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
2111 return;
2112
2113 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
2114 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2115 if (r) {
2116 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2117 return;
2118 }
2119 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
2120 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2121 if (r) {
2122 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2123 return;
2124 }
2125 r = vce_v1_0_init(rdev);
2126 if (r) {
2127 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
2128 return;
2129 }
2130}
2131
2132static int cayman_startup(struct radeon_device *rdev)
2133{
2134 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2135 int r;
2136
2137 /* enable pcie gen2 link */
2138 evergreen_pcie_gen2_enable(rdev);
2139 /* enable aspm */
2140 evergreen_program_aspm(rdev);
2141
2142 /* scratch needs to be initialized before MC */
2143 r = r600_vram_scratch_init(rdev);
2144 if (r)
2145 return r;
2146
2147 evergreen_mc_program(rdev);
2148
2149 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
2150 r = ni_mc_load_microcode(rdev);
2151 if (r) {
2152 DRM_ERROR("Failed to load MC firmware!\n");
2153 return r;
2154 }
2155 }
2156
2157 r = cayman_pcie_gart_enable(rdev);
2158 if (r)
2159 return r;
2160 cayman_gpu_init(rdev);
2161
2162 /* allocate rlc buffers */
2163 if (rdev->flags & RADEON_IS_IGP) {
2164 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
2165 rdev->rlc.reg_list_size =
2166 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
2167 rdev->rlc.cs_data = cayman_cs_data;
2168 r = sumo_rlc_init(rdev);
2169 if (r) {
2170 DRM_ERROR("Failed to init rlc BOs!\n");
2171 return r;
2172 }
2173 }
2174
2175 /* allocate wb buffer */
2176 r = radeon_wb_init(rdev);
2177 if (r)
2178 return r;
2179
2180 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2181 if (r) {
2182 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2183 return r;
2184 }
2185
2186 cayman_uvd_start(rdev);
2187 cayman_vce_start(rdev);
2188
2189 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2190 if (r) {
2191 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2192 return r;
2193 }
2194
2195 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2196 if (r) {
2197 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2198 return r;
2199 }
2200
2201 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2202 if (r) {
2203 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2204 return r;
2205 }
2206
2207 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2208 if (r) {
2209 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2210 return r;
2211 }
2212
2213 /* Enable IRQ */
2214 if (!rdev->irq.installed) {
2215 r = radeon_irq_kms_init(rdev);
2216 if (r)
2217 return r;
2218 }
2219
2220 r = r600_irq_init(rdev);
2221 if (r) {
2222 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2223 radeon_irq_kms_fini(rdev);
2224 return r;
2225 }
2226 evergreen_irq_set(rdev);
2227
2228 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2229 RADEON_CP_PACKET2);
2230 if (r)
2231 return r;
2232
2233 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2234 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2235 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2236 if (r)
2237 return r;
2238
2239 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2240 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2241 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2242 if (r)
2243 return r;
2244
2245 r = cayman_cp_load_microcode(rdev);
2246 if (r)
2247 return r;
2248 r = cayman_cp_resume(rdev);
2249 if (r)
2250 return r;
2251
2252 r = cayman_dma_resume(rdev);
2253 if (r)
2254 return r;
2255
2256 cayman_uvd_resume(rdev);
2257 cayman_vce_resume(rdev);
2258
2259 r = radeon_ib_pool_init(rdev);
2260 if (r) {
2261 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2262 return r;
2263 }
2264
2265 r = radeon_vm_manager_init(rdev);
2266 if (r) {
2267 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2268 return r;
2269 }
2270
2271 r = radeon_audio_init(rdev);
2272 if (r)
2273 return r;
2274
2275 return 0;
2276}
2277
2278int cayman_resume(struct radeon_device *rdev)
2279{
2280 int r;
2281
2282 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2283 * posting will perform necessary task to bring back GPU into good
2284 * shape.
2285 */
2286 /* post card */
2287 atom_asic_init(rdev->mode_info.atom_context);
2288
2289 /* init golden registers */
2290 ni_init_golden_registers(rdev);
2291
2292 if (rdev->pm.pm_method == PM_METHOD_DPM)
2293 radeon_pm_resume(rdev);
2294
2295 rdev->accel_working = true;
2296 r = cayman_startup(rdev);
2297 if (r) {
2298 DRM_ERROR("cayman startup failed on resume\n");
2299 rdev->accel_working = false;
2300 return r;
2301 }
2302 return r;
2303}
2304
2305int cayman_suspend(struct radeon_device *rdev)
2306{
2307 radeon_pm_suspend(rdev);
2308 radeon_audio_fini(rdev);
2309 radeon_vm_manager_fini(rdev);
2310 cayman_cp_enable(rdev, false);
2311 cayman_dma_stop(rdev);
2312 if (rdev->has_uvd) {
2313 radeon_uvd_suspend(rdev);
2314 uvd_v1_0_fini(rdev);
2315 }
2316 evergreen_irq_suspend(rdev);
2317 radeon_wb_disable(rdev);
2318 cayman_pcie_gart_disable(rdev);
2319 return 0;
2320}
2321
2322/* Plan is to move initialization in that function and use
2323 * helper function so that radeon_device_init pretty much
2324 * do nothing more than calling asic specific function. This
2325 * should also allow to remove a bunch of callback function
2326 * like vram_info.
2327 */
2328int cayman_init(struct radeon_device *rdev)
2329{
2330 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2331 int r;
2332
2333 /* Read BIOS */
2334 if (!radeon_get_bios(rdev)) {
2335 if (ASIC_IS_AVIVO(rdev))
2336 return -EINVAL;
2337 }
2338 /* Must be an ATOMBIOS */
2339 if (!rdev->is_atom_bios) {
2340 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2341 return -EINVAL;
2342 }
2343 r = radeon_atombios_init(rdev);
2344 if (r)
2345 return r;
2346
2347 /* Post card if necessary */
2348 if (!radeon_card_posted(rdev)) {
2349 if (!rdev->bios) {
2350 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2351 return -EINVAL;
2352 }
2353 DRM_INFO("GPU not posted. posting now...\n");
2354 atom_asic_init(rdev->mode_info.atom_context);
2355 }
2356 /* init golden registers */
2357 ni_init_golden_registers(rdev);
2358 /* Initialize scratch registers */
2359 r600_scratch_init(rdev);
2360 /* Initialize surface registers */
2361 radeon_surface_init(rdev);
2362 /* Initialize clocks */
2363 radeon_get_clock_info(rdev_to_drm(rdev));
2364 /* Fence driver */
2365 radeon_fence_driver_init(rdev);
2366 /* initialize memory controller */
2367 r = evergreen_mc_init(rdev);
2368 if (r)
2369 return r;
2370 /* Memory manager */
2371 r = radeon_bo_init(rdev);
2372 if (r)
2373 return r;
2374
2375 if (rdev->flags & RADEON_IS_IGP) {
2376 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2377 r = ni_init_microcode(rdev);
2378 if (r) {
2379 DRM_ERROR("Failed to load firmware!\n");
2380 return r;
2381 }
2382 }
2383 } else {
2384 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2385 r = ni_init_microcode(rdev);
2386 if (r) {
2387 DRM_ERROR("Failed to load firmware!\n");
2388 return r;
2389 }
2390 }
2391 }
2392
2393 /* Initialize power management */
2394 radeon_pm_init(rdev);
2395
2396 ring->ring_obj = NULL;
2397 r600_ring_init(rdev, ring, 1024 * 1024);
2398
2399 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2400 ring->ring_obj = NULL;
2401 r600_ring_init(rdev, ring, 64 * 1024);
2402
2403 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2404 ring->ring_obj = NULL;
2405 r600_ring_init(rdev, ring, 64 * 1024);
2406
2407 cayman_uvd_init(rdev);
2408 cayman_vce_init(rdev);
2409
2410 rdev->ih.ring_obj = NULL;
2411 r600_ih_ring_init(rdev, 64 * 1024);
2412
2413 r = r600_pcie_gart_init(rdev);
2414 if (r)
2415 return r;
2416
2417 rdev->accel_working = true;
2418 r = cayman_startup(rdev);
2419 if (r) {
2420 dev_err(rdev->dev, "disabling GPU acceleration\n");
2421 cayman_cp_fini(rdev);
2422 cayman_dma_fini(rdev);
2423 r600_irq_fini(rdev);
2424 if (rdev->flags & RADEON_IS_IGP)
2425 sumo_rlc_fini(rdev);
2426 radeon_wb_fini(rdev);
2427 radeon_ib_pool_fini(rdev);
2428 radeon_vm_manager_fini(rdev);
2429 radeon_irq_kms_fini(rdev);
2430 cayman_pcie_gart_fini(rdev);
2431 rdev->accel_working = false;
2432 }
2433
2434 /* Don't start up if the MC ucode is missing.
2435 * The default clocks and voltages before the MC ucode
2436 * is loaded are not suffient for advanced operations.
2437 *
2438 * We can skip this check for TN, because there is no MC
2439 * ucode.
2440 */
2441 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2442 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2443 return -EINVAL;
2444 }
2445
2446 return 0;
2447}
2448
2449void cayman_fini(struct radeon_device *rdev)
2450{
2451 radeon_pm_fini(rdev);
2452 cayman_cp_fini(rdev);
2453 cayman_dma_fini(rdev);
2454 r600_irq_fini(rdev);
2455 if (rdev->flags & RADEON_IS_IGP)
2456 sumo_rlc_fini(rdev);
2457 radeon_wb_fini(rdev);
2458 radeon_vm_manager_fini(rdev);
2459 radeon_ib_pool_fini(rdev);
2460 radeon_irq_kms_fini(rdev);
2461 uvd_v1_0_fini(rdev);
2462 radeon_uvd_fini(rdev);
2463 if (rdev->has_vce)
2464 radeon_vce_fini(rdev);
2465 cayman_pcie_gart_fini(rdev);
2466 r600_vram_scratch_fini(rdev);
2467 radeon_gem_fini(rdev);
2468 radeon_fence_driver_fini(rdev);
2469 radeon_bo_fini(rdev);
2470 radeon_atombios_fini(rdev);
2471 kfree(rdev->bios);
2472 rdev->bios = NULL;
2473}
2474
2475/*
2476 * vm
2477 */
2478int cayman_vm_init(struct radeon_device *rdev)
2479{
2480 /* number of VMs */
2481 rdev->vm_manager.nvm = 8;
2482 /* base offset of vram pages */
2483 if (rdev->flags & RADEON_IS_IGP) {
2484 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2485 tmp <<= 22;
2486 rdev->vm_manager.vram_base_offset = tmp;
2487 } else
2488 rdev->vm_manager.vram_base_offset = 0;
2489 return 0;
2490}
2491
2492void cayman_vm_fini(struct radeon_device *rdev)
2493{
2494}
2495
2496/**
2497 * cayman_vm_decode_fault - print human readable fault info
2498 *
2499 * @rdev: radeon_device pointer
2500 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2501 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2502 *
2503 * Print human readable fault information (cayman/TN).
2504 */
2505void cayman_vm_decode_fault(struct radeon_device *rdev,
2506 u32 status, u32 addr)
2507{
2508 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2509 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2510 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2511 char *block;
2512
2513 switch (mc_id) {
2514 case 32:
2515 case 16:
2516 case 96:
2517 case 80:
2518 case 160:
2519 case 144:
2520 case 224:
2521 case 208:
2522 block = "CB";
2523 break;
2524 case 33:
2525 case 17:
2526 case 97:
2527 case 81:
2528 case 161:
2529 case 145:
2530 case 225:
2531 case 209:
2532 block = "CB_FMASK";
2533 break;
2534 case 34:
2535 case 18:
2536 case 98:
2537 case 82:
2538 case 162:
2539 case 146:
2540 case 226:
2541 case 210:
2542 block = "CB_CMASK";
2543 break;
2544 case 35:
2545 case 19:
2546 case 99:
2547 case 83:
2548 case 163:
2549 case 147:
2550 case 227:
2551 case 211:
2552 block = "CB_IMMED";
2553 break;
2554 case 36:
2555 case 20:
2556 case 100:
2557 case 84:
2558 case 164:
2559 case 148:
2560 case 228:
2561 case 212:
2562 block = "DB";
2563 break;
2564 case 37:
2565 case 21:
2566 case 101:
2567 case 85:
2568 case 165:
2569 case 149:
2570 case 229:
2571 case 213:
2572 block = "DB_HTILE";
2573 break;
2574 case 38:
2575 case 22:
2576 case 102:
2577 case 86:
2578 case 166:
2579 case 150:
2580 case 230:
2581 case 214:
2582 block = "SX";
2583 break;
2584 case 39:
2585 case 23:
2586 case 103:
2587 case 87:
2588 case 167:
2589 case 151:
2590 case 231:
2591 case 215:
2592 block = "DB_STEN";
2593 break;
2594 case 40:
2595 case 24:
2596 case 104:
2597 case 88:
2598 case 232:
2599 case 216:
2600 case 168:
2601 case 152:
2602 block = "TC_TFETCH";
2603 break;
2604 case 41:
2605 case 25:
2606 case 105:
2607 case 89:
2608 case 233:
2609 case 217:
2610 case 169:
2611 case 153:
2612 block = "TC_VFETCH";
2613 break;
2614 case 42:
2615 case 26:
2616 case 106:
2617 case 90:
2618 case 234:
2619 case 218:
2620 case 170:
2621 case 154:
2622 block = "VC";
2623 break;
2624 case 112:
2625 block = "CP";
2626 break;
2627 case 113:
2628 case 114:
2629 block = "SH";
2630 break;
2631 case 115:
2632 block = "VGT";
2633 break;
2634 case 178:
2635 block = "IH";
2636 break;
2637 case 51:
2638 block = "RLC";
2639 break;
2640 case 55:
2641 block = "DMA";
2642 break;
2643 case 56:
2644 block = "HDP";
2645 break;
2646 default:
2647 block = "unknown";
2648 break;
2649 }
2650
2651 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2652 protections, vmid, addr,
2653 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2654 block, mc_id);
2655}
2656
2657/*
2658 * cayman_vm_flush - vm flush using the CP
2659 *
2660 * Update the page table base and flush the VM TLB
2661 * using the CP (cayman-si).
2662 */
2663void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
2664 unsigned vm_id, uint64_t pd_addr)
2665{
2666 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
2667 radeon_ring_write(ring, pd_addr >> 12);
2668
2669 /* flush hdp cache */
2670 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2671 radeon_ring_write(ring, 0x1);
2672
2673 /* bits 0-7 are the VM contexts0-7 */
2674 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2675 radeon_ring_write(ring, 1 << vm_id);
2676
2677 /* wait for the invalidate to complete */
2678 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2679 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2680 WAIT_REG_MEM_ENGINE(0))); /* me */
2681 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
2682 radeon_ring_write(ring, 0);
2683 radeon_ring_write(ring, 0); /* ref */
2684 radeon_ring_write(ring, 0); /* mask */
2685 radeon_ring_write(ring, 0x20); /* poll interval */
2686
2687 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2688 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2689 radeon_ring_write(ring, 0x0);
2690}
2691
2692int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
2693{
2694 struct atom_clock_dividers dividers;
2695 int r, i;
2696
2697 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2698 ecclk, false, ÷rs);
2699 if (r)
2700 return r;
2701
2702 for (i = 0; i < 100; i++) {
2703 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2704 break;
2705 mdelay(10);
2706 }
2707 if (i == 100)
2708 return -ETIMEDOUT;
2709
2710 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
2711
2712 for (i = 0; i < 100; i++) {
2713 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2714 break;
2715 mdelay(10);
2716 }
2717 if (i == 100)
2718 return -ETIMEDOUT;
2719
2720 return 0;
2721}
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#include <linux/firmware.h>
25#include <linux/slab.h>
26#include <linux/module.h>
27#include <drm/drmP.h>
28#include "radeon.h"
29#include "radeon_asic.h"
30#include "radeon_audio.h"
31#include <drm/radeon_drm.h>
32#include "nid.h"
33#include "atom.h"
34#include "ni_reg.h"
35#include "cayman_blit_shaders.h"
36#include "radeon_ucode.h"
37#include "clearstate_cayman.h"
38
39/*
40 * Indirect registers accessor
41 */
42u32 tn_smc_rreg(struct radeon_device *rdev, u32 reg)
43{
44 unsigned long flags;
45 u32 r;
46
47 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
48 WREG32(TN_SMC_IND_INDEX_0, (reg));
49 r = RREG32(TN_SMC_IND_DATA_0);
50 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
51 return r;
52}
53
54void tn_smc_wreg(struct radeon_device *rdev, u32 reg, u32 v)
55{
56 unsigned long flags;
57
58 spin_lock_irqsave(&rdev->smc_idx_lock, flags);
59 WREG32(TN_SMC_IND_INDEX_0, (reg));
60 WREG32(TN_SMC_IND_DATA_0, (v));
61 spin_unlock_irqrestore(&rdev->smc_idx_lock, flags);
62}
63
64static const u32 tn_rlc_save_restore_register_list[] =
65{
66 0x98fc,
67 0x98f0,
68 0x9834,
69 0x9838,
70 0x9870,
71 0x9874,
72 0x8a14,
73 0x8b24,
74 0x8bcc,
75 0x8b10,
76 0x8c30,
77 0x8d00,
78 0x8d04,
79 0x8c00,
80 0x8c04,
81 0x8c10,
82 0x8c14,
83 0x8d8c,
84 0x8cf0,
85 0x8e38,
86 0x9508,
87 0x9688,
88 0x9608,
89 0x960c,
90 0x9610,
91 0x9614,
92 0x88c4,
93 0x8978,
94 0x88d4,
95 0x900c,
96 0x9100,
97 0x913c,
98 0x90e8,
99 0x9354,
100 0xa008,
101 0x98f8,
102 0x9148,
103 0x914c,
104 0x3f94,
105 0x98f4,
106 0x9b7c,
107 0x3f8c,
108 0x8950,
109 0x8954,
110 0x8a18,
111 0x8b28,
112 0x9144,
113 0x3f90,
114 0x915c,
115 0x9160,
116 0x9178,
117 0x917c,
118 0x9180,
119 0x918c,
120 0x9190,
121 0x9194,
122 0x9198,
123 0x919c,
124 0x91a8,
125 0x91ac,
126 0x91b0,
127 0x91b4,
128 0x91b8,
129 0x91c4,
130 0x91c8,
131 0x91cc,
132 0x91d0,
133 0x91d4,
134 0x91e0,
135 0x91e4,
136 0x91ec,
137 0x91f0,
138 0x91f4,
139 0x9200,
140 0x9204,
141 0x929c,
142 0x8030,
143 0x9150,
144 0x9a60,
145 0x920c,
146 0x9210,
147 0x9228,
148 0x922c,
149 0x9244,
150 0x9248,
151 0x91e8,
152 0x9294,
153 0x9208,
154 0x9224,
155 0x9240,
156 0x9220,
157 0x923c,
158 0x9258,
159 0x9744,
160 0xa200,
161 0xa204,
162 0xa208,
163 0xa20c,
164 0x8d58,
165 0x9030,
166 0x9034,
167 0x9038,
168 0x903c,
169 0x9040,
170 0x9654,
171 0x897c,
172 0xa210,
173 0xa214,
174 0x9868,
175 0xa02c,
176 0x9664,
177 0x9698,
178 0x949c,
179 0x8e10,
180 0x8e18,
181 0x8c50,
182 0x8c58,
183 0x8c60,
184 0x8c68,
185 0x89b4,
186 0x9830,
187 0x802c,
188};
189
190extern bool evergreen_is_display_hung(struct radeon_device *rdev);
191extern void evergreen_print_gpu_status_regs(struct radeon_device *rdev);
192extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
193extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
194extern int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
195extern void evergreen_mc_program(struct radeon_device *rdev);
196extern void evergreen_irq_suspend(struct radeon_device *rdev);
197extern int evergreen_mc_init(struct radeon_device *rdev);
198extern void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
199extern void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
200extern void evergreen_program_aspm(struct radeon_device *rdev);
201extern void sumo_rlc_fini(struct radeon_device *rdev);
202extern int sumo_rlc_init(struct radeon_device *rdev);
203extern void evergreen_gpu_pci_config_reset(struct radeon_device *rdev);
204
205/* Firmware Names */
206MODULE_FIRMWARE("radeon/BARTS_pfp.bin");
207MODULE_FIRMWARE("radeon/BARTS_me.bin");
208MODULE_FIRMWARE("radeon/BARTS_mc.bin");
209MODULE_FIRMWARE("radeon/BARTS_smc.bin");
210MODULE_FIRMWARE("radeon/BTC_rlc.bin");
211MODULE_FIRMWARE("radeon/TURKS_pfp.bin");
212MODULE_FIRMWARE("radeon/TURKS_me.bin");
213MODULE_FIRMWARE("radeon/TURKS_mc.bin");
214MODULE_FIRMWARE("radeon/TURKS_smc.bin");
215MODULE_FIRMWARE("radeon/CAICOS_pfp.bin");
216MODULE_FIRMWARE("radeon/CAICOS_me.bin");
217MODULE_FIRMWARE("radeon/CAICOS_mc.bin");
218MODULE_FIRMWARE("radeon/CAICOS_smc.bin");
219MODULE_FIRMWARE("radeon/CAYMAN_pfp.bin");
220MODULE_FIRMWARE("radeon/CAYMAN_me.bin");
221MODULE_FIRMWARE("radeon/CAYMAN_mc.bin");
222MODULE_FIRMWARE("radeon/CAYMAN_rlc.bin");
223MODULE_FIRMWARE("radeon/CAYMAN_smc.bin");
224MODULE_FIRMWARE("radeon/ARUBA_pfp.bin");
225MODULE_FIRMWARE("radeon/ARUBA_me.bin");
226MODULE_FIRMWARE("radeon/ARUBA_rlc.bin");
227
228
229static const u32 cayman_golden_registers2[] =
230{
231 0x3e5c, 0xffffffff, 0x00000000,
232 0x3e48, 0xffffffff, 0x00000000,
233 0x3e4c, 0xffffffff, 0x00000000,
234 0x3e64, 0xffffffff, 0x00000000,
235 0x3e50, 0xffffffff, 0x00000000,
236 0x3e60, 0xffffffff, 0x00000000
237};
238
239static const u32 cayman_golden_registers[] =
240{
241 0x5eb4, 0xffffffff, 0x00000002,
242 0x5e78, 0x8f311ff1, 0x001000f0,
243 0x3f90, 0xffff0000, 0xff000000,
244 0x9148, 0xffff0000, 0xff000000,
245 0x3f94, 0xffff0000, 0xff000000,
246 0x914c, 0xffff0000, 0xff000000,
247 0xc78, 0x00000080, 0x00000080,
248 0xbd4, 0x70073777, 0x00011003,
249 0xd02c, 0xbfffff1f, 0x08421000,
250 0xd0b8, 0x73773777, 0x02011003,
251 0x5bc0, 0x00200000, 0x50100000,
252 0x98f8, 0x33773777, 0x02011003,
253 0x98fc, 0xffffffff, 0x76541032,
254 0x7030, 0x31000311, 0x00000011,
255 0x2f48, 0x33773777, 0x42010001,
256 0x6b28, 0x00000010, 0x00000012,
257 0x7728, 0x00000010, 0x00000012,
258 0x10328, 0x00000010, 0x00000012,
259 0x10f28, 0x00000010, 0x00000012,
260 0x11b28, 0x00000010, 0x00000012,
261 0x12728, 0x00000010, 0x00000012,
262 0x240c, 0x000007ff, 0x00000000,
263 0x8a14, 0xf000001f, 0x00000007,
264 0x8b24, 0x3fff3fff, 0x00ff0fff,
265 0x8b10, 0x0000ff0f, 0x00000000,
266 0x28a4c, 0x07ffffff, 0x06000000,
267 0x10c, 0x00000001, 0x00010003,
268 0xa02c, 0xffffffff, 0x0000009b,
269 0x913c, 0x0000010f, 0x01000100,
270 0x8c04, 0xf8ff00ff, 0x40600060,
271 0x28350, 0x00000f01, 0x00000000,
272 0x9508, 0x3700001f, 0x00000002,
273 0x960c, 0xffffffff, 0x54763210,
274 0x88c4, 0x001f3ae3, 0x00000082,
275 0x88d0, 0xffffffff, 0x0f40df40,
276 0x88d4, 0x0000001f, 0x00000010,
277 0x8974, 0xffffffff, 0x00000000
278};
279
280static const u32 dvst_golden_registers2[] =
281{
282 0x8f8, 0xffffffff, 0,
283 0x8fc, 0x00380000, 0,
284 0x8f8, 0xffffffff, 1,
285 0x8fc, 0x0e000000, 0
286};
287
288static const u32 dvst_golden_registers[] =
289{
290 0x690, 0x3fff3fff, 0x20c00033,
291 0x918c, 0x0fff0fff, 0x00010006,
292 0x91a8, 0x0fff0fff, 0x00010006,
293 0x9150, 0xffffdfff, 0x6e944040,
294 0x917c, 0x0fff0fff, 0x00030002,
295 0x9198, 0x0fff0fff, 0x00030002,
296 0x915c, 0x0fff0fff, 0x00010000,
297 0x3f90, 0xffff0001, 0xff000000,
298 0x9178, 0x0fff0fff, 0x00070000,
299 0x9194, 0x0fff0fff, 0x00070000,
300 0x9148, 0xffff0001, 0xff000000,
301 0x9190, 0x0fff0fff, 0x00090008,
302 0x91ac, 0x0fff0fff, 0x00090008,
303 0x3f94, 0xffff0000, 0xff000000,
304 0x914c, 0xffff0000, 0xff000000,
305 0x929c, 0x00000fff, 0x00000001,
306 0x55e4, 0xff607fff, 0xfc000100,
307 0x8a18, 0xff000fff, 0x00000100,
308 0x8b28, 0xff000fff, 0x00000100,
309 0x9144, 0xfffc0fff, 0x00000100,
310 0x6ed8, 0x00010101, 0x00010000,
311 0x9830, 0xffffffff, 0x00000000,
312 0x9834, 0xf00fffff, 0x00000400,
313 0x9838, 0xfffffffe, 0x00000000,
314 0xd0c0, 0xff000fff, 0x00000100,
315 0xd02c, 0xbfffff1f, 0x08421000,
316 0xd0b8, 0x73773777, 0x12010001,
317 0x5bb0, 0x000000f0, 0x00000070,
318 0x98f8, 0x73773777, 0x12010001,
319 0x98fc, 0xffffffff, 0x00000010,
320 0x9b7c, 0x00ff0000, 0x00fc0000,
321 0x8030, 0x00001f0f, 0x0000100a,
322 0x2f48, 0x73773777, 0x12010001,
323 0x2408, 0x00030000, 0x000c007f,
324 0x8a14, 0xf000003f, 0x00000007,
325 0x8b24, 0x3fff3fff, 0x00ff0fff,
326 0x8b10, 0x0000ff0f, 0x00000000,
327 0x28a4c, 0x07ffffff, 0x06000000,
328 0x4d8, 0x00000fff, 0x00000100,
329 0xa008, 0xffffffff, 0x00010000,
330 0x913c, 0xffff03ff, 0x01000100,
331 0x8c00, 0x000000ff, 0x00000003,
332 0x8c04, 0xf8ff00ff, 0x40600060,
333 0x8cf0, 0x1fff1fff, 0x08e00410,
334 0x28350, 0x00000f01, 0x00000000,
335 0x9508, 0xf700071f, 0x00000002,
336 0x960c, 0xffffffff, 0x54763210,
337 0x20ef8, 0x01ff01ff, 0x00000002,
338 0x20e98, 0xfffffbff, 0x00200000,
339 0x2015c, 0xffffffff, 0x00000f40,
340 0x88c4, 0x001f3ae3, 0x00000082,
341 0x8978, 0x3fffffff, 0x04050140,
342 0x88d4, 0x0000001f, 0x00000010,
343 0x8974, 0xffffffff, 0x00000000
344};
345
346static const u32 scrapper_golden_registers[] =
347{
348 0x690, 0x3fff3fff, 0x20c00033,
349 0x918c, 0x0fff0fff, 0x00010006,
350 0x918c, 0x0fff0fff, 0x00010006,
351 0x91a8, 0x0fff0fff, 0x00010006,
352 0x91a8, 0x0fff0fff, 0x00010006,
353 0x9150, 0xffffdfff, 0x6e944040,
354 0x9150, 0xffffdfff, 0x6e944040,
355 0x917c, 0x0fff0fff, 0x00030002,
356 0x917c, 0x0fff0fff, 0x00030002,
357 0x9198, 0x0fff0fff, 0x00030002,
358 0x9198, 0x0fff0fff, 0x00030002,
359 0x915c, 0x0fff0fff, 0x00010000,
360 0x915c, 0x0fff0fff, 0x00010000,
361 0x3f90, 0xffff0001, 0xff000000,
362 0x3f90, 0xffff0001, 0xff000000,
363 0x9178, 0x0fff0fff, 0x00070000,
364 0x9178, 0x0fff0fff, 0x00070000,
365 0x9194, 0x0fff0fff, 0x00070000,
366 0x9194, 0x0fff0fff, 0x00070000,
367 0x9148, 0xffff0001, 0xff000000,
368 0x9148, 0xffff0001, 0xff000000,
369 0x9190, 0x0fff0fff, 0x00090008,
370 0x9190, 0x0fff0fff, 0x00090008,
371 0x91ac, 0x0fff0fff, 0x00090008,
372 0x91ac, 0x0fff0fff, 0x00090008,
373 0x3f94, 0xffff0000, 0xff000000,
374 0x3f94, 0xffff0000, 0xff000000,
375 0x914c, 0xffff0000, 0xff000000,
376 0x914c, 0xffff0000, 0xff000000,
377 0x929c, 0x00000fff, 0x00000001,
378 0x929c, 0x00000fff, 0x00000001,
379 0x55e4, 0xff607fff, 0xfc000100,
380 0x8a18, 0xff000fff, 0x00000100,
381 0x8a18, 0xff000fff, 0x00000100,
382 0x8b28, 0xff000fff, 0x00000100,
383 0x8b28, 0xff000fff, 0x00000100,
384 0x9144, 0xfffc0fff, 0x00000100,
385 0x9144, 0xfffc0fff, 0x00000100,
386 0x6ed8, 0x00010101, 0x00010000,
387 0x9830, 0xffffffff, 0x00000000,
388 0x9830, 0xffffffff, 0x00000000,
389 0x9834, 0xf00fffff, 0x00000400,
390 0x9834, 0xf00fffff, 0x00000400,
391 0x9838, 0xfffffffe, 0x00000000,
392 0x9838, 0xfffffffe, 0x00000000,
393 0xd0c0, 0xff000fff, 0x00000100,
394 0xd02c, 0xbfffff1f, 0x08421000,
395 0xd02c, 0xbfffff1f, 0x08421000,
396 0xd0b8, 0x73773777, 0x12010001,
397 0xd0b8, 0x73773777, 0x12010001,
398 0x5bb0, 0x000000f0, 0x00000070,
399 0x98f8, 0x73773777, 0x12010001,
400 0x98f8, 0x73773777, 0x12010001,
401 0x98fc, 0xffffffff, 0x00000010,
402 0x98fc, 0xffffffff, 0x00000010,
403 0x9b7c, 0x00ff0000, 0x00fc0000,
404 0x9b7c, 0x00ff0000, 0x00fc0000,
405 0x8030, 0x00001f0f, 0x0000100a,
406 0x8030, 0x00001f0f, 0x0000100a,
407 0x2f48, 0x73773777, 0x12010001,
408 0x2f48, 0x73773777, 0x12010001,
409 0x2408, 0x00030000, 0x000c007f,
410 0x8a14, 0xf000003f, 0x00000007,
411 0x8a14, 0xf000003f, 0x00000007,
412 0x8b24, 0x3fff3fff, 0x00ff0fff,
413 0x8b24, 0x3fff3fff, 0x00ff0fff,
414 0x8b10, 0x0000ff0f, 0x00000000,
415 0x8b10, 0x0000ff0f, 0x00000000,
416 0x28a4c, 0x07ffffff, 0x06000000,
417 0x28a4c, 0x07ffffff, 0x06000000,
418 0x4d8, 0x00000fff, 0x00000100,
419 0x4d8, 0x00000fff, 0x00000100,
420 0xa008, 0xffffffff, 0x00010000,
421 0xa008, 0xffffffff, 0x00010000,
422 0x913c, 0xffff03ff, 0x01000100,
423 0x913c, 0xffff03ff, 0x01000100,
424 0x90e8, 0x001fffff, 0x010400c0,
425 0x8c00, 0x000000ff, 0x00000003,
426 0x8c00, 0x000000ff, 0x00000003,
427 0x8c04, 0xf8ff00ff, 0x40600060,
428 0x8c04, 0xf8ff00ff, 0x40600060,
429 0x8c30, 0x0000000f, 0x00040005,
430 0x8cf0, 0x1fff1fff, 0x08e00410,
431 0x8cf0, 0x1fff1fff, 0x08e00410,
432 0x900c, 0x00ffffff, 0x0017071f,
433 0x28350, 0x00000f01, 0x00000000,
434 0x28350, 0x00000f01, 0x00000000,
435 0x9508, 0xf700071f, 0x00000002,
436 0x9508, 0xf700071f, 0x00000002,
437 0x9688, 0x00300000, 0x0017000f,
438 0x960c, 0xffffffff, 0x54763210,
439 0x960c, 0xffffffff, 0x54763210,
440 0x20ef8, 0x01ff01ff, 0x00000002,
441 0x20e98, 0xfffffbff, 0x00200000,
442 0x2015c, 0xffffffff, 0x00000f40,
443 0x88c4, 0x001f3ae3, 0x00000082,
444 0x88c4, 0x001f3ae3, 0x00000082,
445 0x8978, 0x3fffffff, 0x04050140,
446 0x8978, 0x3fffffff, 0x04050140,
447 0x88d4, 0x0000001f, 0x00000010,
448 0x88d4, 0x0000001f, 0x00000010,
449 0x8974, 0xffffffff, 0x00000000,
450 0x8974, 0xffffffff, 0x00000000
451};
452
453static void ni_init_golden_registers(struct radeon_device *rdev)
454{
455 switch (rdev->family) {
456 case CHIP_CAYMAN:
457 radeon_program_register_sequence(rdev,
458 cayman_golden_registers,
459 (const u32)ARRAY_SIZE(cayman_golden_registers));
460 radeon_program_register_sequence(rdev,
461 cayman_golden_registers2,
462 (const u32)ARRAY_SIZE(cayman_golden_registers2));
463 break;
464 case CHIP_ARUBA:
465 if ((rdev->pdev->device == 0x9900) ||
466 (rdev->pdev->device == 0x9901) ||
467 (rdev->pdev->device == 0x9903) ||
468 (rdev->pdev->device == 0x9904) ||
469 (rdev->pdev->device == 0x9905) ||
470 (rdev->pdev->device == 0x9906) ||
471 (rdev->pdev->device == 0x9907) ||
472 (rdev->pdev->device == 0x9908) ||
473 (rdev->pdev->device == 0x9909) ||
474 (rdev->pdev->device == 0x990A) ||
475 (rdev->pdev->device == 0x990B) ||
476 (rdev->pdev->device == 0x990C) ||
477 (rdev->pdev->device == 0x990D) ||
478 (rdev->pdev->device == 0x990E) ||
479 (rdev->pdev->device == 0x990F) ||
480 (rdev->pdev->device == 0x9910) ||
481 (rdev->pdev->device == 0x9913) ||
482 (rdev->pdev->device == 0x9917) ||
483 (rdev->pdev->device == 0x9918)) {
484 radeon_program_register_sequence(rdev,
485 dvst_golden_registers,
486 (const u32)ARRAY_SIZE(dvst_golden_registers));
487 radeon_program_register_sequence(rdev,
488 dvst_golden_registers2,
489 (const u32)ARRAY_SIZE(dvst_golden_registers2));
490 } else {
491 radeon_program_register_sequence(rdev,
492 scrapper_golden_registers,
493 (const u32)ARRAY_SIZE(scrapper_golden_registers));
494 radeon_program_register_sequence(rdev,
495 dvst_golden_registers2,
496 (const u32)ARRAY_SIZE(dvst_golden_registers2));
497 }
498 break;
499 default:
500 break;
501 }
502}
503
504#define BTC_IO_MC_REGS_SIZE 29
505
506static const u32 barts_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
507 {0x00000077, 0xff010100},
508 {0x00000078, 0x00000000},
509 {0x00000079, 0x00001434},
510 {0x0000007a, 0xcc08ec08},
511 {0x0000007b, 0x00040000},
512 {0x0000007c, 0x000080c0},
513 {0x0000007d, 0x09000000},
514 {0x0000007e, 0x00210404},
515 {0x00000081, 0x08a8e800},
516 {0x00000082, 0x00030444},
517 {0x00000083, 0x00000000},
518 {0x00000085, 0x00000001},
519 {0x00000086, 0x00000002},
520 {0x00000087, 0x48490000},
521 {0x00000088, 0x20244647},
522 {0x00000089, 0x00000005},
523 {0x0000008b, 0x66030000},
524 {0x0000008c, 0x00006603},
525 {0x0000008d, 0x00000100},
526 {0x0000008f, 0x00001c0a},
527 {0x00000090, 0xff000001},
528 {0x00000094, 0x00101101},
529 {0x00000095, 0x00000fff},
530 {0x00000096, 0x00116fff},
531 {0x00000097, 0x60010000},
532 {0x00000098, 0x10010000},
533 {0x00000099, 0x00006000},
534 {0x0000009a, 0x00001000},
535 {0x0000009f, 0x00946a00}
536};
537
538static const u32 turks_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
539 {0x00000077, 0xff010100},
540 {0x00000078, 0x00000000},
541 {0x00000079, 0x00001434},
542 {0x0000007a, 0xcc08ec08},
543 {0x0000007b, 0x00040000},
544 {0x0000007c, 0x000080c0},
545 {0x0000007d, 0x09000000},
546 {0x0000007e, 0x00210404},
547 {0x00000081, 0x08a8e800},
548 {0x00000082, 0x00030444},
549 {0x00000083, 0x00000000},
550 {0x00000085, 0x00000001},
551 {0x00000086, 0x00000002},
552 {0x00000087, 0x48490000},
553 {0x00000088, 0x20244647},
554 {0x00000089, 0x00000005},
555 {0x0000008b, 0x66030000},
556 {0x0000008c, 0x00006603},
557 {0x0000008d, 0x00000100},
558 {0x0000008f, 0x00001c0a},
559 {0x00000090, 0xff000001},
560 {0x00000094, 0x00101101},
561 {0x00000095, 0x00000fff},
562 {0x00000096, 0x00116fff},
563 {0x00000097, 0x60010000},
564 {0x00000098, 0x10010000},
565 {0x00000099, 0x00006000},
566 {0x0000009a, 0x00001000},
567 {0x0000009f, 0x00936a00}
568};
569
570static const u32 caicos_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
571 {0x00000077, 0xff010100},
572 {0x00000078, 0x00000000},
573 {0x00000079, 0x00001434},
574 {0x0000007a, 0xcc08ec08},
575 {0x0000007b, 0x00040000},
576 {0x0000007c, 0x000080c0},
577 {0x0000007d, 0x09000000},
578 {0x0000007e, 0x00210404},
579 {0x00000081, 0x08a8e800},
580 {0x00000082, 0x00030444},
581 {0x00000083, 0x00000000},
582 {0x00000085, 0x00000001},
583 {0x00000086, 0x00000002},
584 {0x00000087, 0x48490000},
585 {0x00000088, 0x20244647},
586 {0x00000089, 0x00000005},
587 {0x0000008b, 0x66030000},
588 {0x0000008c, 0x00006603},
589 {0x0000008d, 0x00000100},
590 {0x0000008f, 0x00001c0a},
591 {0x00000090, 0xff000001},
592 {0x00000094, 0x00101101},
593 {0x00000095, 0x00000fff},
594 {0x00000096, 0x00116fff},
595 {0x00000097, 0x60010000},
596 {0x00000098, 0x10010000},
597 {0x00000099, 0x00006000},
598 {0x0000009a, 0x00001000},
599 {0x0000009f, 0x00916a00}
600};
601
602static const u32 cayman_io_mc_regs[BTC_IO_MC_REGS_SIZE][2] = {
603 {0x00000077, 0xff010100},
604 {0x00000078, 0x00000000},
605 {0x00000079, 0x00001434},
606 {0x0000007a, 0xcc08ec08},
607 {0x0000007b, 0x00040000},
608 {0x0000007c, 0x000080c0},
609 {0x0000007d, 0x09000000},
610 {0x0000007e, 0x00210404},
611 {0x00000081, 0x08a8e800},
612 {0x00000082, 0x00030444},
613 {0x00000083, 0x00000000},
614 {0x00000085, 0x00000001},
615 {0x00000086, 0x00000002},
616 {0x00000087, 0x48490000},
617 {0x00000088, 0x20244647},
618 {0x00000089, 0x00000005},
619 {0x0000008b, 0x66030000},
620 {0x0000008c, 0x00006603},
621 {0x0000008d, 0x00000100},
622 {0x0000008f, 0x00001c0a},
623 {0x00000090, 0xff000001},
624 {0x00000094, 0x00101101},
625 {0x00000095, 0x00000fff},
626 {0x00000096, 0x00116fff},
627 {0x00000097, 0x60010000},
628 {0x00000098, 0x10010000},
629 {0x00000099, 0x00006000},
630 {0x0000009a, 0x00001000},
631 {0x0000009f, 0x00976b00}
632};
633
634int ni_mc_load_microcode(struct radeon_device *rdev)
635{
636 const __be32 *fw_data;
637 u32 mem_type, running, blackout = 0;
638 u32 *io_mc_regs;
639 int i, ucode_size, regs_size;
640
641 if (!rdev->mc_fw)
642 return -EINVAL;
643
644 switch (rdev->family) {
645 case CHIP_BARTS:
646 io_mc_regs = (u32 *)&barts_io_mc_regs;
647 ucode_size = BTC_MC_UCODE_SIZE;
648 regs_size = BTC_IO_MC_REGS_SIZE;
649 break;
650 case CHIP_TURKS:
651 io_mc_regs = (u32 *)&turks_io_mc_regs;
652 ucode_size = BTC_MC_UCODE_SIZE;
653 regs_size = BTC_IO_MC_REGS_SIZE;
654 break;
655 case CHIP_CAICOS:
656 default:
657 io_mc_regs = (u32 *)&caicos_io_mc_regs;
658 ucode_size = BTC_MC_UCODE_SIZE;
659 regs_size = BTC_IO_MC_REGS_SIZE;
660 break;
661 case CHIP_CAYMAN:
662 io_mc_regs = (u32 *)&cayman_io_mc_regs;
663 ucode_size = CAYMAN_MC_UCODE_SIZE;
664 regs_size = BTC_IO_MC_REGS_SIZE;
665 break;
666 }
667
668 mem_type = (RREG32(MC_SEQ_MISC0) & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT;
669 running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
670
671 if ((mem_type == MC_SEQ_MISC0_GDDR5_VALUE) && (running == 0)) {
672 if (running) {
673 blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
674 WREG32(MC_SHARED_BLACKOUT_CNTL, 1);
675 }
676
677 /* reset the engine and set to writable */
678 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
679 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
680
681 /* load mc io regs */
682 for (i = 0; i < regs_size; i++) {
683 WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
684 WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
685 }
686 /* load the MC ucode */
687 fw_data = (const __be32 *)rdev->mc_fw->data;
688 for (i = 0; i < ucode_size; i++)
689 WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
690
691 /* put the engine back into the active state */
692 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
693 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
694 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
695
696 /* wait for training to complete */
697 for (i = 0; i < rdev->usec_timeout; i++) {
698 if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)
699 break;
700 udelay(1);
701 }
702
703 if (running)
704 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
705 }
706
707 return 0;
708}
709
710int ni_init_microcode(struct radeon_device *rdev)
711{
712 const char *chip_name;
713 const char *rlc_chip_name;
714 size_t pfp_req_size, me_req_size, rlc_req_size, mc_req_size;
715 size_t smc_req_size = 0;
716 char fw_name[30];
717 int err;
718
719 DRM_DEBUG("\n");
720
721 switch (rdev->family) {
722 case CHIP_BARTS:
723 chip_name = "BARTS";
724 rlc_chip_name = "BTC";
725 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
726 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
727 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
728 mc_req_size = BTC_MC_UCODE_SIZE * 4;
729 smc_req_size = ALIGN(BARTS_SMC_UCODE_SIZE, 4);
730 break;
731 case CHIP_TURKS:
732 chip_name = "TURKS";
733 rlc_chip_name = "BTC";
734 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
735 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
736 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
737 mc_req_size = BTC_MC_UCODE_SIZE * 4;
738 smc_req_size = ALIGN(TURKS_SMC_UCODE_SIZE, 4);
739 break;
740 case CHIP_CAICOS:
741 chip_name = "CAICOS";
742 rlc_chip_name = "BTC";
743 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
744 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
745 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
746 mc_req_size = BTC_MC_UCODE_SIZE * 4;
747 smc_req_size = ALIGN(CAICOS_SMC_UCODE_SIZE, 4);
748 break;
749 case CHIP_CAYMAN:
750 chip_name = "CAYMAN";
751 rlc_chip_name = "CAYMAN";
752 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
753 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
754 rlc_req_size = CAYMAN_RLC_UCODE_SIZE * 4;
755 mc_req_size = CAYMAN_MC_UCODE_SIZE * 4;
756 smc_req_size = ALIGN(CAYMAN_SMC_UCODE_SIZE, 4);
757 break;
758 case CHIP_ARUBA:
759 chip_name = "ARUBA";
760 rlc_chip_name = "ARUBA";
761 /* pfp/me same size as CAYMAN */
762 pfp_req_size = CAYMAN_PFP_UCODE_SIZE * 4;
763 me_req_size = CAYMAN_PM4_UCODE_SIZE * 4;
764 rlc_req_size = ARUBA_RLC_UCODE_SIZE * 4;
765 mc_req_size = 0;
766 break;
767 default: BUG();
768 }
769
770 DRM_INFO("Loading %s Microcode\n", chip_name);
771
772 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
773 err = request_firmware(&rdev->pfp_fw, fw_name, rdev->dev);
774 if (err)
775 goto out;
776 if (rdev->pfp_fw->size != pfp_req_size) {
777 printk(KERN_ERR
778 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
779 rdev->pfp_fw->size, fw_name);
780 err = -EINVAL;
781 goto out;
782 }
783
784 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
785 err = request_firmware(&rdev->me_fw, fw_name, rdev->dev);
786 if (err)
787 goto out;
788 if (rdev->me_fw->size != me_req_size) {
789 printk(KERN_ERR
790 "ni_cp: Bogus length %zu in firmware \"%s\"\n",
791 rdev->me_fw->size, fw_name);
792 err = -EINVAL;
793 }
794
795 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
796 err = request_firmware(&rdev->rlc_fw, fw_name, rdev->dev);
797 if (err)
798 goto out;
799 if (rdev->rlc_fw->size != rlc_req_size) {
800 printk(KERN_ERR
801 "ni_rlc: Bogus length %zu in firmware \"%s\"\n",
802 rdev->rlc_fw->size, fw_name);
803 err = -EINVAL;
804 }
805
806 /* no MC ucode on TN */
807 if (!(rdev->flags & RADEON_IS_IGP)) {
808 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
809 err = request_firmware(&rdev->mc_fw, fw_name, rdev->dev);
810 if (err)
811 goto out;
812 if (rdev->mc_fw->size != mc_req_size) {
813 printk(KERN_ERR
814 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
815 rdev->mc_fw->size, fw_name);
816 err = -EINVAL;
817 }
818 }
819
820 if ((rdev->family >= CHIP_BARTS) && (rdev->family <= CHIP_CAYMAN)) {
821 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
822 err = request_firmware(&rdev->smc_fw, fw_name, rdev->dev);
823 if (err) {
824 printk(KERN_ERR
825 "smc: error loading firmware \"%s\"\n",
826 fw_name);
827 release_firmware(rdev->smc_fw);
828 rdev->smc_fw = NULL;
829 err = 0;
830 } else if (rdev->smc_fw->size != smc_req_size) {
831 printk(KERN_ERR
832 "ni_mc: Bogus length %zu in firmware \"%s\"\n",
833 rdev->mc_fw->size, fw_name);
834 err = -EINVAL;
835 }
836 }
837
838out:
839 if (err) {
840 if (err != -EINVAL)
841 printk(KERN_ERR
842 "ni_cp: Failed to load firmware \"%s\"\n",
843 fw_name);
844 release_firmware(rdev->pfp_fw);
845 rdev->pfp_fw = NULL;
846 release_firmware(rdev->me_fw);
847 rdev->me_fw = NULL;
848 release_firmware(rdev->rlc_fw);
849 rdev->rlc_fw = NULL;
850 release_firmware(rdev->mc_fw);
851 rdev->mc_fw = NULL;
852 }
853 return err;
854}
855
856/**
857 * cayman_get_allowed_info_register - fetch the register for the info ioctl
858 *
859 * @rdev: radeon_device pointer
860 * @reg: register offset in bytes
861 * @val: register value
862 *
863 * Returns 0 for success or -EINVAL for an invalid register
864 *
865 */
866int cayman_get_allowed_info_register(struct radeon_device *rdev,
867 u32 reg, u32 *val)
868{
869 switch (reg) {
870 case GRBM_STATUS:
871 case GRBM_STATUS_SE0:
872 case GRBM_STATUS_SE1:
873 case SRBM_STATUS:
874 case SRBM_STATUS2:
875 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
876 case (DMA_STATUS_REG + DMA1_REGISTER_OFFSET):
877 case UVD_STATUS:
878 *val = RREG32(reg);
879 return 0;
880 default:
881 return -EINVAL;
882 }
883}
884
885int tn_get_temp(struct radeon_device *rdev)
886{
887 u32 temp = RREG32_SMC(TN_CURRENT_GNB_TEMP) & 0x7ff;
888 int actual_temp = (temp / 8) - 49;
889
890 return actual_temp * 1000;
891}
892
893/*
894 * Core functions
895 */
896static void cayman_gpu_init(struct radeon_device *rdev)
897{
898 u32 gb_addr_config = 0;
899 u32 mc_shared_chmap, mc_arb_ramcfg;
900 u32 cgts_tcc_disable;
901 u32 sx_debug_1;
902 u32 smx_dc_ctl0;
903 u32 cgts_sm_ctrl_reg;
904 u32 hdp_host_path_cntl;
905 u32 tmp;
906 u32 disabled_rb_mask;
907 int i, j;
908
909 switch (rdev->family) {
910 case CHIP_CAYMAN:
911 rdev->config.cayman.max_shader_engines = 2;
912 rdev->config.cayman.max_pipes_per_simd = 4;
913 rdev->config.cayman.max_tile_pipes = 8;
914 rdev->config.cayman.max_simds_per_se = 12;
915 rdev->config.cayman.max_backends_per_se = 4;
916 rdev->config.cayman.max_texture_channel_caches = 8;
917 rdev->config.cayman.max_gprs = 256;
918 rdev->config.cayman.max_threads = 256;
919 rdev->config.cayman.max_gs_threads = 32;
920 rdev->config.cayman.max_stack_entries = 512;
921 rdev->config.cayman.sx_num_of_sets = 8;
922 rdev->config.cayman.sx_max_export_size = 256;
923 rdev->config.cayman.sx_max_export_pos_size = 64;
924 rdev->config.cayman.sx_max_export_smx_size = 192;
925 rdev->config.cayman.max_hw_contexts = 8;
926 rdev->config.cayman.sq_num_cf_insts = 2;
927
928 rdev->config.cayman.sc_prim_fifo_size = 0x100;
929 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
930 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
931 gb_addr_config = CAYMAN_GB_ADDR_CONFIG_GOLDEN;
932 break;
933 case CHIP_ARUBA:
934 default:
935 rdev->config.cayman.max_shader_engines = 1;
936 rdev->config.cayman.max_pipes_per_simd = 4;
937 rdev->config.cayman.max_tile_pipes = 2;
938 if ((rdev->pdev->device == 0x9900) ||
939 (rdev->pdev->device == 0x9901) ||
940 (rdev->pdev->device == 0x9905) ||
941 (rdev->pdev->device == 0x9906) ||
942 (rdev->pdev->device == 0x9907) ||
943 (rdev->pdev->device == 0x9908) ||
944 (rdev->pdev->device == 0x9909) ||
945 (rdev->pdev->device == 0x990B) ||
946 (rdev->pdev->device == 0x990C) ||
947 (rdev->pdev->device == 0x990F) ||
948 (rdev->pdev->device == 0x9910) ||
949 (rdev->pdev->device == 0x9917) ||
950 (rdev->pdev->device == 0x9999) ||
951 (rdev->pdev->device == 0x999C)) {
952 rdev->config.cayman.max_simds_per_se = 6;
953 rdev->config.cayman.max_backends_per_se = 2;
954 rdev->config.cayman.max_hw_contexts = 8;
955 rdev->config.cayman.sx_max_export_size = 256;
956 rdev->config.cayman.sx_max_export_pos_size = 64;
957 rdev->config.cayman.sx_max_export_smx_size = 192;
958 } else if ((rdev->pdev->device == 0x9903) ||
959 (rdev->pdev->device == 0x9904) ||
960 (rdev->pdev->device == 0x990A) ||
961 (rdev->pdev->device == 0x990D) ||
962 (rdev->pdev->device == 0x990E) ||
963 (rdev->pdev->device == 0x9913) ||
964 (rdev->pdev->device == 0x9918) ||
965 (rdev->pdev->device == 0x999D)) {
966 rdev->config.cayman.max_simds_per_se = 4;
967 rdev->config.cayman.max_backends_per_se = 2;
968 rdev->config.cayman.max_hw_contexts = 8;
969 rdev->config.cayman.sx_max_export_size = 256;
970 rdev->config.cayman.sx_max_export_pos_size = 64;
971 rdev->config.cayman.sx_max_export_smx_size = 192;
972 } else if ((rdev->pdev->device == 0x9919) ||
973 (rdev->pdev->device == 0x9990) ||
974 (rdev->pdev->device == 0x9991) ||
975 (rdev->pdev->device == 0x9994) ||
976 (rdev->pdev->device == 0x9995) ||
977 (rdev->pdev->device == 0x9996) ||
978 (rdev->pdev->device == 0x999A) ||
979 (rdev->pdev->device == 0x99A0)) {
980 rdev->config.cayman.max_simds_per_se = 3;
981 rdev->config.cayman.max_backends_per_se = 1;
982 rdev->config.cayman.max_hw_contexts = 4;
983 rdev->config.cayman.sx_max_export_size = 128;
984 rdev->config.cayman.sx_max_export_pos_size = 32;
985 rdev->config.cayman.sx_max_export_smx_size = 96;
986 } else {
987 rdev->config.cayman.max_simds_per_se = 2;
988 rdev->config.cayman.max_backends_per_se = 1;
989 rdev->config.cayman.max_hw_contexts = 4;
990 rdev->config.cayman.sx_max_export_size = 128;
991 rdev->config.cayman.sx_max_export_pos_size = 32;
992 rdev->config.cayman.sx_max_export_smx_size = 96;
993 }
994 rdev->config.cayman.max_texture_channel_caches = 2;
995 rdev->config.cayman.max_gprs = 256;
996 rdev->config.cayman.max_threads = 256;
997 rdev->config.cayman.max_gs_threads = 32;
998 rdev->config.cayman.max_stack_entries = 512;
999 rdev->config.cayman.sx_num_of_sets = 8;
1000 rdev->config.cayman.sq_num_cf_insts = 2;
1001
1002 rdev->config.cayman.sc_prim_fifo_size = 0x40;
1003 rdev->config.cayman.sc_hiz_tile_fifo_size = 0x30;
1004 rdev->config.cayman.sc_earlyz_tile_fifo_size = 0x130;
1005 gb_addr_config = ARUBA_GB_ADDR_CONFIG_GOLDEN;
1006 break;
1007 }
1008
1009 /* Initialize HDP */
1010 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1011 WREG32((0x2c14 + j), 0x00000000);
1012 WREG32((0x2c18 + j), 0x00000000);
1013 WREG32((0x2c1c + j), 0x00000000);
1014 WREG32((0x2c20 + j), 0x00000000);
1015 WREG32((0x2c24 + j), 0x00000000);
1016 }
1017
1018 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1019 WREG32(SRBM_INT_CNTL, 0x1);
1020 WREG32(SRBM_INT_ACK, 0x1);
1021
1022 evergreen_fix_pci_max_read_req_size(rdev);
1023
1024 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1025 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1026
1027 tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1028 rdev->config.cayman.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1029 if (rdev->config.cayman.mem_row_size_in_kb > 4)
1030 rdev->config.cayman.mem_row_size_in_kb = 4;
1031 /* XXX use MC settings? */
1032 rdev->config.cayman.shader_engine_tile_size = 32;
1033 rdev->config.cayman.num_gpus = 1;
1034 rdev->config.cayman.multi_gpu_tile_size = 64;
1035
1036 tmp = (gb_addr_config & NUM_PIPES_MASK) >> NUM_PIPES_SHIFT;
1037 rdev->config.cayman.num_tile_pipes = (1 << tmp);
1038 tmp = (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
1039 rdev->config.cayman.mem_max_burst_length_bytes = (tmp + 1) * 256;
1040 tmp = (gb_addr_config & NUM_SHADER_ENGINES_MASK) >> NUM_SHADER_ENGINES_SHIFT;
1041 rdev->config.cayman.num_shader_engines = tmp + 1;
1042 tmp = (gb_addr_config & NUM_GPUS_MASK) >> NUM_GPUS_SHIFT;
1043 rdev->config.cayman.num_gpus = tmp + 1;
1044 tmp = (gb_addr_config & MULTI_GPU_TILE_SIZE_MASK) >> MULTI_GPU_TILE_SIZE_SHIFT;
1045 rdev->config.cayman.multi_gpu_tile_size = 1 << tmp;
1046 tmp = (gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT;
1047 rdev->config.cayman.mem_row_size_in_kb = 1 << tmp;
1048
1049
1050 /* setup tiling info dword. gb_addr_config is not adequate since it does
1051 * not have bank info, so create a custom tiling dword.
1052 * bits 3:0 num_pipes
1053 * bits 7:4 num_banks
1054 * bits 11:8 group_size
1055 * bits 15:12 row_size
1056 */
1057 rdev->config.cayman.tile_config = 0;
1058 switch (rdev->config.cayman.num_tile_pipes) {
1059 case 1:
1060 default:
1061 rdev->config.cayman.tile_config |= (0 << 0);
1062 break;
1063 case 2:
1064 rdev->config.cayman.tile_config |= (1 << 0);
1065 break;
1066 case 4:
1067 rdev->config.cayman.tile_config |= (2 << 0);
1068 break;
1069 case 8:
1070 rdev->config.cayman.tile_config |= (3 << 0);
1071 break;
1072 }
1073
1074 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
1075 if (rdev->flags & RADEON_IS_IGP)
1076 rdev->config.cayman.tile_config |= 1 << 4;
1077 else {
1078 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1079 case 0: /* four banks */
1080 rdev->config.cayman.tile_config |= 0 << 4;
1081 break;
1082 case 1: /* eight banks */
1083 rdev->config.cayman.tile_config |= 1 << 4;
1084 break;
1085 case 2: /* sixteen banks */
1086 default:
1087 rdev->config.cayman.tile_config |= 2 << 4;
1088 break;
1089 }
1090 }
1091 rdev->config.cayman.tile_config |=
1092 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1093 rdev->config.cayman.tile_config |=
1094 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1095
1096 tmp = 0;
1097 for (i = (rdev->config.cayman.max_shader_engines - 1); i >= 0; i--) {
1098 u32 rb_disable_bitmap;
1099
1100 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1101 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1102 rb_disable_bitmap = (RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000) >> 16;
1103 tmp <<= 4;
1104 tmp |= rb_disable_bitmap;
1105 }
1106 /* enabled rb are just the one not disabled :) */
1107 disabled_rb_mask = tmp;
1108 tmp = 0;
1109 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1110 tmp |= (1 << i);
1111 /* if all the backends are disabled, fix it up here */
1112 if ((disabled_rb_mask & tmp) == tmp) {
1113 for (i = 0; i < (rdev->config.cayman.max_backends_per_se * rdev->config.cayman.max_shader_engines); i++)
1114 disabled_rb_mask &= ~(1 << i);
1115 }
1116
1117 for (i = 0; i < rdev->config.cayman.max_shader_engines; i++) {
1118 u32 simd_disable_bitmap;
1119
1120 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1121 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_INDEX(i));
1122 simd_disable_bitmap = (RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffff0000) >> 16;
1123 simd_disable_bitmap |= 0xffffffff << rdev->config.cayman.max_simds_per_se;
1124 tmp <<= 16;
1125 tmp |= simd_disable_bitmap;
1126 }
1127 rdev->config.cayman.active_simds = hweight32(~tmp);
1128
1129 WREG32(GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1130 WREG32(RLC_GFX_INDEX, INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES);
1131
1132 WREG32(GB_ADDR_CONFIG, gb_addr_config);
1133 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1134 if (ASIC_IS_DCE6(rdev))
1135 WREG32(DMIF_ADDR_CALC, gb_addr_config);
1136 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1137 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1138 WREG32(DMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1139 WREG32(UVD_UDEC_ADDR_CONFIG, gb_addr_config);
1140 WREG32(UVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1141 WREG32(UVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1142
1143 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1144 (rdev->flags & RADEON_IS_IGP)) {
1145 if ((disabled_rb_mask & 3) == 2) {
1146 /* RB1 disabled, RB0 enabled */
1147 tmp = 0x00000000;
1148 } else {
1149 /* RB0 disabled, RB1 enabled */
1150 tmp = 0x11111111;
1151 }
1152 } else {
1153 tmp = gb_addr_config & NUM_PIPES_MASK;
1154 tmp = r6xx_remap_render_backend(rdev, tmp,
1155 rdev->config.cayman.max_backends_per_se *
1156 rdev->config.cayman.max_shader_engines,
1157 CAYMAN_MAX_BACKENDS, disabled_rb_mask);
1158 }
1159 WREG32(GB_BACKEND_MAP, tmp);
1160
1161 cgts_tcc_disable = 0xffff0000;
1162 for (i = 0; i < rdev->config.cayman.max_texture_channel_caches; i++)
1163 cgts_tcc_disable &= ~(1 << (16 + i));
1164 WREG32(CGTS_TCC_DISABLE, cgts_tcc_disable);
1165 WREG32(CGTS_SYS_TCC_DISABLE, cgts_tcc_disable);
1166 WREG32(CGTS_USER_SYS_TCC_DISABLE, cgts_tcc_disable);
1167 WREG32(CGTS_USER_TCC_DISABLE, cgts_tcc_disable);
1168
1169 /* reprogram the shader complex */
1170 cgts_sm_ctrl_reg = RREG32(CGTS_SM_CTRL_REG);
1171 for (i = 0; i < 16; i++)
1172 WREG32(CGTS_SM_CTRL_REG, OVERRIDE);
1173 WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
1174
1175 /* set HW defaults for 3D engine */
1176 WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1177
1178 sx_debug_1 = RREG32(SX_DEBUG_1);
1179 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1180 WREG32(SX_DEBUG_1, sx_debug_1);
1181
1182 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1183 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1184 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
1185 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1186
1187 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
1188
1189 /* need to be explicitly zero-ed */
1190 WREG32(VGT_OFFCHIP_LDS_BASE, 0);
1191 WREG32(SQ_LSTMP_RING_BASE, 0);
1192 WREG32(SQ_HSTMP_RING_BASE, 0);
1193 WREG32(SQ_ESTMP_RING_BASE, 0);
1194 WREG32(SQ_GSTMP_RING_BASE, 0);
1195 WREG32(SQ_VSTMP_RING_BASE, 0);
1196 WREG32(SQ_PSTMP_RING_BASE, 0);
1197
1198 WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
1199
1200 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
1201 POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
1202 SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
1203
1204 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
1205 SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
1206 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
1207
1208
1209 WREG32(VGT_NUM_INSTANCES, 1);
1210
1211 WREG32(CP_PERFMON_CNTL, 0);
1212
1213 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
1214 FETCH_FIFO_HIWATER(0x4) |
1215 DONE_FIFO_HIWATER(0xe0) |
1216 ALU_UPDATE_FIFO_HIWATER(0x8)));
1217
1218 WREG32(SQ_GPR_RESOURCE_MGMT_1, NUM_CLAUSE_TEMP_GPRS(4));
1219 WREG32(SQ_CONFIG, (VC_ENABLE |
1220 EXPORT_SRC_C |
1221 GFX_PRIO(0) |
1222 CS1_PRIO(0) |
1223 CS2_PRIO(1)));
1224 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, DYN_GPR_ENABLE);
1225
1226 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1227 FORCE_EOV_MAX_REZ_CNT(255)));
1228
1229 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1230 AUTO_INVLD_EN(ES_AND_GS_AUTO));
1231
1232 WREG32(VGT_GS_VERTEX_REUSE, 16);
1233 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1234
1235 WREG32(CB_PERF_CTR0_SEL_0, 0);
1236 WREG32(CB_PERF_CTR0_SEL_1, 0);
1237 WREG32(CB_PERF_CTR1_SEL_0, 0);
1238 WREG32(CB_PERF_CTR1_SEL_1, 0);
1239 WREG32(CB_PERF_CTR2_SEL_0, 0);
1240 WREG32(CB_PERF_CTR2_SEL_1, 0);
1241 WREG32(CB_PERF_CTR3_SEL_0, 0);
1242 WREG32(CB_PERF_CTR3_SEL_1, 0);
1243
1244 tmp = RREG32(HDP_MISC_CNTL);
1245 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1246 WREG32(HDP_MISC_CNTL, tmp);
1247
1248 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1249 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1250
1251 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1252
1253 udelay(50);
1254
1255 /* set clockgating golden values on TN */
1256 if (rdev->family == CHIP_ARUBA) {
1257 tmp = RREG32_CG(CG_CGTT_LOCAL_0);
1258 tmp &= ~0x00380000;
1259 WREG32_CG(CG_CGTT_LOCAL_0, tmp);
1260 tmp = RREG32_CG(CG_CGTT_LOCAL_1);
1261 tmp &= ~0x0e000000;
1262 WREG32_CG(CG_CGTT_LOCAL_1, tmp);
1263 }
1264}
1265
1266/*
1267 * GART
1268 */
1269void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev)
1270{
1271 /* flush hdp cache */
1272 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
1273
1274 /* bits 0-7 are the VM contexts0-7 */
1275 WREG32(VM_INVALIDATE_REQUEST, 1);
1276}
1277
1278static int cayman_pcie_gart_enable(struct radeon_device *rdev)
1279{
1280 int i, r;
1281
1282 if (rdev->gart.robj == NULL) {
1283 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1284 return -EINVAL;
1285 }
1286 r = radeon_gart_table_vram_pin(rdev);
1287 if (r)
1288 return r;
1289 /* Setup TLB control */
1290 WREG32(MC_VM_MX_L1_TLB_CNTL,
1291 (0xA << 7) |
1292 ENABLE_L1_TLB |
1293 ENABLE_L1_FRAGMENT_PROCESSING |
1294 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1295 ENABLE_ADVANCED_DRIVER_MODEL |
1296 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1297 /* Setup L2 cache */
1298 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
1299 ENABLE_L2_FRAGMENT_PROCESSING |
1300 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1301 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1302 EFFECTIVE_L2_QUEUE_SIZE(7) |
1303 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1304 WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
1305 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1306 BANK_SELECT(6) |
1307 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1308 /* setup context0 */
1309 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1310 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1311 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1312 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1313 (u32)(rdev->dummy_page.addr >> 12));
1314 WREG32(VM_CONTEXT0_CNTL2, 0);
1315 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1316 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1317
1318 WREG32(0x15D4, 0);
1319 WREG32(0x15D8, 0);
1320 WREG32(0x15DC, 0);
1321
1322 /* empty context1-7 */
1323 /* Assign the pt base to something valid for now; the pts used for
1324 * the VMs are determined by the application and setup and assigned
1325 * on the fly in the vm part of radeon_gart.c
1326 */
1327 for (i = 1; i < 8; i++) {
1328 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR + (i << 2), 0);
1329 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR + (i << 2),
1330 rdev->vm_manager.max_pfn - 1);
1331 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
1332 rdev->vm_manager.saved_table_addr[i]);
1333 }
1334
1335 /* enable context1-7 */
1336 WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
1337 (u32)(rdev->dummy_page.addr >> 12));
1338 WREG32(VM_CONTEXT1_CNTL2, 4);
1339 WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
1340 PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
1341 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1342 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1343 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1344 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
1345 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
1346 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
1347 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
1348 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
1349 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
1350 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
1351 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
1352 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
1353
1354 cayman_pcie_gart_tlb_flush(rdev);
1355 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1356 (unsigned)(rdev->mc.gtt_size >> 20),
1357 (unsigned long long)rdev->gart.table_addr);
1358 rdev->gart.ready = true;
1359 return 0;
1360}
1361
1362static void cayman_pcie_gart_disable(struct radeon_device *rdev)
1363{
1364 unsigned i;
1365
1366 for (i = 1; i < 8; ++i) {
1367 rdev->vm_manager.saved_table_addr[i] = RREG32(
1368 VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2));
1369 }
1370
1371 /* Disable all tables */
1372 WREG32(VM_CONTEXT0_CNTL, 0);
1373 WREG32(VM_CONTEXT1_CNTL, 0);
1374 /* Setup TLB control */
1375 WREG32(MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_FRAGMENT_PROCESSING |
1376 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1377 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
1378 /* Setup L2 cache */
1379 WREG32(VM_L2_CNTL, ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1380 ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
1381 EFFECTIVE_L2_QUEUE_SIZE(7) |
1382 CONTEXT1_IDENTITY_ACCESS_MODE(1));
1383 WREG32(VM_L2_CNTL2, 0);
1384 WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
1385 L2_CACHE_BIGK_FRAGMENT_SIZE(6));
1386 radeon_gart_table_vram_unpin(rdev);
1387}
1388
1389static void cayman_pcie_gart_fini(struct radeon_device *rdev)
1390{
1391 cayman_pcie_gart_disable(rdev);
1392 radeon_gart_table_vram_free(rdev);
1393 radeon_gart_fini(rdev);
1394}
1395
1396void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
1397 int ring, u32 cp_int_cntl)
1398{
1399 WREG32(SRBM_GFX_CNTL, RINGID(ring));
1400 WREG32(CP_INT_CNTL, cp_int_cntl);
1401}
1402
1403/*
1404 * CP.
1405 */
1406void cayman_fence_ring_emit(struct radeon_device *rdev,
1407 struct radeon_fence *fence)
1408{
1409 struct radeon_ring *ring = &rdev->ring[fence->ring];
1410 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1411 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1412 PACKET3_SH_ACTION_ENA;
1413
1414 /* flush read cache over gart for this vmid */
1415 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1416 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1417 radeon_ring_write(ring, 0xFFFFFFFF);
1418 radeon_ring_write(ring, 0);
1419 radeon_ring_write(ring, 10); /* poll interval */
1420 /* EVENT_WRITE_EOP - flush caches, send int */
1421 radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1422 radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
1423 radeon_ring_write(ring, lower_32_bits(addr));
1424 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
1425 radeon_ring_write(ring, fence->seq);
1426 radeon_ring_write(ring, 0);
1427}
1428
1429void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1430{
1431 struct radeon_ring *ring = &rdev->ring[ib->ring];
1432 unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0;
1433 u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA |
1434 PACKET3_SH_ACTION_ENA;
1435
1436 /* set to DX10/11 mode */
1437 radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1438 radeon_ring_write(ring, 1);
1439
1440 if (ring->rptr_save_reg) {
1441 uint32_t next_rptr = ring->wptr + 3 + 4 + 8;
1442 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1443 radeon_ring_write(ring, ((ring->rptr_save_reg -
1444 PACKET3_SET_CONFIG_REG_START) >> 2));
1445 radeon_ring_write(ring, next_rptr);
1446 }
1447
1448 radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1449 radeon_ring_write(ring,
1450#ifdef __BIG_ENDIAN
1451 (2 << 0) |
1452#endif
1453 (ib->gpu_addr & 0xFFFFFFFC));
1454 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1455 radeon_ring_write(ring, ib->length_dw | (vm_id << 24));
1456
1457 /* flush read cache over gart for this vmid */
1458 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1459 radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl);
1460 radeon_ring_write(ring, 0xFFFFFFFF);
1461 radeon_ring_write(ring, 0);
1462 radeon_ring_write(ring, (vm_id << 24) | 10); /* poll interval */
1463}
1464
1465static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
1466{
1467 if (enable)
1468 WREG32(CP_ME_CNTL, 0);
1469 else {
1470 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1471 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1472 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1473 WREG32(SCRATCH_UMSK, 0);
1474 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1475 }
1476}
1477
1478u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
1479 struct radeon_ring *ring)
1480{
1481 u32 rptr;
1482
1483 if (rdev->wb.enabled)
1484 rptr = rdev->wb.wb[ring->rptr_offs/4];
1485 else {
1486 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1487 rptr = RREG32(CP_RB0_RPTR);
1488 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1489 rptr = RREG32(CP_RB1_RPTR);
1490 else
1491 rptr = RREG32(CP_RB2_RPTR);
1492 }
1493
1494 return rptr;
1495}
1496
1497u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
1498 struct radeon_ring *ring)
1499{
1500 u32 wptr;
1501
1502 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX)
1503 wptr = RREG32(CP_RB0_WPTR);
1504 else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX)
1505 wptr = RREG32(CP_RB1_WPTR);
1506 else
1507 wptr = RREG32(CP_RB2_WPTR);
1508
1509 return wptr;
1510}
1511
1512void cayman_gfx_set_wptr(struct radeon_device *rdev,
1513 struct radeon_ring *ring)
1514{
1515 if (ring->idx == RADEON_RING_TYPE_GFX_INDEX) {
1516 WREG32(CP_RB0_WPTR, ring->wptr);
1517 (void)RREG32(CP_RB0_WPTR);
1518 } else if (ring->idx == CAYMAN_RING_TYPE_CP1_INDEX) {
1519 WREG32(CP_RB1_WPTR, ring->wptr);
1520 (void)RREG32(CP_RB1_WPTR);
1521 } else {
1522 WREG32(CP_RB2_WPTR, ring->wptr);
1523 (void)RREG32(CP_RB2_WPTR);
1524 }
1525}
1526
1527static int cayman_cp_load_microcode(struct radeon_device *rdev)
1528{
1529 const __be32 *fw_data;
1530 int i;
1531
1532 if (!rdev->me_fw || !rdev->pfp_fw)
1533 return -EINVAL;
1534
1535 cayman_cp_enable(rdev, false);
1536
1537 fw_data = (const __be32 *)rdev->pfp_fw->data;
1538 WREG32(CP_PFP_UCODE_ADDR, 0);
1539 for (i = 0; i < CAYMAN_PFP_UCODE_SIZE; i++)
1540 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1541 WREG32(CP_PFP_UCODE_ADDR, 0);
1542
1543 fw_data = (const __be32 *)rdev->me_fw->data;
1544 WREG32(CP_ME_RAM_WADDR, 0);
1545 for (i = 0; i < CAYMAN_PM4_UCODE_SIZE; i++)
1546 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1547
1548 WREG32(CP_PFP_UCODE_ADDR, 0);
1549 WREG32(CP_ME_RAM_WADDR, 0);
1550 WREG32(CP_ME_RAM_RADDR, 0);
1551 return 0;
1552}
1553
1554static int cayman_cp_start(struct radeon_device *rdev)
1555{
1556 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1557 int r, i;
1558
1559 r = radeon_ring_lock(rdev, ring, 7);
1560 if (r) {
1561 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1562 return r;
1563 }
1564 radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1565 radeon_ring_write(ring, 0x1);
1566 radeon_ring_write(ring, 0x0);
1567 radeon_ring_write(ring, rdev->config.cayman.max_hw_contexts - 1);
1568 radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1569 radeon_ring_write(ring, 0);
1570 radeon_ring_write(ring, 0);
1571 radeon_ring_unlock_commit(rdev, ring, false);
1572
1573 cayman_cp_enable(rdev, true);
1574
1575 r = radeon_ring_lock(rdev, ring, cayman_default_size + 19);
1576 if (r) {
1577 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1578 return r;
1579 }
1580
1581 /* setup clear context state */
1582 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1583 radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1584
1585 for (i = 0; i < cayman_default_size; i++)
1586 radeon_ring_write(ring, cayman_default_state[i]);
1587
1588 radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1589 radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1590
1591 /* set clear context state */
1592 radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1593 radeon_ring_write(ring, 0);
1594
1595 /* SQ_VTX_BASE_VTX_LOC */
1596 radeon_ring_write(ring, 0xc0026f00);
1597 radeon_ring_write(ring, 0x00000000);
1598 radeon_ring_write(ring, 0x00000000);
1599 radeon_ring_write(ring, 0x00000000);
1600
1601 /* Clear consts */
1602 radeon_ring_write(ring, 0xc0036f00);
1603 radeon_ring_write(ring, 0x00000bc4);
1604 radeon_ring_write(ring, 0xffffffff);
1605 radeon_ring_write(ring, 0xffffffff);
1606 radeon_ring_write(ring, 0xffffffff);
1607
1608 radeon_ring_write(ring, 0xc0026900);
1609 radeon_ring_write(ring, 0x00000316);
1610 radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1611 radeon_ring_write(ring, 0x00000010); /* */
1612
1613 radeon_ring_unlock_commit(rdev, ring, false);
1614
1615 /* XXX init other rings */
1616
1617 return 0;
1618}
1619
1620static void cayman_cp_fini(struct radeon_device *rdev)
1621{
1622 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1623 cayman_cp_enable(rdev, false);
1624 radeon_ring_fini(rdev, ring);
1625 radeon_scratch_free(rdev, ring->rptr_save_reg);
1626}
1627
1628static int cayman_cp_resume(struct radeon_device *rdev)
1629{
1630 static const int ridx[] = {
1631 RADEON_RING_TYPE_GFX_INDEX,
1632 CAYMAN_RING_TYPE_CP1_INDEX,
1633 CAYMAN_RING_TYPE_CP2_INDEX
1634 };
1635 static const unsigned cp_rb_cntl[] = {
1636 CP_RB0_CNTL,
1637 CP_RB1_CNTL,
1638 CP_RB2_CNTL,
1639 };
1640 static const unsigned cp_rb_rptr_addr[] = {
1641 CP_RB0_RPTR_ADDR,
1642 CP_RB1_RPTR_ADDR,
1643 CP_RB2_RPTR_ADDR
1644 };
1645 static const unsigned cp_rb_rptr_addr_hi[] = {
1646 CP_RB0_RPTR_ADDR_HI,
1647 CP_RB1_RPTR_ADDR_HI,
1648 CP_RB2_RPTR_ADDR_HI
1649 };
1650 static const unsigned cp_rb_base[] = {
1651 CP_RB0_BASE,
1652 CP_RB1_BASE,
1653 CP_RB2_BASE
1654 };
1655 static const unsigned cp_rb_rptr[] = {
1656 CP_RB0_RPTR,
1657 CP_RB1_RPTR,
1658 CP_RB2_RPTR
1659 };
1660 static const unsigned cp_rb_wptr[] = {
1661 CP_RB0_WPTR,
1662 CP_RB1_WPTR,
1663 CP_RB2_WPTR
1664 };
1665 struct radeon_ring *ring;
1666 int i, r;
1667
1668 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1669 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1670 SOFT_RESET_PA |
1671 SOFT_RESET_SH |
1672 SOFT_RESET_VGT |
1673 SOFT_RESET_SPI |
1674 SOFT_RESET_SX));
1675 RREG32(GRBM_SOFT_RESET);
1676 mdelay(15);
1677 WREG32(GRBM_SOFT_RESET, 0);
1678 RREG32(GRBM_SOFT_RESET);
1679
1680 WREG32(CP_SEM_WAIT_TIMER, 0x0);
1681 WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1682
1683 /* Set the write pointer delay */
1684 WREG32(CP_RB_WPTR_DELAY, 0);
1685
1686 WREG32(CP_DEBUG, (1 << 27));
1687
1688 /* set the wb address whether it's enabled or not */
1689 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1690 WREG32(SCRATCH_UMSK, 0xff);
1691
1692 for (i = 0; i < 3; ++i) {
1693 uint32_t rb_cntl;
1694 uint64_t addr;
1695
1696 /* Set ring buffer size */
1697 ring = &rdev->ring[ridx[i]];
1698 rb_cntl = order_base_2(ring->ring_size / 8);
1699 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1700#ifdef __BIG_ENDIAN
1701 rb_cntl |= BUF_SWAP_32BIT;
1702#endif
1703 WREG32(cp_rb_cntl[i], rb_cntl);
1704
1705 /* set the wb address whether it's enabled or not */
1706 addr = rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET;
1707 WREG32(cp_rb_rptr_addr[i], addr & 0xFFFFFFFC);
1708 WREG32(cp_rb_rptr_addr_hi[i], upper_32_bits(addr) & 0xFF);
1709 }
1710
1711 /* set the rb base addr, this causes an internal reset of ALL rings */
1712 for (i = 0; i < 3; ++i) {
1713 ring = &rdev->ring[ridx[i]];
1714 WREG32(cp_rb_base[i], ring->gpu_addr >> 8);
1715 }
1716
1717 for (i = 0; i < 3; ++i) {
1718 /* Initialize the ring buffer's read and write pointers */
1719 ring = &rdev->ring[ridx[i]];
1720 WREG32_P(cp_rb_cntl[i], RB_RPTR_WR_ENA, ~RB_RPTR_WR_ENA);
1721
1722 ring->wptr = 0;
1723 WREG32(cp_rb_rptr[i], 0);
1724 WREG32(cp_rb_wptr[i], ring->wptr);
1725
1726 mdelay(1);
1727 WREG32_P(cp_rb_cntl[i], 0, ~RB_RPTR_WR_ENA);
1728 }
1729
1730 /* start the rings */
1731 cayman_cp_start(rdev);
1732 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1733 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1734 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1735 /* this only test cp0 */
1736 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1737 if (r) {
1738 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1739 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
1740 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
1741 return r;
1742 }
1743
1744 if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
1745 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1746
1747 return 0;
1748}
1749
1750u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev)
1751{
1752 u32 reset_mask = 0;
1753 u32 tmp;
1754
1755 /* GRBM_STATUS */
1756 tmp = RREG32(GRBM_STATUS);
1757 if (tmp & (PA_BUSY | SC_BUSY |
1758 SH_BUSY | SX_BUSY |
1759 TA_BUSY | VGT_BUSY |
1760 DB_BUSY | CB_BUSY |
1761 GDS_BUSY | SPI_BUSY |
1762 IA_BUSY | IA_BUSY_NO_DMA))
1763 reset_mask |= RADEON_RESET_GFX;
1764
1765 if (tmp & (CF_RQ_PENDING | PF_RQ_PENDING |
1766 CP_BUSY | CP_COHERENCY_BUSY))
1767 reset_mask |= RADEON_RESET_CP;
1768
1769 if (tmp & GRBM_EE_BUSY)
1770 reset_mask |= RADEON_RESET_GRBM | RADEON_RESET_GFX | RADEON_RESET_CP;
1771
1772 /* DMA_STATUS_REG 0 */
1773 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1774 if (!(tmp & DMA_IDLE))
1775 reset_mask |= RADEON_RESET_DMA;
1776
1777 /* DMA_STATUS_REG 1 */
1778 tmp = RREG32(DMA_STATUS_REG + DMA1_REGISTER_OFFSET);
1779 if (!(tmp & DMA_IDLE))
1780 reset_mask |= RADEON_RESET_DMA1;
1781
1782 /* SRBM_STATUS2 */
1783 tmp = RREG32(SRBM_STATUS2);
1784 if (tmp & DMA_BUSY)
1785 reset_mask |= RADEON_RESET_DMA;
1786
1787 if (tmp & DMA1_BUSY)
1788 reset_mask |= RADEON_RESET_DMA1;
1789
1790 /* SRBM_STATUS */
1791 tmp = RREG32(SRBM_STATUS);
1792 if (tmp & (RLC_RQ_PENDING | RLC_BUSY))
1793 reset_mask |= RADEON_RESET_RLC;
1794
1795 if (tmp & IH_BUSY)
1796 reset_mask |= RADEON_RESET_IH;
1797
1798 if (tmp & SEM_BUSY)
1799 reset_mask |= RADEON_RESET_SEM;
1800
1801 if (tmp & GRBM_RQ_PENDING)
1802 reset_mask |= RADEON_RESET_GRBM;
1803
1804 if (tmp & VMC_BUSY)
1805 reset_mask |= RADEON_RESET_VMC;
1806
1807 if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
1808 MCC_BUSY | MCD_BUSY))
1809 reset_mask |= RADEON_RESET_MC;
1810
1811 if (evergreen_is_display_hung(rdev))
1812 reset_mask |= RADEON_RESET_DISPLAY;
1813
1814 /* VM_L2_STATUS */
1815 tmp = RREG32(VM_L2_STATUS);
1816 if (tmp & L2_BUSY)
1817 reset_mask |= RADEON_RESET_VMC;
1818
1819 /* Skip MC reset as it's mostly likely not hung, just busy */
1820 if (reset_mask & RADEON_RESET_MC) {
1821 DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
1822 reset_mask &= ~RADEON_RESET_MC;
1823 }
1824
1825 return reset_mask;
1826}
1827
1828static void cayman_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
1829{
1830 struct evergreen_mc_save save;
1831 u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
1832 u32 tmp;
1833
1834 if (reset_mask == 0)
1835 return;
1836
1837 dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
1838
1839 evergreen_print_gpu_status_regs(rdev);
1840 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_ADDR 0x%08X\n",
1841 RREG32(0x14F8));
1842 dev_info(rdev->dev, " VM_CONTEXT0_PROTECTION_FAULT_STATUS 0x%08X\n",
1843 RREG32(0x14D8));
1844 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
1845 RREG32(0x14FC));
1846 dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
1847 RREG32(0x14DC));
1848
1849 /* Disable CP parsing/prefetching */
1850 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1851
1852 if (reset_mask & RADEON_RESET_DMA) {
1853 /* dma0 */
1854 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1855 tmp &= ~DMA_RB_ENABLE;
1856 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
1857 }
1858
1859 if (reset_mask & RADEON_RESET_DMA1) {
1860 /* dma1 */
1861 tmp = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET);
1862 tmp &= ~DMA_RB_ENABLE;
1863 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
1864 }
1865
1866 udelay(50);
1867
1868 evergreen_mc_stop(rdev, &save);
1869 if (evergreen_mc_wait_for_idle(rdev)) {
1870 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1871 }
1872
1873 if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE)) {
1874 grbm_soft_reset = SOFT_RESET_CB |
1875 SOFT_RESET_DB |
1876 SOFT_RESET_GDS |
1877 SOFT_RESET_PA |
1878 SOFT_RESET_SC |
1879 SOFT_RESET_SPI |
1880 SOFT_RESET_SH |
1881 SOFT_RESET_SX |
1882 SOFT_RESET_TC |
1883 SOFT_RESET_TA |
1884 SOFT_RESET_VGT |
1885 SOFT_RESET_IA;
1886 }
1887
1888 if (reset_mask & RADEON_RESET_CP) {
1889 grbm_soft_reset |= SOFT_RESET_CP | SOFT_RESET_VGT;
1890
1891 srbm_soft_reset |= SOFT_RESET_GRBM;
1892 }
1893
1894 if (reset_mask & RADEON_RESET_DMA)
1895 srbm_soft_reset |= SOFT_RESET_DMA;
1896
1897 if (reset_mask & RADEON_RESET_DMA1)
1898 srbm_soft_reset |= SOFT_RESET_DMA1;
1899
1900 if (reset_mask & RADEON_RESET_DISPLAY)
1901 srbm_soft_reset |= SOFT_RESET_DC;
1902
1903 if (reset_mask & RADEON_RESET_RLC)
1904 srbm_soft_reset |= SOFT_RESET_RLC;
1905
1906 if (reset_mask & RADEON_RESET_SEM)
1907 srbm_soft_reset |= SOFT_RESET_SEM;
1908
1909 if (reset_mask & RADEON_RESET_IH)
1910 srbm_soft_reset |= SOFT_RESET_IH;
1911
1912 if (reset_mask & RADEON_RESET_GRBM)
1913 srbm_soft_reset |= SOFT_RESET_GRBM;
1914
1915 if (reset_mask & RADEON_RESET_VMC)
1916 srbm_soft_reset |= SOFT_RESET_VMC;
1917
1918 if (!(rdev->flags & RADEON_IS_IGP)) {
1919 if (reset_mask & RADEON_RESET_MC)
1920 srbm_soft_reset |= SOFT_RESET_MC;
1921 }
1922
1923 if (grbm_soft_reset) {
1924 tmp = RREG32(GRBM_SOFT_RESET);
1925 tmp |= grbm_soft_reset;
1926 dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
1927 WREG32(GRBM_SOFT_RESET, tmp);
1928 tmp = RREG32(GRBM_SOFT_RESET);
1929
1930 udelay(50);
1931
1932 tmp &= ~grbm_soft_reset;
1933 WREG32(GRBM_SOFT_RESET, tmp);
1934 tmp = RREG32(GRBM_SOFT_RESET);
1935 }
1936
1937 if (srbm_soft_reset) {
1938 tmp = RREG32(SRBM_SOFT_RESET);
1939 tmp |= srbm_soft_reset;
1940 dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1941 WREG32(SRBM_SOFT_RESET, tmp);
1942 tmp = RREG32(SRBM_SOFT_RESET);
1943
1944 udelay(50);
1945
1946 tmp &= ~srbm_soft_reset;
1947 WREG32(SRBM_SOFT_RESET, tmp);
1948 tmp = RREG32(SRBM_SOFT_RESET);
1949 }
1950
1951 /* Wait a little for things to settle down */
1952 udelay(50);
1953
1954 evergreen_mc_resume(rdev, &save);
1955 udelay(50);
1956
1957 evergreen_print_gpu_status_regs(rdev);
1958}
1959
1960int cayman_asic_reset(struct radeon_device *rdev, bool hard)
1961{
1962 u32 reset_mask;
1963
1964 if (hard) {
1965 evergreen_gpu_pci_config_reset(rdev);
1966 return 0;
1967 }
1968
1969 reset_mask = cayman_gpu_check_soft_reset(rdev);
1970
1971 if (reset_mask)
1972 r600_set_bios_scratch_engine_hung(rdev, true);
1973
1974 cayman_gpu_soft_reset(rdev, reset_mask);
1975
1976 reset_mask = cayman_gpu_check_soft_reset(rdev);
1977
1978 if (reset_mask)
1979 evergreen_gpu_pci_config_reset(rdev);
1980
1981 r600_set_bios_scratch_engine_hung(rdev, false);
1982
1983 return 0;
1984}
1985
1986/**
1987 * cayman_gfx_is_lockup - Check if the GFX engine is locked up
1988 *
1989 * @rdev: radeon_device pointer
1990 * @ring: radeon_ring structure holding ring information
1991 *
1992 * Check if the GFX engine is locked up.
1993 * Returns true if the engine appears to be locked up, false if not.
1994 */
1995bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1996{
1997 u32 reset_mask = cayman_gpu_check_soft_reset(rdev);
1998
1999 if (!(reset_mask & (RADEON_RESET_GFX |
2000 RADEON_RESET_COMPUTE |
2001 RADEON_RESET_CP))) {
2002 radeon_ring_lockup_update(rdev, ring);
2003 return false;
2004 }
2005 return radeon_ring_test_lockup(rdev, ring);
2006}
2007
2008static void cayman_uvd_init(struct radeon_device *rdev)
2009{
2010 int r;
2011
2012 if (!rdev->has_uvd)
2013 return;
2014
2015 r = radeon_uvd_init(rdev);
2016 if (r) {
2017 dev_err(rdev->dev, "failed UVD (%d) init.\n", r);
2018 /*
2019 * At this point rdev->uvd.vcpu_bo is NULL which trickles down
2020 * to early fails uvd_v2_2_resume() and thus nothing happens
2021 * there. So it is pointless to try to go through that code
2022 * hence why we disable uvd here.
2023 */
2024 rdev->has_uvd = 0;
2025 return;
2026 }
2027 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
2028 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX], 4096);
2029}
2030
2031static void cayman_uvd_start(struct radeon_device *rdev)
2032{
2033 int r;
2034
2035 if (!rdev->has_uvd)
2036 return;
2037
2038 r = uvd_v2_2_resume(rdev);
2039 if (r) {
2040 dev_err(rdev->dev, "failed UVD resume (%d).\n", r);
2041 goto error;
2042 }
2043 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_UVD_INDEX);
2044 if (r) {
2045 dev_err(rdev->dev, "failed initializing UVD fences (%d).\n", r);
2046 goto error;
2047 }
2048 return;
2049
2050error:
2051 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
2052}
2053
2054static void cayman_uvd_resume(struct radeon_device *rdev)
2055{
2056 struct radeon_ring *ring;
2057 int r;
2058
2059 if (!rdev->has_uvd || !rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size)
2060 return;
2061
2062 ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
2063 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, PACKET0(UVD_NO_OP, 0));
2064 if (r) {
2065 dev_err(rdev->dev, "failed initializing UVD ring (%d).\n", r);
2066 return;
2067 }
2068 r = uvd_v1_0_init(rdev);
2069 if (r) {
2070 dev_err(rdev->dev, "failed initializing UVD (%d).\n", r);
2071 return;
2072 }
2073}
2074
2075static void cayman_vce_init(struct radeon_device *rdev)
2076{
2077 int r;
2078
2079 /* Only set for CHIP_ARUBA */
2080 if (!rdev->has_vce)
2081 return;
2082
2083 r = radeon_vce_init(rdev);
2084 if (r) {
2085 dev_err(rdev->dev, "failed VCE (%d) init.\n", r);
2086 /*
2087 * At this point rdev->vce.vcpu_bo is NULL which trickles down
2088 * to early fails cayman_vce_start() and thus nothing happens
2089 * there. So it is pointless to try to go through that code
2090 * hence why we disable vce here.
2091 */
2092 rdev->has_vce = 0;
2093 return;
2094 }
2095 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_obj = NULL;
2096 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE1_INDEX], 4096);
2097 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_obj = NULL;
2098 r600_ring_init(rdev, &rdev->ring[TN_RING_TYPE_VCE2_INDEX], 4096);
2099}
2100
2101static void cayman_vce_start(struct radeon_device *rdev)
2102{
2103 int r;
2104
2105 if (!rdev->has_vce)
2106 return;
2107
2108 r = radeon_vce_resume(rdev);
2109 if (r) {
2110 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2111 goto error;
2112 }
2113 r = vce_v1_0_resume(rdev);
2114 if (r) {
2115 dev_err(rdev->dev, "failed VCE resume (%d).\n", r);
2116 goto error;
2117 }
2118 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE1_INDEX);
2119 if (r) {
2120 dev_err(rdev->dev, "failed initializing VCE1 fences (%d).\n", r);
2121 goto error;
2122 }
2123 r = radeon_fence_driver_start_ring(rdev, TN_RING_TYPE_VCE2_INDEX);
2124 if (r) {
2125 dev_err(rdev->dev, "failed initializing VCE2 fences (%d).\n", r);
2126 goto error;
2127 }
2128 return;
2129
2130error:
2131 rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size = 0;
2132 rdev->ring[TN_RING_TYPE_VCE2_INDEX].ring_size = 0;
2133}
2134
2135static void cayman_vce_resume(struct radeon_device *rdev)
2136{
2137 struct radeon_ring *ring;
2138 int r;
2139
2140 if (!rdev->has_vce || !rdev->ring[TN_RING_TYPE_VCE1_INDEX].ring_size)
2141 return;
2142
2143 ring = &rdev->ring[TN_RING_TYPE_VCE1_INDEX];
2144 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2145 if (r) {
2146 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2147 return;
2148 }
2149 ring = &rdev->ring[TN_RING_TYPE_VCE2_INDEX];
2150 r = radeon_ring_init(rdev, ring, ring->ring_size, 0, 0x0);
2151 if (r) {
2152 dev_err(rdev->dev, "failed initializing VCE1 ring (%d).\n", r);
2153 return;
2154 }
2155 r = vce_v1_0_init(rdev);
2156 if (r) {
2157 dev_err(rdev->dev, "failed initializing VCE (%d).\n", r);
2158 return;
2159 }
2160}
2161
2162static int cayman_startup(struct radeon_device *rdev)
2163{
2164 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2165 int r;
2166
2167 /* enable pcie gen2 link */
2168 evergreen_pcie_gen2_enable(rdev);
2169 /* enable aspm */
2170 evergreen_program_aspm(rdev);
2171
2172 /* scratch needs to be initialized before MC */
2173 r = r600_vram_scratch_init(rdev);
2174 if (r)
2175 return r;
2176
2177 evergreen_mc_program(rdev);
2178
2179 if (!(rdev->flags & RADEON_IS_IGP) && !rdev->pm.dpm_enabled) {
2180 r = ni_mc_load_microcode(rdev);
2181 if (r) {
2182 DRM_ERROR("Failed to load MC firmware!\n");
2183 return r;
2184 }
2185 }
2186
2187 r = cayman_pcie_gart_enable(rdev);
2188 if (r)
2189 return r;
2190 cayman_gpu_init(rdev);
2191
2192 /* allocate rlc buffers */
2193 if (rdev->flags & RADEON_IS_IGP) {
2194 rdev->rlc.reg_list = tn_rlc_save_restore_register_list;
2195 rdev->rlc.reg_list_size =
2196 (u32)ARRAY_SIZE(tn_rlc_save_restore_register_list);
2197 rdev->rlc.cs_data = cayman_cs_data;
2198 r = sumo_rlc_init(rdev);
2199 if (r) {
2200 DRM_ERROR("Failed to init rlc BOs!\n");
2201 return r;
2202 }
2203 }
2204
2205 /* allocate wb buffer */
2206 r = radeon_wb_init(rdev);
2207 if (r)
2208 return r;
2209
2210 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
2211 if (r) {
2212 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2213 return r;
2214 }
2215
2216 cayman_uvd_start(rdev);
2217 cayman_vce_start(rdev);
2218
2219 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
2220 if (r) {
2221 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2222 return r;
2223 }
2224
2225 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
2226 if (r) {
2227 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
2228 return r;
2229 }
2230
2231 r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
2232 if (r) {
2233 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2234 return r;
2235 }
2236
2237 r = radeon_fence_driver_start_ring(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
2238 if (r) {
2239 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
2240 return r;
2241 }
2242
2243 /* Enable IRQ */
2244 if (!rdev->irq.installed) {
2245 r = radeon_irq_kms_init(rdev);
2246 if (r)
2247 return r;
2248 }
2249
2250 r = r600_irq_init(rdev);
2251 if (r) {
2252 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2253 radeon_irq_kms_fini(rdev);
2254 return r;
2255 }
2256 evergreen_irq_set(rdev);
2257
2258 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
2259 RADEON_CP_PACKET2);
2260 if (r)
2261 return r;
2262
2263 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2264 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
2265 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2266 if (r)
2267 return r;
2268
2269 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2270 r = radeon_ring_init(rdev, ring, ring->ring_size, CAYMAN_WB_DMA1_RPTR_OFFSET,
2271 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
2272 if (r)
2273 return r;
2274
2275 r = cayman_cp_load_microcode(rdev);
2276 if (r)
2277 return r;
2278 r = cayman_cp_resume(rdev);
2279 if (r)
2280 return r;
2281
2282 r = cayman_dma_resume(rdev);
2283 if (r)
2284 return r;
2285
2286 cayman_uvd_resume(rdev);
2287 cayman_vce_resume(rdev);
2288
2289 r = radeon_ib_pool_init(rdev);
2290 if (r) {
2291 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2292 return r;
2293 }
2294
2295 r = radeon_vm_manager_init(rdev);
2296 if (r) {
2297 dev_err(rdev->dev, "vm manager initialization failed (%d).\n", r);
2298 return r;
2299 }
2300
2301 r = radeon_audio_init(rdev);
2302 if (r)
2303 return r;
2304
2305 return 0;
2306}
2307
2308int cayman_resume(struct radeon_device *rdev)
2309{
2310 int r;
2311
2312 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2313 * posting will perform necessary task to bring back GPU into good
2314 * shape.
2315 */
2316 /* post card */
2317 atom_asic_init(rdev->mode_info.atom_context);
2318
2319 /* init golden registers */
2320 ni_init_golden_registers(rdev);
2321
2322 if (rdev->pm.pm_method == PM_METHOD_DPM)
2323 radeon_pm_resume(rdev);
2324
2325 rdev->accel_working = true;
2326 r = cayman_startup(rdev);
2327 if (r) {
2328 DRM_ERROR("cayman startup failed on resume\n");
2329 rdev->accel_working = false;
2330 return r;
2331 }
2332 return r;
2333}
2334
2335int cayman_suspend(struct radeon_device *rdev)
2336{
2337 radeon_pm_suspend(rdev);
2338 radeon_audio_fini(rdev);
2339 radeon_vm_manager_fini(rdev);
2340 cayman_cp_enable(rdev, false);
2341 cayman_dma_stop(rdev);
2342 if (rdev->has_uvd) {
2343 uvd_v1_0_fini(rdev);
2344 radeon_uvd_suspend(rdev);
2345 }
2346 evergreen_irq_suspend(rdev);
2347 radeon_wb_disable(rdev);
2348 cayman_pcie_gart_disable(rdev);
2349 return 0;
2350}
2351
2352/* Plan is to move initialization in that function and use
2353 * helper function so that radeon_device_init pretty much
2354 * do nothing more than calling asic specific function. This
2355 * should also allow to remove a bunch of callback function
2356 * like vram_info.
2357 */
2358int cayman_init(struct radeon_device *rdev)
2359{
2360 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
2361 int r;
2362
2363 /* Read BIOS */
2364 if (!radeon_get_bios(rdev)) {
2365 if (ASIC_IS_AVIVO(rdev))
2366 return -EINVAL;
2367 }
2368 /* Must be an ATOMBIOS */
2369 if (!rdev->is_atom_bios) {
2370 dev_err(rdev->dev, "Expecting atombios for cayman GPU\n");
2371 return -EINVAL;
2372 }
2373 r = radeon_atombios_init(rdev);
2374 if (r)
2375 return r;
2376
2377 /* Post card if necessary */
2378 if (!radeon_card_posted(rdev)) {
2379 if (!rdev->bios) {
2380 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2381 return -EINVAL;
2382 }
2383 DRM_INFO("GPU not posted. posting now...\n");
2384 atom_asic_init(rdev->mode_info.atom_context);
2385 }
2386 /* init golden registers */
2387 ni_init_golden_registers(rdev);
2388 /* Initialize scratch registers */
2389 r600_scratch_init(rdev);
2390 /* Initialize surface registers */
2391 radeon_surface_init(rdev);
2392 /* Initialize clocks */
2393 radeon_get_clock_info(rdev->ddev);
2394 /* Fence driver */
2395 r = radeon_fence_driver_init(rdev);
2396 if (r)
2397 return r;
2398 /* initialize memory controller */
2399 r = evergreen_mc_init(rdev);
2400 if (r)
2401 return r;
2402 /* Memory manager */
2403 r = radeon_bo_init(rdev);
2404 if (r)
2405 return r;
2406
2407 if (rdev->flags & RADEON_IS_IGP) {
2408 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2409 r = ni_init_microcode(rdev);
2410 if (r) {
2411 DRM_ERROR("Failed to load firmware!\n");
2412 return r;
2413 }
2414 }
2415 } else {
2416 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2417 r = ni_init_microcode(rdev);
2418 if (r) {
2419 DRM_ERROR("Failed to load firmware!\n");
2420 return r;
2421 }
2422 }
2423 }
2424
2425 /* Initialize power management */
2426 radeon_pm_init(rdev);
2427
2428 ring->ring_obj = NULL;
2429 r600_ring_init(rdev, ring, 1024 * 1024);
2430
2431 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2432 ring->ring_obj = NULL;
2433 r600_ring_init(rdev, ring, 64 * 1024);
2434
2435 ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2436 ring->ring_obj = NULL;
2437 r600_ring_init(rdev, ring, 64 * 1024);
2438
2439 cayman_uvd_init(rdev);
2440 cayman_vce_init(rdev);
2441
2442 rdev->ih.ring_obj = NULL;
2443 r600_ih_ring_init(rdev, 64 * 1024);
2444
2445 r = r600_pcie_gart_init(rdev);
2446 if (r)
2447 return r;
2448
2449 rdev->accel_working = true;
2450 r = cayman_startup(rdev);
2451 if (r) {
2452 dev_err(rdev->dev, "disabling GPU acceleration\n");
2453 cayman_cp_fini(rdev);
2454 cayman_dma_fini(rdev);
2455 r600_irq_fini(rdev);
2456 if (rdev->flags & RADEON_IS_IGP)
2457 sumo_rlc_fini(rdev);
2458 radeon_wb_fini(rdev);
2459 radeon_ib_pool_fini(rdev);
2460 radeon_vm_manager_fini(rdev);
2461 radeon_irq_kms_fini(rdev);
2462 cayman_pcie_gart_fini(rdev);
2463 rdev->accel_working = false;
2464 }
2465
2466 /* Don't start up if the MC ucode is missing.
2467 * The default clocks and voltages before the MC ucode
2468 * is loaded are not suffient for advanced operations.
2469 *
2470 * We can skip this check for TN, because there is no MC
2471 * ucode.
2472 */
2473 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
2474 DRM_ERROR("radeon: MC ucode required for NI+.\n");
2475 return -EINVAL;
2476 }
2477
2478 return 0;
2479}
2480
2481void cayman_fini(struct radeon_device *rdev)
2482{
2483 radeon_pm_fini(rdev);
2484 cayman_cp_fini(rdev);
2485 cayman_dma_fini(rdev);
2486 r600_irq_fini(rdev);
2487 if (rdev->flags & RADEON_IS_IGP)
2488 sumo_rlc_fini(rdev);
2489 radeon_wb_fini(rdev);
2490 radeon_vm_manager_fini(rdev);
2491 radeon_ib_pool_fini(rdev);
2492 radeon_irq_kms_fini(rdev);
2493 uvd_v1_0_fini(rdev);
2494 radeon_uvd_fini(rdev);
2495 if (rdev->has_vce)
2496 radeon_vce_fini(rdev);
2497 cayman_pcie_gart_fini(rdev);
2498 r600_vram_scratch_fini(rdev);
2499 radeon_gem_fini(rdev);
2500 radeon_fence_driver_fini(rdev);
2501 radeon_bo_fini(rdev);
2502 radeon_atombios_fini(rdev);
2503 kfree(rdev->bios);
2504 rdev->bios = NULL;
2505}
2506
2507/*
2508 * vm
2509 */
2510int cayman_vm_init(struct radeon_device *rdev)
2511{
2512 /* number of VMs */
2513 rdev->vm_manager.nvm = 8;
2514 /* base offset of vram pages */
2515 if (rdev->flags & RADEON_IS_IGP) {
2516 u64 tmp = RREG32(FUS_MC_VM_FB_OFFSET);
2517 tmp <<= 22;
2518 rdev->vm_manager.vram_base_offset = tmp;
2519 } else
2520 rdev->vm_manager.vram_base_offset = 0;
2521 return 0;
2522}
2523
2524void cayman_vm_fini(struct radeon_device *rdev)
2525{
2526}
2527
2528/**
2529 * cayman_vm_decode_fault - print human readable fault info
2530 *
2531 * @rdev: radeon_device pointer
2532 * @status: VM_CONTEXT1_PROTECTION_FAULT_STATUS register value
2533 * @addr: VM_CONTEXT1_PROTECTION_FAULT_ADDR register value
2534 *
2535 * Print human readable fault information (cayman/TN).
2536 */
2537void cayman_vm_decode_fault(struct radeon_device *rdev,
2538 u32 status, u32 addr)
2539{
2540 u32 mc_id = (status & MEMORY_CLIENT_ID_MASK) >> MEMORY_CLIENT_ID_SHIFT;
2541 u32 vmid = (status & FAULT_VMID_MASK) >> FAULT_VMID_SHIFT;
2542 u32 protections = (status & PROTECTIONS_MASK) >> PROTECTIONS_SHIFT;
2543 char *block;
2544
2545 switch (mc_id) {
2546 case 32:
2547 case 16:
2548 case 96:
2549 case 80:
2550 case 160:
2551 case 144:
2552 case 224:
2553 case 208:
2554 block = "CB";
2555 break;
2556 case 33:
2557 case 17:
2558 case 97:
2559 case 81:
2560 case 161:
2561 case 145:
2562 case 225:
2563 case 209:
2564 block = "CB_FMASK";
2565 break;
2566 case 34:
2567 case 18:
2568 case 98:
2569 case 82:
2570 case 162:
2571 case 146:
2572 case 226:
2573 case 210:
2574 block = "CB_CMASK";
2575 break;
2576 case 35:
2577 case 19:
2578 case 99:
2579 case 83:
2580 case 163:
2581 case 147:
2582 case 227:
2583 case 211:
2584 block = "CB_IMMED";
2585 break;
2586 case 36:
2587 case 20:
2588 case 100:
2589 case 84:
2590 case 164:
2591 case 148:
2592 case 228:
2593 case 212:
2594 block = "DB";
2595 break;
2596 case 37:
2597 case 21:
2598 case 101:
2599 case 85:
2600 case 165:
2601 case 149:
2602 case 229:
2603 case 213:
2604 block = "DB_HTILE";
2605 break;
2606 case 38:
2607 case 22:
2608 case 102:
2609 case 86:
2610 case 166:
2611 case 150:
2612 case 230:
2613 case 214:
2614 block = "SX";
2615 break;
2616 case 39:
2617 case 23:
2618 case 103:
2619 case 87:
2620 case 167:
2621 case 151:
2622 case 231:
2623 case 215:
2624 block = "DB_STEN";
2625 break;
2626 case 40:
2627 case 24:
2628 case 104:
2629 case 88:
2630 case 232:
2631 case 216:
2632 case 168:
2633 case 152:
2634 block = "TC_TFETCH";
2635 break;
2636 case 41:
2637 case 25:
2638 case 105:
2639 case 89:
2640 case 233:
2641 case 217:
2642 case 169:
2643 case 153:
2644 block = "TC_VFETCH";
2645 break;
2646 case 42:
2647 case 26:
2648 case 106:
2649 case 90:
2650 case 234:
2651 case 218:
2652 case 170:
2653 case 154:
2654 block = "VC";
2655 break;
2656 case 112:
2657 block = "CP";
2658 break;
2659 case 113:
2660 case 114:
2661 block = "SH";
2662 break;
2663 case 115:
2664 block = "VGT";
2665 break;
2666 case 178:
2667 block = "IH";
2668 break;
2669 case 51:
2670 block = "RLC";
2671 break;
2672 case 55:
2673 block = "DMA";
2674 break;
2675 case 56:
2676 block = "HDP";
2677 break;
2678 default:
2679 block = "unknown";
2680 break;
2681 }
2682
2683 printk("VM fault (0x%02x, vmid %d) at page %u, %s from %s (%d)\n",
2684 protections, vmid, addr,
2685 (status & MEMORY_CLIENT_RW_MASK) ? "write" : "read",
2686 block, mc_id);
2687}
2688
2689/**
2690 * cayman_vm_flush - vm flush using the CP
2691 *
2692 * @rdev: radeon_device pointer
2693 *
2694 * Update the page table base and flush the VM TLB
2695 * using the CP (cayman-si).
2696 */
2697void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
2698 unsigned vm_id, uint64_t pd_addr)
2699{
2700 radeon_ring_write(ring, PACKET0(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2), 0));
2701 radeon_ring_write(ring, pd_addr >> 12);
2702
2703 /* flush hdp cache */
2704 radeon_ring_write(ring, PACKET0(HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
2705 radeon_ring_write(ring, 0x1);
2706
2707 /* bits 0-7 are the VM contexts0-7 */
2708 radeon_ring_write(ring, PACKET0(VM_INVALIDATE_REQUEST, 0));
2709 radeon_ring_write(ring, 1 << vm_id);
2710
2711 /* wait for the invalidate to complete */
2712 radeon_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2713 radeon_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2714 WAIT_REG_MEM_ENGINE(0))); /* me */
2715 radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
2716 radeon_ring_write(ring, 0);
2717 radeon_ring_write(ring, 0); /* ref */
2718 radeon_ring_write(ring, 0); /* mask */
2719 radeon_ring_write(ring, 0x20); /* poll interval */
2720
2721 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2722 radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2723 radeon_ring_write(ring, 0x0);
2724}
2725
2726int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk)
2727{
2728 struct atom_clock_dividers dividers;
2729 int r, i;
2730
2731 r = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
2732 ecclk, false, ÷rs);
2733 if (r)
2734 return r;
2735
2736 for (i = 0; i < 100; i++) {
2737 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2738 break;
2739 mdelay(10);
2740 }
2741 if (i == 100)
2742 return -ETIMEDOUT;
2743
2744 WREG32_P(CG_ECLK_CNTL, dividers.post_div, ~(ECLK_DIR_CNTL_EN|ECLK_DIVIDER_MASK));
2745
2746 for (i = 0; i < 100; i++) {
2747 if (RREG32(CG_ECLK_STATUS) & ECLK_STATUS)
2748 break;
2749 mdelay(10);
2750 }
2751 if (i == 100)
2752 return -ETIMEDOUT;
2753
2754 return 0;
2755}