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1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2009 Nokia Corporation
4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
5 *
6 * Some code and ideas taken from drivers/video/omap/ driver
7 * by Imre Deak.
8 */
9
10#ifndef __OMAP2_DSS_H
11#define __OMAP2_DSS_H
12
13#include <linux/interrupt.h>
14
15#include "omapdss.h"
16
17struct dispc_device;
18struct dss_debugfs_entry;
19struct platform_device;
20struct seq_file;
21
22#define MAX_DSS_LCD_MANAGERS 3
23#define MAX_NUM_DSI 2
24
25#ifdef pr_fmt
26#undef pr_fmt
27#endif
28
29#ifdef DSS_SUBSYS_NAME
30#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
31#else
32#define pr_fmt(fmt) fmt
33#endif
34
35#define DSSDBG(format, ...) \
36 pr_debug(format, ## __VA_ARGS__)
37
38#ifdef DSS_SUBSYS_NAME
39#define DSSERR(format, ...) \
40 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
41#else
42#define DSSERR(format, ...) \
43 pr_err("omapdss error: " format, ##__VA_ARGS__)
44#endif
45
46#ifdef DSS_SUBSYS_NAME
47#define DSSINFO(format, ...) \
48 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
49#else
50#define DSSINFO(format, ...) \
51 pr_info("omapdss: " format, ## __VA_ARGS__)
52#endif
53
54#ifdef DSS_SUBSYS_NAME
55#define DSSWARN(format, ...) \
56 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
57#else
58#define DSSWARN(format, ...) \
59 pr_warn("omapdss: " format, ##__VA_ARGS__)
60#endif
61
62/* OMAP TRM gives bitfields as start:end, where start is the higher bit
63 number. For example 7:0 */
64#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
65#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
66#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
67#define FLD_MOD(orig, val, start, end) \
68 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
69
70enum dss_model {
71 DSS_MODEL_OMAP2,
72 DSS_MODEL_OMAP3,
73 DSS_MODEL_OMAP4,
74 DSS_MODEL_OMAP5,
75 DSS_MODEL_DRA7,
76};
77
78enum dss_io_pad_mode {
79 DSS_IO_PAD_MODE_RESET,
80 DSS_IO_PAD_MODE_RFBI,
81 DSS_IO_PAD_MODE_BYPASS,
82};
83
84enum dss_hdmi_venc_clk_source_select {
85 DSS_VENC_TV_CLK = 0,
86 DSS_HDMI_M_PCLK = 1,
87};
88
89enum dss_dsi_content_type {
90 DSS_DSI_CONTENT_DCS,
91 DSS_DSI_CONTENT_GENERIC,
92};
93
94enum dss_clk_source {
95 DSS_CLK_SRC_FCK = 0,
96
97 DSS_CLK_SRC_PLL1_1,
98 DSS_CLK_SRC_PLL1_2,
99 DSS_CLK_SRC_PLL1_3,
100
101 DSS_CLK_SRC_PLL2_1,
102 DSS_CLK_SRC_PLL2_2,
103 DSS_CLK_SRC_PLL2_3,
104
105 DSS_CLK_SRC_HDMI_PLL,
106};
107
108enum dss_pll_id {
109 DSS_PLL_DSI1,
110 DSS_PLL_DSI2,
111 DSS_PLL_HDMI,
112 DSS_PLL_VIDEO1,
113 DSS_PLL_VIDEO2,
114};
115
116struct dss_pll;
117
118#define DSS_PLL_MAX_HSDIVS 4
119
120enum dss_pll_type {
121 DSS_PLL_TYPE_A,
122 DSS_PLL_TYPE_B,
123};
124
125/*
126 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
127 * Type-B PLLs: clkout[0] refers to m2.
128 */
129struct dss_pll_clock_info {
130 /* rates that we get with dividers below */
131 unsigned long fint;
132 unsigned long clkdco;
133 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
134
135 /* dividers */
136 u16 n;
137 u16 m;
138 u32 mf;
139 u16 mX[DSS_PLL_MAX_HSDIVS];
140 u16 sd;
141};
142
143struct dss_pll_ops {
144 int (*enable)(struct dss_pll *pll);
145 void (*disable)(struct dss_pll *pll);
146 int (*set_config)(struct dss_pll *pll,
147 const struct dss_pll_clock_info *cinfo);
148};
149
150struct dss_pll_hw {
151 enum dss_pll_type type;
152
153 unsigned int n_max;
154 unsigned int m_min;
155 unsigned int m_max;
156 unsigned int mX_max;
157
158 unsigned long fint_min, fint_max;
159 unsigned long clkdco_min, clkdco_low, clkdco_max;
160
161 u8 n_msb, n_lsb;
162 u8 m_msb, m_lsb;
163 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
164
165 bool has_stopmode;
166 bool has_freqsel;
167 bool has_selfreqdco;
168 bool has_refsel;
169
170 /* DRA7 errata i886: use high N & M to avoid jitter */
171 bool errata_i886;
172
173 /* DRA7 errata i932: retry pll lock on failure */
174 bool errata_i932;
175};
176
177struct dss_pll {
178 const char *name;
179 enum dss_pll_id id;
180 struct dss_device *dss;
181
182 struct clk *clkin;
183 struct regulator *regulator;
184
185 void __iomem *base;
186
187 const struct dss_pll_hw *hw;
188
189 const struct dss_pll_ops *ops;
190
191 struct dss_pll_clock_info cinfo;
192};
193
194/* Defines a generic omap register field */
195struct dss_reg_field {
196 u8 start, end;
197};
198
199struct dispc_clock_info {
200 /* rates that we get with dividers below */
201 unsigned long lck;
202 unsigned long pck;
203
204 /* dividers */
205 u16 lck_div;
206 u16 pck_div;
207};
208
209struct dss_lcd_mgr_config {
210 enum dss_io_pad_mode io_pad_mode;
211
212 bool stallmode;
213 bool fifohandcheck;
214
215 struct dispc_clock_info clock_info;
216
217 int video_port_width;
218
219 int lcden_sig_polarity;
220};
221
222#define DSS_SZ_REGS SZ_512
223
224struct dss_device {
225 struct platform_device *pdev;
226 void __iomem *base;
227 struct regmap *syscon_pll_ctrl;
228 u32 syscon_pll_ctrl_offset;
229
230 struct platform_device *drm_pdev;
231
232 struct clk *parent_clk;
233 struct clk *dss_clk;
234 unsigned long dss_clk_rate;
235
236 unsigned long cache_req_pck;
237 unsigned long cache_prate;
238 struct dispc_clock_info cache_dispc_cinfo;
239
240 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
241 enum dss_clk_source dispc_clk_source;
242 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
243
244 bool ctx_valid;
245 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
246
247 const struct dss_features *feat;
248
249 struct {
250 struct dentry *root;
251 struct dss_debugfs_entry *clk;
252 struct dss_debugfs_entry *dss;
253 } debugfs;
254
255 struct dss_pll *plls[4];
256 struct dss_pll *video1_pll;
257 struct dss_pll *video2_pll;
258
259 struct dispc_device *dispc;
260 struct omap_drm_private *mgr_ops_priv;
261};
262
263/* core */
264static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
265{
266 /* To be implemented when the OMAP platform will provide this feature */
267 return 0;
268}
269
270static inline bool dss_mgr_is_lcd(enum omap_channel id)
271{
272 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
273 id == OMAP_DSS_CHANNEL_LCD3)
274 return true;
275 else
276 return false;
277}
278
279/* DSS */
280#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
281struct dss_debugfs_entry *
282dss_debugfs_create_file(struct dss_device *dss, const char *name,
283 int (*show_fn)(struct seq_file *s, void *data),
284 void *data);
285void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
286#else
287static inline struct dss_debugfs_entry *
288dss_debugfs_create_file(struct dss_device *dss, const char *name,
289 int (*show_fn)(struct seq_file *s, void *data),
290 void *data)
291{
292 return NULL;
293}
294
295static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
296{
297}
298#endif /* CONFIG_OMAP2_DSS_DEBUGFS */
299
300struct dss_device *dss_get_device(struct device *dev);
301
302int dss_runtime_get(struct dss_device *dss);
303void dss_runtime_put(struct dss_device *dss);
304
305unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
306unsigned long dss_get_max_fck_rate(struct dss_device *dss);
307int dss_dpi_select_source(struct dss_device *dss, int port,
308 enum omap_channel channel);
309void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
310 enum dss_hdmi_venc_clk_source_select src);
311const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
312
313/* DSS VIDEO PLL */
314struct dss_pll *dss_video_pll_init(struct dss_device *dss,
315 struct platform_device *pdev, int id,
316 struct regulator *regulator);
317void dss_video_pll_uninit(struct dss_pll *pll);
318
319void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
320
321void dss_sdi_init(struct dss_device *dss, int datapairs);
322int dss_sdi_enable(struct dss_device *dss);
323void dss_sdi_disable(struct dss_device *dss);
324
325void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
326 enum dss_clk_source clk_src);
327void dss_select_lcd_clk_source(struct dss_device *dss,
328 enum omap_channel channel,
329 enum dss_clk_source clk_src);
330enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
331enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
332 int dsi_module);
333enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
334 enum omap_channel channel);
335
336void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
337void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
338
339int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
340
341typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
342bool dss_div_calc(struct dss_device *dss, unsigned long pck,
343 unsigned long fck_min, dss_div_calc_func func, void *data);
344
345/* SDI */
346#ifdef CONFIG_OMAP2_DSS_SDI
347int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
348 struct device_node *port);
349void sdi_uninit_port(struct device_node *port);
350#else
351static inline int sdi_init_port(struct dss_device *dss,
352 struct platform_device *pdev,
353 struct device_node *port)
354{
355 return 0;
356}
357static inline void sdi_uninit_port(struct device_node *port)
358{
359}
360#endif
361
362/* DSI */
363
364#ifdef CONFIG_OMAP2_DSS_DSI
365
366void dsi_irq_handler(void);
367
368#endif
369
370/* DPI */
371#ifdef CONFIG_OMAP2_DSS_DPI
372int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
373 struct device_node *port, enum dss_model dss_model);
374void dpi_uninit_port(struct device_node *port);
375#else
376static inline int dpi_init_port(struct dss_device *dss,
377 struct platform_device *pdev,
378 struct device_node *port,
379 enum dss_model dss_model)
380{
381 return 0;
382}
383static inline void dpi_uninit_port(struct device_node *port)
384{
385}
386#endif
387
388/* DISPC */
389void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
390
391int dispc_runtime_get(struct dispc_device *dispc);
392void dispc_runtime_put(struct dispc_device *dispc);
393
394int dispc_get_num_ovls(struct dispc_device *dispc);
395int dispc_get_num_mgrs(struct dispc_device *dispc);
396
397const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc,
398 enum omap_plane_id plane);
399
400void dispc_ovl_get_max_size(struct dispc_device *dispc, u16 *width, u16 *height);
401bool dispc_ovl_color_mode_supported(struct dispc_device *dispc,
402 enum omap_plane_id plane, u32 fourcc);
403enum omap_overlay_caps dispc_ovl_get_caps(struct dispc_device *dispc, enum omap_plane_id plane);
404
405u32 dispc_read_irqstatus(struct dispc_device *dispc);
406void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
407void dispc_write_irqenable(struct dispc_device *dispc, u32 mask);
408
409int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler,
410 void *dev_id);
411void dispc_free_irq(struct dispc_device *dispc, void *dev_id);
412
413u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc,
414 enum omap_channel channel);
415u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc,
416 enum omap_channel channel);
417u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc,
418 enum omap_channel channel);
419
420u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc);
421
422void dispc_mgr_enable(struct dispc_device *dispc,
423 enum omap_channel channel, bool enable);
424
425bool dispc_mgr_go_busy(struct dispc_device *dispc,
426 enum omap_channel channel);
427
428void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel);
429
430void dispc_mgr_set_lcd_config(struct dispc_device *dispc,
431 enum omap_channel channel,
432 const struct dss_lcd_mgr_config *config);
433void dispc_mgr_set_timings(struct dispc_device *dispc,
434 enum omap_channel channel,
435 const struct videomode *vm);
436void dispc_mgr_setup(struct dispc_device *dispc,
437 enum omap_channel channel,
438 const struct omap_overlay_manager_info *info);
439
440int dispc_mgr_check_timings(struct dispc_device *dispc,
441 enum omap_channel channel,
442 const struct videomode *vm);
443
444u32 dispc_mgr_gamma_size(struct dispc_device *dispc,
445 enum omap_channel channel);
446void dispc_mgr_set_gamma(struct dispc_device *dispc,
447 enum omap_channel channel,
448 const struct drm_color_lut *lut,
449 unsigned int length);
450
451int dispc_ovl_setup(struct dispc_device *dispc,
452 enum omap_plane_id plane,
453 const struct omap_overlay_info *oi,
454 const struct videomode *vm, bool mem_to_mem,
455 enum omap_channel channel);
456
457int dispc_ovl_enable(struct dispc_device *dispc,
458 enum omap_plane_id plane, bool enable);
459
460void dispc_enable_sidle(struct dispc_device *dispc);
461void dispc_disable_sidle(struct dispc_device *dispc);
462
463void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
464void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
465
466typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
467 unsigned long pck, void *data);
468bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
469 unsigned long pck_min, unsigned long pck_max,
470 dispc_div_calc_func func, void *data);
471
472int dispc_calc_clock_rates(struct dispc_device *dispc,
473 unsigned long dispc_fclk_rate,
474 struct dispc_clock_info *cinfo);
475
476
477void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
478 enum omap_plane_id plane, u32 low, u32 high);
479void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
480 enum omap_plane_id plane,
481 u32 *fifo_low, u32 *fifo_high,
482 bool use_fifomerge, bool manual_update);
483
484void dispc_mgr_set_clock_div(struct dispc_device *dispc,
485 enum omap_channel channel,
486 const struct dispc_clock_info *cinfo);
487void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
488
489#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
490static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
491{
492 int b;
493 for (b = 0; b < 32; ++b) {
494 if (irqstatus & (1 << b))
495 irq_arr[b]++;
496 }
497}
498#endif
499
500/* PLL */
501typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
502 unsigned long clkdco, void *data);
503typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
504 void *data);
505
506int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
507void dss_pll_unregister(struct dss_pll *pll);
508struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
509struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
510 enum dss_clk_source src);
511unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
512int dss_pll_enable(struct dss_pll *pll);
513void dss_pll_disable(struct dss_pll *pll);
514int dss_pll_set_config(struct dss_pll *pll,
515 const struct dss_pll_clock_info *cinfo);
516
517bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
518 unsigned long out_min, unsigned long out_max,
519 dss_hsdiv_calc_func func, void *data);
520bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
521 unsigned long pll_min, unsigned long pll_max,
522 dss_pll_calc_func func, void *data);
523
524bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
525 unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
526
527int dss_pll_write_config_type_a(struct dss_pll *pll,
528 const struct dss_pll_clock_info *cinfo);
529int dss_pll_write_config_type_b(struct dss_pll *pll,
530 const struct dss_pll_clock_info *cinfo);
531int dss_pll_wait_reset_done(struct dss_pll *pll);
532
533extern struct platform_driver omap_dsshw_driver;
534extern struct platform_driver omap_dispchw_driver;
535#ifdef CONFIG_OMAP2_DSS_DSI
536extern struct platform_driver omap_dsihw_driver;
537#endif
538#ifdef CONFIG_OMAP2_DSS_VENC
539extern struct platform_driver omap_venchw_driver;
540#endif
541#ifdef CONFIG_OMAP4_DSS_HDMI
542extern struct platform_driver omapdss_hdmi4hw_driver;
543#endif
544#ifdef CONFIG_OMAP5_DSS_HDMI
545extern struct platform_driver omapdss_hdmi5hw_driver;
546#endif
547
548#endif
1/*
2 * linux/drivers/video/omap2/dss/dss.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#ifndef __OMAP2_DSS_H
24#define __OMAP2_DSS_H
25
26#include <linux/interrupt.h>
27
28#include "omapdss.h"
29
30#ifdef pr_fmt
31#undef pr_fmt
32#endif
33
34#ifdef DSS_SUBSYS_NAME
35#define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
36#else
37#define pr_fmt(fmt) fmt
38#endif
39
40#define DSSDBG(format, ...) \
41 pr_debug(format, ## __VA_ARGS__)
42
43#ifdef DSS_SUBSYS_NAME
44#define DSSERR(format, ...) \
45 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
46 ## __VA_ARGS__)
47#else
48#define DSSERR(format, ...) \
49 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
50#endif
51
52#ifdef DSS_SUBSYS_NAME
53#define DSSINFO(format, ...) \
54 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
55 ## __VA_ARGS__)
56#else
57#define DSSINFO(format, ...) \
58 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
59#endif
60
61#ifdef DSS_SUBSYS_NAME
62#define DSSWARN(format, ...) \
63 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
64 ## __VA_ARGS__)
65#else
66#define DSSWARN(format, ...) \
67 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
68#endif
69
70/* OMAP TRM gives bitfields as start:end, where start is the higher bit
71 number. For example 7:0 */
72#define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
73#define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
74#define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
75#define FLD_MOD(orig, val, start, end) \
76 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
77
78enum dss_io_pad_mode {
79 DSS_IO_PAD_MODE_RESET,
80 DSS_IO_PAD_MODE_RFBI,
81 DSS_IO_PAD_MODE_BYPASS,
82};
83
84enum dss_hdmi_venc_clk_source_select {
85 DSS_VENC_TV_CLK = 0,
86 DSS_HDMI_M_PCLK = 1,
87};
88
89enum dss_dsi_content_type {
90 DSS_DSI_CONTENT_DCS,
91 DSS_DSI_CONTENT_GENERIC,
92};
93
94enum dss_writeback_channel {
95 DSS_WB_LCD1_MGR = 0,
96 DSS_WB_LCD2_MGR = 1,
97 DSS_WB_TV_MGR = 2,
98 DSS_WB_OVL0 = 3,
99 DSS_WB_OVL1 = 4,
100 DSS_WB_OVL2 = 5,
101 DSS_WB_OVL3 = 6,
102 DSS_WB_LCD3_MGR = 7,
103};
104
105enum dss_clk_source {
106 DSS_CLK_SRC_FCK = 0,
107
108 DSS_CLK_SRC_PLL1_1,
109 DSS_CLK_SRC_PLL1_2,
110 DSS_CLK_SRC_PLL1_3,
111
112 DSS_CLK_SRC_PLL2_1,
113 DSS_CLK_SRC_PLL2_2,
114 DSS_CLK_SRC_PLL2_3,
115
116 DSS_CLK_SRC_HDMI_PLL,
117};
118
119enum dss_pll_id {
120 DSS_PLL_DSI1,
121 DSS_PLL_DSI2,
122 DSS_PLL_HDMI,
123 DSS_PLL_VIDEO1,
124 DSS_PLL_VIDEO2,
125};
126
127struct dss_pll;
128
129#define DSS_PLL_MAX_HSDIVS 4
130
131enum dss_pll_type {
132 DSS_PLL_TYPE_A,
133 DSS_PLL_TYPE_B,
134};
135
136/*
137 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
138 * Type-B PLLs: clkout[0] refers to m2.
139 */
140struct dss_pll_clock_info {
141 /* rates that we get with dividers below */
142 unsigned long fint;
143 unsigned long clkdco;
144 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
145
146 /* dividers */
147 u16 n;
148 u16 m;
149 u32 mf;
150 u16 mX[DSS_PLL_MAX_HSDIVS];
151 u16 sd;
152};
153
154struct dss_pll_ops {
155 int (*enable)(struct dss_pll *pll);
156 void (*disable)(struct dss_pll *pll);
157 int (*set_config)(struct dss_pll *pll,
158 const struct dss_pll_clock_info *cinfo);
159};
160
161struct dss_pll_hw {
162 enum dss_pll_type type;
163
164 unsigned n_max;
165 unsigned m_min;
166 unsigned m_max;
167 unsigned mX_max;
168
169 unsigned long fint_min, fint_max;
170 unsigned long clkdco_min, clkdco_low, clkdco_max;
171
172 u8 n_msb, n_lsb;
173 u8 m_msb, m_lsb;
174 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
175
176 bool has_stopmode;
177 bool has_freqsel;
178 bool has_selfreqdco;
179 bool has_refsel;
180};
181
182struct dss_pll {
183 const char *name;
184 enum dss_pll_id id;
185
186 struct clk *clkin;
187 struct regulator *regulator;
188
189 void __iomem *base;
190
191 const struct dss_pll_hw *hw;
192
193 const struct dss_pll_ops *ops;
194
195 struct dss_pll_clock_info cinfo;
196};
197
198struct dispc_clock_info {
199 /* rates that we get with dividers below */
200 unsigned long lck;
201 unsigned long pck;
202
203 /* dividers */
204 u16 lck_div;
205 u16 pck_div;
206};
207
208struct dss_lcd_mgr_config {
209 enum dss_io_pad_mode io_pad_mode;
210
211 bool stallmode;
212 bool fifohandcheck;
213
214 struct dispc_clock_info clock_info;
215
216 int video_port_width;
217
218 int lcden_sig_polarity;
219};
220
221struct seq_file;
222struct platform_device;
223
224/* core */
225struct platform_device *dss_get_core_pdev(void);
226int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
227void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
228int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
229int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
230
231static inline bool dss_mgr_is_lcd(enum omap_channel id)
232{
233 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
234 id == OMAP_DSS_CHANNEL_LCD3)
235 return true;
236 else
237 return false;
238}
239
240/* DSS */
241int dss_init_platform_driver(void) __init;
242void dss_uninit_platform_driver(void);
243
244int dss_runtime_get(void);
245void dss_runtime_put(void);
246
247unsigned long dss_get_dispc_clk_rate(void);
248int dss_dpi_select_source(int port, enum omap_channel channel);
249void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
250enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
251const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
252void dss_dump_clocks(struct seq_file *s);
253
254/* DSS VIDEO PLL */
255struct dss_pll *dss_video_pll_init(struct platform_device *pdev, int id,
256 struct regulator *regulator);
257void dss_video_pll_uninit(struct dss_pll *pll);
258
259/* dss-of */
260struct device_node *dss_of_port_get_parent_device(struct device_node *port);
261u32 dss_of_port_get_port_number(struct device_node *port);
262
263#if defined(CONFIG_OMAP2_DSS_DEBUGFS)
264void dss_debug_dump_clocks(struct seq_file *s);
265#endif
266
267void dss_ctrl_pll_enable(enum dss_pll_id pll_id, bool enable);
268
269void dss_sdi_init(int datapairs);
270int dss_sdi_enable(void);
271void dss_sdi_disable(void);
272
273void dss_select_dsi_clk_source(int dsi_module,
274 enum dss_clk_source clk_src);
275void dss_select_lcd_clk_source(enum omap_channel channel,
276 enum dss_clk_source clk_src);
277enum dss_clk_source dss_get_dispc_clk_source(void);
278enum dss_clk_source dss_get_dsi_clk_source(int dsi_module);
279enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
280
281void dss_set_venc_output(enum omap_dss_venc_type type);
282void dss_set_dac_pwrdn_bgz(bool enable);
283
284int dss_set_fck_rate(unsigned long rate);
285
286typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
287bool dss_div_calc(unsigned long pck, unsigned long fck_min,
288 dss_div_calc_func func, void *data);
289
290/* SDI */
291int sdi_init_platform_driver(void) __init;
292void sdi_uninit_platform_driver(void);
293
294#ifdef CONFIG_OMAP2_DSS_SDI
295int sdi_init_port(struct platform_device *pdev, struct device_node *port);
296void sdi_uninit_port(struct device_node *port);
297#else
298static inline int sdi_init_port(struct platform_device *pdev,
299 struct device_node *port)
300{
301 return 0;
302}
303static inline void sdi_uninit_port(struct device_node *port)
304{
305}
306#endif
307
308/* DSI */
309
310#ifdef CONFIG_OMAP2_DSS_DSI
311
312struct dentry;
313struct file_operations;
314
315int dsi_init_platform_driver(void) __init;
316void dsi_uninit_platform_driver(void);
317
318void dsi_dump_clocks(struct seq_file *s);
319
320void dsi_irq_handler(void);
321u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
322
323#else
324static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
325{
326 WARN(1, "%s: DSI not compiled in, returning pixel_size as 0\n",
327 __func__);
328 return 0;
329}
330#endif
331
332/* DPI */
333int dpi_init_platform_driver(void) __init;
334void dpi_uninit_platform_driver(void);
335
336#ifdef CONFIG_OMAP2_DSS_DPI
337int dpi_init_port(struct platform_device *pdev, struct device_node *port);
338void dpi_uninit_port(struct device_node *port);
339#else
340static inline int dpi_init_port(struct platform_device *pdev,
341 struct device_node *port)
342{
343 return 0;
344}
345static inline void dpi_uninit_port(struct device_node *port)
346{
347}
348#endif
349
350/* DISPC */
351int dispc_init_platform_driver(void) __init;
352void dispc_uninit_platform_driver(void);
353void dispc_dump_clocks(struct seq_file *s);
354
355void dispc_enable_sidle(void);
356void dispc_disable_sidle(void);
357
358void dispc_lcd_enable_signal(bool enable);
359void dispc_pck_free_enable(bool enable);
360void dispc_enable_fifomerge(bool enable);
361void dispc_enable_gamma_table(bool enable);
362
363typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
364 unsigned long pck, void *data);
365bool dispc_div_calc(unsigned long dispc,
366 unsigned long pck_min, unsigned long pck_max,
367 dispc_div_calc_func func, void *data);
368
369bool dispc_mgr_timings_ok(enum omap_channel channel, const struct videomode *vm);
370int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
371 struct dispc_clock_info *cinfo);
372
373
374void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
375void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
376 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
377 bool manual_update);
378
379void dispc_mgr_set_clock_div(enum omap_channel channel,
380 const struct dispc_clock_info *cinfo);
381int dispc_mgr_get_clock_div(enum omap_channel channel,
382 struct dispc_clock_info *cinfo);
383void dispc_set_tv_pclk(unsigned long pclk);
384
385u32 dispc_wb_get_framedone_irq(void);
386bool dispc_wb_go_busy(void);
387void dispc_wb_go(void);
388void dispc_wb_enable(bool enable);
389bool dispc_wb_is_enabled(void);
390void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
391int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
392 bool mem_to_mem, const struct videomode *vm);
393
394/* VENC */
395int venc_init_platform_driver(void) __init;
396void venc_uninit_platform_driver(void);
397
398/* HDMI */
399int hdmi4_init_platform_driver(void) __init;
400void hdmi4_uninit_platform_driver(void);
401
402int hdmi5_init_platform_driver(void) __init;
403void hdmi5_uninit_platform_driver(void);
404
405/* RFBI */
406int rfbi_init_platform_driver(void) __init;
407void rfbi_uninit_platform_driver(void);
408
409
410#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
411static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
412{
413 int b;
414 for (b = 0; b < 32; ++b) {
415 if (irqstatus & (1 << b))
416 irq_arr[b]++;
417 }
418}
419#endif
420
421/* PLL */
422typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
423 unsigned long clkdco, void *data);
424typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
425 void *data);
426
427int dss_pll_register(struct dss_pll *pll);
428void dss_pll_unregister(struct dss_pll *pll);
429struct dss_pll *dss_pll_find(const char *name);
430struct dss_pll *dss_pll_find_by_src(enum dss_clk_source src);
431unsigned dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
432int dss_pll_enable(struct dss_pll *pll);
433void dss_pll_disable(struct dss_pll *pll);
434int dss_pll_set_config(struct dss_pll *pll,
435 const struct dss_pll_clock_info *cinfo);
436
437bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
438 unsigned long out_min, unsigned long out_max,
439 dss_hsdiv_calc_func func, void *data);
440bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
441 unsigned long pll_min, unsigned long pll_max,
442 dss_pll_calc_func func, void *data);
443
444bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
445 unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
446
447int dss_pll_write_config_type_a(struct dss_pll *pll,
448 const struct dss_pll_clock_info *cinfo);
449int dss_pll_write_config_type_b(struct dss_pll *pll,
450 const struct dss_pll_clock_info *cinfo);
451int dss_pll_wait_reset_done(struct dss_pll *pll);
452
453#endif