Loading...
Note: File does not exist in v4.10.11.
1/*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/delay.h>
25#include <linux/firmware.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28
29#include "amdgpu.h"
30#include "amdgpu_ucode.h"
31#include "amdgpu_trace.h"
32
33#include "gc/gc_11_0_0_offset.h"
34#include "gc/gc_11_0_0_sh_mask.h"
35#include "gc/gc_11_0_0_default.h"
36#include "hdp/hdp_6_0_0_offset.h"
37#include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
38
39#include "soc15_common.h"
40#include "soc15.h"
41#include "sdma_v6_0_0_pkt_open.h"
42#include "nbio_v4_3.h"
43#include "sdma_common.h"
44#include "sdma_v6_0.h"
45#include "v11_structs.h"
46
47MODULE_FIRMWARE("amdgpu/sdma_6_0_0.bin");
48MODULE_FIRMWARE("amdgpu/sdma_6_0_1.bin");
49MODULE_FIRMWARE("amdgpu/sdma_6_0_2.bin");
50MODULE_FIRMWARE("amdgpu/sdma_6_0_3.bin");
51MODULE_FIRMWARE("amdgpu/sdma_6_1_0.bin");
52MODULE_FIRMWARE("amdgpu/sdma_6_1_1.bin");
53MODULE_FIRMWARE("amdgpu/sdma_6_1_2.bin");
54
55#define SDMA1_REG_OFFSET 0x600
56#define SDMA0_HYP_DEC_REG_START 0x5880
57#define SDMA0_HYP_DEC_REG_END 0x589a
58#define SDMA1_HYP_DEC_REG_OFFSET 0x20
59
60static const struct amdgpu_hwip_reg_entry sdma_reg_list_6_0[] = {
61 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG),
62 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG),
63 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS2_REG),
64 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS3_REG),
65 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS4_REG),
66 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS5_REG),
67 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS6_REG),
68 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UCODE_CHECKSUM),
69 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH_HI),
70 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_RB_RPTR_FETCH),
71 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_STATUS),
72 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_STATUS),
73 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK0),
74 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_RD_XNACK1),
75 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK0),
76 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_UTCL1_WR_XNACK1),
77 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_CNTL),
78 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR),
79 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_RPTR_HI),
80 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR),
81 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_RB_WPTR_HI),
82 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_OFFSET),
83 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_LO),
84 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_BASE_HI),
85 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_CNTL),
86 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_RPTR),
87 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_IB_SUB_REMAIN),
88 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE0_DUMMY_REG),
89 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE_STATUS0),
90 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_CNTL),
91 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR),
92 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_RPTR_HI),
93 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR),
94 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_RB_WPTR_HI),
95 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_OFFSET),
96 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_LO),
97 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_BASE_HI),
98 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_RPTR),
99 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_IB_SUB_REMAIN),
100 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE1_DUMMY_REG),
101 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_CNTL),
102 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR),
103 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_RPTR_HI),
104 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_RB_WPTR_HI),
106 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_OFFSET),
107 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_LO),
108 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_BASE_HI),
109 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_RPTR),
110 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_IB_SUB_REMAIN),
111 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_QUEUE2_DUMMY_REG),
112 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_INT_STATUS),
113 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
114 SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_CHICKEN_BITS),
115};
116
117static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev);
118static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev);
119static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev);
120static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev);
121static int sdma_v6_0_start(struct amdgpu_device *adev);
122
123static u32 sdma_v6_0_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
124{
125 u32 base;
126
127 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
128 internal_offset <= SDMA0_HYP_DEC_REG_END) {
129 base = adev->reg_offset[GC_HWIP][0][1];
130 if (instance != 0)
131 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
132 } else {
133 base = adev->reg_offset[GC_HWIP][0][0];
134 if (instance == 1)
135 internal_offset += SDMA1_REG_OFFSET;
136 }
137
138 return base + internal_offset;
139}
140
141static unsigned sdma_v6_0_ring_init_cond_exec(struct amdgpu_ring *ring,
142 uint64_t addr)
143{
144 unsigned ret;
145
146 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COND_EXE));
147 amdgpu_ring_write(ring, lower_32_bits(addr));
148 amdgpu_ring_write(ring, upper_32_bits(addr));
149 amdgpu_ring_write(ring, 1);
150 /* this is the offset we need patch later */
151 ret = ring->wptr & ring->buf_mask;
152 /* insert dummy here and patch it later */
153 amdgpu_ring_write(ring, 0);
154
155 return ret;
156}
157
158/**
159 * sdma_v6_0_ring_get_rptr - get the current read pointer
160 *
161 * @ring: amdgpu ring pointer
162 *
163 * Get the current rptr from the hardware.
164 */
165static uint64_t sdma_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
166{
167 u64 *rptr;
168
169 /* XXX check if swapping is necessary on BE */
170 rptr = (u64 *)ring->rptr_cpu_addr;
171
172 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
173 return ((*rptr) >> 2);
174}
175
176/**
177 * sdma_v6_0_ring_get_wptr - get the current write pointer
178 *
179 * @ring: amdgpu ring pointer
180 *
181 * Get the current wptr from the hardware.
182 */
183static uint64_t sdma_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
184{
185 u64 wptr = 0;
186
187 if (ring->use_doorbell) {
188 /* XXX check if swapping is necessary on BE */
189 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
190 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
191 }
192
193 return wptr >> 2;
194}
195
196/**
197 * sdma_v6_0_ring_set_wptr - commit the write pointer
198 *
199 * @ring: amdgpu ring pointer
200 *
201 * Write the wptr back to the hardware.
202 */
203static void sdma_v6_0_ring_set_wptr(struct amdgpu_ring *ring)
204{
205 struct amdgpu_device *adev = ring->adev;
206
207 if (ring->use_doorbell) {
208 DRM_DEBUG("Using doorbell -- "
209 "wptr_offs == 0x%08x "
210 "lower_32_bits(ring->wptr) << 2 == 0x%08x "
211 "upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
212 ring->wptr_offs,
213 lower_32_bits(ring->wptr << 2),
214 upper_32_bits(ring->wptr << 2));
215 /* XXX check if swapping is necessary on BE */
216 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
217 ring->wptr << 2);
218 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
219 ring->doorbell_index, ring->wptr << 2);
220 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
221 } else {
222 DRM_DEBUG("Not using doorbell -- "
223 "regSDMA%i_GFX_RB_WPTR == 0x%08x "
224 "regSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
225 ring->me,
226 lower_32_bits(ring->wptr << 2),
227 ring->me,
228 upper_32_bits(ring->wptr << 2));
229 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
230 ring->me, regSDMA0_QUEUE0_RB_WPTR),
231 lower_32_bits(ring->wptr << 2));
232 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev,
233 ring->me, regSDMA0_QUEUE0_RB_WPTR_HI),
234 upper_32_bits(ring->wptr << 2));
235 }
236}
237
238static void sdma_v6_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
239{
240 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
241 int i;
242
243 for (i = 0; i < count; i++)
244 if (sdma && sdma->burst_nop && (i == 0))
245 amdgpu_ring_write(ring, ring->funcs->nop |
246 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
247 else
248 amdgpu_ring_write(ring, ring->funcs->nop);
249}
250
251/*
252 * sdma_v6_0_ring_emit_ib - Schedule an IB on the DMA engine
253 *
254 * @ring: amdgpu ring pointer
255 * @ib: IB object to schedule
256 * @flags: unused
257 * @job: job to retrieve vmid from
258 *
259 * Schedule an IB in the DMA ring.
260 */
261static void sdma_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
262 struct amdgpu_job *job,
263 struct amdgpu_ib *ib,
264 uint32_t flags)
265{
266 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
267 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
268
269 /* An IB packet must end on a 8 DW boundary--the next dword
270 * must be on a 8-dword boundary. Our IB packet below is 6
271 * dwords long, thus add x number of NOPs, such that, in
272 * modular arithmetic,
273 * wptr + 6 + x = 8k, k >= 0, which in C is,
274 * (wptr + 6 + x) % 8 = 0.
275 * The expression below, is a solution of x.
276 */
277 sdma_v6_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
278
279 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_INDIRECT) |
280 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
281 /* base must be 32 byte aligned */
282 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
283 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
284 amdgpu_ring_write(ring, ib->length_dw);
285 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
286 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
287}
288
289/**
290 * sdma_v6_0_ring_emit_mem_sync - flush the IB by graphics cache rinse
291 *
292 * @ring: amdgpu ring pointer
293 *
294 * flush the IB by graphics cache rinse.
295 */
296static void sdma_v6_0_ring_emit_mem_sync(struct amdgpu_ring *ring)
297{
298 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB | SDMA_GCR_GLM_INV |
299 SDMA_GCR_GL1_INV | SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
300 SDMA_GCR_GLI_INV(1);
301
302 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
303 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_GCR_REQ));
304 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
305 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
306 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
307 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
308 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
309 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
310 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
311}
312
313
314/**
315 * sdma_v6_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
316 *
317 * @ring: amdgpu ring pointer
318 *
319 * Emit an hdp flush packet on the requested DMA ring.
320 */
321static void sdma_v6_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
322{
323 struct amdgpu_device *adev = ring->adev;
324 u32 ref_and_mask = 0;
325 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
326
327 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
328
329 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
330 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
331 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
332 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
333 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
334 amdgpu_ring_write(ring, ref_and_mask); /* reference */
335 amdgpu_ring_write(ring, ref_and_mask); /* mask */
336 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
337 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
338}
339
340/**
341 * sdma_v6_0_ring_emit_fence - emit a fence on the DMA ring
342 *
343 * @ring: amdgpu ring pointer
344 * @addr: address
345 * @seq: fence seq number
346 * @flags: fence flags
347 *
348 * Add a DMA fence packet to the ring to write
349 * the fence seq number and DMA trap packet to generate
350 * an interrupt if needed.
351 */
352static void sdma_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
353 unsigned flags)
354{
355 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
356 /* write the fence */
357 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
358 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
359 /* zero in first two bits */
360 BUG_ON(addr & 0x3);
361 amdgpu_ring_write(ring, lower_32_bits(addr));
362 amdgpu_ring_write(ring, upper_32_bits(addr));
363 amdgpu_ring_write(ring, lower_32_bits(seq));
364
365 /* optionally write high bits as well */
366 if (write64bit) {
367 addr += 4;
368 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_FENCE) |
369 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
370 /* zero in first two bits */
371 BUG_ON(addr & 0x3);
372 amdgpu_ring_write(ring, lower_32_bits(addr));
373 amdgpu_ring_write(ring, upper_32_bits(addr));
374 amdgpu_ring_write(ring, upper_32_bits(seq));
375 }
376
377 if (flags & AMDGPU_FENCE_FLAG_INT) {
378 uint32_t ctx = ring->is_mes_queue ?
379 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
380 /* generate an interrupt */
381 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_TRAP));
382 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
383 }
384}
385
386/**
387 * sdma_v6_0_gfx_stop - stop the gfx async dma engines
388 *
389 * @adev: amdgpu_device pointer
390 *
391 * Stop the gfx async dma ring buffers.
392 */
393static void sdma_v6_0_gfx_stop(struct amdgpu_device *adev)
394{
395 u32 rb_cntl, ib_cntl;
396 int i;
397
398 for (i = 0; i < adev->sdma.num_instances; i++) {
399 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
400 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0);
401 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
402 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
403 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 0);
404 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
405 }
406}
407
408/**
409 * sdma_v6_0_rlc_stop - stop the compute async dma engines
410 *
411 * @adev: amdgpu_device pointer
412 *
413 * Stop the compute async dma queues.
414 */
415static void sdma_v6_0_rlc_stop(struct amdgpu_device *adev)
416{
417 /* XXX todo */
418}
419
420/**
421 * sdma_v6_0_ctxempty_int_enable - enable or disable context empty interrupts
422 *
423 * @adev: amdgpu_device pointer
424 * @enable: enable/disable context switching due to queue empty conditions
425 *
426 * Enable or disable the async dma engines queue empty context switch.
427 */
428static void sdma_v6_0_ctxempty_int_enable(struct amdgpu_device *adev, bool enable)
429{
430 u32 f32_cntl;
431 int i;
432
433 if (!amdgpu_sriov_vf(adev)) {
434 for (i = 0; i < adev->sdma.num_instances; i++) {
435 f32_cntl = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL));
436 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
437 CTXEMPTY_INT_ENABLE, enable ? 1 : 0);
438 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_CNTL), f32_cntl);
439 }
440 }
441}
442
443/**
444 * sdma_v6_0_enable - stop the async dma engines
445 *
446 * @adev: amdgpu_device pointer
447 * @enable: enable/disable the DMA MEs.
448 *
449 * Halt or unhalt the async dma engines.
450 */
451static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable)
452{
453 u32 f32_cntl;
454 int i;
455
456 if (!enable) {
457 sdma_v6_0_gfx_stop(adev);
458 sdma_v6_0_rlc_stop(adev);
459 }
460
461 if (amdgpu_sriov_vf(adev))
462 return;
463
464 for (i = 0; i < adev->sdma.num_instances; i++) {
465 f32_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
466 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
467 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), f32_cntl);
468 }
469}
470
471/**
472 * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine
473 *
474 * @adev: amdgpu_device pointer
475 * @i: instance
476 * @restore: used to restore wptr when restart
477 *
478 * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr.
479 * Return 0 for success.
480 */
481static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore)
482{
483 struct amdgpu_ring *ring;
484 u32 rb_cntl, ib_cntl;
485 u32 rb_bufsz;
486 u32 doorbell;
487 u32 doorbell_offset;
488 u32 temp;
489 u64 wptr_gpu_addr;
490
491 ring = &adev->sdma.instance[i].ring;
492 if (!amdgpu_sriov_vf(adev))
493 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
494
495 /* Set ring buffer size in dwords */
496 rb_bufsz = order_base_2(ring->ring_size / 4);
497 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
498 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz);
499#ifdef __BIG_ENDIAN
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1);
501 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL,
502 RPTR_WRITEBACK_SWAP_ENABLE, 1);
503#endif
504 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1);
505 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
506
507 /* Initialize the ring buffer's read and write pointers */
508 if (restore) {
509 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2));
510 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2));
511 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2));
512 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
513 } else {
514 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0);
515 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0);
516 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0);
517 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0);
518 }
519 /* setup the wptr shadow polling */
520 wptr_gpu_addr = ring->wptr_gpu_addr;
521 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO),
522 lower_32_bits(wptr_gpu_addr));
523 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI),
524 upper_32_bits(wptr_gpu_addr));
525
526 /* set the wb address whether it's enabled or not */
527 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI),
528 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
529 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO),
530 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
531
532 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
533 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0);
534 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1);
535
536 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8);
537 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40);
538
539 if (!restore)
540 ring->wptr = 0;
541
542 /* before programing wptr to a less value, need set minor_ptr_update first */
543 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1);
544
545 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
546 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2);
547 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2);
548 }
549
550 doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL));
551 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET));
552
553 if (ring->use_doorbell) {
554 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
555 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET,
556 OFFSET, ring->doorbell_index);
557 } else {
558 doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0);
559 }
560 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell);
561 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset);
562
563 if (i == 0)
564 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
565 ring->doorbell_index,
566 adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances);
567
568 if (amdgpu_sriov_vf(adev))
569 sdma_v6_0_ring_set_wptr(ring);
570
571 /* set minor_ptr_update to 0 after wptr programed */
572 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0);
573
574 /* Set up sdma hang watchdog */
575 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL));
576 /* 100ms per unit */
577 temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT,
578 max(adev->usec_timeout/100000, 1));
579 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp);
580
581 /* Set up RESP_MODE to non-copy addresses */
582 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL));
583 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
584 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
585 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp);
586
587 /* program default cache read and write policy */
588 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE));
589 /* clean read policy and write policy bits */
590 temp &= 0xFF0FFF;
591 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
592 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
593 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
594 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp);
595
596 if (!amdgpu_sriov_vf(adev)) {
597 /* unhalt engine */
598 temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
599 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
600 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0);
601 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp);
602 }
603
604 /* enable DMA RB */
605 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1);
606 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
607
608 ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL));
609 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1);
610#ifdef __BIG_ENDIAN
611 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1);
612#endif
613 /* enable DMA IBs */
614 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl);
615
616 if (amdgpu_sriov_vf(adev))
617 sdma_v6_0_enable(adev, true);
618
619 return amdgpu_ring_test_helper(ring);
620}
621
622/**
623 * sdma_v6_0_gfx_resume - setup and start the async dma engines
624 *
625 * @adev: amdgpu_device pointer
626 *
627 * Set up the gfx DMA ring buffers and enable them.
628 * Returns 0 for success, error for failure.
629 */
630static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev)
631{
632 int i, r;
633
634 for (i = 0; i < adev->sdma.num_instances; i++) {
635 r = sdma_v6_0_gfx_resume_instance(adev, i, false);
636 if (r)
637 return r;
638 }
639
640 return 0;
641}
642
643/**
644 * sdma_v6_0_rlc_resume - setup and start the async dma engines
645 *
646 * @adev: amdgpu_device pointer
647 *
648 * Set up the compute DMA queues and enable them.
649 * Returns 0 for success, error for failure.
650 */
651static int sdma_v6_0_rlc_resume(struct amdgpu_device *adev)
652{
653 return 0;
654}
655
656/**
657 * sdma_v6_0_load_microcode - load the sDMA ME ucode
658 *
659 * @adev: amdgpu_device pointer
660 *
661 * Loads the sDMA0/1 ucode.
662 * Returns 0 for success, -EINVAL if the ucode is not available.
663 */
664static int sdma_v6_0_load_microcode(struct amdgpu_device *adev)
665{
666 const struct sdma_firmware_header_v2_0 *hdr;
667 const __le32 *fw_data;
668 u32 fw_size;
669 int i, j;
670 bool use_broadcast;
671
672 /* halt the MEs */
673 sdma_v6_0_enable(adev, false);
674
675 if (!adev->sdma.instance[0].fw)
676 return -EINVAL;
677
678 /* use broadcast mode to load SDMA microcode by default */
679 use_broadcast = true;
680
681 if (use_broadcast) {
682 dev_info(adev->dev, "Use broadcast method to load SDMA firmware\n");
683 /* load Control Thread microcode */
684 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
685 amdgpu_ucode_print_sdma_hdr(&hdr->header);
686 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
687
688 fw_data = (const __le32 *)
689 (adev->sdma.instance[0].fw->data +
690 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
691
692 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0);
693
694 for (j = 0; j < fw_size; j++) {
695 if (amdgpu_emu_mode == 1 && j % 500 == 0)
696 msleep(1);
697 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
698 }
699
700 /* load Context Switch microcode */
701 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
702
703 fw_data = (const __le32 *)
704 (adev->sdma.instance[0].fw->data +
705 le32_to_cpu(hdr->ctl_ucode_offset));
706
707 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_ADDR), 0x8000);
708
709 for (j = 0; j < fw_size; j++) {
710 if (amdgpu_emu_mode == 1 && j % 500 == 0)
711 msleep(1);
712 WREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_BROADCAST_UCODE_DATA), le32_to_cpup(fw_data++));
713 }
714 } else {
715 dev_info(adev->dev, "Use legacy method to load SDMA firmware\n");
716 for (i = 0; i < adev->sdma.num_instances; i++) {
717 /* load Control Thread microcode */
718 hdr = (const struct sdma_firmware_header_v2_0 *)adev->sdma.instance[0].fw->data;
719 amdgpu_ucode_print_sdma_hdr(&hdr->header);
720 fw_size = le32_to_cpu(hdr->ctx_jt_offset + hdr->ctx_jt_size) / 4;
721
722 fw_data = (const __le32 *)
723 (adev->sdma.instance[0].fw->data +
724 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
725
726 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0);
727
728 for (j = 0; j < fw_size; j++) {
729 if (amdgpu_emu_mode == 1 && j % 500 == 0)
730 msleep(1);
731 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
732 }
733
734 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
735
736 /* load Context Switch microcode */
737 fw_size = le32_to_cpu(hdr->ctl_jt_offset + hdr->ctl_jt_size) / 4;
738
739 fw_data = (const __le32 *)
740 (adev->sdma.instance[0].fw->data +
741 le32_to_cpu(hdr->ctl_ucode_offset));
742
743 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), 0x8000);
744
745 for (j = 0; j < fw_size; j++) {
746 if (amdgpu_emu_mode == 1 && j % 500 == 0)
747 msleep(1);
748 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
749 }
750
751 WREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UCODE_ADDR), adev->sdma.instance[0].fw_version);
752 }
753 }
754
755 return 0;
756}
757
758static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
759{
760 struct amdgpu_device *adev = ip_block->adev;
761 u32 tmp;
762 int i;
763
764 sdma_v6_0_gfx_stop(adev);
765
766 for (i = 0; i < adev->sdma.num_instances; i++) {
767 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE));
768 tmp |= SDMA0_FREEZE__FREEZE_MASK;
769 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_FREEZE), tmp);
770 tmp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL));
771 tmp |= SDMA0_F32_CNTL__HALT_MASK;
772 tmp |= SDMA0_F32_CNTL__TH1_RESET_MASK;
773 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), tmp);
774
775 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_PREEMPT), 0);
776
777 udelay(100);
778
779 tmp = GRBM_SOFT_RESET__SOFT_RESET_SDMA0_MASK << i;
780 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, tmp);
781 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
782
783 udelay(100);
784
785 WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, 0);
786 tmp = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
787
788 udelay(100);
789 }
790
791 return sdma_v6_0_start(adev);
792}
793
794static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
795{
796 struct amdgpu_device *adev = ip_block->adev;
797 struct amdgpu_ring *ring;
798 int i, r;
799 long tmo = msecs_to_jiffies(1000);
800
801 for (i = 0; i < adev->sdma.num_instances; i++) {
802 ring = &adev->sdma.instance[i].ring;
803 r = amdgpu_ring_test_ib(ring, tmo);
804 if (r)
805 return true;
806 }
807
808 return false;
809}
810
811/**
812 * sdma_v6_0_start - setup and start the async dma engines
813 *
814 * @adev: amdgpu_device pointer
815 *
816 * Set up the DMA engines and enable them.
817 * Returns 0 for success, error for failure.
818 */
819static int sdma_v6_0_start(struct amdgpu_device *adev)
820{
821 int r = 0;
822
823 if (amdgpu_sriov_vf(adev)) {
824 sdma_v6_0_enable(adev, false);
825
826 /* set RB registers */
827 r = sdma_v6_0_gfx_resume(adev);
828 return r;
829 }
830
831 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
832 r = sdma_v6_0_load_microcode(adev);
833 if (r)
834 return r;
835
836 /* The value of regSDMA_F32_CNTL is invalid the moment after loading fw */
837 if (amdgpu_emu_mode == 1)
838 msleep(1000);
839 }
840
841 /* unhalt the MEs */
842 sdma_v6_0_enable(adev, true);
843 /* enable sdma ring preemption */
844 sdma_v6_0_ctxempty_int_enable(adev, true);
845
846 /* start the gfx rings and rlc compute queues */
847 r = sdma_v6_0_gfx_resume(adev);
848 if (r)
849 return r;
850 r = sdma_v6_0_rlc_resume(adev);
851
852 return r;
853}
854
855static int sdma_v6_0_mqd_init(struct amdgpu_device *adev, void *mqd,
856 struct amdgpu_mqd_prop *prop)
857{
858 struct v11_sdma_mqd *m = mqd;
859 uint64_t wb_gpu_addr;
860
861 m->sdmax_rlcx_rb_cntl =
862 order_base_2(prop->queue_size / 4) << SDMA0_QUEUE0_RB_CNTL__RB_SIZE__SHIFT |
863 1 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
864 4 << SDMA0_QUEUE0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
865 1 << SDMA0_QUEUE0_RB_CNTL__F32_WPTR_POLL_ENABLE__SHIFT;
866
867 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
868 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
869
870 wb_gpu_addr = prop->wptr_gpu_addr;
871 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
872 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
873
874 wb_gpu_addr = prop->rptr_gpu_addr;
875 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
876 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
877
878 m->sdmax_rlcx_ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, 0,
879 regSDMA0_QUEUE0_IB_CNTL));
880
881 m->sdmax_rlcx_doorbell_offset =
882 prop->doorbell_index << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT;
883
884 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_QUEUE0_DOORBELL, ENABLE, 1);
885
886 m->sdmax_rlcx_skip_cntl = 0;
887 m->sdmax_rlcx_context_status = 0;
888 m->sdmax_rlcx_doorbell_log = 0;
889
890 m->sdmax_rlcx_rb_aql_cntl = regSDMA0_QUEUE0_RB_AQL_CNTL_DEFAULT;
891 m->sdmax_rlcx_dummy_reg = regSDMA0_QUEUE0_DUMMY_REG_DEFAULT;
892
893 return 0;
894}
895
896static void sdma_v6_0_set_mqd_funcs(struct amdgpu_device *adev)
897{
898 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v11_sdma_mqd);
899 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v6_0_mqd_init;
900}
901
902/**
903 * sdma_v6_0_ring_test_ring - simple async dma engine test
904 *
905 * @ring: amdgpu_ring structure holding ring information
906 *
907 * Test the DMA engine by writing using it to write an
908 * value to memory.
909 * Returns 0 for success, error for failure.
910 */
911static int sdma_v6_0_ring_test_ring(struct amdgpu_ring *ring)
912{
913 struct amdgpu_device *adev = ring->adev;
914 unsigned i;
915 unsigned index;
916 int r;
917 u32 tmp;
918 u64 gpu_addr;
919 volatile uint32_t *cpu_ptr = NULL;
920
921 tmp = 0xCAFEDEAD;
922
923 if (ring->is_mes_queue) {
924 uint32_t offset = 0;
925 offset = amdgpu_mes_ctx_get_offs(ring,
926 AMDGPU_MES_CTX_PADDING_OFFS);
927 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
928 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
929 *cpu_ptr = tmp;
930 } else {
931 r = amdgpu_device_wb_get(adev, &index);
932 if (r) {
933 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
934 return r;
935 }
936
937 gpu_addr = adev->wb.gpu_addr + (index * 4);
938 adev->wb.wb[index] = cpu_to_le32(tmp);
939 }
940
941 r = amdgpu_ring_alloc(ring, 5);
942 if (r) {
943 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
944 if (!ring->is_mes_queue)
945 amdgpu_device_wb_free(adev, index);
946 return r;
947 }
948
949 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
950 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
951 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
952 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
953 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
954 amdgpu_ring_write(ring, 0xDEADBEEF);
955 amdgpu_ring_commit(ring);
956
957 for (i = 0; i < adev->usec_timeout; i++) {
958 if (ring->is_mes_queue)
959 tmp = le32_to_cpu(*cpu_ptr);
960 else
961 tmp = le32_to_cpu(adev->wb.wb[index]);
962 if (tmp == 0xDEADBEEF)
963 break;
964 if (amdgpu_emu_mode == 1)
965 msleep(1);
966 else
967 udelay(1);
968 }
969
970 if (i >= adev->usec_timeout)
971 r = -ETIMEDOUT;
972
973 if (!ring->is_mes_queue)
974 amdgpu_device_wb_free(adev, index);
975
976 return r;
977}
978
979/*
980 * sdma_v6_0_ring_test_ib - test an IB on the DMA engine
981 *
982 * @ring: amdgpu_ring structure holding ring information
983 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
984 *
985 * Test a simple IB in the DMA ring.
986 * Returns 0 on success, error on failure.
987 */
988static int sdma_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
989{
990 struct amdgpu_device *adev = ring->adev;
991 struct amdgpu_ib ib;
992 struct dma_fence *f = NULL;
993 unsigned index;
994 long r;
995 u32 tmp = 0;
996 u64 gpu_addr;
997 volatile uint32_t *cpu_ptr = NULL;
998
999 tmp = 0xCAFEDEAD;
1000 memset(&ib, 0, sizeof(ib));
1001
1002 if (ring->is_mes_queue) {
1003 uint32_t offset = 0;
1004 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
1005 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1006 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1007
1008 offset = amdgpu_mes_ctx_get_offs(ring,
1009 AMDGPU_MES_CTX_PADDING_OFFS);
1010 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
1011 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
1012 *cpu_ptr = tmp;
1013 } else {
1014 r = amdgpu_device_wb_get(adev, &index);
1015 if (r) {
1016 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
1017 return r;
1018 }
1019
1020 gpu_addr = adev->wb.gpu_addr + (index * 4);
1021 adev->wb.wb[index] = cpu_to_le32(tmp);
1022
1023 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1024 if (r) {
1025 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1026 goto err0;
1027 }
1028 }
1029
1030 ib.ptr[0] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1031 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1032 ib.ptr[1] = lower_32_bits(gpu_addr);
1033 ib.ptr[2] = upper_32_bits(gpu_addr);
1034 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
1035 ib.ptr[4] = 0xDEADBEEF;
1036 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1037 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1038 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
1039 ib.length_dw = 8;
1040
1041 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1042 if (r)
1043 goto err1;
1044
1045 r = dma_fence_wait_timeout(f, false, timeout);
1046 if (r == 0) {
1047 DRM_ERROR("amdgpu: IB test timed out\n");
1048 r = -ETIMEDOUT;
1049 goto err1;
1050 } else if (r < 0) {
1051 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1052 goto err1;
1053 }
1054
1055 if (ring->is_mes_queue)
1056 tmp = le32_to_cpu(*cpu_ptr);
1057 else
1058 tmp = le32_to_cpu(adev->wb.wb[index]);
1059
1060 if (tmp == 0xDEADBEEF)
1061 r = 0;
1062 else
1063 r = -EINVAL;
1064
1065err1:
1066 amdgpu_ib_free(adev, &ib, NULL);
1067 dma_fence_put(f);
1068err0:
1069 if (!ring->is_mes_queue)
1070 amdgpu_device_wb_free(adev, index);
1071 return r;
1072}
1073
1074
1075/**
1076 * sdma_v6_0_vm_copy_pte - update PTEs by copying them from the GART
1077 *
1078 * @ib: indirect buffer to fill with commands
1079 * @pe: addr of the page entry
1080 * @src: src addr to copy from
1081 * @count: number of page entries to update
1082 *
1083 * Update PTEs by copying them from the GART using sDMA.
1084 */
1085static void sdma_v6_0_vm_copy_pte(struct amdgpu_ib *ib,
1086 uint64_t pe, uint64_t src,
1087 unsigned count)
1088{
1089 unsigned bytes = count * 8;
1090
1091 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1092 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1093 ib->ptr[ib->length_dw++] = bytes - 1;
1094 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1095 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1096 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1097 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1098 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1099
1100}
1101
1102/**
1103 * sdma_v6_0_vm_write_pte - update PTEs by writing them manually
1104 *
1105 * @ib: indirect buffer to fill with commands
1106 * @pe: addr of the page entry
1107 * @value: dst addr to write into pe
1108 * @count: number of page entries to update
1109 * @incr: increase next addr by incr bytes
1110 *
1111 * Update PTEs by writing them manually using sDMA.
1112 */
1113static void sdma_v6_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1114 uint64_t value, unsigned count,
1115 uint32_t incr)
1116{
1117 unsigned ndw = count * 2;
1118
1119 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_WRITE) |
1120 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1121 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1122 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1123 ib->ptr[ib->length_dw++] = ndw - 1;
1124 for (; ndw > 0; ndw -= 2) {
1125 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1126 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1127 value += incr;
1128 }
1129}
1130
1131/**
1132 * sdma_v6_0_vm_set_pte_pde - update the page tables using sDMA
1133 *
1134 * @ib: indirect buffer to fill with commands
1135 * @pe: addr of the page entry
1136 * @addr: dst addr to write into pe
1137 * @count: number of page entries to update
1138 * @incr: increase next addr by incr bytes
1139 * @flags: access flags
1140 *
1141 * Update the page tables using sDMA.
1142 */
1143static void sdma_v6_0_vm_set_pte_pde(struct amdgpu_ib *ib,
1144 uint64_t pe,
1145 uint64_t addr, unsigned count,
1146 uint32_t incr, uint64_t flags)
1147{
1148 /* for physically contiguous pages (vram) */
1149 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_PTEPDE);
1150 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1151 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1152 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1153 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1154 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1155 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1156 ib->ptr[ib->length_dw++] = incr; /* increment size */
1157 ib->ptr[ib->length_dw++] = 0;
1158 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1159}
1160
1161/*
1162 * sdma_v6_0_ring_pad_ib - pad the IB
1163 * @ib: indirect buffer to fill with padding
1164 * @ring: amdgpu ring pointer
1165 *
1166 * Pad the IB with NOPs to a boundary multiple of 8.
1167 */
1168static void sdma_v6_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1169{
1170 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1171 u32 pad_count;
1172 int i;
1173
1174 pad_count = (-ib->length_dw) & 0x7;
1175 for (i = 0; i < pad_count; i++)
1176 if (sdma && sdma->burst_nop && (i == 0))
1177 ib->ptr[ib->length_dw++] =
1178 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP) |
1179 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1180 else
1181 ib->ptr[ib->length_dw++] =
1182 SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_NOP);
1183}
1184
1185/**
1186 * sdma_v6_0_ring_emit_pipeline_sync - sync the pipeline
1187 *
1188 * @ring: amdgpu_ring pointer
1189 *
1190 * Make sure all previous operations are completed (CIK).
1191 */
1192static void sdma_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1193{
1194 uint32_t seq = ring->fence_drv.sync_seq;
1195 uint64_t addr = ring->fence_drv.gpu_addr;
1196
1197 /* wait for idle */
1198 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1199 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1200 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1201 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1202 amdgpu_ring_write(ring, addr & 0xfffffffc);
1203 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1204 amdgpu_ring_write(ring, seq); /* reference */
1205 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1206 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1207 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1208}
1209
1210/*
1211 * sdma_v6_0_ring_emit_vm_flush - vm flush using sDMA
1212 *
1213 * @ring: amdgpu_ring pointer
1214 * @vmid: vmid number to use
1215 * @pd_addr: address
1216 *
1217 * Update the page table base and flush the VM TLB
1218 * using sDMA.
1219 */
1220static void sdma_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1221 unsigned vmid, uint64_t pd_addr)
1222{
1223 struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub];
1224 uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0);
1225
1226 /* Update the PD address for this VMID. */
1227 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
1228 (hub->ctx_addr_distance * vmid),
1229 lower_32_bits(pd_addr));
1230 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
1231 (hub->ctx_addr_distance * vmid),
1232 upper_32_bits(pd_addr));
1233
1234 /* Trigger invalidation. */
1235 amdgpu_ring_write(ring,
1236 SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1237 SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) |
1238 SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) |
1239 SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f));
1240 amdgpu_ring_write(ring, req);
1241 amdgpu_ring_write(ring, 0xFFFFFFFF);
1242 amdgpu_ring_write(ring,
1243 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) |
1244 SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F));
1245}
1246
1247static void sdma_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
1248 uint32_t reg, uint32_t val)
1249{
1250 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1251 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1252 amdgpu_ring_write(ring, reg);
1253 amdgpu_ring_write(ring, val);
1254}
1255
1256static void sdma_v6_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1257 uint32_t val, uint32_t mask)
1258{
1259 amdgpu_ring_write(ring, SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1260 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1261 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1262 amdgpu_ring_write(ring, reg << 2);
1263 amdgpu_ring_write(ring, 0);
1264 amdgpu_ring_write(ring, val); /* reference */
1265 amdgpu_ring_write(ring, mask); /* mask */
1266 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1267 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1268}
1269
1270static void sdma_v6_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1271 uint32_t reg0, uint32_t reg1,
1272 uint32_t ref, uint32_t mask)
1273{
1274 amdgpu_ring_emit_wreg(ring, reg0, ref);
1275 /* wait for a cycle to reset vm_inv_eng*_ack */
1276 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1277 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1278}
1279
1280static struct amdgpu_sdma_ras sdma_v6_0_3_ras = {
1281 .ras_block = {
1282 .ras_late_init = amdgpu_ras_block_late_init,
1283 },
1284};
1285
1286static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev)
1287{
1288 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1289 case IP_VERSION(6, 0, 3):
1290 adev->sdma.ras = &sdma_v6_0_3_ras;
1291 break;
1292 default:
1293 break;
1294 }
1295}
1296
1297static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
1298{
1299 struct amdgpu_device *adev = ip_block->adev;
1300 int r;
1301
1302 r = amdgpu_sdma_init_microcode(adev, 0, true);
1303 if (r)
1304 return r;
1305
1306 sdma_v6_0_set_ring_funcs(adev);
1307 sdma_v6_0_set_buffer_funcs(adev);
1308 sdma_v6_0_set_vm_pte_funcs(adev);
1309 sdma_v6_0_set_irq_funcs(adev);
1310 sdma_v6_0_set_mqd_funcs(adev);
1311 sdma_v6_0_set_ras_funcs(adev);
1312
1313 return 0;
1314}
1315
1316static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
1317{
1318 struct amdgpu_ring *ring;
1319 int r, i;
1320 struct amdgpu_device *adev = ip_block->adev;
1321 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1322 uint32_t *ptr;
1323
1324 /* SDMA trap event */
1325 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1326 GFX_11_0_0__SRCID__SDMA_TRAP,
1327 &adev->sdma.trap_irq);
1328 if (r)
1329 return r;
1330
1331 for (i = 0; i < adev->sdma.num_instances; i++) {
1332 ring = &adev->sdma.instance[i].ring;
1333 ring->ring_obj = NULL;
1334 ring->use_doorbell = true;
1335 ring->me = i;
1336
1337 DRM_DEBUG("SDMA %d use_doorbell being set to: [%s]\n", i,
1338 ring->use_doorbell?"true":"false");
1339
1340 ring->doorbell_index =
1341 (adev->doorbell_index.sdma_engine[i] << 1); // get DWORD offset
1342
1343 ring->vm_hub = AMDGPU_GFXHUB(0);
1344 sprintf(ring->name, "sdma%d", i);
1345 r = amdgpu_ring_init(adev, ring, 1024,
1346 &adev->sdma.trap_irq,
1347 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1348 AMDGPU_RING_PRIO_DEFAULT, NULL);
1349 if (r)
1350 return r;
1351 }
1352
1353 adev->sdma.supported_reset =
1354 amdgpu_get_soft_full_reset_mask(&adev->sdma.instance[0].ring);
1355 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) {
1356 case IP_VERSION(6, 0, 0):
1357 case IP_VERSION(6, 0, 2):
1358 case IP_VERSION(6, 0, 3):
1359 if (adev->sdma.instance[0].fw_version >= 21)
1360 adev->sdma.supported_reset |= AMDGPU_RESET_TYPE_PER_QUEUE;
1361 break;
1362 default:
1363 break;
1364 }
1365
1366 if (amdgpu_sdma_ras_sw_init(adev)) {
1367 dev_err(adev->dev, "Failed to initialize sdma ras block!\n");
1368 return -EINVAL;
1369 }
1370
1371 /* Allocate memory for SDMA IP Dump buffer */
1372 ptr = kcalloc(adev->sdma.num_instances * reg_count, sizeof(uint32_t), GFP_KERNEL);
1373 if (ptr)
1374 adev->sdma.ip_dump = ptr;
1375 else
1376 DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
1377
1378 r = amdgpu_sdma_sysfs_reset_mask_init(adev);
1379 if (r)
1380 return r;
1381
1382 return r;
1383}
1384
1385static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
1386{
1387 struct amdgpu_device *adev = ip_block->adev;
1388 int i;
1389
1390 for (i = 0; i < adev->sdma.num_instances; i++)
1391 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1392
1393 amdgpu_sdma_sysfs_reset_mask_fini(adev);
1394 amdgpu_sdma_destroy_inst_ctx(adev, true);
1395
1396 kfree(adev->sdma.ip_dump);
1397
1398 return 0;
1399}
1400
1401static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
1402{
1403 struct amdgpu_device *adev = ip_block->adev;
1404
1405 return sdma_v6_0_start(adev);
1406}
1407
1408static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
1409{
1410 struct amdgpu_device *adev = ip_block->adev;
1411
1412 if (amdgpu_sriov_vf(adev))
1413 return 0;
1414
1415 sdma_v6_0_ctxempty_int_enable(adev, false);
1416 sdma_v6_0_enable(adev, false);
1417
1418 return 0;
1419}
1420
1421static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block)
1422{
1423 return sdma_v6_0_hw_fini(ip_block);
1424}
1425
1426static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block)
1427{
1428 return sdma_v6_0_hw_init(ip_block);
1429}
1430
1431static bool sdma_v6_0_is_idle(void *handle)
1432{
1433 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1434 u32 i;
1435
1436 for (i = 0; i < adev->sdma.num_instances; i++) {
1437 u32 tmp = RREG32(sdma_v6_0_get_reg_offset(adev, i, regSDMA0_STATUS_REG));
1438
1439 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1440 return false;
1441 }
1442
1443 return true;
1444}
1445
1446static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
1447{
1448 unsigned i;
1449 u32 sdma0, sdma1;
1450 struct amdgpu_device *adev = ip_block->adev;
1451
1452 for (i = 0; i < adev->usec_timeout; i++) {
1453 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG));
1454 sdma1 = RREG32(sdma_v6_0_get_reg_offset(adev, 1, regSDMA0_STATUS_REG));
1455
1456 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK)
1457 return 0;
1458 udelay(1);
1459 }
1460 return -ETIMEDOUT;
1461}
1462
1463static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring)
1464{
1465 int i, r = 0;
1466 struct amdgpu_device *adev = ring->adev;
1467 u32 index = 0;
1468 u64 sdma_gfx_preempt;
1469
1470 amdgpu_sdma_get_index_from_ring(ring, &index);
1471 sdma_gfx_preempt =
1472 sdma_v6_0_get_reg_offset(adev, index, regSDMA0_QUEUE0_PREEMPT);
1473
1474 /* assert preemption condition */
1475 amdgpu_ring_set_preempt_cond_exec(ring, false);
1476
1477 /* emit the trailing fence */
1478 ring->trail_seq += 1;
1479 amdgpu_ring_alloc(ring, 10);
1480 sdma_v6_0_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1481 ring->trail_seq, 0);
1482 amdgpu_ring_commit(ring);
1483
1484 /* assert IB preemption */
1485 WREG32(sdma_gfx_preempt, 1);
1486
1487 /* poll the trailing fence */
1488 for (i = 0; i < adev->usec_timeout; i++) {
1489 if (ring->trail_seq ==
1490 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1491 break;
1492 udelay(1);
1493 }
1494
1495 if (i >= adev->usec_timeout) {
1496 r = -EINVAL;
1497 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1498 }
1499
1500 /* deassert IB preemption */
1501 WREG32(sdma_gfx_preempt, 0);
1502
1503 /* deassert the preemption condition */
1504 amdgpu_ring_set_preempt_cond_exec(ring, true);
1505 return r;
1506}
1507
1508static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid)
1509{
1510 struct amdgpu_device *adev = ring->adev;
1511 int i, r;
1512
1513 if (amdgpu_sriov_vf(adev))
1514 return -EINVAL;
1515
1516 for (i = 0; i < adev->sdma.num_instances; i++) {
1517 if (ring == &adev->sdma.instance[i].ring)
1518 break;
1519 }
1520
1521 if (i == adev->sdma.num_instances) {
1522 DRM_ERROR("sdma instance not found\n");
1523 return -EINVAL;
1524 }
1525
1526 r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true);
1527 if (r)
1528 return r;
1529
1530 return sdma_v6_0_gfx_resume_instance(adev, i, true);
1531}
1532
1533static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
1534 struct amdgpu_irq_src *source,
1535 unsigned type,
1536 enum amdgpu_interrupt_state state)
1537{
1538 u32 sdma_cntl;
1539
1540 u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
1541
1542 if (!amdgpu_sriov_vf(adev)) {
1543 sdma_cntl = RREG32(reg_offset);
1544 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1545 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1546 WREG32(reg_offset, sdma_cntl);
1547 }
1548
1549 return 0;
1550}
1551
1552static int sdma_v6_0_process_trap_irq(struct amdgpu_device *adev,
1553 struct amdgpu_irq_src *source,
1554 struct amdgpu_iv_entry *entry)
1555{
1556 int instances, queue;
1557 uint32_t mes_queue_id = entry->src_data[0];
1558
1559 DRM_DEBUG("IH: SDMA trap\n");
1560
1561 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1562 struct amdgpu_mes_queue *queue;
1563
1564 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1565
1566 spin_lock(&adev->mes.queue_id_lock);
1567 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1568 if (queue) {
1569 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1570 amdgpu_fence_process(queue->ring);
1571 }
1572 spin_unlock(&adev->mes.queue_id_lock);
1573 return 0;
1574 }
1575
1576 queue = entry->ring_id & 0xf;
1577 instances = (entry->ring_id & 0xf0) >> 4;
1578 if (instances > 1) {
1579 DRM_ERROR("IH: wrong ring_ID detected, as wrong sdma instance\n");
1580 return -EINVAL;
1581 }
1582
1583 switch (entry->client_id) {
1584 case SOC21_IH_CLIENTID_GFX:
1585 switch (queue) {
1586 case 0:
1587 amdgpu_fence_process(&adev->sdma.instance[instances].ring);
1588 break;
1589 default:
1590 break;
1591 }
1592 break;
1593 }
1594 return 0;
1595}
1596
1597static int sdma_v6_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1598 struct amdgpu_irq_src *source,
1599 struct amdgpu_iv_entry *entry)
1600{
1601 return 0;
1602}
1603
1604static int sdma_v6_0_set_clockgating_state(void *handle,
1605 enum amd_clockgating_state state)
1606{
1607 return 0;
1608}
1609
1610static int sdma_v6_0_set_powergating_state(void *handle,
1611 enum amd_powergating_state state)
1612{
1613 return 0;
1614}
1615
1616static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags)
1617{
1618}
1619
1620static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p)
1621{
1622 struct amdgpu_device *adev = ip_block->adev;
1623 int i, j;
1624 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1625 uint32_t instance_offset;
1626
1627 if (!adev->sdma.ip_dump)
1628 return;
1629
1630 drm_printf(p, "num_instances:%d\n", adev->sdma.num_instances);
1631 for (i = 0; i < adev->sdma.num_instances; i++) {
1632 instance_offset = i * reg_count;
1633 drm_printf(p, "\nInstance:%d\n", i);
1634
1635 for (j = 0; j < reg_count; j++)
1636 drm_printf(p, "%-50s \t 0x%08x\n", sdma_reg_list_6_0[j].reg_name,
1637 adev->sdma.ip_dump[instance_offset + j]);
1638 }
1639}
1640
1641static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block)
1642{
1643 struct amdgpu_device *adev = ip_block->adev;
1644 int i, j;
1645 uint32_t instance_offset;
1646 uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0);
1647
1648 if (!adev->sdma.ip_dump)
1649 return;
1650
1651 amdgpu_gfx_off_ctrl(adev, false);
1652 for (i = 0; i < adev->sdma.num_instances; i++) {
1653 instance_offset = i * reg_count;
1654 for (j = 0; j < reg_count; j++)
1655 adev->sdma.ip_dump[instance_offset + j] =
1656 RREG32(sdma_v6_0_get_reg_offset(adev, i,
1657 sdma_reg_list_6_0[j].reg_offset));
1658 }
1659 amdgpu_gfx_off_ctrl(adev, true);
1660}
1661
1662const struct amd_ip_funcs sdma_v6_0_ip_funcs = {
1663 .name = "sdma_v6_0",
1664 .early_init = sdma_v6_0_early_init,
1665 .sw_init = sdma_v6_0_sw_init,
1666 .sw_fini = sdma_v6_0_sw_fini,
1667 .hw_init = sdma_v6_0_hw_init,
1668 .hw_fini = sdma_v6_0_hw_fini,
1669 .suspend = sdma_v6_0_suspend,
1670 .resume = sdma_v6_0_resume,
1671 .is_idle = sdma_v6_0_is_idle,
1672 .wait_for_idle = sdma_v6_0_wait_for_idle,
1673 .soft_reset = sdma_v6_0_soft_reset,
1674 .check_soft_reset = sdma_v6_0_check_soft_reset,
1675 .set_clockgating_state = sdma_v6_0_set_clockgating_state,
1676 .set_powergating_state = sdma_v6_0_set_powergating_state,
1677 .get_clockgating_state = sdma_v6_0_get_clockgating_state,
1678 .dump_ip_state = sdma_v6_0_dump_ip_state,
1679 .print_ip_state = sdma_v6_0_print_ip_state,
1680};
1681
1682static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = {
1683 .type = AMDGPU_RING_TYPE_SDMA,
1684 .align_mask = 0xf,
1685 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1686 .support_64bit_ptrs = true,
1687 .secure_submission_supported = true,
1688 .get_rptr = sdma_v6_0_ring_get_rptr,
1689 .get_wptr = sdma_v6_0_ring_get_wptr,
1690 .set_wptr = sdma_v6_0_ring_set_wptr,
1691 .emit_frame_size =
1692 5 + /* sdma_v6_0_ring_init_cond_exec */
1693 6 + /* sdma_v6_0_ring_emit_hdp_flush */
1694 6 + /* sdma_v6_0_ring_emit_pipeline_sync */
1695 /* sdma_v6_0_ring_emit_vm_flush */
1696 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1697 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1698 10 + 10 + 10, /* sdma_v6_0_ring_emit_fence x3 for user fence, vm fence */
1699 .emit_ib_size = 5 + 7 + 6, /* sdma_v6_0_ring_emit_ib */
1700 .emit_ib = sdma_v6_0_ring_emit_ib,
1701 .emit_mem_sync = sdma_v6_0_ring_emit_mem_sync,
1702 .emit_fence = sdma_v6_0_ring_emit_fence,
1703 .emit_pipeline_sync = sdma_v6_0_ring_emit_pipeline_sync,
1704 .emit_vm_flush = sdma_v6_0_ring_emit_vm_flush,
1705 .emit_hdp_flush = sdma_v6_0_ring_emit_hdp_flush,
1706 .test_ring = sdma_v6_0_ring_test_ring,
1707 .test_ib = sdma_v6_0_ring_test_ib,
1708 .insert_nop = sdma_v6_0_ring_insert_nop,
1709 .pad_ib = sdma_v6_0_ring_pad_ib,
1710 .emit_wreg = sdma_v6_0_ring_emit_wreg,
1711 .emit_reg_wait = sdma_v6_0_ring_emit_reg_wait,
1712 .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait,
1713 .init_cond_exec = sdma_v6_0_ring_init_cond_exec,
1714 .preempt_ib = sdma_v6_0_ring_preempt_ib,
1715 .reset = sdma_v6_0_reset_queue,
1716};
1717
1718static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev)
1719{
1720 int i;
1721
1722 for (i = 0; i < adev->sdma.num_instances; i++) {
1723 adev->sdma.instance[i].ring.funcs = &sdma_v6_0_ring_funcs;
1724 adev->sdma.instance[i].ring.me = i;
1725 }
1726}
1727
1728static const struct amdgpu_irq_src_funcs sdma_v6_0_trap_irq_funcs = {
1729 .set = sdma_v6_0_set_trap_irq_state,
1730 .process = sdma_v6_0_process_trap_irq,
1731};
1732
1733static const struct amdgpu_irq_src_funcs sdma_v6_0_illegal_inst_irq_funcs = {
1734 .process = sdma_v6_0_process_illegal_inst_irq,
1735};
1736
1737static void sdma_v6_0_set_irq_funcs(struct amdgpu_device *adev)
1738{
1739 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1740 adev->sdma.num_instances;
1741 adev->sdma.trap_irq.funcs = &sdma_v6_0_trap_irq_funcs;
1742 adev->sdma.illegal_inst_irq.funcs = &sdma_v6_0_illegal_inst_irq_funcs;
1743}
1744
1745/**
1746 * sdma_v6_0_emit_copy_buffer - copy buffer using the sDMA engine
1747 *
1748 * @ib: indirect buffer to fill with commands
1749 * @src_offset: src GPU address
1750 * @dst_offset: dst GPU address
1751 * @byte_count: number of bytes to xfer
1752 * @copy_flags: copy flags for the buffers
1753 *
1754 * Copy GPU buffers using the DMA engine.
1755 * Used by the amdgpu ttm implementation to move pages if
1756 * registered as the asic copy callback.
1757 */
1758static void sdma_v6_0_emit_copy_buffer(struct amdgpu_ib *ib,
1759 uint64_t src_offset,
1760 uint64_t dst_offset,
1761 uint32_t byte_count,
1762 uint32_t copy_flags)
1763{
1764 ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) |
1765 SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1766 SDMA_PKT_COPY_LINEAR_HEADER_TMZ((copy_flags & AMDGPU_COPY_FLAGS_TMZ) ? 1 : 0);
1767 ib->ptr[ib->length_dw++] = byte_count - 1;
1768 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1769 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1770 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1771 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1772 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1773}
1774
1775/**
1776 * sdma_v6_0_emit_fill_buffer - fill buffer using the sDMA engine
1777 *
1778 * @ib: indirect buffer to fill
1779 * @src_data: value to write to buffer
1780 * @dst_offset: dst GPU address
1781 * @byte_count: number of bytes to xfer
1782 *
1783 * Fill GPU buffers using the DMA engine.
1784 */
1785static void sdma_v6_0_emit_fill_buffer(struct amdgpu_ib *ib,
1786 uint32_t src_data,
1787 uint64_t dst_offset,
1788 uint32_t byte_count)
1789{
1790 ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL);
1791 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1792 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1793 ib->ptr[ib->length_dw++] = src_data;
1794 ib->ptr[ib->length_dw++] = byte_count - 1;
1795}
1796
1797static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
1798 .copy_max_bytes = 0x400000,
1799 .copy_num_dw = 7,
1800 .emit_copy_buffer = sdma_v6_0_emit_copy_buffer,
1801
1802 .fill_max_bytes = 0x400000,
1803 .fill_num_dw = 5,
1804 .emit_fill_buffer = sdma_v6_0_emit_fill_buffer,
1805};
1806
1807static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
1808{
1809 adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
1810 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1811}
1812
1813static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
1814 .copy_pte_num_dw = 7,
1815 .copy_pte = sdma_v6_0_vm_copy_pte,
1816 .write_pte = sdma_v6_0_vm_write_pte,
1817 .set_pte_pde = sdma_v6_0_vm_set_pte_pde,
1818};
1819
1820static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1821{
1822 unsigned i;
1823
1824 adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
1825 for (i = 0; i < adev->sdma.num_instances; i++) {
1826 adev->vm_manager.vm_pte_scheds[i] =
1827 &adev->sdma.instance[i].ring.sched;
1828 }
1829 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1830}
1831
1832const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
1833 .type = AMD_IP_BLOCK_TYPE_SDMA,
1834 .major = 6,
1835 .minor = 0,
1836 .rev = 0,
1837 .funcs = &sdma_v6_0_ip_funcs,
1838};