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1/*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "amdgpu.h"
25#include "amdgpu_jpeg.h"
26#include "amdgpu_pm.h"
27#include "soc15.h"
28#include "soc15d.h"
29#include "jpeg_v2_0.h"
30#include "jpeg_v4_0_3.h"
31
32#include "vcn/vcn_5_0_0_offset.h"
33#include "vcn/vcn_5_0_0_sh_mask.h"
34#include "ivsrcid/vcn/irqsrcs_vcn_4_0.h"
35#include "jpeg_v5_0_0.h"
36
37static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev);
38static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev);
39static int jpeg_v5_0_0_set_powergating_state(void *handle,
40 enum amd_powergating_state state);
41
42/**
43 * jpeg_v5_0_0_early_init - set function pointers
44 *
45 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
46 *
47 * Set ring and irq function pointers
48 */
49static int jpeg_v5_0_0_early_init(struct amdgpu_ip_block *ip_block)
50{
51 struct amdgpu_device *adev = ip_block->adev;
52
53 adev->jpeg.num_jpeg_inst = 1;
54 adev->jpeg.num_jpeg_rings = 1;
55
56 jpeg_v5_0_0_set_dec_ring_funcs(adev);
57 jpeg_v5_0_0_set_irq_funcs(adev);
58
59 return 0;
60}
61
62/**
63 * jpeg_v5_0_0_sw_init - sw init for JPEG block
64 *
65 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
66 *
67 * Load firmware and sw initialization
68 */
69static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block)
70{
71 struct amdgpu_device *adev = ip_block->adev;
72 struct amdgpu_ring *ring;
73 int r;
74
75 /* JPEG TRAP */
76 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
77 VCN_4_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq);
78 if (r)
79 return r;
80
81 r = amdgpu_jpeg_sw_init(adev);
82 if (r)
83 return r;
84
85 r = amdgpu_jpeg_resume(adev);
86 if (r)
87 return r;
88
89 ring = adev->jpeg.inst->ring_dec;
90 ring->use_doorbell = true;
91 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1;
92 ring->vm_hub = AMDGPU_MMHUB0(0);
93
94 sprintf(ring->name, "jpeg_dec");
95 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, 0,
96 AMDGPU_RING_PRIO_DEFAULT, NULL);
97 if (r)
98 return r;
99
100 adev->jpeg.internal.jpeg_pitch[0] = regUVD_JPEG_PITCH_INTERNAL_OFFSET;
101 adev->jpeg.inst->external.jpeg_pitch[0] = SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_PITCH);
102
103 /* TODO: Add queue reset mask when FW fully supports it */
104 adev->jpeg.supported_reset =
105 amdgpu_get_soft_full_reset_mask(&adev->jpeg.inst[0].ring_dec[0]);
106 r = amdgpu_jpeg_sysfs_reset_mask_init(adev);
107 if (r)
108 return r;
109 return 0;
110}
111
112/**
113 * jpeg_v5_0_0_sw_fini - sw fini for JPEG block
114 *
115 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
116 *
117 * JPEG suspend and free up sw allocation
118 */
119static int jpeg_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block)
120{
121 struct amdgpu_device *adev = ip_block->adev;
122 int r;
123
124 r = amdgpu_jpeg_suspend(adev);
125 if (r)
126 return r;
127
128 amdgpu_jpeg_sysfs_reset_mask_fini(adev);
129 r = amdgpu_jpeg_sw_fini(adev);
130
131 return r;
132}
133
134/**
135 * jpeg_v5_0_0_hw_init - start and test JPEG block
136 *
137 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
138 *
139 */
140static int jpeg_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block)
141{
142 struct amdgpu_device *adev = ip_block->adev;
143 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
144 int r;
145
146 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
147 (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
148
149 /* Skip ring test because pause DPG is not implemented. */
150 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG)
151 return 0;
152
153 r = amdgpu_ring_test_helper(ring);
154 if (r)
155 return r;
156
157 return 0;
158}
159
160/**
161 * jpeg_v5_0_0_hw_fini - stop the hardware block
162 *
163 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
164 *
165 * Stop the JPEG block, mark ring as not ready any more
166 */
167static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block)
168{
169 struct amdgpu_device *adev = ip_block->adev;
170
171 cancel_delayed_work_sync(&adev->jpeg.idle_work);
172
173 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE &&
174 RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS))
175 jpeg_v5_0_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
176
177 return 0;
178}
179
180/**
181 * jpeg_v5_0_0_suspend - suspend JPEG block
182 *
183 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
184 *
185 * HW fini and suspend JPEG block
186 */
187static int jpeg_v5_0_0_suspend(struct amdgpu_ip_block *ip_block)
188{
189 int r;
190
191 r = jpeg_v5_0_0_hw_fini(ip_block);
192 if (r)
193 return r;
194
195 r = amdgpu_jpeg_suspend(ip_block->adev);
196
197 return r;
198}
199
200/**
201 * jpeg_v5_0_0_resume - resume JPEG block
202 *
203 * @ip_block: Pointer to the amdgpu_ip_block for this hw instance.
204 *
205 * Resume firmware and hw init JPEG block
206 */
207static int jpeg_v5_0_0_resume(struct amdgpu_ip_block *ip_block)
208{
209 int r;
210
211 r = amdgpu_jpeg_resume(ip_block->adev);
212 if (r)
213 return r;
214
215 r = jpeg_v5_0_0_hw_init(ip_block);
216
217 return r;
218}
219
220static void jpeg_v5_0_0_disable_clock_gating(struct amdgpu_device *adev)
221{
222 uint32_t data = 0;
223
224 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
225
226 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
227 data &= ~(JPEG_CGC_CTRL__JPEG0_DEC_MODE_MASK
228 | JPEG_CGC_CTRL__JPEG_ENC_MODE_MASK);
229 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
230}
231
232static void jpeg_v5_0_0_enable_clock_gating(struct amdgpu_device *adev)
233{
234 uint32_t data = 0;
235
236 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL);
237
238 data |= 1 << JPEG_CGC_CTRL__JPEG0_DEC_MODE__SHIFT;
239 WREG32_SOC15(JPEG, 0, regJPEG_CGC_CTRL, data);
240
241 data = RREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE);
242 data |= (JPEG_CGC_GATE__JPEG0_DEC_MASK
243 |JPEG_CGC_GATE__JPEG_ENC_MASK
244 |JPEG_CGC_GATE__JMCIF_MASK
245 |JPEG_CGC_GATE__JRBBM_MASK);
246 WREG32_SOC15(JPEG, 0, regJPEG_CGC_GATE, data);
247}
248
249static int jpeg_v5_0_0_disable_power_gating(struct amdgpu_device *adev)
250{
251 uint32_t data = 0;
252
253 data = 1 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT;
254 WREG32_SOC15(JPEG, 0, regUVD_IPX_DLDO_CONFIG, data);
255 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0,
256 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
257
258 /* disable anti hang mechanism */
259 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS), 0,
260 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
261
262 return 0;
263}
264
265static int jpeg_v5_0_0_enable_power_gating(struct amdgpu_device *adev)
266{
267 /* enable anti hang mechanism */
268 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JPEG_POWER_STATUS),
269 UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK,
270 ~UVD_JPEG_POWER_STATUS__JPEG_POWER_STATUS_MASK);
271
272 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG) {
273 WREG32(SOC15_REG_OFFSET(JPEG, 0, regUVD_IPX_DLDO_CONFIG),
274 2 << UVD_IPX_DLDO_CONFIG__ONO1_PWR_CONFIG__SHIFT);
275 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS,
276 1 << UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS__SHIFT,
277 UVD_IPX_DLDO_STATUS__ONO1_PWR_STATUS_MASK);
278 }
279
280 return 0;
281}
282
283static void jpeg_engine_5_0_0_dpg_clock_gating_mode(struct amdgpu_device *adev,
284 int inst_idx, uint8_t indirect)
285{
286 uint32_t data = 0;
287
288 // JPEG disable CGC
289 if (adev->cg_flags & AMD_CG_SUPPORT_JPEG_MGCG)
290 data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
291 else
292 data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
293
294 data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
295 data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
296
297 if (indirect) {
298 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
299
300 // Turn on All JPEG clocks
301 data = 0;
302 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
303 } else {
304 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect);
305
306 // Turn on All JPEG clocks
307 data = 0;
308 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect);
309 }
310}
311
312/**
313 * jpeg_v5_0_0_start_dpg_mode - Jpeg start with dpg mode
314 *
315 * @adev: amdgpu_device pointer
316 * @inst_idx: instance number index
317 * @indirect: indirectly write sram
318 *
319 * Start JPEG block with dpg mode
320 */
321static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect)
322{
323 struct amdgpu_ring *ring = adev->jpeg.inst[inst_idx].ring_dec;
324 uint32_t reg_data = 0;
325
326 jpeg_v5_0_0_enable_power_gating(adev);
327
328 // enable dynamic power gating mode
329 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
330 reg_data |= UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
331 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
332
333 if (indirect)
334 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr =
335 (uint32_t *)adev->jpeg.inst[inst_idx].dpg_sram_cpu_addr;
336
337 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect);
338
339 /* MJPEG global tiling registers */
340 if (indirect)
341 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,
342 adev->gfx.config.gb_addr_config, indirect);
343 else
344 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_DEC_GFX10_ADDR_CONFIG,
345 adev->gfx.config.gb_addr_config, 1);
346
347 /* enable System Interrupt for JRBC */
348 if (indirect)
349 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_SYS_INT_EN,
350 JPEG_SYS_INT_EN__DJRBC0_MASK, indirect);
351 else
352 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_SYS_INT_EN,
353 JPEG_SYS_INT_EN__DJRBC0_MASK, 1);
354
355 if (indirect) {
356 /* add nop to workaround PSP size check */
357 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipUVD_NO_OP, 0, indirect);
358
359 amdgpu_jpeg_psp_update_sram(adev, inst_idx, 0);
360 }
361
362 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
363 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
364 VCN_JPEG_DB_CTRL__EN_MASK);
365
366 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_VMID, 0);
367 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
368 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
369 lower_32_bits(ring->gpu_addr));
370 WREG32_SOC15(JPEG, inst_idx, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
371 upper_32_bits(ring->gpu_addr));
372 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_RPTR, 0);
373 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR, 0);
374 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_CNTL, 0x00000002L);
375 WREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
376 ring->wptr = RREG32_SOC15(JPEG, inst_idx, regUVD_JRBC_RB_WPTR);
377
378 return 0;
379}
380
381/**
382 * jpeg_v5_0_0_stop_dpg_mode - Jpeg stop with dpg mode
383 *
384 * @adev: amdgpu_device pointer
385 * @inst_idx: instance number index
386 *
387 * Stop JPEG block with dpg mode
388 */
389static void jpeg_v5_0_0_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
390{
391 uint32_t reg_data = 0;
392
393 reg_data = RREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS);
394 reg_data &= ~UVD_JPEG_POWER_STATUS__JPEG_PG_MODE_MASK;
395 WREG32_SOC15(JPEG, inst_idx, regUVD_JPEG_POWER_STATUS, reg_data);
396}
397
398/**
399 * jpeg_v5_0_0_start - start JPEG block
400 *
401 * @adev: amdgpu_device pointer
402 *
403 * Setup and start the JPEG block
404 */
405static int jpeg_v5_0_0_start(struct amdgpu_device *adev)
406{
407 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec;
408 int r;
409
410 if (adev->pm.dpm_enabled)
411 amdgpu_dpm_enable_jpeg(adev, true);
412
413 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
414 r = jpeg_v5_0_0_start_dpg_mode(adev, 0, adev->jpeg.indirect_sram);
415 return r;
416 }
417
418 /* disable power gating */
419 r = jpeg_v5_0_0_disable_power_gating(adev);
420 if (r)
421 return r;
422
423 /* JPEG disable CGC */
424 jpeg_v5_0_0_disable_clock_gating(adev);
425
426 /* MJPEG global tiling registers */
427 WREG32_SOC15(JPEG, 0, regJPEG_DEC_GFX10_ADDR_CONFIG,
428 adev->gfx.config.gb_addr_config);
429
430 /* enable JMI channel */
431 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL), 0,
432 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
433
434 /* enable System Interrupt for JRBC */
435 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regJPEG_SYS_INT_EN),
436 JPEG_SYS_INT_EN__DJRBC0_MASK,
437 ~JPEG_SYS_INT_EN__DJRBC0_MASK);
438
439 WREG32_SOC15(VCN, 0, regVCN_JPEG_DB_CTRL,
440 ring->doorbell_index << VCN_JPEG_DB_CTRL__OFFSET__SHIFT |
441 VCN_JPEG_DB_CTRL__EN_MASK);
442
443 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_VMID, 0);
444 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, (0x00000001L | 0x00000002L));
445 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
446 lower_32_bits(ring->gpu_addr));
447 WREG32_SOC15(JPEG, 0, regUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
448 upper_32_bits(ring->gpu_addr));
449 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR, 0);
450 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, 0);
451 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_CNTL, 0x00000002L);
452 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_SIZE, ring->ring_size / 4);
453 ring->wptr = RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
454
455 return 0;
456}
457
458/**
459 * jpeg_v5_0_0_stop - stop JPEG block
460 *
461 * @adev: amdgpu_device pointer
462 *
463 * stop the JPEG block
464 */
465static int jpeg_v5_0_0_stop(struct amdgpu_device *adev)
466{
467 int r;
468
469 if (adev->pg_flags & AMD_PG_SUPPORT_JPEG_DPG) {
470 jpeg_v5_0_0_stop_dpg_mode(adev, 0);
471 } else {
472
473 /* reset JMI */
474 WREG32_P(SOC15_REG_OFFSET(JPEG, 0, regUVD_JMI_CNTL),
475 UVD_JMI_CNTL__SOFT_RESET_MASK,
476 ~UVD_JMI_CNTL__SOFT_RESET_MASK);
477
478 jpeg_v5_0_0_enable_clock_gating(adev);
479
480 /* enable power gating */
481 r = jpeg_v5_0_0_enable_power_gating(adev);
482 if (r)
483 return r;
484 }
485
486 if (adev->pm.dpm_enabled)
487 amdgpu_dpm_enable_jpeg(adev, false);
488
489 return 0;
490}
491
492/**
493 * jpeg_v5_0_0_dec_ring_get_rptr - get read pointer
494 *
495 * @ring: amdgpu_ring pointer
496 *
497 * Returns the current hardware read pointer
498 */
499static uint64_t jpeg_v5_0_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
500{
501 struct amdgpu_device *adev = ring->adev;
502
503 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_RPTR);
504}
505
506/**
507 * jpeg_v5_0_0_dec_ring_get_wptr - get write pointer
508 *
509 * @ring: amdgpu_ring pointer
510 *
511 * Returns the current hardware write pointer
512 */
513static uint64_t jpeg_v5_0_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
514{
515 struct amdgpu_device *adev = ring->adev;
516
517 if (ring->use_doorbell)
518 return *ring->wptr_cpu_addr;
519 else
520 return RREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR);
521}
522
523/**
524 * jpeg_v5_0_0_dec_ring_set_wptr - set write pointer
525 *
526 * @ring: amdgpu_ring pointer
527 *
528 * Commits the write pointer to the hardware
529 */
530static void jpeg_v5_0_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
531{
532 struct amdgpu_device *adev = ring->adev;
533
534 if (ring->use_doorbell) {
535 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr);
536 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
537 } else {
538 WREG32_SOC15(JPEG, 0, regUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr));
539 }
540}
541
542static bool jpeg_v5_0_0_is_idle(void *handle)
543{
544 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
545 int ret = 1;
546
547 ret &= (((RREG32_SOC15(JPEG, 0, regUVD_JRBC_STATUS) &
548 UVD_JRBC_STATUS__RB_JOB_DONE_MASK) ==
549 UVD_JRBC_STATUS__RB_JOB_DONE_MASK));
550
551 return ret;
552}
553
554static int jpeg_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
555{
556 struct amdgpu_device *adev = ip_block->adev;
557
558 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS,
559 UVD_JRBC_STATUS__RB_JOB_DONE_MASK,
560 UVD_JRBC_STATUS__RB_JOB_DONE_MASK);
561}
562
563static int jpeg_v5_0_0_set_clockgating_state(void *handle,
564 enum amd_clockgating_state state)
565{
566 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
567 bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
568
569 if (enable) {
570 if (!jpeg_v5_0_0_is_idle(handle))
571 return -EBUSY;
572 jpeg_v5_0_0_enable_clock_gating(adev);
573 } else {
574 jpeg_v5_0_0_disable_clock_gating(adev);
575 }
576
577 return 0;
578}
579
580static int jpeg_v5_0_0_set_powergating_state(void *handle,
581 enum amd_powergating_state state)
582{
583 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
584 int ret;
585
586 if (state == adev->jpeg.cur_state)
587 return 0;
588
589 if (state == AMD_PG_STATE_GATE)
590 ret = jpeg_v5_0_0_stop(adev);
591 else
592 ret = jpeg_v5_0_0_start(adev);
593
594 if (!ret)
595 adev->jpeg.cur_state = state;
596
597 return ret;
598}
599
600static int jpeg_v5_0_0_set_interrupt_state(struct amdgpu_device *adev,
601 struct amdgpu_irq_src *source,
602 unsigned int type,
603 enum amdgpu_interrupt_state state)
604{
605 return 0;
606}
607
608static int jpeg_v5_0_0_process_interrupt(struct amdgpu_device *adev,
609 struct amdgpu_irq_src *source,
610 struct amdgpu_iv_entry *entry)
611{
612 DRM_DEBUG("IH: JPEG TRAP\n");
613
614 switch (entry->src_id) {
615 case VCN_4_0__SRCID__JPEG_DECODE:
616 amdgpu_fence_process(adev->jpeg.inst->ring_dec);
617 break;
618 default:
619 DRM_DEV_ERROR(adev->dev, "Unhandled interrupt: %d %d\n",
620 entry->src_id, entry->src_data[0]);
621 break;
622 }
623
624 return 0;
625}
626
627static const struct amd_ip_funcs jpeg_v5_0_0_ip_funcs = {
628 .name = "jpeg_v5_0_0",
629 .early_init = jpeg_v5_0_0_early_init,
630 .sw_init = jpeg_v5_0_0_sw_init,
631 .sw_fini = jpeg_v5_0_0_sw_fini,
632 .hw_init = jpeg_v5_0_0_hw_init,
633 .hw_fini = jpeg_v5_0_0_hw_fini,
634 .suspend = jpeg_v5_0_0_suspend,
635 .resume = jpeg_v5_0_0_resume,
636 .is_idle = jpeg_v5_0_0_is_idle,
637 .wait_for_idle = jpeg_v5_0_0_wait_for_idle,
638 .set_clockgating_state = jpeg_v5_0_0_set_clockgating_state,
639 .set_powergating_state = jpeg_v5_0_0_set_powergating_state,
640};
641
642static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = {
643 .type = AMDGPU_RING_TYPE_VCN_JPEG,
644 .align_mask = 0xf,
645 .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr,
646 .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr,
647 .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr,
648 .parse_cs = jpeg_v2_dec_ring_parse_cs,
649 .emit_frame_size =
650 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
651 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
652 8 + /* jpeg_v5_0_0_dec_ring_emit_vm_flush */
653 22 + 22 + /* jpeg_v5_0_0_dec_ring_emit_fence x2 vm fence */
654 8 + 16,
655 .emit_ib_size = 22, /* jpeg_v5_0_0_dec_ring_emit_ib */
656 .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib,
657 .emit_fence = jpeg_v4_0_3_dec_ring_emit_fence,
658 .emit_vm_flush = jpeg_v4_0_3_dec_ring_emit_vm_flush,
659 .test_ring = amdgpu_jpeg_dec_ring_test_ring,
660 .test_ib = amdgpu_jpeg_dec_ring_test_ib,
661 .insert_nop = jpeg_v4_0_3_dec_ring_nop,
662 .insert_start = jpeg_v4_0_3_dec_ring_insert_start,
663 .insert_end = jpeg_v4_0_3_dec_ring_insert_end,
664 .pad_ib = amdgpu_ring_generic_pad_ib,
665 .begin_use = amdgpu_jpeg_ring_begin_use,
666 .end_use = amdgpu_jpeg_ring_end_use,
667 .emit_wreg = jpeg_v4_0_3_dec_ring_emit_wreg,
668 .emit_reg_wait = jpeg_v4_0_3_dec_ring_emit_reg_wait,
669 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
670};
671
672static void jpeg_v5_0_0_set_dec_ring_funcs(struct amdgpu_device *adev)
673{
674 adev->jpeg.inst->ring_dec->funcs = &jpeg_v5_0_0_dec_ring_vm_funcs;
675}
676
677static const struct amdgpu_irq_src_funcs jpeg_v5_0_0_irq_funcs = {
678 .set = jpeg_v5_0_0_set_interrupt_state,
679 .process = jpeg_v5_0_0_process_interrupt,
680};
681
682static void jpeg_v5_0_0_set_irq_funcs(struct amdgpu_device *adev)
683{
684 adev->jpeg.inst->irq.num_types = 1;
685 adev->jpeg.inst->irq.funcs = &jpeg_v5_0_0_irq_funcs;
686}
687
688const struct amdgpu_ip_block_version jpeg_v5_0_0_ip_block = {
689 .type = AMD_IP_BLOCK_TYPE_JPEG,
690 .major = 5,
691 .minor = 0,
692 .rev = 0,
693 .funcs = &jpeg_v5_0_0_ip_funcs,
694};