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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/pci.h>
25
26#include <drm/drm_edid.h>
27#include <drm/drm_fourcc.h>
28#include <drm/drm_modeset_helper.h>
29#include <drm/drm_modeset_helper_vtables.h>
30#include <drm/drm_vblank.h>
31
32#include "amdgpu.h"
33#include "amdgpu_pm.h"
34#include "amdgpu_i2c.h"
35#include "atom.h"
36#include "amdgpu_atombios.h"
37#include "atombios_crtc.h"
38#include "atombios_encoders.h"
39#include "amdgpu_pll.h"
40#include "amdgpu_connectors.h"
41#include "amdgpu_display.h"
42
43#include "bif/bif_3_0_d.h"
44#include "bif/bif_3_0_sh_mask.h"
45#include "oss/oss_1_0_d.h"
46#include "oss/oss_1_0_sh_mask.h"
47#include "gca/gfx_6_0_d.h"
48#include "gca/gfx_6_0_sh_mask.h"
49#include "gmc/gmc_6_0_d.h"
50#include "gmc/gmc_6_0_sh_mask.h"
51#include "dce/dce_6_0_d.h"
52#include "dce/dce_6_0_sh_mask.h"
53#include "gca/gfx_7_2_enum.h"
54#include "dce_v6_0.h"
55#include "si_enums.h"
56
57static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
58static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
59
60static const u32 crtc_offsets[6] =
61{
62 SI_CRTC0_REGISTER_OFFSET,
63 SI_CRTC1_REGISTER_OFFSET,
64 SI_CRTC2_REGISTER_OFFSET,
65 SI_CRTC3_REGISTER_OFFSET,
66 SI_CRTC4_REGISTER_OFFSET,
67 SI_CRTC5_REGISTER_OFFSET
68};
69
70static const u32 hpd_offsets[] =
71{
72 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
73 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
74 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
75 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
76 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
77 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
78};
79
80static const uint32_t dig_offsets[] = {
81 SI_CRTC0_REGISTER_OFFSET,
82 SI_CRTC1_REGISTER_OFFSET,
83 SI_CRTC2_REGISTER_OFFSET,
84 SI_CRTC3_REGISTER_OFFSET,
85 SI_CRTC4_REGISTER_OFFSET,
86 SI_CRTC5_REGISTER_OFFSET,
87 (0x13830 - 0x7030) >> 2,
88};
89
90static const struct {
91 uint32_t reg;
92 uint32_t vblank;
93 uint32_t vline;
94 uint32_t hpd;
95
96} interrupt_status_offsets[6] = { {
97 .reg = mmDISP_INTERRUPT_STATUS,
98 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
116}, {
117 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
118 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
119 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
120 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
121}, {
122 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
123 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
124 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
125 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
126} };
127
128static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
129 u32 block_offset, u32 reg)
130{
131 unsigned long flags;
132 u32 r;
133
134 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
135 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
136 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
137 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
138
139 return r;
140}
141
142static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
143 u32 block_offset, u32 reg, u32 v)
144{
145 unsigned long flags;
146
147 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
148 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset,
149 reg | AZALIA_F0_CODEC_ENDPOINT_INDEX__AZALIA_ENDPOINT_REG_WRITE_EN_MASK);
150 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
151 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
152}
153
154static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
155{
156 if (crtc >= adev->mode_info.num_crtc)
157 return 0;
158 else
159 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
160}
161
162static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
163{
164 unsigned i;
165
166 /* Enable pflip interrupts */
167 for (i = 0; i < adev->mode_info.num_crtc; i++)
168 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
169}
170
171static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
172{
173 unsigned i;
174
175 /* Disable pflip interrupts */
176 for (i = 0; i < adev->mode_info.num_crtc; i++)
177 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
178}
179
180/**
181 * dce_v6_0_page_flip - pageflip callback.
182 *
183 * @adev: amdgpu_device pointer
184 * @crtc_id: crtc to cleanup pageflip on
185 * @crtc_base: new address of the crtc (GPU MC address)
186 * @async: asynchronous flip
187 *
188 * Does the actual pageflip (evergreen+).
189 * During vblank we take the crtc lock and wait for the update_pending
190 * bit to go high, when it does, we release the lock, and allow the
191 * double buffered update to take place.
192 * Returns the current update pending status.
193 */
194static void dce_v6_0_page_flip(struct amdgpu_device *adev,
195 int crtc_id, u64 crtc_base, bool async)
196{
197 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
198 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
199
200 /* flip at hsync for async, default is vsync */
201 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
202 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
203 /* update pitch */
204 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
205 fb->pitches[0] / fb->format->cpp[0]);
206 /* update the scanout addresses */
207 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
208 upper_32_bits(crtc_base));
209 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
210 (u32)crtc_base);
211
212 /* post the write */
213 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
214}
215
216static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
217 u32 *vbl, u32 *position)
218{
219 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
220 return -EINVAL;
221 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
222 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
223
224 return 0;
225
226}
227
228/**
229 * dce_v6_0_hpd_sense - hpd sense callback.
230 *
231 * @adev: amdgpu_device pointer
232 * @hpd: hpd (hotplug detect) pin
233 *
234 * Checks if a digital monitor is connected (evergreen+).
235 * Returns true if connected, false if not connected.
236 */
237static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
238 enum amdgpu_hpd_id hpd)
239{
240 bool connected = false;
241
242 if (hpd >= adev->mode_info.num_hpd)
243 return connected;
244
245 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
246 connected = true;
247
248 return connected;
249}
250
251/**
252 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
253 *
254 * @adev: amdgpu_device pointer
255 * @hpd: hpd (hotplug detect) pin
256 *
257 * Set the polarity of the hpd pin (evergreen+).
258 */
259static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
260 enum amdgpu_hpd_id hpd)
261{
262 u32 tmp;
263 bool connected = dce_v6_0_hpd_sense(adev, hpd);
264
265 if (hpd >= adev->mode_info.num_hpd)
266 return;
267
268 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
269 if (connected)
270 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
271 else
272 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
273 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
274}
275
276static void dce_v6_0_hpd_int_ack(struct amdgpu_device *adev,
277 int hpd)
278{
279 u32 tmp;
280
281 if (hpd >= adev->mode_info.num_hpd) {
282 DRM_DEBUG("invalid hdp %d\n", hpd);
283 return;
284 }
285
286 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
287 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
288 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
289}
290
291/**
292 * dce_v6_0_hpd_init - hpd setup callback.
293 *
294 * @adev: amdgpu_device pointer
295 *
296 * Setup the hpd pins used by the card (evergreen+).
297 * Enable the pin, set the polarity, and enable the hpd interrupts.
298 */
299static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
300{
301 struct drm_device *dev = adev_to_drm(adev);
302 struct drm_connector *connector;
303 struct drm_connector_list_iter iter;
304 u32 tmp;
305
306 drm_connector_list_iter_begin(dev, &iter);
307 drm_for_each_connector_iter(connector, &iter) {
308 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
309
310 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
311 continue;
312
313 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
314 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
315 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
316
317 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
318 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
319 /* don't try to enable hpd on eDP or LVDS avoid breaking the
320 * aux dp channel on imac and help (but not completely fix)
321 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
322 * also avoid interrupt storms during dpms.
323 */
324 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
325 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
326 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
327 continue;
328 }
329
330 dce_v6_0_hpd_int_ack(adev, amdgpu_connector->hpd.hpd);
331 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
332 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
333 }
334 drm_connector_list_iter_end(&iter);
335}
336
337/**
338 * dce_v6_0_hpd_fini - hpd tear down callback.
339 *
340 * @adev: amdgpu_device pointer
341 *
342 * Tear down the hpd pins used by the card (evergreen+).
343 * Disable the hpd interrupts.
344 */
345static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
346{
347 struct drm_device *dev = adev_to_drm(adev);
348 struct drm_connector *connector;
349 struct drm_connector_list_iter iter;
350 u32 tmp;
351
352 drm_connector_list_iter_begin(dev, &iter);
353 drm_for_each_connector_iter(connector, &iter) {
354 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
355
356 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
357 continue;
358
359 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
360 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
361 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
362
363 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
364 }
365 drm_connector_list_iter_end(&iter);
366}
367
368static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
369{
370 return mmDC_GPIO_HPD_A;
371}
372
373static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
374 bool render)
375{
376 if (!render)
377 WREG32(mmVGA_RENDER_CONTROL,
378 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
379
380}
381
382static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
383{
384 switch (adev->asic_type) {
385 case CHIP_TAHITI:
386 case CHIP_PITCAIRN:
387 case CHIP_VERDE:
388 return 6;
389 case CHIP_OLAND:
390 return 2;
391 default:
392 return 0;
393 }
394}
395
396void dce_v6_0_disable_dce(struct amdgpu_device *adev)
397{
398 /*Disable VGA render and enabled crtc, if has DCE engine*/
399 if (amdgpu_atombios_has_dce_engine_info(adev)) {
400 u32 tmp;
401 int crtc_enabled, i;
402
403 dce_v6_0_set_vga_render_state(adev, false);
404
405 /*Disable crtc*/
406 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
407 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
408 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
409 if (crtc_enabled) {
410 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
411 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
412 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
413 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
415 }
416 }
417 }
418}
419
420static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
421{
422
423 struct drm_device *dev = encoder->dev;
424 struct amdgpu_device *adev = drm_to_adev(dev);
425 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
426 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
427 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
428 int bpc = 0;
429 u32 tmp = 0;
430 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
431
432 if (connector) {
433 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
434 bpc = amdgpu_connector_get_monitor_bpc(connector);
435 dither = amdgpu_connector->dither;
436 }
437
438 /* LVDS FMT is set up by atom */
439 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
440 return;
441
442 if (bpc == 0)
443 return;
444
445
446 switch (bpc) {
447 case 6:
448 if (dither == AMDGPU_FMT_DITHER_ENABLE)
449 /* XXX sort out optimal dither settings */
450 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
451 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
452 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
453 else
454 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
455 break;
456 case 8:
457 if (dither == AMDGPU_FMT_DITHER_ENABLE)
458 /* XXX sort out optimal dither settings */
459 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
460 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
461 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
462 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
463 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
464 else
465 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
466 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
467 break;
468 case 10:
469 default:
470 /* not needed */
471 break;
472 }
473
474 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
475}
476
477/**
478 * si_get_number_of_dram_channels - get the number of dram channels
479 *
480 * @adev: amdgpu_device pointer
481 *
482 * Look up the number of video ram channels (CIK).
483 * Used for display watermark bandwidth calculations
484 * Returns the number of dram channels
485 */
486static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
487{
488 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
489
490 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
491 case 0:
492 default:
493 return 1;
494 case 1:
495 return 2;
496 case 2:
497 return 4;
498 case 3:
499 return 8;
500 case 4:
501 return 3;
502 case 5:
503 return 6;
504 case 6:
505 return 10;
506 case 7:
507 return 12;
508 case 8:
509 return 16;
510 }
511}
512
513struct dce6_wm_params {
514 u32 dram_channels; /* number of dram channels */
515 u32 yclk; /* bandwidth per dram data pin in kHz */
516 u32 sclk; /* engine clock in kHz */
517 u32 disp_clk; /* display clock in kHz */
518 u32 src_width; /* viewport width */
519 u32 active_time; /* active display time in ns */
520 u32 blank_time; /* blank time in ns */
521 bool interlaced; /* mode is interlaced */
522 fixed20_12 vsc; /* vertical scale ratio */
523 u32 num_heads; /* number of active crtcs */
524 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
525 u32 lb_size; /* line buffer allocated to pipe */
526 u32 vtaps; /* vertical scaler taps */
527};
528
529/**
530 * dce_v6_0_dram_bandwidth - get the dram bandwidth
531 *
532 * @wm: watermark calculation data
533 *
534 * Calculate the raw dram bandwidth (CIK).
535 * Used for display watermark bandwidth calculations
536 * Returns the dram bandwidth in MBytes/s
537 */
538static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
539{
540 /* Calculate raw DRAM Bandwidth */
541 fixed20_12 dram_efficiency; /* 0.7 */
542 fixed20_12 yclk, dram_channels, bandwidth;
543 fixed20_12 a;
544
545 a.full = dfixed_const(1000);
546 yclk.full = dfixed_const(wm->yclk);
547 yclk.full = dfixed_div(yclk, a);
548 dram_channels.full = dfixed_const(wm->dram_channels * 4);
549 a.full = dfixed_const(10);
550 dram_efficiency.full = dfixed_const(7);
551 dram_efficiency.full = dfixed_div(dram_efficiency, a);
552 bandwidth.full = dfixed_mul(dram_channels, yclk);
553 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
554
555 return dfixed_trunc(bandwidth);
556}
557
558/**
559 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
560 *
561 * @wm: watermark calculation data
562 *
563 * Calculate the dram bandwidth used for display (CIK).
564 * Used for display watermark bandwidth calculations
565 * Returns the dram bandwidth for display in MBytes/s
566 */
567static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
568{
569 /* Calculate DRAM Bandwidth and the part allocated to display. */
570 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
571 fixed20_12 yclk, dram_channels, bandwidth;
572 fixed20_12 a;
573
574 a.full = dfixed_const(1000);
575 yclk.full = dfixed_const(wm->yclk);
576 yclk.full = dfixed_div(yclk, a);
577 dram_channels.full = dfixed_const(wm->dram_channels * 4);
578 a.full = dfixed_const(10);
579 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
580 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
581 bandwidth.full = dfixed_mul(dram_channels, yclk);
582 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
583
584 return dfixed_trunc(bandwidth);
585}
586
587/**
588 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
589 *
590 * @wm: watermark calculation data
591 *
592 * Calculate the data return bandwidth used for display (CIK).
593 * Used for display watermark bandwidth calculations
594 * Returns the data return bandwidth in MBytes/s
595 */
596static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
597{
598 /* Calculate the display Data return Bandwidth */
599 fixed20_12 return_efficiency; /* 0.8 */
600 fixed20_12 sclk, bandwidth;
601 fixed20_12 a;
602
603 a.full = dfixed_const(1000);
604 sclk.full = dfixed_const(wm->sclk);
605 sclk.full = dfixed_div(sclk, a);
606 a.full = dfixed_const(10);
607 return_efficiency.full = dfixed_const(8);
608 return_efficiency.full = dfixed_div(return_efficiency, a);
609 a.full = dfixed_const(32);
610 bandwidth.full = dfixed_mul(a, sclk);
611 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
612
613 return dfixed_trunc(bandwidth);
614}
615
616/**
617 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
618 *
619 * @wm: watermark calculation data
620 *
621 * Calculate the dmif bandwidth used for display (CIK).
622 * Used for display watermark bandwidth calculations
623 * Returns the dmif bandwidth in MBytes/s
624 */
625static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
626{
627 /* Calculate the DMIF Request Bandwidth */
628 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
629 fixed20_12 disp_clk, bandwidth;
630 fixed20_12 a, b;
631
632 a.full = dfixed_const(1000);
633 disp_clk.full = dfixed_const(wm->disp_clk);
634 disp_clk.full = dfixed_div(disp_clk, a);
635 a.full = dfixed_const(32);
636 b.full = dfixed_mul(a, disp_clk);
637
638 a.full = dfixed_const(10);
639 disp_clk_request_efficiency.full = dfixed_const(8);
640 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
641
642 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
643
644 return dfixed_trunc(bandwidth);
645}
646
647/**
648 * dce_v6_0_available_bandwidth - get the min available bandwidth
649 *
650 * @wm: watermark calculation data
651 *
652 * Calculate the min available bandwidth used for display (CIK).
653 * Used for display watermark bandwidth calculations
654 * Returns the min available bandwidth in MBytes/s
655 */
656static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
657{
658 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
659 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
660 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
661 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
662
663 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
664}
665
666/**
667 * dce_v6_0_average_bandwidth - get the average available bandwidth
668 *
669 * @wm: watermark calculation data
670 *
671 * Calculate the average available bandwidth used for display (CIK).
672 * Used for display watermark bandwidth calculations
673 * Returns the average available bandwidth in MBytes/s
674 */
675static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
676{
677 /* Calculate the display mode Average Bandwidth
678 * DisplayMode should contain the source and destination dimensions,
679 * timing, etc.
680 */
681 fixed20_12 bpp;
682 fixed20_12 line_time;
683 fixed20_12 src_width;
684 fixed20_12 bandwidth;
685 fixed20_12 a;
686
687 a.full = dfixed_const(1000);
688 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
689 line_time.full = dfixed_div(line_time, a);
690 bpp.full = dfixed_const(wm->bytes_per_pixel);
691 src_width.full = dfixed_const(wm->src_width);
692 bandwidth.full = dfixed_mul(src_width, bpp);
693 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
694 bandwidth.full = dfixed_div(bandwidth, line_time);
695
696 return dfixed_trunc(bandwidth);
697}
698
699/**
700 * dce_v6_0_latency_watermark - get the latency watermark
701 *
702 * @wm: watermark calculation data
703 *
704 * Calculate the latency watermark (CIK).
705 * Used for display watermark bandwidth calculations
706 * Returns the latency watermark in ns
707 */
708static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
709{
710 /* First calculate the latency in ns */
711 u32 mc_latency = 2000; /* 2000 ns. */
712 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
713 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
714 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
715 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
716 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
717 (wm->num_heads * cursor_line_pair_return_time);
718 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
719 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
720 u32 tmp, dmif_size = 12288;
721 fixed20_12 a, b, c;
722
723 if (wm->num_heads == 0)
724 return 0;
725
726 a.full = dfixed_const(2);
727 b.full = dfixed_const(1);
728 if ((wm->vsc.full > a.full) ||
729 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
730 (wm->vtaps >= 5) ||
731 ((wm->vsc.full >= a.full) && wm->interlaced))
732 max_src_lines_per_dst_line = 4;
733 else
734 max_src_lines_per_dst_line = 2;
735
736 a.full = dfixed_const(available_bandwidth);
737 b.full = dfixed_const(wm->num_heads);
738 a.full = dfixed_div(a, b);
739 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
740 tmp = min(dfixed_trunc(a), tmp);
741
742 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
743
744 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
745 b.full = dfixed_const(1000);
746 c.full = dfixed_const(lb_fill_bw);
747 b.full = dfixed_div(c, b);
748 a.full = dfixed_div(a, b);
749 line_fill_time = dfixed_trunc(a);
750
751 if (line_fill_time < wm->active_time)
752 return latency;
753 else
754 return latency + (line_fill_time - wm->active_time);
755
756}
757
758/**
759 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
760 * average and available dram bandwidth
761 *
762 * @wm: watermark calculation data
763 *
764 * Check if the display average bandwidth fits in the display
765 * dram bandwidth (CIK).
766 * Used for display watermark bandwidth calculations
767 * Returns true if the display fits, false if not.
768 */
769static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
770{
771 if (dce_v6_0_average_bandwidth(wm) <=
772 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
773 return true;
774 else
775 return false;
776}
777
778/**
779 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
780 * average and available bandwidth
781 *
782 * @wm: watermark calculation data
783 *
784 * Check if the display average bandwidth fits in the display
785 * available bandwidth (CIK).
786 * Used for display watermark bandwidth calculations
787 * Returns true if the display fits, false if not.
788 */
789static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
790{
791 if (dce_v6_0_average_bandwidth(wm) <=
792 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
793 return true;
794 else
795 return false;
796}
797
798/**
799 * dce_v6_0_check_latency_hiding - check latency hiding
800 *
801 * @wm: watermark calculation data
802 *
803 * Check latency hiding (CIK).
804 * Used for display watermark bandwidth calculations
805 * Returns true if the display fits, false if not.
806 */
807static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
808{
809 u32 lb_partitions = wm->lb_size / wm->src_width;
810 u32 line_time = wm->active_time + wm->blank_time;
811 u32 latency_tolerant_lines;
812 u32 latency_hiding;
813 fixed20_12 a;
814
815 a.full = dfixed_const(1);
816 if (wm->vsc.full > a.full)
817 latency_tolerant_lines = 1;
818 else {
819 if (lb_partitions <= (wm->vtaps + 1))
820 latency_tolerant_lines = 1;
821 else
822 latency_tolerant_lines = 2;
823 }
824
825 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
826
827 if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
828 return true;
829 else
830 return false;
831}
832
833/**
834 * dce_v6_0_program_watermarks - program display watermarks
835 *
836 * @adev: amdgpu_device pointer
837 * @amdgpu_crtc: the selected display controller
838 * @lb_size: line buffer size
839 * @num_heads: number of display controllers in use
840 *
841 * Calculate and program the display watermarks for the
842 * selected display controller (CIK).
843 */
844static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
845 struct amdgpu_crtc *amdgpu_crtc,
846 u32 lb_size, u32 num_heads)
847{
848 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
849 struct dce6_wm_params wm_low, wm_high;
850 u32 dram_channels;
851 u32 active_time;
852 u32 line_time = 0;
853 u32 latency_watermark_a = 0, latency_watermark_b = 0;
854 u32 priority_a_mark = 0, priority_b_mark = 0;
855 u32 priority_a_cnt = PRIORITY_OFF;
856 u32 priority_b_cnt = PRIORITY_OFF;
857 u32 tmp, arb_control3, lb_vblank_lead_lines = 0;
858 fixed20_12 a, b, c;
859
860 if (amdgpu_crtc->base.enabled && num_heads && mode) {
861 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
862 (u32)mode->clock);
863 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
864 (u32)mode->clock);
865 line_time = min_t(u32, line_time, 65535);
866 priority_a_cnt = 0;
867 priority_b_cnt = 0;
868
869 dram_channels = si_get_number_of_dram_channels(adev);
870
871 /* watermark for high clocks */
872 if (adev->pm.dpm_enabled) {
873 wm_high.yclk =
874 amdgpu_dpm_get_mclk(adev, false) * 10;
875 wm_high.sclk =
876 amdgpu_dpm_get_sclk(adev, false) * 10;
877 } else {
878 wm_high.yclk = adev->pm.current_mclk * 10;
879 wm_high.sclk = adev->pm.current_sclk * 10;
880 }
881
882 wm_high.disp_clk = mode->clock;
883 wm_high.src_width = mode->crtc_hdisplay;
884 wm_high.active_time = active_time;
885 wm_high.blank_time = line_time - wm_high.active_time;
886 wm_high.interlaced = false;
887 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
888 wm_high.interlaced = true;
889 wm_high.vsc = amdgpu_crtc->vsc;
890 wm_high.vtaps = 1;
891 if (amdgpu_crtc->rmx_type != RMX_OFF)
892 wm_high.vtaps = 2;
893 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
894 wm_high.lb_size = lb_size;
895 wm_high.dram_channels = dram_channels;
896 wm_high.num_heads = num_heads;
897
898 if (adev->pm.dpm_enabled) {
899 /* watermark for low clocks */
900 wm_low.yclk =
901 amdgpu_dpm_get_mclk(adev, true) * 10;
902 wm_low.sclk =
903 amdgpu_dpm_get_sclk(adev, true) * 10;
904 } else {
905 wm_low.yclk = adev->pm.current_mclk * 10;
906 wm_low.sclk = adev->pm.current_sclk * 10;
907 }
908
909 wm_low.disp_clk = mode->clock;
910 wm_low.src_width = mode->crtc_hdisplay;
911 wm_low.active_time = active_time;
912 wm_low.blank_time = line_time - wm_low.active_time;
913 wm_low.interlaced = false;
914 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
915 wm_low.interlaced = true;
916 wm_low.vsc = amdgpu_crtc->vsc;
917 wm_low.vtaps = 1;
918 if (amdgpu_crtc->rmx_type != RMX_OFF)
919 wm_low.vtaps = 2;
920 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
921 wm_low.lb_size = lb_size;
922 wm_low.dram_channels = dram_channels;
923 wm_low.num_heads = num_heads;
924
925 /* set for high clocks */
926 latency_watermark_a = min_t(u32, dce_v6_0_latency_watermark(&wm_high), 65535);
927 /* set for low clocks */
928 latency_watermark_b = min_t(u32, dce_v6_0_latency_watermark(&wm_low), 65535);
929
930 /* possibly force display priority to high */
931 /* should really do this at mode validation time... */
932 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
933 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
934 !dce_v6_0_check_latency_hiding(&wm_high) ||
935 (adev->mode_info.disp_priority == 2)) {
936 DRM_DEBUG_KMS("force priority to high\n");
937 priority_a_cnt |= PRIORITY_ALWAYS_ON;
938 priority_b_cnt |= PRIORITY_ALWAYS_ON;
939 }
940 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
941 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
942 !dce_v6_0_check_latency_hiding(&wm_low) ||
943 (adev->mode_info.disp_priority == 2)) {
944 DRM_DEBUG_KMS("force priority to high\n");
945 priority_a_cnt |= PRIORITY_ALWAYS_ON;
946 priority_b_cnt |= PRIORITY_ALWAYS_ON;
947 }
948
949 a.full = dfixed_const(1000);
950 b.full = dfixed_const(mode->clock);
951 b.full = dfixed_div(b, a);
952 c.full = dfixed_const(latency_watermark_a);
953 c.full = dfixed_mul(c, b);
954 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
955 c.full = dfixed_div(c, a);
956 a.full = dfixed_const(16);
957 c.full = dfixed_div(c, a);
958 priority_a_mark = dfixed_trunc(c);
959 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
960
961 a.full = dfixed_const(1000);
962 b.full = dfixed_const(mode->clock);
963 b.full = dfixed_div(b, a);
964 c.full = dfixed_const(latency_watermark_b);
965 c.full = dfixed_mul(c, b);
966 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
967 c.full = dfixed_div(c, a);
968 a.full = dfixed_const(16);
969 c.full = dfixed_div(c, a);
970 priority_b_mark = dfixed_trunc(c);
971 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
972
973 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
974 }
975
976 /* select wm A */
977 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
978 tmp = arb_control3;
979 tmp &= ~LATENCY_WATERMARK_MASK(3);
980 tmp |= LATENCY_WATERMARK_MASK(1);
981 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
982 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
983 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
984 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
985 /* select wm B */
986 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
987 tmp &= ~LATENCY_WATERMARK_MASK(3);
988 tmp |= LATENCY_WATERMARK_MASK(2);
989 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
990 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
991 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
992 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
993 /* restore original selection */
994 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
995
996 /* write the priority marks */
997 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
998 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
999
1000 /* save values for DPM */
1001 amdgpu_crtc->line_time = line_time;
1002 amdgpu_crtc->wm_high = latency_watermark_a;
1003
1004 /* Save number of lines the linebuffer leads before the scanout */
1005 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1006}
1007
1008/* watermark setup */
1009static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1010 struct amdgpu_crtc *amdgpu_crtc,
1011 struct drm_display_mode *mode,
1012 struct drm_display_mode *other_mode)
1013{
1014 u32 tmp, buffer_alloc, i;
1015 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
1016 /*
1017 * Line Buffer Setup
1018 * There are 3 line buffers, each one shared by 2 display controllers.
1019 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1020 * the display controllers. The paritioning is done via one of four
1021 * preset allocations specified in bits 21:20:
1022 * 0 - half lb
1023 * 2 - whole lb, other crtc must be disabled
1024 */
1025 /* this can get tricky if we have two large displays on a paired group
1026 * of crtcs. Ideally for multiple large displays we'd assign them to
1027 * non-linked crtcs for maximum line buffer allocation.
1028 */
1029 if (amdgpu_crtc->base.enabled && mode) {
1030 if (other_mode) {
1031 tmp = 0; /* 1/2 */
1032 buffer_alloc = 1;
1033 } else {
1034 tmp = 2; /* whole */
1035 buffer_alloc = 2;
1036 }
1037 } else {
1038 tmp = 0;
1039 buffer_alloc = 0;
1040 }
1041
1042 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1043 DC_LB_MEMORY_CONFIG(tmp));
1044
1045 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1046 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1047 for (i = 0; i < adev->usec_timeout; i++) {
1048 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1049 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1050 break;
1051 udelay(1);
1052 }
1053
1054 if (amdgpu_crtc->base.enabled && mode) {
1055 switch (tmp) {
1056 case 0:
1057 default:
1058 return 4096 * 2;
1059 case 2:
1060 return 8192 * 2;
1061 }
1062 }
1063
1064 /* controller not enabled, so no lb used */
1065 return 0;
1066}
1067
1068
1069/**
1070 * dce_v6_0_bandwidth_update - program display watermarks
1071 *
1072 * @adev: amdgpu_device pointer
1073 *
1074 * Calculate and program the display watermarks and line
1075 * buffer allocation (CIK).
1076 */
1077static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1078{
1079 struct drm_display_mode *mode0 = NULL;
1080 struct drm_display_mode *mode1 = NULL;
1081 u32 num_heads = 0, lb_size;
1082 int i;
1083
1084 if (!adev->mode_info.mode_config_initialized)
1085 return;
1086
1087 amdgpu_display_update_priority(adev);
1088
1089 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1090 if (adev->mode_info.crtcs[i]->base.enabled)
1091 num_heads++;
1092 }
1093 for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1094 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1095 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1096 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1097 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1098 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1099 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1100 }
1101}
1102
1103static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1104{
1105 int i;
1106 u32 tmp;
1107
1108 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1109 tmp = RREG32_AUDIO_ENDPT(adev->mode_info.audio.pin[i].offset,
1110 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1111 if (REG_GET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT,
1112 PORT_CONNECTIVITY))
1113 adev->mode_info.audio.pin[i].connected = false;
1114 else
1115 adev->mode_info.audio.pin[i].connected = true;
1116 }
1117
1118}
1119
1120static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1121{
1122 int i;
1123
1124 dce_v6_0_audio_get_connected_pins(adev);
1125
1126 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1127 if (adev->mode_info.audio.pin[i].connected)
1128 return &adev->mode_info.audio.pin[i];
1129 }
1130 DRM_ERROR("No connected audio pins found!\n");
1131 return NULL;
1132}
1133
1134static void dce_v6_0_audio_select_pin(struct drm_encoder *encoder)
1135{
1136 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
1137 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1138 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1139
1140 if (!dig || !dig->afmt || !dig->afmt->pin)
1141 return;
1142
1143 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset,
1144 REG_SET_FIELD(0, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT,
1145 dig->afmt->pin->id));
1146}
1147
1148static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1149 struct drm_display_mode *mode)
1150{
1151 struct drm_device *dev = encoder->dev;
1152 struct amdgpu_device *adev = drm_to_adev(dev);
1153 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1154 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1155 struct drm_connector *connector;
1156 struct drm_connector_list_iter iter;
1157 struct amdgpu_connector *amdgpu_connector = NULL;
1158 int interlace = 0;
1159 u32 tmp;
1160
1161 drm_connector_list_iter_begin(dev, &iter);
1162 drm_for_each_connector_iter(connector, &iter) {
1163 if (connector->encoder == encoder) {
1164 amdgpu_connector = to_amdgpu_connector(connector);
1165 break;
1166 }
1167 }
1168 drm_connector_list_iter_end(&iter);
1169
1170 if (!amdgpu_connector) {
1171 DRM_ERROR("Couldn't find encoder's connector\n");
1172 return;
1173 }
1174
1175 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1176 interlace = 1;
1177
1178 if (connector->latency_present[interlace]) {
1179 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1180 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1181 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1182 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1183 } else {
1184 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1185 VIDEO_LIPSYNC, 0);
1186 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1187 AUDIO_LIPSYNC, 0);
1188 }
1189 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1190 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1191}
1192
1193static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1194{
1195 struct drm_device *dev = encoder->dev;
1196 struct amdgpu_device *adev = drm_to_adev(dev);
1197 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1198 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1199 struct drm_connector *connector;
1200 struct drm_connector_list_iter iter;
1201 struct amdgpu_connector *amdgpu_connector = NULL;
1202 u8 *sadb = NULL;
1203 int sad_count;
1204 u32 tmp;
1205
1206 drm_connector_list_iter_begin(dev, &iter);
1207 drm_for_each_connector_iter(connector, &iter) {
1208 if (connector->encoder == encoder) {
1209 amdgpu_connector = to_amdgpu_connector(connector);
1210 break;
1211 }
1212 }
1213 drm_connector_list_iter_end(&iter);
1214
1215 if (!amdgpu_connector) {
1216 DRM_ERROR("Couldn't find encoder's connector\n");
1217 return;
1218 }
1219
1220 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector->edid, &sadb);
1221 if (sad_count < 0) {
1222 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1223 sad_count = 0;
1224 }
1225
1226 /* program the speaker allocation */
1227 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1228 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1229 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1230 HDMI_CONNECTION, 0);
1231 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1232 DP_CONNECTION, 0);
1233
1234 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort)
1235 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1236 DP_CONNECTION, 1);
1237 else
1238 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1239 HDMI_CONNECTION, 1);
1240
1241 if (sad_count)
1242 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1243 SPEAKER_ALLOCATION, sadb[0]);
1244 else
1245 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1246 SPEAKER_ALLOCATION, 5); /* stereo */
1247
1248 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1249 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1250
1251 kfree(sadb);
1252}
1253
1254static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1255{
1256 struct drm_device *dev = encoder->dev;
1257 struct amdgpu_device *adev = drm_to_adev(dev);
1258 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1259 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1260 struct drm_connector *connector;
1261 struct drm_connector_list_iter iter;
1262 struct amdgpu_connector *amdgpu_connector = NULL;
1263 struct cea_sad *sads;
1264 int i, sad_count;
1265
1266 static const u16 eld_reg_to_type[][2] = {
1267 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1268 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1269 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1270 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1271 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1272 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1273 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1274 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1275 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1276 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1277 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1278 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1279 };
1280
1281 drm_connector_list_iter_begin(dev, &iter);
1282 drm_for_each_connector_iter(connector, &iter) {
1283 if (connector->encoder == encoder) {
1284 amdgpu_connector = to_amdgpu_connector(connector);
1285 break;
1286 }
1287 }
1288 drm_connector_list_iter_end(&iter);
1289
1290 if (!amdgpu_connector) {
1291 DRM_ERROR("Couldn't find encoder's connector\n");
1292 return;
1293 }
1294
1295 sad_count = drm_edid_to_sad(amdgpu_connector->edid, &sads);
1296 if (sad_count < 0)
1297 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1298 if (sad_count <= 0)
1299 return;
1300
1301 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1302 u32 tmp = 0;
1303 u8 stereo_freqs = 0;
1304 int max_channels = -1;
1305 int j;
1306
1307 for (j = 0; j < sad_count; j++) {
1308 struct cea_sad *sad = &sads[j];
1309
1310 if (sad->format == eld_reg_to_type[i][1]) {
1311 if (sad->channels > max_channels) {
1312 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1313 MAX_CHANNELS, sad->channels);
1314 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1315 DESCRIPTOR_BYTE_2, sad->byte2);
1316 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1317 SUPPORTED_FREQUENCIES, sad->freq);
1318 max_channels = sad->channels;
1319 }
1320
1321 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1322 stereo_freqs |= sad->freq;
1323 else
1324 break;
1325 }
1326 }
1327
1328 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1329 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1330 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1331 }
1332
1333 kfree(sads);
1334
1335}
1336
1337static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1338 struct amdgpu_audio_pin *pin,
1339 bool enable)
1340{
1341 if (!pin)
1342 return;
1343
1344 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1345 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1346}
1347
1348static const u32 pin_offsets[7] =
1349{
1350 (0x1780 - 0x1780),
1351 (0x1786 - 0x1780),
1352 (0x178c - 0x1780),
1353 (0x1792 - 0x1780),
1354 (0x1798 - 0x1780),
1355 (0x179d - 0x1780),
1356 (0x17a4 - 0x1780),
1357};
1358
1359static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1360{
1361 int i;
1362
1363 if (!amdgpu_audio)
1364 return 0;
1365
1366 adev->mode_info.audio.enabled = true;
1367
1368 switch (adev->asic_type) {
1369 case CHIP_TAHITI:
1370 case CHIP_PITCAIRN:
1371 case CHIP_VERDE:
1372 default:
1373 adev->mode_info.audio.num_pins = 6;
1374 break;
1375 case CHIP_OLAND:
1376 adev->mode_info.audio.num_pins = 2;
1377 break;
1378 }
1379
1380 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1381 adev->mode_info.audio.pin[i].channels = -1;
1382 adev->mode_info.audio.pin[i].rate = -1;
1383 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1384 adev->mode_info.audio.pin[i].status_bits = 0;
1385 adev->mode_info.audio.pin[i].category_code = 0;
1386 adev->mode_info.audio.pin[i].connected = false;
1387 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1388 adev->mode_info.audio.pin[i].id = i;
1389 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1390 }
1391
1392 return 0;
1393}
1394
1395static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1396{
1397 int i;
1398
1399 if (!amdgpu_audio)
1400 return;
1401
1402 if (!adev->mode_info.audio.enabled)
1403 return;
1404
1405 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1406 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1407
1408 adev->mode_info.audio.enabled = false;
1409}
1410
1411static void dce_v6_0_audio_set_vbi_packet(struct drm_encoder *encoder)
1412{
1413 struct drm_device *dev = encoder->dev;
1414 struct amdgpu_device *adev = drm_to_adev(dev);
1415 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1416 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1417 u32 tmp;
1418
1419 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1420 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1421 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1);
1422 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1);
1423 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1424}
1425
1426static void dce_v6_0_audio_set_acr(struct drm_encoder *encoder,
1427 uint32_t clock, int bpc)
1428{
1429 struct drm_device *dev = encoder->dev;
1430 struct amdgpu_device *adev = drm_to_adev(dev);
1431 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1432 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1433 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1434 u32 tmp;
1435
1436 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1437 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1438 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE,
1439 bpc > 8 ? 0 : 1);
1440 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1441
1442 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1443 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1444 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1445 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1446 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1447 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1448
1449 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1450 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1451 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1452 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1453 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1454 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1455
1456 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1457 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1458 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1459 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1460 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1461 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1462}
1463
1464static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder,
1465 struct drm_display_mode *mode)
1466{
1467 struct drm_device *dev = encoder->dev;
1468 struct amdgpu_device *adev = drm_to_adev(dev);
1469 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1470 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1471 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1472 struct hdmi_avi_infoframe frame;
1473 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1474 uint8_t *payload = buffer + 3;
1475 uint8_t *header = buffer;
1476 ssize_t err;
1477 u32 tmp;
1478
1479 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1480 if (err < 0) {
1481 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1482 return;
1483 }
1484
1485 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1486 if (err < 0) {
1487 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1488 return;
1489 }
1490
1491 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1492 payload[0x0] | (payload[0x1] << 8) | (payload[0x2] << 16) | (payload[0x3] << 24));
1493 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1494 payload[0x4] | (payload[0x5] << 8) | (payload[0x6] << 16) | (payload[0x7] << 24));
1495 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1496 payload[0x8] | (payload[0x9] << 8) | (payload[0xA] << 16) | (payload[0xB] << 24));
1497 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1498 payload[0xC] | (payload[0xD] << 8) | (header[1] << 24));
1499
1500 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1501 /* anything other than 0 */
1502 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1,
1503 HDMI_AUDIO_INFO_LINE, 2);
1504 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1505}
1506
1507static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1508{
1509 struct drm_device *dev = encoder->dev;
1510 struct amdgpu_device *adev = drm_to_adev(dev);
1511 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1512 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1513 u32 tmp;
1514
1515 /*
1516 * Two dtos: generally use dto0 for hdmi, dto1 for dp.
1517 * Express [24MHz / target pixel clock] as an exact rational
1518 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1519 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1520 */
1521 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1522 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1523 DCCG_AUDIO_DTO0_SOURCE_SEL, amdgpu_crtc->crtc_id);
1524 if (em == ATOM_ENCODER_MODE_HDMI) {
1525 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1526 DCCG_AUDIO_DTO_SEL, 0);
1527 } else if (ENCODER_MODE_IS_DP(em)) {
1528 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE,
1529 DCCG_AUDIO_DTO_SEL, 1);
1530 }
1531 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1532 if (em == ATOM_ENCODER_MODE_HDMI) {
1533 WREG32(mmDCCG_AUDIO_DTO0_PHASE, 24000);
1534 WREG32(mmDCCG_AUDIO_DTO0_MODULE, clock);
1535 } else if (ENCODER_MODE_IS_DP(em)) {
1536 WREG32(mmDCCG_AUDIO_DTO1_PHASE, 24000);
1537 WREG32(mmDCCG_AUDIO_DTO1_MODULE, clock);
1538 }
1539}
1540
1541static void dce_v6_0_audio_set_packet(struct drm_encoder *encoder)
1542{
1543 struct drm_device *dev = encoder->dev;
1544 struct amdgpu_device *adev = drm_to_adev(dev);
1545 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1546 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1547 u32 tmp;
1548
1549 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1550 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1551 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1552
1553 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1554 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1555 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1556
1557 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1558 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1559 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1560
1561 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1562 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1563 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1564 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1565 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1566 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1567 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1568 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1569
1570 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset);
1571 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, 0xff);
1572 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset, tmp);
1573
1574 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1575 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1576 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1577 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1578
1579 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1580 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_RESET_FIFO_WHEN_AUDIO_DIS, 1);
1581 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1582 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1583}
1584
1585static void dce_v6_0_audio_set_mute(struct drm_encoder *encoder, bool mute)
1586{
1587 struct drm_device *dev = encoder->dev;
1588 struct amdgpu_device *adev = drm_to_adev(dev);
1589 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1590 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1591 u32 tmp;
1592
1593 tmp = RREG32(mmHDMI_GC + dig->afmt->offset);
1594 tmp = REG_SET_FIELD(tmp, HDMI_GC, HDMI_GC_AVMUTE, mute ? 1 : 0);
1595 WREG32(mmHDMI_GC + dig->afmt->offset, tmp);
1596}
1597
1598static void dce_v6_0_audio_hdmi_enable(struct drm_encoder *encoder, bool enable)
1599{
1600 struct drm_device *dev = encoder->dev;
1601 struct amdgpu_device *adev = drm_to_adev(dev);
1602 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1603 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1604 u32 tmp;
1605
1606 if (enable) {
1607 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1608 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1609 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1610 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1611 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1612 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1613
1614 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1615 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1616 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1617
1618 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1619 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1620 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1621 } else {
1622 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1623 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 0);
1624 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 0);
1625 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 0);
1626 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 0);
1627 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1628
1629 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1630 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 0);
1631 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1632 }
1633}
1634
1635static void dce_v6_0_audio_dp_enable(struct drm_encoder *encoder, bool enable)
1636{
1637 struct drm_device *dev = encoder->dev;
1638 struct amdgpu_device *adev = drm_to_adev(dev);
1639 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1640 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1641 u32 tmp;
1642
1643 if (enable) {
1644 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1645 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1646 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1647
1648 tmp = RREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset);
1649 tmp = REG_SET_FIELD(tmp, DP_SEC_TIMESTAMP, DP_SEC_TIMESTAMP_MODE, 1);
1650 WREG32(mmDP_SEC_TIMESTAMP + dig->afmt->offset, tmp);
1651
1652 tmp = RREG32(mmDP_SEC_CNTL + dig->afmt->offset);
1653 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1);
1654 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_ATP_ENABLE, 1);
1655 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_AIP_ENABLE, 1);
1656 tmp = REG_SET_FIELD(tmp, DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1);
1657 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, tmp);
1658 } else {
1659 WREG32(mmDP_SEC_CNTL + dig->afmt->offset, 0);
1660 }
1661}
1662
1663static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1664 struct drm_display_mode *mode)
1665{
1666 struct drm_device *dev = encoder->dev;
1667 struct amdgpu_device *adev = drm_to_adev(dev);
1668 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1669 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1670 struct drm_connector *connector;
1671 struct drm_connector_list_iter iter;
1672 struct amdgpu_connector *amdgpu_connector = NULL;
1673 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
1674 int bpc = 8;
1675
1676 if (!dig || !dig->afmt)
1677 return;
1678
1679 drm_connector_list_iter_begin(dev, &iter);
1680 drm_for_each_connector_iter(connector, &iter) {
1681 if (connector->encoder == encoder) {
1682 amdgpu_connector = to_amdgpu_connector(connector);
1683 break;
1684 }
1685 }
1686 drm_connector_list_iter_end(&iter);
1687
1688 if (!amdgpu_connector) {
1689 DRM_ERROR("Couldn't find encoder's connector\n");
1690 return;
1691 }
1692
1693 if (!dig->afmt->enabled)
1694 return;
1695
1696 dig->afmt->pin = dce_v6_0_audio_get_pin(adev);
1697 if (!dig->afmt->pin)
1698 return;
1699
1700 if (encoder->crtc) {
1701 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1702 bpc = amdgpu_crtc->bpc;
1703 }
1704
1705 /* disable audio before setting up hw */
1706 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1707
1708 dce_v6_0_audio_set_mute(encoder, true);
1709 dce_v6_0_audio_write_speaker_allocation(encoder);
1710 dce_v6_0_audio_write_sad_regs(encoder);
1711 dce_v6_0_audio_write_latency_fields(encoder, mode);
1712 if (em == ATOM_ENCODER_MODE_HDMI) {
1713 dce_v6_0_audio_set_dto(encoder, mode->clock);
1714 dce_v6_0_audio_set_vbi_packet(encoder);
1715 dce_v6_0_audio_set_acr(encoder, mode->clock, bpc);
1716 } else if (ENCODER_MODE_IS_DP(em)) {
1717 dce_v6_0_audio_set_dto(encoder, adev->clock.default_dispclk * 10);
1718 }
1719 dce_v6_0_audio_set_packet(encoder);
1720 dce_v6_0_audio_select_pin(encoder);
1721 dce_v6_0_audio_set_avi_infoframe(encoder, mode);
1722 dce_v6_0_audio_set_mute(encoder, false);
1723 if (em == ATOM_ENCODER_MODE_HDMI) {
1724 dce_v6_0_audio_hdmi_enable(encoder, 1);
1725 } else if (ENCODER_MODE_IS_DP(em)) {
1726 dce_v6_0_audio_dp_enable(encoder, 1);
1727 }
1728
1729 /* enable audio after setting up hw */
1730 dce_v6_0_audio_enable(adev, dig->afmt->pin, true);
1731}
1732
1733static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1734{
1735 struct drm_device *dev = encoder->dev;
1736 struct amdgpu_device *adev = drm_to_adev(dev);
1737 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1738 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1739
1740 if (!dig || !dig->afmt)
1741 return;
1742
1743 /* Silent, r600_hdmi_enable will raise WARN for us */
1744 if (enable && dig->afmt->enabled)
1745 return;
1746
1747 if (!enable && !dig->afmt->enabled)
1748 return;
1749
1750 if (!enable && dig->afmt->pin) {
1751 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1752 dig->afmt->pin = NULL;
1753 }
1754
1755 dig->afmt->enabled = enable;
1756
1757 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1758 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1759}
1760
1761static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1762{
1763 int i, j;
1764
1765 for (i = 0; i < adev->mode_info.num_dig; i++)
1766 adev->mode_info.afmt[i] = NULL;
1767
1768 /* DCE6 has audio blocks tied to DIG encoders */
1769 for (i = 0; i < adev->mode_info.num_dig; i++) {
1770 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1771 if (adev->mode_info.afmt[i]) {
1772 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1773 adev->mode_info.afmt[i]->id = i;
1774 } else {
1775 for (j = 0; j < i; j++) {
1776 kfree(adev->mode_info.afmt[j]);
1777 adev->mode_info.afmt[j] = NULL;
1778 }
1779 DRM_ERROR("Out of memory allocating afmt table\n");
1780 return -ENOMEM;
1781 }
1782 }
1783 return 0;
1784}
1785
1786static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1787{
1788 int i;
1789
1790 for (i = 0; i < adev->mode_info.num_dig; i++) {
1791 kfree(adev->mode_info.afmt[i]);
1792 adev->mode_info.afmt[i] = NULL;
1793 }
1794}
1795
1796static const u32 vga_control_regs[6] =
1797{
1798 mmD1VGA_CONTROL,
1799 mmD2VGA_CONTROL,
1800 mmD3VGA_CONTROL,
1801 mmD4VGA_CONTROL,
1802 mmD5VGA_CONTROL,
1803 mmD6VGA_CONTROL,
1804};
1805
1806static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1807{
1808 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1809 struct drm_device *dev = crtc->dev;
1810 struct amdgpu_device *adev = drm_to_adev(dev);
1811 u32 vga_control;
1812
1813 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1814 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1815}
1816
1817static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1818{
1819 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1820 struct drm_device *dev = crtc->dev;
1821 struct amdgpu_device *adev = drm_to_adev(dev);
1822
1823 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1824}
1825
1826static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1827 struct drm_framebuffer *fb,
1828 int x, int y, int atomic)
1829{
1830 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1831 struct drm_device *dev = crtc->dev;
1832 struct amdgpu_device *adev = drm_to_adev(dev);
1833 struct drm_framebuffer *target_fb;
1834 struct drm_gem_object *obj;
1835 struct amdgpu_bo *abo;
1836 uint64_t fb_location, tiling_flags;
1837 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1838 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1839 u32 viewport_w, viewport_h;
1840 int r;
1841 bool bypass_lut = false;
1842
1843 /* no fb bound */
1844 if (!atomic && !crtc->primary->fb) {
1845 DRM_DEBUG_KMS("No FB bound\n");
1846 return 0;
1847 }
1848
1849 if (atomic)
1850 target_fb = fb;
1851 else
1852 target_fb = crtc->primary->fb;
1853
1854 /* If atomic, assume fb object is pinned & idle & fenced and
1855 * just update base pointers
1856 */
1857 obj = target_fb->obj[0];
1858 abo = gem_to_amdgpu_bo(obj);
1859 r = amdgpu_bo_reserve(abo, false);
1860 if (unlikely(r != 0))
1861 return r;
1862
1863 if (!atomic) {
1864 abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1865 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1866 if (unlikely(r != 0)) {
1867 amdgpu_bo_unreserve(abo);
1868 return -EINVAL;
1869 }
1870 }
1871 fb_location = amdgpu_bo_gpu_offset(abo);
1872
1873 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1874 amdgpu_bo_unreserve(abo);
1875
1876 switch (target_fb->format->format) {
1877 case DRM_FORMAT_C8:
1878 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1879 GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1880 break;
1881 case DRM_FORMAT_XRGB4444:
1882 case DRM_FORMAT_ARGB4444:
1883 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1884 GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1885#ifdef __BIG_ENDIAN
1886 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1887#endif
1888 break;
1889 case DRM_FORMAT_XRGB1555:
1890 case DRM_FORMAT_ARGB1555:
1891 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1892 GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1893#ifdef __BIG_ENDIAN
1894 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1895#endif
1896 break;
1897 case DRM_FORMAT_BGRX5551:
1898 case DRM_FORMAT_BGRA5551:
1899 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1900 GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1901#ifdef __BIG_ENDIAN
1902 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1903#endif
1904 break;
1905 case DRM_FORMAT_RGB565:
1906 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1907 GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1908#ifdef __BIG_ENDIAN
1909 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1910#endif
1911 break;
1912 case DRM_FORMAT_XRGB8888:
1913 case DRM_FORMAT_ARGB8888:
1914 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1915 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1916#ifdef __BIG_ENDIAN
1917 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1918#endif
1919 break;
1920 case DRM_FORMAT_XRGB2101010:
1921 case DRM_FORMAT_ARGB2101010:
1922 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1923 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1924#ifdef __BIG_ENDIAN
1925 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1926#endif
1927 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1928 bypass_lut = true;
1929 break;
1930 case DRM_FORMAT_BGRX1010102:
1931 case DRM_FORMAT_BGRA1010102:
1932 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1933 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1934#ifdef __BIG_ENDIAN
1935 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1936#endif
1937 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1938 bypass_lut = true;
1939 break;
1940 case DRM_FORMAT_XBGR8888:
1941 case DRM_FORMAT_ABGR8888:
1942 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1943 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1944 fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) |
1945 GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R));
1946#ifdef __BIG_ENDIAN
1947 fb_swap |= GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1948#endif
1949 break;
1950 default:
1951 DRM_ERROR("Unsupported screen format %p4cc\n",
1952 &target_fb->format->format);
1953 return -EINVAL;
1954 }
1955
1956 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1957 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1958
1959 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1960 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1961 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1962 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1963 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1964
1965 fb_format |= GRPH_NUM_BANKS(num_banks);
1966 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1967 fb_format |= GRPH_TILE_SPLIT(tile_split);
1968 fb_format |= GRPH_BANK_WIDTH(bankw);
1969 fb_format |= GRPH_BANK_HEIGHT(bankh);
1970 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1971 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1972 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1973 }
1974
1975 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1976 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1977
1978 dce_v6_0_vga_enable(crtc, false);
1979
1980 /* Make sure surface address is updated at vertical blank rather than
1981 * horizontal blank
1982 */
1983 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1984
1985 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1986 upper_32_bits(fb_location));
1987 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1988 upper_32_bits(fb_location));
1989 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1990 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1991 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1992 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1993 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1994 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1995
1996 /*
1997 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1998 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1999 * retain the full precision throughout the pipeline.
2000 */
2001 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
2002 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
2003 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
2004
2005 if (bypass_lut)
2006 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2007
2008 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2009 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2010 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2011 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2012 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2013 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2014
2015 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2016 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2017
2018 dce_v6_0_grph_enable(crtc, true);
2019
2020 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2021 target_fb->height);
2022 x &= ~3;
2023 y &= ~1;
2024 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2025 (x << 16) | y);
2026 viewport_w = crtc->mode.hdisplay;
2027 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2028
2029 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2030 (viewport_w << 16) | viewport_h);
2031
2032 /* set pageflip to happen anywhere in vblank interval */
2033 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2034
2035 if (!atomic && fb && fb != crtc->primary->fb) {
2036 abo = gem_to_amdgpu_bo(fb->obj[0]);
2037 r = amdgpu_bo_reserve(abo, true);
2038 if (unlikely(r != 0))
2039 return r;
2040 amdgpu_bo_unpin(abo);
2041 amdgpu_bo_unreserve(abo);
2042 }
2043
2044 /* Bytes per pixel may have changed */
2045 dce_v6_0_bandwidth_update(adev);
2046
2047 return 0;
2048
2049}
2050
2051static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
2052 struct drm_display_mode *mode)
2053{
2054 struct drm_device *dev = crtc->dev;
2055 struct amdgpu_device *adev = drm_to_adev(dev);
2056 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2057
2058 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2059 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
2060 INTERLEAVE_EN);
2061 else
2062 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
2063}
2064
2065static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
2066{
2067
2068 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2069 struct drm_device *dev = crtc->dev;
2070 struct amdgpu_device *adev = drm_to_adev(dev);
2071 u16 *r, *g, *b;
2072 int i;
2073
2074 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2075
2076 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2077 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
2078 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
2079 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
2080 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
2081 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
2082 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
2083 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2084 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
2085 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
2086
2087 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2088
2089 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2090 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2091 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2092
2093 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2094 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2095 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2096
2097 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2098 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2099
2100 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2101 r = crtc->gamma_store;
2102 g = r + crtc->gamma_size;
2103 b = g + crtc->gamma_size;
2104 for (i = 0; i < 256; i++) {
2105 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2106 ((*r++ & 0xffc0) << 14) |
2107 ((*g++ & 0xffc0) << 4) |
2108 (*b++ >> 6));
2109 }
2110
2111 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2112 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
2113 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
2114 ICON_DEGAMMA_MODE(0) |
2115 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
2116 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
2117 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
2118 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
2119 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
2120 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
2121 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
2122 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
2123 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
2124 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
2125 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2126 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
2127
2128
2129}
2130
2131static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
2132{
2133 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2134 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2135
2136 switch (amdgpu_encoder->encoder_id) {
2137 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2138 return dig->linkb ? 1 : 0;
2139 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2140 return dig->linkb ? 3 : 2;
2141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2142 return dig->linkb ? 5 : 4;
2143 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2144 return 6;
2145 default:
2146 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2147 return 0;
2148 }
2149}
2150
2151/**
2152 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
2153 *
2154 * @crtc: drm crtc
2155 *
2156 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2157 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2158 * monitors a dedicated PPLL must be used. If a particular board has
2159 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2160 * as there is no need to program the PLL itself. If we are not able to
2161 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2162 * avoid messing up an existing monitor.
2163 *
2164 *
2165 */
2166static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
2167{
2168 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2169 struct drm_device *dev = crtc->dev;
2170 struct amdgpu_device *adev = drm_to_adev(dev);
2171 u32 pll_in_use;
2172 int pll;
2173
2174 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2175 if (adev->clock.dp_extclk)
2176 /* skip PPLL programming if using ext clock */
2177 return ATOM_PPLL_INVALID;
2178 else
2179 return ATOM_PPLL0;
2180 } else {
2181 /* use the same PPLL for all monitors with the same clock */
2182 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2183 if (pll != ATOM_PPLL_INVALID)
2184 return pll;
2185 }
2186
2187 /* PPLL1, and PPLL2 */
2188 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2189 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2190 return ATOM_PPLL2;
2191 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2192 return ATOM_PPLL1;
2193 DRM_ERROR("unable to allocate a PPLL\n");
2194 return ATOM_PPLL_INVALID;
2195}
2196
2197static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2198{
2199 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2200 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2201 uint32_t cur_lock;
2202
2203 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2204 if (lock)
2205 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2206 else
2207 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
2208 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2209}
2210
2211static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
2212{
2213 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2214 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2215
2216 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2217 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2218 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2219
2220
2221}
2222
2223static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
2224{
2225 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2226 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2227
2228 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2229 upper_32_bits(amdgpu_crtc->cursor_addr));
2230 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2231 lower_32_bits(amdgpu_crtc->cursor_addr));
2232
2233 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
2234 CUR_CONTROL__CURSOR_EN_MASK |
2235 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
2236 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
2237
2238}
2239
2240static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
2241 int x, int y)
2242{
2243 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2244 struct amdgpu_device *adev = drm_to_adev(crtc->dev);
2245 int xorigin = 0, yorigin = 0;
2246
2247 int w = amdgpu_crtc->cursor_width;
2248
2249 amdgpu_crtc->cursor_x = x;
2250 amdgpu_crtc->cursor_y = y;
2251
2252 /* avivo cursor are offset into the total surface */
2253 x += crtc->x;
2254 y += crtc->y;
2255 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2256
2257 if (x < 0) {
2258 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2259 x = 0;
2260 }
2261 if (y < 0) {
2262 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2263 y = 0;
2264 }
2265
2266 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2267 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2268 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2269 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2270
2271 return 0;
2272}
2273
2274static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
2275 int x, int y)
2276{
2277 int ret;
2278
2279 dce_v6_0_lock_cursor(crtc, true);
2280 ret = dce_v6_0_cursor_move_locked(crtc, x, y);
2281 dce_v6_0_lock_cursor(crtc, false);
2282
2283 return ret;
2284}
2285
2286static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
2287 struct drm_file *file_priv,
2288 uint32_t handle,
2289 uint32_t width,
2290 uint32_t height,
2291 int32_t hot_x,
2292 int32_t hot_y)
2293{
2294 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2295 struct drm_gem_object *obj;
2296 struct amdgpu_bo *aobj;
2297 int ret;
2298
2299 if (!handle) {
2300 /* turn off cursor */
2301 dce_v6_0_hide_cursor(crtc);
2302 obj = NULL;
2303 goto unpin;
2304 }
2305
2306 if ((width > amdgpu_crtc->max_cursor_width) ||
2307 (height > amdgpu_crtc->max_cursor_height)) {
2308 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2309 return -EINVAL;
2310 }
2311
2312 obj = drm_gem_object_lookup(file_priv, handle);
2313 if (!obj) {
2314 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2315 return -ENOENT;
2316 }
2317
2318 aobj = gem_to_amdgpu_bo(obj);
2319 ret = amdgpu_bo_reserve(aobj, false);
2320 if (ret != 0) {
2321 drm_gem_object_put(obj);
2322 return ret;
2323 }
2324
2325 aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2326 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2327 amdgpu_bo_unreserve(aobj);
2328 if (ret) {
2329 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2330 drm_gem_object_put(obj);
2331 return ret;
2332 }
2333 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2334
2335 dce_v6_0_lock_cursor(crtc, true);
2336
2337 if (width != amdgpu_crtc->cursor_width ||
2338 height != amdgpu_crtc->cursor_height ||
2339 hot_x != amdgpu_crtc->cursor_hot_x ||
2340 hot_y != amdgpu_crtc->cursor_hot_y) {
2341 int x, y;
2342
2343 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2344 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2345
2346 dce_v6_0_cursor_move_locked(crtc, x, y);
2347
2348 amdgpu_crtc->cursor_width = width;
2349 amdgpu_crtc->cursor_height = height;
2350 amdgpu_crtc->cursor_hot_x = hot_x;
2351 amdgpu_crtc->cursor_hot_y = hot_y;
2352 }
2353
2354 dce_v6_0_show_cursor(crtc);
2355 dce_v6_0_lock_cursor(crtc, false);
2356
2357unpin:
2358 if (amdgpu_crtc->cursor_bo) {
2359 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2360 ret = amdgpu_bo_reserve(aobj, true);
2361 if (likely(ret == 0)) {
2362 amdgpu_bo_unpin(aobj);
2363 amdgpu_bo_unreserve(aobj);
2364 }
2365 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2366 }
2367
2368 amdgpu_crtc->cursor_bo = obj;
2369 return 0;
2370}
2371
2372static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
2373{
2374 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2375
2376 if (amdgpu_crtc->cursor_bo) {
2377 dce_v6_0_lock_cursor(crtc, true);
2378
2379 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2380 amdgpu_crtc->cursor_y);
2381
2382 dce_v6_0_show_cursor(crtc);
2383 dce_v6_0_lock_cursor(crtc, false);
2384 }
2385}
2386
2387static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2388 u16 *blue, uint32_t size,
2389 struct drm_modeset_acquire_ctx *ctx)
2390{
2391 dce_v6_0_crtc_load_lut(crtc);
2392
2393 return 0;
2394}
2395
2396static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2397{
2398 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2399
2400 drm_crtc_cleanup(crtc);
2401 kfree(amdgpu_crtc);
2402}
2403
2404static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2405 .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2406 .cursor_move = dce_v6_0_crtc_cursor_move,
2407 .gamma_set = dce_v6_0_crtc_gamma_set,
2408 .set_config = amdgpu_display_crtc_set_config,
2409 .destroy = dce_v6_0_crtc_destroy,
2410 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2411 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2412 .enable_vblank = amdgpu_enable_vblank_kms,
2413 .disable_vblank = amdgpu_disable_vblank_kms,
2414 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2415};
2416
2417static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2418{
2419 struct drm_device *dev = crtc->dev;
2420 struct amdgpu_device *adev = drm_to_adev(dev);
2421 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2422 unsigned type;
2423
2424 switch (mode) {
2425 case DRM_MODE_DPMS_ON:
2426 amdgpu_crtc->enabled = true;
2427 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2428 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2429 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2430 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2431 amdgpu_crtc->crtc_id);
2432 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2433 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2434 drm_crtc_vblank_on(crtc);
2435 dce_v6_0_crtc_load_lut(crtc);
2436 break;
2437 case DRM_MODE_DPMS_STANDBY:
2438 case DRM_MODE_DPMS_SUSPEND:
2439 case DRM_MODE_DPMS_OFF:
2440 drm_crtc_vblank_off(crtc);
2441 if (amdgpu_crtc->enabled)
2442 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2443 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2444 amdgpu_crtc->enabled = false;
2445 break;
2446 }
2447 /* adjust pm to dpms */
2448 amdgpu_dpm_compute_clocks(adev);
2449}
2450
2451static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2452{
2453 /* disable crtc pair power gating before programming */
2454 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2455 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2456 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2457}
2458
2459static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2460{
2461 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2462 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2463}
2464
2465static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2466{
2467
2468 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2469 struct drm_device *dev = crtc->dev;
2470 struct amdgpu_device *adev = drm_to_adev(dev);
2471 struct amdgpu_atom_ss ss;
2472 int i;
2473
2474 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2475 if (crtc->primary->fb) {
2476 int r;
2477 struct amdgpu_bo *abo;
2478
2479 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2480 r = amdgpu_bo_reserve(abo, true);
2481 if (unlikely(r))
2482 DRM_ERROR("failed to reserve abo before unpin\n");
2483 else {
2484 amdgpu_bo_unpin(abo);
2485 amdgpu_bo_unreserve(abo);
2486 }
2487 }
2488 /* disable the GRPH */
2489 dce_v6_0_grph_enable(crtc, false);
2490
2491 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2492
2493 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2494 if (adev->mode_info.crtcs[i] &&
2495 adev->mode_info.crtcs[i]->enabled &&
2496 i != amdgpu_crtc->crtc_id &&
2497 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2498 /* one other crtc is using this pll don't turn
2499 * off the pll
2500 */
2501 goto done;
2502 }
2503 }
2504
2505 switch (amdgpu_crtc->pll_id) {
2506 case ATOM_PPLL1:
2507 case ATOM_PPLL2:
2508 /* disable the ppll */
2509 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2510 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2511 break;
2512 default:
2513 break;
2514 }
2515done:
2516 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2517 amdgpu_crtc->adjusted_clock = 0;
2518 amdgpu_crtc->encoder = NULL;
2519 amdgpu_crtc->connector = NULL;
2520}
2521
2522static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2523 struct drm_display_mode *mode,
2524 struct drm_display_mode *adjusted_mode,
2525 int x, int y, struct drm_framebuffer *old_fb)
2526{
2527 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2528
2529 if (!amdgpu_crtc->adjusted_clock)
2530 return -EINVAL;
2531
2532 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2533 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2534 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2535 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2536 amdgpu_atombios_crtc_scaler_setup(crtc);
2537 dce_v6_0_cursor_reset(crtc);
2538 /* update the hw version fpr dpm */
2539 amdgpu_crtc->hw_mode = *adjusted_mode;
2540
2541 return 0;
2542}
2543
2544static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2545 const struct drm_display_mode *mode,
2546 struct drm_display_mode *adjusted_mode)
2547{
2548
2549 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2550 struct drm_device *dev = crtc->dev;
2551 struct drm_encoder *encoder;
2552
2553 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2554 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2555 if (encoder->crtc == crtc) {
2556 amdgpu_crtc->encoder = encoder;
2557 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2558 break;
2559 }
2560 }
2561 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2562 amdgpu_crtc->encoder = NULL;
2563 amdgpu_crtc->connector = NULL;
2564 return false;
2565 }
2566 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2567 return false;
2568 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2569 return false;
2570 /* pick pll */
2571 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2572 /* if we can't get a PPLL for a non-DP encoder, fail */
2573 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2574 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2575 return false;
2576
2577 return true;
2578}
2579
2580static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2581 struct drm_framebuffer *old_fb)
2582{
2583 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2584}
2585
2586static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2587 struct drm_framebuffer *fb,
2588 int x, int y, enum mode_set_atomic state)
2589{
2590 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2591}
2592
2593static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2594 .dpms = dce_v6_0_crtc_dpms,
2595 .mode_fixup = dce_v6_0_crtc_mode_fixup,
2596 .mode_set = dce_v6_0_crtc_mode_set,
2597 .mode_set_base = dce_v6_0_crtc_set_base,
2598 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2599 .prepare = dce_v6_0_crtc_prepare,
2600 .commit = dce_v6_0_crtc_commit,
2601 .disable = dce_v6_0_crtc_disable,
2602 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2603};
2604
2605static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2606{
2607 struct amdgpu_crtc *amdgpu_crtc;
2608
2609 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2610 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2611 if (amdgpu_crtc == NULL)
2612 return -ENOMEM;
2613
2614 drm_crtc_init(adev_to_drm(adev), &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2615
2616 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2617 amdgpu_crtc->crtc_id = index;
2618 adev->mode_info.crtcs[index] = amdgpu_crtc;
2619
2620 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2621 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2622 adev_to_drm(adev)->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2623 adev_to_drm(adev)->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2624
2625 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2626
2627 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2628 amdgpu_crtc->adjusted_clock = 0;
2629 amdgpu_crtc->encoder = NULL;
2630 amdgpu_crtc->connector = NULL;
2631 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2632
2633 return 0;
2634}
2635
2636static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block)
2637{
2638 struct amdgpu_device *adev = ip_block->adev;
2639
2640 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2641 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2642
2643 dce_v6_0_set_display_funcs(adev);
2644
2645 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2646
2647 switch (adev->asic_type) {
2648 case CHIP_TAHITI:
2649 case CHIP_PITCAIRN:
2650 case CHIP_VERDE:
2651 adev->mode_info.num_hpd = 6;
2652 adev->mode_info.num_dig = 6;
2653 break;
2654 case CHIP_OLAND:
2655 adev->mode_info.num_hpd = 2;
2656 adev->mode_info.num_dig = 2;
2657 break;
2658 default:
2659 return -EINVAL;
2660 }
2661
2662 dce_v6_0_set_irq_funcs(adev);
2663
2664 return 0;
2665}
2666
2667static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
2668{
2669 int r, i;
2670 bool ret;
2671 struct amdgpu_device *adev = ip_block->adev;
2672
2673 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2674 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2675 if (r)
2676 return r;
2677 }
2678
2679 for (i = 8; i < 20; i += 2) {
2680 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2681 if (r)
2682 return r;
2683 }
2684
2685 /* HPD hotplug */
2686 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2687 if (r)
2688 return r;
2689
2690 adev->mode_info.mode_config_initialized = true;
2691
2692 adev_to_drm(adev)->mode_config.funcs = &amdgpu_mode_funcs;
2693 adev_to_drm(adev)->mode_config.async_page_flip = true;
2694 adev_to_drm(adev)->mode_config.max_width = 16384;
2695 adev_to_drm(adev)->mode_config.max_height = 16384;
2696 adev_to_drm(adev)->mode_config.preferred_depth = 24;
2697 adev_to_drm(adev)->mode_config.prefer_shadow = 1;
2698 adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true;
2699
2700 r = amdgpu_display_modeset_create_props(adev);
2701 if (r)
2702 return r;
2703
2704 adev_to_drm(adev)->mode_config.max_width = 16384;
2705 adev_to_drm(adev)->mode_config.max_height = 16384;
2706
2707 /* allocate crtcs */
2708 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2709 r = dce_v6_0_crtc_init(adev, i);
2710 if (r)
2711 return r;
2712 }
2713
2714 ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2715 if (ret)
2716 amdgpu_display_print_display_setup(adev_to_drm(adev));
2717 else
2718 return -EINVAL;
2719
2720 /* setup afmt */
2721 r = dce_v6_0_afmt_init(adev);
2722 if (r)
2723 return r;
2724
2725 r = dce_v6_0_audio_init(adev);
2726 if (r)
2727 return r;
2728
2729 /* Disable vblank IRQs aggressively for power-saving */
2730 /* XXX: can this be enabled for DC? */
2731 adev_to_drm(adev)->vblank_disable_immediate = true;
2732
2733 r = drm_vblank_init(adev_to_drm(adev), adev->mode_info.num_crtc);
2734 if (r)
2735 return r;
2736
2737 /* Pre-DCE11 */
2738 INIT_DELAYED_WORK(&adev->hotplug_work,
2739 amdgpu_display_hotplug_work_func);
2740
2741 drm_kms_helper_poll_init(adev_to_drm(adev));
2742
2743 return r;
2744}
2745
2746static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
2747{
2748 struct amdgpu_device *adev = ip_block->adev;
2749
2750 drm_edid_free(adev->mode_info.bios_hardcoded_edid);
2751
2752 drm_kms_helper_poll_fini(adev_to_drm(adev));
2753
2754 dce_v6_0_audio_fini(adev);
2755 dce_v6_0_afmt_fini(adev);
2756
2757 drm_mode_config_cleanup(adev_to_drm(adev));
2758 adev->mode_info.mode_config_initialized = false;
2759
2760 return 0;
2761}
2762
2763static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
2764{
2765 int i;
2766 struct amdgpu_device *adev = ip_block->adev;
2767
2768 /* disable vga render */
2769 dce_v6_0_set_vga_render_state(adev, false);
2770 /* init dig PHYs, disp eng pll */
2771 amdgpu_atombios_encoder_init_dig(adev);
2772 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2773
2774 /* initialize hpd */
2775 dce_v6_0_hpd_init(adev);
2776
2777 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2778 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2779 }
2780
2781 dce_v6_0_pageflip_interrupt_init(adev);
2782
2783 return 0;
2784}
2785
2786static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
2787{
2788 int i;
2789 struct amdgpu_device *adev = ip_block->adev;
2790
2791 dce_v6_0_hpd_fini(adev);
2792
2793 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2794 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2795 }
2796
2797 dce_v6_0_pageflip_interrupt_fini(adev);
2798
2799 flush_delayed_work(&adev->hotplug_work);
2800
2801 return 0;
2802}
2803
2804static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block)
2805{
2806 struct amdgpu_device *adev = ip_block->adev;
2807 int r;
2808
2809 r = amdgpu_display_suspend_helper(adev);
2810 if (r)
2811 return r;
2812 adev->mode_info.bl_level =
2813 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2814
2815 return dce_v6_0_hw_fini(ip_block);
2816}
2817
2818static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block)
2819{
2820 struct amdgpu_device *adev = ip_block->adev;
2821 int ret;
2822
2823 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
2824 adev->mode_info.bl_level);
2825
2826 ret = dce_v6_0_hw_init(ip_block);
2827
2828 /* turn on the BL */
2829 if (adev->mode_info.bl_encoder) {
2830 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2831 adev->mode_info.bl_encoder);
2832 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2833 bl_level);
2834 }
2835 if (ret)
2836 return ret;
2837
2838 return amdgpu_display_resume_helper(adev);
2839}
2840
2841static bool dce_v6_0_is_idle(void *handle)
2842{
2843 return true;
2844}
2845
2846static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block)
2847{
2848 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2849 return 0;
2850}
2851
2852static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2853 int crtc,
2854 enum amdgpu_interrupt_state state)
2855{
2856 u32 reg_block, interrupt_mask;
2857
2858 if (crtc >= adev->mode_info.num_crtc) {
2859 DRM_DEBUG("invalid crtc %d\n", crtc);
2860 return;
2861 }
2862
2863 switch (crtc) {
2864 case 0:
2865 reg_block = SI_CRTC0_REGISTER_OFFSET;
2866 break;
2867 case 1:
2868 reg_block = SI_CRTC1_REGISTER_OFFSET;
2869 break;
2870 case 2:
2871 reg_block = SI_CRTC2_REGISTER_OFFSET;
2872 break;
2873 case 3:
2874 reg_block = SI_CRTC3_REGISTER_OFFSET;
2875 break;
2876 case 4:
2877 reg_block = SI_CRTC4_REGISTER_OFFSET;
2878 break;
2879 case 5:
2880 reg_block = SI_CRTC5_REGISTER_OFFSET;
2881 break;
2882 default:
2883 DRM_DEBUG("invalid crtc %d\n", crtc);
2884 return;
2885 }
2886
2887 switch (state) {
2888 case AMDGPU_IRQ_STATE_DISABLE:
2889 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2890 interrupt_mask &= ~VBLANK_INT_MASK;
2891 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2892 break;
2893 case AMDGPU_IRQ_STATE_ENABLE:
2894 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2895 interrupt_mask |= VBLANK_INT_MASK;
2896 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2897 break;
2898 default:
2899 break;
2900 }
2901}
2902
2903static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2904 int crtc,
2905 enum amdgpu_interrupt_state state)
2906{
2907
2908}
2909
2910static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2911 struct amdgpu_irq_src *src,
2912 unsigned type,
2913 enum amdgpu_interrupt_state state)
2914{
2915 u32 dc_hpd_int_cntl;
2916
2917 if (type >= adev->mode_info.num_hpd) {
2918 DRM_DEBUG("invalid hdp %d\n", type);
2919 return 0;
2920 }
2921
2922 switch (state) {
2923 case AMDGPU_IRQ_STATE_DISABLE:
2924 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2925 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2926 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2927 break;
2928 case AMDGPU_IRQ_STATE_ENABLE:
2929 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2930 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2931 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2932 break;
2933 default:
2934 break;
2935 }
2936
2937 return 0;
2938}
2939
2940static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2941 struct amdgpu_irq_src *src,
2942 unsigned type,
2943 enum amdgpu_interrupt_state state)
2944{
2945 switch (type) {
2946 case AMDGPU_CRTC_IRQ_VBLANK1:
2947 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2948 break;
2949 case AMDGPU_CRTC_IRQ_VBLANK2:
2950 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2951 break;
2952 case AMDGPU_CRTC_IRQ_VBLANK3:
2953 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2954 break;
2955 case AMDGPU_CRTC_IRQ_VBLANK4:
2956 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2957 break;
2958 case AMDGPU_CRTC_IRQ_VBLANK5:
2959 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2960 break;
2961 case AMDGPU_CRTC_IRQ_VBLANK6:
2962 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2963 break;
2964 case AMDGPU_CRTC_IRQ_VLINE1:
2965 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2966 break;
2967 case AMDGPU_CRTC_IRQ_VLINE2:
2968 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2969 break;
2970 case AMDGPU_CRTC_IRQ_VLINE3:
2971 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2972 break;
2973 case AMDGPU_CRTC_IRQ_VLINE4:
2974 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2975 break;
2976 case AMDGPU_CRTC_IRQ_VLINE5:
2977 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2978 break;
2979 case AMDGPU_CRTC_IRQ_VLINE6:
2980 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2981 break;
2982 default:
2983 break;
2984 }
2985 return 0;
2986}
2987
2988static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2989 struct amdgpu_irq_src *source,
2990 struct amdgpu_iv_entry *entry)
2991{
2992 unsigned crtc = entry->src_id - 1;
2993 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2994 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
2995 crtc);
2996
2997 switch (entry->src_data[0]) {
2998 case 0: /* vblank */
2999 if (disp_int & interrupt_status_offsets[crtc].vblank)
3000 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
3001 else
3002 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3003
3004 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3005 drm_handle_vblank(adev_to_drm(adev), crtc);
3006 }
3007 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3008 break;
3009 case 1: /* vline */
3010 if (disp_int & interrupt_status_offsets[crtc].vline)
3011 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
3012 else
3013 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3014
3015 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3016 break;
3017 default:
3018 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3019 break;
3020 }
3021
3022 return 0;
3023}
3024
3025static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
3026 struct amdgpu_irq_src *src,
3027 unsigned type,
3028 enum amdgpu_interrupt_state state)
3029{
3030 u32 reg;
3031
3032 if (type >= adev->mode_info.num_crtc) {
3033 DRM_ERROR("invalid pageflip crtc %d\n", type);
3034 return -EINVAL;
3035 }
3036
3037 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3038 if (state == AMDGPU_IRQ_STATE_DISABLE)
3039 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3040 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3041 else
3042 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3043 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3044
3045 return 0;
3046}
3047
3048static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
3049 struct amdgpu_irq_src *source,
3050 struct amdgpu_iv_entry *entry)
3051{
3052 unsigned long flags;
3053 unsigned crtc_id;
3054 struct amdgpu_crtc *amdgpu_crtc;
3055 struct amdgpu_flip_work *works;
3056
3057 crtc_id = (entry->src_id - 8) >> 1;
3058 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3059
3060 if (crtc_id >= adev->mode_info.num_crtc) {
3061 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3062 return -EINVAL;
3063 }
3064
3065 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3066 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3067 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3068 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3069
3070 /* IRQ could occur when in initial stage */
3071 if (amdgpu_crtc == NULL)
3072 return 0;
3073
3074 spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags);
3075 works = amdgpu_crtc->pflip_works;
3076 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3077 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3078 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3079 amdgpu_crtc->pflip_status,
3080 AMDGPU_FLIP_SUBMITTED);
3081 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3082 return 0;
3083 }
3084
3085 /* page flip completed. clean up */
3086 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3087 amdgpu_crtc->pflip_works = NULL;
3088
3089 /* wakeup usersapce */
3090 if (works->event)
3091 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3092
3093 spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
3094
3095 drm_crtc_vblank_put(&amdgpu_crtc->base);
3096 schedule_work(&works->unpin_work);
3097
3098 return 0;
3099}
3100
3101static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
3102 struct amdgpu_irq_src *source,
3103 struct amdgpu_iv_entry *entry)
3104{
3105 uint32_t disp_int, mask;
3106 unsigned hpd;
3107
3108 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3109 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3110 return 0;
3111 }
3112
3113 hpd = entry->src_data[0];
3114 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3115 mask = interrupt_status_offsets[hpd].hpd;
3116
3117 if (disp_int & mask) {
3118 dce_v6_0_hpd_int_ack(adev, hpd);
3119 schedule_delayed_work(&adev->hotplug_work, 0);
3120 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3121 }
3122
3123 return 0;
3124
3125}
3126
3127static int dce_v6_0_set_clockgating_state(void *handle,
3128 enum amd_clockgating_state state)
3129{
3130 return 0;
3131}
3132
3133static int dce_v6_0_set_powergating_state(void *handle,
3134 enum amd_powergating_state state)
3135{
3136 return 0;
3137}
3138
3139static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
3140 .name = "dce_v6_0",
3141 .early_init = dce_v6_0_early_init,
3142 .sw_init = dce_v6_0_sw_init,
3143 .sw_fini = dce_v6_0_sw_fini,
3144 .hw_init = dce_v6_0_hw_init,
3145 .hw_fini = dce_v6_0_hw_fini,
3146 .suspend = dce_v6_0_suspend,
3147 .resume = dce_v6_0_resume,
3148 .is_idle = dce_v6_0_is_idle,
3149 .soft_reset = dce_v6_0_soft_reset,
3150 .set_clockgating_state = dce_v6_0_set_clockgating_state,
3151 .set_powergating_state = dce_v6_0_set_powergating_state,
3152};
3153
3154static void
3155dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
3156 struct drm_display_mode *mode,
3157 struct drm_display_mode *adjusted_mode)
3158{
3159
3160 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3161 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3162
3163 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3164
3165 /* need to call this here rather than in prepare() since we need some crtc info */
3166 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3167
3168 /* set scaler clears this on some chips */
3169 dce_v6_0_set_interleave(encoder->crtc, mode);
3170
3171 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em)) {
3172 dce_v6_0_afmt_enable(encoder, true);
3173 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
3174 }
3175}
3176
3177static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
3178{
3179
3180 struct amdgpu_device *adev = drm_to_adev(encoder->dev);
3181 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3182 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3183
3184 if ((amdgpu_encoder->active_device &
3185 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3186 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3187 ENCODER_OBJECT_ID_NONE)) {
3188 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3189 if (dig) {
3190 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
3191 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3192 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3193 }
3194 }
3195
3196 amdgpu_atombios_scratch_regs_lock(adev, true);
3197
3198 if (connector) {
3199 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3200
3201 /* select the clock/data port if it uses a router */
3202 if (amdgpu_connector->router.cd_valid)
3203 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3204
3205 /* turn eDP panel on for mode set */
3206 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3207 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3208 ATOM_TRANSMITTER_ACTION_POWER_ON);
3209 }
3210
3211 /* this is needed for the pll/ss setup to work correctly in some cases */
3212 amdgpu_atombios_encoder_set_crtc_source(encoder);
3213 /* set up the FMT blocks */
3214 dce_v6_0_program_fmt(encoder);
3215}
3216
3217static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
3218{
3219
3220 struct drm_device *dev = encoder->dev;
3221 struct amdgpu_device *adev = drm_to_adev(dev);
3222
3223 /* need to call this here as we need the crtc set up */
3224 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3225 amdgpu_atombios_scratch_regs_lock(adev, false);
3226}
3227
3228static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
3229{
3230
3231 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3232 struct amdgpu_encoder_atom_dig *dig;
3233 int em = amdgpu_atombios_encoder_get_encoder_mode(encoder);
3234
3235 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3236
3237 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3238 if (em == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(em))
3239 dce_v6_0_afmt_enable(encoder, false);
3240 dig = amdgpu_encoder->enc_priv;
3241 dig->dig_encoder = -1;
3242 }
3243 amdgpu_encoder->active_device = 0;
3244}
3245
3246/* these are handled by the primary encoders */
3247static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
3248{
3249
3250}
3251
3252static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
3253{
3254
3255}
3256
3257static void
3258dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
3259 struct drm_display_mode *mode,
3260 struct drm_display_mode *adjusted_mode)
3261{
3262
3263}
3264
3265static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
3266{
3267
3268}
3269
3270static void
3271dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
3272{
3273
3274}
3275
3276static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
3277 const struct drm_display_mode *mode,
3278 struct drm_display_mode *adjusted_mode)
3279{
3280 return true;
3281}
3282
3283static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
3284 .dpms = dce_v6_0_ext_dpms,
3285 .mode_fixup = dce_v6_0_ext_mode_fixup,
3286 .prepare = dce_v6_0_ext_prepare,
3287 .mode_set = dce_v6_0_ext_mode_set,
3288 .commit = dce_v6_0_ext_commit,
3289 .disable = dce_v6_0_ext_disable,
3290 /* no detect for TMDS/LVDS yet */
3291};
3292
3293static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
3294 .dpms = amdgpu_atombios_encoder_dpms,
3295 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3296 .prepare = dce_v6_0_encoder_prepare,
3297 .mode_set = dce_v6_0_encoder_mode_set,
3298 .commit = dce_v6_0_encoder_commit,
3299 .disable = dce_v6_0_encoder_disable,
3300 .detect = amdgpu_atombios_encoder_dig_detect,
3301};
3302
3303static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
3304 .dpms = amdgpu_atombios_encoder_dpms,
3305 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3306 .prepare = dce_v6_0_encoder_prepare,
3307 .mode_set = dce_v6_0_encoder_mode_set,
3308 .commit = dce_v6_0_encoder_commit,
3309 .detect = amdgpu_atombios_encoder_dac_detect,
3310};
3311
3312static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
3313{
3314 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3315 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3316 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3317 kfree(amdgpu_encoder->enc_priv);
3318 drm_encoder_cleanup(encoder);
3319 kfree(amdgpu_encoder);
3320}
3321
3322static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
3323 .destroy = dce_v6_0_encoder_destroy,
3324};
3325
3326static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
3327 uint32_t encoder_enum,
3328 uint32_t supported_device,
3329 u16 caps)
3330{
3331 struct drm_device *dev = adev_to_drm(adev);
3332 struct drm_encoder *encoder;
3333 struct amdgpu_encoder *amdgpu_encoder;
3334
3335 /* see if we already added it */
3336 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3337 amdgpu_encoder = to_amdgpu_encoder(encoder);
3338 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3339 amdgpu_encoder->devices |= supported_device;
3340 return;
3341 }
3342
3343 }
3344
3345 /* add a new one */
3346 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3347 if (!amdgpu_encoder)
3348 return;
3349
3350 encoder = &amdgpu_encoder->base;
3351 switch (adev->mode_info.num_crtc) {
3352 case 1:
3353 encoder->possible_crtcs = 0x1;
3354 break;
3355 case 2:
3356 default:
3357 encoder->possible_crtcs = 0x3;
3358 break;
3359 case 4:
3360 encoder->possible_crtcs = 0xf;
3361 break;
3362 case 6:
3363 encoder->possible_crtcs = 0x3f;
3364 break;
3365 }
3366
3367 amdgpu_encoder->enc_priv = NULL;
3368 amdgpu_encoder->encoder_enum = encoder_enum;
3369 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3370 amdgpu_encoder->devices = supported_device;
3371 amdgpu_encoder->rmx_type = RMX_OFF;
3372 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3373 amdgpu_encoder->is_ext_encoder = false;
3374 amdgpu_encoder->caps = caps;
3375
3376 switch (amdgpu_encoder->encoder_id) {
3377 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3378 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3379 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3380 DRM_MODE_ENCODER_DAC, NULL);
3381 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
3382 break;
3383 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3384 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3385 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3386 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3387 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3388 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3389 amdgpu_encoder->rmx_type = RMX_FULL;
3390 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3391 DRM_MODE_ENCODER_LVDS, NULL);
3392 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3393 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3394 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3395 DRM_MODE_ENCODER_DAC, NULL);
3396 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3397 } else {
3398 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3399 DRM_MODE_ENCODER_TMDS, NULL);
3400 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3401 }
3402 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
3403 break;
3404 case ENCODER_OBJECT_ID_SI170B:
3405 case ENCODER_OBJECT_ID_CH7303:
3406 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3407 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3408 case ENCODER_OBJECT_ID_TITFP513:
3409 case ENCODER_OBJECT_ID_VT1623:
3410 case ENCODER_OBJECT_ID_HDMI_SI1930:
3411 case ENCODER_OBJECT_ID_TRAVIS:
3412 case ENCODER_OBJECT_ID_NUTMEG:
3413 /* these are handled by the primary encoders */
3414 amdgpu_encoder->is_ext_encoder = true;
3415 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3416 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3417 DRM_MODE_ENCODER_LVDS, NULL);
3418 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3419 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3420 DRM_MODE_ENCODER_DAC, NULL);
3421 else
3422 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3423 DRM_MODE_ENCODER_TMDS, NULL);
3424 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3425 break;
3426 }
3427}
3428
3429static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3430 .bandwidth_update = &dce_v6_0_bandwidth_update,
3431 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3432 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3433 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3434 .hpd_sense = &dce_v6_0_hpd_sense,
3435 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3436 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3437 .page_flip = &dce_v6_0_page_flip,
3438 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3439 .add_encoder = &dce_v6_0_encoder_add,
3440 .add_connector = &amdgpu_connector_add,
3441};
3442
3443static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3444{
3445 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3446}
3447
3448static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3449 .set = dce_v6_0_set_crtc_interrupt_state,
3450 .process = dce_v6_0_crtc_irq,
3451};
3452
3453static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3454 .set = dce_v6_0_set_pageflip_interrupt_state,
3455 .process = dce_v6_0_pageflip_irq,
3456};
3457
3458static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3459 .set = dce_v6_0_set_hpd_interrupt_state,
3460 .process = dce_v6_0_hpd_irq,
3461};
3462
3463static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3464{
3465 if (adev->mode_info.num_crtc > 0)
3466 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3467 else
3468 adev->crtc_irq.num_types = 0;
3469 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3470
3471 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3472 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3473
3474 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3475 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3476}
3477
3478const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3479{
3480 .type = AMD_IP_BLOCK_TYPE_DCE,
3481 .major = 6,
3482 .minor = 0,
3483 .rev = 0,
3484 .funcs = &dce_v6_0_ip_funcs,
3485};
3486
3487const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3488{
3489 .type = AMD_IP_BLOCK_TYPE_DCE,
3490 .major = 6,
3491 .minor = 4,
3492 .rev = 0,
3493 .funcs = &dce_v6_0_ip_funcs,
3494};
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "drmP.h"
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "atom.h"
28#include "amdgpu_atombios.h"
29#include "atombios_crtc.h"
30#include "atombios_encoders.h"
31#include "amdgpu_pll.h"
32#include "amdgpu_connectors.h"
33
34#include "bif/bif_3_0_d.h"
35#include "bif/bif_3_0_sh_mask.h"
36#include "oss/oss_1_0_d.h"
37#include "oss/oss_1_0_sh_mask.h"
38#include "gca/gfx_6_0_d.h"
39#include "gca/gfx_6_0_sh_mask.h"
40#include "gmc/gmc_6_0_d.h"
41#include "gmc/gmc_6_0_sh_mask.h"
42#include "dce/dce_6_0_d.h"
43#include "dce/dce_6_0_sh_mask.h"
44#include "gca/gfx_7_2_enum.h"
45#include "si_enums.h"
46
47static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev);
48static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev);
49
50static const u32 crtc_offsets[6] =
51{
52 SI_CRTC0_REGISTER_OFFSET,
53 SI_CRTC1_REGISTER_OFFSET,
54 SI_CRTC2_REGISTER_OFFSET,
55 SI_CRTC3_REGISTER_OFFSET,
56 SI_CRTC4_REGISTER_OFFSET,
57 SI_CRTC5_REGISTER_OFFSET
58};
59
60static const u32 hpd_offsets[] =
61{
62 mmDC_HPD1_INT_STATUS - mmDC_HPD1_INT_STATUS,
63 mmDC_HPD2_INT_STATUS - mmDC_HPD1_INT_STATUS,
64 mmDC_HPD3_INT_STATUS - mmDC_HPD1_INT_STATUS,
65 mmDC_HPD4_INT_STATUS - mmDC_HPD1_INT_STATUS,
66 mmDC_HPD5_INT_STATUS - mmDC_HPD1_INT_STATUS,
67 mmDC_HPD6_INT_STATUS - mmDC_HPD1_INT_STATUS,
68};
69
70static const uint32_t dig_offsets[] = {
71 SI_CRTC0_REGISTER_OFFSET,
72 SI_CRTC1_REGISTER_OFFSET,
73 SI_CRTC2_REGISTER_OFFSET,
74 SI_CRTC3_REGISTER_OFFSET,
75 SI_CRTC4_REGISTER_OFFSET,
76 SI_CRTC5_REGISTER_OFFSET,
77 (0x13830 - 0x7030) >> 2,
78};
79
80static const struct {
81 uint32_t reg;
82 uint32_t vblank;
83 uint32_t vline;
84 uint32_t hpd;
85
86} interrupt_status_offsets[6] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91}, {
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
116} };
117
118static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
119 u32 block_offset, u32 reg)
120{
121 DRM_INFO("xxxx: dce_v6_0_audio_endpt_rreg ----no impl!!!!\n");
122 return 0;
123}
124
125static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
126 u32 block_offset, u32 reg, u32 v)
127{
128 DRM_INFO("xxxx: dce_v6_0_audio_endpt_wreg ----no impl!!!!\n");
129}
130
131static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
132{
133 if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
134 return true;
135 else
136 return false;
137}
138
139static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
140{
141 u32 pos1, pos2;
142
143 pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
144 pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
145
146 if (pos1 != pos2)
147 return true;
148 else
149 return false;
150}
151
152/**
153 * dce_v6_0_wait_for_vblank - vblank wait asic callback.
154 *
155 * @crtc: crtc to wait for vblank on
156 *
157 * Wait for vblank on the requested crtc (evergreen+).
158 */
159static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
160{
161 unsigned i = 100;
162
163 if (crtc >= adev->mode_info.num_crtc)
164 return;
165
166 if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
167 return;
168
169 /* depending on when we hit vblank, we may be close to active; if so,
170 * wait for another frame.
171 */
172 while (dce_v6_0_is_in_vblank(adev, crtc)) {
173 if (i++ == 100) {
174 i = 0;
175 if (!dce_v6_0_is_counter_moving(adev, crtc))
176 break;
177 }
178 }
179
180 while (!dce_v6_0_is_in_vblank(adev, crtc)) {
181 if (i++ == 100) {
182 i = 0;
183 if (!dce_v6_0_is_counter_moving(adev, crtc))
184 break;
185 }
186 }
187}
188
189static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
190{
191 if (crtc >= adev->mode_info.num_crtc)
192 return 0;
193 else
194 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
195}
196
197static void dce_v6_0_pageflip_interrupt_init(struct amdgpu_device *adev)
198{
199 unsigned i;
200
201 /* Enable pflip interrupts */
202 for (i = 0; i < adev->mode_info.num_crtc; i++)
203 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
204}
205
206static void dce_v6_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
207{
208 unsigned i;
209
210 /* Disable pflip interrupts */
211 for (i = 0; i < adev->mode_info.num_crtc; i++)
212 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
213}
214
215/**
216 * dce_v6_0_page_flip - pageflip callback.
217 *
218 * @adev: amdgpu_device pointer
219 * @crtc_id: crtc to cleanup pageflip on
220 * @crtc_base: new address of the crtc (GPU MC address)
221 *
222 * Does the actual pageflip (evergreen+).
223 * During vblank we take the crtc lock and wait for the update_pending
224 * bit to go high, when it does, we release the lock, and allow the
225 * double buffered update to take place.
226 * Returns the current update pending status.
227 */
228static void dce_v6_0_page_flip(struct amdgpu_device *adev,
229 int crtc_id, u64 crtc_base, bool async)
230{
231 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
232
233 /* flip at hsync for async, default is vsync */
234 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ?
235 GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0);
236 /* update the scanout addresses */
237 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
238 upper_32_bits(crtc_base));
239 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
240 (u32)crtc_base);
241
242 /* post the write */
243 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
244}
245
246static int dce_v6_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
247 u32 *vbl, u32 *position)
248{
249 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
250 return -EINVAL;
251 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
252 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
253
254 return 0;
255
256}
257
258/**
259 * dce_v6_0_hpd_sense - hpd sense callback.
260 *
261 * @adev: amdgpu_device pointer
262 * @hpd: hpd (hotplug detect) pin
263 *
264 * Checks if a digital monitor is connected (evergreen+).
265 * Returns true if connected, false if not connected.
266 */
267static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
268 enum amdgpu_hpd_id hpd)
269{
270 bool connected = false;
271
272 if (hpd >= adev->mode_info.num_hpd)
273 return connected;
274
275 if (RREG32(mmDC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPD1_INT_STATUS__DC_HPD1_SENSE_MASK)
276 connected = true;
277
278 return connected;
279}
280
281/**
282 * dce_v6_0_hpd_set_polarity - hpd set polarity callback.
283 *
284 * @adev: amdgpu_device pointer
285 * @hpd: hpd (hotplug detect) pin
286 *
287 * Set the polarity of the hpd pin (evergreen+).
288 */
289static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
290 enum amdgpu_hpd_id hpd)
291{
292 u32 tmp;
293 bool connected = dce_v6_0_hpd_sense(adev, hpd);
294
295 if (hpd >= adev->mode_info.num_hpd)
296 return;
297
298 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
299 if (connected)
300 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
301 else
302 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_POLARITY_MASK;
303 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
304}
305
306/**
307 * dce_v6_0_hpd_init - hpd setup callback.
308 *
309 * @adev: amdgpu_device pointer
310 *
311 * Setup the hpd pins used by the card (evergreen+).
312 * Enable the pin, set the polarity, and enable the hpd interrupts.
313 */
314static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
315{
316 struct drm_device *dev = adev->ddev;
317 struct drm_connector *connector;
318 u32 tmp;
319
320 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
321 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
322
323 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
324 continue;
325
326 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
327 tmp |= DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
328 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
329
330 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
331 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
332 /* don't try to enable hpd on eDP or LVDS avoid breaking the
333 * aux dp channel on imac and help (but not completely fix)
334 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
335 * also avoid interrupt storms during dpms.
336 */
337 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
338 tmp &= ~DC_HPD1_INT_CONTROL__DC_HPD1_INT_EN_MASK;
339 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
340 continue;
341 }
342
343 dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
344 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
345 }
346
347}
348
349/**
350 * dce_v6_0_hpd_fini - hpd tear down callback.
351 *
352 * @adev: amdgpu_device pointer
353 *
354 * Tear down the hpd pins used by the card (evergreen+).
355 * Disable the hpd interrupts.
356 */
357static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
358{
359 struct drm_device *dev = adev->ddev;
360 struct drm_connector *connector;
361 u32 tmp;
362
363 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
364 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
365
366 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
367 continue;
368
369 tmp = RREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
370 tmp &= ~DC_HPD1_CONTROL__DC_HPD1_EN_MASK;
371 WREG32(mmDC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
372
373 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
374 }
375}
376
377static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
378{
379 return mmDC_GPIO_HPD_A;
380}
381
382static u32 evergreen_get_vblank_counter(struct amdgpu_device* adev, int crtc)
383{
384 if (crtc >= adev->mode_info.num_crtc)
385 return 0;
386 else
387 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
388}
389
390static void dce_v6_0_stop_mc_access(struct amdgpu_device *adev,
391 struct amdgpu_mode_mc_save *save)
392{
393 u32 crtc_enabled, tmp, frame_count;
394 int i, j;
395
396 save->vga_render_control = RREG32(mmVGA_RENDER_CONTROL);
397 save->vga_hdp_control = RREG32(mmVGA_HDP_CONTROL);
398
399 /* disable VGA render */
400 WREG32(mmVGA_RENDER_CONTROL, 0);
401
402 /* blank the display controllers */
403 for (i = 0; i < adev->mode_info.num_crtc; i++) {
404 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK;
405 if (crtc_enabled) {
406 save->crtc_enabled[i] = true;
407 tmp = RREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i]);
408
409 if (!(tmp & CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK)) {
410 dce_v6_0_vblank_wait(adev, i);
411 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
412 tmp |= CRTC_BLANK_CONTROL__CRTC_BLANK_DATA_EN_MASK;
413 WREG32(mmCRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
414 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
415 }
416 /* wait for the next frame */
417 frame_count = evergreen_get_vblank_counter(adev, i);
418 for (j = 0; j < adev->usec_timeout; j++) {
419 if (evergreen_get_vblank_counter(adev, i) != frame_count)
420 break;
421 udelay(1);
422 }
423
424 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
425 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
426 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
427 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
428 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
429 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
430 save->crtc_enabled[i] = false;
431 /* ***** */
432 } else {
433 save->crtc_enabled[i] = false;
434 }
435 }
436}
437
438static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
439 struct amdgpu_mode_mc_save *save)
440{
441 u32 tmp;
442 int i, j;
443
444 /* update crtc base addresses */
445 for (i = 0; i < adev->mode_info.num_crtc; i++) {
446 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
447 upper_32_bits(adev->mc.vram_start));
448 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
449 upper_32_bits(adev->mc.vram_start));
450 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
451 (u32)adev->mc.vram_start);
452 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
453 (u32)adev->mc.vram_start);
454 }
455
456 WREG32(mmVGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(adev->mc.vram_start));
457 WREG32(mmVGA_MEMORY_BASE_ADDRESS, (u32)adev->mc.vram_start);
458
459 /* unlock regs and wait for update */
460 for (i = 0; i < adev->mode_info.num_crtc; i++) {
461 if (save->crtc_enabled[i]) {
462 tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
463 if ((tmp & 0x7) != 0) {
464 tmp &= ~0x7;
465 WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
466 }
467 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
468 if (tmp & GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK) {
469 tmp &= ~GRPH_UPDATE__GRPH_UPDATE_LOCK_MASK;
470 WREG32(mmGRPH_UPDATE + crtc_offsets[i], tmp);
471 }
472 tmp = RREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i]);
473 if (tmp & 1) {
474 tmp &= ~1;
475 WREG32(mmMASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
476 }
477 for (j = 0; j < adev->usec_timeout; j++) {
478 tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
479 if ((tmp & GRPH_UPDATE__GRPH_SURFACE_UPDATE_PENDING_MASK) == 0)
480 break;
481 udelay(1);
482 }
483 }
484 }
485
486 /* Unlock vga access */
487 WREG32(mmVGA_HDP_CONTROL, save->vga_hdp_control);
488 mdelay(1);
489 WREG32(mmVGA_RENDER_CONTROL, save->vga_render_control);
490
491}
492
493static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
494 bool render)
495{
496 if (!render)
497 WREG32(mmVGA_RENDER_CONTROL,
498 RREG32(mmVGA_RENDER_CONTROL) & VGA_VSTATUS_CNTL);
499
500}
501
502static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
503{
504 int num_crtc = 0;
505
506 switch (adev->asic_type) {
507 case CHIP_TAHITI:
508 case CHIP_PITCAIRN:
509 case CHIP_VERDE:
510 num_crtc = 6;
511 break;
512 case CHIP_OLAND:
513 num_crtc = 2;
514 break;
515 default:
516 num_crtc = 0;
517 }
518 return num_crtc;
519}
520
521void dce_v6_0_disable_dce(struct amdgpu_device *adev)
522{
523 /*Disable VGA render and enabled crtc, if has DCE engine*/
524 if (amdgpu_atombios_has_dce_engine_info(adev)) {
525 u32 tmp;
526 int crtc_enabled, i;
527
528 dce_v6_0_set_vga_render_state(adev, false);
529
530 /*Disable crtc*/
531 for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
532 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) &
533 CRTC_CONTROL__CRTC_MASTER_EN_MASK;
534 if (crtc_enabled) {
535 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
536 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
537 tmp &= ~CRTC_CONTROL__CRTC_MASTER_EN_MASK;
538 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
539 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
540 }
541 }
542 }
543}
544
545static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
546{
547
548 struct drm_device *dev = encoder->dev;
549 struct amdgpu_device *adev = dev->dev_private;
550 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
551 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
552 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
553 int bpc = 0;
554 u32 tmp = 0;
555 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
556
557 if (connector) {
558 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
559 bpc = amdgpu_connector_get_monitor_bpc(connector);
560 dither = amdgpu_connector->dither;
561 }
562
563 /* LVDS FMT is set up by atom */
564 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
565 return;
566
567 if (bpc == 0)
568 return;
569
570
571 switch (bpc) {
572 case 6:
573 if (dither == AMDGPU_FMT_DITHER_ENABLE)
574 /* XXX sort out optimal dither settings */
575 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
576 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
577 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK);
578 else
579 tmp |= FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK;
580 break;
581 case 8:
582 if (dither == AMDGPU_FMT_DITHER_ENABLE)
583 /* XXX sort out optimal dither settings */
584 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_FRAME_RANDOM_ENABLE_MASK |
585 FMT_BIT_DEPTH_CONTROL__FMT_HIGHPASS_RANDOM_ENABLE_MASK |
586 FMT_BIT_DEPTH_CONTROL__FMT_RGB_RANDOM_ENABLE_MASK |
587 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_EN_MASK |
588 FMT_BIT_DEPTH_CONTROL__FMT_SPATIAL_DITHER_DEPTH_MASK);
589 else
590 tmp |= (FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_EN_MASK |
591 FMT_BIT_DEPTH_CONTROL__FMT_TRUNCATE_DEPTH_MASK);
592 break;
593 case 10:
594 default:
595 /* not needed */
596 break;
597 }
598
599 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
600}
601
602/**
603 * cik_get_number_of_dram_channels - get the number of dram channels
604 *
605 * @adev: amdgpu_device pointer
606 *
607 * Look up the number of video ram channels (CIK).
608 * Used for display watermark bandwidth calculations
609 * Returns the number of dram channels
610 */
611static u32 si_get_number_of_dram_channels(struct amdgpu_device *adev)
612{
613 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
614
615 switch ((tmp & MC_SHARED_CHMAP__NOOFCHAN_MASK) >> MC_SHARED_CHMAP__NOOFCHAN__SHIFT) {
616 case 0:
617 default:
618 return 1;
619 case 1:
620 return 2;
621 case 2:
622 return 4;
623 case 3:
624 return 8;
625 case 4:
626 return 3;
627 case 5:
628 return 6;
629 case 6:
630 return 10;
631 case 7:
632 return 12;
633 case 8:
634 return 16;
635 }
636}
637
638struct dce6_wm_params {
639 u32 dram_channels; /* number of dram channels */
640 u32 yclk; /* bandwidth per dram data pin in kHz */
641 u32 sclk; /* engine clock in kHz */
642 u32 disp_clk; /* display clock in kHz */
643 u32 src_width; /* viewport width */
644 u32 active_time; /* active display time in ns */
645 u32 blank_time; /* blank time in ns */
646 bool interlaced; /* mode is interlaced */
647 fixed20_12 vsc; /* vertical scale ratio */
648 u32 num_heads; /* number of active crtcs */
649 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
650 u32 lb_size; /* line buffer allocated to pipe */
651 u32 vtaps; /* vertical scaler taps */
652};
653
654/**
655 * dce_v6_0_dram_bandwidth - get the dram bandwidth
656 *
657 * @wm: watermark calculation data
658 *
659 * Calculate the raw dram bandwidth (CIK).
660 * Used for display watermark bandwidth calculations
661 * Returns the dram bandwidth in MBytes/s
662 */
663static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm)
664{
665 /* Calculate raw DRAM Bandwidth */
666 fixed20_12 dram_efficiency; /* 0.7 */
667 fixed20_12 yclk, dram_channels, bandwidth;
668 fixed20_12 a;
669
670 a.full = dfixed_const(1000);
671 yclk.full = dfixed_const(wm->yclk);
672 yclk.full = dfixed_div(yclk, a);
673 dram_channels.full = dfixed_const(wm->dram_channels * 4);
674 a.full = dfixed_const(10);
675 dram_efficiency.full = dfixed_const(7);
676 dram_efficiency.full = dfixed_div(dram_efficiency, a);
677 bandwidth.full = dfixed_mul(dram_channels, yclk);
678 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
679
680 return dfixed_trunc(bandwidth);
681}
682
683/**
684 * dce_v6_0_dram_bandwidth_for_display - get the dram bandwidth for display
685 *
686 * @wm: watermark calculation data
687 *
688 * Calculate the dram bandwidth used for display (CIK).
689 * Used for display watermark bandwidth calculations
690 * Returns the dram bandwidth for display in MBytes/s
691 */
692static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm)
693{
694 /* Calculate DRAM Bandwidth and the part allocated to display. */
695 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
696 fixed20_12 yclk, dram_channels, bandwidth;
697 fixed20_12 a;
698
699 a.full = dfixed_const(1000);
700 yclk.full = dfixed_const(wm->yclk);
701 yclk.full = dfixed_div(yclk, a);
702 dram_channels.full = dfixed_const(wm->dram_channels * 4);
703 a.full = dfixed_const(10);
704 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
705 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
706 bandwidth.full = dfixed_mul(dram_channels, yclk);
707 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
708
709 return dfixed_trunc(bandwidth);
710}
711
712/**
713 * dce_v6_0_data_return_bandwidth - get the data return bandwidth
714 *
715 * @wm: watermark calculation data
716 *
717 * Calculate the data return bandwidth used for display (CIK).
718 * Used for display watermark bandwidth calculations
719 * Returns the data return bandwidth in MBytes/s
720 */
721static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm)
722{
723 /* Calculate the display Data return Bandwidth */
724 fixed20_12 return_efficiency; /* 0.8 */
725 fixed20_12 sclk, bandwidth;
726 fixed20_12 a;
727
728 a.full = dfixed_const(1000);
729 sclk.full = dfixed_const(wm->sclk);
730 sclk.full = dfixed_div(sclk, a);
731 a.full = dfixed_const(10);
732 return_efficiency.full = dfixed_const(8);
733 return_efficiency.full = dfixed_div(return_efficiency, a);
734 a.full = dfixed_const(32);
735 bandwidth.full = dfixed_mul(a, sclk);
736 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
737
738 return dfixed_trunc(bandwidth);
739}
740
741/**
742 * dce_v6_0_dmif_request_bandwidth - get the dmif bandwidth
743 *
744 * @wm: watermark calculation data
745 *
746 * Calculate the dmif bandwidth used for display (CIK).
747 * Used for display watermark bandwidth calculations
748 * Returns the dmif bandwidth in MBytes/s
749 */
750static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm)
751{
752 /* Calculate the DMIF Request Bandwidth */
753 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
754 fixed20_12 disp_clk, bandwidth;
755 fixed20_12 a, b;
756
757 a.full = dfixed_const(1000);
758 disp_clk.full = dfixed_const(wm->disp_clk);
759 disp_clk.full = dfixed_div(disp_clk, a);
760 a.full = dfixed_const(32);
761 b.full = dfixed_mul(a, disp_clk);
762
763 a.full = dfixed_const(10);
764 disp_clk_request_efficiency.full = dfixed_const(8);
765 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
766
767 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
768
769 return dfixed_trunc(bandwidth);
770}
771
772/**
773 * dce_v6_0_available_bandwidth - get the min available bandwidth
774 *
775 * @wm: watermark calculation data
776 *
777 * Calculate the min available bandwidth used for display (CIK).
778 * Used for display watermark bandwidth calculations
779 * Returns the min available bandwidth in MBytes/s
780 */
781static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm)
782{
783 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
784 u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm);
785 u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm);
786 u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm);
787
788 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
789}
790
791/**
792 * dce_v6_0_average_bandwidth - get the average available bandwidth
793 *
794 * @wm: watermark calculation data
795 *
796 * Calculate the average available bandwidth used for display (CIK).
797 * Used for display watermark bandwidth calculations
798 * Returns the average available bandwidth in MBytes/s
799 */
800static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm)
801{
802 /* Calculate the display mode Average Bandwidth
803 * DisplayMode should contain the source and destination dimensions,
804 * timing, etc.
805 */
806 fixed20_12 bpp;
807 fixed20_12 line_time;
808 fixed20_12 src_width;
809 fixed20_12 bandwidth;
810 fixed20_12 a;
811
812 a.full = dfixed_const(1000);
813 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
814 line_time.full = dfixed_div(line_time, a);
815 bpp.full = dfixed_const(wm->bytes_per_pixel);
816 src_width.full = dfixed_const(wm->src_width);
817 bandwidth.full = dfixed_mul(src_width, bpp);
818 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
819 bandwidth.full = dfixed_div(bandwidth, line_time);
820
821 return dfixed_trunc(bandwidth);
822}
823
824/**
825 * dce_v6_0_latency_watermark - get the latency watermark
826 *
827 * @wm: watermark calculation data
828 *
829 * Calculate the latency watermark (CIK).
830 * Used for display watermark bandwidth calculations
831 * Returns the latency watermark in ns
832 */
833static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm)
834{
835 /* First calculate the latency in ns */
836 u32 mc_latency = 2000; /* 2000 ns. */
837 u32 available_bandwidth = dce_v6_0_available_bandwidth(wm);
838 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
839 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
840 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
841 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
842 (wm->num_heads * cursor_line_pair_return_time);
843 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
844 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
845 u32 tmp, dmif_size = 12288;
846 fixed20_12 a, b, c;
847
848 if (wm->num_heads == 0)
849 return 0;
850
851 a.full = dfixed_const(2);
852 b.full = dfixed_const(1);
853 if ((wm->vsc.full > a.full) ||
854 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
855 (wm->vtaps >= 5) ||
856 ((wm->vsc.full >= a.full) && wm->interlaced))
857 max_src_lines_per_dst_line = 4;
858 else
859 max_src_lines_per_dst_line = 2;
860
861 a.full = dfixed_const(available_bandwidth);
862 b.full = dfixed_const(wm->num_heads);
863 a.full = dfixed_div(a, b);
864
865 b.full = dfixed_const(mc_latency + 512);
866 c.full = dfixed_const(wm->disp_clk);
867 b.full = dfixed_div(b, c);
868
869 c.full = dfixed_const(dmif_size);
870 b.full = dfixed_div(c, b);
871
872 tmp = min(dfixed_trunc(a), dfixed_trunc(b));
873
874 b.full = dfixed_const(1000);
875 c.full = dfixed_const(wm->disp_clk);
876 b.full = dfixed_div(c, b);
877 c.full = dfixed_const(wm->bytes_per_pixel);
878 b.full = dfixed_mul(b, c);
879
880 lb_fill_bw = min(tmp, dfixed_trunc(b));
881
882 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
883 b.full = dfixed_const(1000);
884 c.full = dfixed_const(lb_fill_bw);
885 b.full = dfixed_div(c, b);
886 a.full = dfixed_div(a, b);
887 line_fill_time = dfixed_trunc(a);
888
889 if (line_fill_time < wm->active_time)
890 return latency;
891 else
892 return latency + (line_fill_time - wm->active_time);
893
894}
895
896/**
897 * dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display - check
898 * average and available dram bandwidth
899 *
900 * @wm: watermark calculation data
901 *
902 * Check if the display average bandwidth fits in the display
903 * dram bandwidth (CIK).
904 * Used for display watermark bandwidth calculations
905 * Returns true if the display fits, false if not.
906 */
907static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm)
908{
909 if (dce_v6_0_average_bandwidth(wm) <=
910 (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads))
911 return true;
912 else
913 return false;
914}
915
916/**
917 * dce_v6_0_average_bandwidth_vs_available_bandwidth - check
918 * average and available bandwidth
919 *
920 * @wm: watermark calculation data
921 *
922 * Check if the display average bandwidth fits in the display
923 * available bandwidth (CIK).
924 * Used for display watermark bandwidth calculations
925 * Returns true if the display fits, false if not.
926 */
927static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm)
928{
929 if (dce_v6_0_average_bandwidth(wm) <=
930 (dce_v6_0_available_bandwidth(wm) / wm->num_heads))
931 return true;
932 else
933 return false;
934}
935
936/**
937 * dce_v6_0_check_latency_hiding - check latency hiding
938 *
939 * @wm: watermark calculation data
940 *
941 * Check latency hiding (CIK).
942 * Used for display watermark bandwidth calculations
943 * Returns true if the display fits, false if not.
944 */
945static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm)
946{
947 u32 lb_partitions = wm->lb_size / wm->src_width;
948 u32 line_time = wm->active_time + wm->blank_time;
949 u32 latency_tolerant_lines;
950 u32 latency_hiding;
951 fixed20_12 a;
952
953 a.full = dfixed_const(1);
954 if (wm->vsc.full > a.full)
955 latency_tolerant_lines = 1;
956 else {
957 if (lb_partitions <= (wm->vtaps + 1))
958 latency_tolerant_lines = 1;
959 else
960 latency_tolerant_lines = 2;
961 }
962
963 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
964
965 if (dce_v6_0_latency_watermark(wm) <= latency_hiding)
966 return true;
967 else
968 return false;
969}
970
971/**
972 * dce_v6_0_program_watermarks - program display watermarks
973 *
974 * @adev: amdgpu_device pointer
975 * @amdgpu_crtc: the selected display controller
976 * @lb_size: line buffer size
977 * @num_heads: number of display controllers in use
978 *
979 * Calculate and program the display watermarks for the
980 * selected display controller (CIK).
981 */
982static void dce_v6_0_program_watermarks(struct amdgpu_device *adev,
983 struct amdgpu_crtc *amdgpu_crtc,
984 u32 lb_size, u32 num_heads)
985{
986 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
987 struct dce6_wm_params wm_low, wm_high;
988 u32 dram_channels;
989 u32 pixel_period;
990 u32 line_time = 0;
991 u32 latency_watermark_a = 0, latency_watermark_b = 0;
992 u32 priority_a_mark = 0, priority_b_mark = 0;
993 u32 priority_a_cnt = PRIORITY_OFF;
994 u32 priority_b_cnt = PRIORITY_OFF;
995 u32 tmp, arb_control3;
996 fixed20_12 a, b, c;
997
998 if (amdgpu_crtc->base.enabled && num_heads && mode) {
999 pixel_period = 1000000 / (u32)mode->clock;
1000 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
1001 priority_a_cnt = 0;
1002 priority_b_cnt = 0;
1003
1004 dram_channels = si_get_number_of_dram_channels(adev);
1005
1006 /* watermark for high clocks */
1007 if (adev->pm.dpm_enabled) {
1008 wm_high.yclk =
1009 amdgpu_dpm_get_mclk(adev, false) * 10;
1010 wm_high.sclk =
1011 amdgpu_dpm_get_sclk(adev, false) * 10;
1012 } else {
1013 wm_high.yclk = adev->pm.current_mclk * 10;
1014 wm_high.sclk = adev->pm.current_sclk * 10;
1015 }
1016
1017 wm_high.disp_clk = mode->clock;
1018 wm_high.src_width = mode->crtc_hdisplay;
1019 wm_high.active_time = mode->crtc_hdisplay * pixel_period;
1020 wm_high.blank_time = line_time - wm_high.active_time;
1021 wm_high.interlaced = false;
1022 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1023 wm_high.interlaced = true;
1024 wm_high.vsc = amdgpu_crtc->vsc;
1025 wm_high.vtaps = 1;
1026 if (amdgpu_crtc->rmx_type != RMX_OFF)
1027 wm_high.vtaps = 2;
1028 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1029 wm_high.lb_size = lb_size;
1030 wm_high.dram_channels = dram_channels;
1031 wm_high.num_heads = num_heads;
1032
1033 if (adev->pm.dpm_enabled) {
1034 /* watermark for low clocks */
1035 wm_low.yclk =
1036 amdgpu_dpm_get_mclk(adev, true) * 10;
1037 wm_low.sclk =
1038 amdgpu_dpm_get_sclk(adev, true) * 10;
1039 } else {
1040 wm_low.yclk = adev->pm.current_mclk * 10;
1041 wm_low.sclk = adev->pm.current_sclk * 10;
1042 }
1043
1044 wm_low.disp_clk = mode->clock;
1045 wm_low.src_width = mode->crtc_hdisplay;
1046 wm_low.active_time = mode->crtc_hdisplay * pixel_period;
1047 wm_low.blank_time = line_time - wm_low.active_time;
1048 wm_low.interlaced = false;
1049 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1050 wm_low.interlaced = true;
1051 wm_low.vsc = amdgpu_crtc->vsc;
1052 wm_low.vtaps = 1;
1053 if (amdgpu_crtc->rmx_type != RMX_OFF)
1054 wm_low.vtaps = 2;
1055 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1056 wm_low.lb_size = lb_size;
1057 wm_low.dram_channels = dram_channels;
1058 wm_low.num_heads = num_heads;
1059
1060 /* set for high clocks */
1061 latency_watermark_a = min(dce_v6_0_latency_watermark(&wm_high), (u32)65535);
1062 /* set for low clocks */
1063 latency_watermark_b = min(dce_v6_0_latency_watermark(&wm_low), (u32)65535);
1064
1065 /* possibly force display priority to high */
1066 /* should really do this at mode validation time... */
1067 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1068 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1069 !dce_v6_0_check_latency_hiding(&wm_high) ||
1070 (adev->mode_info.disp_priority == 2)) {
1071 DRM_DEBUG_KMS("force priority to high\n");
1072 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1073 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1074 }
1075 if (!dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1076 !dce_v6_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1077 !dce_v6_0_check_latency_hiding(&wm_low) ||
1078 (adev->mode_info.disp_priority == 2)) {
1079 DRM_DEBUG_KMS("force priority to high\n");
1080 priority_a_cnt |= PRIORITY_ALWAYS_ON;
1081 priority_b_cnt |= PRIORITY_ALWAYS_ON;
1082 }
1083
1084 a.full = dfixed_const(1000);
1085 b.full = dfixed_const(mode->clock);
1086 b.full = dfixed_div(b, a);
1087 c.full = dfixed_const(latency_watermark_a);
1088 c.full = dfixed_mul(c, b);
1089 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1090 c.full = dfixed_div(c, a);
1091 a.full = dfixed_const(16);
1092 c.full = dfixed_div(c, a);
1093 priority_a_mark = dfixed_trunc(c);
1094 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
1095
1096 a.full = dfixed_const(1000);
1097 b.full = dfixed_const(mode->clock);
1098 b.full = dfixed_div(b, a);
1099 c.full = dfixed_const(latency_watermark_b);
1100 c.full = dfixed_mul(c, b);
1101 c.full = dfixed_mul(c, amdgpu_crtc->hsc);
1102 c.full = dfixed_div(c, a);
1103 a.full = dfixed_const(16);
1104 c.full = dfixed_div(c, a);
1105 priority_b_mark = dfixed_trunc(c);
1106 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
1107 }
1108
1109 /* select wm A */
1110 arb_control3 = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1111 tmp = arb_control3;
1112 tmp &= ~LATENCY_WATERMARK_MASK(3);
1113 tmp |= LATENCY_WATERMARK_MASK(1);
1114 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1115 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1116 ((latency_watermark_a << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1117 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1118 /* select wm B */
1119 tmp = RREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset);
1120 tmp &= ~LATENCY_WATERMARK_MASK(3);
1121 tmp |= LATENCY_WATERMARK_MASK(2);
1122 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, tmp);
1123 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset,
1124 ((latency_watermark_b << DPG_PIPE_URGENCY_CONTROL__URGENCY_LOW_WATERMARK__SHIFT) |
1125 (line_time << DPG_PIPE_URGENCY_CONTROL__URGENCY_HIGH_WATERMARK__SHIFT)));
1126 /* restore original selection */
1127 WREG32(mmDPG_PIPE_ARBITRATION_CONTROL3 + amdgpu_crtc->crtc_offset, arb_control3);
1128
1129 /* write the priority marks */
1130 WREG32(mmPRIORITY_A_CNT + amdgpu_crtc->crtc_offset, priority_a_cnt);
1131 WREG32(mmPRIORITY_B_CNT + amdgpu_crtc->crtc_offset, priority_b_cnt);
1132
1133 /* save values for DPM */
1134 amdgpu_crtc->line_time = line_time;
1135 amdgpu_crtc->wm_high = latency_watermark_a;
1136}
1137
1138/* watermark setup */
1139static u32 dce_v6_0_line_buffer_adjust(struct amdgpu_device *adev,
1140 struct amdgpu_crtc *amdgpu_crtc,
1141 struct drm_display_mode *mode,
1142 struct drm_display_mode *other_mode)
1143{
1144 u32 tmp, buffer_alloc, i;
1145 u32 pipe_offset = amdgpu_crtc->crtc_id * 0x8;
1146 /*
1147 * Line Buffer Setup
1148 * There are 3 line buffers, each one shared by 2 display controllers.
1149 * mmDC_LB_MEMORY_SPLIT controls how that line buffer is shared between
1150 * the display controllers. The paritioning is done via one of four
1151 * preset allocations specified in bits 21:20:
1152 * 0 - half lb
1153 * 2 - whole lb, other crtc must be disabled
1154 */
1155 /* this can get tricky if we have two large displays on a paired group
1156 * of crtcs. Ideally for multiple large displays we'd assign them to
1157 * non-linked crtcs for maximum line buffer allocation.
1158 */
1159 if (amdgpu_crtc->base.enabled && mode) {
1160 if (other_mode) {
1161 tmp = 0; /* 1/2 */
1162 buffer_alloc = 1;
1163 } else {
1164 tmp = 2; /* whole */
1165 buffer_alloc = 2;
1166 }
1167 } else {
1168 tmp = 0;
1169 buffer_alloc = 0;
1170 }
1171
1172 WREG32(mmDC_LB_MEMORY_SPLIT + amdgpu_crtc->crtc_offset,
1173 DC_LB_MEMORY_CONFIG(tmp));
1174
1175 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset,
1176 (buffer_alloc << PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATED__SHIFT));
1177 for (i = 0; i < adev->usec_timeout; i++) {
1178 if (RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset) &
1179 PIPE0_DMIF_BUFFER_CONTROL__DMIF_BUFFERS_ALLOCATION_COMPLETED_MASK)
1180 break;
1181 udelay(1);
1182 }
1183
1184 if (amdgpu_crtc->base.enabled && mode) {
1185 switch (tmp) {
1186 case 0:
1187 default:
1188 return 4096 * 2;
1189 case 2:
1190 return 8192 * 2;
1191 }
1192 }
1193
1194 /* controller not enabled, so no lb used */
1195 return 0;
1196}
1197
1198
1199/**
1200 *
1201 * dce_v6_0_bandwidth_update - program display watermarks
1202 *
1203 * @adev: amdgpu_device pointer
1204 *
1205 * Calculate and program the display watermarks and line
1206 * buffer allocation (CIK).
1207 */
1208static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
1209{
1210 struct drm_display_mode *mode0 = NULL;
1211 struct drm_display_mode *mode1 = NULL;
1212 u32 num_heads = 0, lb_size;
1213 int i;
1214
1215 if (!adev->mode_info.mode_config_initialized)
1216 return;
1217
1218 amdgpu_update_display_priority(adev);
1219
1220 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1221 if (adev->mode_info.crtcs[i]->base.enabled)
1222 num_heads++;
1223 }
1224 for (i = 0; i < adev->mode_info.num_crtc; i += 2) {
1225 mode0 = &adev->mode_info.crtcs[i]->base.mode;
1226 mode1 = &adev->mode_info.crtcs[i+1]->base.mode;
1227 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode0, mode1);
1228 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i], lb_size, num_heads);
1229 lb_size = dce_v6_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i+1], mode1, mode0);
1230 dce_v6_0_program_watermarks(adev, adev->mode_info.crtcs[i+1], lb_size, num_heads);
1231 }
1232}
1233/*
1234static void dce_v6_0_audio_get_connected_pins(struct amdgpu_device *adev)
1235{
1236 int i;
1237 u32 offset, tmp;
1238
1239 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1240 offset = adev->mode_info.audio.pin[i].offset;
1241 tmp = RREG32_AUDIO_ENDPT(offset,
1242 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1243 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
1244 adev->mode_info.audio.pin[i].connected = false;
1245 else
1246 adev->mode_info.audio.pin[i].connected = true;
1247 }
1248
1249}
1250
1251static struct amdgpu_audio_pin *dce_v6_0_audio_get_pin(struct amdgpu_device *adev)
1252{
1253 int i;
1254
1255 dce_v6_0_audio_get_connected_pins(adev);
1256
1257 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1258 if (adev->mode_info.audio.pin[i].connected)
1259 return &adev->mode_info.audio.pin[i];
1260 }
1261 DRM_ERROR("No connected audio pins found!\n");
1262 return NULL;
1263}
1264
1265static void dce_v6_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1266{
1267 struct amdgpu_device *adev = encoder->dev->dev_private;
1268 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1269 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1270 u32 offset;
1271
1272 if (!dig || !dig->afmt || !dig->afmt->pin)
1273 return;
1274
1275 offset = dig->afmt->offset;
1276
1277 WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
1278 AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
1279
1280}
1281
1282static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder,
1283 struct drm_display_mode *mode)
1284{
1285 DRM_INFO("xxxx: dce_v6_0_audio_write_latency_fields---no imp!!!!!\n");
1286}
1287
1288static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1289{
1290 DRM_INFO("xxxx: dce_v6_0_audio_write_speaker_allocation---no imp!!!!!\n");
1291}
1292
1293static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder)
1294{
1295 DRM_INFO("xxxx: dce_v6_0_audio_write_sad_regs---no imp!!!!!\n");
1296
1297}
1298*/
1299static void dce_v6_0_audio_enable(struct amdgpu_device *adev,
1300 struct amdgpu_audio_pin *pin,
1301 bool enable)
1302{
1303 DRM_INFO("xxxx: dce_v6_0_audio_enable---no imp!!!!!\n");
1304}
1305
1306static const u32 pin_offsets[7] =
1307{
1308 (0x1780 - 0x1780),
1309 (0x1786 - 0x1780),
1310 (0x178c - 0x1780),
1311 (0x1792 - 0x1780),
1312 (0x1798 - 0x1780),
1313 (0x179d - 0x1780),
1314 (0x17a4 - 0x1780),
1315};
1316
1317static int dce_v6_0_audio_init(struct amdgpu_device *adev)
1318{
1319 return 0;
1320}
1321
1322static void dce_v6_0_audio_fini(struct amdgpu_device *adev)
1323{
1324
1325}
1326
1327/*
1328static void dce_v6_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1329{
1330 DRM_INFO("xxxx: dce_v6_0_afmt_update_ACR---no imp!!!!!\n");
1331}
1332*/
1333/*
1334 * build a HDMI Video Info Frame
1335 */
1336/*
1337static void dce_v6_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1338 void *buffer, size_t size)
1339{
1340 DRM_INFO("xxxx: dce_v6_0_afmt_update_avi_infoframe---no imp!!!!!\n");
1341}
1342
1343static void dce_v6_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1344{
1345 DRM_INFO("xxxx: dce_v6_0_audio_set_dto---no imp!!!!!\n");
1346}
1347*/
1348/*
1349 * update the info frames with the data from the current display mode
1350 */
1351static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder,
1352 struct drm_display_mode *mode)
1353{
1354 DRM_INFO("xxxx: dce_v6_0_afmt_setmode ----no impl !!!!!!!!\n");
1355}
1356
1357static void dce_v6_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1358{
1359 struct drm_device *dev = encoder->dev;
1360 struct amdgpu_device *adev = dev->dev_private;
1361 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1362 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1363
1364 if (!dig || !dig->afmt)
1365 return;
1366
1367 /* Silent, r600_hdmi_enable will raise WARN for us */
1368 if (enable && dig->afmt->enabled)
1369 return;
1370 if (!enable && !dig->afmt->enabled)
1371 return;
1372
1373 if (!enable && dig->afmt->pin) {
1374 dce_v6_0_audio_enable(adev, dig->afmt->pin, false);
1375 dig->afmt->pin = NULL;
1376 }
1377
1378 dig->afmt->enabled = enable;
1379
1380 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1381 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1382}
1383
1384static int dce_v6_0_afmt_init(struct amdgpu_device *adev)
1385{
1386 int i, j;
1387
1388 for (i = 0; i < adev->mode_info.num_dig; i++)
1389 adev->mode_info.afmt[i] = NULL;
1390
1391 /* DCE6 has audio blocks tied to DIG encoders */
1392 for (i = 0; i < adev->mode_info.num_dig; i++) {
1393 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1394 if (adev->mode_info.afmt[i]) {
1395 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1396 adev->mode_info.afmt[i]->id = i;
1397 } else {
1398 for (j = 0; j < i; j++) {
1399 kfree(adev->mode_info.afmt[j]);
1400 adev->mode_info.afmt[j] = NULL;
1401 }
1402 DRM_ERROR("Out of memory allocating afmt table\n");
1403 return -ENOMEM;
1404 }
1405 }
1406 return 0;
1407}
1408
1409static void dce_v6_0_afmt_fini(struct amdgpu_device *adev)
1410{
1411 int i;
1412
1413 for (i = 0; i < adev->mode_info.num_dig; i++) {
1414 kfree(adev->mode_info.afmt[i]);
1415 adev->mode_info.afmt[i] = NULL;
1416 }
1417}
1418
1419static const u32 vga_control_regs[6] =
1420{
1421 mmD1VGA_CONTROL,
1422 mmD2VGA_CONTROL,
1423 mmD3VGA_CONTROL,
1424 mmD4VGA_CONTROL,
1425 mmD5VGA_CONTROL,
1426 mmD6VGA_CONTROL,
1427};
1428
1429static void dce_v6_0_vga_enable(struct drm_crtc *crtc, bool enable)
1430{
1431 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1432 struct drm_device *dev = crtc->dev;
1433 struct amdgpu_device *adev = dev->dev_private;
1434 u32 vga_control;
1435
1436 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1437 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | (enable ? 1 : 0));
1438}
1439
1440static void dce_v6_0_grph_enable(struct drm_crtc *crtc, bool enable)
1441{
1442 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1443 struct drm_device *dev = crtc->dev;
1444 struct amdgpu_device *adev = dev->dev_private;
1445
1446 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, enable ? 1 : 0);
1447}
1448
1449static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc,
1450 struct drm_framebuffer *fb,
1451 int x, int y, int atomic)
1452{
1453 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1454 struct drm_device *dev = crtc->dev;
1455 struct amdgpu_device *adev = dev->dev_private;
1456 struct amdgpu_framebuffer *amdgpu_fb;
1457 struct drm_framebuffer *target_fb;
1458 struct drm_gem_object *obj;
1459 struct amdgpu_bo *abo;
1460 uint64_t fb_location, tiling_flags;
1461 uint32_t fb_format, fb_pitch_pixels, pipe_config;
1462 u32 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_NONE);
1463 u32 viewport_w, viewport_h;
1464 int r;
1465 bool bypass_lut = false;
1466 struct drm_format_name_buf format_name;
1467
1468 /* no fb bound */
1469 if (!atomic && !crtc->primary->fb) {
1470 DRM_DEBUG_KMS("No FB bound\n");
1471 return 0;
1472 }
1473
1474 if (atomic) {
1475 amdgpu_fb = to_amdgpu_framebuffer(fb);
1476 target_fb = fb;
1477 } else {
1478 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1479 target_fb = crtc->primary->fb;
1480 }
1481
1482 /* If atomic, assume fb object is pinned & idle & fenced and
1483 * just update base pointers
1484 */
1485 obj = amdgpu_fb->obj;
1486 abo = gem_to_amdgpu_bo(obj);
1487 r = amdgpu_bo_reserve(abo, false);
1488 if (unlikely(r != 0))
1489 return r;
1490
1491 if (atomic) {
1492 fb_location = amdgpu_bo_gpu_offset(abo);
1493 } else {
1494 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1495 if (unlikely(r != 0)) {
1496 amdgpu_bo_unreserve(abo);
1497 return -EINVAL;
1498 }
1499 }
1500
1501 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1502 amdgpu_bo_unreserve(abo);
1503
1504 switch (target_fb->pixel_format) {
1505 case DRM_FORMAT_C8:
1506 fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) |
1507 GRPH_FORMAT(GRPH_FORMAT_INDEXED));
1508 break;
1509 case DRM_FORMAT_XRGB4444:
1510 case DRM_FORMAT_ARGB4444:
1511 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1512 GRPH_FORMAT(GRPH_FORMAT_ARGB4444));
1513#ifdef __BIG_ENDIAN
1514 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1515#endif
1516 break;
1517 case DRM_FORMAT_XRGB1555:
1518 case DRM_FORMAT_ARGB1555:
1519 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1520 GRPH_FORMAT(GRPH_FORMAT_ARGB1555));
1521#ifdef __BIG_ENDIAN
1522 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1523#endif
1524 break;
1525 case DRM_FORMAT_BGRX5551:
1526 case DRM_FORMAT_BGRA5551:
1527 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1528 GRPH_FORMAT(GRPH_FORMAT_BGRA5551));
1529#ifdef __BIG_ENDIAN
1530 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1531#endif
1532 break;
1533 case DRM_FORMAT_RGB565:
1534 fb_format = (GRPH_DEPTH(GRPH_DEPTH_16BPP) |
1535 GRPH_FORMAT(GRPH_FORMAT_ARGB565));
1536#ifdef __BIG_ENDIAN
1537 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN16);
1538#endif
1539 break;
1540 case DRM_FORMAT_XRGB8888:
1541 case DRM_FORMAT_ARGB8888:
1542 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1543 GRPH_FORMAT(GRPH_FORMAT_ARGB8888));
1544#ifdef __BIG_ENDIAN
1545 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1546#endif
1547 break;
1548 case DRM_FORMAT_XRGB2101010:
1549 case DRM_FORMAT_ARGB2101010:
1550 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1551 GRPH_FORMAT(GRPH_FORMAT_ARGB2101010));
1552#ifdef __BIG_ENDIAN
1553 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1554#endif
1555 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1556 bypass_lut = true;
1557 break;
1558 case DRM_FORMAT_BGRX1010102:
1559 case DRM_FORMAT_BGRA1010102:
1560 fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) |
1561 GRPH_FORMAT(GRPH_FORMAT_BGRA1010102));
1562#ifdef __BIG_ENDIAN
1563 fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32);
1564#endif
1565 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1566 bypass_lut = true;
1567 break;
1568 default:
1569 DRM_ERROR("Unsupported screen format %s\n",
1570 drm_get_format_name(target_fb->pixel_format, &format_name));
1571 return -EINVAL;
1572 }
1573
1574 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1575 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1576
1577 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1578 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1579 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1580 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
1581 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
1582
1583 fb_format |= GRPH_NUM_BANKS(num_banks);
1584 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_2D_TILED_THIN1);
1585 fb_format |= GRPH_TILE_SPLIT(tile_split);
1586 fb_format |= GRPH_BANK_WIDTH(bankw);
1587 fb_format |= GRPH_BANK_HEIGHT(bankh);
1588 fb_format |= GRPH_MACRO_TILE_ASPECT(mtaspect);
1589 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
1590 fb_format |= GRPH_ARRAY_MODE(GRPH_ARRAY_1D_TILED_THIN1);
1591 }
1592
1593 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1594 fb_format |= GRPH_PIPE_CONFIG(pipe_config);
1595
1596 dce_v6_0_vga_enable(crtc, false);
1597
1598 /* Make sure surface address is updated at vertical blank rather than
1599 * horizontal blank
1600 */
1601 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, 0);
1602
1603 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1604 upper_32_bits(fb_location));
1605 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1606 upper_32_bits(fb_location));
1607 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1608 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1609 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1610 (u32) fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
1611 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
1612 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
1613
1614 /*
1615 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
1616 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
1617 * retain the full precision throughout the pipeline.
1618 */
1619 WREG32_P(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset,
1620 (bypass_lut ? GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK : 0),
1621 ~GRPH_LUT_10BIT_BYPASS__GRPH_LUT_10BIT_BYPASS_EN_MASK);
1622
1623 if (bypass_lut)
1624 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1625
1626 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
1627 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
1628 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
1629 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
1630 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
1631 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
1632
1633 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1634 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
1635
1636 dce_v6_0_grph_enable(crtc, true);
1637
1638 WREG32(mmDESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
1639 target_fb->height);
1640 x &= ~3;
1641 y &= ~1;
1642 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
1643 (x << 16) | y);
1644 viewport_w = crtc->mode.hdisplay;
1645 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1646
1647 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
1648 (viewport_w << 16) | viewport_h);
1649
1650 /* set pageflip to happen anywhere in vblank interval */
1651 WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
1652
1653 if (!atomic && fb && fb != crtc->primary->fb) {
1654 amdgpu_fb = to_amdgpu_framebuffer(fb);
1655 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
1656 r = amdgpu_bo_reserve(abo, false);
1657 if (unlikely(r != 0))
1658 return r;
1659 amdgpu_bo_unpin(abo);
1660 amdgpu_bo_unreserve(abo);
1661 }
1662
1663 /* Bytes per pixel may have changed */
1664 dce_v6_0_bandwidth_update(adev);
1665
1666 return 0;
1667
1668}
1669
1670static void dce_v6_0_set_interleave(struct drm_crtc *crtc,
1671 struct drm_display_mode *mode)
1672{
1673 struct drm_device *dev = crtc->dev;
1674 struct amdgpu_device *adev = dev->dev_private;
1675 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1676
1677 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1678 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset,
1679 INTERLEAVE_EN);
1680 else
1681 WREG32(mmDATA_FORMAT + amdgpu_crtc->crtc_offset, 0);
1682}
1683
1684static void dce_v6_0_crtc_load_lut(struct drm_crtc *crtc)
1685{
1686
1687 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1688 struct drm_device *dev = crtc->dev;
1689 struct amdgpu_device *adev = dev->dev_private;
1690 int i;
1691
1692 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
1693
1694 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1695 ((0 << INPUT_CSC_CONTROL__INPUT_CSC_GRPH_MODE__SHIFT) |
1696 (0 << INPUT_CSC_CONTROL__INPUT_CSC_OVL_MODE__SHIFT)));
1697 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset,
1698 PRESCALE_GRPH_CONTROL__GRPH_PRESCALE_BYPASS_MASK);
1699 WREG32(mmPRESCALE_OVL_CONTROL + amdgpu_crtc->crtc_offset,
1700 PRESCALE_OVL_CONTROL__OVL_PRESCALE_BYPASS_MASK);
1701 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1702 ((0 << INPUT_GAMMA_CONTROL__GRPH_INPUT_GAMMA_MODE__SHIFT) |
1703 (0 << INPUT_GAMMA_CONTROL__OVL_INPUT_GAMMA_MODE__SHIFT)));
1704
1705 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
1706
1707 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
1708 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
1709 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
1710
1711 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
1712 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
1713 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
1714
1715 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
1716 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
1717
1718 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
1719 for (i = 0; i < 256; i++) {
1720 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
1721 (amdgpu_crtc->lut_r[i] << 20) |
1722 (amdgpu_crtc->lut_g[i] << 10) |
1723 (amdgpu_crtc->lut_b[i] << 0));
1724 }
1725
1726 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1727 ((0 << DEGAMMA_CONTROL__GRPH_DEGAMMA_MODE__SHIFT) |
1728 (0 << DEGAMMA_CONTROL__OVL_DEGAMMA_MODE__SHIFT) |
1729 ICON_DEGAMMA_MODE(0) |
1730 (0 << DEGAMMA_CONTROL__CURSOR_DEGAMMA_MODE__SHIFT)));
1731 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset,
1732 ((0 << GAMUT_REMAP_CONTROL__GRPH_GAMUT_REMAP_MODE__SHIFT) |
1733 (0 << GAMUT_REMAP_CONTROL__OVL_GAMUT_REMAP_MODE__SHIFT)));
1734 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset,
1735 ((0 << REGAMMA_CONTROL__GRPH_REGAMMA_MODE__SHIFT) |
1736 (0 << REGAMMA_CONTROL__OVL_REGAMMA_MODE__SHIFT)));
1737 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset,
1738 ((0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_GRPH_MODE__SHIFT) |
1739 (0 << OUTPUT_CSC_CONTROL__OUTPUT_CSC_OVL_MODE__SHIFT)));
1740 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
1741 WREG32(0x1a50 + amdgpu_crtc->crtc_offset, 0);
1742
1743
1744}
1745
1746static int dce_v6_0_pick_dig_encoder(struct drm_encoder *encoder)
1747{
1748 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1749 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1750
1751 switch (amdgpu_encoder->encoder_id) {
1752 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1753 return dig->linkb ? 1 : 0;
1754 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1755 return dig->linkb ? 3 : 2;
1756 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1757 return dig->linkb ? 5 : 4;
1758 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1759 return 6;
1760 default:
1761 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
1762 return 0;
1763 }
1764}
1765
1766/**
1767 * dce_v6_0_pick_pll - Allocate a PPLL for use by the crtc.
1768 *
1769 * @crtc: drm crtc
1770 *
1771 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
1772 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
1773 * monitors a dedicated PPLL must be used. If a particular board has
1774 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
1775 * as there is no need to program the PLL itself. If we are not able to
1776 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
1777 * avoid messing up an existing monitor.
1778 *
1779 *
1780 */
1781static u32 dce_v6_0_pick_pll(struct drm_crtc *crtc)
1782{
1783 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1784 struct drm_device *dev = crtc->dev;
1785 struct amdgpu_device *adev = dev->dev_private;
1786 u32 pll_in_use;
1787 int pll;
1788
1789 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
1790 if (adev->clock.dp_extclk)
1791 /* skip PPLL programming if using ext clock */
1792 return ATOM_PPLL_INVALID;
1793 else
1794 return ATOM_PPLL0;
1795 } else {
1796 /* use the same PPLL for all monitors with the same clock */
1797 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
1798 if (pll != ATOM_PPLL_INVALID)
1799 return pll;
1800 }
1801
1802 /* PPLL1, and PPLL2 */
1803 pll_in_use = amdgpu_pll_get_use_mask(crtc);
1804 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1805 return ATOM_PPLL2;
1806 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1807 return ATOM_PPLL1;
1808 DRM_ERROR("unable to allocate a PPLL\n");
1809 return ATOM_PPLL_INVALID;
1810}
1811
1812static void dce_v6_0_lock_cursor(struct drm_crtc *crtc, bool lock)
1813{
1814 struct amdgpu_device *adev = crtc->dev->dev_private;
1815 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1816 uint32_t cur_lock;
1817
1818 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
1819 if (lock)
1820 cur_lock |= CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1821 else
1822 cur_lock &= ~CUR_UPDATE__CURSOR_UPDATE_LOCK_MASK;
1823 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
1824}
1825
1826static void dce_v6_0_hide_cursor(struct drm_crtc *crtc)
1827{
1828 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1829 struct amdgpu_device *adev = crtc->dev->dev_private;
1830
1831 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1832 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1833 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1834
1835
1836}
1837
1838static void dce_v6_0_show_cursor(struct drm_crtc *crtc)
1839{
1840 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1841 struct amdgpu_device *adev = crtc->dev->dev_private;
1842
1843 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
1844 upper_32_bits(amdgpu_crtc->cursor_addr));
1845 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
1846 lower_32_bits(amdgpu_crtc->cursor_addr));
1847
1848 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset,
1849 CUR_CONTROL__CURSOR_EN_MASK |
1850 (CURSOR_24_8_PRE_MULT << CUR_CONTROL__CURSOR_MODE__SHIFT) |
1851 (CURSOR_URGENT_1_2 << CUR_CONTROL__CURSOR_URGENT_CONTROL__SHIFT));
1852
1853}
1854
1855static int dce_v6_0_cursor_move_locked(struct drm_crtc *crtc,
1856 int x, int y)
1857{
1858 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1859 struct amdgpu_device *adev = crtc->dev->dev_private;
1860 int xorigin = 0, yorigin = 0;
1861
1862 int w = amdgpu_crtc->cursor_width;
1863
1864 amdgpu_crtc->cursor_x = x;
1865 amdgpu_crtc->cursor_y = y;
1866
1867 /* avivo cursor are offset into the total surface */
1868 x += crtc->x;
1869 y += crtc->y;
1870 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
1871
1872 if (x < 0) {
1873 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
1874 x = 0;
1875 }
1876 if (y < 0) {
1877 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
1878 y = 0;
1879 }
1880
1881 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
1882 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
1883 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
1884 ((w - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
1885
1886 return 0;
1887}
1888
1889static int dce_v6_0_crtc_cursor_move(struct drm_crtc *crtc,
1890 int x, int y)
1891{
1892 int ret;
1893
1894 dce_v6_0_lock_cursor(crtc, true);
1895 ret = dce_v6_0_cursor_move_locked(crtc, x, y);
1896 dce_v6_0_lock_cursor(crtc, false);
1897
1898 return ret;
1899}
1900
1901static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
1902 struct drm_file *file_priv,
1903 uint32_t handle,
1904 uint32_t width,
1905 uint32_t height,
1906 int32_t hot_x,
1907 int32_t hot_y)
1908{
1909 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1910 struct drm_gem_object *obj;
1911 struct amdgpu_bo *aobj;
1912 int ret;
1913
1914 if (!handle) {
1915 /* turn off cursor */
1916 dce_v6_0_hide_cursor(crtc);
1917 obj = NULL;
1918 goto unpin;
1919 }
1920
1921 if ((width > amdgpu_crtc->max_cursor_width) ||
1922 (height > amdgpu_crtc->max_cursor_height)) {
1923 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
1924 return -EINVAL;
1925 }
1926
1927 obj = drm_gem_object_lookup(file_priv, handle);
1928 if (!obj) {
1929 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
1930 return -ENOENT;
1931 }
1932
1933 aobj = gem_to_amdgpu_bo(obj);
1934 ret = amdgpu_bo_reserve(aobj, false);
1935 if (ret != 0) {
1936 drm_gem_object_unreference_unlocked(obj);
1937 return ret;
1938 }
1939
1940 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
1941 amdgpu_bo_unreserve(aobj);
1942 if (ret) {
1943 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
1944 drm_gem_object_unreference_unlocked(obj);
1945 return ret;
1946 }
1947
1948 dce_v6_0_lock_cursor(crtc, true);
1949
1950 if (width != amdgpu_crtc->cursor_width ||
1951 height != amdgpu_crtc->cursor_height ||
1952 hot_x != amdgpu_crtc->cursor_hot_x ||
1953 hot_y != amdgpu_crtc->cursor_hot_y) {
1954 int x, y;
1955
1956 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
1957 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
1958
1959 dce_v6_0_cursor_move_locked(crtc, x, y);
1960
1961 amdgpu_crtc->cursor_width = width;
1962 amdgpu_crtc->cursor_height = height;
1963 amdgpu_crtc->cursor_hot_x = hot_x;
1964 amdgpu_crtc->cursor_hot_y = hot_y;
1965 }
1966
1967 dce_v6_0_show_cursor(crtc);
1968 dce_v6_0_lock_cursor(crtc, false);
1969
1970unpin:
1971 if (amdgpu_crtc->cursor_bo) {
1972 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
1973 ret = amdgpu_bo_reserve(aobj, false);
1974 if (likely(ret == 0)) {
1975 amdgpu_bo_unpin(aobj);
1976 amdgpu_bo_unreserve(aobj);
1977 }
1978 drm_gem_object_unreference_unlocked(amdgpu_crtc->cursor_bo);
1979 }
1980
1981 amdgpu_crtc->cursor_bo = obj;
1982 return 0;
1983}
1984
1985static void dce_v6_0_cursor_reset(struct drm_crtc *crtc)
1986{
1987 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1988
1989 if (amdgpu_crtc->cursor_bo) {
1990 dce_v6_0_lock_cursor(crtc, true);
1991
1992 dce_v6_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
1993 amdgpu_crtc->cursor_y);
1994
1995 dce_v6_0_show_cursor(crtc);
1996 dce_v6_0_lock_cursor(crtc, false);
1997 }
1998}
1999
2000static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2001 u16 *blue, uint32_t size)
2002{
2003 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2004 int i;
2005
2006 /* userspace palettes are always correct as is */
2007 for (i = 0; i < size; i++) {
2008 amdgpu_crtc->lut_r[i] = red[i] >> 6;
2009 amdgpu_crtc->lut_g[i] = green[i] >> 6;
2010 amdgpu_crtc->lut_b[i] = blue[i] >> 6;
2011 }
2012 dce_v6_0_crtc_load_lut(crtc);
2013
2014 return 0;
2015}
2016
2017static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc)
2018{
2019 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2020
2021 drm_crtc_cleanup(crtc);
2022 kfree(amdgpu_crtc);
2023}
2024
2025static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
2026 .cursor_set2 = dce_v6_0_crtc_cursor_set2,
2027 .cursor_move = dce_v6_0_crtc_cursor_move,
2028 .gamma_set = dce_v6_0_crtc_gamma_set,
2029 .set_config = amdgpu_crtc_set_config,
2030 .destroy = dce_v6_0_crtc_destroy,
2031 .page_flip_target = amdgpu_crtc_page_flip_target,
2032};
2033
2034static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2035{
2036 struct drm_device *dev = crtc->dev;
2037 struct amdgpu_device *adev = dev->dev_private;
2038 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2039 unsigned type;
2040
2041 switch (mode) {
2042 case DRM_MODE_DPMS_ON:
2043 amdgpu_crtc->enabled = true;
2044 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2045 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2046 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2047 type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
2048 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2049 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2050 drm_crtc_vblank_on(crtc);
2051 dce_v6_0_crtc_load_lut(crtc);
2052 break;
2053 case DRM_MODE_DPMS_STANDBY:
2054 case DRM_MODE_DPMS_SUSPEND:
2055 case DRM_MODE_DPMS_OFF:
2056 drm_crtc_vblank_off(crtc);
2057 if (amdgpu_crtc->enabled)
2058 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2059 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2060 amdgpu_crtc->enabled = false;
2061 break;
2062 }
2063 /* adjust pm to dpms */
2064 amdgpu_pm_compute_clocks(adev);
2065}
2066
2067static void dce_v6_0_crtc_prepare(struct drm_crtc *crtc)
2068{
2069 /* disable crtc pair power gating before programming */
2070 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2071 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2072 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2073}
2074
2075static void dce_v6_0_crtc_commit(struct drm_crtc *crtc)
2076{
2077 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2078 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2079}
2080
2081static void dce_v6_0_crtc_disable(struct drm_crtc *crtc)
2082{
2083
2084 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2085 struct drm_device *dev = crtc->dev;
2086 struct amdgpu_device *adev = dev->dev_private;
2087 struct amdgpu_atom_ss ss;
2088 int i;
2089
2090 dce_v6_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2091 if (crtc->primary->fb) {
2092 int r;
2093 struct amdgpu_framebuffer *amdgpu_fb;
2094 struct amdgpu_bo *abo;
2095
2096 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2097 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2098 r = amdgpu_bo_reserve(abo, false);
2099 if (unlikely(r))
2100 DRM_ERROR("failed to reserve abo before unpin\n");
2101 else {
2102 amdgpu_bo_unpin(abo);
2103 amdgpu_bo_unreserve(abo);
2104 }
2105 }
2106 /* disable the GRPH */
2107 dce_v6_0_grph_enable(crtc, false);
2108
2109 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2110
2111 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2112 if (adev->mode_info.crtcs[i] &&
2113 adev->mode_info.crtcs[i]->enabled &&
2114 i != amdgpu_crtc->crtc_id &&
2115 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2116 /* one other crtc is using this pll don't turn
2117 * off the pll
2118 */
2119 goto done;
2120 }
2121 }
2122
2123 switch (amdgpu_crtc->pll_id) {
2124 case ATOM_PPLL1:
2125 case ATOM_PPLL2:
2126 /* disable the ppll */
2127 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2128 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2129 break;
2130 default:
2131 break;
2132 }
2133done:
2134 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2135 amdgpu_crtc->adjusted_clock = 0;
2136 amdgpu_crtc->encoder = NULL;
2137 amdgpu_crtc->connector = NULL;
2138}
2139
2140static int dce_v6_0_crtc_mode_set(struct drm_crtc *crtc,
2141 struct drm_display_mode *mode,
2142 struct drm_display_mode *adjusted_mode,
2143 int x, int y, struct drm_framebuffer *old_fb)
2144{
2145 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2146
2147 if (!amdgpu_crtc->adjusted_clock)
2148 return -EINVAL;
2149
2150 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2151 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2152 dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2153 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2154 amdgpu_atombios_crtc_scaler_setup(crtc);
2155 dce_v6_0_cursor_reset(crtc);
2156 /* update the hw version fpr dpm */
2157 amdgpu_crtc->hw_mode = *adjusted_mode;
2158
2159 return 0;
2160}
2161
2162static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
2163 const struct drm_display_mode *mode,
2164 struct drm_display_mode *adjusted_mode)
2165{
2166
2167 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2168 struct drm_device *dev = crtc->dev;
2169 struct drm_encoder *encoder;
2170
2171 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2172 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2173 if (encoder->crtc == crtc) {
2174 amdgpu_crtc->encoder = encoder;
2175 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2176 break;
2177 }
2178 }
2179 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2180 amdgpu_crtc->encoder = NULL;
2181 amdgpu_crtc->connector = NULL;
2182 return false;
2183 }
2184 if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2185 return false;
2186 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2187 return false;
2188 /* pick pll */
2189 amdgpu_crtc->pll_id = dce_v6_0_pick_pll(crtc);
2190 /* if we can't get a PPLL for a non-DP encoder, fail */
2191 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2192 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2193 return false;
2194
2195 return true;
2196}
2197
2198static int dce_v6_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2199 struct drm_framebuffer *old_fb)
2200{
2201 return dce_v6_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2202}
2203
2204static int dce_v6_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2205 struct drm_framebuffer *fb,
2206 int x, int y, enum mode_set_atomic state)
2207{
2208 return dce_v6_0_crtc_do_set_base(crtc, fb, x, y, 1);
2209}
2210
2211static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = {
2212 .dpms = dce_v6_0_crtc_dpms,
2213 .mode_fixup = dce_v6_0_crtc_mode_fixup,
2214 .mode_set = dce_v6_0_crtc_mode_set,
2215 .mode_set_base = dce_v6_0_crtc_set_base,
2216 .mode_set_base_atomic = dce_v6_0_crtc_set_base_atomic,
2217 .prepare = dce_v6_0_crtc_prepare,
2218 .commit = dce_v6_0_crtc_commit,
2219 .load_lut = dce_v6_0_crtc_load_lut,
2220 .disable = dce_v6_0_crtc_disable,
2221};
2222
2223static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index)
2224{
2225 struct amdgpu_crtc *amdgpu_crtc;
2226 int i;
2227
2228 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2229 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2230 if (amdgpu_crtc == NULL)
2231 return -ENOMEM;
2232
2233 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v6_0_crtc_funcs);
2234
2235 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2236 amdgpu_crtc->crtc_id = index;
2237 adev->mode_info.crtcs[index] = amdgpu_crtc;
2238
2239 amdgpu_crtc->max_cursor_width = CURSOR_WIDTH;
2240 amdgpu_crtc->max_cursor_height = CURSOR_HEIGHT;
2241 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2242 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2243
2244 for (i = 0; i < 256; i++) {
2245 amdgpu_crtc->lut_r[i] = i << 2;
2246 amdgpu_crtc->lut_g[i] = i << 2;
2247 amdgpu_crtc->lut_b[i] = i << 2;
2248 }
2249
2250 amdgpu_crtc->crtc_offset = crtc_offsets[amdgpu_crtc->crtc_id];
2251
2252 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2253 amdgpu_crtc->adjusted_clock = 0;
2254 amdgpu_crtc->encoder = NULL;
2255 amdgpu_crtc->connector = NULL;
2256 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v6_0_crtc_helper_funcs);
2257
2258 return 0;
2259}
2260
2261static int dce_v6_0_early_init(void *handle)
2262{
2263 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2264
2265 adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg;
2266 adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg;
2267
2268 dce_v6_0_set_display_funcs(adev);
2269 dce_v6_0_set_irq_funcs(adev);
2270
2271 adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
2272
2273 switch (adev->asic_type) {
2274 case CHIP_TAHITI:
2275 case CHIP_PITCAIRN:
2276 case CHIP_VERDE:
2277 adev->mode_info.num_hpd = 6;
2278 adev->mode_info.num_dig = 6;
2279 break;
2280 case CHIP_OLAND:
2281 adev->mode_info.num_hpd = 2;
2282 adev->mode_info.num_dig = 2;
2283 break;
2284 default:
2285 return -EINVAL;
2286 }
2287
2288 return 0;
2289}
2290
2291static int dce_v6_0_sw_init(void *handle)
2292{
2293 int r, i;
2294 bool ret;
2295 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2296
2297 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2298 r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
2299 if (r)
2300 return r;
2301 }
2302
2303 for (i = 8; i < 20; i += 2) {
2304 r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
2305 if (r)
2306 return r;
2307 }
2308
2309 /* HPD hotplug */
2310 r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
2311 if (r)
2312 return r;
2313
2314 adev->mode_info.mode_config_initialized = true;
2315
2316 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2317 adev->ddev->mode_config.async_page_flip = true;
2318 adev->ddev->mode_config.max_width = 16384;
2319 adev->ddev->mode_config.max_height = 16384;
2320 adev->ddev->mode_config.preferred_depth = 24;
2321 adev->ddev->mode_config.prefer_shadow = 1;
2322 adev->ddev->mode_config.fb_base = adev->mc.aper_base;
2323
2324 r = amdgpu_modeset_create_props(adev);
2325 if (r)
2326 return r;
2327
2328 adev->ddev->mode_config.max_width = 16384;
2329 adev->ddev->mode_config.max_height = 16384;
2330
2331 /* allocate crtcs */
2332 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2333 r = dce_v6_0_crtc_init(adev, i);
2334 if (r)
2335 return r;
2336 }
2337
2338 ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
2339 if (ret)
2340 amdgpu_print_display_setup(adev->ddev);
2341 else
2342 return -EINVAL;
2343
2344 /* setup afmt */
2345 r = dce_v6_0_afmt_init(adev);
2346 if (r)
2347 return r;
2348
2349 r = dce_v6_0_audio_init(adev);
2350 if (r)
2351 return r;
2352
2353 drm_kms_helper_poll_init(adev->ddev);
2354
2355 return r;
2356}
2357
2358static int dce_v6_0_sw_fini(void *handle)
2359{
2360 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2361
2362 kfree(adev->mode_info.bios_hardcoded_edid);
2363
2364 drm_kms_helper_poll_fini(adev->ddev);
2365
2366 dce_v6_0_audio_fini(adev);
2367 dce_v6_0_afmt_fini(adev);
2368
2369 drm_mode_config_cleanup(adev->ddev);
2370 adev->mode_info.mode_config_initialized = false;
2371
2372 return 0;
2373}
2374
2375static int dce_v6_0_hw_init(void *handle)
2376{
2377 int i;
2378 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2379
2380 /* init dig PHYs, disp eng pll */
2381 amdgpu_atombios_encoder_init_dig(adev);
2382 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2383
2384 /* initialize hpd */
2385 dce_v6_0_hpd_init(adev);
2386
2387 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2388 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2389 }
2390
2391 dce_v6_0_pageflip_interrupt_init(adev);
2392
2393 return 0;
2394}
2395
2396static int dce_v6_0_hw_fini(void *handle)
2397{
2398 int i;
2399 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2400
2401 dce_v6_0_hpd_fini(adev);
2402
2403 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2404 dce_v6_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2405 }
2406
2407 dce_v6_0_pageflip_interrupt_fini(adev);
2408
2409 return 0;
2410}
2411
2412static int dce_v6_0_suspend(void *handle)
2413{
2414 return dce_v6_0_hw_fini(handle);
2415}
2416
2417static int dce_v6_0_resume(void *handle)
2418{
2419 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2420 int ret;
2421
2422 ret = dce_v6_0_hw_init(handle);
2423
2424 /* turn on the BL */
2425 if (adev->mode_info.bl_encoder) {
2426 u8 bl_level = amdgpu_display_backlight_get_level(adev,
2427 adev->mode_info.bl_encoder);
2428 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
2429 bl_level);
2430 }
2431
2432 return ret;
2433}
2434
2435static bool dce_v6_0_is_idle(void *handle)
2436{
2437 return true;
2438}
2439
2440static int dce_v6_0_wait_for_idle(void *handle)
2441{
2442 return 0;
2443}
2444
2445static int dce_v6_0_soft_reset(void *handle)
2446{
2447 DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n");
2448 return 0;
2449}
2450
2451static void dce_v6_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
2452 int crtc,
2453 enum amdgpu_interrupt_state state)
2454{
2455 u32 reg_block, interrupt_mask;
2456
2457 if (crtc >= adev->mode_info.num_crtc) {
2458 DRM_DEBUG("invalid crtc %d\n", crtc);
2459 return;
2460 }
2461
2462 switch (crtc) {
2463 case 0:
2464 reg_block = SI_CRTC0_REGISTER_OFFSET;
2465 break;
2466 case 1:
2467 reg_block = SI_CRTC1_REGISTER_OFFSET;
2468 break;
2469 case 2:
2470 reg_block = SI_CRTC2_REGISTER_OFFSET;
2471 break;
2472 case 3:
2473 reg_block = SI_CRTC3_REGISTER_OFFSET;
2474 break;
2475 case 4:
2476 reg_block = SI_CRTC4_REGISTER_OFFSET;
2477 break;
2478 case 5:
2479 reg_block = SI_CRTC5_REGISTER_OFFSET;
2480 break;
2481 default:
2482 DRM_DEBUG("invalid crtc %d\n", crtc);
2483 return;
2484 }
2485
2486 switch (state) {
2487 case AMDGPU_IRQ_STATE_DISABLE:
2488 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2489 interrupt_mask &= ~VBLANK_INT_MASK;
2490 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2491 break;
2492 case AMDGPU_IRQ_STATE_ENABLE:
2493 interrupt_mask = RREG32(mmINT_MASK + reg_block);
2494 interrupt_mask |= VBLANK_INT_MASK;
2495 WREG32(mmINT_MASK + reg_block, interrupt_mask);
2496 break;
2497 default:
2498 break;
2499 }
2500}
2501
2502static void dce_v6_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
2503 int crtc,
2504 enum amdgpu_interrupt_state state)
2505{
2506
2507}
2508
2509static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
2510 struct amdgpu_irq_src *src,
2511 unsigned type,
2512 enum amdgpu_interrupt_state state)
2513{
2514 u32 dc_hpd_int_cntl;
2515
2516 if (type >= adev->mode_info.num_hpd) {
2517 DRM_DEBUG("invalid hdp %d\n", type);
2518 return 0;
2519 }
2520
2521 switch (state) {
2522 case AMDGPU_IRQ_STATE_DISABLE:
2523 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2524 dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
2525 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2526 break;
2527 case AMDGPU_IRQ_STATE_ENABLE:
2528 dc_hpd_int_cntl = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type]);
2529 dc_hpd_int_cntl |= DC_HPDx_INT_EN;
2530 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
2531 break;
2532 default:
2533 break;
2534 }
2535
2536 return 0;
2537}
2538
2539static int dce_v6_0_set_crtc_interrupt_state(struct amdgpu_device *adev,
2540 struct amdgpu_irq_src *src,
2541 unsigned type,
2542 enum amdgpu_interrupt_state state)
2543{
2544 switch (type) {
2545 case AMDGPU_CRTC_IRQ_VBLANK1:
2546 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 0, state);
2547 break;
2548 case AMDGPU_CRTC_IRQ_VBLANK2:
2549 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 1, state);
2550 break;
2551 case AMDGPU_CRTC_IRQ_VBLANK3:
2552 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 2, state);
2553 break;
2554 case AMDGPU_CRTC_IRQ_VBLANK4:
2555 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 3, state);
2556 break;
2557 case AMDGPU_CRTC_IRQ_VBLANK5:
2558 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 4, state);
2559 break;
2560 case AMDGPU_CRTC_IRQ_VBLANK6:
2561 dce_v6_0_set_crtc_vblank_interrupt_state(adev, 5, state);
2562 break;
2563 case AMDGPU_CRTC_IRQ_VLINE1:
2564 dce_v6_0_set_crtc_vline_interrupt_state(adev, 0, state);
2565 break;
2566 case AMDGPU_CRTC_IRQ_VLINE2:
2567 dce_v6_0_set_crtc_vline_interrupt_state(adev, 1, state);
2568 break;
2569 case AMDGPU_CRTC_IRQ_VLINE3:
2570 dce_v6_0_set_crtc_vline_interrupt_state(adev, 2, state);
2571 break;
2572 case AMDGPU_CRTC_IRQ_VLINE4:
2573 dce_v6_0_set_crtc_vline_interrupt_state(adev, 3, state);
2574 break;
2575 case AMDGPU_CRTC_IRQ_VLINE5:
2576 dce_v6_0_set_crtc_vline_interrupt_state(adev, 4, state);
2577 break;
2578 case AMDGPU_CRTC_IRQ_VLINE6:
2579 dce_v6_0_set_crtc_vline_interrupt_state(adev, 5, state);
2580 break;
2581 default:
2582 break;
2583 }
2584 return 0;
2585}
2586
2587static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
2588 struct amdgpu_irq_src *source,
2589 struct amdgpu_iv_entry *entry)
2590{
2591 unsigned crtc = entry->src_id - 1;
2592 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
2593 unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
2594
2595 switch (entry->src_data) {
2596 case 0: /* vblank */
2597 if (disp_int & interrupt_status_offsets[crtc].vblank)
2598 WREG32(mmVBLANK_STATUS + crtc_offsets[crtc], VBLANK_ACK);
2599 else
2600 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2601
2602 if (amdgpu_irq_enabled(adev, source, irq_type)) {
2603 drm_handle_vblank(adev->ddev, crtc);
2604 }
2605 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
2606 break;
2607 case 1: /* vline */
2608 if (disp_int & interrupt_status_offsets[crtc].vline)
2609 WREG32(mmVLINE_STATUS + crtc_offsets[crtc], VLINE_ACK);
2610 else
2611 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
2612
2613 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
2614 break;
2615 default:
2616 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
2617 break;
2618 }
2619
2620 return 0;
2621}
2622
2623static int dce_v6_0_set_pageflip_interrupt_state(struct amdgpu_device *adev,
2624 struct amdgpu_irq_src *src,
2625 unsigned type,
2626 enum amdgpu_interrupt_state state)
2627{
2628 u32 reg;
2629
2630 if (type >= adev->mode_info.num_crtc) {
2631 DRM_ERROR("invalid pageflip crtc %d\n", type);
2632 return -EINVAL;
2633 }
2634
2635 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
2636 if (state == AMDGPU_IRQ_STATE_DISABLE)
2637 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2638 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2639 else
2640 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
2641 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
2642
2643 return 0;
2644}
2645
2646static int dce_v6_0_pageflip_irq(struct amdgpu_device *adev,
2647 struct amdgpu_irq_src *source,
2648 struct amdgpu_iv_entry *entry)
2649{
2650 unsigned long flags;
2651 unsigned crtc_id;
2652 struct amdgpu_crtc *amdgpu_crtc;
2653 struct amdgpu_flip_work *works;
2654
2655 crtc_id = (entry->src_id - 8) >> 1;
2656 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
2657
2658 if (crtc_id >= adev->mode_info.num_crtc) {
2659 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
2660 return -EINVAL;
2661 }
2662
2663 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
2664 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
2665 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
2666 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
2667
2668 /* IRQ could occur when in initial stage */
2669 if (amdgpu_crtc == NULL)
2670 return 0;
2671
2672 spin_lock_irqsave(&adev->ddev->event_lock, flags);
2673 works = amdgpu_crtc->pflip_works;
2674 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
2675 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
2676 "AMDGPU_FLIP_SUBMITTED(%d)\n",
2677 amdgpu_crtc->pflip_status,
2678 AMDGPU_FLIP_SUBMITTED);
2679 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2680 return 0;
2681 }
2682
2683 /* page flip completed. clean up */
2684 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
2685 amdgpu_crtc->pflip_works = NULL;
2686
2687 /* wakeup usersapce */
2688 if (works->event)
2689 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
2690
2691 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
2692
2693 drm_crtc_vblank_put(&amdgpu_crtc->base);
2694 schedule_work(&works->unpin_work);
2695
2696 return 0;
2697}
2698
2699static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
2700 struct amdgpu_irq_src *source,
2701 struct amdgpu_iv_entry *entry)
2702{
2703 uint32_t disp_int, mask, tmp;
2704 unsigned hpd;
2705
2706 if (entry->src_data >= adev->mode_info.num_hpd) {
2707 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data);
2708 return 0;
2709 }
2710
2711 hpd = entry->src_data;
2712 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
2713 mask = interrupt_status_offsets[hpd].hpd;
2714
2715 if (disp_int & mask) {
2716 tmp = RREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
2717 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
2718 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
2719 schedule_work(&adev->hotplug_work);
2720 DRM_INFO("IH: HPD%d\n", hpd + 1);
2721 }
2722
2723 return 0;
2724
2725}
2726
2727static int dce_v6_0_set_clockgating_state(void *handle,
2728 enum amd_clockgating_state state)
2729{
2730 return 0;
2731}
2732
2733static int dce_v6_0_set_powergating_state(void *handle,
2734 enum amd_powergating_state state)
2735{
2736 return 0;
2737}
2738
2739static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
2740 .name = "dce_v6_0",
2741 .early_init = dce_v6_0_early_init,
2742 .late_init = NULL,
2743 .sw_init = dce_v6_0_sw_init,
2744 .sw_fini = dce_v6_0_sw_fini,
2745 .hw_init = dce_v6_0_hw_init,
2746 .hw_fini = dce_v6_0_hw_fini,
2747 .suspend = dce_v6_0_suspend,
2748 .resume = dce_v6_0_resume,
2749 .is_idle = dce_v6_0_is_idle,
2750 .wait_for_idle = dce_v6_0_wait_for_idle,
2751 .soft_reset = dce_v6_0_soft_reset,
2752 .set_clockgating_state = dce_v6_0_set_clockgating_state,
2753 .set_powergating_state = dce_v6_0_set_powergating_state,
2754};
2755
2756static void
2757dce_v6_0_encoder_mode_set(struct drm_encoder *encoder,
2758 struct drm_display_mode *mode,
2759 struct drm_display_mode *adjusted_mode)
2760{
2761
2762 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2763
2764 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
2765
2766 /* need to call this here rather than in prepare() since we need some crtc info */
2767 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2768
2769 /* set scaler clears this on some chips */
2770 dce_v6_0_set_interleave(encoder->crtc, mode);
2771
2772 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2773 dce_v6_0_afmt_enable(encoder, true);
2774 dce_v6_0_afmt_setmode(encoder, adjusted_mode);
2775 }
2776}
2777
2778static void dce_v6_0_encoder_prepare(struct drm_encoder *encoder)
2779{
2780
2781 struct amdgpu_device *adev = encoder->dev->dev_private;
2782 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2783 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
2784
2785 if ((amdgpu_encoder->active_device &
2786 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2787 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
2788 ENCODER_OBJECT_ID_NONE)) {
2789 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2790 if (dig) {
2791 dig->dig_encoder = dce_v6_0_pick_dig_encoder(encoder);
2792 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
2793 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
2794 }
2795 }
2796
2797 amdgpu_atombios_scratch_regs_lock(adev, true);
2798
2799 if (connector) {
2800 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
2801
2802 /* select the clock/data port if it uses a router */
2803 if (amdgpu_connector->router.cd_valid)
2804 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
2805
2806 /* turn eDP panel on for mode set */
2807 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2808 amdgpu_atombios_encoder_set_edp_panel_power(connector,
2809 ATOM_TRANSMITTER_ACTION_POWER_ON);
2810 }
2811
2812 /* this is needed for the pll/ss setup to work correctly in some cases */
2813 amdgpu_atombios_encoder_set_crtc_source(encoder);
2814 /* set up the FMT blocks */
2815 dce_v6_0_program_fmt(encoder);
2816}
2817
2818static void dce_v6_0_encoder_commit(struct drm_encoder *encoder)
2819{
2820
2821 struct drm_device *dev = encoder->dev;
2822 struct amdgpu_device *adev = dev->dev_private;
2823
2824 /* need to call this here as we need the crtc set up */
2825 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2826 amdgpu_atombios_scratch_regs_lock(adev, false);
2827}
2828
2829static void dce_v6_0_encoder_disable(struct drm_encoder *encoder)
2830{
2831
2832 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2833 struct amdgpu_encoder_atom_dig *dig;
2834
2835 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2836
2837 if (amdgpu_atombios_encoder_is_digital(encoder)) {
2838 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2839 dce_v6_0_afmt_enable(encoder, false);
2840 dig = amdgpu_encoder->enc_priv;
2841 dig->dig_encoder = -1;
2842 }
2843 amdgpu_encoder->active_device = 0;
2844}
2845
2846/* these are handled by the primary encoders */
2847static void dce_v6_0_ext_prepare(struct drm_encoder *encoder)
2848{
2849
2850}
2851
2852static void dce_v6_0_ext_commit(struct drm_encoder *encoder)
2853{
2854
2855}
2856
2857static void
2858dce_v6_0_ext_mode_set(struct drm_encoder *encoder,
2859 struct drm_display_mode *mode,
2860 struct drm_display_mode *adjusted_mode)
2861{
2862
2863}
2864
2865static void dce_v6_0_ext_disable(struct drm_encoder *encoder)
2866{
2867
2868}
2869
2870static void
2871dce_v6_0_ext_dpms(struct drm_encoder *encoder, int mode)
2872{
2873
2874}
2875
2876static bool dce_v6_0_ext_mode_fixup(struct drm_encoder *encoder,
2877 const struct drm_display_mode *mode,
2878 struct drm_display_mode *adjusted_mode)
2879{
2880 return true;
2881}
2882
2883static const struct drm_encoder_helper_funcs dce_v6_0_ext_helper_funcs = {
2884 .dpms = dce_v6_0_ext_dpms,
2885 .mode_fixup = dce_v6_0_ext_mode_fixup,
2886 .prepare = dce_v6_0_ext_prepare,
2887 .mode_set = dce_v6_0_ext_mode_set,
2888 .commit = dce_v6_0_ext_commit,
2889 .disable = dce_v6_0_ext_disable,
2890 /* no detect for TMDS/LVDS yet */
2891};
2892
2893static const struct drm_encoder_helper_funcs dce_v6_0_dig_helper_funcs = {
2894 .dpms = amdgpu_atombios_encoder_dpms,
2895 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2896 .prepare = dce_v6_0_encoder_prepare,
2897 .mode_set = dce_v6_0_encoder_mode_set,
2898 .commit = dce_v6_0_encoder_commit,
2899 .disable = dce_v6_0_encoder_disable,
2900 .detect = amdgpu_atombios_encoder_dig_detect,
2901};
2902
2903static const struct drm_encoder_helper_funcs dce_v6_0_dac_helper_funcs = {
2904 .dpms = amdgpu_atombios_encoder_dpms,
2905 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
2906 .prepare = dce_v6_0_encoder_prepare,
2907 .mode_set = dce_v6_0_encoder_mode_set,
2908 .commit = dce_v6_0_encoder_commit,
2909 .detect = amdgpu_atombios_encoder_dac_detect,
2910};
2911
2912static void dce_v6_0_encoder_destroy(struct drm_encoder *encoder)
2913{
2914 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2915 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2916 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
2917 kfree(amdgpu_encoder->enc_priv);
2918 drm_encoder_cleanup(encoder);
2919 kfree(amdgpu_encoder);
2920}
2921
2922static const struct drm_encoder_funcs dce_v6_0_encoder_funcs = {
2923 .destroy = dce_v6_0_encoder_destroy,
2924};
2925
2926static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
2927 uint32_t encoder_enum,
2928 uint32_t supported_device,
2929 u16 caps)
2930{
2931 struct drm_device *dev = adev->ddev;
2932 struct drm_encoder *encoder;
2933 struct amdgpu_encoder *amdgpu_encoder;
2934
2935 /* see if we already added it */
2936 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2937 amdgpu_encoder = to_amdgpu_encoder(encoder);
2938 if (amdgpu_encoder->encoder_enum == encoder_enum) {
2939 amdgpu_encoder->devices |= supported_device;
2940 return;
2941 }
2942
2943 }
2944
2945 /* add a new one */
2946 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
2947 if (!amdgpu_encoder)
2948 return;
2949
2950 encoder = &amdgpu_encoder->base;
2951 switch (adev->mode_info.num_crtc) {
2952 case 1:
2953 encoder->possible_crtcs = 0x1;
2954 break;
2955 case 2:
2956 default:
2957 encoder->possible_crtcs = 0x3;
2958 break;
2959 case 4:
2960 encoder->possible_crtcs = 0xf;
2961 break;
2962 case 6:
2963 encoder->possible_crtcs = 0x3f;
2964 break;
2965 }
2966
2967 amdgpu_encoder->enc_priv = NULL;
2968 amdgpu_encoder->encoder_enum = encoder_enum;
2969 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2970 amdgpu_encoder->devices = supported_device;
2971 amdgpu_encoder->rmx_type = RMX_OFF;
2972 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
2973 amdgpu_encoder->is_ext_encoder = false;
2974 amdgpu_encoder->caps = caps;
2975
2976 switch (amdgpu_encoder->encoder_id) {
2977 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2978 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2979 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2980 DRM_MODE_ENCODER_DAC, NULL);
2981 drm_encoder_helper_add(encoder, &dce_v6_0_dac_helper_funcs);
2982 break;
2983 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2984 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2985 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2986 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2987 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2988 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2989 amdgpu_encoder->rmx_type = RMX_FULL;
2990 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2991 DRM_MODE_ENCODER_LVDS, NULL);
2992 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
2993 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2994 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2995 DRM_MODE_ENCODER_DAC, NULL);
2996 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
2997 } else {
2998 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
2999 DRM_MODE_ENCODER_TMDS, NULL);
3000 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3001 }
3002 drm_encoder_helper_add(encoder, &dce_v6_0_dig_helper_funcs);
3003 break;
3004 case ENCODER_OBJECT_ID_SI170B:
3005 case ENCODER_OBJECT_ID_CH7303:
3006 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3007 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3008 case ENCODER_OBJECT_ID_TITFP513:
3009 case ENCODER_OBJECT_ID_VT1623:
3010 case ENCODER_OBJECT_ID_HDMI_SI1930:
3011 case ENCODER_OBJECT_ID_TRAVIS:
3012 case ENCODER_OBJECT_ID_NUTMEG:
3013 /* these are handled by the primary encoders */
3014 amdgpu_encoder->is_ext_encoder = true;
3015 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3016 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3017 DRM_MODE_ENCODER_LVDS, NULL);
3018 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3019 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3020 DRM_MODE_ENCODER_DAC, NULL);
3021 else
3022 drm_encoder_init(dev, encoder, &dce_v6_0_encoder_funcs,
3023 DRM_MODE_ENCODER_TMDS, NULL);
3024 drm_encoder_helper_add(encoder, &dce_v6_0_ext_helper_funcs);
3025 break;
3026 }
3027}
3028
3029static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
3030 .set_vga_render_state = &dce_v6_0_set_vga_render_state,
3031 .bandwidth_update = &dce_v6_0_bandwidth_update,
3032 .vblank_get_counter = &dce_v6_0_vblank_get_counter,
3033 .vblank_wait = &dce_v6_0_vblank_wait,
3034 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3035 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3036 .hpd_sense = &dce_v6_0_hpd_sense,
3037 .hpd_set_polarity = &dce_v6_0_hpd_set_polarity,
3038 .hpd_get_gpio_reg = &dce_v6_0_hpd_get_gpio_reg,
3039 .page_flip = &dce_v6_0_page_flip,
3040 .page_flip_get_scanoutpos = &dce_v6_0_crtc_get_scanoutpos,
3041 .add_encoder = &dce_v6_0_encoder_add,
3042 .add_connector = &amdgpu_connector_add,
3043 .stop_mc_access = &dce_v6_0_stop_mc_access,
3044 .resume_mc_access = &dce_v6_0_resume_mc_access,
3045};
3046
3047static void dce_v6_0_set_display_funcs(struct amdgpu_device *adev)
3048{
3049 if (adev->mode_info.funcs == NULL)
3050 adev->mode_info.funcs = &dce_v6_0_display_funcs;
3051}
3052
3053static const struct amdgpu_irq_src_funcs dce_v6_0_crtc_irq_funcs = {
3054 .set = dce_v6_0_set_crtc_interrupt_state,
3055 .process = dce_v6_0_crtc_irq,
3056};
3057
3058static const struct amdgpu_irq_src_funcs dce_v6_0_pageflip_irq_funcs = {
3059 .set = dce_v6_0_set_pageflip_interrupt_state,
3060 .process = dce_v6_0_pageflip_irq,
3061};
3062
3063static const struct amdgpu_irq_src_funcs dce_v6_0_hpd_irq_funcs = {
3064 .set = dce_v6_0_set_hpd_interrupt_state,
3065 .process = dce_v6_0_hpd_irq,
3066};
3067
3068static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3069{
3070 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_LAST;
3071 adev->crtc_irq.funcs = &dce_v6_0_crtc_irq_funcs;
3072
3073 adev->pageflip_irq.num_types = AMDGPU_PAGEFLIP_IRQ_LAST;
3074 adev->pageflip_irq.funcs = &dce_v6_0_pageflip_irq_funcs;
3075
3076 adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
3077 adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
3078}
3079
3080const struct amdgpu_ip_block_version dce_v6_0_ip_block =
3081{
3082 .type = AMD_IP_BLOCK_TYPE_DCE,
3083 .major = 6,
3084 .minor = 0,
3085 .rev = 0,
3086 .funcs = &dce_v6_0_ip_funcs,
3087};
3088
3089const struct amdgpu_ip_block_version dce_v6_4_ip_block =
3090{
3091 .type = AMD_IP_BLOCK_TYPE_DCE,
3092 .major = 6,
3093 .minor = 4,
3094 .rev = 0,
3095 .funcs = &dce_v6_0_ip_funcs,
3096};