1/*
  2 * Copyright 2021 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 */
 23
 24#ifndef __AMDGPU_RESET_H__
 25#define __AMDGPU_RESET_H__
 26
 27#include "amdgpu.h"
 28
 29#define AMDGPU_RESET_MAX_HANDLERS 5
 30
 31enum AMDGPU_RESET_FLAGS {
 32
 33	AMDGPU_NEED_FULL_RESET = 0,
 34	AMDGPU_SKIP_HW_RESET = 1,
 35	AMDGPU_SKIP_COREDUMP = 2,
 36	AMDGPU_HOST_FLR = 3,
 37};
 38
 39enum AMDGPU_RESET_SRCS {
 40	AMDGPU_RESET_SRC_UNKNOWN,
 41	AMDGPU_RESET_SRC_JOB,
 42	AMDGPU_RESET_SRC_RAS,
 43	AMDGPU_RESET_SRC_MES,
 44	AMDGPU_RESET_SRC_HWS,
 45	AMDGPU_RESET_SRC_USER,
 46};
 47
 48struct amdgpu_reset_context {
 49	enum amd_reset_method method;
 50	struct amdgpu_device *reset_req_dev;
 51	struct amdgpu_job *job;
 52	struct amdgpu_hive_info *hive;
 53	struct list_head *reset_device_list;
 54	unsigned long flags;
 55	enum AMDGPU_RESET_SRCS src;
 56};
 57
 58struct amdgpu_reset_handler {
 59	enum amd_reset_method reset_method;
 60	int (*prepare_env)(struct amdgpu_reset_control *reset_ctl,
 61			   struct amdgpu_reset_context *context);
 62	int (*prepare_hwcontext)(struct amdgpu_reset_control *reset_ctl,
 63				 struct amdgpu_reset_context *context);
 64	int (*perform_reset)(struct amdgpu_reset_control *reset_ctl,
 65			     struct amdgpu_reset_context *context);
 66	int (*restore_hwcontext)(struct amdgpu_reset_control *reset_ctl,
 67				 struct amdgpu_reset_context *context);
 68	int (*restore_env)(struct amdgpu_reset_control *reset_ctl,
 69			   struct amdgpu_reset_context *context);
 70
 71	int (*do_reset)(struct amdgpu_device *adev);
 72};
 73
 74struct amdgpu_reset_control {
 75	void *handle;
 76	struct work_struct reset_work;
 77	struct mutex reset_lock;
 78	struct amdgpu_reset_handler *(
 79		*reset_handlers)[AMDGPU_RESET_MAX_HANDLERS];
 80	atomic_t in_reset;
 81	enum amd_reset_method active_reset;
 82	struct amdgpu_reset_handler *(*get_reset_handler)(
 83		struct amdgpu_reset_control *reset_ctl,
 84		struct amdgpu_reset_context *context);
 85	void (*async_reset)(struct work_struct *work);
 86};
 87
 88
 89enum amdgpu_reset_domain_type {
 90	SINGLE_DEVICE,
 91	XGMI_HIVE
 92};
 93
 94struct amdgpu_reset_domain {
 95	struct kref refcount;
 96	struct workqueue_struct *wq;
 97	enum amdgpu_reset_domain_type type;
 98	struct rw_semaphore sem;
 99	atomic_t in_gpu_reset;
100	atomic_t reset_res;
101};
102
103int amdgpu_reset_init(struct amdgpu_device *adev);
104int amdgpu_reset_fini(struct amdgpu_device *adev);
105
106int amdgpu_reset_prepare_hwcontext(struct amdgpu_device *adev,
107				   struct amdgpu_reset_context *reset_context);
108
109int amdgpu_reset_perform_reset(struct amdgpu_device *adev,
110			       struct amdgpu_reset_context *reset_context);
111
112int amdgpu_reset_prepare_env(struct amdgpu_device *adev,
113			     struct amdgpu_reset_context *reset_context);
114int amdgpu_reset_restore_env(struct amdgpu_device *adev,
115			     struct amdgpu_reset_context *reset_context);
116
117struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type,
118							     char *wq_name);
119
120void amdgpu_reset_destroy_reset_domain(struct kref *ref);
121
122static inline bool amdgpu_reset_get_reset_domain(struct amdgpu_reset_domain *domain)
123{
124	return kref_get_unless_zero(&domain->refcount) != 0;
125}
126
127static inline void amdgpu_reset_put_reset_domain(struct amdgpu_reset_domain *domain)
128{
129	if (domain)
130		kref_put(&domain->refcount, amdgpu_reset_destroy_reset_domain);
131}
132
133static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *domain,
134						struct work_struct *work)
135{
136	return queue_work(domain->wq, work);
137}
138
139static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain)
140{
141	lockdep_assert_held(&domain->sem);
142	return rwsem_is_contended(&domain->sem);
143}
144
145void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain);
146
147void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain);
148
149void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf,
150			   size_t len);
151
152#define for_each_handler(i, handler, reset_ctl)                  \
153	for (i = 0; (i < AMDGPU_RESET_MAX_HANDLERS) &&           \
154		    (handler = (*reset_ctl->reset_handlers)[i]); \
155	     ++i)
156
157extern struct amdgpu_reset_handler xgmi_reset_on_init_handler;
158int amdgpu_reset_do_xgmi_reset_on_init(
159	struct amdgpu_reset_context *reset_context);
160
161bool amdgpu_reset_in_recovery(struct amdgpu_device *adev);
162
163#endif