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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * GHES/EDAC Linux driver
4 *
5 * Copyright (c) 2013 by Mauro Carvalho Chehab
6 *
7 * Red Hat Inc. https://www.redhat.com
8 */
9
10#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
11
12#include <acpi/ghes.h>
13#include <linux/edac.h>
14#include <linux/dmi.h>
15#include "edac_module.h"
16#include <ras/ras_event.h>
17#include <linux/notifier.h>
18
19#define OTHER_DETAIL_LEN 400
20
21struct ghes_pvt {
22 struct mem_ctl_info *mci;
23
24 /* Buffers for the error handling routine */
25 char other_detail[OTHER_DETAIL_LEN];
26 char msg[80];
27};
28
29static refcount_t ghes_refcount = REFCOUNT_INIT(0);
30
31/*
32 * Access to ghes_pvt must be protected by ghes_lock. The spinlock
33 * also provides the necessary (implicit) memory barrier for the SMP
34 * case to make the pointer visible on another CPU.
35 */
36static struct ghes_pvt *ghes_pvt;
37
38/*
39 * This driver's representation of the system hardware, as collected
40 * from DMI.
41 */
42static struct ghes_hw_desc {
43 int num_dimms;
44 struct dimm_info *dimms;
45} ghes_hw;
46
47/* GHES registration mutex */
48static DEFINE_MUTEX(ghes_reg_mutex);
49
50/*
51 * Sync with other, potentially concurrent callers of
52 * ghes_edac_report_mem_error(). We don't know what the
53 * "inventive" firmware would do.
54 */
55static DEFINE_SPINLOCK(ghes_lock);
56
57static bool system_scanned;
58
59static struct list_head *ghes_devs;
60
61/* Memory Device - Type 17 of SMBIOS spec */
62struct memdev_dmi_entry {
63 u8 type;
64 u8 length;
65 u16 handle;
66 u16 phys_mem_array_handle;
67 u16 mem_err_info_handle;
68 u16 total_width;
69 u16 data_width;
70 u16 size;
71 u8 form_factor;
72 u8 device_set;
73 u8 device_locator;
74 u8 bank_locator;
75 u8 memory_type;
76 u16 type_detail;
77 u16 speed;
78 u8 manufacturer;
79 u8 serial_number;
80 u8 asset_tag;
81 u8 part_number;
82 u8 attributes;
83 u32 extended_size;
84 u16 conf_mem_clk_speed;
85} __attribute__((__packed__));
86
87static struct dimm_info *find_dimm_by_handle(struct mem_ctl_info *mci, u16 handle)
88{
89 struct dimm_info *dimm;
90
91 mci_for_each_dimm(mci, dimm) {
92 if (dimm->smbios_handle == handle)
93 return dimm;
94 }
95
96 return NULL;
97}
98
99static void dimm_setup_label(struct dimm_info *dimm, u16 handle)
100{
101 const char *bank = NULL, *device = NULL;
102
103 dmi_memdev_name(handle, &bank, &device);
104
105 /*
106 * Set to a NULL string when both bank and device are zero. In this case,
107 * the label assigned by default will be preserved.
108 */
109 snprintf(dimm->label, sizeof(dimm->label), "%s%s%s",
110 (bank && *bank) ? bank : "",
111 (bank && *bank && device && *device) ? " " : "",
112 (device && *device) ? device : "");
113}
114
115static void assign_dmi_dimm_info(struct dimm_info *dimm, struct memdev_dmi_entry *entry)
116{
117 u16 rdr_mask = BIT(7) | BIT(13);
118
119 if (entry->size == 0xffff) {
120 pr_info("Can't get DIMM%i size\n", dimm->idx);
121 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
122 } else if (entry->size == 0x7fff) {
123 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
124 } else {
125 if (entry->size & BIT(15))
126 dimm->nr_pages = MiB_TO_PAGES((entry->size & 0x7fff) << 10);
127 else
128 dimm->nr_pages = MiB_TO_PAGES(entry->size);
129 }
130
131 switch (entry->memory_type) {
132 case 0x12:
133 if (entry->type_detail & BIT(13))
134 dimm->mtype = MEM_RDDR;
135 else
136 dimm->mtype = MEM_DDR;
137 break;
138 case 0x13:
139 if (entry->type_detail & BIT(13))
140 dimm->mtype = MEM_RDDR2;
141 else
142 dimm->mtype = MEM_DDR2;
143 break;
144 case 0x14:
145 dimm->mtype = MEM_FB_DDR2;
146 break;
147 case 0x18:
148 if (entry->type_detail & BIT(12))
149 dimm->mtype = MEM_NVDIMM;
150 else if (entry->type_detail & BIT(13))
151 dimm->mtype = MEM_RDDR3;
152 else
153 dimm->mtype = MEM_DDR3;
154 break;
155 case 0x1a:
156 if (entry->type_detail & BIT(12))
157 dimm->mtype = MEM_NVDIMM;
158 else if (entry->type_detail & BIT(13))
159 dimm->mtype = MEM_RDDR4;
160 else
161 dimm->mtype = MEM_DDR4;
162 break;
163 default:
164 if (entry->type_detail & BIT(6))
165 dimm->mtype = MEM_RMBS;
166 else if ((entry->type_detail & rdr_mask) == rdr_mask)
167 dimm->mtype = MEM_RDR;
168 else if (entry->type_detail & BIT(7))
169 dimm->mtype = MEM_SDR;
170 else if (entry->type_detail & BIT(9))
171 dimm->mtype = MEM_EDO;
172 else
173 dimm->mtype = MEM_UNKNOWN;
174 }
175
176 /*
177 * Actually, we can only detect if the memory has bits for
178 * checksum or not
179 */
180 if (entry->total_width == entry->data_width)
181 dimm->edac_mode = EDAC_NONE;
182 else
183 dimm->edac_mode = EDAC_SECDED;
184
185 dimm->dtype = DEV_UNKNOWN;
186 dimm->grain = 128; /* Likely, worse case */
187
188 dimm_setup_label(dimm, entry->handle);
189
190 if (dimm->nr_pages) {
191 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
192 dimm->idx, edac_mem_types[dimm->mtype],
193 PAGES_TO_MiB(dimm->nr_pages),
194 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
195 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
196 entry->memory_type, entry->type_detail,
197 entry->total_width, entry->data_width);
198 }
199
200 dimm->smbios_handle = entry->handle;
201}
202
203static void enumerate_dimms(const struct dmi_header *dh, void *arg)
204{
205 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
206 struct ghes_hw_desc *hw = (struct ghes_hw_desc *)arg;
207 struct dimm_info *d;
208
209 if (dh->type != DMI_ENTRY_MEM_DEVICE)
210 return;
211
212 /* Enlarge the array with additional 16 */
213 if (!hw->num_dimms || !(hw->num_dimms % 16)) {
214 struct dimm_info *new;
215
216 new = krealloc_array(hw->dimms, hw->num_dimms + 16,
217 sizeof(struct dimm_info), GFP_KERNEL);
218 if (!new) {
219 WARN_ON_ONCE(1);
220 return;
221 }
222
223 hw->dimms = new;
224 }
225
226 d = &hw->dimms[hw->num_dimms];
227 d->idx = hw->num_dimms;
228
229 assign_dmi_dimm_info(d, entry);
230
231 hw->num_dimms++;
232}
233
234static void ghes_scan_system(void)
235{
236 if (system_scanned)
237 return;
238
239 dmi_walk(enumerate_dimms, &ghes_hw);
240
241 system_scanned = true;
242}
243
244static int print_mem_error_other_detail(const struct cper_sec_mem_err *mem, char *msg,
245 const char *location, unsigned int len)
246{
247 u32 n;
248
249 if (!msg)
250 return 0;
251
252 n = 0;
253 len -= 1;
254
255 n += scnprintf(msg + n, len - n, "APEI location: %s ", location);
256
257 if (!(mem->validation_bits & CPER_MEM_VALID_ERROR_STATUS))
258 goto out;
259
260 n += scnprintf(msg + n, len - n, "status(0x%016llx): ", mem->error_status);
261 n += scnprintf(msg + n, len - n, "%s ", cper_mem_err_status_str(mem->error_status));
262
263out:
264 msg[n] = '\0';
265
266 return n;
267}
268
269static int ghes_edac_report_mem_error(struct notifier_block *nb,
270 unsigned long val, void *data)
271{
272 struct cper_sec_mem_err *mem_err = (struct cper_sec_mem_err *)data;
273 struct cper_mem_err_compact cmem;
274 struct edac_raw_error_desc *e;
275 struct mem_ctl_info *mci;
276 unsigned long sev = val;
277 struct ghes_pvt *pvt;
278 unsigned long flags;
279 char *p;
280
281 /*
282 * We can do the locking below because GHES defers error processing
283 * from NMI to IRQ context. Whenever that changes, we'd at least
284 * know.
285 */
286 if (WARN_ON_ONCE(in_nmi()))
287 return NOTIFY_OK;
288
289 spin_lock_irqsave(&ghes_lock, flags);
290
291 pvt = ghes_pvt;
292 if (!pvt)
293 goto unlock;
294
295 mci = pvt->mci;
296 e = &mci->error_desc;
297
298 /* Cleans the error report buffer */
299 memset(e, 0, sizeof (*e));
300 e->error_count = 1;
301 e->grain = 1;
302 e->msg = pvt->msg;
303 e->other_detail = pvt->other_detail;
304 e->top_layer = -1;
305 e->mid_layer = -1;
306 e->low_layer = -1;
307 *pvt->other_detail = '\0';
308 *pvt->msg = '\0';
309
310 switch (sev) {
311 case GHES_SEV_CORRECTED:
312 e->type = HW_EVENT_ERR_CORRECTED;
313 break;
314 case GHES_SEV_RECOVERABLE:
315 e->type = HW_EVENT_ERR_UNCORRECTED;
316 break;
317 case GHES_SEV_PANIC:
318 e->type = HW_EVENT_ERR_FATAL;
319 break;
320 default:
321 case GHES_SEV_NO:
322 e->type = HW_EVENT_ERR_INFO;
323 }
324
325 edac_dbg(1, "error validation_bits: 0x%08llx\n",
326 (long long)mem_err->validation_bits);
327
328 /* Error type, mapped on e->msg */
329 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
330 u8 etype = mem_err->error_type;
331
332 p = pvt->msg;
333 p += snprintf(p, sizeof(pvt->msg), "%s", cper_mem_err_type_str(etype));
334 } else {
335 strcpy(pvt->msg, "unknown error");
336 }
337
338 /* Error address */
339 if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
340 e->page_frame_number = PHYS_PFN(mem_err->physical_addr);
341 e->offset_in_page = offset_in_page(mem_err->physical_addr);
342 }
343
344 /* Error grain */
345 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
346 e->grain = ~mem_err->physical_addr_mask + 1;
347
348 /* Memory error location, mapped on e->location */
349 p = e->location;
350 cper_mem_err_pack(mem_err, &cmem);
351 p += cper_mem_err_location(&cmem, p);
352
353 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
354 struct dimm_info *dimm;
355
356 p += cper_dimm_err_location(&cmem, p);
357 dimm = find_dimm_by_handle(mci, mem_err->mem_dev_handle);
358 if (dimm) {
359 e->top_layer = dimm->idx;
360 strcpy(e->label, dimm->label);
361 }
362 }
363 if (p > e->location)
364 *(p - 1) = '\0';
365
366 if (!*e->label)
367 strcpy(e->label, "unknown memory");
368
369 /* All other fields are mapped on e->other_detail */
370 p = pvt->other_detail;
371 p += print_mem_error_other_detail(mem_err, p, e->location, OTHER_DETAIL_LEN);
372 if (p > pvt->other_detail)
373 *(p - 1) = '\0';
374
375 edac_raw_mc_handle_error(e);
376
377unlock:
378 spin_unlock_irqrestore(&ghes_lock, flags);
379
380 return NOTIFY_OK;
381}
382
383static struct notifier_block ghes_edac_mem_err_nb = {
384 .notifier_call = ghes_edac_report_mem_error,
385 .priority = 0,
386};
387
388static int ghes_edac_register(struct device *dev)
389{
390 bool fake = false;
391 struct mem_ctl_info *mci;
392 struct ghes_pvt *pvt;
393 struct edac_mc_layer layers[1];
394 unsigned long flags;
395 int rc = 0;
396
397 /* finish another registration/unregistration instance first */
398 mutex_lock(&ghes_reg_mutex);
399
400 /*
401 * We have only one logical memory controller to which all DIMMs belong.
402 */
403 if (refcount_inc_not_zero(&ghes_refcount))
404 goto unlock;
405
406 ghes_scan_system();
407
408 /* Check if we've got a bogus BIOS */
409 if (!ghes_hw.num_dimms) {
410 fake = true;
411 ghes_hw.num_dimms = 1;
412 }
413
414 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
415 layers[0].size = ghes_hw.num_dimms;
416 layers[0].is_virt_csrow = true;
417
418 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(struct ghes_pvt));
419 if (!mci) {
420 pr_info("Can't allocate memory for EDAC data\n");
421 rc = -ENOMEM;
422 goto unlock;
423 }
424
425 pvt = mci->pvt_info;
426 pvt->mci = mci;
427
428 mci->pdev = dev;
429 mci->mtype_cap = MEM_FLAG_EMPTY;
430 mci->edac_ctl_cap = EDAC_FLAG_NONE;
431 mci->edac_cap = EDAC_FLAG_NONE;
432 mci->mod_name = "ghes_edac.c";
433 mci->ctl_name = "ghes_edac";
434 mci->dev_name = "ghes";
435
436 if (fake) {
437 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
438 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
439 pr_info("work on such system. Use this driver with caution\n");
440 }
441
442 pr_info("This system has %d DIMM sockets.\n", ghes_hw.num_dimms);
443
444 if (!fake) {
445 struct dimm_info *src, *dst;
446 int i = 0;
447
448 mci_for_each_dimm(mci, dst) {
449 src = &ghes_hw.dimms[i];
450
451 dst->idx = src->idx;
452 dst->smbios_handle = src->smbios_handle;
453 dst->nr_pages = src->nr_pages;
454 dst->mtype = src->mtype;
455 dst->edac_mode = src->edac_mode;
456 dst->dtype = src->dtype;
457 dst->grain = src->grain;
458
459 /*
460 * If no src->label, preserve default label assigned
461 * from EDAC core.
462 */
463 if (strlen(src->label))
464 memcpy(dst->label, src->label, sizeof(src->label));
465
466 i++;
467 }
468
469 } else {
470 struct dimm_info *dimm = edac_get_dimm(mci, 0, 0, 0);
471
472 dimm->nr_pages = 1;
473 dimm->grain = 128;
474 dimm->mtype = MEM_UNKNOWN;
475 dimm->dtype = DEV_UNKNOWN;
476 dimm->edac_mode = EDAC_SECDED;
477 }
478
479 rc = edac_mc_add_mc(mci);
480 if (rc < 0) {
481 pr_info("Can't register with the EDAC core\n");
482 edac_mc_free(mci);
483 rc = -ENODEV;
484 goto unlock;
485 }
486
487 spin_lock_irqsave(&ghes_lock, flags);
488 ghes_pvt = pvt;
489 spin_unlock_irqrestore(&ghes_lock, flags);
490
491 ghes_register_report_chain(&ghes_edac_mem_err_nb);
492
493 /* only set on success */
494 refcount_set(&ghes_refcount, 1);
495
496unlock:
497
498 /* Not needed anymore */
499 kfree(ghes_hw.dimms);
500 ghes_hw.dimms = NULL;
501
502 mutex_unlock(&ghes_reg_mutex);
503
504 return rc;
505}
506
507static void ghes_edac_unregister(struct ghes *ghes)
508{
509 struct mem_ctl_info *mci;
510 unsigned long flags;
511
512 mutex_lock(&ghes_reg_mutex);
513
514 system_scanned = false;
515 memset(&ghes_hw, 0, sizeof(struct ghes_hw_desc));
516
517 if (!refcount_dec_and_test(&ghes_refcount))
518 goto unlock;
519
520 /*
521 * Wait for the irq handler being finished.
522 */
523 spin_lock_irqsave(&ghes_lock, flags);
524 mci = ghes_pvt ? ghes_pvt->mci : NULL;
525 ghes_pvt = NULL;
526 spin_unlock_irqrestore(&ghes_lock, flags);
527
528 if (!mci)
529 goto unlock;
530
531 mci = edac_mc_del_mc(mci->pdev);
532 if (mci)
533 edac_mc_free(mci);
534
535 ghes_unregister_report_chain(&ghes_edac_mem_err_nb);
536
537unlock:
538 mutex_unlock(&ghes_reg_mutex);
539}
540
541static int __init ghes_edac_init(void)
542{
543 struct ghes *g, *g_tmp;
544
545 ghes_devs = ghes_get_devices();
546 if (!ghes_devs)
547 return -ENODEV;
548
549 if (list_empty(ghes_devs)) {
550 pr_info("GHES probing device list is empty\n");
551 return -ENODEV;
552 }
553
554 list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
555 ghes_edac_register(g->dev);
556 }
557
558 return 0;
559}
560module_init(ghes_edac_init);
561
562static void __exit ghes_edac_exit(void)
563{
564 struct ghes *g, *g_tmp;
565
566 list_for_each_entry_safe(g, g_tmp, ghes_devs, elist) {
567 ghes_edac_unregister(g);
568 }
569}
570module_exit(ghes_edac_exit);
571
572MODULE_LICENSE("GPL");
573MODULE_DESCRIPTION("Output ACPI APEI/GHES BIOS detected errors via EDAC");
1/*
2 * GHES/EDAC Linux driver
3 *
4 * This file may be distributed under the terms of the GNU General Public
5 * License version 2.
6 *
7 * Copyright (c) 2013 by Mauro Carvalho Chehab
8 *
9 * Red Hat Inc. http://www.redhat.com
10 */
11
12#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
13
14#include <acpi/ghes.h>
15#include <linux/edac.h>
16#include <linux/dmi.h>
17#include "edac_module.h"
18#include <ras/ras_event.h>
19
20#define GHES_EDAC_REVISION " Ver: 1.0.0"
21
22struct ghes_edac_pvt {
23 struct list_head list;
24 struct ghes *ghes;
25 struct mem_ctl_info *mci;
26
27 /* Buffers for the error handling routine */
28 char detail_location[240];
29 char other_detail[160];
30 char msg[80];
31};
32
33static LIST_HEAD(ghes_reglist);
34static DEFINE_MUTEX(ghes_edac_lock);
35static int ghes_edac_mc_num;
36
37
38/* Memory Device - Type 17 of SMBIOS spec */
39struct memdev_dmi_entry {
40 u8 type;
41 u8 length;
42 u16 handle;
43 u16 phys_mem_array_handle;
44 u16 mem_err_info_handle;
45 u16 total_width;
46 u16 data_width;
47 u16 size;
48 u8 form_factor;
49 u8 device_set;
50 u8 device_locator;
51 u8 bank_locator;
52 u8 memory_type;
53 u16 type_detail;
54 u16 speed;
55 u8 manufacturer;
56 u8 serial_number;
57 u8 asset_tag;
58 u8 part_number;
59 u8 attributes;
60 u32 extended_size;
61 u16 conf_mem_clk_speed;
62} __attribute__((__packed__));
63
64struct ghes_edac_dimm_fill {
65 struct mem_ctl_info *mci;
66 unsigned count;
67};
68
69static void ghes_edac_count_dimms(const struct dmi_header *dh, void *arg)
70{
71 int *num_dimm = arg;
72
73 if (dh->type == DMI_ENTRY_MEM_DEVICE)
74 (*num_dimm)++;
75}
76
77static void ghes_edac_dmidecode(const struct dmi_header *dh, void *arg)
78{
79 struct ghes_edac_dimm_fill *dimm_fill = arg;
80 struct mem_ctl_info *mci = dimm_fill->mci;
81
82 if (dh->type == DMI_ENTRY_MEM_DEVICE) {
83 struct memdev_dmi_entry *entry = (struct memdev_dmi_entry *)dh;
84 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
85 mci->n_layers,
86 dimm_fill->count, 0, 0);
87
88 if (entry->size == 0xffff) {
89 pr_info("Can't get DIMM%i size\n",
90 dimm_fill->count);
91 dimm->nr_pages = MiB_TO_PAGES(32);/* Unknown */
92 } else if (entry->size == 0x7fff) {
93 dimm->nr_pages = MiB_TO_PAGES(entry->extended_size);
94 } else {
95 if (entry->size & 1 << 15)
96 dimm->nr_pages = MiB_TO_PAGES((entry->size &
97 0x7fff) << 10);
98 else
99 dimm->nr_pages = MiB_TO_PAGES(entry->size);
100 }
101
102 switch (entry->memory_type) {
103 case 0x12:
104 if (entry->type_detail & 1 << 13)
105 dimm->mtype = MEM_RDDR;
106 else
107 dimm->mtype = MEM_DDR;
108 break;
109 case 0x13:
110 if (entry->type_detail & 1 << 13)
111 dimm->mtype = MEM_RDDR2;
112 else
113 dimm->mtype = MEM_DDR2;
114 break;
115 case 0x14:
116 dimm->mtype = MEM_FB_DDR2;
117 break;
118 case 0x18:
119 if (entry->type_detail & 1 << 13)
120 dimm->mtype = MEM_RDDR3;
121 else
122 dimm->mtype = MEM_DDR3;
123 break;
124 default:
125 if (entry->type_detail & 1 << 6)
126 dimm->mtype = MEM_RMBS;
127 else if ((entry->type_detail & ((1 << 7) | (1 << 13)))
128 == ((1 << 7) | (1 << 13)))
129 dimm->mtype = MEM_RDR;
130 else if (entry->type_detail & 1 << 7)
131 dimm->mtype = MEM_SDR;
132 else if (entry->type_detail & 1 << 9)
133 dimm->mtype = MEM_EDO;
134 else
135 dimm->mtype = MEM_UNKNOWN;
136 }
137
138 /*
139 * Actually, we can only detect if the memory has bits for
140 * checksum or not
141 */
142 if (entry->total_width == entry->data_width)
143 dimm->edac_mode = EDAC_NONE;
144 else
145 dimm->edac_mode = EDAC_SECDED;
146
147 dimm->dtype = DEV_UNKNOWN;
148 dimm->grain = 128; /* Likely, worse case */
149
150 /*
151 * FIXME: It shouldn't be hard to also fill the DIMM labels
152 */
153
154 if (dimm->nr_pages) {
155 edac_dbg(1, "DIMM%i: %s size = %d MB%s\n",
156 dimm_fill->count, edac_mem_types[dimm->mtype],
157 PAGES_TO_MiB(dimm->nr_pages),
158 (dimm->edac_mode != EDAC_NONE) ? "(ECC)" : "");
159 edac_dbg(2, "\ttype %d, detail 0x%02x, width %d(total %d)\n",
160 entry->memory_type, entry->type_detail,
161 entry->total_width, entry->data_width);
162 }
163
164 dimm_fill->count++;
165 }
166}
167
168void ghes_edac_report_mem_error(struct ghes *ghes, int sev,
169 struct cper_sec_mem_err *mem_err)
170{
171 enum hw_event_mc_err_type type;
172 struct edac_raw_error_desc *e;
173 struct mem_ctl_info *mci;
174 struct ghes_edac_pvt *pvt = NULL;
175 char *p;
176 u8 grain_bits;
177
178 list_for_each_entry(pvt, &ghes_reglist, list) {
179 if (ghes == pvt->ghes)
180 break;
181 }
182 if (!pvt) {
183 pr_err("Internal error: Can't find EDAC structure\n");
184 return;
185 }
186 mci = pvt->mci;
187 e = &mci->error_desc;
188
189 /* Cleans the error report buffer */
190 memset(e, 0, sizeof (*e));
191 e->error_count = 1;
192 strcpy(e->label, "unknown label");
193 e->msg = pvt->msg;
194 e->other_detail = pvt->other_detail;
195 e->top_layer = -1;
196 e->mid_layer = -1;
197 e->low_layer = -1;
198 *pvt->other_detail = '\0';
199 *pvt->msg = '\0';
200
201 switch (sev) {
202 case GHES_SEV_CORRECTED:
203 type = HW_EVENT_ERR_CORRECTED;
204 break;
205 case GHES_SEV_RECOVERABLE:
206 type = HW_EVENT_ERR_UNCORRECTED;
207 break;
208 case GHES_SEV_PANIC:
209 type = HW_EVENT_ERR_FATAL;
210 break;
211 default:
212 case GHES_SEV_NO:
213 type = HW_EVENT_ERR_INFO;
214 }
215
216 edac_dbg(1, "error validation_bits: 0x%08llx\n",
217 (long long)mem_err->validation_bits);
218
219 /* Error type, mapped on e->msg */
220 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_TYPE) {
221 p = pvt->msg;
222 switch (mem_err->error_type) {
223 case 0:
224 p += sprintf(p, "Unknown");
225 break;
226 case 1:
227 p += sprintf(p, "No error");
228 break;
229 case 2:
230 p += sprintf(p, "Single-bit ECC");
231 break;
232 case 3:
233 p += sprintf(p, "Multi-bit ECC");
234 break;
235 case 4:
236 p += sprintf(p, "Single-symbol ChipKill ECC");
237 break;
238 case 5:
239 p += sprintf(p, "Multi-symbol ChipKill ECC");
240 break;
241 case 6:
242 p += sprintf(p, "Master abort");
243 break;
244 case 7:
245 p += sprintf(p, "Target abort");
246 break;
247 case 8:
248 p += sprintf(p, "Parity Error");
249 break;
250 case 9:
251 p += sprintf(p, "Watchdog timeout");
252 break;
253 case 10:
254 p += sprintf(p, "Invalid address");
255 break;
256 case 11:
257 p += sprintf(p, "Mirror Broken");
258 break;
259 case 12:
260 p += sprintf(p, "Memory Sparing");
261 break;
262 case 13:
263 p += sprintf(p, "Scrub corrected error");
264 break;
265 case 14:
266 p += sprintf(p, "Scrub uncorrected error");
267 break;
268 case 15:
269 p += sprintf(p, "Physical Memory Map-out event");
270 break;
271 default:
272 p += sprintf(p, "reserved error (%d)",
273 mem_err->error_type);
274 }
275 } else {
276 strcpy(pvt->msg, "unknown error");
277 }
278
279 /* Error address */
280 if (mem_err->validation_bits & CPER_MEM_VALID_PA) {
281 e->page_frame_number = mem_err->physical_addr >> PAGE_SHIFT;
282 e->offset_in_page = mem_err->physical_addr & ~PAGE_MASK;
283 }
284
285 /* Error grain */
286 if (mem_err->validation_bits & CPER_MEM_VALID_PA_MASK)
287 e->grain = ~(mem_err->physical_addr_mask & ~PAGE_MASK);
288
289 /* Memory error location, mapped on e->location */
290 p = e->location;
291 if (mem_err->validation_bits & CPER_MEM_VALID_NODE)
292 p += sprintf(p, "node:%d ", mem_err->node);
293 if (mem_err->validation_bits & CPER_MEM_VALID_CARD)
294 p += sprintf(p, "card:%d ", mem_err->card);
295 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE)
296 p += sprintf(p, "module:%d ", mem_err->module);
297 if (mem_err->validation_bits & CPER_MEM_VALID_RANK_NUMBER)
298 p += sprintf(p, "rank:%d ", mem_err->rank);
299 if (mem_err->validation_bits & CPER_MEM_VALID_BANK)
300 p += sprintf(p, "bank:%d ", mem_err->bank);
301 if (mem_err->validation_bits & CPER_MEM_VALID_ROW)
302 p += sprintf(p, "row:%d ", mem_err->row);
303 if (mem_err->validation_bits & CPER_MEM_VALID_COLUMN)
304 p += sprintf(p, "col:%d ", mem_err->column);
305 if (mem_err->validation_bits & CPER_MEM_VALID_BIT_POSITION)
306 p += sprintf(p, "bit_pos:%d ", mem_err->bit_pos);
307 if (mem_err->validation_bits & CPER_MEM_VALID_MODULE_HANDLE) {
308 const char *bank = NULL, *device = NULL;
309 dmi_memdev_name(mem_err->mem_dev_handle, &bank, &device);
310 if (bank != NULL && device != NULL)
311 p += sprintf(p, "DIMM location:%s %s ", bank, device);
312 else
313 p += sprintf(p, "DIMM DMI handle: 0x%.4x ",
314 mem_err->mem_dev_handle);
315 }
316 if (p > e->location)
317 *(p - 1) = '\0';
318
319 /* All other fields are mapped on e->other_detail */
320 p = pvt->other_detail;
321 if (mem_err->validation_bits & CPER_MEM_VALID_ERROR_STATUS) {
322 u64 status = mem_err->error_status;
323
324 p += sprintf(p, "status(0x%016llx): ", (long long)status);
325 switch ((status >> 8) & 0xff) {
326 case 1:
327 p += sprintf(p, "Error detected internal to the component ");
328 break;
329 case 16:
330 p += sprintf(p, "Error detected in the bus ");
331 break;
332 case 4:
333 p += sprintf(p, "Storage error in DRAM memory ");
334 break;
335 case 5:
336 p += sprintf(p, "Storage error in TLB ");
337 break;
338 case 6:
339 p += sprintf(p, "Storage error in cache ");
340 break;
341 case 7:
342 p += sprintf(p, "Error in one or more functional units ");
343 break;
344 case 8:
345 p += sprintf(p, "component failed self test ");
346 break;
347 case 9:
348 p += sprintf(p, "Overflow or undervalue of internal queue ");
349 break;
350 case 17:
351 p += sprintf(p, "Virtual address not found on IO-TLB or IO-PDIR ");
352 break;
353 case 18:
354 p += sprintf(p, "Improper access error ");
355 break;
356 case 19:
357 p += sprintf(p, "Access to a memory address which is not mapped to any component ");
358 break;
359 case 20:
360 p += sprintf(p, "Loss of Lockstep ");
361 break;
362 case 21:
363 p += sprintf(p, "Response not associated with a request ");
364 break;
365 case 22:
366 p += sprintf(p, "Bus parity error - must also set the A, C, or D Bits ");
367 break;
368 case 23:
369 p += sprintf(p, "Detection of a PATH_ERROR ");
370 break;
371 case 25:
372 p += sprintf(p, "Bus operation timeout ");
373 break;
374 case 26:
375 p += sprintf(p, "A read was issued to data that has been poisoned ");
376 break;
377 default:
378 p += sprintf(p, "reserved ");
379 break;
380 }
381 }
382 if (mem_err->validation_bits & CPER_MEM_VALID_REQUESTOR_ID)
383 p += sprintf(p, "requestorID: 0x%016llx ",
384 (long long)mem_err->requestor_id);
385 if (mem_err->validation_bits & CPER_MEM_VALID_RESPONDER_ID)
386 p += sprintf(p, "responderID: 0x%016llx ",
387 (long long)mem_err->responder_id);
388 if (mem_err->validation_bits & CPER_MEM_VALID_TARGET_ID)
389 p += sprintf(p, "targetID: 0x%016llx ",
390 (long long)mem_err->responder_id);
391 if (p > pvt->other_detail)
392 *(p - 1) = '\0';
393
394 /* Generate the trace event */
395 grain_bits = fls_long(e->grain);
396 snprintf(pvt->detail_location, sizeof(pvt->detail_location),
397 "APEI location: %s %s", e->location, e->other_detail);
398 trace_mc_event(type, e->msg, e->label, e->error_count,
399 mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
400 (e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
401 grain_bits, e->syndrome, pvt->detail_location);
402
403 /* Report the error via EDAC API */
404 edac_raw_mc_handle_error(type, mci, e);
405}
406EXPORT_SYMBOL_GPL(ghes_edac_report_mem_error);
407
408int ghes_edac_register(struct ghes *ghes, struct device *dev)
409{
410 bool fake = false;
411 int rc, num_dimm = 0;
412 struct mem_ctl_info *mci;
413 struct edac_mc_layer layers[1];
414 struct ghes_edac_pvt *pvt;
415 struct ghes_edac_dimm_fill dimm_fill;
416
417 /* Get the number of DIMMs */
418 dmi_walk(ghes_edac_count_dimms, &num_dimm);
419
420 /* Check if we've got a bogus BIOS */
421 if (num_dimm == 0) {
422 fake = true;
423 num_dimm = 1;
424 }
425
426 layers[0].type = EDAC_MC_LAYER_ALL_MEM;
427 layers[0].size = num_dimm;
428 layers[0].is_virt_csrow = true;
429
430 /*
431 * We need to serialize edac_mc_alloc() and edac_mc_add_mc(),
432 * to avoid duplicated memory controller numbers
433 */
434 mutex_lock(&ghes_edac_lock);
435 mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers,
436 sizeof(*pvt));
437 if (!mci) {
438 pr_info("Can't allocate memory for EDAC data\n");
439 mutex_unlock(&ghes_edac_lock);
440 return -ENOMEM;
441 }
442
443 pvt = mci->pvt_info;
444 memset(pvt, 0, sizeof(*pvt));
445 list_add_tail(&pvt->list, &ghes_reglist);
446 pvt->ghes = ghes;
447 pvt->mci = mci;
448 mci->pdev = dev;
449
450 mci->mtype_cap = MEM_FLAG_EMPTY;
451 mci->edac_ctl_cap = EDAC_FLAG_NONE;
452 mci->edac_cap = EDAC_FLAG_NONE;
453 mci->mod_name = "ghes_edac.c";
454 mci->mod_ver = GHES_EDAC_REVISION;
455 mci->ctl_name = "ghes_edac";
456 mci->dev_name = "ghes";
457
458 if (!ghes_edac_mc_num) {
459 if (!fake) {
460 pr_info("This EDAC driver relies on BIOS to enumerate memory and get error reports.\n");
461 pr_info("Unfortunately, not all BIOSes reflect the memory layout correctly.\n");
462 pr_info("So, the end result of using this driver varies from vendor to vendor.\n");
463 pr_info("If you find incorrect reports, please contact your hardware vendor\n");
464 pr_info("to correct its BIOS.\n");
465 pr_info("This system has %d DIMM sockets.\n",
466 num_dimm);
467 } else {
468 pr_info("This system has a very crappy BIOS: It doesn't even list the DIMMS.\n");
469 pr_info("Its SMBIOS info is wrong. It is doubtful that the error report would\n");
470 pr_info("work on such system. Use this driver with caution\n");
471 }
472 }
473
474 if (!fake) {
475 /*
476 * Fill DIMM info from DMI for the memory controller #0
477 *
478 * Keep it in blank for the other memory controllers, as
479 * there's no reliable way to properly credit each DIMM to
480 * the memory controller, as different BIOSes fill the
481 * DMI bank location fields on different ways
482 */
483 if (!ghes_edac_mc_num) {
484 dimm_fill.count = 0;
485 dimm_fill.mci = mci;
486 dmi_walk(ghes_edac_dmidecode, &dimm_fill);
487 }
488 } else {
489 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
490 mci->n_layers, 0, 0, 0);
491
492 dimm->nr_pages = 1;
493 dimm->grain = 128;
494 dimm->mtype = MEM_UNKNOWN;
495 dimm->dtype = DEV_UNKNOWN;
496 dimm->edac_mode = EDAC_SECDED;
497 }
498
499 rc = edac_mc_add_mc(mci);
500 if (rc < 0) {
501 pr_info("Can't register at EDAC core\n");
502 edac_mc_free(mci);
503 mutex_unlock(&ghes_edac_lock);
504 return -ENODEV;
505 }
506
507 ghes_edac_mc_num++;
508 mutex_unlock(&ghes_edac_lock);
509 return 0;
510}
511EXPORT_SYMBOL_GPL(ghes_edac_register);
512
513void ghes_edac_unregister(struct ghes *ghes)
514{
515 struct mem_ctl_info *mci;
516 struct ghes_edac_pvt *pvt, *tmp;
517
518 list_for_each_entry_safe(pvt, tmp, &ghes_reglist, list) {
519 if (ghes == pvt->ghes) {
520 mci = pvt->mci;
521 edac_mc_del_mc(mci->pdev);
522 edac_mc_free(mci);
523 list_del(&pvt->list);
524 }
525 }
526}
527EXPORT_SYMBOL_GPL(ghes_edac_unregister);